1/****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD$*/ 34 35#include "ixgbe_api.h" 36#include "ixgbe_common.h" 37#include "ixgbe_phy.h" 38 39static void ixgbe_i2c_start(struct ixgbe_hw *hw); 40static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49static bool ixgbe_get_i2c_data(u32 *i2cctl); 50static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 51 u8 *sff8472_data); 52 53/** 54 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 55 * @hw: pointer to the hardware structure 56 * 57 * Initialize the function pointers. 58 **/ 59s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 60{ 61 struct ixgbe_phy_info *phy = &hw->phy; 62 63 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 64 65 /* PHY */ 66 phy->ops.identify = &ixgbe_identify_phy_generic; 67 phy->ops.reset = &ixgbe_reset_phy_generic; 68 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 69 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 70 phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi; 71 phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi; 72 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 73 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 74 phy->ops.check_link = NULL; 75 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 76 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 77 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 78 phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic; 79 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 80 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 81 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 82 phy->ops.identify_sfp = &ixgbe_identify_module_generic; 83 phy->sfp_type = ixgbe_sfp_type_unknown; 84 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp; 85 return IXGBE_SUCCESS; 86} 87 88/** 89 * ixgbe_identify_phy_generic - Get physical layer module 90 * @hw: pointer to hardware structure 91 * 92 * Determines the physical layer module found on the current adapter. 93 **/ 94s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 95{ 96 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 97 u32 phy_addr; 98 u16 ext_ability = 0; 99 100 DEBUGFUNC("ixgbe_identify_phy_generic"); 101 102 if (hw->phy.type == ixgbe_phy_unknown) { 103 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 104 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 105 hw->phy.addr = phy_addr; 106 ixgbe_get_phy_id(hw); 107 hw->phy.type = 108 ixgbe_get_phy_type_from_id(hw->phy.id); 109 110 if (hw->phy.type == ixgbe_phy_unknown) { 111 hw->phy.ops.read_reg(hw, 112 IXGBE_MDIO_PHY_EXT_ABILITY, 113 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 114 &ext_ability); 115 if (ext_ability & 116 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 117 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 118 hw->phy.type = 119 ixgbe_phy_cu_unknown; 120 else 121 hw->phy.type = 122 ixgbe_phy_generic; 123 } 124 125 status = IXGBE_SUCCESS; 126 break; 127 } 128 } 129 /* clear value if nothing found */ 130 if (status != IXGBE_SUCCESS) { 131 hw->phy.addr = 0; 132 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 133 "Could not identify valid PHY address"); 134 } 135 } else { 136 status = IXGBE_SUCCESS; 137 } 138 139 return status; 140} 141 142/** 143 * ixgbe_validate_phy_addr - Determines phy address is valid 144 * @hw: pointer to hardware structure 145 * 146 **/ 147bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 148{ 149 u16 phy_id = 0; 150 bool valid = FALSE; 151 152 DEBUGFUNC("ixgbe_validate_phy_addr"); 153 154 hw->phy.addr = phy_addr; 155 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 156 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 157 158 if (phy_id != 0xFFFF && phy_id != 0x0) 159 valid = TRUE; 160 161 return valid; 162} 163 164/** 165 * ixgbe_get_phy_id - Get the phy type 166 * @hw: pointer to hardware structure 167 * 168 **/ 169s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 170{ 171 u32 status; 172 u16 phy_id_high = 0; 173 u16 phy_id_low = 0; 174 175 DEBUGFUNC("ixgbe_get_phy_id"); 176 177 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 178 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 179 &phy_id_high); 180 181 if (status == IXGBE_SUCCESS) { 182 hw->phy.id = (u32)(phy_id_high << 16); 183 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 184 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 185 &phy_id_low); 186 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 187 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 188 } 189 return status; 190} 191 192/** 193 * ixgbe_get_phy_type_from_id - Get the phy type 194 * @hw: pointer to hardware structure 195 * 196 **/ 197enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 198{ 199 enum ixgbe_phy_type phy_type; 200 201 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 202 203 switch (phy_id) { 204 case TN1010_PHY_ID: 205 phy_type = ixgbe_phy_tn; 206 break; 207 case X540_PHY_ID: 208 phy_type = ixgbe_phy_aq; 209 break; 210 case QT2022_PHY_ID: 211 phy_type = ixgbe_phy_qt; 212 break; 213 case ATH_PHY_ID: 214 phy_type = ixgbe_phy_nl; 215 break; 216 default: 217 phy_type = ixgbe_phy_unknown; 218 break; 219 } 220 221 DEBUGOUT1("phy type found is %d\n", phy_type); 222 return phy_type; 223} 224 225/** 226 * ixgbe_reset_phy_generic - Performs a PHY reset 227 * @hw: pointer to hardware structure 228 **/ 229s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 230{ 231 u32 i; 232 u16 ctrl = 0; 233 s32 status = IXGBE_SUCCESS; 234 235 DEBUGFUNC("ixgbe_reset_phy_generic"); 236 237 if (hw->phy.type == ixgbe_phy_unknown) 238 status = ixgbe_identify_phy_generic(hw); 239 240 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 241 goto out; 242 243 /* Don't reset PHY if it's shut down due to overtemp. */ 244 if (!hw->phy.reset_if_overtemp && 245 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 246 goto out; 247 248 /* 249 * Perform soft PHY reset to the PHY_XS. 250 * This will cause a soft reset to the PHY 251 */ 252 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 253 IXGBE_MDIO_PHY_XS_DEV_TYPE, 254 IXGBE_MDIO_PHY_XS_RESET); 255 256 /* 257 * Poll for reset bit to self-clear indicating reset is complete. 258 * Some PHYs could take up to 3 seconds to complete and need about 259 * 1.7 usec delay after the reset is complete. 260 */ 261 for (i = 0; i < 30; i++) { 262 msec_delay(100); 263 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 264 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 265 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 266 usec_delay(2); 267 break; 268 } 269 } 270 271 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 272 status = IXGBE_ERR_RESET_FAILED; 273 ERROR_REPORT1(IXGBE_ERROR_POLLING, 274 "PHY reset polling failed to complete.\n"); 275 } 276 277out: 278 return status; 279} 280 281/** 282 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 283 * the SWFW lock 284 * @hw: pointer to hardware structure 285 * @reg_addr: 32 bit address of PHY register to read 286 * @phy_data: Pointer to read data from PHY register 287 **/ 288s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 289 u16 *phy_data) 290{ 291 u32 i, data, command; 292 293 /* Setup and write the address cycle command */ 294 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 295 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 296 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 297 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 298 299 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 300 301 /* 302 * Check every 10 usec to see if the address cycle completed. 303 * The MDI Command bit will clear when the operation is 304 * complete 305 */ 306 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 307 usec_delay(10); 308 309 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 310 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 311 break; 312 } 313 314 315 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 316 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 317 return IXGBE_ERR_PHY; 318 } 319 320 /* 321 * Address cycle complete, setup and write the read 322 * command 323 */ 324 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 325 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 326 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 327 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 328 329 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 330 331 /* 332 * Check every 10 usec to see if the address cycle 333 * completed. The MDI Command bit will clear when the 334 * operation is complete 335 */ 336 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 337 usec_delay(10); 338 339 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 340 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 341 break; 342 } 343 344 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 345 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 346 return IXGBE_ERR_PHY; 347 } 348 349 /* 350 * Read operation is complete. Get the data 351 * from MSRWD 352 */ 353 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 354 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 355 *phy_data = (u16)(data); 356 357 return IXGBE_SUCCESS; 358} 359 360/** 361 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 362 * using the SWFW lock - this function is needed in most cases 363 * @hw: pointer to hardware structure 364 * @reg_addr: 32 bit address of PHY register to read 365 * @phy_data: Pointer to read data from PHY register 366 **/ 367s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 368 u32 device_type, u16 *phy_data) 369{ 370 s32 status; 371 u16 gssr; 372 373 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 374 375 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 376 gssr = IXGBE_GSSR_PHY1_SM; 377 else 378 gssr = IXGBE_GSSR_PHY0_SM; 379 380 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 381 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 382 phy_data); 383 hw->mac.ops.release_swfw_sync(hw, gssr); 384 } else { 385 status = IXGBE_ERR_SWFW_SYNC; 386 } 387 388 return status; 389} 390 391/** 392 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 393 * without SWFW lock 394 * @hw: pointer to hardware structure 395 * @reg_addr: 32 bit PHY register to write 396 * @device_type: 5 bit device type 397 * @phy_data: Data to write to the PHY register 398 **/ 399s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 400 u32 device_type, u16 phy_data) 401{ 402 u32 i, command; 403 404 /* Put the data in the MDI single read and write data register*/ 405 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 406 407 /* Setup and write the address cycle command */ 408 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 409 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 410 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 411 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 412 413 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 414 415 /* 416 * Check every 10 usec to see if the address cycle completed. 417 * The MDI Command bit will clear when the operation is 418 * complete 419 */ 420 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 421 usec_delay(10); 422 423 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 424 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 425 break; 426 } 427 428 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 429 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 430 return IXGBE_ERR_PHY; 431 } 432 433 /* 434 * Address cycle complete, setup and write the write 435 * command 436 */ 437 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 438 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 439 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 440 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 441 442 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 443 444 /* 445 * Check every 10 usec to see if the address cycle 446 * completed. The MDI Command bit will clear when the 447 * operation is complete 448 */ 449 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 450 usec_delay(10); 451 452 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 453 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 454 break; 455 } 456 457 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 458 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 459 return IXGBE_ERR_PHY; 460 } 461 462 return IXGBE_SUCCESS; 463} 464 465/** 466 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 467 * using SWFW lock- this function is needed in most cases 468 * @hw: pointer to hardware structure 469 * @reg_addr: 32 bit PHY register to write 470 * @device_type: 5 bit device type 471 * @phy_data: Data to write to the PHY register 472 **/ 473s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 474 u32 device_type, u16 phy_data) 475{ 476 s32 status; 477 u16 gssr; 478 479 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 480 481 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 482 gssr = IXGBE_GSSR_PHY1_SM; 483 else 484 gssr = IXGBE_GSSR_PHY0_SM; 485 486 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 487 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 488 phy_data); 489 hw->mac.ops.release_swfw_sync(hw, gssr); 490 } else { 491 status = IXGBE_ERR_SWFW_SYNC; 492 } 493 494 return status; 495} 496 497/** 498 * ixgbe_setup_phy_link_generic - Set and restart autoneg 499 * @hw: pointer to hardware structure 500 * 501 * Restart autonegotiation and PHY and waits for completion. 502 **/ 503s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 504{ 505 s32 status = IXGBE_SUCCESS; 506 u32 time_out; 507 u32 max_time_out = 10; 508 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 509 bool autoneg = FALSE; 510 ixgbe_link_speed speed; 511 512 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 513 514 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 515 516 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 517 /* Set or unset auto-negotiation 10G advertisement */ 518 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 519 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 520 &autoneg_reg); 521 522 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 523 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 524 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 525 526 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 527 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 528 autoneg_reg); 529 } 530 531 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 532 /* Set or unset auto-negotiation 1G advertisement */ 533 hw->phy.ops.read_reg(hw, 534 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 535 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 536 &autoneg_reg); 537 538 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 539 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 540 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 541 542 hw->phy.ops.write_reg(hw, 543 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 544 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 545 autoneg_reg); 546 } 547 548 if (speed & IXGBE_LINK_SPEED_100_FULL) { 549 /* Set or unset auto-negotiation 100M advertisement */ 550 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 551 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 552 &autoneg_reg); 553 554 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 555 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 556 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 557 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 558 559 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 560 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 561 autoneg_reg); 562 } 563 564 /* Restart PHY autonegotiation and wait for completion */ 565 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 566 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 567 568 autoneg_reg |= IXGBE_MII_RESTART; 569 570 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 571 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 572 573 /* Wait for autonegotiation to finish */ 574 for (time_out = 0; time_out < max_time_out; time_out++) { 575 usec_delay(10); 576 /* Restart PHY autonegotiation and wait for completion */ 577 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 578 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 579 &autoneg_reg); 580 581 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 582 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) 583 break; 584 } 585 586 if (time_out == max_time_out) { 587 status = IXGBE_ERR_LINK_SETUP; 588 ERROR_REPORT1(IXGBE_ERROR_POLLING, 589 "PHY autonegotiation time out"); 590 } 591 592 return status; 593} 594 595/** 596 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 597 * @hw: pointer to hardware structure 598 * @speed: new link speed 599 **/ 600s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 601 ixgbe_link_speed speed, 602 bool autoneg_wait_to_complete) 603{ 604 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 605 606 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 607 608 /* 609 * Clear autoneg_advertised and set new values based on input link 610 * speed. 611 */ 612 hw->phy.autoneg_advertised = 0; 613 614 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 615 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 616 617 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 618 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 619 620 if (speed & IXGBE_LINK_SPEED_100_FULL) 621 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 622 623 /* Setup link based on the new speed settings */ 624 hw->phy.ops.setup_link(hw); 625 626 return IXGBE_SUCCESS; 627} 628 629/** 630 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 631 * @hw: pointer to hardware structure 632 * @speed: pointer to link speed 633 * @autoneg: boolean auto-negotiation value 634 * 635 * Determines the link capabilities by reading the AUTOC register. 636 **/ 637s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 638 ixgbe_link_speed *speed, 639 bool *autoneg) 640{ 641 s32 status = IXGBE_ERR_LINK_SETUP; 642 u16 speed_ability; 643 644 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 645 646 *speed = 0; 647 *autoneg = TRUE; 648 649 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 650 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 651 &speed_ability); 652 653 if (status == IXGBE_SUCCESS) { 654 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 655 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 656 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 657 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 658 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 659 *speed |= IXGBE_LINK_SPEED_100_FULL; 660 } 661 662 return status; 663} 664 665/** 666 * ixgbe_check_phy_link_tnx - Determine link and speed status 667 * @hw: pointer to hardware structure 668 * 669 * Reads the VS1 register to determine if link is up and the current speed for 670 * the PHY. 671 **/ 672s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 673 bool *link_up) 674{ 675 s32 status = IXGBE_SUCCESS; 676 u32 time_out; 677 u32 max_time_out = 10; 678 u16 phy_link = 0; 679 u16 phy_speed = 0; 680 u16 phy_data = 0; 681 682 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 683 684 /* Initialize speed and link to default case */ 685 *link_up = FALSE; 686 *speed = IXGBE_LINK_SPEED_10GB_FULL; 687 688 /* 689 * Check current speed and link status of the PHY register. 690 * This is a vendor specific register and may have to 691 * be changed for other copper PHYs. 692 */ 693 for (time_out = 0; time_out < max_time_out; time_out++) { 694 usec_delay(10); 695 status = hw->phy.ops.read_reg(hw, 696 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 697 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 698 &phy_data); 699 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 700 phy_speed = phy_data & 701 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 702 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 703 *link_up = TRUE; 704 if (phy_speed == 705 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 706 *speed = IXGBE_LINK_SPEED_1GB_FULL; 707 break; 708 } 709 } 710 711 return status; 712} 713 714/** 715 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 716 * @hw: pointer to hardware structure 717 * 718 * Restart autonegotiation and PHY and waits for completion. 719 **/ 720s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 721{ 722 s32 status = IXGBE_SUCCESS; 723 u32 time_out; 724 u32 max_time_out = 10; 725 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 726 bool autoneg = FALSE; 727 ixgbe_link_speed speed; 728 729 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 730 731 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 732 733 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 734 /* Set or unset auto-negotiation 10G advertisement */ 735 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 736 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 737 &autoneg_reg); 738 739 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 740 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 741 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 742 743 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 744 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 745 autoneg_reg); 746 } 747 748 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 749 /* Set or unset auto-negotiation 1G advertisement */ 750 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 751 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 752 &autoneg_reg); 753 754 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 755 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 756 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 757 758 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 759 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 760 autoneg_reg); 761 } 762 763 if (speed & IXGBE_LINK_SPEED_100_FULL) { 764 /* Set or unset auto-negotiation 100M advertisement */ 765 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 766 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 767 &autoneg_reg); 768 769 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 770 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 771 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 772 773 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 774 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 775 autoneg_reg); 776 } 777 778 /* Restart PHY autonegotiation and wait for completion */ 779 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 780 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 781 782 autoneg_reg |= IXGBE_MII_RESTART; 783 784 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 785 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 786 787 /* Wait for autonegotiation to finish */ 788 for (time_out = 0; time_out < max_time_out; time_out++) { 789 usec_delay(10); 790 /* Restart PHY autonegotiation and wait for completion */ 791 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 792 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 793 &autoneg_reg); 794 795 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 796 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) 797 break; 798 } 799 800 if (time_out == max_time_out) { 801 status = IXGBE_ERR_LINK_SETUP; 802 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out"); 803 } 804 805 return status; 806} 807 808/** 809 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 810 * @hw: pointer to hardware structure 811 * @firmware_version: pointer to the PHY Firmware Version 812 **/ 813s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 814 u16 *firmware_version) 815{ 816 s32 status = IXGBE_SUCCESS; 817 818 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 819 820 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 821 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 822 firmware_version); 823 824 return status; 825} 826 827/** 828 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 829 * @hw: pointer to hardware structure 830 * @firmware_version: pointer to the PHY Firmware Version 831 **/ 832s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 833 u16 *firmware_version) 834{ 835 s32 status = IXGBE_SUCCESS; 836 837 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 838 839 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 840 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 841 firmware_version); 842 843 return status; 844} 845 846/** 847 * ixgbe_reset_phy_nl - Performs a PHY reset 848 * @hw: pointer to hardware structure 849 **/ 850s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 851{ 852 u16 phy_offset, control, eword, edata, block_crc; 853 bool end_data = FALSE; 854 u16 list_offset, data_offset; 855 u16 phy_data = 0; 856 s32 ret_val = IXGBE_SUCCESS; 857 u32 i; 858 859 DEBUGFUNC("ixgbe_reset_phy_nl"); 860 861 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 862 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 863 864 /* reset the PHY and poll for completion */ 865 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 866 IXGBE_MDIO_PHY_XS_DEV_TYPE, 867 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 868 869 for (i = 0; i < 100; i++) { 870 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 871 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 872 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 873 break; 874 msec_delay(10); 875 } 876 877 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 878 DEBUGOUT("PHY reset did not complete.\n"); 879 ret_val = IXGBE_ERR_PHY; 880 goto out; 881 } 882 883 /* Get init offsets */ 884 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 885 &data_offset); 886 if (ret_val != IXGBE_SUCCESS) 887 goto out; 888 889 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 890 data_offset++; 891 while (!end_data) { 892 /* 893 * Read control word from PHY init contents offset 894 */ 895 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 896 if (ret_val) 897 goto err_eeprom; 898 control = (eword & IXGBE_CONTROL_MASK_NL) >> 899 IXGBE_CONTROL_SHIFT_NL; 900 edata = eword & IXGBE_DATA_MASK_NL; 901 switch (control) { 902 case IXGBE_DELAY_NL: 903 data_offset++; 904 DEBUGOUT1("DELAY: %d MS\n", edata); 905 msec_delay(edata); 906 break; 907 case IXGBE_DATA_NL: 908 DEBUGOUT("DATA:\n"); 909 data_offset++; 910 ret_val = hw->eeprom.ops.read(hw, data_offset, 911 &phy_offset); 912 if (ret_val) 913 goto err_eeprom; 914 data_offset++; 915 for (i = 0; i < edata; i++) { 916 ret_val = hw->eeprom.ops.read(hw, data_offset, 917 &eword); 918 if (ret_val) 919 goto err_eeprom; 920 hw->phy.ops.write_reg(hw, phy_offset, 921 IXGBE_TWINAX_DEV, eword); 922 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 923 phy_offset); 924 data_offset++; 925 phy_offset++; 926 } 927 break; 928 case IXGBE_CONTROL_NL: 929 data_offset++; 930 DEBUGOUT("CONTROL:\n"); 931 if (edata == IXGBE_CONTROL_EOL_NL) { 932 DEBUGOUT("EOL\n"); 933 end_data = TRUE; 934 } else if (edata == IXGBE_CONTROL_SOL_NL) { 935 DEBUGOUT("SOL\n"); 936 } else { 937 DEBUGOUT("Bad control value\n"); 938 ret_val = IXGBE_ERR_PHY; 939 goto out; 940 } 941 break; 942 default: 943 DEBUGOUT("Bad control type\n"); 944 ret_val = IXGBE_ERR_PHY; 945 goto out; 946 } 947 } 948 949out: 950 return ret_val; 951 952err_eeprom: 953 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 954 "eeprom read at offset %d failed", data_offset); 955 return IXGBE_ERR_PHY; 956} 957 958/** 959 * ixgbe_identify_module_generic - Identifies module type 960 * @hw: pointer to hardware structure 961 * 962 * Determines HW type and calls appropriate function. 963 **/ 964s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 965{ 966 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 967 968 DEBUGFUNC("ixgbe_identify_module_generic"); 969 970 switch (hw->mac.ops.get_media_type(hw)) { 971 case ixgbe_media_type_fiber: 972 status = ixgbe_identify_sfp_module_generic(hw); 973 break; 974 975 976 default: 977 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 978 status = IXGBE_ERR_SFP_NOT_PRESENT; 979 break; 980 } 981 982 return status; 983} 984 985/** 986 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 987 * @hw: pointer to hardware structure 988 * 989 * Searches for and identifies the SFP module and assigns appropriate PHY type. 990 **/ 991s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 992{ 993 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 994 u32 vendor_oui = 0; 995 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 996 u8 identifier = 0; 997 u8 comp_codes_1g = 0; 998 u8 comp_codes_10g = 0; 999 u8 oui_bytes[3] = {0, 0, 0}; 1000 u8 cable_tech = 0; 1001 u8 cable_spec = 0; 1002 u16 enforce_sfp = 0; 1003 1004 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1005 1006 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1007 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1008 status = IXGBE_ERR_SFP_NOT_PRESENT; 1009 goto out; 1010 } 1011 1012 status = hw->phy.ops.read_i2c_eeprom(hw, 1013 IXGBE_SFF_IDENTIFIER, 1014 &identifier); 1015 1016 if (status != IXGBE_SUCCESS) 1017 goto err_read_i2c_eeprom; 1018 1019 /* LAN ID is needed for sfp_type determination */ 1020 hw->mac.ops.set_lan_id(hw); 1021 1022 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1023 hw->phy.type = ixgbe_phy_sfp_unsupported; 1024 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1025 } else { 1026 status = hw->phy.ops.read_i2c_eeprom(hw, 1027 IXGBE_SFF_1GBE_COMP_CODES, 1028 &comp_codes_1g); 1029 1030 if (status != IXGBE_SUCCESS) 1031 goto err_read_i2c_eeprom; 1032 1033 status = hw->phy.ops.read_i2c_eeprom(hw, 1034 IXGBE_SFF_10GBE_COMP_CODES, 1035 &comp_codes_10g); 1036 1037 if (status != IXGBE_SUCCESS) 1038 goto err_read_i2c_eeprom; 1039 status = hw->phy.ops.read_i2c_eeprom(hw, 1040 IXGBE_SFF_CABLE_TECHNOLOGY, 1041 &cable_tech); 1042 1043 if (status != IXGBE_SUCCESS) 1044 goto err_read_i2c_eeprom; 1045 1046 /* ID Module 1047 * ========= 1048 * 0 SFP_DA_CU 1049 * 1 SFP_SR 1050 * 2 SFP_LR 1051 * 3 SFP_DA_CORE0 - 82599-specific 1052 * 4 SFP_DA_CORE1 - 82599-specific 1053 * 5 SFP_SR/LR_CORE0 - 82599-specific 1054 * 6 SFP_SR/LR_CORE1 - 82599-specific 1055 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1056 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1057 * 9 SFP_1g_cu_CORE0 - 82599-specific 1058 * 10 SFP_1g_cu_CORE1 - 82599-specific 1059 * 11 SFP_1g_sx_CORE0 - 82599-specific 1060 * 12 SFP_1g_sx_CORE1 - 82599-specific 1061 */ 1062 if (hw->mac.type == ixgbe_mac_82598EB) { 1063 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1064 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1065 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1066 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1067 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1068 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1069 else 1070 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1071 } else if (hw->mac.type == ixgbe_mac_82599EB) { 1072 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1073 if (hw->bus.lan_id == 0) 1074 hw->phy.sfp_type = 1075 ixgbe_sfp_type_da_cu_core0; 1076 else 1077 hw->phy.sfp_type = 1078 ixgbe_sfp_type_da_cu_core1; 1079 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1080 hw->phy.ops.read_i2c_eeprom( 1081 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1082 &cable_spec); 1083 if (cable_spec & 1084 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1085 if (hw->bus.lan_id == 0) 1086 hw->phy.sfp_type = 1087 ixgbe_sfp_type_da_act_lmt_core0; 1088 else 1089 hw->phy.sfp_type = 1090 ixgbe_sfp_type_da_act_lmt_core1; 1091 } else { 1092 hw->phy.sfp_type = 1093 ixgbe_sfp_type_unknown; 1094 } 1095 } else if (comp_codes_10g & 1096 (IXGBE_SFF_10GBASESR_CAPABLE | 1097 IXGBE_SFF_10GBASELR_CAPABLE)) { 1098 if (hw->bus.lan_id == 0) 1099 hw->phy.sfp_type = 1100 ixgbe_sfp_type_srlr_core0; 1101 else 1102 hw->phy.sfp_type = 1103 ixgbe_sfp_type_srlr_core1; 1104 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1105 if (hw->bus.lan_id == 0) 1106 hw->phy.sfp_type = 1107 ixgbe_sfp_type_1g_cu_core0; 1108 else 1109 hw->phy.sfp_type = 1110 ixgbe_sfp_type_1g_cu_core1; 1111 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1112 if (hw->bus.lan_id == 0) 1113 hw->phy.sfp_type = 1114 ixgbe_sfp_type_1g_sx_core0; 1115 else 1116 hw->phy.sfp_type = 1117 ixgbe_sfp_type_1g_sx_core1; 1118 } else { 1119 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1120 } 1121 } 1122 1123 if (hw->phy.sfp_type != stored_sfp_type) 1124 hw->phy.sfp_setup_needed = TRUE; 1125 1126 /* Determine if the SFP+ PHY is dual speed or not. */ 1127 hw->phy.multispeed_fiber = FALSE; 1128 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1129 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1130 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1131 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1132 hw->phy.multispeed_fiber = TRUE; 1133 1134 /* Determine PHY vendor */ 1135 if (hw->phy.type != ixgbe_phy_nl) { 1136 hw->phy.id = identifier; 1137 status = hw->phy.ops.read_i2c_eeprom(hw, 1138 IXGBE_SFF_VENDOR_OUI_BYTE0, 1139 &oui_bytes[0]); 1140 1141 if (status != IXGBE_SUCCESS) 1142 goto err_read_i2c_eeprom; 1143 1144 status = hw->phy.ops.read_i2c_eeprom(hw, 1145 IXGBE_SFF_VENDOR_OUI_BYTE1, 1146 &oui_bytes[1]); 1147 1148 if (status != IXGBE_SUCCESS) 1149 goto err_read_i2c_eeprom; 1150 1151 status = hw->phy.ops.read_i2c_eeprom(hw, 1152 IXGBE_SFF_VENDOR_OUI_BYTE2, 1153 &oui_bytes[2]); 1154 1155 if (status != IXGBE_SUCCESS) 1156 goto err_read_i2c_eeprom; 1157 1158 vendor_oui = 1159 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1160 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1161 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1162 1163 switch (vendor_oui) { 1164 case IXGBE_SFF_VENDOR_OUI_TYCO: 1165 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1166 hw->phy.type = 1167 ixgbe_phy_sfp_passive_tyco; 1168 break; 1169 case IXGBE_SFF_VENDOR_OUI_FTL: 1170 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1171 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1172 else 1173 hw->phy.type = ixgbe_phy_sfp_ftl; 1174 break; 1175 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1176 hw->phy.type = ixgbe_phy_sfp_avago; 1177 break; 1178 case IXGBE_SFF_VENDOR_OUI_INTEL: 1179 hw->phy.type = ixgbe_phy_sfp_intel; 1180 break; 1181 default: 1182 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1183 hw->phy.type = 1184 ixgbe_phy_sfp_passive_unknown; 1185 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1186 hw->phy.type = 1187 ixgbe_phy_sfp_active_unknown; 1188 else 1189 hw->phy.type = ixgbe_phy_sfp_unknown; 1190 break; 1191 } 1192 } 1193 1194 /* Allow any DA cable vendor */ 1195 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1196 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1197 status = IXGBE_SUCCESS; 1198 goto out; 1199 } 1200 1201 /* Verify supported 1G SFP modules */ 1202 if (comp_codes_10g == 0 && 1203 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1204 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1205 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1206 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1207 hw->phy.type = ixgbe_phy_sfp_unsupported; 1208 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1209 goto out; 1210 } 1211 1212 /* Anything else 82598-based is supported */ 1213 if (hw->mac.type == ixgbe_mac_82598EB) { 1214 status = IXGBE_SUCCESS; 1215 goto out; 1216 } 1217 1218 ixgbe_get_device_caps(hw, &enforce_sfp); 1219 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1220 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1221 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1222 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1223 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1224 /* Make sure we're a supported PHY type */ 1225 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1226 status = IXGBE_SUCCESS; 1227 } else { 1228 if (hw->allow_unsupported_sfp == TRUE) { 1229 EWARN(hw, "WARNING: Intel (R) Network " 1230 "Connections are quality tested " 1231 "using Intel (R) Ethernet Optics." 1232 " Using untested modules is not " 1233 "supported and may cause unstable" 1234 " operation or damage to the " 1235 "module or the adapter. Intel " 1236 "Corporation is not responsible " 1237 "for any harm caused by using " 1238 "untested modules.\n", status); 1239 status = IXGBE_SUCCESS; 1240 } else { 1241 DEBUGOUT("SFP+ module not supported\n"); 1242 hw->phy.type = 1243 ixgbe_phy_sfp_unsupported; 1244 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1245 } 1246 } 1247 } else { 1248 status = IXGBE_SUCCESS; 1249 } 1250 } 1251 1252out: 1253 return status; 1254 1255err_read_i2c_eeprom: 1256 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1257 if (hw->phy.type != ixgbe_phy_nl) { 1258 hw->phy.id = 0; 1259 hw->phy.type = ixgbe_phy_unknown; 1260 } 1261 return IXGBE_ERR_SFP_NOT_PRESENT; 1262} 1263 1264 1265 1266/** 1267 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1268 * @hw: pointer to hardware structure 1269 * @list_offset: offset to the SFP ID list 1270 * @data_offset: offset to the SFP data block 1271 * 1272 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1273 * so it returns the offsets to the phy init sequence block. 1274 **/ 1275s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1276 u16 *list_offset, 1277 u16 *data_offset) 1278{ 1279 u16 sfp_id; 1280 u16 sfp_type = hw->phy.sfp_type; 1281 1282 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1283 1284 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1285 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1286 1287 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1288 return IXGBE_ERR_SFP_NOT_PRESENT; 1289 1290 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1291 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1292 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1293 1294 /* 1295 * Limiting active cables and 1G Phys must be initialized as 1296 * SR modules 1297 */ 1298 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1299 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1300 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1301 sfp_type = ixgbe_sfp_type_srlr_core0; 1302 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1303 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1304 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1305 sfp_type = ixgbe_sfp_type_srlr_core1; 1306 1307 /* Read offset to PHY init contents */ 1308 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1309 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1310 "eeprom read at offset %d failed", 1311 IXGBE_PHY_INIT_OFFSET_NL); 1312 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1313 } 1314 1315 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1316 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1317 1318 /* Shift offset to first ID word */ 1319 (*list_offset)++; 1320 1321 /* 1322 * Find the matching SFP ID in the EEPROM 1323 * and program the init sequence 1324 */ 1325 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1326 goto err_phy; 1327 1328 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1329 if (sfp_id == sfp_type) { 1330 (*list_offset)++; 1331 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1332 goto err_phy; 1333 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1334 DEBUGOUT("SFP+ module not supported\n"); 1335 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1336 } else { 1337 break; 1338 } 1339 } else { 1340 (*list_offset) += 2; 1341 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1342 goto err_phy; 1343 } 1344 } 1345 1346 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1347 DEBUGOUT("No matching SFP+ module found\n"); 1348 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1349 } 1350 1351 return IXGBE_SUCCESS; 1352 1353err_phy: 1354 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1355 "eeprom read at offset %d failed", *list_offset); 1356 return IXGBE_ERR_PHY; 1357} 1358 1359/** 1360 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1361 * @hw: pointer to hardware structure 1362 * @byte_offset: EEPROM byte offset to read 1363 * @eeprom_data: value read 1364 * 1365 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1366 **/ 1367s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1368 u8 *eeprom_data) 1369{ 1370 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1371 1372 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1373 IXGBE_I2C_EEPROM_DEV_ADDR, 1374 eeprom_data); 1375} 1376 1377/** 1378 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1379 * @hw: pointer to hardware structure 1380 * @byte_offset: byte offset at address 0xA2 1381 * @eeprom_data: value read 1382 * 1383 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1384 **/ 1385static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1386 u8 *sff8472_data) 1387{ 1388 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1389 IXGBE_I2C_EEPROM_DEV_ADDR2, 1390 sff8472_data); 1391} 1392 1393/** 1394 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1395 * @hw: pointer to hardware structure 1396 * @byte_offset: EEPROM byte offset to write 1397 * @eeprom_data: value to write 1398 * 1399 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1400 **/ 1401s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1402 u8 eeprom_data) 1403{ 1404 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1405 1406 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1407 IXGBE_I2C_EEPROM_DEV_ADDR, 1408 eeprom_data); 1409} 1410 1411/** 1412 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1413 * @hw: pointer to hardware structure 1414 * @byte_offset: byte offset to read 1415 * @data: value read 1416 * 1417 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1418 * a specified device address. 1419 **/ 1420s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1421 u8 dev_addr, u8 *data) 1422{ 1423 s32 status = IXGBE_SUCCESS; 1424 u32 max_retry = 10; 1425 u32 retry = 0; 1426 u16 swfw_mask = 0; 1427 bool nack = 1; 1428 *data = 0; 1429 1430 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1431 1432 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1433 swfw_mask = IXGBE_GSSR_PHY1_SM; 1434 else 1435 swfw_mask = IXGBE_GSSR_PHY0_SM; 1436 1437 do { 1438 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 1439 != IXGBE_SUCCESS) { 1440 status = IXGBE_ERR_SWFW_SYNC; 1441 goto read_byte_out; 1442 } 1443 1444 ixgbe_i2c_start(hw); 1445 1446 /* Device Address and write indication */ 1447 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1448 if (status != IXGBE_SUCCESS) 1449 goto fail; 1450 1451 status = ixgbe_get_i2c_ack(hw); 1452 if (status != IXGBE_SUCCESS) 1453 goto fail; 1454 1455 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1456 if (status != IXGBE_SUCCESS) 1457 goto fail; 1458 1459 status = ixgbe_get_i2c_ack(hw); 1460 if (status != IXGBE_SUCCESS) 1461 goto fail; 1462 1463 ixgbe_i2c_start(hw); 1464 1465 /* Device Address and read indication */ 1466 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1467 if (status != IXGBE_SUCCESS) 1468 goto fail; 1469 1470 status = ixgbe_get_i2c_ack(hw); 1471 if (status != IXGBE_SUCCESS) 1472 goto fail; 1473 1474 status = ixgbe_clock_in_i2c_byte(hw, data); 1475 if (status != IXGBE_SUCCESS) 1476 goto fail; 1477 1478 status = ixgbe_clock_out_i2c_bit(hw, nack); 1479 if (status != IXGBE_SUCCESS) 1480 goto fail; 1481 1482 ixgbe_i2c_stop(hw); 1483 break; 1484 1485fail: 1486 ixgbe_i2c_bus_clear(hw); 1487 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1488 msec_delay(100); 1489 retry++; 1490 if (retry < max_retry) 1491 DEBUGOUT("I2C byte read error - Retrying.\n"); 1492 else 1493 DEBUGOUT("I2C byte read error.\n"); 1494 1495 } while (retry < max_retry); 1496 1497 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1498 1499read_byte_out: 1500 return status; 1501} 1502 1503/** 1504 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1505 * @hw: pointer to hardware structure 1506 * @byte_offset: byte offset to write 1507 * @data: value to write 1508 * 1509 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1510 * a specified device address. 1511 **/ 1512s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1513 u8 dev_addr, u8 data) 1514{ 1515 s32 status = IXGBE_SUCCESS; 1516 u32 max_retry = 1; 1517 u32 retry = 0; 1518 u16 swfw_mask = 0; 1519 1520 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 1521 1522 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1523 swfw_mask = IXGBE_GSSR_PHY1_SM; 1524 else 1525 swfw_mask = IXGBE_GSSR_PHY0_SM; 1526 1527 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1528 status = IXGBE_ERR_SWFW_SYNC; 1529 goto write_byte_out; 1530 } 1531 1532 do { 1533 ixgbe_i2c_start(hw); 1534 1535 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1536 if (status != IXGBE_SUCCESS) 1537 goto fail; 1538 1539 status = ixgbe_get_i2c_ack(hw); 1540 if (status != IXGBE_SUCCESS) 1541 goto fail; 1542 1543 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1544 if (status != IXGBE_SUCCESS) 1545 goto fail; 1546 1547 status = ixgbe_get_i2c_ack(hw); 1548 if (status != IXGBE_SUCCESS) 1549 goto fail; 1550 1551 status = ixgbe_clock_out_i2c_byte(hw, data); 1552 if (status != IXGBE_SUCCESS) 1553 goto fail; 1554 1555 status = ixgbe_get_i2c_ack(hw); 1556 if (status != IXGBE_SUCCESS) 1557 goto fail; 1558 1559 ixgbe_i2c_stop(hw); 1560 break; 1561 1562fail: 1563 ixgbe_i2c_bus_clear(hw); 1564 retry++; 1565 if (retry < max_retry) 1566 DEBUGOUT("I2C byte write error - Retrying.\n"); 1567 else 1568 DEBUGOUT("I2C byte write error.\n"); 1569 } while (retry < max_retry); 1570 1571 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1572 1573write_byte_out: 1574 return status; 1575} 1576 1577/** 1578 * ixgbe_i2c_start - Sets I2C start condition 1579 * @hw: pointer to hardware structure 1580 * 1581 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1582 **/ 1583static void ixgbe_i2c_start(struct ixgbe_hw *hw) 1584{ 1585 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1586 1587 DEBUGFUNC("ixgbe_i2c_start"); 1588 1589 /* Start condition must begin with data and clock high */ 1590 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1591 ixgbe_raise_i2c_clk(hw, &i2cctl); 1592 1593 /* Setup time for start condition (4.7us) */ 1594 usec_delay(IXGBE_I2C_T_SU_STA); 1595 1596 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1597 1598 /* Hold time for start condition (4us) */ 1599 usec_delay(IXGBE_I2C_T_HD_STA); 1600 1601 ixgbe_lower_i2c_clk(hw, &i2cctl); 1602 1603 /* Minimum low period of clock is 4.7 us */ 1604 usec_delay(IXGBE_I2C_T_LOW); 1605 1606} 1607 1608/** 1609 * ixgbe_i2c_stop - Sets I2C stop condition 1610 * @hw: pointer to hardware structure 1611 * 1612 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1613 **/ 1614static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1615{ 1616 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1617 1618 DEBUGFUNC("ixgbe_i2c_stop"); 1619 1620 /* Stop condition must begin with data low and clock high */ 1621 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1622 ixgbe_raise_i2c_clk(hw, &i2cctl); 1623 1624 /* Setup time for stop condition (4us) */ 1625 usec_delay(IXGBE_I2C_T_SU_STO); 1626 1627 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1628 1629 /* bus free time between stop and start (4.7us)*/ 1630 usec_delay(IXGBE_I2C_T_BUF); 1631} 1632 1633/** 1634 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1635 * @hw: pointer to hardware structure 1636 * @data: data byte to clock in 1637 * 1638 * Clocks in one byte data via I2C data/clock 1639 **/ 1640static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1641{ 1642 s32 i; 1643 bool bit = 0; 1644 1645 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 1646 1647 for (i = 7; i >= 0; i--) { 1648 ixgbe_clock_in_i2c_bit(hw, &bit); 1649 *data |= bit << i; 1650 } 1651 1652 return IXGBE_SUCCESS; 1653} 1654 1655/** 1656 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1657 * @hw: pointer to hardware structure 1658 * @data: data byte clocked out 1659 * 1660 * Clocks out one byte data via I2C data/clock 1661 **/ 1662static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1663{ 1664 s32 status = IXGBE_SUCCESS; 1665 s32 i; 1666 u32 i2cctl; 1667 bool bit = 0; 1668 1669 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 1670 1671 for (i = 7; i >= 0; i--) { 1672 bit = (data >> i) & 0x1; 1673 status = ixgbe_clock_out_i2c_bit(hw, bit); 1674 1675 if (status != IXGBE_SUCCESS) 1676 break; 1677 } 1678 1679 /* Release SDA line (set high) */ 1680 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1681 i2cctl |= IXGBE_I2C_DATA_OUT; 1682 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1683 IXGBE_WRITE_FLUSH(hw); 1684 1685 return status; 1686} 1687 1688/** 1689 * ixgbe_get_i2c_ack - Polls for I2C ACK 1690 * @hw: pointer to hardware structure 1691 * 1692 * Clocks in/out one bit via I2C data/clock 1693 **/ 1694static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1695{ 1696 s32 status = IXGBE_SUCCESS; 1697 u32 i = 0; 1698 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1699 u32 timeout = 10; 1700 bool ack = 1; 1701 1702 DEBUGFUNC("ixgbe_get_i2c_ack"); 1703 1704 ixgbe_raise_i2c_clk(hw, &i2cctl); 1705 1706 1707 /* Minimum high period of clock is 4us */ 1708 usec_delay(IXGBE_I2C_T_HIGH); 1709 1710 /* Poll for ACK. Note that ACK in I2C spec is 1711 * transition from 1 to 0 */ 1712 for (i = 0; i < timeout; i++) { 1713 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1714 ack = ixgbe_get_i2c_data(&i2cctl); 1715 1716 usec_delay(1); 1717 if (ack == 0) 1718 break; 1719 } 1720 1721 if (ack == 1) { 1722 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1723 "I2C ack was not received.\n"); 1724 status = IXGBE_ERR_I2C; 1725 } 1726 1727 ixgbe_lower_i2c_clk(hw, &i2cctl); 1728 1729 /* Minimum low period of clock is 4.7 us */ 1730 usec_delay(IXGBE_I2C_T_LOW); 1731 1732 return status; 1733} 1734 1735/** 1736 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1737 * @hw: pointer to hardware structure 1738 * @data: read data value 1739 * 1740 * Clocks in one bit via I2C data/clock 1741 **/ 1742static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1743{ 1744 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1745 1746 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 1747 1748 ixgbe_raise_i2c_clk(hw, &i2cctl); 1749 1750 /* Minimum high period of clock is 4us */ 1751 usec_delay(IXGBE_I2C_T_HIGH); 1752 1753 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1754 *data = ixgbe_get_i2c_data(&i2cctl); 1755 1756 ixgbe_lower_i2c_clk(hw, &i2cctl); 1757 1758 /* Minimum low period of clock is 4.7 us */ 1759 usec_delay(IXGBE_I2C_T_LOW); 1760 1761 return IXGBE_SUCCESS; 1762} 1763 1764/** 1765 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1766 * @hw: pointer to hardware structure 1767 * @data: data value to write 1768 * 1769 * Clocks out one bit via I2C data/clock 1770 **/ 1771static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1772{ 1773 s32 status; 1774 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1775 1776 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 1777 1778 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1779 if (status == IXGBE_SUCCESS) { 1780 ixgbe_raise_i2c_clk(hw, &i2cctl); 1781 1782 /* Minimum high period of clock is 4us */ 1783 usec_delay(IXGBE_I2C_T_HIGH); 1784 1785 ixgbe_lower_i2c_clk(hw, &i2cctl); 1786 1787 /* Minimum low period of clock is 4.7 us. 1788 * This also takes care of the data hold time. 1789 */ 1790 usec_delay(IXGBE_I2C_T_LOW); 1791 } else { 1792 status = IXGBE_ERR_I2C; 1793 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1794 "I2C data was not set to %X\n", data); 1795 } 1796 1797 return status; 1798} 1799/** 1800 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1801 * @hw: pointer to hardware structure 1802 * @i2cctl: Current value of I2CCTL register 1803 * 1804 * Raises the I2C clock line '0'->'1' 1805 **/ 1806static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1807{ 1808 u32 i = 0; 1809 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 1810 u32 i2cctl_r = 0; 1811 1812 DEBUGFUNC("ixgbe_raise_i2c_clk"); 1813 1814 for (i = 0; i < timeout; i++) { 1815 *i2cctl |= IXGBE_I2C_CLK_OUT; 1816 1817 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1818 IXGBE_WRITE_FLUSH(hw); 1819 /* SCL rise time (1000ns) */ 1820 usec_delay(IXGBE_I2C_T_RISE); 1821 1822 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1823 if (i2cctl_r & IXGBE_I2C_CLK_IN) 1824 break; 1825 } 1826} 1827 1828/** 1829 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1830 * @hw: pointer to hardware structure 1831 * @i2cctl: Current value of I2CCTL register 1832 * 1833 * Lowers the I2C clock line '1'->'0' 1834 **/ 1835static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1836{ 1837 1838 DEBUGFUNC("ixgbe_lower_i2c_clk"); 1839 1840 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1841 1842 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1843 IXGBE_WRITE_FLUSH(hw); 1844 1845 /* SCL fall time (300ns) */ 1846 usec_delay(IXGBE_I2C_T_FALL); 1847} 1848 1849/** 1850 * ixgbe_set_i2c_data - Sets the I2C data bit 1851 * @hw: pointer to hardware structure 1852 * @i2cctl: Current value of I2CCTL register 1853 * @data: I2C data value (0 or 1) to set 1854 * 1855 * Sets the I2C data bit 1856 **/ 1857static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1858{ 1859 s32 status = IXGBE_SUCCESS; 1860 1861 DEBUGFUNC("ixgbe_set_i2c_data"); 1862 1863 if (data) 1864 *i2cctl |= IXGBE_I2C_DATA_OUT; 1865 else 1866 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1867 1868 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1869 IXGBE_WRITE_FLUSH(hw); 1870 1871 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1872 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1873 1874 /* Verify data was set correctly */ 1875 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1876 if (data != ixgbe_get_i2c_data(i2cctl)) { 1877 status = IXGBE_ERR_I2C; 1878 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1879 "Error - I2C data was not set to %X.\n", 1880 data); 1881 } 1882 1883 return status; 1884} 1885 1886/** 1887 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1888 * @hw: pointer to hardware structure 1889 * @i2cctl: Current value of I2CCTL register 1890 * 1891 * Returns the I2C data bit value 1892 **/ 1893static bool ixgbe_get_i2c_data(u32 *i2cctl) 1894{ 1895 bool data; 1896 1897 DEBUGFUNC("ixgbe_get_i2c_data"); 1898 1899 if (*i2cctl & IXGBE_I2C_DATA_IN) 1900 data = 1; 1901 else 1902 data = 0; 1903 1904 return data; 1905} 1906 1907/** 1908 * ixgbe_i2c_bus_clear - Clears the I2C bus 1909 * @hw: pointer to hardware structure 1910 * 1911 * Clears the I2C bus by sending nine clock pulses. 1912 * Used when data line is stuck low. 1913 **/ 1914void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1915{ 1916 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1917 u32 i; 1918 1919 DEBUGFUNC("ixgbe_i2c_bus_clear"); 1920 1921 ixgbe_i2c_start(hw); 1922 1923 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1924 1925 for (i = 0; i < 9; i++) { 1926 ixgbe_raise_i2c_clk(hw, &i2cctl); 1927 1928 /* Min high period of clock is 4us */ 1929 usec_delay(IXGBE_I2C_T_HIGH); 1930 1931 ixgbe_lower_i2c_clk(hw, &i2cctl); 1932 1933 /* Min low period of clock is 4.7us*/ 1934 usec_delay(IXGBE_I2C_T_LOW); 1935 } 1936 1937 ixgbe_i2c_start(hw); 1938 1939 /* Put the i2c bus back to default state */ 1940 ixgbe_i2c_stop(hw); 1941} 1942 1943/** 1944 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 1945 * @hw: pointer to hardware structure 1946 * 1947 * Checks if the LASI temp alarm status was triggered due to overtemp 1948 **/ 1949s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 1950{ 1951 s32 status = IXGBE_SUCCESS; 1952 u16 phy_data = 0; 1953 1954 DEBUGFUNC("ixgbe_tn_check_overtemp"); 1955 1956 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 1957 goto out; 1958 1959 /* Check that the LASI temp alarm status was triggered */ 1960 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 1961 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 1962 1963 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 1964 goto out; 1965 1966 status = IXGBE_ERR_OVERTEMP; 1967 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 1968out: 1969 return status; 1970} 1971