1/****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD$*/ 34 35 36#include "ixgbe_type.h" 37#include "ixgbe_dcb.h" 38#include "ixgbe_dcb_82598.h" 39#include "ixgbe_dcb_82599.h" 40 41/** 42 * ixgbe_dcb_calculate_tc_credits - This calculates the ieee traffic class 43 * credits from the configured bandwidth percentages. Credits 44 * are the smallest unit programmable into the underlying 45 * hardware. The IEEE 802.1Qaz specification do not use bandwidth 46 * groups so this is much simplified from the CEE case. 47 */ 48s32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max, 49 int max_frame_size) 50{ 51 int min_percent = 100; 52 int min_credit, multiplier; 53 int i; 54 55 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) / 56 IXGBE_DCB_CREDIT_QUANTUM; 57 58 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 59 if (bw[i] < min_percent && bw[i]) 60 min_percent = bw[i]; 61 } 62 63 multiplier = (min_credit / min_percent) + 1; 64 65 /* Find out the hw credits for each TC */ 66 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 67 int val = min(bw[i] * multiplier, IXGBE_DCB_MAX_CREDIT_REFILL); 68 69 if (val < min_credit) 70 val = min_credit; 71 refill[i] = (u16)val; 72 73 max[i] = bw[i] ? (bw[i]*IXGBE_DCB_MAX_CREDIT)/100 : min_credit; 74 } 75 76 return 0; 77} 78 79/** 80 * ixgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits 81 * @ixgbe_dcb_config: Struct containing DCB settings. 82 * @direction: Configuring either Tx or Rx. 83 * 84 * This function calculates the credits allocated to each traffic class. 85 * It should be called only after the rules are checked by 86 * ixgbe_dcb_check_config_cee(). 87 */ 88s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *hw, 89 struct ixgbe_dcb_config *dcb_config, 90 u32 max_frame_size, u8 direction) 91{ 92 struct ixgbe_dcb_tc_path *p; 93 u32 min_multiplier = 0; 94 u16 min_percent = 100; 95 s32 ret_val = IXGBE_SUCCESS; 96 /* Initialization values default for Tx settings */ 97 u32 min_credit = 0; 98 u32 credit_refill = 0; 99 u32 credit_max = 0; 100 u16 link_percentage = 0; 101 u8 bw_percent = 0; 102 u8 i; 103 104 if (dcb_config == NULL) { 105 ret_val = IXGBE_ERR_CONFIG; 106 goto out; 107 } 108 109 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) / 110 IXGBE_DCB_CREDIT_QUANTUM; 111 112 /* Find smallest link percentage */ 113 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 114 p = &dcb_config->tc_config[i].path[direction]; 115 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id]; 116 link_percentage = p->bwg_percent; 117 118 link_percentage = (link_percentage * bw_percent) / 100; 119 120 if (link_percentage && link_percentage < min_percent) 121 min_percent = link_percentage; 122 } 123 124 /* 125 * The ratio between traffic classes will control the bandwidth 126 * percentages seen on the wire. To calculate this ratio we use 127 * a multiplier. It is required that the refill credits must be 128 * larger than the max frame size so here we find the smallest 129 * multiplier that will allow all bandwidth percentages to be 130 * greater than the max frame size. 131 */ 132 min_multiplier = (min_credit / min_percent) + 1; 133 134 /* Find out the link percentage for each TC first */ 135 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 136 p = &dcb_config->tc_config[i].path[direction]; 137 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id]; 138 139 link_percentage = p->bwg_percent; 140 /* Must be careful of integer division for very small nums */ 141 link_percentage = (link_percentage * bw_percent) / 100; 142 if (p->bwg_percent > 0 && link_percentage == 0) 143 link_percentage = 1; 144 145 /* Save link_percentage for reference */ 146 p->link_percent = (u8)link_percentage; 147 148 /* Calculate credit refill ratio using multiplier */ 149 credit_refill = min(link_percentage * min_multiplier, 150 (u32)IXGBE_DCB_MAX_CREDIT_REFILL); 151 p->data_credits_refill = (u16)credit_refill; 152 153 /* Calculate maximum credit for the TC */ 154 credit_max = (link_percentage * IXGBE_DCB_MAX_CREDIT) / 100; 155 156 /* 157 * Adjustment based on rule checking, if the percentage 158 * of a TC is too small, the maximum credit may not be 159 * enough to send out a jumbo frame in data plane arbitration. 160 */ 161 if (credit_max && (credit_max < min_credit)) 162 credit_max = min_credit; 163 164 if (direction == IXGBE_DCB_TX_CONFIG) { 165 /* 166 * Adjustment based on rule checking, if the 167 * percentage of a TC is too small, the maximum 168 * credit may not be enough to send out a TSO 169 * packet in descriptor plane arbitration. 170 */ 171 if (credit_max && (credit_max < 172 IXGBE_DCB_MIN_TSO_CREDIT) 173 && (hw->mac.type == ixgbe_mac_82598EB)) 174 credit_max = IXGBE_DCB_MIN_TSO_CREDIT; 175 176 dcb_config->tc_config[i].desc_credits_max = 177 (u16)credit_max; 178 } 179 180 p->data_credits_max = (u16)credit_max; 181 } 182 183out: 184 return ret_val; 185} 186 187/** 188 * ixgbe_dcb_unpack_pfc_cee - Unpack dcb_config PFC info 189 * @cfg: dcb configuration to unpack into hardware consumable fields 190 * @map: user priority to traffic class map 191 * @pfc_up: u8 to store user priority PFC bitmask 192 * 193 * This unpacks the dcb configuration PFC info which is stored per 194 * traffic class into a 8bit user priority bitmask that can be 195 * consumed by hardware routines. The priority to tc map must be 196 * updated before calling this routine to use current up-to maps. 197 */ 198void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *cfg, u8 *map, u8 *pfc_up) 199{ 200 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 201 int up; 202 203 /* 204 * If the TC for this user priority has PFC enabled then set the 205 * matching bit in 'pfc_up' to reflect that PFC is enabled. 206 */ 207 for (*pfc_up = 0, up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) { 208 if (tc_config[map[up]].pfc != ixgbe_dcb_pfc_disabled) 209 *pfc_up |= 1 << up; 210 } 211} 212 213void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *cfg, int direction, 214 u16 *refill) 215{ 216 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 217 int tc; 218 219 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 220 refill[tc] = tc_config[tc].path[direction].data_credits_refill; 221} 222 223void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *cfg, u16 *max) 224{ 225 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 226 int tc; 227 228 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 229 max[tc] = tc_config[tc].desc_credits_max; 230} 231 232void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *cfg, int direction, 233 u8 *bwgid) 234{ 235 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 236 int tc; 237 238 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 239 bwgid[tc] = tc_config[tc].path[direction].bwg_id; 240} 241 242void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *cfg, int direction, 243 u8 *tsa) 244{ 245 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 246 int tc; 247 248 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 249 tsa[tc] = tc_config[tc].path[direction].tsa; 250} 251 252u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up) 253{ 254 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 255 u8 prio_mask = 1 << up; 256 u8 tc = cfg->num_tcs.pg_tcs; 257 258 /* If tc is 0 then DCB is likely not enabled or supported */ 259 if (!tc) 260 goto out; 261 262 /* 263 * Test from maximum TC to 1 and report the first match we find. If 264 * we find no match we can assume that the TC is 0 since the TC must 265 * be set for all user priorities 266 */ 267 for (tc--; tc; tc--) { 268 if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap) 269 break; 270 } 271out: 272 return tc; 273} 274 275void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *cfg, int direction, 276 u8 *map) 277{ 278 u8 up; 279 280 for (up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) 281 map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up); 282} 283 284/** 285 * ixgbe_dcb_config - Struct containing DCB settings. 286 * @dcb_config: Pointer to DCB config structure 287 * 288 * This function checks DCB rules for DCB settings. 289 * The following rules are checked: 290 * 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%. 291 * 2. The sum of bandwidth percentages of all Traffic Classes within a Bandwidth 292 * Group must total 100. 293 * 3. A Traffic Class should not be set to both Link Strict Priority 294 * and Group Strict Priority. 295 * 4. Link strict Bandwidth Groups can only have link strict traffic classes 296 * with zero bandwidth. 297 */ 298s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *dcb_config) 299{ 300 struct ixgbe_dcb_tc_path *p; 301 s32 ret_val = IXGBE_SUCCESS; 302 u8 i, j, bw = 0, bw_id; 303 u8 bw_sum[2][IXGBE_DCB_MAX_BW_GROUP]; 304 bool link_strict[2][IXGBE_DCB_MAX_BW_GROUP]; 305 306 memset(bw_sum, 0, sizeof(bw_sum)); 307 memset(link_strict, 0, sizeof(link_strict)); 308 309 /* First Tx, then Rx */ 310 for (i = 0; i < 2; i++) { 311 /* Check each traffic class for rule violation */ 312 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) { 313 p = &dcb_config->tc_config[j].path[i]; 314 315 bw = p->bwg_percent; 316 bw_id = p->bwg_id; 317 318 if (bw_id >= IXGBE_DCB_MAX_BW_GROUP) { 319 ret_val = IXGBE_ERR_CONFIG; 320 goto err_config; 321 } 322 if (p->tsa == ixgbe_dcb_tsa_strict) { 323 link_strict[i][bw_id] = TRUE; 324 /* Link strict should have zero bandwidth */ 325 if (bw) { 326 ret_val = IXGBE_ERR_CONFIG; 327 goto err_config; 328 } 329 } else if (!bw) { 330 /* 331 * Traffic classes without link strict 332 * should have non-zero bandwidth. 333 */ 334 ret_val = IXGBE_ERR_CONFIG; 335 goto err_config; 336 } 337 bw_sum[i][bw_id] += bw; 338 } 339 340 bw = 0; 341 342 /* Check each bandwidth group for rule violation */ 343 for (j = 0; j < IXGBE_DCB_MAX_BW_GROUP; j++) { 344 bw += dcb_config->bw_percentage[i][j]; 345 /* 346 * Sum of bandwidth percentages of all traffic classes 347 * within a Bandwidth Group must total 100 except for 348 * link strict group (zero bandwidth). 349 */ 350 if (link_strict[i][j]) { 351 if (bw_sum[i][j]) { 352 /* 353 * Link strict group should have zero 354 * bandwidth. 355 */ 356 ret_val = IXGBE_ERR_CONFIG; 357 goto err_config; 358 } 359 } else if (bw_sum[i][j] != IXGBE_DCB_BW_PERCENT && 360 bw_sum[i][j] != 0) { 361 ret_val = IXGBE_ERR_CONFIG; 362 goto err_config; 363 } 364 } 365 366 if (bw != IXGBE_DCB_BW_PERCENT) { 367 ret_val = IXGBE_ERR_CONFIG; 368 goto err_config; 369 } 370 } 371 372err_config: 373 DEBUGOUT2("DCB error code %d while checking %s settings.\n", 374 ret_val, (i == IXGBE_DCB_TX_CONFIG) ? "Tx" : "Rx"); 375 376 return ret_val; 377} 378 379/** 380 * ixgbe_dcb_get_tc_stats - Returns status of each traffic class 381 * @hw: pointer to hardware structure 382 * @stats: pointer to statistics structure 383 * @tc_count: Number of elements in bwg_array. 384 * 385 * This function returns the status data for each of the Traffic Classes in use. 386 */ 387s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, 388 u8 tc_count) 389{ 390 s32 ret = IXGBE_NOT_IMPLEMENTED; 391 switch (hw->mac.type) { 392 case ixgbe_mac_82598EB: 393 ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count); 394 break; 395 case ixgbe_mac_82599EB: 396 case ixgbe_mac_X540: 397#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 398 ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count); 399 break; 400#endif 401 default: 402 break; 403 } 404 return ret; 405} 406 407/** 408 * ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class 409 * @hw: pointer to hardware structure 410 * @stats: pointer to statistics structure 411 * @tc_count: Number of elements in bwg_array. 412 * 413 * This function returns the CBFC status data for each of the Traffic Classes. 414 */ 415s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, 416 u8 tc_count) 417{ 418 s32 ret = IXGBE_NOT_IMPLEMENTED; 419 switch (hw->mac.type) { 420 case ixgbe_mac_82598EB: 421 ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count); 422 break; 423 case ixgbe_mac_82599EB: 424 case ixgbe_mac_X540: 425#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 426 ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count); 427 break; 428#endif 429 default: 430 break; 431 } 432 return ret; 433} 434 435/** 436 * ixgbe_dcb_config_rx_arbiter_cee - Config Rx arbiter 437 * @hw: pointer to hardware structure 438 * @dcb_config: pointer to ixgbe_dcb_config structure 439 * 440 * Configure Rx Data Arbiter and credits for each traffic class. 441 */ 442s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw, 443 struct ixgbe_dcb_config *dcb_config) 444{ 445 s32 ret = IXGBE_NOT_IMPLEMENTED; 446 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 447 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 448 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 449 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 450 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 451 452 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 453 ixgbe_dcb_unpack_max_cee(dcb_config, max); 454 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 455 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 456 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 457 458 switch (hw->mac.type) { 459 case ixgbe_mac_82598EB: 460 ret = ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa); 461 break; 462 case ixgbe_mac_82599EB: 463 case ixgbe_mac_X540: 464#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 465 ret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid, 466 tsa, map); 467 break; 468#endif 469 default: 470 break; 471 } 472 return ret; 473} 474 475/** 476 * ixgbe_dcb_config_tx_desc_arbiter_cee - Config Tx Desc arbiter 477 * @hw: pointer to hardware structure 478 * @dcb_config: pointer to ixgbe_dcb_config structure 479 * 480 * Configure Tx Descriptor Arbiter and credits for each traffic class. 481 */ 482s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *hw, 483 struct ixgbe_dcb_config *dcb_config) 484{ 485 s32 ret = IXGBE_NOT_IMPLEMENTED; 486 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 487 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 488 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 489 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 490 491 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 492 ixgbe_dcb_unpack_max_cee(dcb_config, max); 493 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 494 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 495 496 switch (hw->mac.type) { 497 case ixgbe_mac_82598EB: 498 ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, 499 bwgid, tsa); 500 break; 501 case ixgbe_mac_82599EB: 502 case ixgbe_mac_X540: 503#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 504 ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 505 bwgid, tsa); 506 break; 507#endif 508 default: 509 break; 510 } 511 return ret; 512} 513 514/** 515 * ixgbe_dcb_config_tx_data_arbiter_cee - Config Tx data arbiter 516 * @hw: pointer to hardware structure 517 * @dcb_config: pointer to ixgbe_dcb_config structure 518 * 519 * Configure Tx Data Arbiter and credits for each traffic class. 520 */ 521s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *hw, 522 struct ixgbe_dcb_config *dcb_config) 523{ 524 s32 ret = IXGBE_NOT_IMPLEMENTED; 525 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 526 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 527 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 528 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 529 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 530 531 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 532 ixgbe_dcb_unpack_max_cee(dcb_config, max); 533 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 534 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 535 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 536 537 switch (hw->mac.type) { 538 case ixgbe_mac_82598EB: 539 ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, 540 bwgid, tsa); 541 break; 542 case ixgbe_mac_82599EB: 543 case ixgbe_mac_X540: 544#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 545 ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, 546 bwgid, tsa, 547 map); 548 break; 549#endif 550 default: 551 break; 552 } 553 return ret; 554} 555 556/** 557 * ixgbe_dcb_config_pfc_cee - Config priority flow control 558 * @hw: pointer to hardware structure 559 * @dcb_config: pointer to ixgbe_dcb_config structure 560 * 561 * Configure Priority Flow Control for each traffic class. 562 */ 563s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *hw, 564 struct ixgbe_dcb_config *dcb_config) 565{ 566 s32 ret = IXGBE_NOT_IMPLEMENTED; 567 u8 pfc_en; 568 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 569 570 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 571 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en); 572 573 switch (hw->mac.type) { 574 case ixgbe_mac_82598EB: 575 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en); 576 break; 577 case ixgbe_mac_82599EB: 578 case ixgbe_mac_X540: 579#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 580 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map); 581 break; 582#endif 583 default: 584 break; 585 } 586 return ret; 587} 588 589/** 590 * ixgbe_dcb_config_tc_stats - Config traffic class statistics 591 * @hw: pointer to hardware structure 592 * 593 * Configure queue statistics registers, all queues belonging to same traffic 594 * class uses a single set of queue statistics counters. 595 */ 596s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw) 597{ 598 s32 ret = IXGBE_NOT_IMPLEMENTED; 599 switch (hw->mac.type) { 600 case ixgbe_mac_82598EB: 601 ret = ixgbe_dcb_config_tc_stats_82598(hw); 602 break; 603 case ixgbe_mac_82599EB: 604 case ixgbe_mac_X540: 605#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 606 ret = ixgbe_dcb_config_tc_stats_82599(hw, NULL); 607 break; 608#endif 609 default: 610 break; 611 } 612 return ret; 613} 614 615/** 616 * ixgbe_dcb_hw_config_cee - Config and enable DCB 617 * @hw: pointer to hardware structure 618 * @dcb_config: pointer to ixgbe_dcb_config structure 619 * 620 * Configure dcb settings and enable dcb mode. 621 */ 622s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *hw, 623 struct ixgbe_dcb_config *dcb_config) 624{ 625 s32 ret = IXGBE_NOT_IMPLEMENTED; 626 u8 pfc_en; 627 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 628 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 629 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 630 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 631 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 632 633 /* Unpack CEE standard containers */ 634 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 635 ixgbe_dcb_unpack_max_cee(dcb_config, max); 636 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 637 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 638 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 639 640 hw->mac.ops.setup_rxpba(hw, dcb_config->num_tcs.pg_tcs, 641 0, dcb_config->rx_pba_cfg); 642 643 switch (hw->mac.type) { 644 case ixgbe_mac_82598EB: 645 ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->link_speed, 646 refill, max, bwgid, tsa); 647 break; 648 case ixgbe_mac_82599EB: 649 case ixgbe_mac_X540: 650#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 651 ixgbe_dcb_config_82599(hw, dcb_config); 652 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->link_speed, 653 refill, max, bwgid, 654 tsa, map); 655 656 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config); 657 break; 658#endif 659 default: 660 break; 661 } 662 663 if (!ret && dcb_config->pfc_mode_enable) { 664 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en); 665 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map); 666 } 667 668 return ret; 669} 670 671/* Helper routines to abstract HW specifics from DCB netlink ops */ 672s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map) 673{ 674 int ret = IXGBE_ERR_PARAM; 675 676 switch (hw->mac.type) { 677 case ixgbe_mac_82598EB: 678 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en); 679 break; 680 case ixgbe_mac_82599EB: 681 case ixgbe_mac_X540: 682#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 683 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map); 684 break; 685#endif 686 default: 687 break; 688 } 689 return ret; 690} 691 692s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max, 693 u8 *bwg_id, u8 *tsa, u8 *map) 694{ 695 switch (hw->mac.type) { 696 case ixgbe_mac_82598EB: 697 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa); 698 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, 699 tsa); 700 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, 701 tsa); 702 break; 703 case ixgbe_mac_82599EB: 704 case ixgbe_mac_X540: 705#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 706 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, 707 tsa, map); 708 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, 709 tsa); 710 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, 711 tsa, map); 712 break; 713#endif 714 default: 715 break; 716 } 717 return 0; 718} 719