ixgbe.h revision 225736 
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3  Copyright (c) 2001-2011, Intel Corporation
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32******************************************************************************/
33/*$FreeBSD: stable/9/sys/dev/ixgbe/ixgbe.h 221189 2011-04-28 23:21:40Z jfv $*/
34
35
36#ifndef _IXGBE_H_
37#define _IXGBE_H_
38
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#if __FreeBSD_version >= 800000
43#include <sys/buf_ring.h>
44#endif
45#include <sys/mbuf.h>
46#include <sys/protosw.h>
47#include <sys/socket.h>
48#include <sys/malloc.h>
49#include <sys/kernel.h>
50#include <sys/module.h>
51#include <sys/sockio.h>
52
53#include <net/if.h>
54#include <net/if_arp.h>
55#include <net/bpf.h>
56#include <net/ethernet.h>
57#include <net/if_dl.h>
58#include <net/if_media.h>
59
60#include <net/bpf.h>
61#include <net/if_types.h>
62#include <net/if_vlan_var.h>
63
64#include <netinet/in_systm.h>
65#include <netinet/in.h>
66#include <netinet/if_ether.h>
67#include <netinet/ip.h>
68#include <netinet/ip6.h>
69#include <netinet/tcp.h>
70#include <netinet/tcp_lro.h>
71#include <netinet/udp.h>
72
73#include <machine/in_cksum.h>
74
75#include <sys/bus.h>
76#include <machine/bus.h>
77#include <sys/rman.h>
78#include <machine/resource.h>
79#include <vm/vm.h>
80#include <vm/pmap.h>
81#include <machine/clock.h>
82#include <dev/pci/pcivar.h>
83#include <dev/pci/pcireg.h>
84#include <sys/proc.h>
85#include <sys/sysctl.h>
86#include <sys/endian.h>
87#include <sys/taskqueue.h>
88#include <sys/pcpu.h>
89#include <sys/smp.h>
90#include <machine/smp.h>
91
92#ifdef IXGBE_IEEE1588
93#include <sys/ieee1588.h>
94#endif
95
96#include "ixgbe_api.h"
97
98/* Tunables */
99
100/*
101 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
102 * number of transmit descriptors allocated by the driver. Increasing this
103 * value allows the driver to queue more transmits. Each descriptor is 16
104 * bytes. Performance tests have show the 2K value to be optimal for top
105 * performance.
106 */
107#define DEFAULT_TXD	1024
108#define PERFORM_TXD	2048
109#define MAX_TXD		4096
110#define MIN_TXD		64
111
112/*
113 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
114 * number of receive descriptors allocated for each RX queue. Increasing this
115 * value allows the driver to buffer more incoming packets. Each descriptor
116 * is 16 bytes.  A receive buffer is also allocated for each descriptor.
117 *
118 * Note: with 8 rings and a dual port card, it is possible to bump up
119 *	against the system mbuf pool limit, you can tune nmbclusters
120 *	to adjust for this.
121 */
122#define DEFAULT_RXD	1024
123#define PERFORM_RXD	2048
124#define MAX_RXD		4096
125#define MIN_RXD		64
126
127/* Alignment for rings */
128#define DBA_ALIGN	128
129
130/*
131 * This parameter controls the maximum no of times the driver will loop in
132 * the isr. Minimum Value = 1
133 */
134#define MAX_LOOP	10
135
136/*
137 * This is the max watchdog interval, ie. the time that can
138 * pass between any two TX clean operations, such only happening
139 * when the TX hardware is functioning.
140 */
141#define IXGBE_WATCHDOG                   (10 * hz)
142
143/*
144 * This parameters control when the driver calls the routine to reclaim
145 * transmit descriptors.
146 */
147#define IXGBE_TX_CLEANUP_THRESHOLD	(adapter->num_tx_desc / 8)
148#define IXGBE_TX_OP_THRESHOLD		(adapter->num_tx_desc / 32)
149
150#define IXGBE_MAX_FRAME_SIZE	0x3F00
151
152/* Flow control constants */
153#define IXGBE_FC_PAUSE		0xFFFF
154#define IXGBE_FC_HI		0x20000
155#define IXGBE_FC_LO		0x10000
156
157/* Keep older OS drivers building... */
158#if !defined(SYSCTL_ADD_UQUAD)
159#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
160#endif
161
162/* Defines for printing debug information */
163#define DEBUG_INIT  0
164#define DEBUG_IOCTL 0
165#define DEBUG_HW    0
166
167#define INIT_DEBUGOUT(S)            if (DEBUG_INIT)  printf(S "\n")
168#define INIT_DEBUGOUT1(S, A)        if (DEBUG_INIT)  printf(S "\n", A)
169#define INIT_DEBUGOUT2(S, A, B)     if (DEBUG_INIT)  printf(S "\n", A, B)
170#define IOCTL_DEBUGOUT(S)           if (DEBUG_IOCTL) printf(S "\n")
171#define IOCTL_DEBUGOUT1(S, A)       if (DEBUG_IOCTL) printf(S "\n", A)
172#define IOCTL_DEBUGOUT2(S, A, B)    if (DEBUG_IOCTL) printf(S "\n", A, B)
173#define HW_DEBUGOUT(S)              if (DEBUG_HW) printf(S "\n")
174#define HW_DEBUGOUT1(S, A)          if (DEBUG_HW) printf(S "\n", A)
175#define HW_DEBUGOUT2(S, A, B)       if (DEBUG_HW) printf(S "\n", A, B)
176
177#define MAX_NUM_MULTICAST_ADDRESSES     128
178#define IXGBE_82598_SCATTER		100
179#define IXGBE_82599_SCATTER		32
180#define MSIX_82598_BAR			3
181#define MSIX_82599_BAR			4
182#define IXGBE_TSO_SIZE			65535
183#define IXGBE_TX_BUFFER_SIZE		((u32) 1514)
184#define IXGBE_RX_HDR			128
185#define IXGBE_VFTA_SIZE			128
186#define IXGBE_BR_SIZE			4096
187#define IXGBE_QUEUE_IDLE		0
188#define IXGBE_QUEUE_WORKING		1
189#define IXGBE_QUEUE_HUNG		2
190
191/* Offload bits in mbuf flag */
192#if __FreeBSD_version >= 800000
193#define CSUM_OFFLOAD		(CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
194#else
195#define CSUM_OFFLOAD		(CSUM_IP|CSUM_TCP|CSUM_UDP)
196#endif
197
198/* For 6.X code compatibility */
199#if !defined(ETHER_BPF_MTAP)
200#define ETHER_BPF_MTAP		BPF_MTAP
201#endif
202
203#if __FreeBSD_version < 700000
204#define CSUM_TSO		0
205#define IFCAP_TSO4		0
206#endif
207
208/*
209 * Interrupt Moderation parameters
210 */
211#define IXGBE_LOW_LATENCY	128
212#define IXGBE_AVE_LATENCY	400
213#define IXGBE_BULK_LATENCY	1200
214#define IXGBE_LINK_ITR		2000
215
216/*
217 *****************************************************************************
218 * vendor_info_array
219 *
220 * This array contains the list of Subvendor/Subdevice IDs on which the driver
221 * should load.
222 *
223 *****************************************************************************
224 */
225typedef struct _ixgbe_vendor_info_t {
226	unsigned int    vendor_id;
227	unsigned int    device_id;
228	unsigned int    subvendor_id;
229	unsigned int    subdevice_id;
230	unsigned int    index;
231} ixgbe_vendor_info_t;
232
233
234struct ixgbe_tx_buf {
235	u32		eop_index;
236	struct mbuf	*m_head;
237	bus_dmamap_t	map;
238};
239
240struct ixgbe_rx_buf {
241	struct mbuf	*m_head;
242	struct mbuf	*m_pack;
243	struct mbuf	*fmp;
244	bus_dmamap_t	hmap;
245	bus_dmamap_t	pmap;
246};
247
248/*
249 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free.
250 */
251struct ixgbe_dma_alloc {
252	bus_addr_t		dma_paddr;
253	caddr_t			dma_vaddr;
254	bus_dma_tag_t		dma_tag;
255	bus_dmamap_t		dma_map;
256	bus_dma_segment_t	dma_seg;
257	bus_size_t		dma_size;
258	int			dma_nseg;
259};
260
261/*
262** Driver queue struct: this is the interrupt container
263**  for the associated tx and rx ring.
264*/
265struct ix_queue {
266	struct adapter		*adapter;
267	u32			msix;           /* This queue's MSIX vector */
268	u32			eims;           /* This queue's EIMS bit */
269	u32			eitr_setting;
270	struct resource		*res;
271	void			*tag;
272	struct tx_ring		*txr;
273	struct rx_ring		*rxr;
274	struct task		que_task;
275	struct taskqueue	*tq;
276	u64			irqs;
277};
278
279/*
280 * The transmit ring, one per queue
281 */
282struct tx_ring {
283        struct adapter		*adapter;
284	struct mtx		tx_mtx;
285	u32			me;
286	int			queue_status;
287	int			watchdog_time;
288	union ixgbe_adv_tx_desc	*tx_base;
289	struct ixgbe_dma_alloc	txdma;
290	u32			next_avail_desc;
291	u32			next_to_clean;
292	struct ixgbe_tx_buf	*tx_buffers;
293	volatile u16		tx_avail;
294	u32			txd_cmd;
295	bus_dma_tag_t		txtag;
296	char			mtx_name[16];
297#if __FreeBSD_version >= 800000
298	struct buf_ring		*br;
299#endif
300#ifdef IXGBE_FDIR
301	u16			atr_sample;
302	u16			atr_count;
303#endif
304	u32			bytes;  /* used for AIM */
305	u32			packets;
306	/* Soft Stats */
307	u64			no_desc_avail;
308	u64			total_packets;
309};
310
311
312/*
313 * The Receive ring, one per rx queue
314 */
315struct rx_ring {
316        struct adapter		*adapter;
317	struct mtx		rx_mtx;
318	u32			me;
319	union ixgbe_adv_rx_desc	*rx_base;
320	struct ixgbe_dma_alloc	rxdma;
321	struct lro_ctrl		lro;
322	bool			lro_enabled;
323	bool			hdr_split;
324	bool			hw_rsc;
325	bool			discard;
326        u32			next_to_refresh;
327        u32 			next_to_check;
328	char			mtx_name[16];
329	struct ixgbe_rx_buf	*rx_buffers;
330	bus_dma_tag_t		htag;
331	bus_dma_tag_t		ptag;
332
333	u32			bytes; /* Used for AIM calc */
334	u32			packets;
335
336	/* Soft stats */
337	u64			rx_irq;
338	u64			rx_split_packets;
339	u64			rx_packets;
340	u64 			rx_bytes;
341	u64 			rx_discarded;
342	u64 			rsc_num;
343#ifdef IXGBE_FDIR
344	u64			flm;
345#endif
346};
347
348/* Our adapter structure */
349struct adapter {
350	struct ifnet		*ifp;
351	struct ixgbe_hw		hw;
352
353	struct ixgbe_osdep	osdep;
354	struct device		*dev;
355
356	struct resource		*pci_mem;
357	struct resource		*msix_mem;
358
359	/*
360	 * Interrupt resources: this set is
361	 * either used for legacy, or for Link
362	 * when doing MSIX
363	 */
364	void			*tag;
365	struct resource 	*res;
366
367	struct ifmedia		media;
368	struct callout		timer;
369	int			msix;
370	int			if_flags;
371
372	struct mtx		core_mtx;
373
374	eventhandler_tag 	vlan_attach;
375	eventhandler_tag 	vlan_detach;
376
377	u16			num_vlans;
378	u16			num_queues;
379
380	/*
381	** Shadow VFTA table, this is needed because
382	** the real vlan filter table gets cleared during
383	** a soft reset and the driver needs to be able
384	** to repopulate it.
385	*/
386	u32			shadow_vfta[IXGBE_VFTA_SIZE];
387
388	/* Info about the interface */
389	u32			optics;
390	int			advertise;  /* link speeds */
391	bool			link_active;
392	u16			max_frame_size;
393	u16			num_segs;
394	u32			link_speed;
395	bool			link_up;
396	u32 			linkvec;
397
398	/* Mbuf cluster size */
399	u32			rx_mbuf_sz;
400
401	/* Support for pluggable optics */
402	bool			sfp_probe;
403	struct task     	link_task;  /* Link tasklet */
404	struct task     	mod_task;   /* SFP tasklet */
405	struct task     	msf_task;   /* Multispeed Fiber */
406#ifdef IXGBE_FDIR
407	int			fdir_reinit;
408	struct task     	fdir_task;
409#endif
410	struct taskqueue	*tq;
411
412	/*
413	** Queues:
414	**   This is the irq holder, it has
415	**   and RX/TX pair or rings associated
416	**   with it.
417	*/
418	struct ix_queue		*queues;
419
420	/*
421	 * Transmit rings:
422	 *	Allocated at run time, an array of rings.
423	 */
424	struct tx_ring		*tx_rings;
425	int			num_tx_desc;
426
427	/*
428	 * Receive rings:
429	 *	Allocated at run time, an array of rings.
430	 */
431	struct rx_ring		*rx_rings;
432	int			num_rx_desc;
433	u64			que_mask;
434	u32			rx_process_limit;
435
436	/* Multicast array memory */
437	u8			*mta;
438
439	/* Misc stats maintained by the driver */
440	unsigned long   	dropped_pkts;
441	unsigned long   	mbuf_defrag_failed;
442	unsigned long   	mbuf_header_failed;
443	unsigned long   	mbuf_packet_failed;
444	unsigned long   	no_tx_map_avail;
445	unsigned long   	no_tx_dma_setup;
446	unsigned long   	watchdog_events;
447	unsigned long   	tso_tx;
448	unsigned long		link_irq;
449
450	struct ixgbe_hw_stats 	stats;
451};
452
453/* Precision Time Sync (IEEE 1588) defines */
454#define ETHERTYPE_IEEE1588      0x88F7
455#define PICOSECS_PER_TICK       20833
456#define TSYNC_UDP_PORT          319 /* UDP port for the protocol */
457#define IXGBE_ADVTXD_TSTAMP	0x00080000
458
459
460#define IXGBE_CORE_LOCK_INIT(_sc, _name) \
461        mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF)
462#define IXGBE_CORE_LOCK_DESTROY(_sc)      mtx_destroy(&(_sc)->core_mtx)
463#define IXGBE_TX_LOCK_DESTROY(_sc)        mtx_destroy(&(_sc)->tx_mtx)
464#define IXGBE_RX_LOCK_DESTROY(_sc)        mtx_destroy(&(_sc)->rx_mtx)
465#define IXGBE_CORE_LOCK(_sc)              mtx_lock(&(_sc)->core_mtx)
466#define IXGBE_TX_LOCK(_sc)                mtx_lock(&(_sc)->tx_mtx)
467#define IXGBE_TX_TRYLOCK(_sc)             mtx_trylock(&(_sc)->tx_mtx)
468#define IXGBE_RX_LOCK(_sc)                mtx_lock(&(_sc)->rx_mtx)
469#define IXGBE_CORE_UNLOCK(_sc)            mtx_unlock(&(_sc)->core_mtx)
470#define IXGBE_TX_UNLOCK(_sc)              mtx_unlock(&(_sc)->tx_mtx)
471#define IXGBE_RX_UNLOCK(_sc)              mtx_unlock(&(_sc)->rx_mtx)
472#define IXGBE_CORE_LOCK_ASSERT(_sc)       mtx_assert(&(_sc)->core_mtx, MA_OWNED)
473#define IXGBE_TX_LOCK_ASSERT(_sc)         mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
474
475
476static inline bool
477ixgbe_is_sfp(struct ixgbe_hw *hw)
478{
479	switch (hw->phy.type) {
480	case ixgbe_phy_sfp_avago:
481	case ixgbe_phy_sfp_ftl:
482	case ixgbe_phy_sfp_intel:
483	case ixgbe_phy_sfp_unknown:
484	case ixgbe_phy_sfp_passive_tyco:
485	case ixgbe_phy_sfp_passive_unknown:
486		return TRUE;
487	default:
488		return FALSE;
489	}
490}
491
492/* Workaround to make 8.0 buildable */
493#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504
494static __inline int
495drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br)
496{
497#ifdef ALTQ
498        if (ALTQ_IS_ENABLED(&ifp->if_snd))
499                return (1);
500#endif
501        return (!buf_ring_empty(br));
502}
503#endif
504
505/*
506** Find the number of unrefreshed RX descriptors
507*/
508static inline u16
509ixgbe_rx_unrefreshed(struct rx_ring *rxr)
510{
511	struct adapter  *adapter = rxr->adapter;
512
513	if (rxr->next_to_check > rxr->next_to_refresh)
514		return (rxr->next_to_check - rxr->next_to_refresh - 1);
515	else
516		return ((adapter->num_rx_desc + rxr->next_to_check) -
517		    rxr->next_to_refresh - 1);
518}
519
520#endif /* _IXGBE_H_ */
521