ixgbe.h revision 190873 
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3  Copyright (c) 2001-2009, Intel Corporation
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32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe.h 190873 2009-04-10 00:22:48Z jfv $*/
34
35
36#ifndef _IXGBE_H_
37#define _IXGBE_H_
38
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/mbuf.h>
43#include <sys/protosw.h>
44#include <sys/socket.h>
45#include <sys/malloc.h>
46#include <sys/kernel.h>
47#include <sys/module.h>
48#include <sys/sockio.h>
49
50#include <net/if.h>
51#include <net/if_arp.h>
52#include <net/bpf.h>
53#include <net/ethernet.h>
54#include <net/if_dl.h>
55#include <net/if_media.h>
56
57#include <net/bpf.h>
58#include <net/if_types.h>
59#include <net/if_vlan_var.h>
60
61#include <netinet/in_systm.h>
62#include <netinet/in.h>
63#include <netinet/if_ether.h>
64#include <netinet/ip.h>
65#include <netinet/ip6.h>
66#include <netinet/tcp.h>
67#include <netinet/tcp_lro.h>
68#include <netinet/udp.h>
69
70#include <machine/in_cksum.h>
71
72#include <sys/bus.h>
73#include <machine/bus.h>
74#include <sys/rman.h>
75#include <machine/resource.h>
76#include <vm/vm.h>
77#include <vm/pmap.h>
78#include <machine/clock.h>
79#include <dev/pci/pcivar.h>
80#include <dev/pci/pcireg.h>
81#include <sys/proc.h>
82#include <sys/sysctl.h>
83#include <sys/endian.h>
84#include <sys/taskqueue.h>
85#include <sys/pcpu.h>
86
87#ifdef IXGBE_TIMESYNC
88#include <sys/ioccom.h>
89#include <sys/time.h>
90#endif
91
92#include "ixgbe_api.h"
93
94/* Tunables */
95
96/*
97 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
98 * number of transmit descriptors allocated by the driver. Increasing this
99 * value allows the driver to queue more transmits. Each descriptor is 16
100 * bytes. Performance tests have show the 2K value to be optimal for top
101 * performance.
102 */
103#define DEFAULT_TXD	1024
104#define PERFORM_TXD	2048
105#define MAX_TXD		4096
106#define MIN_TXD		64
107
108/*
109 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
110 * number of receive descriptors allocated for each RX queue. Increasing this
111 * value allows the driver to buffer more incoming packets. Each descriptor
112 * is 16 bytes.  A receive buffer is also allocated for each descriptor.
113 *
114 * Note: with 8 rings and a dual port card, it is possible to bump up
115 *	against the system mbuf pool limit, you can tune nmbclusters
116 *	to adjust for this.
117 */
118#define DEFAULT_RXD	1024
119#define PERFORM_RXD	2048
120#define MAX_RXD		4096
121#define MIN_RXD		64
122
123/* Alignment for rings */
124#define DBA_ALIGN	128
125
126/*
127 * This parameter controls the maximum no of times the driver will loop in
128 * the isr. Minimum Value = 1
129 */
130#define MAX_LOOP	10
131
132/*
133 * This parameter controls the duration of transmit watchdog timer.
134 */
135#define IXGBE_TX_TIMEOUT                   5	/* set to 5 seconds */
136
137/*
138 * This parameters control when the driver calls the routine to reclaim
139 * transmit descriptors.
140 */
141#define IXGBE_TX_CLEANUP_THRESHOLD	(adapter->num_tx_desc / 8)
142#define IXGBE_TX_OP_THRESHOLD		(adapter->num_tx_desc / 32)
143
144#define IXGBE_MAX_FRAME_SIZE	0x3F00
145
146/* Flow control constants */
147#define IXGBE_FC_PAUSE		0x680
148#define IXGBE_FC_HI		0x20000
149#define IXGBE_FC_LO		0x10000
150
151/* Defines for printing debug information */
152#define DEBUG_INIT  0
153#define DEBUG_IOCTL 0
154#define DEBUG_HW    0
155
156#define INIT_DEBUGOUT(S)            if (DEBUG_INIT)  printf(S "\n")
157#define INIT_DEBUGOUT1(S, A)        if (DEBUG_INIT)  printf(S "\n", A)
158#define INIT_DEBUGOUT2(S, A, B)     if (DEBUG_INIT)  printf(S "\n", A, B)
159#define IOCTL_DEBUGOUT(S)           if (DEBUG_IOCTL) printf(S "\n")
160#define IOCTL_DEBUGOUT1(S, A)       if (DEBUG_IOCTL) printf(S "\n", A)
161#define IOCTL_DEBUGOUT2(S, A, B)    if (DEBUG_IOCTL) printf(S "\n", A, B)
162#define HW_DEBUGOUT(S)              if (DEBUG_HW) printf(S "\n")
163#define HW_DEBUGOUT1(S, A)          if (DEBUG_HW) printf(S "\n", A)
164#define HW_DEBUGOUT2(S, A, B)       if (DEBUG_HW) printf(S "\n", A, B)
165
166#define MAX_NUM_MULTICAST_ADDRESSES     128
167#define IXGBE_82598_SCATTER		100
168#define IXGBE_82599_SCATTER		32
169#define MSIX_82598_BAR			3
170#define MSIX_82599_BAR			4
171#define IXGBE_TSO_SIZE			65535
172#define IXGBE_TX_BUFFER_SIZE		((u32) 1514)
173#define IXGBE_RX_HDR			128
174#define CSUM_OFFLOAD			7	/* Bits in csum flags */
175
176/* The number of MSIX messages the 82598 supports */
177#define IXGBE_MSGS			18
178
179/* For 6.X code compatibility */
180#if !defined(ETHER_BPF_MTAP)
181#define ETHER_BPF_MTAP		BPF_MTAP
182#endif
183
184#if __FreeBSD_version < 700000
185#define CSUM_TSO		0
186#define IFCAP_TSO4		0
187#endif
188
189/*
190 * Interrupt Moderation parameters
191 */
192#define IXGBE_LOW_LATENCY	128
193#define IXGBE_AVE_LATENCY	400
194#define IXGBE_BULK_LATENCY	1200
195#define IXGBE_LINK_ITR		2000
196
197/* Header split args for get_bug */
198#define IXGBE_CLEAN_HDR		1
199#define IXGBE_CLEAN_PKT		2
200#define IXGBE_CLEAN_ALL		3
201
202/* Used for auto RX queue configuration */
203extern int mp_ncpus;
204
205/*
206 *****************************************************************************
207 * vendor_info_array
208 *
209 * This array contains the list of Subvendor/Subdevice IDs on which the driver
210 * should load.
211 *
212 *****************************************************************************
213 */
214typedef struct _ixgbe_vendor_info_t {
215	unsigned int    vendor_id;
216	unsigned int    device_id;
217	unsigned int    subvendor_id;
218	unsigned int    subdevice_id;
219	unsigned int    index;
220} ixgbe_vendor_info_t;
221
222
223struct ixgbe_tx_buf {
224	u32		eop_index;
225	struct mbuf	*m_head;
226	bus_dmamap_t	map;
227};
228
229struct ixgbe_rx_buf {
230	struct mbuf	*m_head;
231	struct mbuf	*m_pack;
232	bus_dmamap_t	map;
233};
234
235/*
236 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free.
237 */
238struct ixgbe_dma_alloc {
239	bus_addr_t		dma_paddr;
240	caddr_t			dma_vaddr;
241	bus_dma_tag_t		dma_tag;
242	bus_dmamap_t		dma_map;
243	bus_dma_segment_t	dma_seg;
244	bus_size_t		dma_size;
245	int			dma_nseg;
246};
247
248/*
249 * The transmit ring, one per tx queue
250 */
251struct tx_ring {
252        struct adapter		*adapter;
253	struct mtx		tx_mtx;
254	u32			me;
255	u32			msix;
256	u32			eims;
257	u32			watchdog_timer;
258	union ixgbe_adv_tx_desc	*tx_base;
259	volatile u32		tx_hwb;
260	struct ixgbe_dma_alloc	txdma;
261	struct task     	tx_task;
262	struct taskqueue	*tq;
263	u32			next_avail_tx_desc;
264	u32			next_tx_to_clean;
265	struct ixgbe_tx_buf	*tx_buffers;
266	volatile u16		tx_avail;
267	u32			txd_cmd;
268	bus_dma_tag_t		txtag;
269	char			mtx_name[16];
270	/* Soft Stats */
271	u32			no_tx_desc_avail;
272	u32			no_tx_desc_late;
273	u64			tx_irq;
274	u64			total_packets;
275};
276
277
278/*
279 * The Receive ring, one per rx queue
280 */
281struct rx_ring {
282        struct adapter		*adapter;
283	struct mtx		rx_mtx;
284	u32			me;
285	u32			msix;
286	u32			eims;
287	u32			payload;
288	struct task     	rx_task;
289	struct taskqueue	*tq;
290	union ixgbe_adv_rx_desc	*rx_base;
291	struct ixgbe_dma_alloc	rxdma;
292	struct lro_ctrl		lro;
293        unsigned int		last_cleaned;
294        unsigned int		next_to_check;
295	struct ixgbe_rx_buf	*rx_buffers;
296	bus_dma_tag_t		rxtag;
297	bus_dmamap_t		spare_map;
298	struct mbuf		*fmp;
299	struct mbuf		*lmp;
300	char			mtx_name[16];
301
302	u32			bytes; /* Used for AIM calc */
303	u32			eitr_setting;
304
305	/* Soft stats */
306	u64			rx_irq;
307	u64			rx_split_packets;
308	u64			rx_packets;
309	u64 			rx_bytes;
310};
311
312/* Our adapter structure */
313struct adapter {
314	struct ifnet	*ifp;
315	struct ixgbe_hw	hw;
316
317	struct ixgbe_osdep	osdep;
318	struct device	*dev;
319
320	struct resource	*pci_mem;
321	struct resource	*msix_mem;
322
323	/*
324	 * Interrupt resources:
325	 */
326	void		*tag[IXGBE_MSGS];
327	struct resource *res[IXGBE_MSGS];
328	int		rid[IXGBE_MSGS];
329
330	struct ifmedia	media;
331	struct callout	timer;
332	int		msix;
333	int		if_flags;
334
335	struct mtx	core_mtx;
336
337	/* Info about the board itself */
338	u32		part_num;
339	u32		optics;
340	bool		link_active;
341	u16		max_frame_size;
342	u32		link_speed;
343	bool		link_up;
344	u32 		linkvec;
345	u32		tx_int_delay;
346	u32		tx_abs_int_delay;
347	u32		rx_int_delay;
348	u32		rx_abs_int_delay;
349
350	/* Mbuf cluster size */
351	u32		rx_mbuf_sz;
352
353	/* Support for pluggable optics */
354	bool		sfp_probe;
355	struct task     link_task; 	/* Link tasklet */
356	struct task     mod_task; 	/* SFP tasklet */
357	struct task     msf_task; 	/* Multispeed Fiber tasklet */
358	struct taskqueue	*tq;
359
360	/*
361	 * Transmit rings:
362	 *	Allocated at run time, an array of rings.
363	 */
364	struct tx_ring	*tx_rings;
365	int		num_tx_desc;
366	int		num_tx_queues;
367
368	/*
369	 * Receive rings:
370	 *	Allocated at run time, an array of rings.
371	 */
372	struct rx_ring	*rx_rings;
373	int		num_rx_desc;
374	int		num_rx_queues;
375	u32		rx_mask;
376	u32		rx_process_limit;
377
378#ifdef IXGBE_TIMESYNC
379	u64		last_stamp;
380	u64		last_sec;
381	u32		last_ns;
382#endif
383
384	/* Misc stats maintained by the driver */
385	unsigned long   dropped_pkts;
386	unsigned long   mbuf_defrag_failed;
387	unsigned long   mbuf_header_failed;
388	unsigned long   mbuf_packet_failed;
389	unsigned long   no_tx_map_avail;
390	unsigned long   no_tx_dma_setup;
391	unsigned long   watchdog_events;
392	unsigned long   tso_tx;
393	unsigned long	link_irq;
394
395	struct ixgbe_hw_stats stats;
396};
397
398#ifdef IXGBE_TIMESYNC
399/* Precision Time Sync (IEEE 1588) defines */
400#define ETHERTYPE_IEEE1588      0x88F7
401#define PICOSECS_PER_TICK       20833
402#define TSYNC_UDP_PORT          319 /* UDP port for the protocol */
403#define IXGBE_ADVTXD_TSTAMP	0x00080000
404
405/* TIMESYNC IOCTL defines */
406#define IXGBE_TIMESYNC_READTS     _IOWR('i', 127, struct ixgbe_tsync_read)
407#define IXGBE_TIMESTAMP           5       /* A unique return value */
408
409/* Used in the READTS IOCTL */
410struct ixgbe_tsync_read {
411        int read_current_time;
412        struct timespec system_time;
413        u64 network_time;
414        u64 rx_stamp;
415        u64 tx_stamp;
416        u16 seqid;
417        unsigned char srcid[6];
418        int rx_valid;
419        int tx_valid;
420};
421
422#endif /* IXGBE_TIMESYNC */
423
424#define IXGBE_CORE_LOCK_INIT(_sc, _name) \
425        mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF)
426#define IXGBE_CORE_LOCK_DESTROY(_sc)      mtx_destroy(&(_sc)->core_mtx)
427#define IXGBE_TX_LOCK_DESTROY(_sc)                mtx_destroy(&(_sc)->tx_mtx)
428#define IXGBE_RX_LOCK_DESTROY(_sc)                mtx_destroy(&(_sc)->rx_mtx)
429#define IXGBE_CORE_LOCK(_sc)              mtx_lock(&(_sc)->core_mtx)
430#define IXGBE_TX_LOCK(_sc)                        mtx_lock(&(_sc)->tx_mtx)
431#define IXGBE_TX_TRYLOCK(_sc)                     mtx_trylock(&(_sc)->tx_mtx)
432#define IXGBE_RX_LOCK(_sc)                        mtx_lock(&(_sc)->rx_mtx)
433#define IXGBE_CORE_UNLOCK(_sc)            mtx_unlock(&(_sc)->core_mtx)
434#define IXGBE_TX_UNLOCK(_sc)              mtx_unlock(&(_sc)->tx_mtx)
435#define IXGBE_RX_UNLOCK(_sc)              mtx_unlock(&(_sc)->rx_mtx)
436#define IXGBE_CORE_LOCK_ASSERT(_sc)       mtx_assert(&(_sc)->core_mtx, MA_OWNED)
437#define IXGBE_TX_LOCK_ASSERT(_sc)         mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
438
439
440static inline bool
441ixgbe_is_sfp(struct ixgbe_hw *hw)
442{
443	switch (hw->phy.type) {
444	case ixgbe_phy_sfp_avago:
445	case ixgbe_phy_sfp_ftl:
446	case ixgbe_phy_sfp_intel:
447	case ixgbe_phy_sfp_unknown:
448	case ixgbe_phy_tw_tyco:
449	case ixgbe_phy_tw_unknown:
450		return TRUE;
451	default:
452		return FALSE;
453	}
454}
455
456#endif /* _IXGBE_H_ */
457