ixgbe.h revision 185352
1/****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe.h 185352 2008-11-26 23:41:18Z jfv $*/ 34 35 36#ifndef _IXGBE_H_ 37#define _IXGBE_H_ 38 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/mbuf.h> 43#include <sys/protosw.h> 44#include <sys/socket.h> 45#include <sys/malloc.h> 46#include <sys/kernel.h> 47#include <sys/module.h> 48#include <sys/sockio.h> 49 50#include <net/if.h> 51#include <net/if_arp.h> 52#include <net/bpf.h> 53#include <net/ethernet.h> 54#include <net/if_dl.h> 55#include <net/if_media.h> 56 57#include <net/bpf.h> 58#include <net/if_types.h> 59#include <net/if_vlan_var.h> 60 61#include <netinet/in_systm.h> 62#include <netinet/in.h> 63#include <netinet/if_ether.h> 64#include <netinet/ip.h> 65#include <netinet/ip6.h> 66#include <netinet/tcp.h> 67#include <netinet/udp.h> 68 69#include <machine/in_cksum.h> 70 71#include <sys/bus.h> 72#include <machine/bus.h> 73#include <sys/rman.h> 74#include <machine/resource.h> 75#include <vm/vm.h> 76#include <vm/pmap.h> 77#include <machine/clock.h> 78#include <dev/pci/pcivar.h> 79#include <dev/pci/pcireg.h> 80#include <sys/proc.h> 81#include <sys/sysctl.h> 82#include <sys/endian.h> 83#include <sys/taskqueue.h> 84#include <sys/pcpu.h> 85 86#include "ixgbe_api.h" 87#include "tcp_lro.h" 88 89/* Tunables */ 90 91/* 92 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 93 * number of transmit descriptors allocated by the driver. Increasing this 94 * value allows the driver to queue more transmits. Each descriptor is 16 95 * bytes. Performance tests have show the 2K value to be optimal for top 96 * performance. 97 */ 98#define DEFAULT_TXD 256 99#define PERFORM_TXD 2048 100#define MAX_TXD 4096 101#define MIN_TXD 64 102 103/* 104 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 105 * number of receive descriptors allocated for each RX queue. Increasing this 106 * value allows the driver to buffer more incoming packets. Each descriptor 107 * is 16 bytes. A receive buffer is also allocated for each descriptor. 108 * 109 * Note: with 8 rings and a dual port card, it is possible to bump up 110 * against the system mbuf pool limit, you can tune nmbclusters 111 * to adjust for this. 112 */ 113#define DEFAULT_RXD 256 114#define PERFORM_RXD 2048 115#define MAX_RXD 4096 116#define MIN_RXD 64 117 118/* Alignment for rings */ 119#define DBA_ALIGN 128 120 121/* 122 * This parameter controls the maximum no of times the driver will loop in 123 * the isr. Minimum Value = 1 124 */ 125#define MAX_LOOP 10 126 127/* 128 * This parameter controls the duration of transmit watchdog timer. 129 */ 130#define IXGBE_TX_TIMEOUT 5 /* set to 5 seconds */ 131 132/* 133 * This parameters control when the driver calls the routine to reclaim 134 * transmit descriptors. 135 */ 136#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 137#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 138 139#define IXGBE_MAX_FRAME_SIZE 0x3F00 140 141/* Flow control constants */ 142#define IXGBE_FC_PAUSE 0x680 143#define IXGBE_FC_HI 0x20000 144#define IXGBE_FC_LO 0x10000 145 146/* Defines for printing debug information */ 147#define DEBUG_INIT 0 148#define DEBUG_IOCTL 0 149#define DEBUG_HW 0 150 151#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 152#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 153#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 154#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 155#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 156#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 157#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 158#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 159#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 160 161#define MAX_NUM_MULTICAST_ADDRESSES 128 162#define IXGBE_MAX_SCATTER 100 163#define MSIX_82598_BAR 3 164#define MSIX_82599_BAR 4 165#define IXGBE_TSO_SIZE 65535 166#define IXGBE_TX_BUFFER_SIZE ((u32) 1514) 167#define IXGBE_RX_HDR 128 168#define CSUM_OFFLOAD 7 /* Bits in csum flags */ 169 170/* The number of MSIX messages the 82598 supports */ 171#define IXGBE_MSGS 18 172 173/* For 6.X code compatibility */ 174#if __FreeBSD_version < 700000 175#define ETHER_BPF_MTAP BPF_MTAP 176#define CSUM_TSO 0 177#define IFCAP_TSO4 0 178#define FILTER_STRAY 179#define FILTER_HANDLED 180#endif 181 182/* 183 * Interrupt Moderation parameters 184 */ 185#define IXGBE_LOW_LATENCY 128 186#define IXGBE_AVE_LATENCY 400 187#define IXGBE_BULK_LATENCY 1200 188#define IXGBE_LINK_ITR 2000 189 190/* Header split args for get_bug */ 191#define IXGBE_CLEAN_HDR 1 192#define IXGBE_CLEAN_PKT 2 193#define IXGBE_CLEAN_ALL 3 194 195/* Used for auto RX queue configuration */ 196extern int mp_ncpus; 197 198/* 199 ***************************************************************************** 200 * vendor_info_array 201 * 202 * This array contains the list of Subvendor/Subdevice IDs on which the driver 203 * should load. 204 * 205 ***************************************************************************** 206 */ 207typedef struct _ixgbe_vendor_info_t { 208 unsigned int vendor_id; 209 unsigned int device_id; 210 unsigned int subvendor_id; 211 unsigned int subdevice_id; 212 unsigned int index; 213} ixgbe_vendor_info_t; 214 215 216struct ixgbe_tx_buf { 217 struct mbuf *m_head; 218 bus_dmamap_t map; 219}; 220 221struct ixgbe_rx_buf { 222 struct mbuf *m_head; 223 struct mbuf *m_pack; 224 bus_dmamap_t map; 225}; 226 227/* 228 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 229 */ 230struct ixgbe_dma_alloc { 231 bus_addr_t dma_paddr; 232 caddr_t dma_vaddr; 233 bus_dma_tag_t dma_tag; 234 bus_dmamap_t dma_map; 235 bus_dma_segment_t dma_seg; 236 bus_size_t dma_size; 237 int dma_nseg; 238}; 239 240/* 241 * The transmit ring, one per tx queue 242 */ 243struct tx_ring { 244 struct adapter *adapter; 245 struct mtx tx_mtx; 246 u32 me; 247 u32 msix; 248 u32 eims; 249 u32 watchdog_timer; 250 union ixgbe_adv_tx_desc *tx_base; 251 volatile u32 tx_hwb; 252 struct ixgbe_dma_alloc txdma; 253 struct task tx_task; 254 struct taskqueue *tq; 255 u32 next_avail_tx_desc; 256 u32 next_tx_to_clean; 257 struct ixgbe_tx_buf *tx_buffers; 258 volatile u16 tx_avail; 259 u32 txd_cmd; 260 bus_dma_tag_t txtag; 261 char mtx_name[16]; 262 /* Soft Stats */ 263 u32 no_tx_desc_avail; 264 u32 no_tx_desc_late; 265 u64 tx_irq; 266 u64 total_packets; 267}; 268 269 270/* 271 * The Receive ring, one per rx queue 272 */ 273struct rx_ring { 274 struct adapter *adapter; 275 struct mtx rx_mtx; 276 u32 me; 277 u32 msix; 278 u32 eims; 279 u32 payload; 280 struct task rx_task; 281 struct taskqueue *tq; 282 union ixgbe_adv_rx_desc *rx_base; 283 struct ixgbe_dma_alloc rxdma; 284 struct lro_ctrl lro; 285 unsigned int last_cleaned; 286 unsigned int next_to_check; 287 struct ixgbe_rx_buf *rx_buffers; 288 bus_dma_tag_t rxtag; 289 bus_dmamap_t spare_map; 290 struct mbuf *fmp; 291 struct mbuf *lmp; 292 char mtx_name[16]; 293 294 u32 bytes; /* Used for AIM calc */ 295 u32 eitr_setting; 296 297 /* Soft stats */ 298 u64 rx_irq; 299 u64 rx_split_packets; 300 u64 rx_packets; 301 u64 rx_bytes; 302}; 303 304/* Our adapter structure */ 305struct adapter { 306 struct ifnet *ifp; 307 struct ixgbe_hw hw; 308 309 struct ixgbe_osdep osdep; 310 struct device *dev; 311 312 struct resource *pci_mem; 313 struct resource *msix_mem; 314 315 /* 316 * Interrupt resources: 317 * Oplin has 20 MSIX messages 318 * so allocate that for now. 319 */ 320 void *tag[IXGBE_MSGS]; 321 struct resource *res[IXGBE_MSGS]; 322 int rid[IXGBE_MSGS]; 323 324 struct ifmedia media; 325 struct callout timer; 326 int msix; 327 int if_flags; 328 329 struct mtx core_mtx; 330 331 /* Info about the board itself */ 332 u32 part_num; 333 u32 optics; 334 bool link_active; 335 u16 max_frame_size; 336 u32 link_speed; 337 u32 linkvec; 338 u32 tx_int_delay; 339 u32 tx_abs_int_delay; 340 u32 rx_int_delay; 341 u32 rx_abs_int_delay; 342 343 /* Mbuf cluster size */ 344 u32 rx_mbuf_sz; 345 346 /* Check for missing optics */ 347 bool sfp_probe; 348 349 /* 350 * Transmit rings: 351 * Allocated at run time, an array of rings. 352 */ 353 struct tx_ring *tx_rings; 354 int num_tx_desc; 355 int num_tx_queues; 356 357 /* 358 * Receive rings: 359 * Allocated at run time, an array of rings. 360 */ 361 struct rx_ring *rx_rings; 362 int num_rx_desc; 363 int num_rx_queues; 364 u32 rx_mask; 365 u32 rx_process_limit; 366 367 /* Misc stats maintained by the driver */ 368 unsigned long dropped_pkts; 369 unsigned long mbuf_defrag_failed; 370 unsigned long mbuf_header_failed; 371 unsigned long mbuf_packet_failed; 372 unsigned long no_tx_map_avail; 373 unsigned long no_tx_dma_setup; 374 unsigned long watchdog_events; 375 unsigned long tso_tx; 376 unsigned long link_irq; 377 378 struct ixgbe_hw_stats stats; 379}; 380 381#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 382 mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 383#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 384#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 385#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 386#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 387#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 388#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 389#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 390#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 391#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 392#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 393#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 394 395 396#endif /* _IXGBE_H_ */ 397