ixgbe.h revision 181003 
1/******************************************************************************
2
3  Copyright (c) 2001-2008, Intel Corporation
4  All rights reserved.
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10      this list of conditions and the following disclaimer.
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32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe.h 181003 2008-07-30 18:15:18Z jfv $*/
34
35#ifndef _IXGBE_H_
36#define _IXGBE_H_
37
38
39#include <sys/param.h>
40#include <sys/systm.h>
41#include <sys/mbuf.h>
42#include <sys/protosw.h>
43#include <sys/socket.h>
44#include <sys/malloc.h>
45#include <sys/kernel.h>
46#include <sys/module.h>
47#include <sys/sockio.h>
48
49#include <net/if.h>
50#include <net/if_arp.h>
51#include <net/bpf.h>
52#include <net/ethernet.h>
53#include <net/if_dl.h>
54#include <net/if_media.h>
55
56#include <net/bpf.h>
57#include <net/if_types.h>
58#include <net/if_vlan_var.h>
59
60#include <netinet/in_systm.h>
61#include <netinet/in.h>
62#include <netinet/if_ether.h>
63#include <netinet/ip.h>
64#include <netinet/ip6.h>
65#include <netinet/tcp.h>
66#include <netinet/tcp_lro.h>
67#include <netinet/udp.h>
68
69#include <machine/in_cksum.h>
70
71#include <sys/bus.h>
72#include <machine/bus.h>
73#include <sys/rman.h>
74#include <machine/resource.h>
75#include <vm/vm.h>
76#include <vm/pmap.h>
77#include <machine/clock.h>
78#include <dev/pci/pcivar.h>
79#include <dev/pci/pcireg.h>
80#include <sys/proc.h>
81#include <sys/sysctl.h>
82#include <sys/endian.h>
83#include <sys/taskqueue.h>
84#include <sys/pcpu.h>
85
86#include "ixgbe_api.h"
87
88/* Tunables */
89
90/*
91 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
92 * number of transmit descriptors allocated by the driver. Increasing this
93 * value allows the driver to queue more transmits. Each descriptor is 16
94 * bytes. Performance tests have show the 2K value to be optimal for top
95 * performance.
96 */
97#define DEFAULT_TXD	256
98#define PERFORM_TXD	2048
99#define MAX_TXD		4096
100#define MIN_TXD		64
101
102/*
103 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
104 * number of receive descriptors allocated for each RX queue. Increasing this
105 * value allows the driver to buffer more incoming packets. Each descriptor
106 * is 16 bytes.  A receive buffer is also allocated for each descriptor.
107 *
108 * Note: with 8 rings and a dual port card, it is possible to bump up
109 *	against the system mbuf pool limit, you can tune nmbclusters
110 *	to adjust for this.
111 */
112#define DEFAULT_RXD	256
113#define PERFORM_RXD	2048
114#define MAX_RXD		4096
115#define MIN_RXD		64
116
117/* Alignment for rings */
118#define DBA_ALIGN	128
119
120/*
121 * This parameter controls the maximum no of times the driver will loop in
122 * the isr. Minimum Value = 1
123 */
124#define MAX_INTR	10
125
126/*
127 * This parameter controls the duration of transmit watchdog timer.
128 */
129#define IXGBE_TX_TIMEOUT                   5	/* set to 5 seconds */
130
131/*
132 * This parameters control when the driver calls the routine to reclaim
133 * transmit descriptors.
134 */
135#define IXGBE_TX_CLEANUP_THRESHOLD	(adapter->num_tx_desc / 8)
136#define IXGBE_TX_OP_THRESHOLD		(adapter->num_tx_desc / 32)
137
138#define IXGBE_MAX_FRAME_SIZE	0x3F00
139
140/* Flow control constants */
141#define IXGBE_FC_PAUSE		0x680
142#define IXGBE_FC_HI		0x20000
143#define IXGBE_FC_LO		0x10000
144
145/* Defines for printing debug information */
146#define DEBUG_INIT  0
147#define DEBUG_IOCTL 0
148#define DEBUG_HW    0
149
150#define INIT_DEBUGOUT(S)            if (DEBUG_INIT)  printf(S "\n")
151#define INIT_DEBUGOUT1(S, A)        if (DEBUG_INIT)  printf(S "\n", A)
152#define INIT_DEBUGOUT2(S, A, B)     if (DEBUG_INIT)  printf(S "\n", A, B)
153#define IOCTL_DEBUGOUT(S)           if (DEBUG_IOCTL) printf(S "\n")
154#define IOCTL_DEBUGOUT1(S, A)       if (DEBUG_IOCTL) printf(S "\n", A)
155#define IOCTL_DEBUGOUT2(S, A, B)    if (DEBUG_IOCTL) printf(S "\n", A, B)
156#define HW_DEBUGOUT(S)              if (DEBUG_HW) printf(S "\n")
157#define HW_DEBUGOUT1(S, A)          if (DEBUG_HW) printf(S "\n", A)
158#define HW_DEBUGOUT2(S, A, B)       if (DEBUG_HW) printf(S "\n", A, B)
159
160#define MAX_NUM_MULTICAST_ADDRESSES     128
161#define IXGBE_MAX_SCATTER		100
162#define IXGBE_MSIX_BAR			3
163#define IXGBE_TSO_SIZE			65535
164#define IXGBE_TX_BUFFER_SIZE		((u32) 1514)
165#define IXGBE_RX_HDR_SIZE		((u32) 256)
166#define CSUM_OFFLOAD			7	/* Bits in csum flags */
167
168/* The number of MSIX messages the 82598 supports */
169#define IXGBE_MSGS			18
170
171/* For 6.X code compatibility */
172#if __FreeBSD_version < 700000
173#define ETHER_BPF_MTAP		BPF_MTAP
174#define CSUM_TSO		0
175#define IFCAP_TSO4		0
176#define FILTER_STRAY
177#define FILTER_HANDLED
178#endif
179
180/*
181 * Interrupt Moderation parameters
182 * 	for now we hardcode, later
183 *	it would be nice to do dynamic
184 */
185#define MAX_IRQ_SEC	8000
186#define DEFAULT_ITR	1000000000/(MAX_IRQ_SEC * 256)
187#define LINK_ITR	1000000000/(1950 * 256)
188
189/* Used for auto RX queue configuration */
190extern int mp_ncpus;
191
192/*
193 * ******************************************************************************
194 * vendor_info_array
195 *
196 * This array contains the list of Subvendor/Subdevice IDs on which the driver
197 * should load.
198 *
199*****************************************************************************
200 */
201typedef struct _ixgbe_vendor_info_t {
202	unsigned int    vendor_id;
203	unsigned int    device_id;
204	unsigned int    subvendor_id;
205	unsigned int    subdevice_id;
206	unsigned int    index;
207}               ixgbe_vendor_info_t;
208
209
210struct ixgbe_tx_buf {
211	struct mbuf	*m_head;
212	bus_dmamap_t	map;
213};
214
215struct ixgbe_rx_buf {
216	struct mbuf	*m_head;
217	boolean_t	bigbuf;
218	/* one small and one large map */
219	bus_dmamap_t	map[2];
220};
221
222/*
223 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free.
224 */
225struct ixgbe_dma_alloc {
226	bus_addr_t		dma_paddr;
227	caddr_t			dma_vaddr;
228	bus_dma_tag_t		dma_tag;
229	bus_dmamap_t		dma_map;
230	bus_dma_segment_t	dma_seg;
231	bus_size_t		dma_size;
232	int			dma_nseg;
233};
234
235/*
236 * The transmit ring, one per tx queue
237 */
238struct tx_ring {
239        struct adapter		*adapter;
240	struct mtx		tx_mtx;
241	u32			me;
242	u32			msix;
243	u32			eims;
244	u32			watchdog_timer;
245	union ixgbe_adv_tx_desc	*tx_base;
246	volatile u32		tx_hwb;
247	struct ixgbe_dma_alloc	txdma;
248	struct task     	tx_task;
249	struct taskqueue	*tq;
250	u32			next_avail_tx_desc;
251	u32			next_tx_to_clean;
252	struct ixgbe_tx_buf	*tx_buffers;
253	volatile u16		tx_avail;
254	u32			txd_cmd;
255	bus_dma_tag_t		txtag;
256	/* Soft Stats */
257	u32			no_tx_desc_avail;
258	u32			no_tx_desc_late;
259	u64			tx_irq;
260	u64			tx_packets;
261};
262
263
264/*
265 * The Receive ring, one per rx queue
266 */
267struct rx_ring {
268        struct adapter		*adapter;
269	struct mtx		rx_mtx;
270	u32			me;
271	u32			msix;
272	u32			eims;
273	u32			payload;
274	struct task     	rx_task;
275	struct taskqueue	*tq;
276	union ixgbe_adv_rx_desc	*rx_base;
277	struct ixgbe_dma_alloc	rxdma;
278	struct lro_ctrl		lro;
279        unsigned int		last_cleaned;
280        unsigned int		next_to_check;
281	struct ixgbe_rx_buf	*rx_buffers;
282	bus_dma_tag_t		rxtag[2];
283	bus_dmamap_t		spare_map[2];
284	struct mbuf		*fmp;
285	struct mbuf		*lmp;
286	/* Soft stats */
287	u64			rx_irq;
288	u64			packet_count;
289	u64 			byte_count;
290};
291
292/* Our adapter structure */
293struct adapter {
294	struct ifnet	*ifp;
295	struct ixgbe_hw	hw;
296
297	/* FreeBSD operating-system-specific structures */
298	struct ixgbe_osdep	osdep;
299	struct device	*dev;
300
301	struct resource	*pci_mem;
302	struct resource	*msix_mem;
303
304	/*
305	 * Interrupt resources:
306	 *  Oplin has 20 MSIX messages
307	 *  so allocate that for now.
308	 */
309	void		*tag[IXGBE_MSGS];
310	struct resource *res[IXGBE_MSGS];
311	int		rid[IXGBE_MSGS];
312	u32		eims_mask;
313
314	struct ifmedia	media;
315	struct callout	timer;
316	int		msix;
317	int		if_flags;
318
319	struct mtx	core_mtx;
320
321	/* Legacy Fast Intr handling */
322	struct task     link_task;
323
324	/* Info about the board itself */
325	u32		part_num;
326	bool		link_active;
327	u16		max_frame_size;
328	u32		link_speed;
329	u32		tx_int_delay;
330	u32		tx_abs_int_delay;
331	u32		rx_int_delay;
332	u32		rx_abs_int_delay;
333
334	/* Indicates the cluster size to use */
335	bool		bigbufs;
336
337	/*
338	 * Transmit rings:
339	 *	Allocated at run time, an array of rings.
340	 */
341	struct tx_ring	*tx_rings;
342	int		num_tx_desc;
343	int		num_tx_queues;
344
345	/*
346	 * Receive rings:
347	 *	Allocated at run time, an array of rings.
348	 */
349	struct rx_ring	*rx_rings;
350	int		num_rx_desc;
351	int		num_rx_queues;
352	u32		rx_process_limit;
353
354	eventhandler_tag	vlan_attach;
355	eventhandler_tag	vlan_detach;
356
357	/* Misc stats maintained by the driver */
358	unsigned long   dropped_pkts;
359	unsigned long   mbuf_alloc_failed;
360	unsigned long   mbuf_cluster_failed;
361	unsigned long   no_tx_map_avail;
362	unsigned long   no_tx_dma_setup;
363	unsigned long   watchdog_events;
364	unsigned long   tso_tx;
365	unsigned long	linkvec;
366	unsigned long	link_irq;
367
368	struct ixgbe_hw_stats stats;
369};
370
371#define IXGBE_CORE_LOCK_INIT(_sc, _name) \
372        mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF)
373#define IXGBE_CORE_LOCK_DESTROY(_sc)      mtx_destroy(&(_sc)->core_mtx)
374#define IXGBE_TX_LOCK_DESTROY(_sc)                mtx_destroy(&(_sc)->tx_mtx)
375#define IXGBE_RX_LOCK_DESTROY(_sc)                mtx_destroy(&(_sc)->rx_mtx)
376#define IXGBE_CORE_LOCK(_sc)              mtx_lock(&(_sc)->core_mtx)
377#define IXGBE_TX_LOCK(_sc)                        mtx_lock(&(_sc)->tx_mtx)
378#define IXGBE_RX_LOCK(_sc)                        mtx_lock(&(_sc)->rx_mtx)
379#define IXGBE_CORE_UNLOCK(_sc)            mtx_unlock(&(_sc)->core_mtx)
380#define IXGBE_TX_UNLOCK(_sc)              mtx_unlock(&(_sc)->tx_mtx)
381#define IXGBE_RX_UNLOCK(_sc)              mtx_unlock(&(_sc)->rx_mtx)
382#define IXGBE_CORE_LOCK_ASSERT(_sc)       mtx_assert(&(_sc)->core_mtx, MA_OWNED)
383#define IXGBE_TX_LOCK_ASSERT(_sc)         mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
384
385
386#endif /* _IXGBE_H_ */
387