1252867Sdelphij/*- 2252867Sdelphij * Copyright (c) 2011 HighPoint Technologies, Inc. 3252867Sdelphij * All rights reserved. 4252867Sdelphij * 5252867Sdelphij * Redistribution and use in source and binary forms, with or without 6252867Sdelphij * modification, are permitted provided that the following conditions 7252867Sdelphij * are met: 8252867Sdelphij * 1. Redistributions of source code must retain the above copyright 9252867Sdelphij * notice, this list of conditions and the following disclaimer. 10252867Sdelphij * 2. Redistributions in binary form must reproduce the above copyright 11252867Sdelphij * notice, this list of conditions and the following disclaimer in the 12252867Sdelphij * documentation and/or other materials provided with the distribution. 13252867Sdelphij * 14252867Sdelphij * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15252867Sdelphij * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16252867Sdelphij * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17252867Sdelphij * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18252867Sdelphij * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19252867Sdelphij * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20252867Sdelphij * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21252867Sdelphij * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22252867Sdelphij * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23252867Sdelphij * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24252867Sdelphij * SUCH DAMAGE. 25252867Sdelphij * 26252867Sdelphij * $FreeBSD$ 27252867Sdelphij */ 28252867Sdelphij 29252867Sdelphij#include <dev/hptnr/hptnr_config.h> 30252867Sdelphij 31252867Sdelphij#ifndef HPT_INTF_H 32252867Sdelphij#define HPT_INTF_H 33252867Sdelphij 34252867Sdelphij#if defined(__BIG_ENDIAN__)&&!defined(__BIG_ENDIAN_BITFIELD) 35252867Sdelphij#define __BIG_ENDIAN_BITFIELD 36252867Sdelphij#endif 37252867Sdelphij 38252867Sdelphij#ifdef __cplusplus 39252867Sdelphijextern "C" { 40252867Sdelphij#endif 41252867Sdelphij 42252867Sdelphij#ifndef __GNUC__ 43252867Sdelphij#define __attribute__(x) 44252867Sdelphij#endif 45252867Sdelphij 46252867Sdelphij#pragma pack(1) 47252867Sdelphij 48252867Sdelphij/* 49252867Sdelphij * Version of this interface. 50252867Sdelphij * The user mode application must first issue a hpt_get_version() call to 51252867Sdelphij * check HPT_INTERFACE_VERSION. When an utility using newer version interface 52252867Sdelphij * is used with old version drivers, it must call only the functions that 53252867Sdelphij * driver supported. 54252867Sdelphij * A new version interface should only add ioctl functions; it should implement 55252867Sdelphij * all old version functions without change their definition. 56252867Sdelphij */ 57252867Sdelphij#define __this_HPT_INTERFACE_VERSION 0x02010000 58252867Sdelphij 59252867Sdelphij#ifndef HPT_INTERFACE_VERSION 60252867Sdelphij#error "You must define HPT_INTERFACE_VERSION you implemented" 61252867Sdelphij#endif 62252867Sdelphij 63252867Sdelphij#if HPT_INTERFACE_VERSION > __this_HPT_INTERFACE_VERSION 64252867Sdelphij#error "HPT_INTERFACE_VERSION is invalid" 65252867Sdelphij#endif 66252867Sdelphij 67252867Sdelphij/* 68252867Sdelphij * DEFINITION 69252867Sdelphij * Logical device --- a device that can be accessed by OS. 70252867Sdelphij * Physical device --- device attached to the controller. 71252867Sdelphij * A logical device can be simply a physical device. 72252867Sdelphij * 73252867Sdelphij * Each logical and physical device has a 32bit ID. GUI will use this ID 74252867Sdelphij * to identify devices. 75252867Sdelphij * 1. The ID must be unique. 76252867Sdelphij * 2. The ID must be immutable. Once an ID is assigned to a device, it 77252867Sdelphij * must not change when system is running and the device exists. 78252867Sdelphij * 3. The ID of logical device must be NOT reusable. If a device is 79252867Sdelphij * removed, other newly created logical device must not use the same ID. 80252867Sdelphij * 4. The ID must not be zero or 0xFFFFFFFF. 81252867Sdelphij */ 82252867Sdelphijtypedef HPT_U32 DEVICEID; 83252867Sdelphij 84252867Sdelphij/* 85252867Sdelphij * logical device type. 86252867Sdelphij * Identify array (logical device) and physical device. 87252867Sdelphij */ 88252867Sdelphij#define LDT_ARRAY 1 89252867Sdelphij#define LDT_DEVICE 2 90252867Sdelphij 91252867Sdelphij/* 92252867Sdelphij * Array types 93252867Sdelphij * GUI will treat all array as 1-level RAID. No RAID0/1 or RAID1/0. 94252867Sdelphij * A RAID0/1 device is type AT_RAID1. A RAID1/0 device is type AT_RAID0. 95252867Sdelphij * Their members may be another array of type RAID0 or RAID1. 96252867Sdelphij */ 97252867Sdelphij#define AT_UNKNOWN 0 98252867Sdelphij#define AT_RAID0 1 99252867Sdelphij#define AT_RAID1 2 100252867Sdelphij#define AT_RAID5 3 101252867Sdelphij#define AT_RAID6 4 102252867Sdelphij#define AT_RAID3 5 103252867Sdelphij#define AT_RAID4 6 104252867Sdelphij#define AT_JBOD 7 105252867Sdelphij#define AT_RAID1E 8 106252867Sdelphij 107252867Sdelphij/* 108252867Sdelphij * physical device type 109252867Sdelphij */ 110252867Sdelphij#define PDT_UNKNOWN 0 111252867Sdelphij#define PDT_HARDDISK 1 112252867Sdelphij#define PDT_CDROM 2 113252867Sdelphij#define PDT_TAPE 3 114252867Sdelphij 115252867Sdelphij/* 116252867Sdelphij * Some constants. 117252867Sdelphij */ 118252867Sdelphij#define MAX_NAME_LENGTH 36 119252867Sdelphij#define MAX_ARRAYNAME_LEN 16 120252867Sdelphij 121252867Sdelphij#define MAX_ARRAY_MEMBERS_V1 8 122252867Sdelphij 123252867Sdelphij#ifndef MAX_ARRAY_MEMBERS_V2 124252867Sdelphij#define MAX_ARRAY_MEMBERS_V2 16 125252867Sdelphij#endif 126252867Sdelphij 127252867Sdelphij#ifndef MAX_ARRAY_MEMBERS_V3 128252867Sdelphij#define MAX_ARRAY_MEMBERS_V3 64 129252867Sdelphij#endif 130252867Sdelphij 131252867Sdelphij/* keep definition for source code compatiblity */ 132252867Sdelphij#define MAX_ARRAY_MEMBERS MAX_ARRAY_MEMBERS_V1 133252867Sdelphij 134252867Sdelphij/* 135252867Sdelphij * io commands 136252867Sdelphij * GUI use these commands to do IO on logical/physical devices. 137252867Sdelphij */ 138252867Sdelphij#define IO_COMMAND_READ 1 139252867Sdelphij#define IO_COMMAND_WRITE 2 140252867Sdelphij 141252867Sdelphij 142252867Sdelphij 143252867Sdelphij/* 144252867Sdelphij * array flags 145252867Sdelphij */ 146252867Sdelphij#define ARRAY_FLAG_DISABLED 0x00000001 /* The array is disabled */ 147252867Sdelphij#define ARRAY_FLAG_NEEDBUILDING 0x00000002 /* array data need to be rebuilt */ 148252867Sdelphij#define ARRAY_FLAG_REBUILDING 0x00000004 /* array is in rebuilding process */ 149252867Sdelphij#define ARRAY_FLAG_BROKEN 0x00000008 /* broken but may still working */ 150252867Sdelphij#define ARRAY_FLAG_BOOTDISK 0x00000010 /* array has a active partition */ 151252867Sdelphij 152252867Sdelphij#define ARRAY_FLAG_BOOTMARK 0x00000040 /* array has boot mark set */ 153252867Sdelphij#define ARRAY_FLAG_NEED_AUTOREBUILD 0x00000080 /* auto-rebuild should start */ 154252867Sdelphij#define ARRAY_FLAG_VERIFYING 0x00000100 /* is being verified */ 155252867Sdelphij#define ARRAY_FLAG_INITIALIZING 0x00000200 /* is being initialized */ 156252867Sdelphij#define ARRAY_FLAG_TRANSFORMING 0x00000400 /* tranform in progress */ 157252867Sdelphij#define ARRAY_FLAG_NEEDTRANSFORM 0x00000800 /* array need tranform */ 158252867Sdelphij#define ARRAY_FLAG_NEEDINITIALIZING 0x00001000 /* the array's initialization hasn't finished*/ 159252867Sdelphij#define ARRAY_FLAG_BROKEN_REDUNDANT 0x00002000 /* broken but redundant (raid6) */ 160252867Sdelphij#define ARRAY_FLAG_RAID15PLUS 0x80000000 /* display this RAID 1 as RAID 1.5 */ 161252867Sdelphij 162252867Sdelphij#define ARRAY_FLAG_ZERO_STARTING 0x40000000 /* start lba of all members of this array is 0 */ 163252867Sdelphij 164252867Sdelphij/* 165252867Sdelphij * device flags 166252867Sdelphij */ 167252867Sdelphij#define DEVICE_FLAG_DISABLED 0x00000001 /* device is disabled */ 168252867Sdelphij#define DEVICE_FLAG_BOOTDISK 0x00000002 /* disk has a active partition */ 169252867Sdelphij#define DEVICE_FLAG_BOOTMARK 0x00000004 /* disk has boot mark set */ 170252867Sdelphij#define DEVICE_FLAG_WITH_601 0x00000008 /* has HPT601 connected */ 171252867Sdelphij#define DEVICE_FLAG_SATA 0x00000010 /* SATA or SAS device */ 172252867Sdelphij#define DEVICE_FLAG_ON_PM_PORT 0x00000020 /* PM port */ 173252867Sdelphij#define DEVICE_FLAG_SAS 0x00000040 /* SAS device */ 174252867Sdelphij#define DEVICE_FLAG_IN_ENCLOSURE 0x00000080 /* PathId is enclosure# */ 175252867Sdelphij#define DEVICE_FLAG_UNINITIALIZED 0x00010000 /* device is not initialized, can't be used to create array */ 176252867Sdelphij#define DEVICE_FLAG_LEGACY 0x00020000 /* single disk & mbr contains at least one partition */ 177252867Sdelphij#define DEVICE_FLAG_BAD_SECTOR_FOUND 0x00040000 /* found bad sector on target disk, set and clear by GUI */ 178252867Sdelphij 179252867Sdelphij#define DEVICE_FLAG_IS_SPARE 0x80000000 /* is a spare disk */ 180252867Sdelphij 181252867Sdelphij 182252867Sdelphij#define DEVICE_FLAG_SSD 0x00000100 /* SSD device */ 183252867Sdelphij#define DEVICE_FLAG_3G 0x10000000 184252867Sdelphij#define DEVICE_FLAG_6G 0x20000000 185252867Sdelphij 186252867Sdelphij 187252867Sdelphij/* 188252867Sdelphij * array states used by hpt_set_array_state() 189252867Sdelphij */ 190252867Sdelphij/* old defines */ 191252867Sdelphij#define MIRROR_REBUILD_START 1 192252867Sdelphij#define MIRROR_REBUILD_ABORT 2 193252867Sdelphij#define MIRROR_REBUILD_COMPLETE 3 194252867Sdelphij/* new defines */ 195252867Sdelphij#define AS_REBUILD_START 1 196252867Sdelphij#define AS_REBUILD_ABORT 2 197252867Sdelphij#define AS_REBUILD_PAUSE AS_REBUILD_ABORT 198252867Sdelphij#define AS_REBUILD_COMPLETE 3 199252867Sdelphij#define AS_VERIFY_START 4 200252867Sdelphij#define AS_VERIFY_ABORT 5 201252867Sdelphij#define AS_VERIFY_COMPLETE 6 202252867Sdelphij#define AS_INITIALIZE_START 7 203252867Sdelphij#define AS_INITIALIZE_ABORT 8 204252867Sdelphij#define AS_INITIALIZE_COMPLETE 9 205252867Sdelphij#define AS_VERIFY_FAILED 10 206252867Sdelphij#define AS_REBUILD_STOP 11 207252867Sdelphij#define AS_SAVE_STATE 12 208252867Sdelphij#define AS_TRANSFORM_START 13 209252867Sdelphij#define AS_TRANSFORM_ABORT 14 210252867Sdelphij 211252867Sdelphij/************************************************************************ 212252867Sdelphij * ioctl code 213252867Sdelphij * It would be better if ioctl code are the same on different platforms, 214252867Sdelphij * but we must not conflict with system defined ioctl code. 215252867Sdelphij ************************************************************************/ 216252867Sdelphij#if defined(LINUX) || defined(__FreeBSD_version) || defined(linux) 217252867Sdelphij#define HPT_CTL_CODE(x) (x+0xFF00) 218252867Sdelphij#define HPT_CTL_CODE_LINUX_TO_IOP(x) ((x)-0xff00) 219252867Sdelphij#elif defined(_MS_WIN32_) || defined(WIN32) 220252867Sdelphij 221252867Sdelphij#ifndef CTL_CODE 222252867Sdelphij#define CTL_CODE( DeviceType, Function, Method, Access ) \ 223252867Sdelphij (((DeviceType) << 16) | ((Access) << 14) | ((Function) << 2) | (Method)) 224252867Sdelphij#endif 225252867Sdelphij#define HPT_CTL_CODE(x) CTL_CODE(0x370, 0x900+(x), 0, 0) 226252867Sdelphij#define HPT_CTL_CODE_WIN32_TO_IOP(x) ((((x) & 0xffff)>>2)-0x900) 227252867Sdelphij 228252867Sdelphij#else 229252867Sdelphij#define HPT_CTL_CODE(x) (x) 230252867Sdelphij#endif 231252867Sdelphij 232252867Sdelphij#define HPT_IOCTL_GET_VERSION HPT_CTL_CODE(0) 233252867Sdelphij#define HPT_IOCTL_GET_CONTROLLER_COUNT HPT_CTL_CODE(1) 234252867Sdelphij#define HPT_IOCTL_GET_CONTROLLER_INFO HPT_CTL_CODE(2) 235252867Sdelphij#define HPT_IOCTL_GET_CHANNEL_INFO HPT_CTL_CODE(3) 236252867Sdelphij#define HPT_IOCTL_GET_LOGICAL_DEVICES HPT_CTL_CODE(4) 237252867Sdelphij#define HPT_IOCTL_GET_DEVICE_INFO HPT_CTL_CODE(5) 238252867Sdelphij#define HPT_IOCTL_CREATE_ARRAY HPT_CTL_CODE(6) 239252867Sdelphij#define HPT_IOCTL_DELETE_ARRAY HPT_CTL_CODE(7) 240252867Sdelphij#define HPT_IOCTL_ARRAY_IO HPT_CTL_CODE(8) 241252867Sdelphij#define HPT_IOCTL_DEVICE_IO HPT_CTL_CODE(9) 242252867Sdelphij#define HPT_IOCTL_GET_EVENT HPT_CTL_CODE(10) 243252867Sdelphij#define HPT_IOCTL_REBUILD_MIRROR HPT_CTL_CODE(11) 244252867Sdelphij/* use HPT_IOCTL_REBUILD_DATA_BLOCK from now on */ 245252867Sdelphij#define HPT_IOCTL_REBUILD_DATA_BLOCK HPT_IOCTL_REBUILD_MIRROR 246252867Sdelphij#define HPT_IOCTL_ADD_SPARE_DISK HPT_CTL_CODE(12) 247252867Sdelphij#define HPT_IOCTL_REMOVE_SPARE_DISK HPT_CTL_CODE(13) 248252867Sdelphij#define HPT_IOCTL_ADD_DISK_TO_ARRAY HPT_CTL_CODE(14) 249252867Sdelphij#define HPT_IOCTL_SET_ARRAY_STATE HPT_CTL_CODE(15) 250252867Sdelphij#define HPT_IOCTL_SET_ARRAY_INFO HPT_CTL_CODE(16) 251252867Sdelphij#define HPT_IOCTL_SET_DEVICE_INFO HPT_CTL_CODE(17) 252252867Sdelphij#define HPT_IOCTL_RESCAN_DEVICES HPT_CTL_CODE(18) 253252867Sdelphij#define HPT_IOCTL_GET_DRIVER_CAPABILITIES HPT_CTL_CODE(19) 254252867Sdelphij#define HPT_IOCTL_GET_601_INFO HPT_CTL_CODE(20) 255252867Sdelphij#define HPT_IOCTL_SET_601_INFO HPT_CTL_CODE(21) 256252867Sdelphij#define HPT_IOCTL_LOCK_DEVICE HPT_CTL_CODE(22) 257252867Sdelphij#define HPT_IOCTL_UNLOCK_DEVICE HPT_CTL_CODE(23) 258252867Sdelphij#define HPT_IOCTL_IDE_PASS_THROUGH HPT_CTL_CODE(24) 259252867Sdelphij#define HPT_IOCTL_VERIFY_DATA_BLOCK HPT_CTL_CODE(25) 260252867Sdelphij#define HPT_IOCTL_INITIALIZE_DATA_BLOCK HPT_CTL_CODE(26) 261252867Sdelphij#define HPT_IOCTL_ADD_DEDICATED_SPARE HPT_CTL_CODE(27) 262252867Sdelphij#define HPT_IOCTL_DEVICE_IO_EX HPT_CTL_CODE(28) 263252867Sdelphij#define HPT_IOCTL_SET_BOOT_MARK HPT_CTL_CODE(29) 264252867Sdelphij#define HPT_IOCTL_QUERY_REMOVE HPT_CTL_CODE(30) 265252867Sdelphij#define HPT_IOCTL_REMOVE_DEVICES HPT_CTL_CODE(31) 266252867Sdelphij#define HPT_IOCTL_CREATE_ARRAY_V2 HPT_CTL_CODE(32) 267252867Sdelphij#define HPT_IOCTL_GET_DEVICE_INFO_V2 HPT_CTL_CODE(33) 268252867Sdelphij#define HPT_IOCTL_SET_DEVICE_INFO_V2 HPT_CTL_CODE(34) 269252867Sdelphij#define HPT_IOCTL_REBUILD_DATA_BLOCK_V2 HPT_CTL_CODE(35) 270252867Sdelphij#define HPT_IOCTL_VERIFY_DATA_BLOCK_V2 HPT_CTL_CODE(36) 271252867Sdelphij#define HPT_IOCTL_INITIALIZE_DATA_BLOCK_V2 HPT_CTL_CODE(37) 272252867Sdelphij#define HPT_IOCTL_LOCK_DEVICE_V2 HPT_CTL_CODE(38) 273252867Sdelphij#define HPT_IOCTL_DEVICE_IO_V2 HPT_CTL_CODE(39) 274252867Sdelphij#define HPT_IOCTL_DEVICE_IO_EX_V2 HPT_CTL_CODE(40) 275252867Sdelphij#define HPT_IOCTL_CREATE_TRANSFORM HPT_CTL_CODE(41) 276252867Sdelphij#define HPT_IOCTL_STEP_TRANSFORM HPT_CTL_CODE(42) 277252867Sdelphij#define HPT_IOCTL_SET_VDEV_INFO HPT_CTL_CODE(43) 278252867Sdelphij#define HPT_IOCTL_CALC_MAX_CAPACITY HPT_CTL_CODE(44) 279252867Sdelphij#define HPT_IOCTL_INIT_DISKS HPT_CTL_CODE(45) 280252867Sdelphij#define HPT_IOCTL_GET_DEVICE_INFO_V3 HPT_CTL_CODE(46) 281252867Sdelphij#define HPT_IOCTL_GET_CONTROLLER_INFO_V2 HPT_CTL_CODE(47) 282252867Sdelphij#define HPT_IOCTL_I2C_TRANSACTION HPT_CTL_CODE(48) 283252867Sdelphij#define HPT_IOCTL_GET_PARAMETER_LIST HPT_CTL_CODE(49) 284252867Sdelphij#define HPT_IOCTL_GET_PARAMETER HPT_CTL_CODE(50) 285252867Sdelphij#define HPT_IOCTL_SET_PARAMETER HPT_CTL_CODE(51) 286252867Sdelphij#define HPT_IOCTL_GET_DRIVER_CAPABILITIES_V2 HPT_CTL_CODE(52) 287252867Sdelphij#define HPT_IOCTL_GET_CHANNEL_INFO_V2 HPT_CTL_CODE(53) 288252867Sdelphij#define HPT_IOCTL_GET_CONTROLLER_INFO_V3 HPT_CTL_CODE(54) 289252867Sdelphij#define HPT_IOCTL_GET_DEVICE_INFO_V4 HPT_CTL_CODE(55) 290252867Sdelphij#define HPT_IOCTL_CREATE_ARRAY_V3 HPT_CTL_CODE(56) 291252867Sdelphij#define HPT_IOCTL_CREATE_TRANSFORM_V2 HPT_CTL_CODE(57) 292252867Sdelphij#define HPT_IOCTL_CALC_MAX_CAPACITY_V2 HPT_CTL_CODE(58) 293252867Sdelphij#define HPT_IOCTL_SCSI_PASSTHROUGH HPT_CTL_CODE(59) 294252867Sdelphij#define HPT_IOCTL_GET_PHYSICAL_DEVICES HPT_CTL_CODE(60) 295252867Sdelphij#define HPT_IOCTL_GET_ENCLOSURE_COUNT HPT_CTL_CODE(61) 296252867Sdelphij#define HPT_IOCTL_GET_ENCLOSURE_INFO HPT_CTL_CODE(62) 297252867Sdelphij#define HPT_IOCTL_GET_PERFMON_STATUS HPT_CTL_CODE(63) 298252867Sdelphij#define HPT_IOCTL_SET_PERFMON_STATUS HPT_CTL_CODE(64) 299252867Sdelphij#define HPT_IOCTL_GET_PERFMON_DATA HPT_CTL_CODE(65) 300252867Sdelphij#define HPT_IOCTL_IDE_PASS_THROUGH_V2 HPT_CTL_CODE(66) 301252867Sdelphij#define HPT_IOCTL_GET_ENCLOSURE_INFO_V2 HPT_CTL_CODE(67) 302252867Sdelphij#define HPT_IOCTL_GET_ENCLOSURE_INFO_V3 HPT_CTL_CODE(68) 303252867Sdelphij#define HPT_IOCTL_ACCESS_CONFIG_REG HPT_CTL_CODE(69) 304252867Sdelphij 305252867Sdelphij#define HPT_IOCTL_GET_ENCLOSURE_INFO_V4 HPT_CTL_CODE(70) 306252867Sdelphij#define HPT_IOCTL_GET_ENCLOSURE_ELEMENT_INFO HPT_CTL_CODE(71) 307252867Sdelphij#define HPT_IOCTL_DUMP_METADATA HPT_CTL_CODE(72) 308252867Sdelphij#define HPT_IOCTL_GET_CONTROLLER_INFO_V2_EXT HPT_CTL_CODE(73) 309252867Sdelphij 310252867Sdelphij 311252867Sdelphij#define HPT_IOCTL_GET_CONTROLLER_IDS HPT_CTL_CODE(100) 312252867Sdelphij#define HPT_IOCTL_GET_DCB HPT_CTL_CODE(101) 313252867Sdelphij 314252867Sdelphij#define HPT_IOCTL_EPROM_IO HPT_CTL_CODE(102) 315252867Sdelphij#define HPT_IOCTL_GET_CONTROLLER_VENID HPT_CTL_CODE(103) 316252867Sdelphij 317252867Sdelphij 318252867Sdelphij#define HPT_IOCTL_GET_DRIVER_CAPABILITIES_CC HPT_CTL_CODE(200) 319252867Sdelphij#define HPT_IOCTL_GET_CCS_INFO HPT_CTL_CODE(201) 320252867Sdelphij#define HPT_IOCTL_CREATE_CC HPT_CTL_CODE(202) 321252867Sdelphij#define HPT_IOCTL_DELETE_CC HPT_CTL_CODE(203) 322252867Sdelphij#define HPT_IOCTL_REENABLE_ARRAY HPT_CTL_CODE(204) 323252867Sdelphij 324252867Sdelphij/************************************************************************ 325252867Sdelphij * shared data structures 326252867Sdelphij ************************************************************************/ 327252867Sdelphij 328252867Sdelphij/* 329252867Sdelphij * Chip Type 330252867Sdelphij */ 331252867Sdelphij#define CHIP_TYPE_HPT366 1 332252867Sdelphij#define CHIP_TYPE_HPT368 2 333252867Sdelphij#define CHIP_TYPE_HPT370 3 334252867Sdelphij#define CHIP_TYPE_HPT370A 4 335252867Sdelphij#define CHIP_TYPE_HPT370B 5 336252867Sdelphij#define CHIP_TYPE_HPT374 6 337252867Sdelphij#define CHIP_TYPE_HPT372 7 338252867Sdelphij#define CHIP_TYPE_HPT372A 8 339252867Sdelphij#define CHIP_TYPE_HPT302 9 340252867Sdelphij#define CHIP_TYPE_HPT371 10 341252867Sdelphij#define CHIP_TYPE_HPT372N 11 342252867Sdelphij#define CHIP_TYPE_HPT302N 12 343252867Sdelphij#define CHIP_TYPE_HPT371N 13 344252867Sdelphij#define CHIP_TYPE_SI3112A 14 345252867Sdelphij#define CHIP_TYPE_ICH5 15 346252867Sdelphij#define CHIP_TYPE_ICH5R 16 347252867Sdelphij#define CHIP_TYPE_MV50XX 20 348252867Sdelphij#define CHIP_TYPE_MV60X1 21 349252867Sdelphij#define CHIP_TYPE_MV60X2 22 350252867Sdelphij#define CHIP_TYPE_MV70X2 23 351252867Sdelphij#define CHIP_TYPE_MV5182 24 352252867Sdelphij#define CHIP_TYPE_IOP331 31 353252867Sdelphij#define CHIP_TYPE_IOP333 32 354252867Sdelphij#define CHIP_TYPE_IOP341 33 355252867Sdelphij#define CHIP_TYPE_IOP348 34 356252867Sdelphij 357252867Sdelphij/* 358252867Sdelphij * Chip Flags 359252867Sdelphij */ 360252867Sdelphij#define CHIP_SUPPORT_ULTRA_66 0x20 361252867Sdelphij#define CHIP_SUPPORT_ULTRA_100 0x40 362252867Sdelphij#define CHIP_HPT3XX_DPLL_MODE 0x80 363252867Sdelphij#define CHIP_SUPPORT_ULTRA_133 0x01 364252867Sdelphij#define CHIP_SUPPORT_ULTRA_150 0x02 365252867Sdelphij#define CHIP_MASTER 0x04 366252867Sdelphij#define CHIP_SUPPORT_SATA_300 0x08 367252867Sdelphij 368252867Sdelphij#define HPT_SPIN_UP_MODE_NOSUPPORT 0 369252867Sdelphij#define HPT_SPIN_UP_MODE_FULL 1 370252867Sdelphij#define HPT_SPIN_UP_MODE_STANDBY 2 371252867Sdelphij 372252867Sdelphij#define HPT_CAP_DUMP_METADATA 0x1 373252867Sdelphij#define HPT_CAP_DISK_CHECKING 0x2 374252867Sdelphij 375252867Sdelphijtypedef struct _DRIVER_CAPABILITIES { 376252867Sdelphij HPT_U32 dwSize; 377252867Sdelphij 378252867Sdelphij HPT_U8 MaximumControllers; /* maximum controllers the driver can support */ 379252867Sdelphij HPT_U8 SupportCrossControllerRAID; /* 1-support, 0-not support */ 380252867Sdelphij HPT_U8 MinimumBlockSizeShift; /* minimum block size shift */ 381252867Sdelphij HPT_U8 MaximumBlockSizeShift; /* maximum block size shift */ 382252867Sdelphij 383252867Sdelphij HPT_U8 SupportDiskModeSetting; 384252867Sdelphij HPT_U8 SupportSparePool; 385252867Sdelphij HPT_U8 MaximumArrayNameLength; 386252867Sdelphij /* only one HPT_U8 left here! */ 387252867Sdelphij#ifdef __BIG_ENDIAN_BITFIELD 388252867Sdelphij HPT_U8 reserved: 2; 389252867Sdelphij HPT_U8 SupportPerformanceMonitor: 1; 390252867Sdelphij HPT_U8 SupportVariableSectorSize: 1; 391252867Sdelphij HPT_U8 SupportHotSwap: 1; 392252867Sdelphij HPT_U8 HighPerformanceRAID1: 1; 393252867Sdelphij HPT_U8 RebuildProcessInDriver: 1; 394252867Sdelphij HPT_U8 SupportDedicatedSpare: 1; 395252867Sdelphij#else 396252867Sdelphij HPT_U8 SupportDedicatedSpare: 1; /* call hpt_add_dedicated_spare() for dedicated spare. */ 397252867Sdelphij HPT_U8 RebuildProcessInDriver: 1; /* Windows only. used by mid layer for rebuild control. */ 398252867Sdelphij HPT_U8 HighPerformanceRAID1: 1; 399252867Sdelphij HPT_U8 SupportHotSwap: 1; 400252867Sdelphij HPT_U8 SupportVariableSectorSize: 1; 401252867Sdelphij HPT_U8 SupportPerformanceMonitor: 1; 402252867Sdelphij HPT_U8 reserved: 2; 403252867Sdelphij#endif 404252867Sdelphij 405252867Sdelphij 406252867Sdelphij HPT_U8 SupportedRAIDTypes[16]; 407252867Sdelphij /* maximum members in an array corresponding to SupportedRAIDTypes */ 408252867Sdelphij HPT_U8 MaximumArrayMembers[16]; 409252867Sdelphij} 410252867SdelphijDRIVER_CAPABILITIES, *PDRIVER_CAPABILITIES; 411252867Sdelphij 412252867Sdelphijtypedef struct _DRIVER_CAPABILITIES_V2 { 413252867Sdelphij DRIVER_CAPABILITIES v1; 414252867Sdelphij HPT_U8 SupportedCachePolicies[16]; 415252867Sdelphij HPT_U32 ConfigRegSize; /* max sectors */ 416252867Sdelphij HPT_U32 SupportDiskCachePolicy; /* disable/enable disk cache policy */ 417252867Sdelphij HPT_U32 Flags; 418252867Sdelphij HPT_U32 reserved[14]; 419252867Sdelphij} 420252867SdelphijDRIVER_CAPABILITIES_V2, *PDRIVER_CAPABILITIES_V2; 421252867Sdelphij 422252867Sdelphij/* 423252867Sdelphij * Controller information. 424252867Sdelphij */ 425252867Sdelphijtypedef struct _CONTROLLER_INFO { 426252867Sdelphij HPT_U8 ChipType; /* chip type */ 427252867Sdelphij HPT_U8 InterruptLevel; /* IRQ level */ 428252867Sdelphij HPT_U8 NumBuses; /* bus count */ 429252867Sdelphij HPT_U8 ChipFlags; 430252867Sdelphij 431252867Sdelphij HPT_U8 szProductID[MAX_NAME_LENGTH];/* product name */ 432252867Sdelphij HPT_U8 szVendorID[MAX_NAME_LENGTH]; /* vender name */ 433252867Sdelphij 434252867Sdelphij} CONTROLLER_INFO, *PCONTROLLER_INFO; 435252867Sdelphij 436252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000 437252867Sdelphijtypedef struct _CONTROLLER_INFO_V2 { 438252867Sdelphij HPT_U8 ChipType; /* chip type */ 439252867Sdelphij HPT_U8 InterruptLevel; /* IRQ level */ 440252867Sdelphij HPT_U8 NumBuses; /* bus count */ 441252867Sdelphij HPT_U8 ChipFlags; 442252867Sdelphij 443252867Sdelphij HPT_U8 szProductID[MAX_NAME_LENGTH];/* product name */ 444252867Sdelphij HPT_U8 szVendorID[MAX_NAME_LENGTH]; /* vender name */ 445252867Sdelphij 446252867Sdelphij HPT_U32 GroupId; /* low 32bit of vbus pointer the controller belongs 447252867Sdelphij * the master controller has CHIP_MASTER flag set*/ 448252867Sdelphij HPT_U8 pci_tree; 449252867Sdelphij HPT_U8 pci_bus; 450252867Sdelphij HPT_U8 pci_device; 451252867Sdelphij HPT_U8 pci_function; 452252867Sdelphij 453252867Sdelphij HPT_U32 ExFlags; 454252867Sdelphij} CONTROLLER_INFO_V2, *PCONTROLLER_INFO_V2; 455252867Sdelphij 456252867Sdelphijtypedef struct _CONTROLLER_INFO_V2_EXT { 457252867Sdelphij HPT_U8 MaxWidth; 458252867Sdelphij HPT_U8 CurrentWidth; 459252867Sdelphij HPT_U8 MaxSpeed; 460252867Sdelphij HPT_U8 CurrentSpeed; 461252867Sdelphij HPT_U8 reserve[64]; 462252867Sdelphij} CONTROLLER_INFO_V2_EXT, *PCONTROLLER_INFO_V2_EXT; 463252867Sdelphij 464252867Sdelphij 465252867Sdelphij#define CEXF_IOPModel 1 466252867Sdelphij#define CEXF_SDRAMSize 2 467252867Sdelphij#define CEXF_BatteryInstalled 4 468252867Sdelphij#define CEXF_BatteryStatus 8 469252867Sdelphij#define CEXF_BatteryVoltage 0x10 470252867Sdelphij#define CEXF_BatteryBackupTime 0x20 471252867Sdelphij#define CEXF_FirmwareVersion 0x40 472252867Sdelphij#define CEXF_SerialNumber 0x80 473252867Sdelphij#define CEXF_BatteryTemperature 0x100 474252867Sdelphij#define CEXF_Power12v 0x200 475252867Sdelphij#define CEXF_Power5v 0x400 476252867Sdelphij#define CEXF_Power3p3v 0x800 477252867Sdelphij#define CEXF_Power2p5v 0x1000 478252867Sdelphij#define CEXF_Power1p8v 0x2000 479252867Sdelphij#define CEXF_Core1p8v 0x4000 480252867Sdelphij#define CEXF_Core1p2v 0x8000 481252867Sdelphij#define CEXF_DDR1p8v 0x10000 482252867Sdelphij#define CEXF_DDR1p8vRef 0x20000 483252867Sdelphij#define CEXF_CPUTemperature 0x40000 484252867Sdelphij#define CEXF_BoardTemperature 0x80000 485252867Sdelphij#define CEXF_FanSpeed 0x100000 486252867Sdelphij#define CEXF_Core1p0v 0x200000 487252867Sdelphij#define CEXF_Fan2Speed 0x400000 488252867Sdelphij#define CEXF_Power1p0v 0x800000 489252867Sdelphij#define CEXF_Power1p5v 0x1000000 490252867Sdelphij#define CEXF_SASAddress 0x2000000 491252867Sdelphij 492252867Sdelphijtypedef struct _CONTROLLER_INFO_V3 { 493252867Sdelphij HPT_U8 ChipType; 494252867Sdelphij HPT_U8 InterruptLevel; 495252867Sdelphij HPT_U8 NumBuses; 496252867Sdelphij HPT_U8 ChipFlags; 497252867Sdelphij HPT_U8 szProductID[MAX_NAME_LENGTH]; 498252867Sdelphij HPT_U8 szVendorID[MAX_NAME_LENGTH]; 499252867Sdelphij HPT_U32 GroupId; 500252867Sdelphij HPT_U8 pci_tree; 501252867Sdelphij HPT_U8 pci_bus; 502252867Sdelphij HPT_U8 pci_device; 503252867Sdelphij HPT_U8 pci_function; 504252867Sdelphij HPT_U32 ExFlags; 505252867Sdelphij HPT_U8 IOPModel[32]; 506252867Sdelphij HPT_U32 SDRAMSize; 507252867Sdelphij HPT_U8 BatteryInstalled; 508252867Sdelphij HPT_U8 BatteryStatus; 509252867Sdelphij HPT_U16 BatteryVoltage; 510252867Sdelphij HPT_U32 BatteryBackupTime; 511252867Sdelphij HPT_U32 FirmwareVersion; 512252867Sdelphij HPT_U8 SerialNumber[32]; 513252867Sdelphij HPT_U8 BatteryMBInstalled; 514252867Sdelphij HPT_U8 BatteryTemperature; 515252867Sdelphij signed char CPUTemperature; 516252867Sdelphij signed char BoardTemperature; 517252867Sdelphij HPT_U16 FanSpeed; 518252867Sdelphij HPT_U16 Power12v; 519252867Sdelphij HPT_U16 Power5v; 520252867Sdelphij HPT_U16 Power3p3v; 521252867Sdelphij HPT_U16 Power2p5v; 522252867Sdelphij HPT_U16 Power1p8v; 523252867Sdelphij HPT_U16 Core1p8v; 524252867Sdelphij HPT_U16 Core1p2v; 525252867Sdelphij HPT_U16 DDR1p8v; 526252867Sdelphij HPT_U16 DDR1p8vRef; 527252867Sdelphij HPT_U16 Core1p0v; 528252867Sdelphij HPT_U16 Fan2Speed; 529252867Sdelphij HPT_U16 Power1p0v; 530252867Sdelphij HPT_U16 Power1p5v; 531252867Sdelphij HPT_U8 SASAddress[8]; 532252867Sdelphij HPT_U8 reserve[48]; 533252867Sdelphij} 534252867SdelphijCONTROLLER_INFO_V3, *PCONTROLLER_INFO_V3; 535252867Sdelphijtypedef char check_CONTROLLER_INFO_V3[sizeof(CONTROLLER_INFO_V3)==256? 1:-1]; 536252867Sdelphij#endif 537252867Sdelphij/* 538252867Sdelphij * Channel information. 539252867Sdelphij */ 540252867Sdelphijtypedef struct _CHANNEL_INFO { 541252867Sdelphij HPT_U32 IoPort; /* IDE Base Port Address */ 542252867Sdelphij HPT_U32 ControlPort; /* IDE Control Port Address */ 543252867Sdelphij 544252867Sdelphij DEVICEID Devices[2]; /* device connected to this channel */ 545252867Sdelphij 546252867Sdelphij} CHANNEL_INFO, *PCHANNEL_INFO; 547252867Sdelphij 548252867Sdelphijtypedef struct _CHANNEL_INFO_V2 { 549252867Sdelphij HPT_U32 IoPort; /* IDE Base Port Address */ 550252867Sdelphij HPT_U32 ControlPort; /* IDE Control Port Address */ 551252867Sdelphij 552252867Sdelphij DEVICEID Devices[2+13]; /* device connected to this channel, PMPort max=15 */ 553252867Sdelphij} CHANNEL_INFO_V2, *PCHANNEL_INFO_V2; 554252867Sdelphij 555252867Sdelphijtypedef struct _ENCLOSURE_INFO { 556252867Sdelphij HPT_U8 EnclosureType; 557252867Sdelphij HPT_U8 NumberOfPhys; 558252867Sdelphij HPT_U8 AttachedTo; 559252867Sdelphij HPT_U8 Status; 560252867Sdelphij HPT_U8 VendorId[8]; 561252867Sdelphij HPT_U8 ProductId[16]; 562252867Sdelphij HPT_U8 ProductRevisionLevel[4]; 563252867Sdelphij HPT_U32 PortPhyMap; 564252867Sdelphij HPT_U32 reserve[55]; 565252867Sdelphij} ENCLOSURE_INFO, *PENCLOSURE_INFO; 566252867Sdelphij 567252867Sdelphij 568252867Sdelphijtypedef struct _SES_ELEMENT_STATUS { 569252867Sdelphij HPT_U8 ElementType; 570252867Sdelphij HPT_U8 ElementOverallIndex; 571252867Sdelphij HPT_U8 ElementStatus; 572252867Sdelphij HPT_U8 Reserved; 573252867Sdelphij HPT_U32 ElementValue; 574252867Sdelphij HPT_U8 ElementDescriptor[32]; 575252867Sdelphij}SES_ELEMENT_STATUS,*PSES_ELEMENT_STATUS; 576252867Sdelphij 577252867Sdelphij#define MAX_ELEMENT_COUNT 80 578252867Sdelphij/* Element Type */ 579252867Sdelphij#define SES_TYPE_UNSPECIFIED 0x00 580252867Sdelphij#define SES_TYPE_DEVICE 0x01 581252867Sdelphij#define SES_TYPE_POWER_SUPPLY 0x02 582252867Sdelphij#define SES_TYPE_FAN 0x03 583252867Sdelphij#define SES_TYPE_TEMPERATURE_SENSOR 0x04 584252867Sdelphij#define SES_TYPE_DOOR_LOCK 0x05 585252867Sdelphij#define SES_TYPE_SPEAKER 0x06 586252867Sdelphij#define SES_TYPE_ES_CONTROLLER 0x07 587252867Sdelphij#define SES_TYPE_SCC_CONTROLLER 0x08 588252867Sdelphij#define SES_TYPE_NONVOLATILE_CACHE 0x09 589252867Sdelphij#define SES_TYPE_UPS 0x0B 590252867Sdelphij#define SES_TYPE_DISPLAY 0x0C 591252867Sdelphij#define SES_TYPE_KEYPAD 0x0D 592252867Sdelphij#define SES_TYPE_ENCLOSURE 0x0E 593252867Sdelphij#define SES_TYPE_SCSI_TRANSCEIVER 0x0F 594252867Sdelphij#define SES_TYPE_LANGUAGE 0x10 595252867Sdelphij#define SES_TYPE_COMM_PORT 0x11 596252867Sdelphij#define SES_TYPE_VOLTAGE_SENSOR 0x12 597252867Sdelphij#define SES_TYPE_CURRENT_SENSOR 0x13 598252867Sdelphij#define SES_TYPE_SCSI_TARGET_PORT 0x14 599252867Sdelphij#define SES_TYPE_SCSI_INITIATOR_PORT 0x15 600252867Sdelphij#define SES_TYPE_SIMPLE_SUBENCLOSURE 0x16 601252867Sdelphij#define SES_TYPE_ARRAY_DEVICE 0x17 602252867Sdelphij#define SES_TYPE_VENDOR_SPECIFIC 0x80 603252867Sdelphij 604252867Sdelphij/* Element Status */ 605252867Sdelphij 606252867Sdelphij#define SES_STATUS_UNSUPPORTED 0x00 607252867Sdelphij#define SES_STATUS_OK 0x01 608252867Sdelphij#define SES_STATUS_CRITICAL 0x02 609252867Sdelphij#define SES_STATUS_NONCRITICAL 0x03 610252867Sdelphij#define SES_STATUS_UNRECOVERABLE 0x04 611252867Sdelphij#define SES_STATUS_NOTINSTALLED 0x05 612252867Sdelphij#define SES_STATUS_UNKNOWN 0x06 613252867Sdelphij#define SES_STATUS_NOTAVAILABLE 0x07 614252867Sdelphij#define SES_STATUS_RESERVED 0x08 615252867Sdelphij 616252867Sdelphij 617252867Sdelphijtypedef struct _ENCLOSURE_INFO_V2 { 618252867Sdelphij HPT_U8 EnclosureType; 619252867Sdelphij HPT_U8 NumberOfPhys; 620252867Sdelphij HPT_U8 AttachedTo; 621252867Sdelphij HPT_U8 Status; 622252867Sdelphij HPT_U8 VendorId[8]; 623252867Sdelphij HPT_U8 ProductId[16]; 624252867Sdelphij HPT_U8 ProductRevisionLevel[4]; 625252867Sdelphij HPT_U32 PortPhyMap; 626252867Sdelphij SES_ELEMENT_STATUS ElementStatus[MAX_ELEMENT_COUNT]; 627252867Sdelphij} ENCLOSURE_INFO_V2, *PENCLOSURE_INFO_V2; 628252867Sdelphij 629252867Sdelphijtypedef struct _ENCLOSURE_INFO_V3 { 630252867Sdelphij HPT_U8 EnclosureType; 631252867Sdelphij HPT_U8 NumberOfPhys; 632252867Sdelphij HPT_U8 AttachedTo; 633252867Sdelphij HPT_U8 Status; 634252867Sdelphij HPT_U8 VendorId[8]; 635252867Sdelphij HPT_U8 ProductId[16]; 636252867Sdelphij HPT_U8 ProductRevisionLevel[4]; 637252867Sdelphij HPT_U32 PortPhyMap; 638252867Sdelphij HPT_U32 UnitId; /*272x card has two Cores, unitId is used to distinguish them */ 639252867Sdelphij HPT_U32 reserved[32]; 640252867Sdelphij SES_ELEMENT_STATUS ElementStatus[MAX_ELEMENT_COUNT]; 641252867Sdelphij} ENCLOSURE_INFO_V3, *PENCLOSURE_INFO_V3; 642252867Sdelphij 643252867Sdelphijtypedef struct _ENCLOSURE_INFO_V4 { 644252867Sdelphij HPT_U8 EnclosureType; 645252867Sdelphij HPT_U8 NumberOfPhys; 646252867Sdelphij HPT_U8 AttachedTo; 647252867Sdelphij HPT_U8 Status; 648252867Sdelphij HPT_U8 VendorId[8]; 649252867Sdelphij HPT_U8 ProductId[16]; 650252867Sdelphij HPT_U8 ProductRevisionLevel[4]; 651252867Sdelphij HPT_U32 PortPhyMap; 652252867Sdelphij HPT_U32 UnitId; /*272x card has two Cores, unitId is used to distinguish them */ 653252867Sdelphij HPT_U32 ElementCount; 654252867Sdelphij HPT_U32 reserved[32]; 655252867Sdelphij} ENCLOSURE_INFO_V4, *PENCLOSURE_INFO_V4; 656252867Sdelphij 657252867Sdelphij#define ENCLOSURE_STATUS_OFFLINE 1 658252867Sdelphij 659252867Sdelphij#define ENCLOSURE_TYPE_INTERNAL 0 660252867Sdelphij#define ENCLOSURE_TYPE_SMP 1 661252867Sdelphij#define ENCLOSURE_TYPE_PM 2 662252867Sdelphij 663252867Sdelphij#ifndef __KERNEL__ 664252867Sdelphij/* 665252867Sdelphij * time represented in HPT_U32 format 666252867Sdelphij */ 667252867Sdelphijtypedef struct _TIME_RECORD { 668252867Sdelphij HPT_U32 seconds:6; /* 0 - 59 */ 669252867Sdelphij HPT_U32 minutes:6; /* 0 - 59 */ 670252867Sdelphij HPT_U32 month:4; /* 1 - 12 */ 671252867Sdelphij HPT_U32 hours:6; /* 0 - 59 */ 672252867Sdelphij HPT_U32 day:5; /* 1 - 31 */ 673252867Sdelphij HPT_U32 year:5; /* 0=2000, 31=2031 */ 674252867Sdelphij} TIME_RECORD; 675252867Sdelphij#endif 676252867Sdelphij 677252867Sdelphij/* 678252867Sdelphij * Array information. 679252867Sdelphij */ 680252867Sdelphijtypedef struct _HPT_ARRAY_INFO { 681252867Sdelphij HPT_U8 Name[MAX_ARRAYNAME_LEN];/* array name */ 682252867Sdelphij HPT_U8 Description[64]; /* array description */ 683252867Sdelphij HPT_U8 CreateManager[16]; /* who created it */ 684252867Sdelphij TIME_RECORD CreateTime; /* when created it */ 685252867Sdelphij 686252867Sdelphij HPT_U8 ArrayType; /* array type */ 687252867Sdelphij HPT_U8 BlockSizeShift; /* stripe size */ 688252867Sdelphij HPT_U8 nDisk; /* member count: Number of ID in Members[] */ 689252867Sdelphij HPT_U8 SubArrayType; 690252867Sdelphij 691252867Sdelphij HPT_U32 Flags; /* working flags, see ARRAY_FLAG_XXX */ 692252867Sdelphij HPT_U32 Members[MAX_ARRAY_MEMBERS_V1]; /* member array/disks */ 693252867Sdelphij 694252867Sdelphij /* 695252867Sdelphij * rebuilding progress, xx.xx% = sprintf(s, "%.2f%%", RebuildingProgress/100.0); 696252867Sdelphij * only valid if rebuilding is done by driver code. 697252867Sdelphij * Member Flags will have ARRAY_FLAG_REBUILDING set at this case. 698252867Sdelphij * Verify operation use same fields below, the only difference is 699252867Sdelphij * ARRAY_FLAG_VERIFYING is set. 700252867Sdelphij */ 701252867Sdelphij HPT_U32 RebuildingProgress; 702252867Sdelphij HPT_U32 RebuiltSectors; /* rebuilding point (LBA) for single member */ 703252867Sdelphij 704252867Sdelphij} HPT_ARRAY_INFO, *PHPT_ARRAY_INFO; 705252867Sdelphij 706252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000 707252867Sdelphijtypedef struct _HPT_ARRAY_INFO_V2 { 708252867Sdelphij HPT_U8 Name[MAX_ARRAYNAME_LEN];/* array name */ 709252867Sdelphij HPT_U8 Description[64]; /* array description */ 710252867Sdelphij HPT_U8 CreateManager[16]; /* who created it */ 711252867Sdelphij TIME_RECORD CreateTime; /* when created it */ 712252867Sdelphij 713252867Sdelphij HPT_U8 ArrayType; /* array type */ 714252867Sdelphij HPT_U8 BlockSizeShift; /* stripe size */ 715252867Sdelphij HPT_U8 nDisk; /* member count: Number of ID in Members[] */ 716252867Sdelphij HPT_U8 SubArrayType; 717252867Sdelphij 718252867Sdelphij HPT_U32 Flags; /* working flags, see ARRAY_FLAG_XXX */ 719252867Sdelphij HPT_U32 Members[MAX_ARRAY_MEMBERS_V2]; /* member array/disks */ 720252867Sdelphij 721252867Sdelphij HPT_U32 RebuildingProgress; 722252867Sdelphij HPT_U64 RebuiltSectors; /* rebuilding point (LBA) for single member */ 723252867Sdelphij 724252867Sdelphij HPT_U32 reserve4[4]; 725252867Sdelphij} HPT_ARRAY_INFO_V2, *PHPT_ARRAY_INFO_V2; 726252867Sdelphij#endif 727252867Sdelphij 728252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000 729252867Sdelphijtypedef struct _HPT_ARRAY_INFO_V3 { 730252867Sdelphij HPT_U8 Name[MAX_ARRAYNAME_LEN];/* array name */ 731252867Sdelphij HPT_U8 Description[64]; /* array description */ 732252867Sdelphij HPT_U8 CreateManager[16]; /* who created it */ 733252867Sdelphij TIME_RECORD CreateTime; /* when created it */ 734252867Sdelphij 735252867Sdelphij HPT_U8 ArrayType; /* array type */ 736252867Sdelphij HPT_U8 BlockSizeShift; /* stripe size */ 737252867Sdelphij HPT_U8 nDisk; /* member count: Number of ID in Members[] */ 738252867Sdelphij HPT_U8 SubArrayType; 739252867Sdelphij 740252867Sdelphij HPT_U32 Flags; /* working flags, see ARRAY_FLAG_XXX */ 741252867Sdelphij HPT_U32 Members[MAX_ARRAY_MEMBERS_V2]; /* member array/disks */ 742252867Sdelphij 743252867Sdelphij HPT_U32 RebuildingProgress; 744252867Sdelphij HPT_U64 RebuiltSectors; /* rebuilding point (LBA) for single member */ 745252867Sdelphij 746252867Sdelphij DEVICEID TransformSource; 747252867Sdelphij DEVICEID TransformTarget; /* destination device ID */ 748252867Sdelphij HPT_U32 TransformingProgress; 749252867Sdelphij HPT_U32 Signature; /* persistent identification*/ 750252867Sdelphij#if MAX_ARRAY_MEMBERS_V2==16 751252867Sdelphij HPT_U16 Critical_Members; /* bit mask of critical members */ 752252867Sdelphij HPT_U16 reserve2; 753252867Sdelphij HPT_U32 reserve; 754252867Sdelphij#else 755252867Sdelphij HPT_U32 Critical_Members; 756252867Sdelphij HPT_U32 reserve; 757252867Sdelphij#endif 758252867Sdelphij} HPT_ARRAY_INFO_V3, *PHPT_ARRAY_INFO_V3; 759252867Sdelphij#endif 760252867Sdelphij 761252867Sdelphij#if HPT_INTERFACE_VERSION>=0x02000001 762252867Sdelphijtypedef struct _HPT_ARRAY_INFO_V4 { 763252867Sdelphij HPT_U8 Name[MAX_ARRAYNAME_LEN];/* array name */ 764252867Sdelphij HPT_U8 Description[64]; /* array description */ 765252867Sdelphij HPT_U8 CreateManager[16]; /* who created it */ 766252867Sdelphij TIME_RECORD CreateTime; /* when created it */ 767252867Sdelphij 768252867Sdelphij HPT_U8 ArrayType; /* array type */ 769252867Sdelphij HPT_U8 BlockSizeShift; /* stripe size */ 770252867Sdelphij HPT_U8 nDisk; /* member count: Number of ID in Members[] */ 771252867Sdelphij HPT_U8 SubArrayType; 772252867Sdelphij 773252867Sdelphij HPT_U32 Flags; /* working flags, see ARRAY_FLAG_XXX */ 774252867Sdelphij 775252867Sdelphij HPT_U32 RebuildingProgress; 776252867Sdelphij HPT_U64 RebuiltSectors; /* rebuilding point (LBA) for single member */ 777252867Sdelphij 778252867Sdelphij DEVICEID TransformSource; 779252867Sdelphij DEVICEID TransformTarget; /* destination device ID */ 780252867Sdelphij HPT_U32 TransformingProgress; 781252867Sdelphij HPT_U32 Signature; /* persistent identification*/ 782252867Sdelphij HPT_U8 SectorSizeShift; /*sector size = 512B<<SectorSizeShift*/ 783252867Sdelphij HPT_U8 reserved2[7]; 784252867Sdelphij HPT_U64 Critical_Members; 785252867Sdelphij HPT_U32 Members[MAX_ARRAY_MEMBERS_V3]; /* member array/disks */ 786252867Sdelphij} HPT_ARRAY_INFO_V4, *PHPT_ARRAY_INFO_V4; 787252867Sdelphij#endif 788252867Sdelphij 789252867Sdelphij 790252867Sdelphij/* 791252867Sdelphij * ATA/ATAPI Device identify data without the Reserved4. 792252867Sdelphij */ 793252867Sdelphijtypedef struct _IDENTIFY_DATA2 { 794252867Sdelphij HPT_U16 GeneralConfiguration; 795252867Sdelphij HPT_U16 NumberOfCylinders; 796252867Sdelphij HPT_U16 Reserved1; 797252867Sdelphij HPT_U16 NumberOfHeads; 798252867Sdelphij HPT_U16 UnformattedBytesPerTrack; 799252867Sdelphij HPT_U16 UnformattedBytesPerSector; 800252867Sdelphij HPT_U8 SasAddress[8]; 801252867Sdelphij HPT_U16 SerialNumber[10]; 802252867Sdelphij HPT_U16 BufferType; 803252867Sdelphij HPT_U16 BufferSectorSize; 804252867Sdelphij HPT_U16 NumberOfEccBytes; 805252867Sdelphij HPT_U16 FirmwareRevision[4]; 806252867Sdelphij HPT_U16 ModelNumber[20]; 807252867Sdelphij HPT_U8 MaximumBlockTransfer; 808252867Sdelphij HPT_U8 VendorUnique2; 809252867Sdelphij HPT_U16 DoubleWordIo; 810252867Sdelphij HPT_U16 Capabilities; 811252867Sdelphij HPT_U16 Reserved2; 812252867Sdelphij HPT_U8 VendorUnique3; 813252867Sdelphij HPT_U8 PioCycleTimingMode; 814252867Sdelphij HPT_U8 VendorUnique4; 815252867Sdelphij HPT_U8 DmaCycleTimingMode; 816252867Sdelphij HPT_U16 TranslationFieldsValid; 817252867Sdelphij HPT_U16 NumberOfCurrentCylinders; 818252867Sdelphij HPT_U16 NumberOfCurrentHeads; 819252867Sdelphij HPT_U16 CurrentSectorsPerTrack; 820252867Sdelphij HPT_U32 CurrentSectorCapacity; 821252867Sdelphij HPT_U16 CurrentMultiSectorSetting; 822252867Sdelphij HPT_U32 UserAddressableSectors; 823252867Sdelphij HPT_U8 SingleWordDMASupport; 824252867Sdelphij HPT_U8 SingleWordDMAActive; 825252867Sdelphij HPT_U8 MultiWordDMASupport; 826252867Sdelphij HPT_U8 MultiWordDMAActive; 827252867Sdelphij HPT_U8 AdvancedPIOModes; 828252867Sdelphij HPT_U8 Reserved4; 829252867Sdelphij HPT_U16 MinimumMWXferCycleTime; 830252867Sdelphij HPT_U16 RecommendedMWXferCycleTime; 831252867Sdelphij HPT_U16 MinimumPIOCycleTime; 832252867Sdelphij HPT_U16 MinimumPIOCycleTimeIORDY; 833252867Sdelphij HPT_U16 Reserved5[2]; 834252867Sdelphij HPT_U16 ReleaseTimeOverlapped; 835252867Sdelphij HPT_U16 ReleaseTimeServiceCommand; 836252867Sdelphij HPT_U16 MajorRevision; 837252867Sdelphij HPT_U16 MinorRevision; 838252867Sdelphij} __attribute__((packed)) IDENTIFY_DATA2, *PIDENTIFY_DATA2; 839252867Sdelphij 840252867Sdelphij/* 841252867Sdelphij * physical device information. 842252867Sdelphij * IdentifyData.ModelNumber[] is HPT_U8-swapped from the original identify data. 843252867Sdelphij */ 844252867Sdelphijtypedef struct _DEVICE_INFO { 845252867Sdelphij HPT_U8 ControllerId; /* controller id */ 846252867Sdelphij HPT_U8 PathId; /* bus */ 847252867Sdelphij HPT_U8 TargetId; /* id */ 848252867Sdelphij HPT_U8 DeviceModeSetting; /* Current Data Transfer mode: 0-4 PIO 0-4 */ 849252867Sdelphij /* 5-7 MW DMA0-2, 8-13 UDMA0-5 */ 850252867Sdelphij HPT_U8 DeviceType; /* device type */ 851252867Sdelphij HPT_U8 UsableMode; /* highest usable mode */ 852252867Sdelphij 853252867Sdelphij#ifdef __BIG_ENDIAN_BITFIELD 854252867Sdelphij HPT_U8 NCQEnabled: 1; 855252867Sdelphij HPT_U8 NCQSupported: 1; 856252867Sdelphij HPT_U8 TCQEnabled: 1; 857252867Sdelphij HPT_U8 TCQSupported: 1; 858252867Sdelphij HPT_U8 WriteCacheEnabled: 1; 859252867Sdelphij HPT_U8 WriteCacheSupported: 1; 860252867Sdelphij HPT_U8 ReadAheadEnabled: 1; 861252867Sdelphij HPT_U8 ReadAheadSupported: 1; 862252867Sdelphij HPT_U8 reserved6: 6; 863252867Sdelphij HPT_U8 SpinUpMode: 2; 864252867Sdelphij#else 865252867Sdelphij HPT_U8 ReadAheadSupported: 1; 866252867Sdelphij HPT_U8 ReadAheadEnabled: 1; 867252867Sdelphij HPT_U8 WriteCacheSupported: 1; 868252867Sdelphij HPT_U8 WriteCacheEnabled: 1; 869252867Sdelphij HPT_U8 TCQSupported: 1; 870252867Sdelphij HPT_U8 TCQEnabled: 1; 871252867Sdelphij HPT_U8 NCQSupported: 1; 872252867Sdelphij HPT_U8 NCQEnabled: 1; 873252867Sdelphij HPT_U8 SpinUpMode: 2; 874252867Sdelphij HPT_U8 reserved6: 6; 875252867Sdelphij#endif 876252867Sdelphij 877252867Sdelphij HPT_U32 Flags; /* working flags, see DEVICE_FLAG_XXX */ 878252867Sdelphij 879252867Sdelphij IDENTIFY_DATA2 IdentifyData; /* Identify Data of this device */ 880252867Sdelphij 881252867Sdelphij} 882252867Sdelphij__attribute__((packed)) DEVICE_INFO, *PDEVICE_INFO; 883252867Sdelphij 884252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000 885252867Sdelphij#define MAX_PARENTS_PER_DISK 8 886252867Sdelphij/* 887252867Sdelphij * physical device information. 888252867Sdelphij * IdentifyData.ModelNumber[] is HPT_U8-swapped from the original identify data. 889252867Sdelphij */ 890252867Sdelphijtypedef struct _DEVICE_INFO_V2 { 891252867Sdelphij HPT_U8 ControllerId; /* controller id */ 892252867Sdelphij HPT_U8 PathId; /* bus */ 893252867Sdelphij HPT_U8 TargetId; /* id */ 894252867Sdelphij HPT_U8 DeviceModeSetting; /* Current Data Transfer mode: 0-4 PIO 0-4 */ 895252867Sdelphij /* 5-7 MW DMA0-2, 8-13 UDMA0-5 */ 896252867Sdelphij HPT_U8 DeviceType; /* device type */ 897252867Sdelphij HPT_U8 UsableMode; /* highest usable mode */ 898252867Sdelphij 899252867Sdelphij#ifdef __BIG_ENDIAN_BITFIELD 900252867Sdelphij HPT_U8 NCQEnabled: 1; 901252867Sdelphij HPT_U8 NCQSupported: 1; 902252867Sdelphij HPT_U8 TCQEnabled: 1; 903252867Sdelphij HPT_U8 TCQSupported: 1; 904252867Sdelphij HPT_U8 WriteCacheEnabled: 1; 905252867Sdelphij HPT_U8 WriteCacheSupported: 1; 906252867Sdelphij HPT_U8 ReadAheadEnabled: 1; 907252867Sdelphij HPT_U8 ReadAheadSupported: 1; 908252867Sdelphij HPT_U8 reserved6: 6; 909252867Sdelphij HPT_U8 SpinUpMode: 2; 910252867Sdelphij#else 911252867Sdelphij HPT_U8 ReadAheadSupported: 1; 912252867Sdelphij HPT_U8 ReadAheadEnabled: 1; 913252867Sdelphij HPT_U8 WriteCacheSupported: 1; 914252867Sdelphij HPT_U8 WriteCacheEnabled: 1; 915252867Sdelphij HPT_U8 TCQSupported: 1; 916252867Sdelphij HPT_U8 TCQEnabled: 1; 917252867Sdelphij HPT_U8 NCQSupported: 1; 918252867Sdelphij HPT_U8 NCQEnabled: 1; 919252867Sdelphij HPT_U8 SpinUpMode: 2; 920252867Sdelphij HPT_U8 reserved6: 6; 921252867Sdelphij#endif 922252867Sdelphij 923252867Sdelphij HPT_U32 Flags; /* working flags, see DEVICE_FLAG_XXX */ 924252867Sdelphij 925252867Sdelphij IDENTIFY_DATA2 IdentifyData; /* Identify Data of this device */ 926252867Sdelphij 927252867Sdelphij HPT_U64 TotalFree; 928252867Sdelphij HPT_U64 MaxFree; 929252867Sdelphij HPT_U64 BadSectors; 930252867Sdelphij DEVICEID ParentArrays[MAX_PARENTS_PER_DISK]; 931252867Sdelphij 932252867Sdelphij} 933252867Sdelphij__attribute__((packed)) DEVICE_INFO_V2, *PDEVICE_INFO_V2, DEVICE_INFO_V3, *PDEVICE_INFO_V3; 934252867Sdelphij 935252867Sdelphij/* 936252867Sdelphij * HPT601 information 937252867Sdelphij */ 938252867Sdelphij#endif 939252867Sdelphij/* 940252867Sdelphij * HPT601 information 941252867Sdelphij */ 942252867Sdelphij#define HPT601_INFO_DEVICEID 1 943252867Sdelphij#define HPT601_INFO_TEMPERATURE 2 944252867Sdelphij#define HPT601_INFO_FANSTATUS 4 945252867Sdelphij#define HPT601_INFO_BEEPERCONTROL 8 946252867Sdelphij#define HPT601_INFO_LED1CONTROL 0x10 947252867Sdelphij#define HPT601_INFO_LED2CONTROL 0x20 948252867Sdelphij#define HPT601_INFO_POWERSTATUS 0x40 949252867Sdelphij 950252867Sdelphijtypedef struct _HPT601_INFO_ { 951252867Sdelphij HPT_U16 ValidFields; /* mark valid fields below */ 952252867Sdelphij HPT_U16 DeviceId; /* 0x5A3E */ 953252867Sdelphij HPT_U16 Temperature; /* Read: temperature sensor value. Write: temperature limit */ 954252867Sdelphij HPT_U16 FanStatus; /* Fan status */ 955252867Sdelphij HPT_U16 BeeperControl; /* bit4: beeper control bit. bit0-3: frequency bits */ 956252867Sdelphij HPT_U16 LED1Control; /* bit4: twinkling control bit. bit0-3: frequency bits */ 957252867Sdelphij HPT_U16 LED2Control; /* bit4: twinkling control bit. bit0-3: frequency bits */ 958252867Sdelphij HPT_U16 PowerStatus; /* 1: has power 2: no power */ 959252867Sdelphij} HPT601_INFO, *PHPT601_INFO; 960252867Sdelphij 961252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000 962252867Sdelphij#ifndef __KERNEL__ 963252867Sdelphij/* cache policy for each vdev, copied from ldm.h */ 964252867Sdelphij#define CACHE_POLICY_NONE 0 965252867Sdelphij#define CACHE_POLICY_WRITE_THROUGH 1 966252867Sdelphij#define CACHE_POLICY_WRITE_BACK 2 967252867Sdelphij 968252867Sdelphij#endif 969252867Sdelphij#endif 970252867Sdelphij/* 971252867Sdelphij * Logical device information. 972252867Sdelphij * Union of ArrayInfo and DeviceInfo. 973252867Sdelphij * Common properties will be put in logical device information. 974252867Sdelphij */ 975252867Sdelphijtypedef struct _LOGICAL_DEVICE_INFO { 976252867Sdelphij HPT_U8 Type; /* LDT_ARRAY or LDT_DEVICE */ 977252867Sdelphij HPT_U8 reserved[3]; 978252867Sdelphij 979252867Sdelphij HPT_U32 Capacity; /* array capacity */ 980252867Sdelphij DEVICEID ParentArray; 981252867Sdelphij 982252867Sdelphij union { 983252867Sdelphij HPT_ARRAY_INFO array; 984252867Sdelphij DEVICE_INFO device; 985252867Sdelphij } __attribute__((packed)) u; 986252867Sdelphij 987252867Sdelphij} __attribute__((packed)) LOGICAL_DEVICE_INFO, *PLOGICAL_DEVICE_INFO; 988252867Sdelphij 989252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000 990252867Sdelphijtypedef struct _LOGICAL_DEVICE_INFO_V2 { 991252867Sdelphij HPT_U8 Type; /* LDT_ARRAY or LDT_DEVICE */ 992252867Sdelphij HPT_U8 reserved[3]; 993252867Sdelphij 994252867Sdelphij HPT_U64 Capacity; /* array capacity */ 995252867Sdelphij DEVICEID ParentArray; /* for physical device, Please don't use this field. 996252867Sdelphij * use ParentArrays field in DEVICE_INFO_V2 997252867Sdelphij */ 998252867Sdelphij 999252867Sdelphij union { 1000252867Sdelphij HPT_ARRAY_INFO_V2 array; 1001252867Sdelphij DEVICE_INFO device; 1002252867Sdelphij } __attribute__((packed)) u; 1003252867Sdelphij 1004252867Sdelphij} __attribute__((packed)) LOGICAL_DEVICE_INFO_V2, *PLOGICAL_DEVICE_INFO_V2; 1005252867Sdelphij#endif 1006252867Sdelphij 1007252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000 1008252867Sdelphij#define INVALID_TARGET_ID 0xFF 1009252867Sdelphij#define INVALID_BUS_ID 0xFF 1010252867Sdelphijtypedef struct _LOGICAL_DEVICE_INFO_V3 { 1011252867Sdelphij HPT_U8 Type; /* LDT_ARRAY or LDT_DEVICE */ 1012252867Sdelphij HPT_U8 CachePolicy; /* refer to CACHE_POLICY_xxx */ 1013252867Sdelphij HPT_U8 VBusId; /* vbus sequence in vbus_list */ 1014252867Sdelphij HPT_U8 TargetId; /* OS target id. Value 0xFF is invalid */ 1015252867Sdelphij /* OS disk name: HPT DISK $VBusId_$TargetId */ 1016252867Sdelphij HPT_U64 Capacity; /* array capacity */ 1017252867Sdelphij DEVICEID ParentArray; /* for physical device, don't use this field. 1018252867Sdelphij * use ParentArrays field in DEVICE_INFO_V2 instead. 1019252867Sdelphij */ 1020252867Sdelphij HPT_U32 TotalIOs; 1021252867Sdelphij HPT_U32 TobalMBs; 1022252867Sdelphij HPT_U32 IOPerSec; 1023252867Sdelphij HPT_U32 MBPerSec; 1024252867Sdelphij 1025252867Sdelphij union { 1026252867Sdelphij HPT_ARRAY_INFO_V3 array; 1027252867Sdelphij DEVICE_INFO_V2 device; 1028252867Sdelphij } __attribute__((packed)) u; 1029252867Sdelphij 1030252867Sdelphij} 1031252867Sdelphij__attribute__((packed)) LOGICAL_DEVICE_INFO_V3, *PLOGICAL_DEVICE_INFO_V3; 1032252867Sdelphij#endif 1033252867Sdelphij 1034252867Sdelphij#if HPT_INTERFACE_VERSION>=0x02000001 1035252867Sdelphijtypedef struct _LOGICAL_DEVICE_INFO_V4 { 1036252867Sdelphij HPT_U32 dwSize; 1037252867Sdelphij HPT_U8 revision; 1038252867Sdelphij HPT_U8 reserved[7]; 1039252867Sdelphij 1040252867Sdelphij HPT_U8 Type; /* LDT_ARRAY or LDT_DEVICE */ 1041252867Sdelphij HPT_U8 CachePolicy; /* refer to CACHE_POLICY_xxx */ 1042252867Sdelphij HPT_U8 VBusId; /* vbus sequence in vbus_list */ 1043252867Sdelphij HPT_U8 TargetId; /* OS target id. Value 0xFF is invalid */ 1044252867Sdelphij /* OS disk name: HPT DISK $VBusId_$TargetId */ 1045252867Sdelphij HPT_U64 Capacity; /* array capacity */ 1046252867Sdelphij DEVICEID ParentArray; /* for physical device, don't use this field. 1047252867Sdelphij * use ParentArrays field in DEVICE_INFO_V2 instead. 1048252867Sdelphij */ 1049252867Sdelphij HPT_U32 TotalIOs; 1050252867Sdelphij HPT_U32 TobalMBs; 1051252867Sdelphij HPT_U32 IOPerSec; 1052252867Sdelphij HPT_U32 MBPerSec; 1053252867Sdelphij 1054252867Sdelphij union { 1055252867Sdelphij HPT_ARRAY_INFO_V4 array; 1056252867Sdelphij DEVICE_INFO_V3 device; 1057252867Sdelphij } __attribute__((packed)) u; 1058252867Sdelphij} 1059252867Sdelphij__attribute__((packed)) LOGICAL_DEVICE_INFO_V4, *PLOGICAL_DEVICE_INFO_V4; 1060252867Sdelphij 1061252867Sdelphij/*LOGICAL_DEVICE_INFO_V4 max revision number*/ 1062252867Sdelphij#define LOGICAL_DEVICE_INFO_V4_REVISION 0 1063252867Sdelphij/*If new revision was defined please check evey revision size*/ 1064252867Sdelphij#define LOGICAL_DEVICE_INFO_V4_R0_SIZE (sizeof(LOGICAL_DEVICE_INFO_V4)) 1065252867Sdelphij#endif 1066252867Sdelphij 1067252867Sdelphij/* 1068252867Sdelphij * ALTERABLE_ARRAY_INFO and ALTERABLE_DEVICE_INFO, used in set_array_info() 1069252867Sdelphij * and set_device_info(). 1070252867Sdelphij * When set_xxx_info() is called, the ValidFields member indicates which 1071252867Sdelphij * fields in the structure are valid. 1072252867Sdelphij */ 1073252867Sdelphij/* field masks */ 1074252867Sdelphij#define AAIF_NAME 1 1075252867Sdelphij#define AAIF_DESCRIPTION 2 1076252867Sdelphij 1077252867Sdelphij#define ADIF_MODE 1 1078252867Sdelphij#define ADIF_TCQ 2 1079252867Sdelphij#define ADIF_NCQ 4 1080252867Sdelphij#define ADIF_WRITE_CACHE 8 1081252867Sdelphij#define ADIF_READ_AHEAD 0x10 1082252867Sdelphij#define ADIF_SPIN_UP_MODE 0x20 1083252867Sdelphij#define ADIF_SET_BAD 0x40 1084252867Sdelphij 1085252867Sdelphijtypedef struct _ALTERABLE_ARRAY_INFO { 1086252867Sdelphij HPT_U32 ValidFields; /* mark valid fields below */ 1087252867Sdelphij HPT_U8 Name[MAX_ARRAYNAME_LEN]; /* array name */ 1088252867Sdelphij HPT_U8 Description[64]; /* array description */ 1089252867Sdelphij}__attribute__((packed))ALTERABLE_ARRAY_INFO, *PALTERABLE_ARRAY_INFO; 1090252867Sdelphij 1091252867Sdelphijtypedef struct _ALTERABLE_DEVICE_INFO { 1092252867Sdelphij HPT_U32 ValidFields; /* mark valid fields below */ 1093252867Sdelphij HPT_U8 DeviceModeSetting; /* 0-4 PIO 0-4, 5-7 MW DMA0-2, 8-13 UDMA0-5 */ 1094252867Sdelphij}__attribute__((packed))ALTERABLE_DEVICE_INFO, *PALTERABLE_DEVICE_INFO; 1095252867Sdelphij 1096252867Sdelphijtypedef struct _ALTERABLE_DEVICE_INFO_V2 { 1097252867Sdelphij HPT_U32 ValidFields; /* mark valid fields below */ 1098252867Sdelphij HPT_U8 DeviceModeSetting; /* 0-4 PIO 0-4, 5-7 MW DMA0-2, 8-13 UDMA0-5 */ 1099252867Sdelphij HPT_U8 TCQEnabled; 1100252867Sdelphij HPT_U8 NCQEnabled; 1101252867Sdelphij HPT_U8 WriteCacheEnabled; 1102252867Sdelphij HPT_U8 ReadAheadEnabled; 1103252867Sdelphij HPT_U8 SpinUpMode; 1104252867Sdelphij HPT_U8 SetBadSector; 1105252867Sdelphij HPT_U8 reserve[1]; 1106252867Sdelphij HPT_U32 reserve2[13]; /* pad to 64 bytes */ 1107252867Sdelphij}__attribute__((packed))ALTERABLE_DEVICE_INFO_V2, *PALTERABLE_DEVICE_INFO_V2; 1108252867Sdelphij 1109252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000 1110252867Sdelphij 1111252867Sdelphij#define TARGET_TYPE_DEVICE 0 1112252867Sdelphij#define TARGET_TYPE_ARRAY 1 1113252867Sdelphij 1114252867Sdelphij 1115252867Sdelphij#define AIT_NAME 0 1116252867Sdelphij#define AIT_DESCRIPTION 1 1117252867Sdelphij#define AIT_CACHE_POLICY 2 1118252867Sdelphij 1119252867Sdelphij 1120252867Sdelphij#define DIT_MODE 0 1121252867Sdelphij#define DIT_READ_AHEAD 1 1122252867Sdelphij#define DIT_WRITE_CACHE 2 1123252867Sdelphij#define DIT_TCQ 3 1124252867Sdelphij#define DIT_NCQ 4 1125252867Sdelphij#define DIT_IDENTIFY 5 1126252867Sdelphij 1127252867Sdelphij#define DISK_CACHE_POLICY_UNCHANGE 0 1128252867Sdelphij#define DISK_CACHE_POLICY_ENABLE 1 1129252867Sdelphij#define DISK_CACHE_POLICY_DISABLE 2 1130252867Sdelphij 1131252867Sdelphij/* param type is determined by target_type and info_type*/ 1132252867Sdelphijtypedef struct _SET_DEV_INFO 1133252867Sdelphij{ 1134252867Sdelphij HPT_U8 target_type; 1135252867Sdelphij HPT_U8 infor_type; 1136252867Sdelphij HPT_U16 param_length; 1137252867Sdelphij #define SET_VDEV_INFO_param(p) ((HPT_U8 *)(p)+sizeof(SET_VDEV_INFO)) 1138252867Sdelphij /* HPT_U8 param[0]; */ 1139252867Sdelphij} SET_VDEV_INFO, * PSET_VDEV_INFO; 1140252867Sdelphij 1141252867Sdelphijtypedef HPT_U8 PARAM_ARRAY_NAME[MAX_ARRAYNAME_LEN] ; 1142252867Sdelphijtypedef HPT_U8 PARAM_ARRAY_DES[64]; 1143252867Sdelphijtypedef HPT_U8 PARAM_DEVICE_MODE, PARAM_TCQ, PARAM_NCQ, PARAM_READ_AHEAD, PARAM_WRITE_CACHE, PARAM_CACHE_POLICY; 1144252867Sdelphij 1145252867Sdelphij#endif 1146252867Sdelphij 1147252867Sdelphij/* 1148252867Sdelphij * CREATE_ARRAY_PARAMS 1149252867Sdelphij * Param structure used to create an array. 1150252867Sdelphij */ 1151252867Sdelphijtypedef struct _CREATE_ARRAY_PARAMS { 1152252867Sdelphij HPT_U8 ArrayType; /* 1-level array type */ 1153252867Sdelphij HPT_U8 nDisk; /* number of elements in Members[] array */ 1154252867Sdelphij HPT_U8 BlockSizeShift; /* Stripe size if ArrayType==AT_RAID0 / AT_RAID5 */ 1155252867Sdelphij HPT_U8 CreateFlags; /* See CAF_xxx */ 1156252867Sdelphij 1157252867Sdelphij HPT_U8 ArrayName[MAX_ARRAYNAME_LEN];/* Array name */ 1158252867Sdelphij HPT_U8 Description[64]; /* array description */ 1159252867Sdelphij HPT_U8 CreateManager[16]; /* who created it */ 1160252867Sdelphij TIME_RECORD CreateTime; /* when created it */ 1161252867Sdelphij 1162252867Sdelphij HPT_U32 Members[MAX_ARRAY_MEMBERS_V1];/* ID of array members, a member can be an array */ 1163252867Sdelphij 1164252867Sdelphij} CREATE_ARRAY_PARAMS, *PCREATE_ARRAY_PARAMS; 1165252867Sdelphij 1166252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000 1167252867Sdelphijtypedef struct _CREATE_ARRAY_PARAMS_V2 { 1168252867Sdelphij HPT_U8 ArrayType; /* 1-level array type */ 1169252867Sdelphij HPT_U8 nDisk; /* number of elements in Members[] array */ 1170252867Sdelphij HPT_U8 BlockSizeShift; /* Stripe size if ArrayType==AT_RAID0 / AT_RAID5 */ 1171252867Sdelphij HPT_U8 CreateFlags; /* See CAF_xxx */ 1172252867Sdelphij 1173252867Sdelphij HPT_U8 ArrayName[MAX_ARRAYNAME_LEN];/* Array name */ 1174252867Sdelphij HPT_U8 Description[64]; /* array description */ 1175252867Sdelphij HPT_U8 CreateManager[16]; /* who created it */ 1176252867Sdelphij TIME_RECORD CreateTime; /* when created it */ 1177252867Sdelphij HPT_U64 Capacity; 1178252867Sdelphij 1179252867Sdelphij HPT_U32 Members[MAX_ARRAY_MEMBERS_V2];/* ID of array members, a member can be an array */ 1180252867Sdelphij 1181252867Sdelphij} CREATE_ARRAY_PARAMS_V2, *PCREATE_ARRAY_PARAMS_V2; 1182252867Sdelphij#endif 1183252867Sdelphij 1184252867Sdelphij#if HPT_INTERFACE_VERSION>=0x02000001 1185252867Sdelphijtypedef struct _CREATE_ARRAY_PARAMS_V3 { 1186252867Sdelphij HPT_U32 dwSize; 1187252867Sdelphij HPT_U8 revision; /*CREATE_ARRAY_PARAMS_V3_REVISION*/ 1188252867Sdelphij HPT_U8 diskCachePolicy; /*unchange:0 enable:1 disable:2*/ 1189252867Sdelphij HPT_U8 reserved[4]; 1190252867Sdelphij HPT_U8 subDisks; /* RAIDn0 sub array */ 1191252867Sdelphij HPT_U8 SectorSizeShift; /*sector size = 512B<<SectorSizeShift*/ 1192252867Sdelphij HPT_U8 ArrayType; /* 1-level array type */ 1193252867Sdelphij HPT_U8 nDisk; /* number of elements in Members[] array */ 1194252867Sdelphij HPT_U8 BlockSizeShift; /* Stripe size if ArrayType==AT_RAID0 / AT_RAID5 */ 1195252867Sdelphij HPT_U8 CreateFlags; /* See CAF_xxx */ 1196252867Sdelphij 1197252867Sdelphij HPT_U8 ArrayName[MAX_ARRAYNAME_LEN];/* Array name */ 1198252867Sdelphij HPT_U8 Description[64]; /* array description */ 1199252867Sdelphij HPT_U8 CreateManager[16]; /* who created it */ 1200252867Sdelphij TIME_RECORD CreateTime; /* when created it */ 1201252867Sdelphij HPT_U64 Capacity; 1202252867Sdelphij 1203252867Sdelphij HPT_U32 Members[MAX_ARRAY_MEMBERS_V3];/* ID of array members, a member can be an array */ 1204252867Sdelphij} CREATE_ARRAY_PARAMS_V3, *PCREATE_ARRAY_PARAMS_V3; 1205252867Sdelphij 1206252867Sdelphij/*CREATE_ARRAY_PARAMS_V3 current max revision*/ 1207252867Sdelphij#define CREATE_ARRAY_PARAMS_V3_REVISION 0 1208252867Sdelphij/*If new revision defined please check evey revision size*/ 1209252867Sdelphij#define CREATE_ARRAY_PARAMS_V3_R0_SIZE (sizeof(CREATE_ARRAY_PARAMS_V3)) 1210252867Sdelphij#endif 1211252867Sdelphij 1212252867Sdelphij#if HPT_INTERFACE_VERSION < 0x01020000 1213252867Sdelphij/* 1214252867Sdelphij * Flags used for creating an RAID 1 array 1215252867Sdelphij * 1216252867Sdelphij * CAF_CREATE_AND_DUPLICATE 1217252867Sdelphij * Copy source disk contents to target for RAID 1. If user choose "create and duplicate" 1218252867Sdelphij * to create an array, GUI will call CreateArray() with this flag set. Then GUI should 1219252867Sdelphij * call hpt_get_device_info() with the returned array ID and check returned flags to 1220252867Sdelphij * see if ARRAY_FLAG_REBUILDING is set. If not set, driver does not support rebuilding 1221252867Sdelphij * and GUI must do duplication itself. 1222252867Sdelphij * CAF_DUPLICATE_MUST_DONE 1223252867Sdelphij * If the duplication is aborted or fails, do not create the array. 1224252867Sdelphij */ 1225252867Sdelphij#define CAF_CREATE_AND_DUPLICATE 1 1226252867Sdelphij#define CAF_DUPLICATE_MUST_DONE 2 1227252867Sdelphij#define CAF_CREATE_AS_RAID15 4 1228252867Sdelphij/* 1229252867Sdelphij * Flags used for creating an RAID 5 array 1230252867Sdelphij */ 1231252867Sdelphij#define CAF_CREATE_R5_NO_BUILD 1 1232252867Sdelphij#define CAF_CREATE_R5_ZERO_INIT 2 1233252867Sdelphij#define CAF_CREATE_R5_BUILD_PARITY 4 1234252867Sdelphij 1235252867Sdelphij#else 1236252867Sdelphij/* 1237252867Sdelphij * Flags used for creating 1238252867Sdelphij */ 1239252867Sdelphij#define CAF_FOREGROUND_INITIALIZE 1 1240252867Sdelphij#define CAF_BACKGROUND_INITIALIZE 2 1241252867Sdelphij#define CAF_CREATE_R5_WRITE_BACK (CACHE_POLICY_WRITE_BACK<<CAF_CACHE_POLICY_SHIFT) 1242252867Sdelphij 1243252867Sdelphij 1244252867Sdelphij#define CAF_CACHE_POLICY_MASK 0x1C 1245252867Sdelphij#define CAF_CACHE_POLICY_SHIFT 2 1246252867Sdelphij 1247252867Sdelphij#endif 1248252867Sdelphij 1249252867Sdelphij#define CAF_KEEP_DATA_ALWAYS 0x80 1250252867Sdelphij 1251252867Sdelphij/* Flags used for deleting an array 1252252867Sdelphij * 1253252867Sdelphij * DAF_KEEP_DATA_IF_POSSIBLE 1254252867Sdelphij * If this flag is set, deleting a RAID 1 array will not destroy the data on both disks. 1255252867Sdelphij * Deleting a JBOD should keep partitions on first disk ( not implement now ). 1256252867Sdelphij * Deleting a RAID 0/1 should result as two RAID 0 array ( not implement now ). 1257252867Sdelphij */ 1258252867Sdelphij#define DAF_KEEP_DATA_IF_POSSIBLE 1 1259252867Sdelphij#define DAF_KEEP_DATA_ALWAYS 2 1260252867Sdelphij 1261252867Sdelphij/* 1262252867Sdelphij * event types 1263252867Sdelphij */ 1264252867Sdelphij#define ET_DEVICE_REMOVED 1 /* device removed */ 1265252867Sdelphij#define ET_DEVICE_PLUGGED 2 /* device plugged */ 1266252867Sdelphij#define ET_DEVICE_ERROR 3 /* device I/O error */ 1267252867Sdelphij#define ET_REBUILD_STARTED 4 1268252867Sdelphij#define ET_REBUILD_ABORTED 5 1269252867Sdelphij#define ET_REBUILD_FINISHED 6 1270252867Sdelphij#define ET_SPARE_TOOK_OVER 7 1271252867Sdelphij#define ET_REBUILD_FAILED 8 1272252867Sdelphij#define ET_VERIFY_STARTED 9 1273252867Sdelphij#define ET_VERIFY_ABORTED 10 1274252867Sdelphij#define ET_VERIFY_FAILED 11 1275252867Sdelphij#define ET_VERIFY_FINISHED 12 1276252867Sdelphij#define ET_INITIALIZE_STARTED 13 1277252867Sdelphij#define ET_INITIALIZE_ABORTED 14 1278252867Sdelphij#define ET_INITIALIZE_FAILED 15 1279252867Sdelphij#define ET_INITIALIZE_FINISHED 16 1280252867Sdelphij#define ET_VERIFY_DATA_ERROR 17 1281252867Sdelphij#define ET_TRANSFORM_STARTED 18 1282252867Sdelphij#define ET_TRANSFORM_ABORTED 19 1283252867Sdelphij#define ET_TRANSFORM_FAILED 20 1284252867Sdelphij#define ET_TRANSFORM_FINISHED 21 1285252867Sdelphij#define ET_SMART_FAILED 22 1286252867Sdelphij#define ET_SMART_PASSED 23 1287252867Sdelphij#define ET_SECTOR_REPAIR_FAIL 24 1288252867Sdelphij#define ET_SECTOR_REPAIR_SUCCESS 25 1289252867Sdelphij#define ET_ERASE_FAIL 26 1290252867Sdelphij#define ET_ERASE_SUCCESS 27 1291252867Sdelphij#define ET_CONTINUE_REBUILD_ON_ERROR 28 1292252867Sdelphij 1293252867Sdelphij 1294252867Sdelphij/* 1295252867Sdelphij * event structure 1296252867Sdelphij */ 1297252867Sdelphijtypedef struct _HPT_EVENT { 1298252867Sdelphij TIME_RECORD Time; 1299252867Sdelphij DEVICEID DeviceID; 1300252867Sdelphij HPT_U8 EventType; 1301252867Sdelphij HPT_U8 reserved[3]; 1302252867Sdelphij 1303252867Sdelphij HPT_U8 Data[32]; /* various data depend on EventType */ 1304252867Sdelphij} HPT_EVENT, *PHPT_EVENT; 1305252867Sdelphij 1306252867Sdelphij/* 1307252867Sdelphij * IDE pass-through command. Use it at your own risk! 1308252867Sdelphij */ 1309252867Sdelphijtypedef struct _IDE_PASS_THROUGH_HEADER { 1310252867Sdelphij DEVICEID idDisk; /* disk ID */ 1311252867Sdelphij HPT_U8 bFeaturesReg; /* feature register */ 1312252867Sdelphij HPT_U8 bSectorCountReg; /* IDE sector count register. */ 1313252867Sdelphij HPT_U8 bLbaLowReg; /* IDE LBA low value. */ 1314252867Sdelphij HPT_U8 bLbaMidReg; /* IDE LBA mid register. */ 1315252867Sdelphij HPT_U8 bLbaHighReg; /* IDE LBA high value. */ 1316252867Sdelphij HPT_U8 bDriveHeadReg; /* IDE drive/head register. */ 1317252867Sdelphij HPT_U8 bCommandReg; /* Actual IDE command. Checked for validity by driver. */ 1318252867Sdelphij HPT_U8 nSectors; /* data size in sectors, if the command has data transfer */ 1319252867Sdelphij HPT_U8 protocol; /* IO_COMMAND_(READ,WRITE) or zero for non-DATA */ 1320252867Sdelphij HPT_U8 reserve[3]; 1321252867Sdelphij #define IDE_PASS_THROUGH_buffer(p) ((HPT_U8 *)(p) + sizeof(IDE_PASS_THROUGH_HEADER)) 1322252867Sdelphij /* HPT_U8 DataBuffer[0]; */ 1323252867Sdelphij} 1324252867SdelphijIDE_PASS_THROUGH_HEADER, *PIDE_PASS_THROUGH_HEADER; 1325252867Sdelphij 1326252867Sdelphijtypedef struct _IDE_PASS_THROUGH_HEADER_V2 { 1327252867Sdelphij DEVICEID idDisk; /* disk ID */ 1328252867Sdelphij HPT_U16 bFeaturesReg; /* feature register */ 1329252867Sdelphij HPT_U16 bSectorCountReg; /* IDE sector count register. */ 1330252867Sdelphij HPT_U16 bLbaLowReg; /* IDE LBA low value. */ 1331252867Sdelphij HPT_U16 bLbaMidReg; /* IDE LBA mid register. */ 1332252867Sdelphij HPT_U16 bLbaHighReg; /* IDE LBA high value. */ 1333252867Sdelphij HPT_U8 bDriveHeadReg; /* IDE drive/head register. */ 1334252867Sdelphij HPT_U8 bCommandReg; /* Actual IDE command. Checked for validity by driver. */ 1335252867Sdelphij HPT_U16 nSectors; /* data size in sectors, if the command has data transfer */ 1336252867Sdelphij HPT_U8 protocol; /* IO_COMMAND_(READ,WRITE) or zero for non-DATA */ 1337252867Sdelphij HPT_U8 reserve; 1338252867Sdelphij #define IDE_PASS_THROUGH_V2_buffer(p) ((HPT_U8 *)(p) + sizeof(IDE_PASS_THROUGH_HEADER_V2)) 1339252867Sdelphij /* HPT_U8 DataBuffer[0]; */ 1340252867Sdelphij} 1341252867SdelphijIDE_PASS_THROUGH_HEADER_V2, *PIDE_PASS_THROUGH_HEADER_V2; 1342252867Sdelphij 1343252867Sdelphijtypedef struct _HPT_SCSI_PASSTHROUGH_IN { 1344252867Sdelphij DEVICEID idDisk; 1345252867Sdelphij HPT_U8 protocol; 1346252867Sdelphij HPT_U8 reserve1; 1347252867Sdelphij HPT_U8 reserve2; 1348252867Sdelphij HPT_U8 cdbLength; 1349252867Sdelphij HPT_U8 cdb[16]; 1350252867Sdelphij HPT_U32 dataLength; 1351252867Sdelphij /* data follows, if any */ 1352252867Sdelphij} 1353252867SdelphijHPT_SCSI_PASSTHROUGH_IN, *PHPT_SCSI_PASSTHROUGH_IN; 1354252867Sdelphij 1355252867Sdelphijtypedef struct _HPT_SCSI_PASSTHROUGH_OUT { 1356252867Sdelphij HPT_U8 scsiStatus; 1357252867Sdelphij HPT_U8 reserve1; 1358252867Sdelphij HPT_U8 reserve2; 1359252867Sdelphij HPT_U8 reserve3; 1360252867Sdelphij HPT_U32 dataLength; 1361252867Sdelphij /* data/sense follows if any */ 1362252867Sdelphij} 1363252867SdelphijHPT_SCSI_PASSTHROUGH_OUT, *PHPT_SCSI_PASSTHROUGH_OUT; 1364252867Sdelphij 1365252867Sdelphij/* 1366252867Sdelphij * device io packet format 1367252867Sdelphij */ 1368252867Sdelphijtypedef struct _DEVICE_IO_EX_PARAMS { 1369252867Sdelphij DEVICEID idDisk; 1370252867Sdelphij HPT_U32 Lba; 1371252867Sdelphij HPT_U16 nSectors; 1372252867Sdelphij HPT_U8 Command; /* IO_COMMAD_xxx */ 1373252867Sdelphij HPT_U8 BufferType; /* BUFFER_TYPE_xxx, see below */ 1374252867Sdelphij HPT_U32 BufferPtr; 1375252867Sdelphij} 1376252867SdelphijDEVICE_IO_EX_PARAMS, *PDEVICE_IO_EX_PARAMS; 1377252867Sdelphij 1378252867Sdelphij#define BUFFER_TYPE_LOGICAL 1 /* logical pointer to buffer */ 1379252867Sdelphij#define BUFFER_TYPE_PHYSICAL 2 /* physical address of buffer */ 1380252867Sdelphij#define BUFFER_TYPE_LOGICAL_LOGICAL_SG 3 /* logical pointer to logical S/G table */ 1381252867Sdelphij#define BUFFER_TYPE_LOGICAL_PHYSICAL_SG 4 /* logical pointer to physical S/G table */ 1382252867Sdelphij#define BUFFER_TYPE_PHYSICAL_LOGICAL_SG 5 /* physical address to logical S/G table */ 1383252867Sdelphij#define BUFFER_TYPE_PHYSICAL_PHYSICAL_SG 6 /* physical address of physical S/G table */ 1384252867Sdelphij#define BUFFER_TYPE_PHYSICAL_PHYSICAL_SG_PIO 7 /* non DMA capable physical address of physical S/G table */ 1385252867Sdelphij 1386252867Sdelphijtypedef struct _HPT_DRIVER_PARAMETER { 1387252867Sdelphij char name[32]; 1388252867Sdelphij HPT_U8 value[32]; 1389252867Sdelphij HPT_U8 type; /* HPT_DRIVER_PARAMETER_TYPE_* */ 1390252867Sdelphij HPT_U8 persistent; 1391252867Sdelphij HPT_U8 reserve2[2]; 1392252867Sdelphij HPT_U8 location; /* 0 - system */ 1393252867Sdelphij HPT_U8 controller; 1394252867Sdelphij HPT_U8 bus; 1395252867Sdelphij HPT_U8 reserve1; 1396252867Sdelphij char desc[128]; 1397252867Sdelphij} 1398252867SdelphijHPT_DRIVER_PARAMETER, *PHPT_DRIVER_PARAMETER; 1399252867Sdelphij 1400252867Sdelphij#define HPT_DRIVER_PARAMETER_TYPE_INT 1 1401252867Sdelphij#define HPT_DRIVER_PARAMETER_TYPE_BOOL 2 1402252867Sdelphij 1403252867Sdelphijtypedef struct _HPT_PM_CMDSTAT { 1404252867Sdelphij HPT_U64 timeStamp; 1405252867Sdelphij HPT_U64 lba; 1406252867Sdelphij HPT_U16 sectors; 1407252867Sdelphij HPT_U16 reserved; 1408252867Sdelphij HPT_U32 rspTime; 1409252867Sdelphij} 1410252867SdelphijHPT_PM_CMDSTAT, *PHPT_PM_CMDSTAT; 1411252867Sdelphij 1412252867Sdelphij#define HIGHEST_RSPTIME_CMD_SAVE 10 1413252867Sdelphij#define RSPTIME_HISTOGRAM_SEGMENT_COUNT 38 1414252867Sdelphij 1415252867Sdelphijtypedef struct _HPT_PM_IOSTAT { 1416252867Sdelphij HPT_PM_CMDSTAT highestRspCmdStatData[HIGHEST_RSPTIME_CMD_SAVE]; 1417252867Sdelphij HPT_U32 rspTimeHistogram[RSPTIME_HISTOGRAM_SEGMENT_COUNT]; 1418252867Sdelphij HPT_U16 pendingIo; 1419252867Sdelphij HPT_U16 activeIo; 1420252867Sdelphij HPT_U32 instantKBPs; 1421252867Sdelphij HPT_U32 averageKBPs; 1422252867Sdelphij HPT_U32 instantIOPs; 1423252867Sdelphij HPT_U32 averageIOPs; 1424252867Sdelphij} 1425252867SdelphijHPT_PM_IOSTAT, *PHPT_PM_IOSTAT; 1426252867Sdelphij 1427252867Sdelphij/* 1428252867Sdelphij * disk config region 1429252867Sdelphij */ 1430252867Sdelphijtypedef struct _ACCESS_CONFIG_REG { 1431252867Sdelphij DEVICEID id; 1432252867Sdelphij HPT_U16 start; 1433252867Sdelphij HPT_U8 sectors; 1434252867Sdelphij HPT_U8 read; 1435252867Sdelphij HPT_U32 Reserved; 1436252867Sdelphij #define ACCESS_CONFIG_REG_buffer(p) ((HPT_U8 *)(p) + sizeof(ACCESS_CONFIG_REG_PARAMS)) 1437252867Sdelphij} __attribute__((packed))ACCESS_CONFIG_REG_PARAMS, *PACCESS_CONFIG_REG_PARAMS; 1438252867Sdelphij 1439252867Sdelphij/* 1440252867Sdelphij * dump meta data 1441252867Sdelphij */ 1442252867Sdelphijtypedef struct _DUMP_METADATA { 1443252867Sdelphij DEVICEID id; 1444252867Sdelphij HPT_U8 sectors; 1445252867Sdelphij HPT_U8 backsectors; 1446252867Sdelphij HPT_U8 offset; 1447252867Sdelphij HPT_U8 backoffset; 1448252867Sdelphij} __attribute__((packed))DUMP_METADATA_PARAMS, *PDUMP_METADATA_PARAMS; 1449252867Sdelphij 1450252867Sdelphij 1451252867Sdelphij 1452252867Sdelphij/* 1453252867Sdelphij * ioctl structure 1454252867Sdelphij */ 1455252867Sdelphij#define HPT_IOCTL_MAGIC32 0x1A2B3C4D 1456252867Sdelphij#define HPT_IOCTL_MAGIC 0xA1B2C3D4 1457252867Sdelphij 1458252867Sdelphijtypedef struct _HPT_IOCTL_PARAM { 1459252867Sdelphij HPT_U32 Magic; /* used to check if it's a valid ioctl packet */ 1460252867Sdelphij HPT_U32 dwIoControlCode; /* operation control code */ 1461252867Sdelphij HPT_PTR lpInBuffer; /* input data buffer */ 1462252867Sdelphij HPT_U32 nInBufferSize; /* size of input data buffer */ 1463252867Sdelphij HPT_PTR lpOutBuffer; /* output data buffer */ 1464252867Sdelphij HPT_U32 nOutBufferSize; /* size of output data buffer */ 1465252867Sdelphij HPT_PTR lpBytesReturned; /* count of HPT_U8s returned */ 1466252867Sdelphij} 1467252867SdelphijHPT_IOCTL_PARAM, *PHPT_IOCTL_PARAM; 1468252867Sdelphij 1469252867Sdelphij/* for 32-bit app running on 64-bit system */ 1470252867Sdelphijtypedef struct _HPT_IOCTL_PARAM32 { 1471252867Sdelphij HPT_U32 Magic; 1472252867Sdelphij HPT_U32 dwIoControlCode; 1473252867Sdelphij HPT_U32 lpInBuffer; 1474252867Sdelphij HPT_U32 nInBufferSize; 1475252867Sdelphij HPT_U32 lpOutBuffer; 1476252867Sdelphij HPT_U32 nOutBufferSize; 1477252867Sdelphij HPT_U32 lpBytesReturned; 1478252867Sdelphij} 1479252867SdelphijHPT_IOCTL_PARAM32, *PHPT_IOCTL_PARAM32; 1480252867Sdelphij 1481252867Sdelphij#if !defined(__KERNEL__) || defined(SIMULATE) 1482252867Sdelphij/* 1483252867Sdelphij * User-mode ioctl parameter passing conventions: 1484252867Sdelphij * The ioctl function implementation is platform specific, so we don't 1485252867Sdelphij * have forced rules for it. However, it's suggested to use a parameter 1486252867Sdelphij * passing method as below 1487252867Sdelphij * 1) Put all input data continuously in an input buffer. 1488252867Sdelphij * 2) Prepare an output buffer with enough size if needed. 1489252867Sdelphij * 3) Fill a HPT_IOCTL_PARAM structure. 1490252867Sdelphij * 4) Pass the structure to driver through a platform-specific method. 1491252867Sdelphij * This is implemented in the mid-layer user-mode library. The UI 1492252867Sdelphij * programmer needn't care about it. 1493252867Sdelphij */ 1494252867Sdelphij 1495252867Sdelphij/************************************************************************ 1496252867Sdelphij * User mode functions 1497252867Sdelphij ************************************************************************/ 1498252867Sdelphij/* 1499252867Sdelphij * hpt_get_version 1500252867Sdelphij * Version compatibility: all versions 1501252867Sdelphij * Parameters: 1502252867Sdelphij * None 1503252867Sdelphij * Returns: 1504252867Sdelphij * interface version. 0 when fail. 1505252867Sdelphij */ 1506252867SdelphijHPT_U32 hpt_get_version(void); 1507252867Sdelphij 1508252867Sdelphij/* 1509252867Sdelphij * hpt_get_driver_capabilities 1510252867Sdelphij * Version compatibility: v1.0.0.2 or later 1511252867Sdelphij * Parameters: 1512252867Sdelphij * Pointer to receive a DRIVE_CAPABILITIES structure. The caller must set 1513252867Sdelphij * dwSize member to sizeof(DRIVER_CAPABILITIES). The callee must check this 1514252867Sdelphij * member to see if it's correct. 1515252867Sdelphij * Returns: 1516252867Sdelphij * 0 - Success 1517252867Sdelphij */ 1518252867Sdelphijint hpt_get_driver_capabilities(PDRIVER_CAPABILITIES cap); 1519252867Sdelphijint hpt_get_driver_capabilities_v2(PDRIVER_CAPABILITIES_V2 cap); 1520252867Sdelphij 1521252867Sdelphij/* 1522252867Sdelphij * hpt_get_controller_count 1523252867Sdelphij * Version compatibility: v1.0.0.1 or later 1524252867Sdelphij * Parameters: 1525252867Sdelphij * None 1526252867Sdelphij * Returns: 1527252867Sdelphij * number of controllers 1528252867Sdelphij */ 1529252867Sdelphijint hpt_get_controller_count(void); 1530252867Sdelphij 1531252867Sdelphij/* hpt_get_controller_info 1532252867Sdelphij * Version compatibility: v1.0.0.1 or later 1533252867Sdelphij * Parameters: 1534252867Sdelphij * id Controller id 1535252867Sdelphij * pInfo pointer to CONTROLLER_INFO buffer 1536252867Sdelphij * Returns: 1537252867Sdelphij * 0 Success, controller info is put into (*pInfo ). 1538252867Sdelphij */ 1539252867Sdelphijint hpt_get_controller_info(int id, PCONTROLLER_INFO pInfo); 1540252867Sdelphij 1541252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000 1542252867Sdelphij/* hpt_get_controller_info_v2 1543252867Sdelphij * Version compatibility: v2.0.0.0 or later 1544252867Sdelphij * Parameters: 1545252867Sdelphij * id Controller id 1546252867Sdelphij * pInfo pointer to CONTROLLER_INFO_V2 buffer 1547252867Sdelphij * Returns: 1548252867Sdelphij * 0 Success, controller info is put into (*pInfo ). 1549252867Sdelphij */ 1550252867Sdelphijint hpt_get_controller_info_v2(int id, PCONTROLLER_INFO_V2 pInfo); 1551252867Sdelphij 1552252867Sdelphij/* hpt_get_controller_info_v2_ext 1553252867Sdelphij * Version compatibility: v2.0.0.0 or later 1554252867Sdelphij * Parameters: 1555252867Sdelphij * id Controller id 1556252867Sdelphij * pInfo pointer to CONTROLLER_INFO_V2_EXT buffer 1557252867Sdelphij * Returns: 1558252867Sdelphij * 0 Success, controller info is put into (*pInfo ). 1559252867Sdelphij */ 1560252867Sdelphijint hpt_get_controller_info_v2_ext(int id, PCONTROLLER_INFO_V2_EXT pInfo); 1561252867Sdelphij 1562252867Sdelphij/* hpt_get_controller_info_v3 1563252867Sdelphij * Version compatibility: v2.0.0.0 or later 1564252867Sdelphij * Parameters: 1565252867Sdelphij * id Controller id 1566252867Sdelphij * pInfo pointer to CONTROLLER_INFO_V3 buffer 1567252867Sdelphij * Returns: 1568252867Sdelphij * 0 Success, controller info is put into (*pInfo ). 1569252867Sdelphij */ 1570252867Sdelphijint hpt_get_controller_info_v3(int id, PCONTROLLER_INFO_V3 pInfo); 1571252867Sdelphij#endif 1572252867Sdelphij 1573252867Sdelphij/* hpt_get_channel_info 1574252867Sdelphij * Version compatibility: v1.0.0.1 or later 1575252867Sdelphij * Parameters: 1576252867Sdelphij * id Controller id 1577252867Sdelphij * bus bus number 1578252867Sdelphij * pInfo pointer to CHANNEL_INFO buffer 1579252867Sdelphij * Returns: 1580252867Sdelphij * 0 Success, channel info is put into (*pInfo ). 1581252867Sdelphij */ 1582252867Sdelphijint hpt_get_channel_info(int id, int bus, PCHANNEL_INFO pInfo); 1583252867Sdelphij 1584252867Sdelphij/* hpt_get_channel_info_v2 1585252867Sdelphij * Version compatibility: v1.0.0.1 or later 1586252867Sdelphij * Parameters: 1587252867Sdelphij * id Controller id 1588252867Sdelphij * bus bus number 1589252867Sdelphij * pInfo pointer to CHANNEL_INFO buffer 1590252867Sdelphij * Returns: 1591252867Sdelphij * 0 Success, channel info is put into (*pInfo ). 1592252867Sdelphij */ 1593252867Sdelphijint hpt_get_channel_info_v2(int id, int bus, PCHANNEL_INFO_V2 pInfo); 1594252867Sdelphij 1595252867Sdelphij/* hpt_get_logical_devices 1596252867Sdelphij * Version compatibility: v1.0.0.1 or later 1597252867Sdelphij * Parameters: 1598252867Sdelphij * pIds pointer to a DEVICEID array 1599252867Sdelphij * nMaxCount array size 1600252867Sdelphij * Returns: 1601252867Sdelphij * Number of ID returned. All logical device IDs are put into pIds array. 1602252867Sdelphij * Note: A spare disk is not a logical device. 1603252867Sdelphij */ 1604252867Sdelphijint hpt_get_logical_devices(DEVICEID * pIds, int nMaxCount); 1605252867Sdelphij 1606252867Sdelphij/* hpt_get_physical_devices 1607252867Sdelphij * Version compatibility: v2.1.0.0 or later 1608252867Sdelphij * Parameters: 1609252867Sdelphij * pIds pointer to a DEVICEID array 1610252867Sdelphij * nMaxCount array size 1611252867Sdelphij * Returns: 1612252867Sdelphij * Number of ID returned. All physical device IDs are put into pIds array. 1613252867Sdelphij */ 1614252867Sdelphijint hpt_get_physical_devices(DEVICEID * pIds, int nMaxCount); 1615252867Sdelphij 1616252867Sdelphij/* hpt_get_device_info 1617252867Sdelphij * Version compatibility: v1.0.0.1 or later 1618252867Sdelphij * Parameters: 1619252867Sdelphij * id logical device id 1620252867Sdelphij * pInfo pointer to LOGICAL_DEVICE_INFO structure 1621252867Sdelphij * Returns: 1622252867Sdelphij * 0 - Success 1623252867Sdelphij */ 1624252867Sdelphijint hpt_get_device_info(DEVICEID id, PLOGICAL_DEVICE_INFO pInfo); 1625252867Sdelphij 1626252867Sdelphij/* hpt_create_array 1627252867Sdelphij * Version compatibility: v1.0.0.1 or later 1628252867Sdelphij * Parameters: 1629252867Sdelphij * pParam pointer to CREATE_ARRAY_PARAMS structure 1630252867Sdelphij * Returns: 1631252867Sdelphij * 0 failed 1632252867Sdelphij * else return array id 1633252867Sdelphij */ 1634252867SdelphijDEVICEID hpt_create_array(PCREATE_ARRAY_PARAMS pParam); 1635252867Sdelphij 1636252867Sdelphij/* hpt_delete_array 1637252867Sdelphij * Version compatibility: v1.0.0.1 or later 1638252867Sdelphij * Parameters: 1639252867Sdelphij * id array id 1640252867Sdelphij * Returns: 1641252867Sdelphij * 0 Success 1642252867Sdelphij */ 1643252867Sdelphijint hpt_delete_array(DEVICEID id, HPT_U32 options); 1644252867Sdelphij 1645252867Sdelphij/* hpt_device_io 1646252867Sdelphij * Read/write data on array and physcal device. 1647252867Sdelphij * Version compatibility: v1.0.0.1 or later 1648252867Sdelphij * Parameters: 1649252867Sdelphij * id device id. If it's an array ID, IO will be performed on the array. 1650252867Sdelphij * If it's a physical device ID, IO will be performed on the device. 1651252867Sdelphij * cmd IO_COMMAND_READ or IO_COMMAND_WRITE 1652252867Sdelphij * buffer data buffer 1653252867Sdelphij * length data size 1654252867Sdelphij * Returns: 1655252867Sdelphij * 0 Success 1656252867Sdelphij */ 1657252867Sdelphijint hpt_device_io(DEVICEID id, int cmd, HPT_U32 lba, HPT_U32 nSector, void * buffer); 1658252867Sdelphij 1659252867Sdelphij/* hpt_add_disk_to_array 1660252867Sdelphij * Used to dynamicly add a disk to an RAID1, RAID0/1, RAID1/0 or RAID5 array. 1661252867Sdelphij * Auto-rebuild will start. 1662252867Sdelphij * Version compatibility: v1.0.0.1 or later 1663252867Sdelphij * Parameters: 1664252867Sdelphij * idArray array id 1665252867Sdelphij * idDisk disk id 1666252867Sdelphij * Returns: 1667252867Sdelphij * 0 Success 1668252867Sdelphij */ 1669252867Sdelphijint hpt_add_disk_to_array(DEVICEID idArray, DEVICEID idDisk); 1670252867Sdelphij 1671252867Sdelphij/* hpt_add_spare_disk 1672252867Sdelphij * Version compatibility: v1.0.0.1 or later 1673252867Sdelphij * Add a disk to spare pool. 1674252867Sdelphij * Parameters: 1675252867Sdelphij * idDisk disk id 1676252867Sdelphij * Returns: 1677252867Sdelphij * 0 Success 1678252867Sdelphij */ 1679252867Sdelphijint hpt_add_spare_disk(DEVICEID idDisk); 1680252867Sdelphij 1681252867Sdelphij/* hpt_add_dedicated_spare 1682252867Sdelphij * Version compatibility: v1.0.0.3 or later 1683252867Sdelphij * Add a spare disk to an array 1684252867Sdelphij * Parameters: 1685252867Sdelphij * idDisk disk id 1686252867Sdelphij * idArray array id 1687252867Sdelphij * Returns: 1688252867Sdelphij * 0 Success 1689252867Sdelphij */ 1690252867Sdelphijint hpt_add_dedicated_spare(DEVICEID idDisk, DEVICEID idArray); 1691252867Sdelphij 1692252867Sdelphij/* hpt_remove_spare_disk 1693252867Sdelphij * remove a disk from spare pool. 1694252867Sdelphij * Version compatibility: v1.0.0.1 or later 1695252867Sdelphij * Parameters: 1696252867Sdelphij * idDisk disk id 1697252867Sdelphij * Returns: 1698252867Sdelphij * 0 Success 1699252867Sdelphij */ 1700252867Sdelphijint hpt_remove_spare_disk(DEVICEID idDisk); 1701252867Sdelphij 1702252867Sdelphij/* hpt_get_event 1703252867Sdelphij * Used to poll events from driver. 1704252867Sdelphij * Version compatibility: v1.0.0.1 or later 1705252867Sdelphij * Parameters: 1706252867Sdelphij * pEvent pointer to HPT_EVENT structure 1707252867Sdelphij * Returns: 1708252867Sdelphij * 0 Success, event info is filled in *pEvent 1709252867Sdelphij */ 1710252867Sdelphijint hpt_get_event(PHPT_EVENT pEvent); 1711252867Sdelphij 1712252867Sdelphij/* hpt_rebuild_data_block 1713252867Sdelphij * Used to copy data from source disk and mirror disk. 1714252867Sdelphij * Version compatibility: v1.0.0.1 or later 1715252867Sdelphij * Parameters: 1716252867Sdelphij * idArray Array ID (RAID1, 0/1 or RAID5) 1717252867Sdelphij * Lba Start LBA for each array member 1718252867Sdelphij * nSector Number of sectors for each array member (RAID 5 will ignore this parameter) 1719252867Sdelphij * 1720252867Sdelphij * Returns: 1721252867Sdelphij * 0 Success, event info is filled in *pEvent 1722252867Sdelphij */ 1723252867Sdelphijint hpt_rebuild_data_block(DEVICEID idMirror, HPT_U32 Lba, HPT_U8 nSector); 1724252867Sdelphij#define hpt_rebuild_mirror(p1, p2, p3) hpt_rebuild_data_block(p1, p2, p3) 1725252867Sdelphij 1726252867Sdelphij/* hpt_set_array_state 1727252867Sdelphij * set array state. 1728252867Sdelphij * Version compatibility: v1.0.0.1 or later 1729252867Sdelphij * Parameters: 1730252867Sdelphij * idArray Array ID 1731252867Sdelphij * state See above 'array states' constants, possible values are: 1732252867Sdelphij * MIRROR_REBUILD_START 1733252867Sdelphij * Indicate that GUI wants to rebuild a mirror array 1734252867Sdelphij * MIRROR_REBUILD_ABORT 1735252867Sdelphij * GUI wants to abort rebuilding an array 1736252867Sdelphij * MIRROR_REBUILD_COMPLETE 1737252867Sdelphij * GUI finished to rebuild an array. If rebuild is done by driver this 1738252867Sdelphij * state has no use 1739252867Sdelphij * 1740252867Sdelphij * Returns: 1741252867Sdelphij * 0 Success 1742252867Sdelphij */ 1743252867Sdelphijint hpt_set_array_state(DEVICEID idArray, HPT_U32 state); 1744252867Sdelphij 1745252867Sdelphij/* hpt_set_array_info 1746252867Sdelphij * set array info. 1747252867Sdelphij * Version compatibility: v1.0.0.1 or later 1748252867Sdelphij * Parameters: 1749252867Sdelphij * idArray Array ID 1750252867Sdelphij * pInfo pointer to new info 1751252867Sdelphij * 1752252867Sdelphij * Returns: 1753252867Sdelphij * 0 Success 1754252867Sdelphij */ 1755252867Sdelphijint hpt_set_array_info(DEVICEID idArray, PALTERABLE_ARRAY_INFO pInfo); 1756252867Sdelphij 1757252867Sdelphij/* hpt_set_device_info 1758252867Sdelphij * set device info. 1759252867Sdelphij * Version compatibility: v1.0.0.1 or later 1760252867Sdelphij * Parameters: 1761252867Sdelphij * idDisk device ID 1762252867Sdelphij * pInfo pointer to new info 1763252867Sdelphij * 1764252867Sdelphij * Returns: 1765252867Sdelphij * 0 Success 1766252867Sdelphij * Additional notes: 1767252867Sdelphij * If idDisk==0, call to this function will stop buzzer on the adapter 1768252867Sdelphij * (if supported by driver). 1769252867Sdelphij */ 1770252867Sdelphijint hpt_set_device_info(DEVICEID idDisk, PALTERABLE_DEVICE_INFO pInfo); 1771252867Sdelphij 1772252867Sdelphij#if HPT_INTERFACE_VERSION >= 0x01000004 1773252867Sdelphijint hpt_set_device_info_v2(DEVICEID idDisk, PALTERABLE_DEVICE_INFO_V2 pInfo); 1774252867Sdelphij#endif 1775252867Sdelphij 1776252867Sdelphij/* hpt_rescan_devices 1777252867Sdelphij * rescan devices 1778252867Sdelphij * Version compatibility: v1.0.0.1 or later 1779252867Sdelphij * Parameters: 1780252867Sdelphij * None 1781252867Sdelphij * Returns: 1782252867Sdelphij * 0 Success 1783252867Sdelphij */ 1784252867Sdelphijint hpt_rescan_devices(void); 1785252867Sdelphij 1786252867Sdelphij/* hpt_get_601_info 1787252867Sdelphij * Get HPT601 status 1788252867Sdelphij * Version compatibiilty: v1.0.0.3 or later 1789252867Sdelphij * Parameters: 1790252867Sdelphij * idDisk - Disk handle 1791252867Sdelphij * PHPT601_INFO - pointer to HPT601 info buffer 1792252867Sdelphij * Returns: 1793252867Sdelphij * 0 Success 1794252867Sdelphij */ 1795252867Sdelphijint hpt_get_601_info(DEVICEID idDisk, PHPT601_INFO pInfo); 1796252867Sdelphij 1797252867Sdelphij/* hpt_set_601_info 1798252867Sdelphij * HPT601 function control 1799252867Sdelphij * Version compatibiilty: v1.0.0.3 or later 1800252867Sdelphij * Parameters: 1801252867Sdelphij * idDisk - Disk handle 1802252867Sdelphij * PHPT601_INFO - pointer to HPT601 info buffer 1803252867Sdelphij * Returns: 1804252867Sdelphij * 0 Success 1805252867Sdelphij */ 1806252867Sdelphijint hpt_set_601_info(DEVICEID idDisk, PHPT601_INFO pInfo); 1807252867Sdelphij 1808252867Sdelphij/* hpt_lock_device 1809252867Sdelphij * Lock a block on a device (prevent OS accessing it) 1810252867Sdelphij * Version compatibiilty: v1.0.0.3 or later 1811252867Sdelphij * Parameters: 1812252867Sdelphij * idDisk - Disk handle 1813252867Sdelphij * Lba - Start LBA 1814252867Sdelphij * nSectors - number of sectors 1815252867Sdelphij * Returns: 1816252867Sdelphij * 0 Success 1817252867Sdelphij */ 1818252867Sdelphijint hpt_lock_device(DEVICEID idDisk, HPT_U32 Lba, HPT_U8 nSectors); 1819252867Sdelphij 1820252867Sdelphij/* hpt_lock_device 1821252867Sdelphij * Unlock a device 1822252867Sdelphij * Version compatibiilty: v1.0.0.3 or later 1823252867Sdelphij * Parameters: 1824252867Sdelphij * idDisk - Disk handle 1825252867Sdelphij * Returns: 1826252867Sdelphij * 0 Success 1827252867Sdelphij */ 1828252867Sdelphijint hpt_unlock_device(DEVICEID idDisk); 1829252867Sdelphij 1830252867Sdelphij/* hpt_ide_pass_through 1831252867Sdelphij * send a ATA passthrough command to a device. 1832252867Sdelphij * Version compatibility: v1.0.0.3 or later 1833252867Sdelphij * Parameters: 1834252867Sdelphij * p - IDE_PASS_THROUGH header pointer 1835252867Sdelphij * Returns: 1836252867Sdelphij * 0 Success 1837252867Sdelphij */ 1838252867Sdelphijint hpt_ide_pass_through(PIDE_PASS_THROUGH_HEADER p); 1839252867Sdelphijint hpt_ide_pass_through_v2(PIDE_PASS_THROUGH_HEADER_V2 p); 1840252867Sdelphij 1841252867Sdelphij/* hpt_scsi_passthrough 1842252867Sdelphij * send a SCSI passthrough command to a device. 1843252867Sdelphij * Version compatibility: v2.0.0.0 or later 1844252867Sdelphij * Parameters: 1845252867Sdelphij * in - HPT_SCSI_PASSTHROUGH_IN header pointer 1846252867Sdelphij * out - PHPT_SCSI_PASSTHROUGH_OUT header pointer 1847252867Sdelphij * insize, outsize - in/out buffer size 1848252867Sdelphij * Returns: 1849252867Sdelphij * 0 Success 1850252867Sdelphij */ 1851252867Sdelphijint hpt_scsi_passthrough(PHPT_SCSI_PASSTHROUGH_IN in, HPT_U32 insize, 1852252867Sdelphij PHPT_SCSI_PASSTHROUGH_OUT out, HPT_U32 outsize); 1853252867Sdelphij 1854252867Sdelphij/* hpt_verify_data_block 1855252867Sdelphij * verify data block on RAID1 or RAID5. 1856252867Sdelphij * Version compatibility: v1.0.0.3 or later 1857252867Sdelphij * Parameters: 1858252867Sdelphij * idArray - Array ID 1859252867Sdelphij * Lba - block number (on each array member, not logical block!) 1860252867Sdelphij * nSectors - Sectors for each member (RAID 5 will ignore this parameter) 1861252867Sdelphij * Returns: 1862252867Sdelphij * 0 Success 1863252867Sdelphij * 1 Data compare error 1864252867Sdelphij * 2 I/O error 1865252867Sdelphij */ 1866252867Sdelphijint hpt_verify_data_block(DEVICEID idArray, HPT_U32 Lba, HPT_U8 nSectors); 1867252867Sdelphij 1868252867Sdelphij/* hpt_initialize_data_block 1869252867Sdelphij * initialize data block (fill with zero) on RAID5 1870252867Sdelphij * Version compatibility: v1.0.0.3 or later 1871252867Sdelphij * Parameters: 1872252867Sdelphij * idArray - Array ID 1873252867Sdelphij * Lba - block number (on each array member, not logical block!) 1874252867Sdelphij * nSectors - Sectors for each member (RAID 5 will ignore this parameter) 1875252867Sdelphij * Returns: 1876252867Sdelphij * 0 Success 1877252867Sdelphij */ 1878252867Sdelphijint hpt_initialize_data_block(DEVICEID idArray, HPT_U32 Lba, HPT_U8 nSectors); 1879252867Sdelphij 1880252867Sdelphij/* hpt_device_io_ex 1881252867Sdelphij * extended device I/O function 1882252867Sdelphij * Version compatibility: v1.0.0.3 or later 1883252867Sdelphij * Parameters: 1884252867Sdelphij * idArray - Array ID 1885252867Sdelphij * Lba - block number (on each array member, not logical block!) 1886252867Sdelphij * nSectors - Sectors for each member 1887252867Sdelphij * buffer - I/O buffer or s/g address 1888252867Sdelphij * Returns: 1889252867Sdelphij * 0 Success 1890252867Sdelphij */ 1891252867Sdelphijint hpt_device_io_ex(PDEVICE_IO_EX_PARAMS param); 1892252867Sdelphij 1893252867Sdelphij/* hpt_set_boot_mark 1894252867Sdelphij * select boot device 1895252867Sdelphij * Version compatibility: v1.0.0.3 or later 1896252867Sdelphij * Parameters: 1897252867Sdelphij * id - logical device ID. If id is 0 the boot mark will be removed. 1898252867Sdelphij * Returns: 1899252867Sdelphij * 0 Success 1900252867Sdelphij */ 1901252867Sdelphijint hpt_set_boot_mark(DEVICEID id); 1902252867Sdelphij 1903252867Sdelphij/* hpt_query_remove 1904252867Sdelphij * check if device can be removed safely 1905252867Sdelphij * Version compatibility: v1.0.0.4 or later 1906252867Sdelphij * Parameters: 1907252867Sdelphij * ndev - number of devices 1908252867Sdelphij * pIds - device ID list 1909252867Sdelphij * Returns: 1910252867Sdelphij * 0 - Success 1911252867Sdelphij * -1 - unknown error 1912252867Sdelphij * n - the n-th device that can't be removed 1913252867Sdelphij */ 1914252867Sdelphijint hpt_query_remove(HPT_U32 ndev, DEVICEID *pIds); 1915252867Sdelphij 1916252867Sdelphij/* hpt_remove_devices 1917252867Sdelphij * remove a list of devices 1918252867Sdelphij * Version compatibility: v1.0.0.4 or later 1919252867Sdelphij * Parameters: 1920252867Sdelphij * ndev - number of devices 1921252867Sdelphij * pIds - device ID list 1922252867Sdelphij * Returns: 1923252867Sdelphij * 0 - Success 1924252867Sdelphij * -1 - unknown error 1925252867Sdelphij * n - the n-th device that can't be removed 1926252867Sdelphij */ 1927252867Sdelphijint hpt_remove_devices(HPT_U32 ndev, DEVICEID *pIds); 1928252867Sdelphij 1929252867Sdelphij/* hpt_create_array_v2 1930252867Sdelphij * Version compatibility: v1.1.0.0 or later 1931252867Sdelphij * Parameters: 1932252867Sdelphij * pParam pointer to CREATE_ARRAY_PARAMS_V2 structure 1933252867Sdelphij * Returns: 1934252867Sdelphij * 0 failed 1935252867Sdelphij * else return array id 1936252867Sdelphij */ 1937252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000 1938252867SdelphijDEVICEID hpt_create_array_v2(PCREATE_ARRAY_PARAMS_V2 pParam); 1939252867Sdelphij#endif 1940252867Sdelphij 1941252867Sdelphij/* hpt_create_array_v3 1942252867Sdelphij * Version compatibility: v2.0.0.1 or later 1943252867Sdelphij * Parameters: 1944252867Sdelphij * pParam pointer to CREATE_ARRAY_PARAMS_V3 structure 1945252867Sdelphij * Returns: 1946252867Sdelphij * 0 failed 1947252867Sdelphij * else return array id 1948252867Sdelphij */ 1949252867Sdelphij#if HPT_INTERFACE_VERSION>=0x02000001 1950252867SdelphijDEVICEID hpt_create_array_v3(PCREATE_ARRAY_PARAMS_V3 pParam); 1951252867Sdelphij#endif 1952252867Sdelphij 1953252867Sdelphij/* hpt_get_device_info_v2 1954252867Sdelphij * Version compatibility: v1.1.0.0 or later 1955252867Sdelphij * Parameters: 1956252867Sdelphij * id logical device id 1957252867Sdelphij * pInfo pointer to LOGICAL_DEVICE_INFO_V2 structure 1958252867Sdelphij * Returns: 1959252867Sdelphij * 0 - Success 1960252867Sdelphij */ 1961252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000 1962252867Sdelphijint hpt_get_device_info_v2(DEVICEID id, PLOGICAL_DEVICE_INFO_V2 pInfo); 1963252867Sdelphij#endif 1964252867Sdelphij 1965252867Sdelphij/* hpt_get_device_info_v3 1966252867Sdelphij * Version compatibility: v1.2.0.0 or later 1967252867Sdelphij * Parameters: 1968252867Sdelphij * id logical device id 1969252867Sdelphij * pInfo pointer to LOGICAL_DEVICE_INFO_V3 structure 1970252867Sdelphij * Returns: 1971252867Sdelphij * 0 - Success 1972252867Sdelphij */ 1973252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000 1974252867Sdelphijint hpt_get_device_info_v3(DEVICEID id, PLOGICAL_DEVICE_INFO_V3 pInfo); 1975252867Sdelphij#endif 1976252867Sdelphij 1977252867Sdelphij/* hpt_get_device_info_v4 1978252867Sdelphij * Version compatibility: v2.0.0.1 or later 1979252867Sdelphij * Parameters: 1980252867Sdelphij * id logical device id 1981252867Sdelphij * pInfo pointer to LOGICAL_DEVICE_INFO_V4 structure 1982252867Sdelphij * Returns: 1983252867Sdelphij * 0 - Success 1984252867Sdelphij */ 1985252867Sdelphij#if HPT_INTERFACE_VERSION>=0x02000001 1986252867Sdelphijint hpt_get_device_info_v4(DEVICEID id, PLOGICAL_DEVICE_INFO_V4 pInfo); 1987252867Sdelphij#endif 1988252867Sdelphij 1989252867Sdelphij/* hpt_create_transform 1990252867Sdelphij * create a transform instance. 1991252867Sdelphij * Version compatibility: v2.0.0.0 or later 1992252867Sdelphij * Parameters: 1993252867Sdelphij * idArray - source array 1994252867Sdelphij * destInfo - destination array info 1995252867Sdelphij * Returns: 1996252867Sdelphij * destination array id 1997252867Sdelphij */ 1998252867Sdelphij#if HPT_INTERFACE_VERSION>=0x02000000 1999252867SdelphijDEVICEID hpt_create_transform(DEVICEID idArray, PCREATE_ARRAY_PARAMS_V2 destInfo); 2000252867Sdelphij#endif 2001252867Sdelphij 2002252867Sdelphij/* hpt_create_transform_v2 2003252867Sdelphij * create a transform instance. 2004252867Sdelphij * Version compatibility: v2.0.0.1 or later 2005252867Sdelphij * Parameters: 2006252867Sdelphij * idArray - source array 2007252867Sdelphij * destInfo - destination array info 2008252867Sdelphij * Returns: 2009252867Sdelphij * destination array id 2010252867Sdelphij */ 2011252867Sdelphij#if HPT_INTERFACE_VERSION>=0x02000001 2012252867SdelphijDEVICEID hpt_create_transform_v2(DEVICEID idArray, PCREATE_ARRAY_PARAMS_V3 destInfo); 2013252867Sdelphij#endif 2014252867Sdelphij 2015252867Sdelphij/* hpt_step_transform 2016252867Sdelphij * move a block in a tranform progress. 2017252867Sdelphij * This function is called by mid-layer, not GUI (which uses set_array_state instead). 2018252867Sdelphij * Version compatibility: v2.0.0.0 or later 2019252867Sdelphij * Parameters: 2020252867Sdelphij * idArray - destination array ID 2021252867Sdelphij * the source ID will be invalid when transform complete. 2022252867Sdelphij * Returns: 2023252867Sdelphij * 0 - Success 2024252867Sdelphij */ 2025252867Sdelphij#if HPT_INTERFACE_VERSION>=0x02000000 2026252867Sdelphijint hpt_step_transform(DEVICEID idArray); 2027252867Sdelphij#endif 2028252867Sdelphij 2029252867Sdelphij/* hpt_set_vdev_info 2030252867Sdelphij * set information for disk or array 2031252867Sdelphij * Version compatibility: v1.2.0.0 or later 2032252867Sdelphij * Parameters: 2033252867Sdelphij * dev - destination device 2034252867Sdelphij * 2035252867Sdelphij * Returns: 2036252867Sdelphij * 0 - Success 2037252867Sdelphij */ 2038252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000 2039252867Sdelphijint hpt_set_vdev_info(DEVICEID dev, PSET_VDEV_INFO pInfo); 2040252867Sdelphij#endif 2041252867Sdelphij 2042252867Sdelphij/* hpt_init_disks 2043252867Sdelphij * initialize disks for use 2044252867Sdelphij * Version compatibility: v2.0.0.0 or later 2045252867Sdelphij * Parameters: 2046252867Sdelphij * ndev - number of disks to initialize 2047252867Sdelphij * pIds - array of DEVICEID 2048252867Sdelphij * 2049252867Sdelphij * Returns: 2050252867Sdelphij * 0 - Success 2051252867Sdelphij */ 2052252867Sdelphij#if HPT_INTERFACE_VERSION>=0x02000000 2053252867Sdelphijint hpt_init_disks(HPT_U32 ndev, DEVICEID * pIds); 2054252867Sdelphij#endif 2055252867Sdelphij 2056252867Sdelphij/* hpt_calc_max_array_capacity 2057252867Sdelphij * cap max capacity of the array user want to create or transform 2058252867Sdelphij * Version compatibility: v1.2.0.0 or later 2059252867Sdelphij * Parameters: 2060252867Sdelphij * source - if transform, this is the source array, otherwise, it should be zero 2061252867Sdelphij * destInfo - target array params 2062252867Sdelphij * Returns: 2063252867Sdelphij * 0 - Success 2064252867Sdelphij * cap - max capacity of the target array 2065252867Sdelphij */ 2066252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000 2067252867Sdelphijint hpt_calc_max_array_capacity(DEVICEID source, PCREATE_ARRAY_PARAMS_V2 destInfo, HPT_U64 * cap); 2068252867Sdelphij#endif 2069252867Sdelphij 2070252867Sdelphij/* hpt_calc_max_array_capacity_v2 2071252867Sdelphij * cap max capacity of the array user want to create or transform 2072252867Sdelphij * Version compatibility: v2.0.0.1 or later 2073252867Sdelphij * Parameters: 2074252867Sdelphij * source - if transform, this is the source array, otherwise, it should be zero 2075252867Sdelphij * destInfo - target array params 2076252867Sdelphij * Returns: 2077252867Sdelphij * 0 - Success 2078252867Sdelphij * cap - max capacity of the target array 2079252867Sdelphij */ 2080252867Sdelphij#if HPT_INTERFACE_VERSION>=0x02000001 2081252867Sdelphijint hpt_calc_max_array_capacity_v2(DEVICEID source, PCREATE_ARRAY_PARAMS_V3 destInfo, HPT_U64 * cap); 2082252867Sdelphij#endif 2083252867Sdelphij 2084252867Sdelphij/* hpt_rebuild_data_block2 2085252867Sdelphij * Used to copy data from source disk and mirror disk. 2086252867Sdelphij * Version compatibility: v1.1.0.0 or later 2087252867Sdelphij * Parameters: 2088252867Sdelphij * idArray Array ID (RAID1, 0/1 or RAID5) 2089252867Sdelphij * Lba Start LBA for each array member 2090252867Sdelphij * nSector Number of sectors for each array member (RAID 5 will ignore this parameter) 2091252867Sdelphij * 2092252867Sdelphij * Returns: 2093252867Sdelphij * 0 Success, event info is filled in *pEvent 2094252867Sdelphij */ 2095252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000 2096252867Sdelphijint hpt_rebuild_data_block_v2(DEVICEID idMirror, HPT_U64 Lba, HPT_U16 nSector); 2097252867Sdelphij#endif 2098252867Sdelphij 2099252867Sdelphij/* hpt_verify_data_block2 2100252867Sdelphij * verify data block on RAID1 or RAID5. 2101252867Sdelphij * Version compatibility: v1.1.0.0 or later 2102252867Sdelphij * Parameters: 2103252867Sdelphij * idArray - Array ID 2104252867Sdelphij * Lba - block number (on each array member, not logical block!) 2105252867Sdelphij * nSectors - Sectors for each member (RAID 5 will ignore this parameter) 2106252867Sdelphij * Returns: 2107252867Sdelphij * 0 Success 2108252867Sdelphij * 1 Data compare error 2109252867Sdelphij * 2 I/O error 2110252867Sdelphij */ 2111252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000 2112252867Sdelphijint hpt_verify_data_block_v2(DEVICEID idArray, HPT_U64 Lba, HPT_U16 nSectors); 2113252867Sdelphij#endif 2114252867Sdelphij 2115252867Sdelphij/* hpt_initialize_data_block2 2116252867Sdelphij * initialize data block (fill with zero) on RAID5 2117252867Sdelphij * Version compatibility: v1.1.0.0 or later 2118252867Sdelphij * Parameters: 2119252867Sdelphij * idArray - Array ID 2120252867Sdelphij * Lba - block number (on each array member, not logical block!) 2121252867Sdelphij * nSectors - Sectors for each member (RAID 5 will ignore this parameter) 2122252867Sdelphij * Returns: 2123252867Sdelphij * 0 Success 2124252867Sdelphij */ 2125252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000 2126252867Sdelphijint hpt_initialize_data_block_v2(DEVICEID idArray, HPT_U64 Lba, HPT_U16 nSectors); 2127252867Sdelphij#endif 2128252867Sdelphij 2129252867Sdelphij/* hpt_i2c_transaction 2130252867Sdelphij * perform an transaction on i2c bus 2131252867Sdelphij * Version compatibility: v2.0.0.0 or later 2132252867Sdelphij * Parameters: 2133252867Sdelphij * indata[0] - controller ID 2134252867Sdelphij * Returns: 2135252867Sdelphij * 0 Success 2136252867Sdelphij */ 2137252867Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000 2138252867Sdelphijint hpt_i2c_transaction(HPT_U8 *indata, HPT_U32 inlen, HPT_U8 *outdata, HPT_U32 outlen, HPT_U32 *poutlen); 2139252867Sdelphij#endif 2140252867Sdelphij 2141252867Sdelphij/* hpt_get_parameter_list 2142252867Sdelphij * get a list of driver parameters. 2143252867Sdelphij * Version compatibility: v1.0.0.0 or later 2144252867Sdelphij * Parameters: 2145252867Sdelphij * location - parameter location 2146252867Sdelphij * outBuffer - a buffer to hold the output 2147252867Sdelphij * outBufferSize - size of outBuffer 2148252867Sdelphij * Returns: 2149252867Sdelphij * 0 Success 2150252867Sdelphij * put in outBuffer a list of zero terminated parameter names. the whole list 2151252867Sdelphij * is terminated with an additional zero byte. 2152252867Sdelphij */ 2153252867Sdelphijint hpt_get_parameter_list(HPT_U32 location, char *outBuffer, HPT_U32 outBufferSize); 2154252867Sdelphij 2155252867Sdelphij/* hpt_{get,set}_parameter 2156252867Sdelphij * get/set a parameter value. 2157252867Sdelphij * Version compatibility: v1.0.0.0 or later 2158252867Sdelphij * Parameters: 2159252867Sdelphij * pParam - a pointer to HPT_DRIVER_PARAMETER. 2160252867Sdelphij * Returns: 2161252867Sdelphij * 0 Success 2162252867Sdelphij */ 2163252867Sdelphijint hpt_get_parameter(PHPT_DRIVER_PARAMETER pParam); 2164252867Sdelphijint hpt_set_parameter(PHPT_DRIVER_PARAMETER pParam); 2165252867Sdelphijint hpt_reenumerate_device(DEVICEID id); 2166252867Sdelphij 2167252867Sdelphij/* 2168252867Sdelphij * hpt_get_enclosure_count 2169252867Sdelphij * Version compatibility: v2.1.0.0 or later 2170252867Sdelphij * Parameters: 2171252867Sdelphij * controller_id 2172252867Sdelphij * Returns: 2173252867Sdelphij * number of enclosurers 2174252867Sdelphij */ 2175252867Sdelphijint hpt_get_enclosure_count(int ctlr_id); 2176252867Sdelphij 2177252867Sdelphij/* hpt_get_enclosure_info 2178252867Sdelphij * Version compatibility: v2.1.0.0 or later 2179252867Sdelphij * Parameters: 2180252867Sdelphij * id enclosure id 2181252867Sdelphij * pInfo pointer to ENCLOSURE_INFO buffer 2182252867Sdelphij * Returns: 2183252867Sdelphij * 0 Success, enclosure info is put into (*pInfo ). 2184252867Sdelphij */ 2185252867Sdelphijint hpt_get_enclosure_info(int ctlr_id, int enc_id, PENCLOSURE_INFO pInfo); 2186252867Sdelphij 2187252867Sdelphijint hpt_get_enclosure_info_v2(int ctlr_id, int enc_id, PENCLOSURE_INFO_V2 pInfo); 2188252867Sdelphij 2189252867Sdelphijint hpt_get_enclosure_info_v3(int ctlr_id, int enc_id, PENCLOSURE_INFO_V3 pInfo); 2190252867Sdelphij 2191252867Sdelphijint hpt_get_enclosure_info_v4(int ctlr_id, int enc_id, PENCLOSURE_INFO_V4 pInfo); 2192252867Sdelphijint hpt_get_enclosure_element_info(int ctlr_id, int enc_id, int ele_id, PSES_ELEMENT_STATUS pInfo); 2193252867Sdelphij 2194252867Sdelphij/* performance monitor interface 2195252867Sdelphij * Version compatibility: v2.1.0.0 or later 2196252867Sdelphij */ 2197252867Sdelphijint hpt_get_perfmon_status(int ctlr_id, int *p_status); 2198252867Sdelphijint hpt_set_perfmon_status(int ctlr_id, int enable); 2199252867Sdelphijint hpt_get_perfmon_data(DEVICEID id, PHPT_PM_IOSTAT iostat); 2200252867Sdelphij 2201252867Sdelphij/* hpt_get_controller_venid 2202252867Sdelphij * Version compatibility: v1.0.0.0 or later 2203252867Sdelphij */ 2204252867Sdelphijint hpt_get_controller_venid(int ctlr_id, HPT_U32 *venid); 2205252867Sdelphij 2206252867Sdelphij/* hpt_access_config_reg 2207252867Sdelphij * access the reserved config space on disk 2208252867Sdelphij * Parameters: 2209252867Sdelphij * p - ACCESS_CONFIG_REG_PARAMS header pointer 2210252867Sdelphij * Returns: 2211252867Sdelphij * 0 Success 2212252867Sdelphij */ 2213252867Sdelphijint hpt_access_config_reg(PACCESS_CONFIG_REG_PARAMS p); 2214252867Sdelphij 2215252867Sdelphij/* hpt_dump_metadata 2216252867Sdelphij * dump internal metadata 2217252867Sdelphij * Parameters: 2218252867Sdelphij * p - PDUMP_METADATA_PARAMS header pointer 2219252867Sdelphij * Returns: 2220252867Sdelphij * 0 Success 2221252867Sdelphij */ 2222252867Sdelphijint hpt_dump_metadata(PDUMP_METADATA_PARAMS p); 2223252867Sdelphij 2224252867Sdelphij#endif 2225252867Sdelphij 2226252867Sdelphij#pragma pack() 2227252867Sdelphij 2228252867Sdelphij#ifdef __cplusplus 2229252867Sdelphij} 2230252867Sdelphij#endif 2231252867Sdelphij#endif 2232