1/****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD$*/ 34 35#include "e1000_api.h" 36 37static s32 e1000_wait_autoneg(struct e1000_hw *hw); 38static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39 u16 *data, bool read, bool page_set); 40static u32 e1000_get_phy_addr_for_hv_page(u32 page); 41static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 42 u16 *data, bool read); 43 44/* Cable length tables */ 45static const u16 e1000_m88_cable_length_table[] = { 46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 47#define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 48 (sizeof(e1000_m88_cable_length_table) / \ 49 sizeof(e1000_m88_cable_length_table[0])) 50 51static const u16 e1000_igp_2_cable_length_table[] = { 52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, 55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, 56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, 57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, 58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, 59 124}; 60#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 61 (sizeof(e1000_igp_2_cable_length_table) / \ 62 sizeof(e1000_igp_2_cable_length_table[0])) 63 64/** 65 * e1000_init_phy_ops_generic - Initialize PHY function pointers 66 * @hw: pointer to the HW structure 67 * 68 * Setups up the function pointers to no-op functions 69 **/ 70void e1000_init_phy_ops_generic(struct e1000_hw *hw) 71{ 72 struct e1000_phy_info *phy = &hw->phy; 73 DEBUGFUNC("e1000_init_phy_ops_generic"); 74 75 /* Initialize function pointers */ 76 phy->ops.init_params = e1000_null_ops_generic; 77 phy->ops.acquire = e1000_null_ops_generic; 78 phy->ops.check_polarity = e1000_null_ops_generic; 79 phy->ops.check_reset_block = e1000_null_ops_generic; 80 phy->ops.commit = e1000_null_ops_generic; 81 phy->ops.force_speed_duplex = e1000_null_ops_generic; 82 phy->ops.get_cfg_done = e1000_null_ops_generic; 83 phy->ops.get_cable_length = e1000_null_ops_generic; 84 phy->ops.get_info = e1000_null_ops_generic; 85 phy->ops.set_page = e1000_null_set_page; 86 phy->ops.read_reg = e1000_null_read_reg; 87 phy->ops.read_reg_locked = e1000_null_read_reg; 88 phy->ops.read_reg_page = e1000_null_read_reg; 89 phy->ops.release = e1000_null_phy_generic; 90 phy->ops.reset = e1000_null_ops_generic; 91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 93 phy->ops.write_reg = e1000_null_write_reg; 94 phy->ops.write_reg_locked = e1000_null_write_reg; 95 phy->ops.write_reg_page = e1000_null_write_reg; 96 phy->ops.power_up = e1000_null_phy_generic; 97 phy->ops.power_down = e1000_null_phy_generic; 98 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null; 99 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null; 100 phy->ops.cfg_on_link_up = e1000_null_ops_generic; 101} 102 103/** 104 * e1000_null_set_page - No-op function, return 0 105 * @hw: pointer to the HW structure 106 **/ 107s32 e1000_null_set_page(struct e1000_hw *hw, u16 data) 108{ 109 DEBUGFUNC("e1000_null_set_page"); 110 return E1000_SUCCESS; 111} 112 113/** 114 * e1000_null_read_reg - No-op function, return 0 115 * @hw: pointer to the HW structure 116 **/ 117s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data) 118{ 119 DEBUGFUNC("e1000_null_read_reg"); 120 return E1000_SUCCESS; 121} 122 123/** 124 * e1000_null_phy_generic - No-op function, return void 125 * @hw: pointer to the HW structure 126 **/ 127void e1000_null_phy_generic(struct e1000_hw *hw) 128{ 129 DEBUGFUNC("e1000_null_phy_generic"); 130 return; 131} 132 133/** 134 * e1000_null_lplu_state - No-op function, return 0 135 * @hw: pointer to the HW structure 136 **/ 137s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active) 138{ 139 DEBUGFUNC("e1000_null_lplu_state"); 140 return E1000_SUCCESS; 141} 142 143/** 144 * e1000_null_write_reg - No-op function, return 0 145 * @hw: pointer to the HW structure 146 **/ 147s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data) 148{ 149 DEBUGFUNC("e1000_null_write_reg"); 150 return E1000_SUCCESS; 151} 152 153/** 154 * e1000_read_i2c_byte_null - No-op function, return 0 155 * @hw: pointer to hardware structure 156 * @byte_offset: byte offset to write 157 * @dev_addr: device address 158 * @data: data value read 159 * 160 **/ 161s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset, 162 u8 dev_addr, u8 *data) 163{ 164 DEBUGFUNC("e1000_read_i2c_byte_null"); 165 return E1000_SUCCESS; 166} 167 168/** 169 * e1000_write_i2c_byte_null - No-op function, return 0 170 * @hw: pointer to hardware structure 171 * @byte_offset: byte offset to write 172 * @dev_addr: device address 173 * @data: data value to write 174 * 175 **/ 176s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, 177 u8 byte_offset, 178 u8 dev_addr, 179 u8 data) 180{ 181 DEBUGFUNC("e1000_write_i2c_byte_null"); 182 return E1000_SUCCESS; 183} 184 185/** 186 * e1000_check_reset_block_generic - Check if PHY reset is blocked 187 * @hw: pointer to the HW structure 188 * 189 * Read the PHY management control register and check whether a PHY reset 190 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 191 * return E1000_BLK_PHY_RESET (12). 192 **/ 193s32 e1000_check_reset_block_generic(struct e1000_hw *hw) 194{ 195 u32 manc; 196 197 DEBUGFUNC("e1000_check_reset_block"); 198 199 manc = E1000_READ_REG(hw, E1000_MANC); 200 201 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 202 E1000_BLK_PHY_RESET : E1000_SUCCESS; 203} 204 205/** 206 * e1000_get_phy_id - Retrieve the PHY ID and revision 207 * @hw: pointer to the HW structure 208 * 209 * Reads the PHY registers and stores the PHY ID and possibly the PHY 210 * revision in the hardware structure. 211 **/ 212s32 e1000_get_phy_id(struct e1000_hw *hw) 213{ 214 struct e1000_phy_info *phy = &hw->phy; 215 s32 ret_val = E1000_SUCCESS; 216 u16 phy_id; 217 u16 retry_count = 0; 218 219 DEBUGFUNC("e1000_get_phy_id"); 220 221 if (!phy->ops.read_reg) 222 return E1000_SUCCESS; 223 224 while (retry_count < 2) { 225 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 226 if (ret_val) 227 return ret_val; 228 229 phy->id = (u32)(phy_id << 16); 230 usec_delay(20); 231 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 232 if (ret_val) 233 return ret_val; 234 235 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 236 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 237 238 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 239 return E1000_SUCCESS; 240 241 retry_count++; 242 } 243 244 return E1000_SUCCESS; 245} 246 247/** 248 * e1000_phy_reset_dsp_generic - Reset PHY DSP 249 * @hw: pointer to the HW structure 250 * 251 * Reset the digital signal processor. 252 **/ 253s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 254{ 255 s32 ret_val; 256 257 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 258 259 if (!hw->phy.ops.write_reg) 260 return E1000_SUCCESS; 261 262 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 263 if (ret_val) 264 return ret_val; 265 266 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 267} 268 269/** 270 * e1000_read_phy_reg_mdic - Read MDI control register 271 * @hw: pointer to the HW structure 272 * @offset: register offset to be read 273 * @data: pointer to the read data 274 * 275 * Reads the MDI control register in the PHY at offset and stores the 276 * information read to data. 277 **/ 278s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 279{ 280 struct e1000_phy_info *phy = &hw->phy; 281 u32 i, mdic = 0; 282 283 DEBUGFUNC("e1000_read_phy_reg_mdic"); 284 285 if (offset > MAX_PHY_REG_ADDRESS) { 286 DEBUGOUT1("PHY Address %d is out of range\n", offset); 287 return -E1000_ERR_PARAM; 288 } 289 290 /* Set up Op-code, Phy Address, and register offset in the MDI 291 * Control register. The MAC will take care of interfacing with the 292 * PHY to retrieve the desired data. 293 */ 294 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 295 (phy->addr << E1000_MDIC_PHY_SHIFT) | 296 (E1000_MDIC_OP_READ)); 297 298 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 299 300 /* Poll the ready bit to see if the MDI read completed 301 * Increasing the time out as testing showed failures with 302 * the lower time out 303 */ 304 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 305 usec_delay(50); 306 mdic = E1000_READ_REG(hw, E1000_MDIC); 307 if (mdic & E1000_MDIC_READY) 308 break; 309 } 310 if (!(mdic & E1000_MDIC_READY)) { 311 DEBUGOUT("MDI Read did not complete\n"); 312 return -E1000_ERR_PHY; 313 } 314 if (mdic & E1000_MDIC_ERROR) { 315 DEBUGOUT("MDI Error\n"); 316 return -E1000_ERR_PHY; 317 } 318 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 319 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n", 320 offset, 321 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 322 return -E1000_ERR_PHY; 323 } 324 *data = (u16) mdic; 325 326 /* Allow some time after each MDIC transaction to avoid 327 * reading duplicate data in the next MDIC transaction. 328 */ 329 if (hw->mac.type == e1000_pch2lan) 330 usec_delay(100); 331 332 return E1000_SUCCESS; 333} 334 335/** 336 * e1000_write_phy_reg_mdic - Write MDI control register 337 * @hw: pointer to the HW structure 338 * @offset: register offset to write to 339 * @data: data to write to register at offset 340 * 341 * Writes data to MDI control register in the PHY at offset. 342 **/ 343s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 344{ 345 struct e1000_phy_info *phy = &hw->phy; 346 u32 i, mdic = 0; 347 348 DEBUGFUNC("e1000_write_phy_reg_mdic"); 349 350 if (offset > MAX_PHY_REG_ADDRESS) { 351 DEBUGOUT1("PHY Address %d is out of range\n", offset); 352 return -E1000_ERR_PARAM; 353 } 354 355 /* Set up Op-code, Phy Address, and register offset in the MDI 356 * Control register. The MAC will take care of interfacing with the 357 * PHY to retrieve the desired data. 358 */ 359 mdic = (((u32)data) | 360 (offset << E1000_MDIC_REG_SHIFT) | 361 (phy->addr << E1000_MDIC_PHY_SHIFT) | 362 (E1000_MDIC_OP_WRITE)); 363 364 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 365 366 /* Poll the ready bit to see if the MDI read completed 367 * Increasing the time out as testing showed failures with 368 * the lower time out 369 */ 370 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 371 usec_delay(50); 372 mdic = E1000_READ_REG(hw, E1000_MDIC); 373 if (mdic & E1000_MDIC_READY) 374 break; 375 } 376 if (!(mdic & E1000_MDIC_READY)) { 377 DEBUGOUT("MDI Write did not complete\n"); 378 return -E1000_ERR_PHY; 379 } 380 if (mdic & E1000_MDIC_ERROR) { 381 DEBUGOUT("MDI Error\n"); 382 return -E1000_ERR_PHY; 383 } 384 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 385 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n", 386 offset, 387 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 388 return -E1000_ERR_PHY; 389 } 390 391 /* Allow some time after each MDIC transaction to avoid 392 * reading duplicate data in the next MDIC transaction. 393 */ 394 if (hw->mac.type == e1000_pch2lan) 395 usec_delay(100); 396 397 return E1000_SUCCESS; 398} 399 400/** 401 * e1000_read_phy_reg_i2c - Read PHY register using i2c 402 * @hw: pointer to the HW structure 403 * @offset: register offset to be read 404 * @data: pointer to the read data 405 * 406 * Reads the PHY register at offset using the i2c interface and stores the 407 * retrieved information in data. 408 **/ 409s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 410{ 411 struct e1000_phy_info *phy = &hw->phy; 412 u32 i, i2ccmd = 0; 413 414 DEBUGFUNC("e1000_read_phy_reg_i2c"); 415 416 /* Set up Op-code, Phy Address, and register address in the I2CCMD 417 * register. The MAC will take care of interfacing with the 418 * PHY to retrieve the desired data. 419 */ 420 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 421 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 422 (E1000_I2CCMD_OPCODE_READ)); 423 424 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 425 426 /* Poll the ready bit to see if the I2C read completed */ 427 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 428 usec_delay(50); 429 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 430 if (i2ccmd & E1000_I2CCMD_READY) 431 break; 432 } 433 if (!(i2ccmd & E1000_I2CCMD_READY)) { 434 DEBUGOUT("I2CCMD Read did not complete\n"); 435 return -E1000_ERR_PHY; 436 } 437 if (i2ccmd & E1000_I2CCMD_ERROR) { 438 DEBUGOUT("I2CCMD Error bit set\n"); 439 return -E1000_ERR_PHY; 440 } 441 442 /* Need to byte-swap the 16-bit value. */ 443 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 444 445 return E1000_SUCCESS; 446} 447 448/** 449 * e1000_write_phy_reg_i2c - Write PHY register using i2c 450 * @hw: pointer to the HW structure 451 * @offset: register offset to write to 452 * @data: data to write at register offset 453 * 454 * Writes the data to PHY register at the offset using the i2c interface. 455 **/ 456s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 457{ 458 struct e1000_phy_info *phy = &hw->phy; 459 u32 i, i2ccmd = 0; 460 u16 phy_data_swapped; 461 462 DEBUGFUNC("e1000_write_phy_reg_i2c"); 463 464 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ 465 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 466 DEBUGOUT1("PHY I2C Address %d is out of range.\n", 467 hw->phy.addr); 468 return -E1000_ERR_CONFIG; 469 } 470 471 /* Swap the data bytes for the I2C interface */ 472 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 473 474 /* Set up Op-code, Phy Address, and register address in the I2CCMD 475 * register. The MAC will take care of interfacing with the 476 * PHY to retrieve the desired data. 477 */ 478 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 479 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 480 E1000_I2CCMD_OPCODE_WRITE | 481 phy_data_swapped); 482 483 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 484 485 /* Poll the ready bit to see if the I2C read completed */ 486 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 487 usec_delay(50); 488 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 489 if (i2ccmd & E1000_I2CCMD_READY) 490 break; 491 } 492 if (!(i2ccmd & E1000_I2CCMD_READY)) { 493 DEBUGOUT("I2CCMD Write did not complete\n"); 494 return -E1000_ERR_PHY; 495 } 496 if (i2ccmd & E1000_I2CCMD_ERROR) { 497 DEBUGOUT("I2CCMD Error bit set\n"); 498 return -E1000_ERR_PHY; 499 } 500 501 return E1000_SUCCESS; 502} 503 504/** 505 * e1000_read_sfp_data_byte - Reads SFP module data. 506 * @hw: pointer to the HW structure 507 * @offset: byte location offset to be read 508 * @data: read data buffer pointer 509 * 510 * Reads one byte from SFP module data stored 511 * in SFP resided EEPROM memory or SFP diagnostic area. 512 * Function should be called with 513 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 514 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 515 * access 516 **/ 517s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) 518{ 519 u32 i = 0; 520 u32 i2ccmd = 0; 521 u32 data_local = 0; 522 523 DEBUGFUNC("e1000_read_sfp_data_byte"); 524 525 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 526 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 527 return -E1000_ERR_PHY; 528 } 529 530 /* Set up Op-code, EEPROM Address,in the I2CCMD 531 * register. The MAC will take care of interfacing with the 532 * EEPROM to retrieve the desired data. 533 */ 534 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 535 E1000_I2CCMD_OPCODE_READ); 536 537 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 538 539 /* Poll the ready bit to see if the I2C read completed */ 540 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 541 usec_delay(50); 542 data_local = E1000_READ_REG(hw, E1000_I2CCMD); 543 if (data_local & E1000_I2CCMD_READY) 544 break; 545 } 546 if (!(data_local & E1000_I2CCMD_READY)) { 547 DEBUGOUT("I2CCMD Read did not complete\n"); 548 return -E1000_ERR_PHY; 549 } 550 if (data_local & E1000_I2CCMD_ERROR) { 551 DEBUGOUT("I2CCMD Error bit set\n"); 552 return -E1000_ERR_PHY; 553 } 554 *data = (u8) data_local & 0xFF; 555 556 return E1000_SUCCESS; 557} 558 559/** 560 * e1000_write_sfp_data_byte - Writes SFP module data. 561 * @hw: pointer to the HW structure 562 * @offset: byte location offset to write to 563 * @data: data to write 564 * 565 * Writes one byte to SFP module data stored 566 * in SFP resided EEPROM memory or SFP diagnostic area. 567 * Function should be called with 568 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 569 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 570 * access 571 **/ 572s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) 573{ 574 u32 i = 0; 575 u32 i2ccmd = 0; 576 u32 data_local = 0; 577 578 DEBUGFUNC("e1000_write_sfp_data_byte"); 579 580 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 581 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 582 return -E1000_ERR_PHY; 583 } 584 /* The programming interface is 16 bits wide 585 * so we need to read the whole word first 586 * then update appropriate byte lane and write 587 * the updated word back. 588 */ 589 /* Set up Op-code, EEPROM Address,in the I2CCMD 590 * register. The MAC will take care of interfacing 591 * with an EEPROM to write the data given. 592 */ 593 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 594 E1000_I2CCMD_OPCODE_READ); 595 /* Set a command to read single word */ 596 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 597 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 598 usec_delay(50); 599 /* Poll the ready bit to see if lastly 600 * launched I2C operation completed 601 */ 602 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 603 if (i2ccmd & E1000_I2CCMD_READY) { 604 /* Check if this is READ or WRITE phase */ 605 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) == 606 E1000_I2CCMD_OPCODE_READ) { 607 /* Write the selected byte 608 * lane and update whole word 609 */ 610 data_local = i2ccmd & 0xFF00; 611 data_local |= data; 612 i2ccmd = ((offset << 613 E1000_I2CCMD_REG_ADDR_SHIFT) | 614 E1000_I2CCMD_OPCODE_WRITE | data_local); 615 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 616 } else { 617 break; 618 } 619 } 620 } 621 if (!(i2ccmd & E1000_I2CCMD_READY)) { 622 DEBUGOUT("I2CCMD Write did not complete\n"); 623 return -E1000_ERR_PHY; 624 } 625 if (i2ccmd & E1000_I2CCMD_ERROR) { 626 DEBUGOUT("I2CCMD Error bit set\n"); 627 return -E1000_ERR_PHY; 628 } 629 return E1000_SUCCESS; 630} 631 632/** 633 * e1000_read_phy_reg_m88 - Read m88 PHY register 634 * @hw: pointer to the HW structure 635 * @offset: register offset to be read 636 * @data: pointer to the read data 637 * 638 * Acquires semaphore, if necessary, then reads the PHY register at offset 639 * and storing the retrieved information in data. Release any acquired 640 * semaphores before exiting. 641 **/ 642s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 643{ 644 s32 ret_val; 645 646 DEBUGFUNC("e1000_read_phy_reg_m88"); 647 648 if (!hw->phy.ops.acquire) 649 return E1000_SUCCESS; 650 651 ret_val = hw->phy.ops.acquire(hw); 652 if (ret_val) 653 return ret_val; 654 655 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 656 data); 657 658 hw->phy.ops.release(hw); 659 660 return ret_val; 661} 662 663/** 664 * e1000_write_phy_reg_m88 - Write m88 PHY register 665 * @hw: pointer to the HW structure 666 * @offset: register offset to write to 667 * @data: data to write at register offset 668 * 669 * Acquires semaphore, if necessary, then writes the data to PHY register 670 * at the offset. Release any acquired semaphores before exiting. 671 **/ 672s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 673{ 674 s32 ret_val; 675 676 DEBUGFUNC("e1000_write_phy_reg_m88"); 677 678 if (!hw->phy.ops.acquire) 679 return E1000_SUCCESS; 680 681 ret_val = hw->phy.ops.acquire(hw); 682 if (ret_val) 683 return ret_val; 684 685 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 686 data); 687 688 hw->phy.ops.release(hw); 689 690 return ret_val; 691} 692 693/** 694 * e1000_set_page_igp - Set page as on IGP-like PHY(s) 695 * @hw: pointer to the HW structure 696 * @page: page to set (shifted left when necessary) 697 * 698 * Sets PHY page required for PHY register access. Assumes semaphore is 699 * already acquired. Note, this function sets phy.addr to 1 so the caller 700 * must set it appropriately (if necessary) after this function returns. 701 **/ 702s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) 703{ 704 DEBUGFUNC("e1000_set_page_igp"); 705 706 DEBUGOUT1("Setting page 0x%x\n", page); 707 708 hw->phy.addr = 1; 709 710 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); 711} 712 713/** 714 * __e1000_read_phy_reg_igp - Read igp PHY register 715 * @hw: pointer to the HW structure 716 * @offset: register offset to be read 717 * @data: pointer to the read data 718 * @locked: semaphore has already been acquired or not 719 * 720 * Acquires semaphore, if necessary, then reads the PHY register at offset 721 * and stores the retrieved information in data. Release any acquired 722 * semaphores before exiting. 723 **/ 724static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 725 bool locked) 726{ 727 s32 ret_val = E1000_SUCCESS; 728 729 DEBUGFUNC("__e1000_read_phy_reg_igp"); 730 731 if (!locked) { 732 if (!hw->phy.ops.acquire) 733 return E1000_SUCCESS; 734 735 ret_val = hw->phy.ops.acquire(hw); 736 if (ret_val) 737 return ret_val; 738 } 739 740 if (offset > MAX_PHY_MULTI_PAGE_REG) 741 ret_val = e1000_write_phy_reg_mdic(hw, 742 IGP01E1000_PHY_PAGE_SELECT, 743 (u16)offset); 744 if (!ret_val) 745 ret_val = e1000_read_phy_reg_mdic(hw, 746 MAX_PHY_REG_ADDRESS & offset, 747 data); 748 if (!locked) 749 hw->phy.ops.release(hw); 750 751 return ret_val; 752} 753 754/** 755 * e1000_read_phy_reg_igp - Read igp PHY register 756 * @hw: pointer to the HW structure 757 * @offset: register offset to be read 758 * @data: pointer to the read data 759 * 760 * Acquires semaphore then reads the PHY register at offset and stores the 761 * retrieved information in data. 762 * Release the acquired semaphore before exiting. 763 **/ 764s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 765{ 766 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE); 767} 768 769/** 770 * e1000_read_phy_reg_igp_locked - Read igp PHY register 771 * @hw: pointer to the HW structure 772 * @offset: register offset to be read 773 * @data: pointer to the read data 774 * 775 * Reads the PHY register at offset and stores the retrieved information 776 * in data. Assumes semaphore already acquired. 777 **/ 778s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 779{ 780 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE); 781} 782 783/** 784 * e1000_write_phy_reg_igp - Write igp PHY register 785 * @hw: pointer to the HW structure 786 * @offset: register offset to write to 787 * @data: data to write at register offset 788 * @locked: semaphore has already been acquired or not 789 * 790 * Acquires semaphore, if necessary, then writes the data to PHY register 791 * at the offset. Release any acquired semaphores before exiting. 792 **/ 793static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 794 bool locked) 795{ 796 s32 ret_val = E1000_SUCCESS; 797 798 DEBUGFUNC("e1000_write_phy_reg_igp"); 799 800 if (!locked) { 801 if (!hw->phy.ops.acquire) 802 return E1000_SUCCESS; 803 804 ret_val = hw->phy.ops.acquire(hw); 805 if (ret_val) 806 return ret_val; 807 } 808 809 if (offset > MAX_PHY_MULTI_PAGE_REG) 810 ret_val = e1000_write_phy_reg_mdic(hw, 811 IGP01E1000_PHY_PAGE_SELECT, 812 (u16)offset); 813 if (!ret_val) 814 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & 815 offset, 816 data); 817 if (!locked) 818 hw->phy.ops.release(hw); 819 820 return ret_val; 821} 822 823/** 824 * e1000_write_phy_reg_igp - Write igp PHY register 825 * @hw: pointer to the HW structure 826 * @offset: register offset to write to 827 * @data: data to write at register offset 828 * 829 * Acquires semaphore then writes the data to PHY register 830 * at the offset. Release any acquired semaphores before exiting. 831 **/ 832s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 833{ 834 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE); 835} 836 837/** 838 * e1000_write_phy_reg_igp_locked - Write igp PHY register 839 * @hw: pointer to the HW structure 840 * @offset: register offset to write to 841 * @data: data to write at register offset 842 * 843 * Writes the data to PHY register at the offset. 844 * Assumes semaphore already acquired. 845 **/ 846s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 847{ 848 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE); 849} 850 851/** 852 * __e1000_read_kmrn_reg - Read kumeran register 853 * @hw: pointer to the HW structure 854 * @offset: register offset to be read 855 * @data: pointer to the read data 856 * @locked: semaphore has already been acquired or not 857 * 858 * Acquires semaphore, if necessary. Then reads the PHY register at offset 859 * using the kumeran interface. The information retrieved is stored in data. 860 * Release any acquired semaphores before exiting. 861 **/ 862static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 863 bool locked) 864{ 865 u32 kmrnctrlsta; 866 867 DEBUGFUNC("__e1000_read_kmrn_reg"); 868 869 if (!locked) { 870 s32 ret_val = E1000_SUCCESS; 871 872 if (!hw->phy.ops.acquire) 873 return E1000_SUCCESS; 874 875 ret_val = hw->phy.ops.acquire(hw); 876 if (ret_val) 877 return ret_val; 878 } 879 880 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 881 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 882 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 883 E1000_WRITE_FLUSH(hw); 884 885 usec_delay(2); 886 887 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 888 *data = (u16)kmrnctrlsta; 889 890 if (!locked) 891 hw->phy.ops.release(hw); 892 893 return E1000_SUCCESS; 894} 895 896/** 897 * e1000_read_kmrn_reg_generic - Read kumeran register 898 * @hw: pointer to the HW structure 899 * @offset: register offset to be read 900 * @data: pointer to the read data 901 * 902 * Acquires semaphore then reads the PHY register at offset using the 903 * kumeran interface. The information retrieved is stored in data. 904 * Release the acquired semaphore before exiting. 905 **/ 906s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 907{ 908 return __e1000_read_kmrn_reg(hw, offset, data, FALSE); 909} 910 911/** 912 * e1000_read_kmrn_reg_locked - Read kumeran register 913 * @hw: pointer to the HW structure 914 * @offset: register offset to be read 915 * @data: pointer to the read data 916 * 917 * Reads the PHY register at offset using the kumeran interface. The 918 * information retrieved is stored in data. 919 * Assumes semaphore already acquired. 920 **/ 921s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 922{ 923 return __e1000_read_kmrn_reg(hw, offset, data, TRUE); 924} 925 926/** 927 * __e1000_write_kmrn_reg - Write kumeran register 928 * @hw: pointer to the HW structure 929 * @offset: register offset to write to 930 * @data: data to write at register offset 931 * @locked: semaphore has already been acquired or not 932 * 933 * Acquires semaphore, if necessary. Then write the data to PHY register 934 * at the offset using the kumeran interface. Release any acquired semaphores 935 * before exiting. 936 **/ 937static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 938 bool locked) 939{ 940 u32 kmrnctrlsta; 941 942 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 943 944 if (!locked) { 945 s32 ret_val = E1000_SUCCESS; 946 947 if (!hw->phy.ops.acquire) 948 return E1000_SUCCESS; 949 950 ret_val = hw->phy.ops.acquire(hw); 951 if (ret_val) 952 return ret_val; 953 } 954 955 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 956 E1000_KMRNCTRLSTA_OFFSET) | data; 957 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 958 E1000_WRITE_FLUSH(hw); 959 960 usec_delay(2); 961 962 if (!locked) 963 hw->phy.ops.release(hw); 964 965 return E1000_SUCCESS; 966} 967 968/** 969 * e1000_write_kmrn_reg_generic - Write kumeran register 970 * @hw: pointer to the HW structure 971 * @offset: register offset to write to 972 * @data: data to write at register offset 973 * 974 * Acquires semaphore then writes the data to the PHY register at the offset 975 * using the kumeran interface. Release the acquired semaphore before exiting. 976 **/ 977s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 978{ 979 return __e1000_write_kmrn_reg(hw, offset, data, FALSE); 980} 981 982/** 983 * e1000_write_kmrn_reg_locked - Write kumeran register 984 * @hw: pointer to the HW structure 985 * @offset: register offset to write to 986 * @data: data to write at register offset 987 * 988 * Write the data to PHY register at the offset using the kumeran interface. 989 * Assumes semaphore already acquired. 990 **/ 991s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 992{ 993 return __e1000_write_kmrn_reg(hw, offset, data, TRUE); 994} 995 996/** 997 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode 998 * @hw: pointer to the HW structure 999 * 1000 * Sets up Master/slave mode 1001 **/ 1002static s32 e1000_set_master_slave_mode(struct e1000_hw *hw) 1003{ 1004 s32 ret_val; 1005 u16 phy_data; 1006 1007 /* Resolve Master/Slave mode */ 1008 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); 1009 if (ret_val) 1010 return ret_val; 1011 1012 /* load defaults for future use */ 1013 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 1014 ((phy_data & CR_1000T_MS_VALUE) ? 1015 e1000_ms_force_master : 1016 e1000_ms_force_slave) : e1000_ms_auto; 1017 1018 switch (hw->phy.ms_type) { 1019 case e1000_ms_force_master: 1020 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1021 break; 1022 case e1000_ms_force_slave: 1023 phy_data |= CR_1000T_MS_ENABLE; 1024 phy_data &= ~(CR_1000T_MS_VALUE); 1025 break; 1026 case e1000_ms_auto: 1027 phy_data &= ~CR_1000T_MS_ENABLE; 1028 /* fall-through */ 1029 default: 1030 break; 1031 } 1032 1033 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 1034} 1035 1036/** 1037 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 1038 * @hw: pointer to the HW structure 1039 * 1040 * Sets up Carrier-sense on Transmit and downshift values. 1041 **/ 1042s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 1043{ 1044 s32 ret_val; 1045 u16 phy_data; 1046 1047 DEBUGFUNC("e1000_copper_link_setup_82577"); 1048 1049 if (hw->phy.type == e1000_phy_82580) { 1050 ret_val = hw->phy.ops.reset(hw); 1051 if (ret_val) { 1052 DEBUGOUT("Error resetting the PHY.\n"); 1053 return ret_val; 1054 } 1055 } 1056 1057 /* Enable CRS on Tx. This must be set for half-duplex operation. 1058 * Not required on some PHYs. 1059 */ 1060 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data); 1061 if (ret_val) 1062 return ret_val; 1063 1064 if ((hw->phy.type != e1000_phy_82579) && 1065 (hw->phy.type != e1000_phy_i217)) 1066 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 1067 1068 /* Enable downshift */ 1069 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 1070 1071 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data); 1072 if (ret_val) 1073 return ret_val; 1074 1075 /* Set MDI/MDIX mode */ 1076 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data); 1077 if (ret_val) 1078 return ret_val; 1079 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; 1080 /* Options: 1081 * 0 - Auto (default) 1082 * 1 - MDI mode 1083 * 2 - MDI-X mode 1084 */ 1085 switch (hw->phy.mdix) { 1086 case 1: 1087 break; 1088 case 2: 1089 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; 1090 break; 1091 case 0: 1092 default: 1093 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; 1094 break; 1095 } 1096 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); 1097 if (ret_val) 1098 return ret_val; 1099 1100 return e1000_set_master_slave_mode(hw); 1101} 1102 1103/** 1104 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 1105 * @hw: pointer to the HW structure 1106 * 1107 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 1108 * and downshift values are set also. 1109 **/ 1110s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 1111{ 1112 struct e1000_phy_info *phy = &hw->phy; 1113 s32 ret_val; 1114 u16 phy_data; 1115 1116 DEBUGFUNC("e1000_copper_link_setup_m88"); 1117 1118 1119 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1120 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1121 if (ret_val) 1122 return ret_val; 1123 1124 /* For BM PHY this bit is downshift enable */ 1125 if (phy->type != e1000_phy_bm) 1126 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1127 1128 /* Options: 1129 * MDI/MDI-X = 0 (default) 1130 * 0 - Auto for all speeds 1131 * 1 - MDI mode 1132 * 2 - MDI-X mode 1133 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1134 */ 1135 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1136 1137 switch (phy->mdix) { 1138 case 1: 1139 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1140 break; 1141 case 2: 1142 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1143 break; 1144 case 3: 1145 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1146 break; 1147 case 0: 1148 default: 1149 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1150 break; 1151 } 1152 1153 /* Options: 1154 * disable_polarity_correction = 0 (default) 1155 * Automatic Correction for Reversed Cable Polarity 1156 * 0 - Disabled 1157 * 1 - Enabled 1158 */ 1159 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1160 if (phy->disable_polarity_correction) 1161 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1162 1163 /* Enable downshift on BM (disabled by default) */ 1164 if (phy->type == e1000_phy_bm) { 1165 /* For 82574/82583, first disable then enable downshift */ 1166 if (phy->id == BME1000_E_PHY_ID_R2) { 1167 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; 1168 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1169 phy_data); 1170 if (ret_val) 1171 return ret_val; 1172 /* Commit the changes. */ 1173 ret_val = phy->ops.commit(hw); 1174 if (ret_val) { 1175 DEBUGOUT("Error committing the PHY changes\n"); 1176 return ret_val; 1177 } 1178 } 1179 1180 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 1181 } 1182 1183 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1184 if (ret_val) 1185 return ret_val; 1186 1187 if ((phy->type == e1000_phy_m88) && 1188 (phy->revision < E1000_REVISION_4) && 1189 (phy->id != BME1000_E_PHY_ID_R2)) { 1190 /* Force TX_CLK in the Extended PHY Specific Control Register 1191 * to 25MHz clock. 1192 */ 1193 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1194 &phy_data); 1195 if (ret_val) 1196 return ret_val; 1197 1198 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1199 1200 if ((phy->revision == E1000_REVISION_2) && 1201 (phy->id == M88E1111_I_PHY_ID)) { 1202 /* 82573L PHY - set the downshift counter to 5x. */ 1203 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 1204 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1205 } else { 1206 /* Configure Master and Slave downshift values */ 1207 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1208 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1209 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1210 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1211 } 1212 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1213 phy_data); 1214 if (ret_val) 1215 return ret_val; 1216 } 1217 1218 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 1219 /* Set PHY page 0, register 29 to 0x0003 */ 1220 ret_val = phy->ops.write_reg(hw, 29, 0x0003); 1221 if (ret_val) 1222 return ret_val; 1223 1224 /* Set PHY page 0, register 30 to 0x0000 */ 1225 ret_val = phy->ops.write_reg(hw, 30, 0x0000); 1226 if (ret_val) 1227 return ret_val; 1228 } 1229 1230 /* Commit the changes. */ 1231 ret_val = phy->ops.commit(hw); 1232 if (ret_val) { 1233 DEBUGOUT("Error committing the PHY changes\n"); 1234 return ret_val; 1235 } 1236 1237 if (phy->type == e1000_phy_82578) { 1238 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1239 &phy_data); 1240 if (ret_val) 1241 return ret_val; 1242 1243 /* 82578 PHY - set the downshift count to 1x. */ 1244 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 1245 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 1246 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1247 phy_data); 1248 if (ret_val) 1249 return ret_val; 1250 } 1251 1252 if (phy->type == e1000_phy_i210) { 1253 ret_val = e1000_set_master_slave_mode(hw); 1254 if (ret_val) 1255 return ret_val; 1256 } 1257 1258 return E1000_SUCCESS; 1259} 1260 1261/** 1262 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 1263 * @hw: pointer to the HW structure 1264 * 1265 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 1266 * Also enables and sets the downshift parameters. 1267 **/ 1268s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw) 1269{ 1270 struct e1000_phy_info *phy = &hw->phy; 1271 s32 ret_val; 1272 u16 phy_data; 1273 1274 DEBUGFUNC("e1000_copper_link_setup_m88_gen2"); 1275 1276 1277 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1278 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1279 if (ret_val) 1280 return ret_val; 1281 1282 /* Options: 1283 * MDI/MDI-X = 0 (default) 1284 * 0 - Auto for all speeds 1285 * 1 - MDI mode 1286 * 2 - MDI-X mode 1287 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1288 */ 1289 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1290 1291 switch (phy->mdix) { 1292 case 1: 1293 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1294 break; 1295 case 2: 1296 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1297 break; 1298 case 3: 1299 /* M88E1112 does not support this mode) */ 1300 if (phy->id != M88E1112_E_PHY_ID) { 1301 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1302 break; 1303 } 1304 case 0: 1305 default: 1306 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1307 break; 1308 } 1309 1310 /* Options: 1311 * disable_polarity_correction = 0 (default) 1312 * Automatic Correction for Reversed Cable Polarity 1313 * 0 - Disabled 1314 * 1 - Enabled 1315 */ 1316 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1317 if (phy->disable_polarity_correction) 1318 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1319 1320 /* Enable downshift and setting it to X6 */ 1321 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 1322 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 1323 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 1324 1325 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1326 if (ret_val) 1327 return ret_val; 1328 1329 /* Commit the changes. */ 1330 ret_val = phy->ops.commit(hw); 1331 if (ret_val) { 1332 DEBUGOUT("Error committing the PHY changes\n"); 1333 return ret_val; 1334 } 1335 1336 return E1000_SUCCESS; 1337} 1338 1339/** 1340 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 1341 * @hw: pointer to the HW structure 1342 * 1343 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 1344 * igp PHY's. 1345 **/ 1346s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 1347{ 1348 struct e1000_phy_info *phy = &hw->phy; 1349 s32 ret_val; 1350 u16 data; 1351 1352 DEBUGFUNC("e1000_copper_link_setup_igp"); 1353 1354 1355 ret_val = hw->phy.ops.reset(hw); 1356 if (ret_val) { 1357 DEBUGOUT("Error resetting the PHY.\n"); 1358 return ret_val; 1359 } 1360 1361 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid 1362 * timeout issues when LFS is enabled. 1363 */ 1364 msec_delay(100); 1365 1366 /* The NVM settings will configure LPLU in D3 for 1367 * non-IGP1 PHYs. 1368 */ 1369 if (phy->type == e1000_phy_igp) { 1370 /* disable lplu d3 during driver init */ 1371 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE); 1372 if (ret_val) { 1373 DEBUGOUT("Error Disabling LPLU D3\n"); 1374 return ret_val; 1375 } 1376 } 1377 1378 /* disable lplu d0 during driver init */ 1379 if (hw->phy.ops.set_d0_lplu_state) { 1380 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE); 1381 if (ret_val) { 1382 DEBUGOUT("Error Disabling LPLU D0\n"); 1383 return ret_val; 1384 } 1385 } 1386 /* Configure mdi-mdix settings */ 1387 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 1388 if (ret_val) 1389 return ret_val; 1390 1391 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1392 1393 switch (phy->mdix) { 1394 case 1: 1395 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1396 break; 1397 case 2: 1398 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1399 break; 1400 case 0: 1401 default: 1402 data |= IGP01E1000_PSCR_AUTO_MDIX; 1403 break; 1404 } 1405 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 1406 if (ret_val) 1407 return ret_val; 1408 1409 /* set auto-master slave resolution settings */ 1410 if (hw->mac.autoneg) { 1411 /* when autonegotiation advertisement is only 1000Mbps then we 1412 * should disable SmartSpeed and enable Auto MasterSlave 1413 * resolution as hardware default. 1414 */ 1415 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 1416 /* Disable SmartSpeed */ 1417 ret_val = phy->ops.read_reg(hw, 1418 IGP01E1000_PHY_PORT_CONFIG, 1419 &data); 1420 if (ret_val) 1421 return ret_val; 1422 1423 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1424 ret_val = phy->ops.write_reg(hw, 1425 IGP01E1000_PHY_PORT_CONFIG, 1426 data); 1427 if (ret_val) 1428 return ret_val; 1429 1430 /* Set auto Master/Slave resolution process */ 1431 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1432 if (ret_val) 1433 return ret_val; 1434 1435 data &= ~CR_1000T_MS_ENABLE; 1436 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1437 if (ret_val) 1438 return ret_val; 1439 } 1440 1441 ret_val = e1000_set_master_slave_mode(hw); 1442 } 1443 1444 return ret_val; 1445} 1446 1447/** 1448 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 1449 * @hw: pointer to the HW structure 1450 * 1451 * Reads the MII auto-neg advertisement register and/or the 1000T control 1452 * register and if the PHY is already setup for auto-negotiation, then 1453 * return successful. Otherwise, setup advertisement and flow control to 1454 * the appropriate values for the wanted auto-negotiation. 1455 **/ 1456s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1457{ 1458 struct e1000_phy_info *phy = &hw->phy; 1459 s32 ret_val; 1460 u16 mii_autoneg_adv_reg; 1461 u16 mii_1000t_ctrl_reg = 0; 1462 1463 DEBUGFUNC("e1000_phy_setup_autoneg"); 1464 1465 phy->autoneg_advertised &= phy->autoneg_mask; 1466 1467 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1468 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1469 if (ret_val) 1470 return ret_val; 1471 1472 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1473 /* Read the MII 1000Base-T Control Register (Address 9). */ 1474 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1475 &mii_1000t_ctrl_reg); 1476 if (ret_val) 1477 return ret_val; 1478 } 1479 1480 /* Need to parse both autoneg_advertised and fc and set up 1481 * the appropriate PHY registers. First we will parse for 1482 * autoneg_advertised software override. Since we can advertise 1483 * a plethora of combinations, we need to check each bit 1484 * individually. 1485 */ 1486 1487 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1488 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1489 * the 1000Base-T Control Register (Address 9). 1490 */ 1491 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1492 NWAY_AR_100TX_HD_CAPS | 1493 NWAY_AR_10T_FD_CAPS | 1494 NWAY_AR_10T_HD_CAPS); 1495 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1496 1497 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 1498 1499 /* Do we want to advertise 10 Mb Half Duplex? */ 1500 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1501 DEBUGOUT("Advertise 10mb Half duplex\n"); 1502 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1503 } 1504 1505 /* Do we want to advertise 10 Mb Full Duplex? */ 1506 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1507 DEBUGOUT("Advertise 10mb Full duplex\n"); 1508 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1509 } 1510 1511 /* Do we want to advertise 100 Mb Half Duplex? */ 1512 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1513 DEBUGOUT("Advertise 100mb Half duplex\n"); 1514 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1515 } 1516 1517 /* Do we want to advertise 100 Mb Full Duplex? */ 1518 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1519 DEBUGOUT("Advertise 100mb Full duplex\n"); 1520 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1521 } 1522 1523 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1524 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1525 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 1526 1527 /* Do we want to advertise 1000 Mb Full Duplex? */ 1528 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1529 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1530 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1531 } 1532 1533 /* Check for a software override of the flow control settings, and 1534 * setup the PHY advertisement registers accordingly. If 1535 * auto-negotiation is enabled, then software will have to set the 1536 * "PAUSE" bits to the correct value in the Auto-Negotiation 1537 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1538 * negotiation. 1539 * 1540 * The possible values of the "fc" parameter are: 1541 * 0: Flow control is completely disabled 1542 * 1: Rx flow control is enabled (we can receive pause frames 1543 * but not send pause frames). 1544 * 2: Tx flow control is enabled (we can send pause frames 1545 * but we do not support receiving pause frames). 1546 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1547 * other: No software override. The flow control configuration 1548 * in the EEPROM is used. 1549 */ 1550 switch (hw->fc.current_mode) { 1551 case e1000_fc_none: 1552 /* Flow control (Rx & Tx) is completely disabled by a 1553 * software over-ride. 1554 */ 1555 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1556 break; 1557 case e1000_fc_rx_pause: 1558 /* Rx Flow control is enabled, and Tx Flow control is 1559 * disabled, by a software over-ride. 1560 * 1561 * Since there really isn't a way to advertise that we are 1562 * capable of Rx Pause ONLY, we will advertise that we 1563 * support both symmetric and asymmetric Rx PAUSE. Later 1564 * (in e1000_config_fc_after_link_up) we will disable the 1565 * hw's ability to send PAUSE frames. 1566 */ 1567 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1568 break; 1569 case e1000_fc_tx_pause: 1570 /* Tx Flow control is enabled, and Rx Flow control is 1571 * disabled, by a software over-ride. 1572 */ 1573 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1574 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1575 break; 1576 case e1000_fc_full: 1577 /* Flow control (both Rx and Tx) is enabled by a software 1578 * over-ride. 1579 */ 1580 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1581 break; 1582 default: 1583 DEBUGOUT("Flow control param set incorrectly\n"); 1584 return -E1000_ERR_CONFIG; 1585 } 1586 1587 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1588 if (ret_val) 1589 return ret_val; 1590 1591 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1592 1593 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 1594 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, 1595 mii_1000t_ctrl_reg); 1596 1597 return ret_val; 1598} 1599 1600/** 1601 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1602 * @hw: pointer to the HW structure 1603 * 1604 * Performs initial bounds checking on autoneg advertisement parameter, then 1605 * configure to advertise the full capability. Setup the PHY to autoneg 1606 * and restart the negotiation process between the link partner. If 1607 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1608 **/ 1609s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1610{ 1611 struct e1000_phy_info *phy = &hw->phy; 1612 s32 ret_val; 1613 u16 phy_ctrl; 1614 1615 DEBUGFUNC("e1000_copper_link_autoneg"); 1616 1617 /* Perform some bounds checking on the autoneg advertisement 1618 * parameter. 1619 */ 1620 phy->autoneg_advertised &= phy->autoneg_mask; 1621 1622 /* If autoneg_advertised is zero, we assume it was not defaulted 1623 * by the calling code so we set to advertise full capability. 1624 */ 1625 if (!phy->autoneg_advertised) 1626 phy->autoneg_advertised = phy->autoneg_mask; 1627 1628 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1629 ret_val = e1000_phy_setup_autoneg(hw); 1630 if (ret_val) { 1631 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1632 return ret_val; 1633 } 1634 DEBUGOUT("Restarting Auto-Neg\n"); 1635 1636 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1637 * the Auto Neg Restart bit in the PHY control register. 1638 */ 1639 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1640 if (ret_val) 1641 return ret_val; 1642 1643 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1644 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1645 if (ret_val) 1646 return ret_val; 1647 1648 /* Does the user want to wait for Auto-Neg to complete here, or 1649 * check at a later time (for example, callback routine). 1650 */ 1651 if (phy->autoneg_wait_to_complete) { 1652 ret_val = e1000_wait_autoneg(hw); 1653 if (ret_val) { 1654 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1655 return ret_val; 1656 } 1657 } 1658 1659 hw->mac.get_link_status = TRUE; 1660 1661 return ret_val; 1662} 1663 1664/** 1665 * e1000_setup_copper_link_generic - Configure copper link settings 1666 * @hw: pointer to the HW structure 1667 * 1668 * Calls the appropriate function to configure the link for auto-neg or forced 1669 * speed and duplex. Then we check for link, once link is established calls 1670 * to configure collision distance and flow control are called. If link is 1671 * not established, we return -E1000_ERR_PHY (-2). 1672 **/ 1673s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1674{ 1675 s32 ret_val; 1676 bool link; 1677 1678 DEBUGFUNC("e1000_setup_copper_link_generic"); 1679 1680 if (hw->mac.autoneg) { 1681 /* Setup autoneg and flow control advertisement and perform 1682 * autonegotiation. 1683 */ 1684 ret_val = e1000_copper_link_autoneg(hw); 1685 if (ret_val) 1686 return ret_val; 1687 } else { 1688 /* PHY will be set to 10H, 10F, 100H or 100F 1689 * depending on user settings. 1690 */ 1691 DEBUGOUT("Forcing Speed and Duplex\n"); 1692 ret_val = hw->phy.ops.force_speed_duplex(hw); 1693 if (ret_val) { 1694 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1695 return ret_val; 1696 } 1697 } 1698 1699 /* Check link status. Wait up to 100 microseconds for link to become 1700 * valid. 1701 */ 1702 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 1703 &link); 1704 if (ret_val) 1705 return ret_val; 1706 1707 if (link) { 1708 DEBUGOUT("Valid link established!!!\n"); 1709 hw->mac.ops.config_collision_dist(hw); 1710 ret_val = e1000_config_fc_after_link_up_generic(hw); 1711 } else { 1712 DEBUGOUT("Unable to establish link!!!\n"); 1713 } 1714 1715 return ret_val; 1716} 1717 1718/** 1719 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1720 * @hw: pointer to the HW structure 1721 * 1722 * Calls the PHY setup function to force speed and duplex. Clears the 1723 * auto-crossover to force MDI manually. Waits for link and returns 1724 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1725 **/ 1726s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1727{ 1728 struct e1000_phy_info *phy = &hw->phy; 1729 s32 ret_val; 1730 u16 phy_data; 1731 bool link; 1732 1733 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1734 1735 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1736 if (ret_val) 1737 return ret_val; 1738 1739 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1740 1741 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1742 if (ret_val) 1743 return ret_val; 1744 1745 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1746 * forced whenever speed and duplex are forced. 1747 */ 1748 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1749 if (ret_val) 1750 return ret_val; 1751 1752 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1753 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1754 1755 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1756 if (ret_val) 1757 return ret_val; 1758 1759 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1760 1761 usec_delay(1); 1762 1763 if (phy->autoneg_wait_to_complete) { 1764 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1765 1766 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1767 100000, &link); 1768 if (ret_val) 1769 return ret_val; 1770 1771 if (!link) 1772 DEBUGOUT("Link taking longer than expected.\n"); 1773 1774 /* Try once more */ 1775 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1776 100000, &link); 1777 } 1778 1779 return ret_val; 1780} 1781 1782/** 1783 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1784 * @hw: pointer to the HW structure 1785 * 1786 * Calls the PHY setup function to force speed and duplex. Clears the 1787 * auto-crossover to force MDI manually. Resets the PHY to commit the 1788 * changes. If time expires while waiting for link up, we reset the DSP. 1789 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1790 * successful completion, else return corresponding error code. 1791 **/ 1792s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1793{ 1794 struct e1000_phy_info *phy = &hw->phy; 1795 s32 ret_val; 1796 u16 phy_data; 1797 bool link; 1798 1799 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1800 1801 /* I210 and I211 devices support Auto-Crossover in forced operation. */ 1802 if (phy->type != e1000_phy_i210) { 1803 /* Clear Auto-Crossover to force MDI manually. M88E1000 1804 * requires MDI forced whenever speed and duplex are forced. 1805 */ 1806 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, 1807 &phy_data); 1808 if (ret_val) 1809 return ret_val; 1810 1811 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1812 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1813 phy_data); 1814 if (ret_val) 1815 return ret_val; 1816 } 1817 1818 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1819 1820 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1821 if (ret_val) 1822 return ret_val; 1823 1824 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1825 1826 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1827 if (ret_val) 1828 return ret_val; 1829 1830 /* Reset the phy to commit changes. */ 1831 ret_val = hw->phy.ops.commit(hw); 1832 if (ret_val) 1833 return ret_val; 1834 1835 if (phy->autoneg_wait_to_complete) { 1836 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1837 1838 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1839 100000, &link); 1840 if (ret_val) 1841 return ret_val; 1842 1843 if (!link) { 1844 bool reset_dsp = TRUE; 1845 1846 switch (hw->phy.id) { 1847 case I347AT4_E_PHY_ID: 1848 case M88E1340M_E_PHY_ID: 1849 case M88E1112_E_PHY_ID: 1850 case I210_I_PHY_ID: 1851 reset_dsp = FALSE; 1852 break; 1853 default: 1854 if (hw->phy.type != e1000_phy_m88) 1855 reset_dsp = FALSE; 1856 break; 1857 } 1858 1859 if (!reset_dsp) { 1860 DEBUGOUT("Link taking longer than expected.\n"); 1861 } else { 1862 /* We didn't get link. 1863 * Reset the DSP and cross our fingers. 1864 */ 1865 ret_val = phy->ops.write_reg(hw, 1866 M88E1000_PHY_PAGE_SELECT, 1867 0x001d); 1868 if (ret_val) 1869 return ret_val; 1870 ret_val = e1000_phy_reset_dsp_generic(hw); 1871 if (ret_val) 1872 return ret_val; 1873 } 1874 } 1875 1876 /* Try once more */ 1877 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1878 100000, &link); 1879 if (ret_val) 1880 return ret_val; 1881 } 1882 1883 if (hw->phy.type != e1000_phy_m88) 1884 return E1000_SUCCESS; 1885 1886 if (hw->phy.id == I347AT4_E_PHY_ID || 1887 hw->phy.id == M88E1340M_E_PHY_ID || 1888 hw->phy.id == M88E1112_E_PHY_ID) 1889 return E1000_SUCCESS; 1890 if (hw->phy.id == I210_I_PHY_ID) 1891 return E1000_SUCCESS; 1892 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1893 if (ret_val) 1894 return ret_val; 1895 1896 /* Resetting the phy means we need to re-force TX_CLK in the 1897 * Extended PHY Specific Control Register to 25MHz clock from 1898 * the reset value of 2.5MHz. 1899 */ 1900 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1901 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1902 if (ret_val) 1903 return ret_val; 1904 1905 /* In addition, we must re-enable CRS on Tx for both half and full 1906 * duplex. 1907 */ 1908 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1909 if (ret_val) 1910 return ret_val; 1911 1912 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1913 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1914 1915 return ret_val; 1916} 1917 1918/** 1919 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1920 * @hw: pointer to the HW structure 1921 * 1922 * Forces the speed and duplex settings of the PHY. 1923 * This is a function pointer entry point only called by 1924 * PHY setup routines. 1925 **/ 1926s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1927{ 1928 struct e1000_phy_info *phy = &hw->phy; 1929 s32 ret_val; 1930 u16 data; 1931 bool link; 1932 1933 DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1934 1935 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1936 if (ret_val) 1937 return ret_val; 1938 1939 e1000_phy_force_speed_duplex_setup(hw, &data); 1940 1941 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1942 if (ret_val) 1943 return ret_val; 1944 1945 /* Disable MDI-X support for 10/100 */ 1946 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1947 if (ret_val) 1948 return ret_val; 1949 1950 data &= ~IFE_PMC_AUTO_MDIX; 1951 data &= ~IFE_PMC_FORCE_MDIX; 1952 1953 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1954 if (ret_val) 1955 return ret_val; 1956 1957 DEBUGOUT1("IFE PMC: %X\n", data); 1958 1959 usec_delay(1); 1960 1961 if (phy->autoneg_wait_to_complete) { 1962 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1963 1964 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1965 100000, &link); 1966 if (ret_val) 1967 return ret_val; 1968 1969 if (!link) 1970 DEBUGOUT("Link taking longer than expected.\n"); 1971 1972 /* Try once more */ 1973 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1974 100000, &link); 1975 if (ret_val) 1976 return ret_val; 1977 } 1978 1979 return E1000_SUCCESS; 1980} 1981 1982/** 1983 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1984 * @hw: pointer to the HW structure 1985 * @phy_ctrl: pointer to current value of PHY_CONTROL 1986 * 1987 * Forces speed and duplex on the PHY by doing the following: disable flow 1988 * control, force speed/duplex on the MAC, disable auto speed detection, 1989 * disable auto-negotiation, configure duplex, configure speed, configure 1990 * the collision distance, write configuration to CTRL register. The 1991 * caller must write to the PHY_CONTROL register for these settings to 1992 * take affect. 1993 **/ 1994void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1995{ 1996 struct e1000_mac_info *mac = &hw->mac; 1997 u32 ctrl; 1998 1999 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 2000 2001 /* Turn off flow control when forcing speed/duplex */ 2002 hw->fc.current_mode = e1000_fc_none; 2003 2004 /* Force speed/duplex on the mac */ 2005 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2006 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2007 ctrl &= ~E1000_CTRL_SPD_SEL; 2008 2009 /* Disable Auto Speed Detection */ 2010 ctrl &= ~E1000_CTRL_ASDE; 2011 2012 /* Disable autoneg on the phy */ 2013 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 2014 2015 /* Forcing Full or Half Duplex? */ 2016 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 2017 ctrl &= ~E1000_CTRL_FD; 2018 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 2019 DEBUGOUT("Half Duplex\n"); 2020 } else { 2021 ctrl |= E1000_CTRL_FD; 2022 *phy_ctrl |= MII_CR_FULL_DUPLEX; 2023 DEBUGOUT("Full Duplex\n"); 2024 } 2025 2026 /* Forcing 10mb or 100mb? */ 2027 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 2028 ctrl |= E1000_CTRL_SPD_100; 2029 *phy_ctrl |= MII_CR_SPEED_100; 2030 *phy_ctrl &= ~MII_CR_SPEED_1000; 2031 DEBUGOUT("Forcing 100mb\n"); 2032 } else { 2033 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2034 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 2035 DEBUGOUT("Forcing 10mb\n"); 2036 } 2037 2038 hw->mac.ops.config_collision_dist(hw); 2039 2040 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2041} 2042 2043/** 2044 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 2045 * @hw: pointer to the HW structure 2046 * @active: boolean used to enable/disable lplu 2047 * 2048 * Success returns 0, Failure returns 1 2049 * 2050 * The low power link up (lplu) state is set to the power management level D3 2051 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 2052 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 2053 * is used during Dx states where the power conservation is most important. 2054 * During driver activity, SmartSpeed should be enabled so performance is 2055 * maintained. 2056 **/ 2057s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 2058{ 2059 struct e1000_phy_info *phy = &hw->phy; 2060 s32 ret_val; 2061 u16 data; 2062 2063 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 2064 2065 if (!hw->phy.ops.read_reg) 2066 return E1000_SUCCESS; 2067 2068 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 2069 if (ret_val) 2070 return ret_val; 2071 2072 if (!active) { 2073 data &= ~IGP02E1000_PM_D3_LPLU; 2074 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2075 data); 2076 if (ret_val) 2077 return ret_val; 2078 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2079 * during Dx states where the power conservation is most 2080 * important. During driver activity we should enable 2081 * SmartSpeed, so performance is maintained. 2082 */ 2083 if (phy->smart_speed == e1000_smart_speed_on) { 2084 ret_val = phy->ops.read_reg(hw, 2085 IGP01E1000_PHY_PORT_CONFIG, 2086 &data); 2087 if (ret_val) 2088 return ret_val; 2089 2090 data |= IGP01E1000_PSCFR_SMART_SPEED; 2091 ret_val = phy->ops.write_reg(hw, 2092 IGP01E1000_PHY_PORT_CONFIG, 2093 data); 2094 if (ret_val) 2095 return ret_val; 2096 } else if (phy->smart_speed == e1000_smart_speed_off) { 2097 ret_val = phy->ops.read_reg(hw, 2098 IGP01E1000_PHY_PORT_CONFIG, 2099 &data); 2100 if (ret_val) 2101 return ret_val; 2102 2103 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2104 ret_val = phy->ops.write_reg(hw, 2105 IGP01E1000_PHY_PORT_CONFIG, 2106 data); 2107 if (ret_val) 2108 return ret_val; 2109 } 2110 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 2111 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 2112 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 2113 data |= IGP02E1000_PM_D3_LPLU; 2114 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2115 data); 2116 if (ret_val) 2117 return ret_val; 2118 2119 /* When LPLU is enabled, we should disable SmartSpeed */ 2120 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2121 &data); 2122 if (ret_val) 2123 return ret_val; 2124 2125 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2126 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2127 data); 2128 } 2129 2130 return ret_val; 2131} 2132 2133/** 2134 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 2135 * @hw: pointer to the HW structure 2136 * 2137 * Success returns 0, Failure returns 1 2138 * 2139 * A downshift is detected by querying the PHY link health. 2140 **/ 2141s32 e1000_check_downshift_generic(struct e1000_hw *hw) 2142{ 2143 struct e1000_phy_info *phy = &hw->phy; 2144 s32 ret_val; 2145 u16 phy_data, offset, mask; 2146 2147 DEBUGFUNC("e1000_check_downshift_generic"); 2148 2149 switch (phy->type) { 2150 case e1000_phy_i210: 2151 case e1000_phy_m88: 2152 case e1000_phy_gg82563: 2153 case e1000_phy_bm: 2154 case e1000_phy_82578: 2155 offset = M88E1000_PHY_SPEC_STATUS; 2156 mask = M88E1000_PSSR_DOWNSHIFT; 2157 break; 2158 case e1000_phy_igp: 2159 case e1000_phy_igp_2: 2160 case e1000_phy_igp_3: 2161 offset = IGP01E1000_PHY_LINK_HEALTH; 2162 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 2163 break; 2164 default: 2165 /* speed downshift not supported */ 2166 phy->speed_downgraded = FALSE; 2167 return E1000_SUCCESS; 2168 } 2169 2170 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2171 2172 if (!ret_val) 2173 phy->speed_downgraded = !!(phy_data & mask); 2174 2175 return ret_val; 2176} 2177 2178/** 2179 * e1000_check_polarity_m88 - Checks the polarity. 2180 * @hw: pointer to the HW structure 2181 * 2182 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2183 * 2184 * Polarity is determined based on the PHY specific status register. 2185 **/ 2186s32 e1000_check_polarity_m88(struct e1000_hw *hw) 2187{ 2188 struct e1000_phy_info *phy = &hw->phy; 2189 s32 ret_val; 2190 u16 data; 2191 2192 DEBUGFUNC("e1000_check_polarity_m88"); 2193 2194 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 2195 2196 if (!ret_val) 2197 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 2198 ? e1000_rev_polarity_reversed 2199 : e1000_rev_polarity_normal; 2200 2201 return ret_val; 2202} 2203 2204/** 2205 * e1000_check_polarity_igp - Checks the polarity. 2206 * @hw: pointer to the HW structure 2207 * 2208 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2209 * 2210 * Polarity is determined based on the PHY port status register, and the 2211 * current speed (since there is no polarity at 100Mbps). 2212 **/ 2213s32 e1000_check_polarity_igp(struct e1000_hw *hw) 2214{ 2215 struct e1000_phy_info *phy = &hw->phy; 2216 s32 ret_val; 2217 u16 data, offset, mask; 2218 2219 DEBUGFUNC("e1000_check_polarity_igp"); 2220 2221 /* Polarity is determined based on the speed of 2222 * our connection. 2223 */ 2224 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2225 if (ret_val) 2226 return ret_val; 2227 2228 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2229 IGP01E1000_PSSR_SPEED_1000MBPS) { 2230 offset = IGP01E1000_PHY_PCS_INIT_REG; 2231 mask = IGP01E1000_PHY_POLARITY_MASK; 2232 } else { 2233 /* This really only applies to 10Mbps since 2234 * there is no polarity for 100Mbps (always 0). 2235 */ 2236 offset = IGP01E1000_PHY_PORT_STATUS; 2237 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 2238 } 2239 2240 ret_val = phy->ops.read_reg(hw, offset, &data); 2241 2242 if (!ret_val) 2243 phy->cable_polarity = (data & mask) 2244 ? e1000_rev_polarity_reversed 2245 : e1000_rev_polarity_normal; 2246 2247 return ret_val; 2248} 2249 2250/** 2251 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 2252 * @hw: pointer to the HW structure 2253 * 2254 * Polarity is determined on the polarity reversal feature being enabled. 2255 **/ 2256s32 e1000_check_polarity_ife(struct e1000_hw *hw) 2257{ 2258 struct e1000_phy_info *phy = &hw->phy; 2259 s32 ret_val; 2260 u16 phy_data, offset, mask; 2261 2262 DEBUGFUNC("e1000_check_polarity_ife"); 2263 2264 /* Polarity is determined based on the reversal feature being enabled. 2265 */ 2266 if (phy->polarity_correction) { 2267 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 2268 mask = IFE_PESC_POLARITY_REVERSED; 2269 } else { 2270 offset = IFE_PHY_SPECIAL_CONTROL; 2271 mask = IFE_PSC_FORCE_POLARITY; 2272 } 2273 2274 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2275 2276 if (!ret_val) 2277 phy->cable_polarity = (phy_data & mask) 2278 ? e1000_rev_polarity_reversed 2279 : e1000_rev_polarity_normal; 2280 2281 return ret_val; 2282} 2283 2284/** 2285 * e1000_wait_autoneg - Wait for auto-neg completion 2286 * @hw: pointer to the HW structure 2287 * 2288 * Waits for auto-negotiation to complete or for the auto-negotiation time 2289 * limit to expire, which ever happens first. 2290 **/ 2291static s32 e1000_wait_autoneg(struct e1000_hw *hw) 2292{ 2293 s32 ret_val = E1000_SUCCESS; 2294 u16 i, phy_status; 2295 2296 DEBUGFUNC("e1000_wait_autoneg"); 2297 2298 if (!hw->phy.ops.read_reg) 2299 return E1000_SUCCESS; 2300 2301 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 2302 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 2303 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2304 if (ret_val) 2305 break; 2306 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2307 if (ret_val) 2308 break; 2309 if (phy_status & MII_SR_AUTONEG_COMPLETE) 2310 break; 2311 msec_delay(100); 2312 } 2313 2314 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 2315 * has completed. 2316 */ 2317 return ret_val; 2318} 2319 2320/** 2321 * e1000_phy_has_link_generic - Polls PHY for link 2322 * @hw: pointer to the HW structure 2323 * @iterations: number of times to poll for link 2324 * @usec_interval: delay between polling attempts 2325 * @success: pointer to whether polling was successful or not 2326 * 2327 * Polls the PHY status register for link, 'iterations' number of times. 2328 **/ 2329s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 2330 u32 usec_interval, bool *success) 2331{ 2332 s32 ret_val = E1000_SUCCESS; 2333 u16 i, phy_status; 2334 2335 DEBUGFUNC("e1000_phy_has_link_generic"); 2336 2337 if (!hw->phy.ops.read_reg) 2338 return E1000_SUCCESS; 2339 2340 for (i = 0; i < iterations; i++) { 2341 /* Some PHYs require the PHY_STATUS register to be read 2342 * twice due to the link bit being sticky. No harm doing 2343 * it across the board. 2344 */ 2345 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2346 if (ret_val) 2347 /* If the first read fails, another entity may have 2348 * ownership of the resources, wait and try again to 2349 * see if they have relinquished the resources yet. 2350 */ 2351 usec_delay(usec_interval); 2352 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2353 if (ret_val) 2354 break; 2355 if (phy_status & MII_SR_LINK_STATUS) 2356 break; 2357 if (usec_interval >= 1000) 2358 msec_delay_irq(usec_interval/1000); 2359 else 2360 usec_delay(usec_interval); 2361 } 2362 2363 *success = (i < iterations); 2364 2365 return ret_val; 2366} 2367 2368/** 2369 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 2370 * @hw: pointer to the HW structure 2371 * 2372 * Reads the PHY specific status register to retrieve the cable length 2373 * information. The cable length is determined by averaging the minimum and 2374 * maximum values to get the "average" cable length. The m88 PHY has four 2375 * possible cable length values, which are: 2376 * Register Value Cable Length 2377 * 0 < 50 meters 2378 * 1 50 - 80 meters 2379 * 2 80 - 110 meters 2380 * 3 110 - 140 meters 2381 * 4 > 140 meters 2382 **/ 2383s32 e1000_get_cable_length_m88(struct e1000_hw *hw) 2384{ 2385 struct e1000_phy_info *phy = &hw->phy; 2386 s32 ret_val; 2387 u16 phy_data, index; 2388 2389 DEBUGFUNC("e1000_get_cable_length_m88"); 2390 2391 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2392 if (ret_val) 2393 return ret_val; 2394 2395 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2396 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2397 2398 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2399 return -E1000_ERR_PHY; 2400 2401 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2402 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2403 2404 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2405 2406 return E1000_SUCCESS; 2407} 2408 2409s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw) 2410{ 2411 struct e1000_phy_info *phy = &hw->phy; 2412 s32 ret_val; 2413 u16 phy_data, phy_data2, is_cm; 2414 u16 index, default_page; 2415 2416 DEBUGFUNC("e1000_get_cable_length_m88_gen2"); 2417 2418 switch (hw->phy.id) { 2419 case I210_I_PHY_ID: 2420 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2421 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2422 (I347AT4_PCDL + phy->addr), 2423 &phy_data); 2424 if (ret_val) 2425 return ret_val; 2426 2427 /* Check if the unit of cable length is meters or cm */ 2428 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2429 I347AT4_PCDC, &phy_data2); 2430 if (ret_val) 2431 return ret_val; 2432 2433 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2434 2435 /* Populate the phy structure with cable length in meters */ 2436 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2437 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2438 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2439 break; 2440 case M88E1340M_E_PHY_ID: 2441 case I347AT4_E_PHY_ID: 2442 /* Remember the original page select and set it to 7 */ 2443 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2444 &default_page); 2445 if (ret_val) 2446 return ret_val; 2447 2448 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 2449 if (ret_val) 2450 return ret_val; 2451 2452 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2453 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 2454 &phy_data); 2455 if (ret_val) 2456 return ret_val; 2457 2458 /* Check if the unit of cable length is meters or cm */ 2459 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 2460 if (ret_val) 2461 return ret_val; 2462 2463 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2464 2465 /* Populate the phy structure with cable length in meters */ 2466 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2467 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2468 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2469 2470 /* Reset the page select to its original value */ 2471 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2472 default_page); 2473 if (ret_val) 2474 return ret_val; 2475 break; 2476 2477 case M88E1112_E_PHY_ID: 2478 /* Remember the original page select and set it to 5 */ 2479 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2480 &default_page); 2481 if (ret_val) 2482 return ret_val; 2483 2484 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 2485 if (ret_val) 2486 return ret_val; 2487 2488 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 2489 &phy_data); 2490 if (ret_val) 2491 return ret_val; 2492 2493 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2494 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2495 2496 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2497 return -E1000_ERR_PHY; 2498 2499 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2500 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2501 2502 phy->cable_length = (phy->min_cable_length + 2503 phy->max_cable_length) / 2; 2504 2505 /* Reset the page select to its original value */ 2506 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2507 default_page); 2508 if (ret_val) 2509 return ret_val; 2510 2511 break; 2512 default: 2513 return -E1000_ERR_PHY; 2514 } 2515 2516 return ret_val; 2517} 2518 2519/** 2520 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 2521 * @hw: pointer to the HW structure 2522 * 2523 * The automatic gain control (agc) normalizes the amplitude of the 2524 * received signal, adjusting for the attenuation produced by the 2525 * cable. By reading the AGC registers, which represent the 2526 * combination of coarse and fine gain value, the value can be put 2527 * into a lookup table to obtain the approximate cable length 2528 * for each channel. 2529 **/ 2530s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 2531{ 2532 struct e1000_phy_info *phy = &hw->phy; 2533 s32 ret_val; 2534 u16 phy_data, i, agc_value = 0; 2535 u16 cur_agc_index, max_agc_index = 0; 2536 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 2537 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 2538 IGP02E1000_PHY_AGC_A, 2539 IGP02E1000_PHY_AGC_B, 2540 IGP02E1000_PHY_AGC_C, 2541 IGP02E1000_PHY_AGC_D 2542 }; 2543 2544 DEBUGFUNC("e1000_get_cable_length_igp_2"); 2545 2546 /* Read the AGC registers for all channels */ 2547 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 2548 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 2549 if (ret_val) 2550 return ret_val; 2551 2552 /* Getting bits 15:9, which represent the combination of 2553 * coarse and fine gain values. The result is a number 2554 * that can be put into the lookup table to obtain the 2555 * approximate cable length. 2556 */ 2557 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 2558 IGP02E1000_AGC_LENGTH_MASK; 2559 2560 /* Array index bound check. */ 2561 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 2562 (cur_agc_index == 0)) 2563 return -E1000_ERR_PHY; 2564 2565 /* Remove min & max AGC values from calculation. */ 2566 if (e1000_igp_2_cable_length_table[min_agc_index] > 2567 e1000_igp_2_cable_length_table[cur_agc_index]) 2568 min_agc_index = cur_agc_index; 2569 if (e1000_igp_2_cable_length_table[max_agc_index] < 2570 e1000_igp_2_cable_length_table[cur_agc_index]) 2571 max_agc_index = cur_agc_index; 2572 2573 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 2574 } 2575 2576 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 2577 e1000_igp_2_cable_length_table[max_agc_index]); 2578 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 2579 2580 /* Calculate cable length with the error range of +/- 10 meters. */ 2581 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 2582 (agc_value - IGP02E1000_AGC_RANGE) : 0; 2583 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 2584 2585 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2586 2587 return E1000_SUCCESS; 2588} 2589 2590/** 2591 * e1000_get_phy_info_m88 - Retrieve PHY information 2592 * @hw: pointer to the HW structure 2593 * 2594 * Valid for only copper links. Read the PHY status register (sticky read) 2595 * to verify that link is up. Read the PHY special control register to 2596 * determine the polarity and 10base-T extended distance. Read the PHY 2597 * special status register to determine MDI/MDIx and current speed. If 2598 * speed is 1000, then determine cable length, local and remote receiver. 2599 **/ 2600s32 e1000_get_phy_info_m88(struct e1000_hw *hw) 2601{ 2602 struct e1000_phy_info *phy = &hw->phy; 2603 s32 ret_val; 2604 u16 phy_data; 2605 bool link; 2606 2607 DEBUGFUNC("e1000_get_phy_info_m88"); 2608 2609 if (phy->media_type != e1000_media_type_copper) { 2610 DEBUGOUT("Phy info is only valid for copper media\n"); 2611 return -E1000_ERR_CONFIG; 2612 } 2613 2614 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2615 if (ret_val) 2616 return ret_val; 2617 2618 if (!link) { 2619 DEBUGOUT("Phy info is only valid if link is up\n"); 2620 return -E1000_ERR_CONFIG; 2621 } 2622 2623 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2624 if (ret_val) 2625 return ret_val; 2626 2627 phy->polarity_correction = !!(phy_data & 2628 M88E1000_PSCR_POLARITY_REVERSAL); 2629 2630 ret_val = e1000_check_polarity_m88(hw); 2631 if (ret_val) 2632 return ret_val; 2633 2634 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2635 if (ret_val) 2636 return ret_val; 2637 2638 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); 2639 2640 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2641 ret_val = hw->phy.ops.get_cable_length(hw); 2642 if (ret_val) 2643 return ret_val; 2644 2645 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2646 if (ret_val) 2647 return ret_val; 2648 2649 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2650 ? e1000_1000t_rx_status_ok 2651 : e1000_1000t_rx_status_not_ok; 2652 2653 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2654 ? e1000_1000t_rx_status_ok 2655 : e1000_1000t_rx_status_not_ok; 2656 } else { 2657 /* Set values to "undefined" */ 2658 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2659 phy->local_rx = e1000_1000t_rx_status_undefined; 2660 phy->remote_rx = e1000_1000t_rx_status_undefined; 2661 } 2662 2663 return ret_val; 2664} 2665 2666/** 2667 * e1000_get_phy_info_igp - Retrieve igp PHY information 2668 * @hw: pointer to the HW structure 2669 * 2670 * Read PHY status to determine if link is up. If link is up, then 2671 * set/determine 10base-T extended distance and polarity correction. Read 2672 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2673 * determine on the cable length, local and remote receiver. 2674 **/ 2675s32 e1000_get_phy_info_igp(struct e1000_hw *hw) 2676{ 2677 struct e1000_phy_info *phy = &hw->phy; 2678 s32 ret_val; 2679 u16 data; 2680 bool link; 2681 2682 DEBUGFUNC("e1000_get_phy_info_igp"); 2683 2684 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2685 if (ret_val) 2686 return ret_val; 2687 2688 if (!link) { 2689 DEBUGOUT("Phy info is only valid if link is up\n"); 2690 return -E1000_ERR_CONFIG; 2691 } 2692 2693 phy->polarity_correction = TRUE; 2694 2695 ret_val = e1000_check_polarity_igp(hw); 2696 if (ret_val) 2697 return ret_val; 2698 2699 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2700 if (ret_val) 2701 return ret_val; 2702 2703 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); 2704 2705 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2706 IGP01E1000_PSSR_SPEED_1000MBPS) { 2707 ret_val = phy->ops.get_cable_length(hw); 2708 if (ret_val) 2709 return ret_val; 2710 2711 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2712 if (ret_val) 2713 return ret_val; 2714 2715 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2716 ? e1000_1000t_rx_status_ok 2717 : e1000_1000t_rx_status_not_ok; 2718 2719 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2720 ? e1000_1000t_rx_status_ok 2721 : e1000_1000t_rx_status_not_ok; 2722 } else { 2723 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2724 phy->local_rx = e1000_1000t_rx_status_undefined; 2725 phy->remote_rx = e1000_1000t_rx_status_undefined; 2726 } 2727 2728 return ret_val; 2729} 2730 2731/** 2732 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2733 * @hw: pointer to the HW structure 2734 * 2735 * Populates "phy" structure with various feature states. 2736 **/ 2737s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2738{ 2739 struct e1000_phy_info *phy = &hw->phy; 2740 s32 ret_val; 2741 u16 data; 2742 bool link; 2743 2744 DEBUGFUNC("e1000_get_phy_info_ife"); 2745 2746 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2747 if (ret_val) 2748 return ret_val; 2749 2750 if (!link) { 2751 DEBUGOUT("Phy info is only valid if link is up\n"); 2752 return -E1000_ERR_CONFIG; 2753 } 2754 2755 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2756 if (ret_val) 2757 return ret_val; 2758 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); 2759 2760 if (phy->polarity_correction) { 2761 ret_val = e1000_check_polarity_ife(hw); 2762 if (ret_val) 2763 return ret_val; 2764 } else { 2765 /* Polarity is forced */ 2766 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 2767 ? e1000_rev_polarity_reversed 2768 : e1000_rev_polarity_normal; 2769 } 2770 2771 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 2772 if (ret_val) 2773 return ret_val; 2774 2775 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); 2776 2777 /* The following parameters are undefined for 10/100 operation. */ 2778 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2779 phy->local_rx = e1000_1000t_rx_status_undefined; 2780 phy->remote_rx = e1000_1000t_rx_status_undefined; 2781 2782 return E1000_SUCCESS; 2783} 2784 2785/** 2786 * e1000_phy_sw_reset_generic - PHY software reset 2787 * @hw: pointer to the HW structure 2788 * 2789 * Does a software reset of the PHY by reading the PHY control register and 2790 * setting/write the control register reset bit to the PHY. 2791 **/ 2792s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2793{ 2794 s32 ret_val; 2795 u16 phy_ctrl; 2796 2797 DEBUGFUNC("e1000_phy_sw_reset_generic"); 2798 2799 if (!hw->phy.ops.read_reg) 2800 return E1000_SUCCESS; 2801 2802 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2803 if (ret_val) 2804 return ret_val; 2805 2806 phy_ctrl |= MII_CR_RESET; 2807 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2808 if (ret_val) 2809 return ret_val; 2810 2811 usec_delay(1); 2812 2813 return ret_val; 2814} 2815 2816/** 2817 * e1000_phy_hw_reset_generic - PHY hardware reset 2818 * @hw: pointer to the HW structure 2819 * 2820 * Verify the reset block is not blocking us from resetting. Acquire 2821 * semaphore (if necessary) and read/set/write the device control reset 2822 * bit in the PHY. Wait the appropriate delay time for the device to 2823 * reset and release the semaphore (if necessary). 2824 **/ 2825s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2826{ 2827 struct e1000_phy_info *phy = &hw->phy; 2828 s32 ret_val; 2829 u32 ctrl; 2830 2831 DEBUGFUNC("e1000_phy_hw_reset_generic"); 2832 2833 if (phy->ops.check_reset_block) { 2834 ret_val = phy->ops.check_reset_block(hw); 2835 if (ret_val) 2836 return E1000_SUCCESS; 2837 } 2838 2839 ret_val = phy->ops.acquire(hw); 2840 if (ret_val) 2841 return ret_val; 2842 2843 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2844 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2845 E1000_WRITE_FLUSH(hw); 2846 2847 usec_delay(phy->reset_delay_us); 2848 2849 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2850 E1000_WRITE_FLUSH(hw); 2851 2852 usec_delay(150); 2853 2854 phy->ops.release(hw); 2855 2856 return phy->ops.get_cfg_done(hw); 2857} 2858 2859/** 2860 * e1000_get_cfg_done_generic - Generic configuration done 2861 * @hw: pointer to the HW structure 2862 * 2863 * Generic function to wait 10 milli-seconds for configuration to complete 2864 * and return success. 2865 **/ 2866s32 e1000_get_cfg_done_generic(struct e1000_hw *hw) 2867{ 2868 DEBUGFUNC("e1000_get_cfg_done_generic"); 2869 2870 msec_delay_irq(10); 2871 2872 return E1000_SUCCESS; 2873} 2874 2875/** 2876 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2877 * @hw: pointer to the HW structure 2878 * 2879 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2880 **/ 2881s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2882{ 2883 DEBUGOUT("Running IGP 3 PHY init script\n"); 2884 2885 /* PHY init IGP 3 */ 2886 /* Enable rise/fall, 10-mode work in class-A */ 2887 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2888 /* Remove all caps from Replica path filter */ 2889 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2890 /* Bias trimming for ADC, AFE and Driver (Default) */ 2891 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2892 /* Increase Hybrid poly bias */ 2893 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2894 /* Add 4% to Tx amplitude in Gig mode */ 2895 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2896 /* Disable trimming (TTT) */ 2897 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2898 /* Poly DC correction to 94.6% + 2% for all channels */ 2899 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2900 /* ABS DC correction to 95.9% */ 2901 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2902 /* BG temp curve trim */ 2903 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2904 /* Increasing ADC OPAMP stage 1 currents to max */ 2905 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2906 /* Force 1000 ( required for enabling PHY regs configuration) */ 2907 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2908 /* Set upd_freq to 6 */ 2909 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2910 /* Disable NPDFE */ 2911 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2912 /* Disable adaptive fixed FFE (Default) */ 2913 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2914 /* Enable FFE hysteresis */ 2915 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2916 /* Fixed FFE for short cable lengths */ 2917 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2918 /* Fixed FFE for medium cable lengths */ 2919 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2920 /* Fixed FFE for long cable lengths */ 2921 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2922 /* Enable Adaptive Clip Threshold */ 2923 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2924 /* AHT reset limit to 1 */ 2925 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2926 /* Set AHT master delay to 127 msec */ 2927 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2928 /* Set scan bits for AHT */ 2929 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2930 /* Set AHT Preset bits */ 2931 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2932 /* Change integ_factor of channel A to 3 */ 2933 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2934 /* Change prop_factor of channels BCD to 8 */ 2935 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2936 /* Change cg_icount + enable integbp for channels BCD */ 2937 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2938 /* Change cg_icount + enable integbp + change prop_factor_master 2939 * to 8 for channel A 2940 */ 2941 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2942 /* Disable AHT in Slave mode on channel A */ 2943 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2944 /* Enable LPLU and disable AN to 1000 in non-D0a states, 2945 * Enable SPD+B2B 2946 */ 2947 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2948 /* Enable restart AN on an1000_dis change */ 2949 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2950 /* Enable wh_fifo read clock in 10/100 modes */ 2951 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2952 /* Restart AN, Speed selection is 1000 */ 2953 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2954 2955 return E1000_SUCCESS; 2956} 2957 2958/** 2959 * e1000_get_phy_type_from_id - Get PHY type from id 2960 * @phy_id: phy_id read from the phy 2961 * 2962 * Returns the phy type from the id. 2963 **/ 2964enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 2965{ 2966 enum e1000_phy_type phy_type = e1000_phy_unknown; 2967 2968 switch (phy_id) { 2969 case M88E1000_I_PHY_ID: 2970 case M88E1000_E_PHY_ID: 2971 case M88E1111_I_PHY_ID: 2972 case M88E1011_I_PHY_ID: 2973 case I347AT4_E_PHY_ID: 2974 case M88E1112_E_PHY_ID: 2975 case M88E1340M_E_PHY_ID: 2976 phy_type = e1000_phy_m88; 2977 break; 2978 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2979 phy_type = e1000_phy_igp_2; 2980 break; 2981 case GG82563_E_PHY_ID: 2982 phy_type = e1000_phy_gg82563; 2983 break; 2984 case IGP03E1000_E_PHY_ID: 2985 phy_type = e1000_phy_igp_3; 2986 break; 2987 case IFE_E_PHY_ID: 2988 case IFE_PLUS_E_PHY_ID: 2989 case IFE_C_E_PHY_ID: 2990 phy_type = e1000_phy_ife; 2991 break; 2992 case BME1000_E_PHY_ID: 2993 case BME1000_E_PHY_ID_R2: 2994 phy_type = e1000_phy_bm; 2995 break; 2996 case I82578_E_PHY_ID: 2997 phy_type = e1000_phy_82578; 2998 break; 2999 case I82577_E_PHY_ID: 3000 phy_type = e1000_phy_82577; 3001 break; 3002 case I82579_E_PHY_ID: 3003 phy_type = e1000_phy_82579; 3004 break; 3005 case I217_E_PHY_ID: 3006 phy_type = e1000_phy_i217; 3007 break; 3008 case I82580_I_PHY_ID: 3009 phy_type = e1000_phy_82580; 3010 break; 3011 case I210_I_PHY_ID: 3012 phy_type = e1000_phy_i210; 3013 break; 3014 default: 3015 phy_type = e1000_phy_unknown; 3016 break; 3017 } 3018 return phy_type; 3019} 3020 3021/** 3022 * e1000_determine_phy_address - Determines PHY address. 3023 * @hw: pointer to the HW structure 3024 * 3025 * This uses a trial and error method to loop through possible PHY 3026 * addresses. It tests each by reading the PHY ID registers and 3027 * checking for a match. 3028 **/ 3029s32 e1000_determine_phy_address(struct e1000_hw *hw) 3030{ 3031 u32 phy_addr = 0; 3032 u32 i; 3033 enum e1000_phy_type phy_type = e1000_phy_unknown; 3034 3035 hw->phy.id = phy_type; 3036 3037 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 3038 hw->phy.addr = phy_addr; 3039 i = 0; 3040 3041 do { 3042 e1000_get_phy_id(hw); 3043 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 3044 3045 /* If phy_type is valid, break - we found our 3046 * PHY address 3047 */ 3048 if (phy_type != e1000_phy_unknown) 3049 return E1000_SUCCESS; 3050 3051 msec_delay(1); 3052 i++; 3053 } while (i < 10); 3054 } 3055 3056 return -E1000_ERR_PHY_TYPE; 3057} 3058 3059/** 3060 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 3061 * @page: page to access 3062 * 3063 * Returns the phy address for the page requested. 3064 **/ 3065static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 3066{ 3067 u32 phy_addr = 2; 3068 3069 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 3070 phy_addr = 1; 3071 3072 return phy_addr; 3073} 3074 3075/** 3076 * e1000_write_phy_reg_bm - Write BM PHY register 3077 * @hw: pointer to the HW structure 3078 * @offset: register offset to write to 3079 * @data: data to write at register offset 3080 * 3081 * Acquires semaphore, if necessary, then writes the data to PHY register 3082 * at the offset. Release any acquired semaphores before exiting. 3083 **/ 3084s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 3085{ 3086 s32 ret_val; 3087 u32 page = offset >> IGP_PAGE_SHIFT; 3088 3089 DEBUGFUNC("e1000_write_phy_reg_bm"); 3090 3091 ret_val = hw->phy.ops.acquire(hw); 3092 if (ret_val) 3093 return ret_val; 3094 3095 /* Page 800 works differently than the rest so it has its own func */ 3096 if (page == BM_WUC_PAGE) { 3097 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3098 FALSE, FALSE); 3099 goto release; 3100 } 3101 3102 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3103 3104 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3105 u32 page_shift, page_select; 3106 3107 /* Page select is register 31 for phy address 1 and 22 for 3108 * phy address 2 and 3. Page select is shifted only for 3109 * phy address 1. 3110 */ 3111 if (hw->phy.addr == 1) { 3112 page_shift = IGP_PAGE_SHIFT; 3113 page_select = IGP01E1000_PHY_PAGE_SELECT; 3114 } else { 3115 page_shift = 0; 3116 page_select = BM_PHY_PAGE_SELECT; 3117 } 3118 3119 /* Page is shifted left, PHY expects (page x 32) */ 3120 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3121 (page << page_shift)); 3122 if (ret_val) 3123 goto release; 3124 } 3125 3126 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3127 data); 3128 3129release: 3130 hw->phy.ops.release(hw); 3131 return ret_val; 3132} 3133 3134/** 3135 * e1000_read_phy_reg_bm - Read BM PHY register 3136 * @hw: pointer to the HW structure 3137 * @offset: register offset to be read 3138 * @data: pointer to the read data 3139 * 3140 * Acquires semaphore, if necessary, then reads the PHY register at offset 3141 * and storing the retrieved information in data. Release any acquired 3142 * semaphores before exiting. 3143 **/ 3144s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 3145{ 3146 s32 ret_val; 3147 u32 page = offset >> IGP_PAGE_SHIFT; 3148 3149 DEBUGFUNC("e1000_read_phy_reg_bm"); 3150 3151 ret_val = hw->phy.ops.acquire(hw); 3152 if (ret_val) 3153 return ret_val; 3154 3155 /* Page 800 works differently than the rest so it has its own func */ 3156 if (page == BM_WUC_PAGE) { 3157 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3158 TRUE, FALSE); 3159 goto release; 3160 } 3161 3162 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3163 3164 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3165 u32 page_shift, page_select; 3166 3167 /* Page select is register 31 for phy address 1 and 22 for 3168 * phy address 2 and 3. Page select is shifted only for 3169 * phy address 1. 3170 */ 3171 if (hw->phy.addr == 1) { 3172 page_shift = IGP_PAGE_SHIFT; 3173 page_select = IGP01E1000_PHY_PAGE_SELECT; 3174 } else { 3175 page_shift = 0; 3176 page_select = BM_PHY_PAGE_SELECT; 3177 } 3178 3179 /* Page is shifted left, PHY expects (page x 32) */ 3180 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3181 (page << page_shift)); 3182 if (ret_val) 3183 goto release; 3184 } 3185 3186 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3187 data); 3188release: 3189 hw->phy.ops.release(hw); 3190 return ret_val; 3191} 3192 3193/** 3194 * e1000_read_phy_reg_bm2 - Read BM PHY register 3195 * @hw: pointer to the HW structure 3196 * @offset: register offset to be read 3197 * @data: pointer to the read data 3198 * 3199 * Acquires semaphore, if necessary, then reads the PHY register at offset 3200 * and storing the retrieved information in data. Release any acquired 3201 * semaphores before exiting. 3202 **/ 3203s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 3204{ 3205 s32 ret_val; 3206 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3207 3208 DEBUGFUNC("e1000_read_phy_reg_bm2"); 3209 3210 ret_val = hw->phy.ops.acquire(hw); 3211 if (ret_val) 3212 return ret_val; 3213 3214 /* Page 800 works differently than the rest so it has its own func */ 3215 if (page == BM_WUC_PAGE) { 3216 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3217 TRUE, FALSE); 3218 goto release; 3219 } 3220 3221 hw->phy.addr = 1; 3222 3223 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3224 /* Page is shifted left, PHY expects (page x 32) */ 3225 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3226 page); 3227 3228 if (ret_val) 3229 goto release; 3230 } 3231 3232 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3233 data); 3234release: 3235 hw->phy.ops.release(hw); 3236 return ret_val; 3237} 3238 3239/** 3240 * e1000_write_phy_reg_bm2 - Write BM PHY register 3241 * @hw: pointer to the HW structure 3242 * @offset: register offset to write to 3243 * @data: data to write at register offset 3244 * 3245 * Acquires semaphore, if necessary, then writes the data to PHY register 3246 * at the offset. Release any acquired semaphores before exiting. 3247 **/ 3248s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 3249{ 3250 s32 ret_val; 3251 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3252 3253 DEBUGFUNC("e1000_write_phy_reg_bm2"); 3254 3255 ret_val = hw->phy.ops.acquire(hw); 3256 if (ret_val) 3257 return ret_val; 3258 3259 /* Page 800 works differently than the rest so it has its own func */ 3260 if (page == BM_WUC_PAGE) { 3261 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3262 FALSE, FALSE); 3263 goto release; 3264 } 3265 3266 hw->phy.addr = 1; 3267 3268 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3269 /* Page is shifted left, PHY expects (page x 32) */ 3270 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3271 page); 3272 3273 if (ret_val) 3274 goto release; 3275 } 3276 3277 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3278 data); 3279 3280release: 3281 hw->phy.ops.release(hw); 3282 return ret_val; 3283} 3284 3285/** 3286 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers 3287 * @hw: pointer to the HW structure 3288 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG 3289 * 3290 * Assumes semaphore already acquired and phy_reg points to a valid memory 3291 * address to store contents of the BM_WUC_ENABLE_REG register. 3292 **/ 3293s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3294{ 3295 s32 ret_val; 3296 u16 temp; 3297 3298 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm"); 3299 3300 if (!phy_reg) 3301 return -E1000_ERR_PARAM; 3302 3303 /* All page select, port ctrl and wakeup registers use phy address 1 */ 3304 hw->phy.addr = 1; 3305 3306 /* Select Port Control Registers page */ 3307 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3308 if (ret_val) { 3309 DEBUGOUT("Could not set Port Control page\n"); 3310 return ret_val; 3311 } 3312 3313 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 3314 if (ret_val) { 3315 DEBUGOUT2("Could not read PHY register %d.%d\n", 3316 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3317 return ret_val; 3318 } 3319 3320 /* Enable both PHY wakeup mode and Wakeup register page writes. 3321 * Prevent a power state change by disabling ME and Host PHY wakeup. 3322 */ 3323 temp = *phy_reg; 3324 temp |= BM_WUC_ENABLE_BIT; 3325 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); 3326 3327 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); 3328 if (ret_val) { 3329 DEBUGOUT2("Could not write PHY register %d.%d\n", 3330 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3331 return ret_val; 3332 } 3333 3334 /* Select Host Wakeup Registers page - caller now able to write 3335 * registers on the Wakeup registers page 3336 */ 3337 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 3338} 3339 3340/** 3341 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs 3342 * @hw: pointer to the HW structure 3343 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG 3344 * 3345 * Restore BM_WUC_ENABLE_REG to its original value. 3346 * 3347 * Assumes semaphore already acquired and *phy_reg is the contents of the 3348 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by 3349 * caller. 3350 **/ 3351s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3352{ 3353 s32 ret_val; 3354 3355 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm"); 3356 3357 if (!phy_reg) 3358 return -E1000_ERR_PARAM; 3359 3360 /* Select Port Control Registers page */ 3361 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3362 if (ret_val) { 3363 DEBUGOUT("Could not set Port Control page\n"); 3364 return ret_val; 3365 } 3366 3367 /* Restore 769.17 to its original value */ 3368 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); 3369 if (ret_val) 3370 DEBUGOUT2("Could not restore PHY register %d.%d\n", 3371 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3372 3373 return ret_val; 3374} 3375 3376/** 3377 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register 3378 * @hw: pointer to the HW structure 3379 * @offset: register offset to be read or written 3380 * @data: pointer to the data to read or write 3381 * @read: determines if operation is read or write 3382 * @page_set: BM_WUC_PAGE already set and access enabled 3383 * 3384 * Read the PHY register at offset and store the retrieved information in 3385 * data, or write data to PHY register at offset. Note the procedure to 3386 * access the PHY wakeup registers is different than reading the other PHY 3387 * registers. It works as such: 3388 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 3389 * 2) Set page to 800 for host (801 if we were manageability) 3390 * 3) Write the address using the address opcode (0x11) 3391 * 4) Read or write the data using the data opcode (0x12) 3392 * 5) Restore 769.17.2 to its original value 3393 * 3394 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and 3395 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). 3396 * 3397 * Assumes semaphore is already acquired. When page_set==TRUE, assumes 3398 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack 3399 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). 3400 **/ 3401static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 3402 u16 *data, bool read, bool page_set) 3403{ 3404 s32 ret_val; 3405 u16 reg = BM_PHY_REG_NUM(offset); 3406 u16 page = BM_PHY_REG_PAGE(offset); 3407 u16 phy_reg = 0; 3408 3409 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); 3410 3411 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ 3412 if ((hw->mac.type == e1000_pchlan) && 3413 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 3414 DEBUGOUT1("Attempting to access page %d while gig enabled.\n", 3415 page); 3416 3417 if (!page_set) { 3418 /* Enable access to PHY wakeup registers */ 3419 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3420 if (ret_val) { 3421 DEBUGOUT("Could not enable PHY wakeup reg access\n"); 3422 return ret_val; 3423 } 3424 } 3425 3426 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg); 3427 3428 /* Write the Wakeup register page offset value using opcode 0x11 */ 3429 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 3430 if (ret_val) { 3431 DEBUGOUT1("Could not write address opcode to page %d\n", page); 3432 return ret_val; 3433 } 3434 3435 if (read) { 3436 /* Read the Wakeup register page value using opcode 0x12 */ 3437 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3438 data); 3439 } else { 3440 /* Write the Wakeup register page value using opcode 0x12 */ 3441 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3442 *data); 3443 } 3444 3445 if (ret_val) { 3446 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg); 3447 return ret_val; 3448 } 3449 3450 if (!page_set) 3451 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3452 3453 return ret_val; 3454} 3455 3456/** 3457 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 3458 * @hw: pointer to the HW structure 3459 * 3460 * In the case of a PHY power down to save power, or to turn off link during a 3461 * driver unload, or wake on lan is not enabled, restore the link to previous 3462 * settings. 3463 **/ 3464void e1000_power_up_phy_copper(struct e1000_hw *hw) 3465{ 3466 u16 mii_reg = 0; 3467 u16 power_reg = 0; 3468 3469 /* The PHY will retain its settings across a power down/up cycle */ 3470 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3471 mii_reg &= ~MII_CR_POWER_DOWN; 3472 if (hw->phy.type == e1000_phy_i210) { 3473 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 3474 power_reg &= ~GS40G_CS_POWER_DOWN; 3475 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 3476 } 3477 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3478} 3479 3480/** 3481 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 3482 * @hw: pointer to the HW structure 3483 * 3484 * In the case of a PHY power down to save power, or to turn off link during a 3485 * driver unload, or wake on lan is not enabled, restore the link to previous 3486 * settings. 3487 **/ 3488void e1000_power_down_phy_copper(struct e1000_hw *hw) 3489{ 3490 u16 mii_reg = 0; 3491 u16 power_reg = 0; 3492 3493 /* The PHY will retain its settings across a power down/up cycle */ 3494 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3495 mii_reg |= MII_CR_POWER_DOWN; 3496 /* i210 Phy requires an additional bit for power up/down */ 3497 if (hw->phy.type == e1000_phy_i210) { 3498 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 3499 power_reg |= GS40G_CS_POWER_DOWN; 3500 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 3501 } 3502 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3503 msec_delay(1); 3504} 3505 3506/** 3507 * __e1000_read_phy_reg_hv - Read HV PHY register 3508 * @hw: pointer to the HW structure 3509 * @offset: register offset to be read 3510 * @data: pointer to the read data 3511 * @locked: semaphore has already been acquired or not 3512 * 3513 * Acquires semaphore, if necessary, then reads the PHY register at offset 3514 * and stores the retrieved information in data. Release any acquired 3515 * semaphore before exiting. 3516 **/ 3517static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 3518 bool locked, bool page_set) 3519{ 3520 s32 ret_val; 3521 u16 page = BM_PHY_REG_PAGE(offset); 3522 u16 reg = BM_PHY_REG_NUM(offset); 3523 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3524 3525 DEBUGFUNC("__e1000_read_phy_reg_hv"); 3526 3527 if (!locked) { 3528 ret_val = hw->phy.ops.acquire(hw); 3529 if (ret_val) 3530 return ret_val; 3531 } 3532 3533 /* Page 800 works differently than the rest so it has its own func */ 3534 if (page == BM_WUC_PAGE) { 3535 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3536 TRUE, page_set); 3537 goto out; 3538 } 3539 3540 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3541 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3542 data, TRUE); 3543 goto out; 3544 } 3545 3546 if (!page_set) { 3547 if (page == HV_INTC_FC_PAGE_START) 3548 page = 0; 3549 3550 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3551 /* Page is shifted left, PHY expects (page x 32) */ 3552 ret_val = e1000_set_page_igp(hw, 3553 (page << IGP_PAGE_SHIFT)); 3554 3555 hw->phy.addr = phy_addr; 3556 3557 if (ret_val) 3558 goto out; 3559 } 3560 } 3561 3562 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3563 page << IGP_PAGE_SHIFT, reg); 3564 3565 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3566 data); 3567out: 3568 if (!locked) 3569 hw->phy.ops.release(hw); 3570 3571 return ret_val; 3572} 3573 3574/** 3575 * e1000_read_phy_reg_hv - Read HV PHY register 3576 * @hw: pointer to the HW structure 3577 * @offset: register offset to be read 3578 * @data: pointer to the read data 3579 * 3580 * Acquires semaphore then reads the PHY register at offset and stores 3581 * the retrieved information in data. Release the acquired semaphore 3582 * before exiting. 3583 **/ 3584s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3585{ 3586 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, FALSE); 3587} 3588 3589/** 3590 * e1000_read_phy_reg_hv_locked - Read HV PHY register 3591 * @hw: pointer to the HW structure 3592 * @offset: register offset to be read 3593 * @data: pointer to the read data 3594 * 3595 * Reads the PHY register at offset and stores the retrieved information 3596 * in data. Assumes semaphore already acquired. 3597 **/ 3598s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 3599{ 3600 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3601} 3602 3603/** 3604 * e1000_read_phy_reg_page_hv - Read HV PHY register 3605 * @hw: pointer to the HW structure 3606 * @offset: register offset to write to 3607 * @data: data to write at register offset 3608 * 3609 * Reads the PHY register at offset and stores the retrieved information 3610 * in data. Assumes semaphore already acquired and page already set. 3611 **/ 3612s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3613{ 3614 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, true); 3615} 3616 3617/** 3618 * __e1000_write_phy_reg_hv - Write HV PHY register 3619 * @hw: pointer to the HW structure 3620 * @offset: register offset to write to 3621 * @data: data to write at register offset 3622 * @locked: semaphore has already been acquired or not 3623 * 3624 * Acquires semaphore, if necessary, then writes the data to PHY register 3625 * at the offset. Release any acquired semaphores before exiting. 3626 **/ 3627static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 3628 bool locked, bool page_set) 3629{ 3630 s32 ret_val; 3631 u16 page = BM_PHY_REG_PAGE(offset); 3632 u16 reg = BM_PHY_REG_NUM(offset); 3633 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3634 3635 DEBUGFUNC("__e1000_write_phy_reg_hv"); 3636 3637 if (!locked) { 3638 ret_val = hw->phy.ops.acquire(hw); 3639 if (ret_val) 3640 return ret_val; 3641 } 3642 3643 /* Page 800 works differently than the rest so it has its own func */ 3644 if (page == BM_WUC_PAGE) { 3645 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3646 FALSE, page_set); 3647 goto out; 3648 } 3649 3650 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3651 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3652 &data, FALSE); 3653 goto out; 3654 } 3655 3656 if (!page_set) { 3657 if (page == HV_INTC_FC_PAGE_START) 3658 page = 0; 3659 3660 /* Workaround MDIO accesses being disabled after entering IEEE 3661 * Power Down (when bit 11 of the PHY Control register is set) 3662 */ 3663 if ((hw->phy.type == e1000_phy_82578) && 3664 (hw->phy.revision >= 1) && 3665 (hw->phy.addr == 2) && 3666 !(MAX_PHY_REG_ADDRESS & reg) && 3667 (data & (1 << 11))) { 3668 u16 data2 = 0x7EFF; 3669 ret_val = e1000_access_phy_debug_regs_hv(hw, 3670 (1 << 6) | 0x3, 3671 &data2, FALSE); 3672 if (ret_val) 3673 goto out; 3674 } 3675 3676 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3677 /* Page is shifted left, PHY expects (page x 32) */ 3678 ret_val = e1000_set_page_igp(hw, 3679 (page << IGP_PAGE_SHIFT)); 3680 3681 hw->phy.addr = phy_addr; 3682 3683 if (ret_val) 3684 goto out; 3685 } 3686 } 3687 3688 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3689 page << IGP_PAGE_SHIFT, reg); 3690 3691 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3692 data); 3693 3694out: 3695 if (!locked) 3696 hw->phy.ops.release(hw); 3697 3698 return ret_val; 3699} 3700 3701/** 3702 * e1000_write_phy_reg_hv - Write HV PHY register 3703 * @hw: pointer to the HW structure 3704 * @offset: register offset to write to 3705 * @data: data to write at register offset 3706 * 3707 * Acquires semaphore then writes the data to PHY register at the offset. 3708 * Release the acquired semaphores before exiting. 3709 **/ 3710s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3711{ 3712 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, FALSE); 3713} 3714 3715/** 3716 * e1000_write_phy_reg_hv_locked - Write HV PHY register 3717 * @hw: pointer to the HW structure 3718 * @offset: register offset to write to 3719 * @data: data to write at register offset 3720 * 3721 * Writes the data to PHY register at the offset. Assumes semaphore 3722 * already acquired. 3723 **/ 3724s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3725{ 3726 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3727} 3728 3729/** 3730 * e1000_write_phy_reg_page_hv - Write HV PHY register 3731 * @hw: pointer to the HW structure 3732 * @offset: register offset to write to 3733 * @data: data to write at register offset 3734 * 3735 * Writes the data to PHY register at the offset. Assumes semaphore 3736 * already acquired and page already set. 3737 **/ 3738s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) 3739{ 3740 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, true); 3741} 3742 3743/** 3744 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page 3745 * @page: page to be accessed 3746 **/ 3747static u32 e1000_get_phy_addr_for_hv_page(u32 page) 3748{ 3749 u32 phy_addr = 2; 3750 3751 if (page >= HV_INTC_FC_PAGE_START) 3752 phy_addr = 1; 3753 3754 return phy_addr; 3755} 3756 3757/** 3758 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3759 * @hw: pointer to the HW structure 3760 * @offset: register offset to be read or written 3761 * @data: pointer to the data to be read or written 3762 * @read: determines if operation is read or write 3763 * 3764 * Reads the PHY register at offset and stores the retreived information 3765 * in data. Assumes semaphore already acquired. Note that the procedure 3766 * to access these regs uses the address port and data port to read/write. 3767 * These accesses done with PHY address 2 and without using pages. 3768 **/ 3769static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3770 u16 *data, bool read) 3771{ 3772 s32 ret_val; 3773 u32 addr_reg; 3774 u32 data_reg; 3775 3776 DEBUGFUNC("e1000_access_phy_debug_regs_hv"); 3777 3778 /* This takes care of the difference with desktop vs mobile phy */ 3779 addr_reg = (hw->phy.type == e1000_phy_82578) ? 3780 I82578_ADDR_REG : I82577_ADDR_REG; 3781 data_reg = addr_reg + 1; 3782 3783 /* All operations in this function are phy address 2 */ 3784 hw->phy.addr = 2; 3785 3786 /* masking with 0x3F to remove the page from offset */ 3787 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3788 if (ret_val) { 3789 DEBUGOUT("Could not write the Address Offset port register\n"); 3790 return ret_val; 3791 } 3792 3793 /* Read or write the data value next */ 3794 if (read) 3795 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data); 3796 else 3797 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data); 3798 3799 if (ret_val) 3800 DEBUGOUT("Could not access the Data port register\n"); 3801 3802 return ret_val; 3803} 3804 3805/** 3806 * e1000_link_stall_workaround_hv - Si workaround 3807 * @hw: pointer to the HW structure 3808 * 3809 * This function works around a Si bug where the link partner can get 3810 * a link up indication before the PHY does. If small packets are sent 3811 * by the link partner they can be placed in the packet buffer without 3812 * being properly accounted for by the PHY and will stall preventing 3813 * further packets from being received. The workaround is to clear the 3814 * packet buffer after the PHY detects link up. 3815 **/ 3816s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3817{ 3818 s32 ret_val = E1000_SUCCESS; 3819 u16 data; 3820 3821 DEBUGFUNC("e1000_link_stall_workaround_hv"); 3822 3823 if (hw->phy.type != e1000_phy_82578) 3824 return E1000_SUCCESS; 3825 3826 /* Do not apply workaround if in PHY loopback bit 14 set */ 3827 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); 3828 if (data & PHY_CONTROL_LB) 3829 return E1000_SUCCESS; 3830 3831 /* check if link is up and at 1Gbps */ 3832 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); 3833 if (ret_val) 3834 return ret_val; 3835 3836 data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3837 BM_CS_STATUS_SPEED_MASK; 3838 3839 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3840 BM_CS_STATUS_SPEED_1000)) 3841 return E1000_SUCCESS; 3842 3843 msec_delay(200); 3844 3845 /* flush the packets in the fifo buffer */ 3846 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3847 (HV_MUX_DATA_CTRL_GEN_TO_MAC | 3848 HV_MUX_DATA_CTRL_FORCE_SPEED)); 3849 if (ret_val) 3850 return ret_val; 3851 3852 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3853 HV_MUX_DATA_CTRL_GEN_TO_MAC); 3854} 3855 3856/** 3857 * e1000_check_polarity_82577 - Checks the polarity. 3858 * @hw: pointer to the HW structure 3859 * 3860 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3861 * 3862 * Polarity is determined based on the PHY specific status register. 3863 **/ 3864s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3865{ 3866 struct e1000_phy_info *phy = &hw->phy; 3867 s32 ret_val; 3868 u16 data; 3869 3870 DEBUGFUNC("e1000_check_polarity_82577"); 3871 3872 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3873 3874 if (!ret_val) 3875 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 3876 ? e1000_rev_polarity_reversed 3877 : e1000_rev_polarity_normal; 3878 3879 return ret_val; 3880} 3881 3882/** 3883 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3884 * @hw: pointer to the HW structure 3885 * 3886 * Calls the PHY setup function to force speed and duplex. 3887 **/ 3888s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3889{ 3890 struct e1000_phy_info *phy = &hw->phy; 3891 s32 ret_val; 3892 u16 phy_data; 3893 bool link; 3894 3895 DEBUGFUNC("e1000_phy_force_speed_duplex_82577"); 3896 3897 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 3898 if (ret_val) 3899 return ret_val; 3900 3901 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 3902 3903 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 3904 if (ret_val) 3905 return ret_val; 3906 3907 usec_delay(1); 3908 3909 if (phy->autoneg_wait_to_complete) { 3910 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n"); 3911 3912 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3913 100000, &link); 3914 if (ret_val) 3915 return ret_val; 3916 3917 if (!link) 3918 DEBUGOUT("Link taking longer than expected.\n"); 3919 3920 /* Try once more */ 3921 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3922 100000, &link); 3923 } 3924 3925 return ret_val; 3926} 3927 3928/** 3929 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3930 * @hw: pointer to the HW structure 3931 * 3932 * Read PHY status to determine if link is up. If link is up, then 3933 * set/determine 10base-T extended distance and polarity correction. Read 3934 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3935 * determine on the cable length, local and remote receiver. 3936 **/ 3937s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3938{ 3939 struct e1000_phy_info *phy = &hw->phy; 3940 s32 ret_val; 3941 u16 data; 3942 bool link; 3943 3944 DEBUGFUNC("e1000_get_phy_info_82577"); 3945 3946 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3947 if (ret_val) 3948 return ret_val; 3949 3950 if (!link) { 3951 DEBUGOUT("Phy info is only valid if link is up\n"); 3952 return -E1000_ERR_CONFIG; 3953 } 3954 3955 phy->polarity_correction = TRUE; 3956 3957 ret_val = e1000_check_polarity_82577(hw); 3958 if (ret_val) 3959 return ret_val; 3960 3961 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3962 if (ret_val) 3963 return ret_val; 3964 3965 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); 3966 3967 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3968 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3969 ret_val = hw->phy.ops.get_cable_length(hw); 3970 if (ret_val) 3971 return ret_val; 3972 3973 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 3974 if (ret_val) 3975 return ret_val; 3976 3977 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 3978 ? e1000_1000t_rx_status_ok 3979 : e1000_1000t_rx_status_not_ok; 3980 3981 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 3982 ? e1000_1000t_rx_status_ok 3983 : e1000_1000t_rx_status_not_ok; 3984 } else { 3985 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 3986 phy->local_rx = e1000_1000t_rx_status_undefined; 3987 phy->remote_rx = e1000_1000t_rx_status_undefined; 3988 } 3989 3990 return E1000_SUCCESS; 3991} 3992 3993/** 3994 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 3995 * @hw: pointer to the HW structure 3996 * 3997 * Reads the diagnostic status register and verifies result is valid before 3998 * placing it in the phy_cable_length field. 3999 **/ 4000s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 4001{ 4002 struct e1000_phy_info *phy = &hw->phy; 4003 s32 ret_val; 4004 u16 phy_data, length; 4005 4006 DEBUGFUNC("e1000_get_cable_length_82577"); 4007 4008 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 4009 if (ret_val) 4010 return ret_val; 4011 4012 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 4013 I82577_DSTATUS_CABLE_LENGTH_SHIFT; 4014 4015 if (length == E1000_CABLE_LENGTH_UNDEFINED) 4016 return -E1000_ERR_PHY; 4017 4018 phy->cable_length = length; 4019 4020 return E1000_SUCCESS; 4021} 4022 4023/** 4024 * e1000_write_phy_reg_gs40g - Write GS40G PHY register 4025 * @hw: pointer to the HW structure 4026 * @offset: register offset to write to 4027 * @data: data to write at register offset 4028 * 4029 * Acquires semaphore, if necessary, then writes the data to PHY register 4030 * at the offset. Release any acquired semaphores before exiting. 4031 **/ 4032s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) 4033{ 4034 s32 ret_val; 4035 u16 page = offset >> GS40G_PAGE_SHIFT; 4036 4037 DEBUGFUNC("e1000_write_phy_reg_gs40g"); 4038 4039 offset = offset & GS40G_OFFSET_MASK; 4040 ret_val = hw->phy.ops.acquire(hw); 4041 if (ret_val) 4042 return ret_val; 4043 4044 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4045 if (ret_val) 4046 goto release; 4047 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 4048 4049release: 4050 hw->phy.ops.release(hw); 4051 return ret_val; 4052} 4053 4054/** 4055 * e1000_read_phy_reg_gs40g - Read GS40G PHY register 4056 * @hw: pointer to the HW structure 4057 * @offset: lower half is register offset to read to 4058 * upper half is page to use. 4059 * @data: data to read at register offset 4060 * 4061 * Acquires semaphore, if necessary, then reads the data in the PHY register 4062 * at the offset. Release any acquired semaphores before exiting. 4063 **/ 4064s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) 4065{ 4066 s32 ret_val; 4067 u16 page = offset >> GS40G_PAGE_SHIFT; 4068 4069 DEBUGFUNC("e1000_read_phy_reg_gs40g"); 4070 4071 offset = offset & GS40G_OFFSET_MASK; 4072 ret_val = hw->phy.ops.acquire(hw); 4073 if (ret_val) 4074 return ret_val; 4075 4076 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4077 if (ret_val) 4078 goto release; 4079 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 4080 4081release: 4082 hw->phy.ops.release(hw); 4083 return ret_val; 4084} 4085 4086