e1000_80003es2lan.c revision 176667
1/******************************************************************************* 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/* $FreeBSD: head/sys/dev/em/e1000_80003es2lan.c 176667 2008-02-29 21:50:11Z jfv $ */ 34 35 36/* e1000_80003es2lan 37 */ 38 39#include "e1000_api.h" 40#include "e1000_80003es2lan.h" 41 42STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw); 43STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw); 44STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw); 45STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); 46STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw); 47STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); 48STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); 49STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 50 u32 offset, 51 u16 *data); 52STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 53 u32 offset, 54 u16 data); 55STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 56 u16 words, u16 *data); 57STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); 58STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); 59STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); 60STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 61 u16 *duplex); 62STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); 63STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); 64STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 65STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 66static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 67static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 68static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 69static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw); 70static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 71static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 72STATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw); 73STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); 74 75/* 76 * A table for the GG82563 cable length where the range is defined 77 * with a lower bound at "index" and the upper bound at 78 * "index + 5". 79 */ 80static const u16 e1000_gg82563_cable_length_table[] = 81 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; 82#define GG82563_CABLE_LENGTH_TABLE_SIZE \ 83 (sizeof(e1000_gg82563_cable_length_table) / \ 84 sizeof(e1000_gg82563_cable_length_table[0])) 85 86/** 87 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 88 * @hw: pointer to the HW structure 89 * 90 * This is a function pointer entry point called by the api module. 91 **/ 92STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 93{ 94 struct e1000_phy_info *phy = &hw->phy; 95 struct e1000_functions *func = &hw->func; 96 s32 ret_val = E1000_SUCCESS; 97 98 DEBUGFUNC("e1000_init_phy_params_80003es2lan"); 99 100 if (hw->phy.media_type != e1000_media_type_copper) { 101 phy->type = e1000_phy_none; 102 goto out; 103 } else { 104 func->power_up_phy = e1000_power_up_phy_copper; 105 func->power_down_phy = e1000_power_down_phy_copper_80003es2lan; 106 } 107 108 phy->addr = 1; 109 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 110 phy->reset_delay_us = 100; 111 phy->type = e1000_phy_gg82563; 112 113 func->acquire_phy = e1000_acquire_phy_80003es2lan; 114 func->check_polarity = e1000_check_polarity_m88; 115 func->check_reset_block = e1000_check_reset_block_generic; 116 func->commit_phy = e1000_phy_sw_reset_generic; 117 func->get_cfg_done = e1000_get_cfg_done_80003es2lan; 118 func->get_phy_info = e1000_get_phy_info_m88; 119 func->release_phy = e1000_release_phy_80003es2lan; 120 func->reset_phy = e1000_phy_hw_reset_generic; 121 func->set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 122 123 func->force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; 124 func->get_cable_length = e1000_get_cable_length_80003es2lan; 125 func->read_phy_reg = e1000_read_phy_reg_gg82563_80003es2lan; 126 func->write_phy_reg = e1000_write_phy_reg_gg82563_80003es2lan; 127 128 /* This can only be done after all function pointers are setup. */ 129 ret_val = e1000_get_phy_id(hw); 130 131 /* Verify phy id */ 132 if (phy->id != GG82563_E_PHY_ID) { 133 ret_val = -E1000_ERR_PHY; 134 goto out; 135 } 136 137out: 138 return ret_val; 139} 140 141/** 142 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 143 * @hw: pointer to the HW structure 144 * 145 * This is a function pointer entry point called by the api module. 146 **/ 147STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 148{ 149 struct e1000_nvm_info *nvm = &hw->nvm; 150 struct e1000_functions *func = &hw->func; 151 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 152 u16 size; 153 154 DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); 155 156 nvm->opcode_bits = 8; 157 nvm->delay_usec = 1; 158 switch (nvm->override) { 159 case e1000_nvm_override_spi_large: 160 nvm->page_size = 32; 161 nvm->address_bits = 16; 162 break; 163 case e1000_nvm_override_spi_small: 164 nvm->page_size = 8; 165 nvm->address_bits = 8; 166 break; 167 default: 168 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 169 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 170 break; 171 } 172 173 nvm->type = e1000_nvm_eeprom_spi; 174 175 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 176 E1000_EECD_SIZE_EX_SHIFT); 177 178 /* 179 * Added to a constant, "size" becomes the left-shift value 180 * for setting word_size. 181 */ 182 size += NVM_WORD_SIZE_BASE_SHIFT; 183 184 /* EEPROM access above 16k is unsupported */ 185 if (size > 14) 186 size = 14; 187 nvm->word_size = 1 << size; 188 189 /* Function Pointers */ 190 func->acquire_nvm = e1000_acquire_nvm_80003es2lan; 191 func->read_nvm = e1000_read_nvm_eerd; 192 func->release_nvm = e1000_release_nvm_80003es2lan; 193 func->update_nvm = e1000_update_nvm_checksum_generic; 194 func->valid_led_default = e1000_valid_led_default_generic; 195 func->validate_nvm = e1000_validate_nvm_checksum_generic; 196 func->write_nvm = e1000_write_nvm_80003es2lan; 197 198 return E1000_SUCCESS; 199} 200 201/** 202 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 203 * @hw: pointer to the HW structure 204 * 205 * This is a function pointer entry point called by the api module. 206 **/ 207STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 208{ 209 struct e1000_mac_info *mac = &hw->mac; 210 struct e1000_functions *func = &hw->func; 211 s32 ret_val = E1000_SUCCESS; 212 213 DEBUGFUNC("e1000_init_mac_params_80003es2lan"); 214 215 /* Set media type */ 216 switch (hw->device_id) { 217 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 218 hw->phy.media_type = e1000_media_type_internal_serdes; 219 break; 220 default: 221 hw->phy.media_type = e1000_media_type_copper; 222 break; 223 } 224 225 /* Set mta register count */ 226 mac->mta_reg_count = 128; 227 /* Set rar entry count */ 228 mac->rar_entry_count = E1000_RAR_ENTRIES; 229 /* Set if part includes ASF firmware */ 230 mac->asf_firmware_present = TRUE; 231 /* Set if manageability features are enabled. */ 232 mac->arc_subsystem_valid = 233 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 234 ? TRUE : FALSE; 235 236 /* Function pointers */ 237 238 /* bus type/speed/width */ 239 func->get_bus_info = e1000_get_bus_info_pcie_generic; 240 /* reset */ 241 func->reset_hw = e1000_reset_hw_80003es2lan; 242 /* hw initialization */ 243 func->init_hw = e1000_init_hw_80003es2lan; 244 /* link setup */ 245 func->setup_link = e1000_setup_link_generic; 246 /* physical interface link setup */ 247 func->setup_physical_interface = 248 (hw->phy.media_type == e1000_media_type_copper) 249 ? e1000_setup_copper_link_80003es2lan 250 : e1000_setup_fiber_serdes_link_generic; 251 /* check for link */ 252 switch (hw->phy.media_type) { 253 case e1000_media_type_copper: 254 func->check_for_link = e1000_check_for_copper_link_generic; 255 break; 256 case e1000_media_type_fiber: 257 func->check_for_link = e1000_check_for_fiber_link_generic; 258 break; 259 case e1000_media_type_internal_serdes: 260 func->check_for_link = e1000_check_for_serdes_link_generic; 261 break; 262 default: 263 ret_val = -E1000_ERR_CONFIG; 264 goto out; 265 break; 266 } 267 /* check management mode */ 268 func->check_mng_mode = e1000_check_mng_mode_generic; 269 /* multicast address update */ 270 func->update_mc_addr_list = e1000_update_mc_addr_list_generic; 271 /* writing VFTA */ 272 func->write_vfta = e1000_write_vfta_generic; 273 /* clearing VFTA */ 274 func->clear_vfta = e1000_clear_vfta_generic; 275 /* setting MTA */ 276 func->mta_set = e1000_mta_set_generic; 277 /* read mac address */ 278 func->read_mac_addr = e1000_read_mac_addr_80003es2lan; 279 /* blink LED */ 280 func->blink_led = e1000_blink_led_generic; 281 /* setup LED */ 282 func->setup_led = e1000_setup_led_generic; 283 /* cleanup LED */ 284 func->cleanup_led = e1000_cleanup_led_generic; 285 /* turn on/off LED */ 286 func->led_on = e1000_led_on_generic; 287 func->led_off = e1000_led_off_generic; 288 /* remove device */ 289 func->remove_device = e1000_remove_device_generic; 290 /* clear hardware counters */ 291 func->clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; 292 /* link info */ 293 func->get_link_up_info = e1000_get_link_up_info_80003es2lan; 294 295out: 296 return ret_val; 297} 298 299/** 300 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. 301 * @hw: pointer to the HW structure 302 * 303 * The only function explicitly called by the api module to initialize 304 * all function pointers and parameters. 305 **/ 306void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) 307{ 308 DEBUGFUNC("e1000_init_function_pointers_80003es2lan"); 309 310 hw->func.init_mac_params = e1000_init_mac_params_80003es2lan; 311 hw->func.init_nvm_params = e1000_init_nvm_params_80003es2lan; 312 hw->func.init_phy_params = e1000_init_phy_params_80003es2lan; 313} 314 315/** 316 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 317 * @hw: pointer to the HW structure 318 * 319 * A wrapper to acquire access rights to the correct PHY. This is a 320 * function pointer entry point called by the api module. 321 **/ 322STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 323{ 324 u16 mask; 325 326 DEBUGFUNC("e1000_acquire_phy_80003es2lan"); 327 328 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 329 mask |= E1000_SWFW_CSR_SM; 330 331 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 332} 333 334/** 335 * e1000_release_phy_80003es2lan - Release rights to access PHY 336 * @hw: pointer to the HW structure 337 * 338 * A wrapper to release access rights to the correct PHY. This is a 339 * function pointer entry point called by the api module. 340 **/ 341STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw) 342{ 343 u16 mask; 344 345 DEBUGFUNC("e1000_release_phy_80003es2lan"); 346 347 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 348 mask |= E1000_SWFW_CSR_SM; 349 350 e1000_release_swfw_sync_80003es2lan(hw, mask); 351} 352 353/** 354 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 355 * @hw: pointer to the HW structure 356 * 357 * Acquire the semaphore to access the EEPROM. This is a function 358 * pointer entry point called by the api module. 359 **/ 360STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 361{ 362 s32 ret_val; 363 364 DEBUGFUNC("e1000_acquire_nvm_80003es2lan"); 365 366 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 367 if (ret_val) 368 goto out; 369 370 ret_val = e1000_acquire_nvm_generic(hw); 371 372 if (ret_val) 373 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 374 375out: 376 return ret_val; 377} 378 379/** 380 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 381 * @hw: pointer to the HW structure 382 * 383 * Release the semaphore used to access the EEPROM. This is a 384 * function pointer entry point called by the api module. 385 **/ 386STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 387{ 388 DEBUGFUNC("e1000_release_nvm_80003es2lan"); 389 390 e1000_release_nvm_generic(hw); 391 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 392} 393 394/** 395 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore 396 * @hw: pointer to the HW structure 397 * @mask: specifies which semaphore to acquire 398 * 399 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 400 * will also specify which port we're acquiring the lock for. 401 **/ 402static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 403{ 404 u32 swfw_sync; 405 u32 swmask = mask; 406 u32 fwmask = mask << 16; 407 s32 ret_val = E1000_SUCCESS; 408 s32 i = 0, timeout = 200; 409 410 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan"); 411 412 while (i < timeout) { 413 if (e1000_get_hw_semaphore_generic(hw)) { 414 ret_val = -E1000_ERR_SWFW_SYNC; 415 goto out; 416 } 417 418 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 419 if (!(swfw_sync & (fwmask | swmask))) 420 break; 421 422 /* 423 * Firmware currently using resource (fwmask) 424 * or other software thread using resource (swmask) 425 */ 426 e1000_put_hw_semaphore_generic(hw); 427 msec_delay_irq(5); 428 i++; 429 } 430 431 if (i == timeout) { 432 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 433 ret_val = -E1000_ERR_SWFW_SYNC; 434 goto out; 435 } 436 437 swfw_sync |= swmask; 438 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 439 440 e1000_put_hw_semaphore_generic(hw); 441 442out: 443 return ret_val; 444} 445 446/** 447 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore 448 * @hw: pointer to the HW structure 449 * @mask: specifies which semaphore to acquire 450 * 451 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 452 * will also specify which port we're releasing the lock for. 453 **/ 454static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 455{ 456 u32 swfw_sync; 457 458 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan"); 459 460 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 461 /* Empty */ 462 463 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 464 swfw_sync &= ~mask; 465 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 466 467 e1000_put_hw_semaphore_generic(hw); 468} 469 470/** 471 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 472 * @hw: pointer to the HW structure 473 * @offset: offset of the register to read 474 * @data: pointer to the data returned from the operation 475 * 476 * Read the GG82563 PHY register. This is a function pointer entry 477 * point called by the api module. 478 **/ 479STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 480 u32 offset, u16 *data) 481{ 482 s32 ret_val; 483 u32 page_select; 484 u16 temp; 485 486 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan"); 487 488 ret_val = e1000_acquire_phy_80003es2lan(hw); 489 if (ret_val) 490 goto out; 491 492 /* Select Configuration Page */ 493 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 494 page_select = GG82563_PHY_PAGE_SELECT; 495 } else { 496 /* 497 * Use Alternative Page Select register to access 498 * registers 30 and 31 499 */ 500 page_select = GG82563_PHY_PAGE_SELECT_ALT; 501 } 502 503 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 504 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 505 if (ret_val) { 506 e1000_release_phy_80003es2lan(hw); 507 goto out; 508 } 509 510 /* 511 * The "ready" bit in the MDIC register may be incorrectly set 512 * before the device has completed the "Page Select" MDI 513 * transaction. So we wait 200us after each MDI command... 514 */ 515 usec_delay(200); 516 517 /* ...and verify the command was successful. */ 518 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 519 520 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 521 ret_val = -E1000_ERR_PHY; 522 e1000_release_phy_80003es2lan(hw); 523 goto out; 524 } 525 526 usec_delay(200); 527 528 ret_val = e1000_read_phy_reg_mdic(hw, 529 MAX_PHY_REG_ADDRESS & offset, 530 data); 531 532 usec_delay(200); 533 e1000_release_phy_80003es2lan(hw); 534 535out: 536 return ret_val; 537} 538 539/** 540 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 541 * @hw: pointer to the HW structure 542 * @offset: offset of the register to read 543 * @data: value to write to the register 544 * 545 * Write to the GG82563 PHY register. This is a function pointer entry 546 * point called by the api module. 547 **/ 548STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 549 u32 offset, u16 data) 550{ 551 s32 ret_val; 552 u32 page_select; 553 u16 temp; 554 555 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan"); 556 557 ret_val = e1000_acquire_phy_80003es2lan(hw); 558 if (ret_val) 559 goto out; 560 561 /* Select Configuration Page */ 562 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 563 page_select = GG82563_PHY_PAGE_SELECT; 564 } else { 565 /* 566 * Use Alternative Page Select register to access 567 * registers 30 and 31 568 */ 569 page_select = GG82563_PHY_PAGE_SELECT_ALT; 570 } 571 572 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 573 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 574 if (ret_val) { 575 e1000_release_phy_80003es2lan(hw); 576 goto out; 577 } 578 579 580 /* 581 * The "ready" bit in the MDIC register may be incorrectly set 582 * before the device has completed the "Page Select" MDI 583 * transaction. So we wait 200us after each MDI command... 584 */ 585 usec_delay(200); 586 587 /* ...and verify the command was successful. */ 588 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 589 590 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 591 ret_val = -E1000_ERR_PHY; 592 e1000_release_phy_80003es2lan(hw); 593 goto out; 594 } 595 596 usec_delay(200); 597 598 ret_val = e1000_write_phy_reg_mdic(hw, 599 MAX_PHY_REG_ADDRESS & offset, 600 data); 601 602 usec_delay(200); 603 e1000_release_phy_80003es2lan(hw); 604 605out: 606 return ret_val; 607} 608 609/** 610 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 611 * @hw: pointer to the HW structure 612 * @offset: offset of the register to read 613 * @words: number of words to write 614 * @data: buffer of data to write to the NVM 615 * 616 * Write "words" of data to the ESB2 NVM. This is a function 617 * pointer entry point called by the api module. 618 **/ 619STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 620 u16 words, u16 *data) 621{ 622 DEBUGFUNC("e1000_write_nvm_80003es2lan"); 623 624 return e1000_write_nvm_spi(hw, offset, words, data); 625} 626 627/** 628 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 629 * @hw: pointer to the HW structure 630 * 631 * Wait a specific amount of time for manageability processes to complete. 632 * This is a function pointer entry point called by the phy module. 633 **/ 634STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 635{ 636 s32 timeout = PHY_CFG_TIMEOUT; 637 s32 ret_val = E1000_SUCCESS; 638 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 639 640 DEBUGFUNC("e1000_get_cfg_done_80003es2lan"); 641 642 if (hw->bus.func == 1) 643 mask = E1000_NVM_CFG_DONE_PORT_1; 644 645 while (timeout) { 646 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 647 break; 648 msec_delay(1); 649 timeout--; 650 } 651 if (!timeout) { 652 DEBUGOUT("MNG configuration cycle has not completed.\n"); 653 ret_val = -E1000_ERR_RESET; 654 goto out; 655 } 656 657out: 658 return ret_val; 659} 660 661/** 662 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 663 * @hw: pointer to the HW structure 664 * 665 * Force the speed and duplex settings onto the PHY. This is a 666 * function pointer entry point called by the phy module. 667 **/ 668STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 669{ 670 s32 ret_val; 671 u16 phy_data; 672 bool link; 673 674 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan"); 675 676 /* 677 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 678 * forced whenever speed and duplex are forced. 679 */ 680 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 681 if (ret_val) 682 goto out; 683 684 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 685 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 686 if (ret_val) 687 goto out; 688 689 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); 690 691 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data); 692 if (ret_val) 693 goto out; 694 695 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 696 697 /* Reset the phy to commit changes. */ 698 phy_data |= MII_CR_RESET; 699 700 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data); 701 if (ret_val) 702 goto out; 703 704 usec_delay(1); 705 706 if (hw->phy.autoneg_wait_to_complete) { 707 DEBUGOUT("Waiting for forced speed/duplex link " 708 "on GG82563 phy.\n"); 709 710 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 711 100000, &link); 712 if (ret_val) 713 goto out; 714 715 if (!link) { 716 /* 717 * We didn't get link. 718 * Reset the DSP and cross our fingers. 719 */ 720 ret_val = e1000_phy_reset_dsp_generic(hw); 721 if (ret_val) 722 goto out; 723 } 724 725 /* Try once more */ 726 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 727 100000, &link); 728 if (ret_val) 729 goto out; 730 } 731 732 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 733 if (ret_val) 734 goto out; 735 736 /* 737 * Resetting the phy means we need to verify the TX_CLK corresponds 738 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 739 */ 740 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 741 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 742 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 743 else 744 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 745 746 /* 747 * In addition, we must re-enable CRS on Tx for both half and full 748 * duplex. 749 */ 750 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 751 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); 752 753out: 754 return ret_val; 755} 756 757/** 758 * e1000_get_cable_length_80003es2lan - Set approximate cable length 759 * @hw: pointer to the HW structure 760 * 761 * Find the approximate cable length as measured by the GG82563 PHY. 762 * This is a function pointer entry point called by the phy module. 763 **/ 764STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 765{ 766 struct e1000_phy_info *phy = &hw->phy; 767 s32 ret_val; 768 u16 phy_data, index; 769 770 DEBUGFUNC("e1000_get_cable_length_80003es2lan"); 771 772 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 773 if (ret_val) 774 goto out; 775 776 index = phy_data & GG82563_DSPD_CABLE_LENGTH; 777 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 778 phy->max_cable_length = e1000_gg82563_cable_length_table[index+5]; 779 780 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 781 782out: 783 return ret_val; 784} 785 786/** 787 * e1000_get_link_up_info_80003es2lan - Report speed and duplex 788 * @hw: pointer to the HW structure 789 * @speed: pointer to speed buffer 790 * @duplex: pointer to duplex buffer 791 * 792 * Retrieve the current speed and duplex configuration. 793 * This is a function pointer entry point called by the api module. 794 **/ 795STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 796 u16 *duplex) 797{ 798 s32 ret_val; 799 800 DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); 801 802 if (hw->phy.media_type == e1000_media_type_copper) { 803 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, 804 speed, 805 duplex); 806 if (ret_val) 807 goto out; 808 if (*speed == SPEED_1000) 809 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 810 else 811 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, 812 *duplex); 813 } else { 814 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, 815 speed, 816 duplex); 817 } 818 819out: 820 return ret_val; 821} 822 823/** 824 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 825 * @hw: pointer to the HW structure 826 * 827 * Perform a global reset to the ESB2 controller. 828 * This is a function pointer entry point called by the api module. 829 **/ 830STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 831{ 832 u32 ctrl, icr; 833 s32 ret_val; 834 835 DEBUGFUNC("e1000_reset_hw_80003es2lan"); 836 837 /* 838 * Prevent the PCI-E bus from sticking if there is no TLP connection 839 * on the last TLP read/write transaction when MAC is reset. 840 */ 841 ret_val = e1000_disable_pcie_master_generic(hw); 842 if (ret_val) { 843 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 844 } 845 846 DEBUGOUT("Masking off all interrupts\n"); 847 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 848 849 E1000_WRITE_REG(hw, E1000_RCTL, 0); 850 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 851 E1000_WRITE_FLUSH(hw); 852 853 msec_delay(10); 854 855 ctrl = E1000_READ_REG(hw, E1000_CTRL); 856 857 DEBUGOUT("Issuing a global reset to MAC\n"); 858 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 859 860 ret_val = e1000_get_auto_rd_done_generic(hw); 861 if (ret_val) 862 /* We don't want to continue accessing MAC registers. */ 863 goto out; 864 865 /* Clear any pending interrupt events. */ 866 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 867 icr = E1000_READ_REG(hw, E1000_ICR); 868 869 e1000_check_alt_mac_addr_generic(hw); 870 871out: 872 return ret_val; 873} 874 875/** 876 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 877 * @hw: pointer to the HW structure 878 * 879 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 880 * This is a function pointer entry point called by the api module. 881 **/ 882STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 883{ 884 struct e1000_mac_info *mac = &hw->mac; 885 u32 reg_data; 886 s32 ret_val; 887 u16 i; 888 889 DEBUGFUNC("e1000_init_hw_80003es2lan"); 890 891 e1000_initialize_hw_bits_80003es2lan(hw); 892 893 /* Initialize identification LED */ 894 ret_val = e1000_id_led_init_generic(hw); 895 if (ret_val) { 896 DEBUGOUT("Error initializing identification LED\n"); 897 /* This is not fatal and we should not stop init due to this */ 898 } 899 900 /* Disabling VLAN filtering */ 901 DEBUGOUT("Initializing the IEEE VLAN\n"); 902 e1000_clear_vfta(hw); 903 904 /* Setup the receive address. */ 905 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 906 907 /* Zero out the Multicast HASH table */ 908 DEBUGOUT("Zeroing the MTA\n"); 909 for (i = 0; i < mac->mta_reg_count; i++) 910 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 911 912 /* Setup link and flow control */ 913 ret_val = e1000_setup_link(hw); 914 915 /* Set the transmit descriptor write-back policy */ 916 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 917 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 918 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 919 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 920 921 /* ...for both queues. */ 922 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 923 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 924 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 925 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 926 927 /* Enable retransmit on late collisions */ 928 reg_data = E1000_READ_REG(hw, E1000_TCTL); 929 reg_data |= E1000_TCTL_RTLC; 930 E1000_WRITE_REG(hw, E1000_TCTL, reg_data); 931 932 /* Configure Gigabit Carry Extend Padding */ 933 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); 934 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 935 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 936 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); 937 938 /* Configure Transmit Inter-Packet Gap */ 939 reg_data = E1000_READ_REG(hw, E1000_TIPG); 940 reg_data &= ~E1000_TIPG_IPGT_MASK; 941 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 942 E1000_WRITE_REG(hw, E1000_TIPG, reg_data); 943 944 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 945 reg_data &= ~0x00100000; 946 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 947 948 /* 949 * Clear all of the statistics registers (clear on read). It is 950 * important that we do this after we have tried to establish link 951 * because the symbol error count will increment wildly if there 952 * is no link. 953 */ 954 e1000_clear_hw_cntrs_80003es2lan(hw); 955 956 return ret_val; 957} 958 959/** 960 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 961 * @hw: pointer to the HW structure 962 * 963 * Initializes required hardware-dependent bits needed for normal operation. 964 **/ 965static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 966{ 967 u32 reg; 968 969 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan"); 970 971 if (hw->mac.disable_hw_init_bits) 972 goto out; 973 974 /* Transmit Descriptor Control 0 */ 975 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 976 reg |= (1 << 22); 977 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 978 979 /* Transmit Descriptor Control 1 */ 980 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 981 reg |= (1 << 22); 982 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 983 984 /* Transmit Arbitration Control 0 */ 985 reg = E1000_READ_REG(hw, E1000_TARC(0)); 986 reg &= ~(0xF << 27); /* 30:27 */ 987 if (hw->phy.media_type != e1000_media_type_copper) 988 reg &= ~(1 << 20); 989 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 990 991 /* Transmit Arbitration Control 1 */ 992 reg = E1000_READ_REG(hw, E1000_TARC(1)); 993 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 994 reg &= ~(1 << 28); 995 else 996 reg |= (1 << 28); 997 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 998 999out: 1000 return; 1001} 1002 1003/** 1004 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 1005 * @hw: pointer to the HW structure 1006 * 1007 * Setup some GG82563 PHY registers for obtaining link 1008 **/ 1009static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 1010{ 1011 struct e1000_phy_info *phy = &hw->phy; 1012 s32 ret_val; 1013 u32 ctrl_ext; 1014 u32 i = 0; 1015 u16 data, data2; 1016 1017 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); 1018 1019 if (!phy->reset_disable) { 1020 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1021 &data); 1022 if (ret_val) 1023 goto out; 1024 1025 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1026 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 1027 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 1028 1029 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1030 data); 1031 if (ret_val) 1032 goto out; 1033 1034 /* 1035 * Options: 1036 * MDI/MDI-X = 0 (default) 1037 * 0 - Auto for all speeds 1038 * 1 - MDI mode 1039 * 2 - MDI-X mode 1040 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1041 */ 1042 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &data); 1043 if (ret_val) 1044 goto out; 1045 1046 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1047 1048 switch (phy->mdix) { 1049 case 1: 1050 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1051 break; 1052 case 2: 1053 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1054 break; 1055 case 0: 1056 default: 1057 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1058 break; 1059 } 1060 1061 /* 1062 * Options: 1063 * disable_polarity_correction = 0 (default) 1064 * Automatic Correction for Reversed Cable Polarity 1065 * 0 - Disabled 1066 * 1 - Enabled 1067 */ 1068 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1069 if (phy->disable_polarity_correction) 1070 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1071 1072 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, data); 1073 if (ret_val) 1074 goto out; 1075 1076 /* SW Reset the PHY so all changes take effect */ 1077 ret_val = e1000_phy_commit(hw); 1078 if (ret_val) { 1079 DEBUGOUT("Error Resetting the PHY\n"); 1080 goto out; 1081 } 1082 1083 } 1084 1085 /* Bypass Rx and Tx FIFO's */ 1086 ret_val = e1000_write_kmrn_reg(hw, 1087 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, 1088 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 1089 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 1090 if (ret_val) 1091 goto out; 1092 1093 ret_val = e1000_read_kmrn_reg(hw, 1094 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, 1095 &data); 1096 if (ret_val) 1097 goto out; 1098 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; 1099 ret_val = e1000_write_kmrn_reg(hw, 1100 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, 1101 data); 1102 if (ret_val) 1103 goto out; 1104 1105 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); 1106 if (ret_val) 1107 goto out; 1108 1109 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1110 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); 1111 if (ret_val) 1112 goto out; 1113 1114 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1115 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 1116 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1117 1118 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 1119 if (ret_val) 1120 goto out; 1121 1122 /* 1123 * Do not init these registers when the HW is in IAMT mode, since the 1124 * firmware will have already initialized them. We only initialize 1125 * them if the HW is not in IAMT mode. 1126 */ 1127 if (!(e1000_check_mng_mode(hw))) { 1128 /* Enable Electrical Idle on the PHY */ 1129 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1130 ret_val = e1000_write_phy_reg(hw, 1131 GG82563_PHY_PWR_MGMT_CTRL, 1132 data); 1133 if (ret_val) 1134 goto out; 1135 1136 do { 1137 ret_val = e1000_read_phy_reg(hw, 1138 GG82563_PHY_KMRN_MODE_CTRL, 1139 &data); 1140 if (ret_val) 1141 goto out; 1142 1143 ret_val = e1000_read_phy_reg(hw, 1144 GG82563_PHY_KMRN_MODE_CTRL, 1145 &data2); 1146 if (ret_val) 1147 goto out; 1148 i++; 1149 } while ((data != data2) && (i < GG82563_MAX_KMRN_RETRY)); 1150 1151 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1152 ret_val = e1000_write_phy_reg(hw, 1153 GG82563_PHY_KMRN_MODE_CTRL, 1154 data); 1155 1156 if (ret_val) 1157 goto out; 1158 } 1159 1160 /* 1161 * Workaround: Disable padding in Kumeran interface in the MAC 1162 * and in the PHY to avoid CRC errors. 1163 */ 1164 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, &data); 1165 if (ret_val) 1166 goto out; 1167 1168 data |= GG82563_ICR_DIS_PADDING; 1169 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, data); 1170 if (ret_val) 1171 goto out; 1172 1173out: 1174 return ret_val; 1175} 1176 1177/** 1178 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1179 * @hw: pointer to the HW structure 1180 * 1181 * Essentially a wrapper for setting up all things "copper" related. 1182 * This is a function pointer entry point called by the mac module. 1183 **/ 1184STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1185{ 1186 u32 ctrl; 1187 s32 ret_val; 1188 u16 reg_data; 1189 1190 DEBUGFUNC("e1000_setup_copper_link_80003es2lan"); 1191 1192 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1193 ctrl |= E1000_CTRL_SLU; 1194 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1195 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1196 1197 /* 1198 * Set the mac to wait the maximum time between each 1199 * iteration and increase the max iterations when 1200 * polling the phy; this fixes erroneous timeouts at 10Mbps. 1201 */ 1202 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 1203 if (ret_val) 1204 goto out; 1205 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); 1206 if (ret_val) 1207 goto out; 1208 reg_data |= 0x3F; 1209 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); 1210 if (ret_val) 1211 goto out; 1212 ret_val = e1000_read_kmrn_reg(hw, 1213 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1214 ®_data); 1215 if (ret_val) 1216 goto out; 1217 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1218 ret_val = e1000_write_kmrn_reg(hw, 1219 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1220 reg_data); 1221 if (ret_val) 1222 goto out; 1223 1224 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1225 if (ret_val) 1226 goto out; 1227 1228 ret_val = e1000_setup_copper_link_generic(hw); 1229 1230out: 1231 return ret_val; 1232} 1233 1234/** 1235 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1236 * @hw: pointer to the HW structure 1237 * @duplex: current duplex setting 1238 * 1239 * Configure the KMRN interface by applying last minute quirks for 1240 * 10/100 operation. 1241 **/ 1242static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1243{ 1244 s32 ret_val = E1000_SUCCESS; 1245 u32 tipg; 1246 u32 i = 0; 1247 u16 reg_data, reg_data2; 1248 1249 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 1250 1251 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1252 ret_val = e1000_write_kmrn_reg(hw, 1253 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1254 reg_data); 1255 if (ret_val) 1256 goto out; 1257 1258 /* Configure Transmit Inter-Packet Gap */ 1259 tipg = E1000_READ_REG(hw, E1000_TIPG); 1260 tipg &= ~E1000_TIPG_IPGT_MASK; 1261 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1262 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1263 1264 1265 do { 1266 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1267 ®_data); 1268 if (ret_val) 1269 goto out; 1270 1271 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1272 ®_data2); 1273 if (ret_val) 1274 goto out; 1275 i++; 1276 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1277 1278 if (duplex == HALF_DUPLEX) 1279 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1280 else 1281 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1282 1283 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1284 1285out: 1286 return ret_val; 1287} 1288 1289/** 1290 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1291 * @hw: pointer to the HW structure 1292 * 1293 * Configure the KMRN interface by applying last minute quirks for 1294 * gigabit operation. 1295 **/ 1296static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1297{ 1298 s32 ret_val = E1000_SUCCESS; 1299 u16 reg_data, reg_data2; 1300 u32 tipg; 1301 u32 i = 0; 1302 1303 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 1304 1305 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1306 ret_val = e1000_write_kmrn_reg(hw, 1307 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1308 reg_data); 1309 if (ret_val) 1310 goto out; 1311 1312 /* Configure Transmit Inter-Packet Gap */ 1313 tipg = E1000_READ_REG(hw, E1000_TIPG); 1314 tipg &= ~E1000_TIPG_IPGT_MASK; 1315 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1316 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1317 1318 1319 do { 1320 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1321 ®_data); 1322 if (ret_val) 1323 goto out; 1324 1325 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1326 ®_data2); 1327 if (ret_val) 1328 goto out; 1329 i++; 1330 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1331 1332 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1333 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1334 1335out: 1336 return ret_val; 1337} 1338 1339/** 1340 * e1000_read_mac_addr_80003es2lan - Read device MAC address 1341 * @hw: pointer to the HW structure 1342 **/ 1343STATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) 1344{ 1345 s32 ret_val = E1000_SUCCESS; 1346 1347 DEBUGFUNC("e1000_read_mac_addr_80003es2lan"); 1348 if (e1000_check_alt_mac_addr_generic(hw)) 1349 ret_val = e1000_read_mac_addr_generic(hw); 1350 1351 return ret_val; 1352} 1353 1354/** 1355 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down 1356 * @hw: pointer to the HW structure 1357 * 1358 * In the case of a PHY power down to save power, or to turn off link during a 1359 * driver unload, or wake on lan is not enabled, remove the link. 1360 **/ 1361STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) 1362{ 1363 /* If the management interface is not enabled, then power down */ 1364 if (!(e1000_check_mng_mode(hw) || e1000_check_reset_block(hw))) 1365 e1000_power_down_phy_copper(hw); 1366 1367 return; 1368} 1369 1370/** 1371 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1372 * @hw: pointer to the HW structure 1373 * 1374 * Clears the hardware counters by reading the counter registers. 1375 **/ 1376STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1377{ 1378 volatile u32 temp; 1379 1380 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan"); 1381 1382 e1000_clear_hw_cntrs_base_generic(hw); 1383 1384 temp = E1000_READ_REG(hw, E1000_PRC64); 1385 temp = E1000_READ_REG(hw, E1000_PRC127); 1386 temp = E1000_READ_REG(hw, E1000_PRC255); 1387 temp = E1000_READ_REG(hw, E1000_PRC511); 1388 temp = E1000_READ_REG(hw, E1000_PRC1023); 1389 temp = E1000_READ_REG(hw, E1000_PRC1522); 1390 temp = E1000_READ_REG(hw, E1000_PTC64); 1391 temp = E1000_READ_REG(hw, E1000_PTC127); 1392 temp = E1000_READ_REG(hw, E1000_PTC255); 1393 temp = E1000_READ_REG(hw, E1000_PTC511); 1394 temp = E1000_READ_REG(hw, E1000_PTC1023); 1395 temp = E1000_READ_REG(hw, E1000_PTC1522); 1396 1397 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1398 temp = E1000_READ_REG(hw, E1000_RXERRC); 1399 temp = E1000_READ_REG(hw, E1000_TNCRS); 1400 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1401 temp = E1000_READ_REG(hw, E1000_TSCTC); 1402 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1403 1404 temp = E1000_READ_REG(hw, E1000_MGTPRC); 1405 temp = E1000_READ_REG(hw, E1000_MGTPDC); 1406 temp = E1000_READ_REG(hw, E1000_MGTPTC); 1407 1408 temp = E1000_READ_REG(hw, E1000_IAC); 1409 temp = E1000_READ_REG(hw, E1000_ICRXOC); 1410 1411 temp = E1000_READ_REG(hw, E1000_ICRXPTC); 1412 temp = E1000_READ_REG(hw, E1000_ICRXATC); 1413 temp = E1000_READ_REG(hw, E1000_ICTXPTC); 1414 temp = E1000_READ_REG(hw, E1000_ICTXATC); 1415 temp = E1000_READ_REG(hw, E1000_ICTXQEC); 1416 temp = E1000_READ_REG(hw, E1000_ICTXQMTC); 1417 temp = E1000_READ_REG(hw, E1000_ICRXDMTC); 1418} 1419