e1000_80003es2lan.c revision 173788
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/* $FreeBSD: head/sys/dev/em/e1000_80003es2lan.c 173788 2007-11-20 21:41:22Z jfv $ */ 34 35/* e1000_80003es2lan 36 */ 37 38#include "e1000_api.h" 39#include "e1000_80003es2lan.h" 40 41void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw); 42 43STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw); 44STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw); 45STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw); 46STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); 47STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw); 48STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); 49STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); 50STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 51 u32 offset, 52 u16 *data); 53STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 54 u32 offset, 55 u16 data); 56STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 57 u16 words, u16 *data); 58STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); 59STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); 60STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); 61STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 62 u16 *duplex); 63STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); 64STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); 65STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 66STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 67static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 68static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 69static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 70static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw); 71static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 72static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 73STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); 74 75/* 76 * A table for the GG82563 cable length where the range is defined 77 * with a lower bound at "index" and the upper bound at 78 * "index + 5". 79 */ 80static const u16 e1000_gg82563_cable_length_table[] = 81 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; 82#define GG82563_CABLE_LENGTH_TABLE_SIZE \ 83 (sizeof(e1000_gg82563_cable_length_table) / \ 84 sizeof(e1000_gg82563_cable_length_table[0])) 85 86/** 87 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 88 * @hw: pointer to the HW structure 89 * 90 * This is a function pointer entry point called by the api module. 91 **/ 92STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 93{ 94 struct e1000_phy_info *phy = &hw->phy; 95 struct e1000_functions *func = &hw->func; 96 s32 ret_val = E1000_SUCCESS; 97 98 DEBUGFUNC("e1000_init_phy_params_80003es2lan"); 99 100 if (hw->phy.media_type != e1000_media_type_copper) { 101 phy->type = e1000_phy_none; 102 goto out; 103 } else { 104 func->power_up_phy = e1000_power_up_phy_copper; 105 func->power_down_phy = e1000_power_down_phy_copper_80003es2lan; 106 } 107 108 phy->addr = 1; 109 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 110 phy->reset_delay_us = 100; 111 phy->type = e1000_phy_gg82563; 112 113 func->acquire_phy = e1000_acquire_phy_80003es2lan; 114 func->check_polarity = e1000_check_polarity_m88; 115 func->check_reset_block = e1000_check_reset_block_generic; 116 func->commit_phy = e1000_phy_sw_reset_generic; 117 func->get_cfg_done = e1000_get_cfg_done_80003es2lan; 118 func->get_phy_info = e1000_get_phy_info_m88; 119 func->release_phy = e1000_release_phy_80003es2lan; 120 func->reset_phy = e1000_phy_hw_reset_generic; 121 func->set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 122 123 func->force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; 124 func->get_cable_length = e1000_get_cable_length_80003es2lan; 125 func->read_phy_reg = e1000_read_phy_reg_gg82563_80003es2lan; 126 func->write_phy_reg = e1000_write_phy_reg_gg82563_80003es2lan; 127 128 /* This can only be done after all function pointers are setup. */ 129 ret_val = e1000_get_phy_id(hw); 130 131 /* Verify phy id */ 132 if (phy->id != GG82563_E_PHY_ID) { 133 ret_val = -E1000_ERR_PHY; 134 goto out; 135 } 136 137out: 138 return ret_val; 139} 140 141/** 142 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 143 * @hw: pointer to the HW structure 144 * 145 * This is a function pointer entry point called by the api module. 146 **/ 147STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 148{ 149 struct e1000_nvm_info *nvm = &hw->nvm; 150 struct e1000_functions *func = &hw->func; 151 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 152 u16 size; 153 154 DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); 155 156 nvm->opcode_bits = 8; 157 nvm->delay_usec = 1; 158 switch (nvm->override) { 159 case e1000_nvm_override_spi_large: 160 nvm->page_size = 32; 161 nvm->address_bits = 16; 162 break; 163 case e1000_nvm_override_spi_small: 164 nvm->page_size = 8; 165 nvm->address_bits = 8; 166 break; 167 default: 168 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 169 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 170 break; 171 } 172 173 nvm->type = e1000_nvm_eeprom_spi; 174 175 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 176 E1000_EECD_SIZE_EX_SHIFT); 177 178 /* 179 * Added to a constant, "size" becomes the left-shift value 180 * for setting word_size. 181 */ 182 size += NVM_WORD_SIZE_BASE_SHIFT; 183 184 /* EEPROM access above 16k is unsupported */ 185 if (size > 14) 186 size = 14; 187 nvm->word_size = 1 << size; 188 189 /* Function Pointers */ 190 func->acquire_nvm = e1000_acquire_nvm_80003es2lan; 191 func->read_nvm = e1000_read_nvm_eerd; 192 func->release_nvm = e1000_release_nvm_80003es2lan; 193 func->update_nvm = e1000_update_nvm_checksum_generic; 194 func->valid_led_default = e1000_valid_led_default_generic; 195 func->validate_nvm = e1000_validate_nvm_checksum_generic; 196 func->write_nvm = e1000_write_nvm_80003es2lan; 197 198 return E1000_SUCCESS; 199} 200 201/** 202 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 203 * @hw: pointer to the HW structure 204 * 205 * This is a function pointer entry point called by the api module. 206 **/ 207STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 208{ 209 struct e1000_mac_info *mac = &hw->mac; 210 struct e1000_functions *func = &hw->func; 211 s32 ret_val = E1000_SUCCESS; 212 213 DEBUGFUNC("e1000_init_mac_params_80003es2lan"); 214 215 /* Set media type */ 216 switch (hw->device_id) { 217 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 218 hw->phy.media_type = e1000_media_type_internal_serdes; 219 break; 220 default: 221 hw->phy.media_type = e1000_media_type_copper; 222 break; 223 } 224 225 /* Set mta register count */ 226 mac->mta_reg_count = 128; 227 /* Set rar entry count */ 228 mac->rar_entry_count = E1000_RAR_ENTRIES; 229 /* Set if part includes ASF firmware */ 230 mac->asf_firmware_present = TRUE; 231 /* Set if manageability features are enabled. */ 232 mac->arc_subsystem_valid = 233 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 234 ? TRUE : FALSE; 235 236 /* Function pointers */ 237 238 /* bus type/speed/width */ 239 func->get_bus_info = e1000_get_bus_info_pcie_generic; 240 /* reset */ 241 func->reset_hw = e1000_reset_hw_80003es2lan; 242 /* hw initialization */ 243 func->init_hw = e1000_init_hw_80003es2lan; 244 /* link setup */ 245 func->setup_link = e1000_setup_link_generic; 246 /* physical interface link setup */ 247 func->setup_physical_interface = 248 (hw->phy.media_type == e1000_media_type_copper) 249 ? e1000_setup_copper_link_80003es2lan 250 : e1000_setup_fiber_serdes_link_generic; 251 /* check for link */ 252 switch (hw->phy.media_type) { 253 case e1000_media_type_copper: 254 func->check_for_link = e1000_check_for_copper_link_generic; 255 break; 256 case e1000_media_type_fiber: 257 func->check_for_link = e1000_check_for_fiber_link_generic; 258 break; 259 case e1000_media_type_internal_serdes: 260 func->check_for_link = e1000_check_for_serdes_link_generic; 261 break; 262 default: 263 ret_val = -E1000_ERR_CONFIG; 264 goto out; 265 break; 266 } 267 /* check management mode */ 268 func->check_mng_mode = e1000_check_mng_mode_generic; 269 /* multicast address update */ 270 func->update_mc_addr_list = e1000_update_mc_addr_list_generic; 271 /* writing VFTA */ 272 func->write_vfta = e1000_write_vfta_generic; 273 /* clearing VFTA */ 274 func->clear_vfta = e1000_clear_vfta_generic; 275 /* setting MTA */ 276 func->mta_set = e1000_mta_set_generic; 277 /* blink LED */ 278 func->blink_led = e1000_blink_led_generic; 279 /* setup LED */ 280 func->setup_led = e1000_setup_led_generic; 281 /* cleanup LED */ 282 func->cleanup_led = e1000_cleanup_led_generic; 283 /* turn on/off LED */ 284 func->led_on = e1000_led_on_generic; 285 func->led_off = e1000_led_off_generic; 286 /* remove device */ 287 func->remove_device = e1000_remove_device_generic; 288 /* clear hardware counters */ 289 func->clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; 290 /* link info */ 291 func->get_link_up_info = e1000_get_link_up_info_80003es2lan; 292 293out: 294 return ret_val; 295} 296 297/** 298 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. 299 * @hw: pointer to the HW structure 300 * 301 * The only function explicitly called by the api module to initialize 302 * all function pointers and parameters. 303 **/ 304void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) 305{ 306 DEBUGFUNC("e1000_init_function_pointers_80003es2lan"); 307 308 hw->func.init_mac_params = e1000_init_mac_params_80003es2lan; 309 hw->func.init_nvm_params = e1000_init_nvm_params_80003es2lan; 310 hw->func.init_phy_params = e1000_init_phy_params_80003es2lan; 311} 312 313/** 314 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 315 * @hw: pointer to the HW structure 316 * 317 * A wrapper to acquire access rights to the correct PHY. This is a 318 * function pointer entry point called by the api module. 319 **/ 320STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 321{ 322 u16 mask; 323 324 DEBUGFUNC("e1000_acquire_phy_80003es2lan"); 325 326 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 327 328 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 329} 330 331/** 332 * e1000_release_phy_80003es2lan - Release rights to access PHY 333 * @hw: pointer to the HW structure 334 * 335 * A wrapper to release access rights to the correct PHY. This is a 336 * function pointer entry point called by the api module. 337 **/ 338STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw) 339{ 340 u16 mask; 341 342 DEBUGFUNC("e1000_release_phy_80003es2lan"); 343 344 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 345 e1000_release_swfw_sync_80003es2lan(hw, mask); 346} 347 348/** 349 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 350 * @hw: pointer to the HW structure 351 * 352 * Acquire the semaphore to access the EEPROM. This is a function 353 * pointer entry point called by the api module. 354 **/ 355STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 356{ 357 s32 ret_val; 358 359 DEBUGFUNC("e1000_acquire_nvm_80003es2lan"); 360 361 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 362 if (ret_val) 363 goto out; 364 365 ret_val = e1000_acquire_nvm_generic(hw); 366 367 if (ret_val) 368 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 369 370out: 371 return ret_val; 372} 373 374/** 375 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 376 * @hw: pointer to the HW structure 377 * 378 * Release the semaphore used to access the EEPROM. This is a 379 * function pointer entry point called by the api module. 380 **/ 381STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 382{ 383 DEBUGFUNC("e1000_release_nvm_80003es2lan"); 384 385 e1000_release_nvm_generic(hw); 386 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 387} 388 389/** 390 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore 391 * @hw: pointer to the HW structure 392 * @mask: specifies which semaphore to acquire 393 * 394 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 395 * will also specify which port we're acquiring the lock for. 396 **/ 397static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 398{ 399 u32 swfw_sync; 400 u32 swmask = mask; 401 u32 fwmask = mask << 16; 402 s32 ret_val = E1000_SUCCESS; 403 s32 i = 0, timeout = 200; 404 405 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan"); 406 407 while (i < timeout) { 408 if (e1000_get_hw_semaphore_generic(hw)) { 409 ret_val = -E1000_ERR_SWFW_SYNC; 410 goto out; 411 } 412 413 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 414 if (!(swfw_sync & (fwmask | swmask))) 415 break; 416 417 /* 418 * Firmware currently using resource (fwmask) 419 * or other software thread using resource (swmask) 420 */ 421 e1000_put_hw_semaphore_generic(hw); 422 msec_delay_irq(5); 423 i++; 424 } 425 426 if (i == timeout) { 427 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 428 ret_val = -E1000_ERR_SWFW_SYNC; 429 goto out; 430 } 431 432 swfw_sync |= swmask; 433 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 434 435 e1000_put_hw_semaphore_generic(hw); 436 437out: 438 return ret_val; 439} 440 441/** 442 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore 443 * @hw: pointer to the HW structure 444 * @mask: specifies which semaphore to acquire 445 * 446 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 447 * will also specify which port we're releasing the lock for. 448 **/ 449static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 450{ 451 u32 swfw_sync; 452 453 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan"); 454 455 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 456 /* Empty */ 457 458 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 459 swfw_sync &= ~mask; 460 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 461 462 e1000_put_hw_semaphore_generic(hw); 463} 464 465/** 466 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 467 * @hw: pointer to the HW structure 468 * @offset: offset of the register to read 469 * @data: pointer to the data returned from the operation 470 * 471 * Read the GG82563 PHY register. This is a function pointer entry 472 * point called by the api module. 473 **/ 474STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 475 u32 offset, u16 *data) 476{ 477 s32 ret_val; 478 u32 page_select; 479 u16 temp; 480 481 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan"); 482 483 /* Select Configuration Page */ 484 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 485 page_select = GG82563_PHY_PAGE_SELECT; 486 } else { 487 /* 488 * Use Alternative Page Select register to access 489 * registers 30 and 31 490 */ 491 page_select = GG82563_PHY_PAGE_SELECT_ALT; 492 } 493 494 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 495 ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); 496 if (ret_val) 497 goto out; 498 499 /* 500 * The "ready" bit in the MDIC register may be incorrectly set 501 * before the device has completed the "Page Select" MDI 502 * transaction. So we wait 200us after each MDI command... 503 */ 504 usec_delay(200); 505 506 /* ...and verify the command was successful. */ 507 ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp); 508 509 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 510 ret_val = -E1000_ERR_PHY; 511 goto out; 512 } 513 514 usec_delay(200); 515 516 ret_val = e1000_read_phy_reg_m88(hw, 517 MAX_PHY_REG_ADDRESS & offset, 518 data); 519 520 usec_delay(200); 521 522out: 523 return ret_val; 524} 525 526/** 527 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 528 * @hw: pointer to the HW structure 529 * @offset: offset of the register to read 530 * @data: value to write to the register 531 * 532 * Write to the GG82563 PHY register. This is a function pointer entry 533 * point called by the api module. 534 **/ 535STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 536 u32 offset, u16 data) 537{ 538 s32 ret_val; 539 u32 page_select; 540 u16 temp; 541 542 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan"); 543 544 /* Select Configuration Page */ 545 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 546 page_select = GG82563_PHY_PAGE_SELECT; 547 } else { 548 /* 549 * Use Alternative Page Select register to access 550 * registers 30 and 31 551 */ 552 page_select = GG82563_PHY_PAGE_SELECT_ALT; 553 } 554 555 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 556 ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); 557 if (ret_val) 558 goto out; 559 560 561 /* 562 * The "ready" bit in the MDIC register may be incorrectly set 563 * before the device has completed the "Page Select" MDI 564 * transaction. So we wait 200us after each MDI command... 565 */ 566 usec_delay(200); 567 568 /* ...and verify the command was successful. */ 569 ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp); 570 571 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 572 ret_val = -E1000_ERR_PHY; 573 goto out; 574 } 575 576 usec_delay(200); 577 578 ret_val = e1000_write_phy_reg_m88(hw, 579 MAX_PHY_REG_ADDRESS & offset, 580 data); 581 582 usec_delay(200); 583 584out: 585 return ret_val; 586} 587 588/** 589 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 590 * @hw: pointer to the HW structure 591 * @offset: offset of the register to read 592 * @words: number of words to write 593 * @data: buffer of data to write to the NVM 594 * 595 * Write "words" of data to the ESB2 NVM. This is a function 596 * pointer entry point called by the api module. 597 **/ 598STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 599 u16 words, u16 *data) 600{ 601 DEBUGFUNC("e1000_write_nvm_80003es2lan"); 602 603 return e1000_write_nvm_spi(hw, offset, words, data); 604} 605 606/** 607 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 608 * @hw: pointer to the HW structure 609 * 610 * Wait a specific amount of time for manageability processes to complete. 611 * This is a function pointer entry point called by the phy module. 612 **/ 613STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 614{ 615 s32 timeout = PHY_CFG_TIMEOUT; 616 s32 ret_val = E1000_SUCCESS; 617 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 618 619 DEBUGFUNC("e1000_get_cfg_done_80003es2lan"); 620 621 if (hw->bus.func == 1) 622 mask = E1000_NVM_CFG_DONE_PORT_1; 623 624 while (timeout) { 625 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 626 break; 627 msec_delay(1); 628 timeout--; 629 } 630 if (!timeout) { 631 DEBUGOUT("MNG configuration cycle has not completed.\n"); 632 ret_val = -E1000_ERR_RESET; 633 goto out; 634 } 635 636out: 637 return ret_val; 638} 639 640/** 641 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 642 * @hw: pointer to the HW structure 643 * 644 * Force the speed and duplex settings onto the PHY. This is a 645 * function pointer entry point called by the phy module. 646 **/ 647STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 648{ 649 s32 ret_val; 650 u16 phy_data; 651 bool link; 652 653 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan"); 654 655 /* 656 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 657 * forced whenever speed and duplex are forced. 658 */ 659 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 660 if (ret_val) 661 goto out; 662 663 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 664 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 665 if (ret_val) 666 goto out; 667 668 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); 669 670 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data); 671 if (ret_val) 672 goto out; 673 674 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 675 676 /* Reset the phy to commit changes. */ 677 phy_data |= MII_CR_RESET; 678 679 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data); 680 if (ret_val) 681 goto out; 682 683 usec_delay(1); 684 685 if (hw->phy.autoneg_wait_to_complete) { 686 DEBUGOUT("Waiting for forced speed/duplex link " 687 "on GG82563 phy.\n"); 688 689 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 690 100000, &link); 691 if (ret_val) 692 goto out; 693 694 if (!link) { 695 /* 696 * We didn't get link. 697 * Reset the DSP and cross our fingers. 698 */ 699 ret_val = e1000_phy_reset_dsp_generic(hw); 700 if (ret_val) 701 goto out; 702 } 703 704 /* Try once more */ 705 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 706 100000, &link); 707 if (ret_val) 708 goto out; 709 } 710 711 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 712 if (ret_val) 713 goto out; 714 715 /* 716 * Resetting the phy means we need to verify the TX_CLK corresponds 717 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 718 */ 719 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 720 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 721 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 722 else 723 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 724 725 /* 726 * In addition, we must re-enable CRS on Tx for both half and full 727 * duplex. 728 */ 729 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 730 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); 731 732out: 733 return ret_val; 734} 735 736/** 737 * e1000_get_cable_length_80003es2lan - Set approximate cable length 738 * @hw: pointer to the HW structure 739 * 740 * Find the approximate cable length as measured by the GG82563 PHY. 741 * This is a function pointer entry point called by the phy module. 742 **/ 743STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 744{ 745 struct e1000_phy_info *phy = &hw->phy; 746 s32 ret_val; 747 u16 phy_data, index; 748 749 DEBUGFUNC("e1000_get_cable_length_80003es2lan"); 750 751 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 752 if (ret_val) 753 goto out; 754 755 index = phy_data & GG82563_DSPD_CABLE_LENGTH; 756 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 757 phy->max_cable_length = e1000_gg82563_cable_length_table[index+5]; 758 759 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 760 761out: 762 return ret_val; 763} 764 765/** 766 * e1000_get_link_up_info_80003es2lan - Report speed and duplex 767 * @hw: pointer to the HW structure 768 * @speed: pointer to speed buffer 769 * @duplex: pointer to duplex buffer 770 * 771 * Retrieve the current speed and duplex configuration. 772 * This is a function pointer entry point called by the api module. 773 **/ 774STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 775 u16 *duplex) 776{ 777 s32 ret_val; 778 779 DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); 780 781 if (hw->phy.media_type == e1000_media_type_copper) { 782 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, 783 speed, 784 duplex); 785 if (ret_val) 786 goto out; 787 if (*speed == SPEED_1000) 788 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 789 else 790 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, 791 *duplex); 792 } else { 793 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, 794 speed, 795 duplex); 796 } 797 798out: 799 return ret_val; 800} 801 802/** 803 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 804 * @hw: pointer to the HW structure 805 * 806 * Perform a global reset to the ESB2 controller. 807 * This is a function pointer entry point called by the api module. 808 **/ 809STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 810{ 811 u32 ctrl, icr; 812 s32 ret_val; 813 814 DEBUGFUNC("e1000_reset_hw_80003es2lan"); 815 816 /* 817 * Prevent the PCI-E bus from sticking if there is no TLP connection 818 * on the last TLP read/write transaction when MAC is reset. 819 */ 820 ret_val = e1000_disable_pcie_master_generic(hw); 821 if (ret_val) { 822 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 823 } 824 825 DEBUGOUT("Masking off all interrupts\n"); 826 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 827 828 E1000_WRITE_REG(hw, E1000_RCTL, 0); 829 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 830 E1000_WRITE_FLUSH(hw); 831 832 msec_delay(10); 833 834 ctrl = E1000_READ_REG(hw, E1000_CTRL); 835 836 DEBUGOUT("Issuing a global reset to MAC\n"); 837 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 838 839 ret_val = e1000_get_auto_rd_done_generic(hw); 840 if (ret_val) 841 /* We don't want to continue accessing MAC registers. */ 842 goto out; 843 844 /* Clear any pending interrupt events. */ 845 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 846 icr = E1000_READ_REG(hw, E1000_ICR); 847 848out: 849 return ret_val; 850} 851 852/** 853 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 854 * @hw: pointer to the HW structure 855 * 856 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 857 * This is a function pointer entry point called by the api module. 858 **/ 859STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 860{ 861 struct e1000_mac_info *mac = &hw->mac; 862 u32 reg_data; 863 s32 ret_val; 864 u16 i; 865 866 DEBUGFUNC("e1000_init_hw_80003es2lan"); 867 868 e1000_initialize_hw_bits_80003es2lan(hw); 869 870 /* Initialize identification LED */ 871 ret_val = e1000_id_led_init_generic(hw); 872 if (ret_val) { 873 DEBUGOUT("Error initializing identification LED\n"); 874 /* This is not fatal and we should not stop init due to this */ 875 } 876 877 /* Disabling VLAN filtering */ 878 DEBUGOUT("Initializing the IEEE VLAN\n"); 879 e1000_clear_vfta(hw); 880 881 /* Setup the receive address. */ 882 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 883 884 /* Zero out the Multicast HASH table */ 885 DEBUGOUT("Zeroing the MTA\n"); 886 for (i = 0; i < mac->mta_reg_count; i++) 887 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 888 889 /* Setup link and flow control */ 890 ret_val = e1000_setup_link(hw); 891 892 /* Set the transmit descriptor write-back policy */ 893 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 894 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 895 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 896 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 897 898 /* ...for both queues. */ 899 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 900 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 901 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 902 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 903 904 /* Enable retransmit on late collisions */ 905 reg_data = E1000_READ_REG(hw, E1000_TCTL); 906 reg_data |= E1000_TCTL_RTLC; 907 E1000_WRITE_REG(hw, E1000_TCTL, reg_data); 908 909 /* Configure Gigabit Carry Extend Padding */ 910 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); 911 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 912 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 913 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); 914 915 /* Configure Transmit Inter-Packet Gap */ 916 reg_data = E1000_READ_REG(hw, E1000_TIPG); 917 reg_data &= ~E1000_TIPG_IPGT_MASK; 918 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 919 E1000_WRITE_REG(hw, E1000_TIPG, reg_data); 920 921 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 922 reg_data &= ~0x00100000; 923 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 924 925 /* 926 * Clear all of the statistics registers (clear on read). It is 927 * important that we do this after we have tried to establish link 928 * because the symbol error count will increment wildly if there 929 * is no link. 930 */ 931 e1000_clear_hw_cntrs_80003es2lan(hw); 932 933 return ret_val; 934} 935 936/** 937 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 938 * @hw: pointer to the HW structure 939 * 940 * Initializes required hardware-dependent bits needed for normal operation. 941 **/ 942static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 943{ 944 u32 reg; 945 946 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan"); 947 948 if (hw->mac.disable_hw_init_bits) 949 goto out; 950 951 /* Transmit Descriptor Control 0 */ 952 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 953 reg |= (1 << 22); 954 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 955 956 /* Transmit Descriptor Control 1 */ 957 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 958 reg |= (1 << 22); 959 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 960 961 /* Transmit Arbitration Control 0 */ 962 reg = E1000_READ_REG(hw, E1000_TARC(0)); 963 reg &= ~(0xF << 27); /* 30:27 */ 964 if (hw->phy.media_type != e1000_media_type_copper) 965 reg &= ~(1 << 20); 966 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 967 968 /* Transmit Arbitration Control 1 */ 969 reg = E1000_READ_REG(hw, E1000_TARC(1)); 970 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 971 reg &= ~(1 << 28); 972 else 973 reg |= (1 << 28); 974 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 975 976out: 977 return; 978} 979 980/** 981 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 982 * @hw: pointer to the HW structure 983 * 984 * Setup some GG82563 PHY registers for obtaining link 985 **/ 986static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 987{ 988 struct e1000_phy_info *phy = &hw->phy; 989 s32 ret_val; 990 u32 ctrl_ext; 991 u16 data; 992 993 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); 994 995 if (!phy->reset_disable) { 996 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 997 &data); 998 if (ret_val) 999 goto out; 1000 1001 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1002 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 1003 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 1004 1005 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1006 data); 1007 if (ret_val) 1008 goto out; 1009 1010 /* 1011 * Options: 1012 * MDI/MDI-X = 0 (default) 1013 * 0 - Auto for all speeds 1014 * 1 - MDI mode 1015 * 2 - MDI-X mode 1016 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1017 */ 1018 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &data); 1019 if (ret_val) 1020 goto out; 1021 1022 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1023 1024 switch (phy->mdix) { 1025 case 1: 1026 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1027 break; 1028 case 2: 1029 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1030 break; 1031 case 0: 1032 default: 1033 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1034 break; 1035 } 1036 1037 /* 1038 * Options: 1039 * disable_polarity_correction = 0 (default) 1040 * Automatic Correction for Reversed Cable Polarity 1041 * 0 - Disabled 1042 * 1 - Enabled 1043 */ 1044 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1045 if (phy->disable_polarity_correction) 1046 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1047 1048 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, data); 1049 if (ret_val) 1050 goto out; 1051 1052 /* SW Reset the PHY so all changes take effect */ 1053 ret_val = e1000_phy_commit(hw); 1054 if (ret_val) { 1055 DEBUGOUT("Error Resetting the PHY\n"); 1056 goto out; 1057 } 1058 1059 } 1060 1061 /* Bypass Rx and Tx FIFO's */ 1062 ret_val = e1000_write_kmrn_reg(hw, 1063 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, 1064 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 1065 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 1066 if (ret_val) 1067 goto out; 1068 1069 ret_val = e1000_read_kmrn_reg(hw, 1070 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, 1071 &data); 1072 if (ret_val) 1073 goto out; 1074 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; 1075 ret_val = e1000_write_kmrn_reg(hw, 1076 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, 1077 data); 1078 if (ret_val) 1079 goto out; 1080 1081 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); 1082 if (ret_val) 1083 goto out; 1084 1085 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1086 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); 1087 if (ret_val) 1088 goto out; 1089 1090 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1091 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 1092 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1093 1094 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 1095 if (ret_val) 1096 goto out; 1097 1098 /* 1099 * Do not init these registers when the HW is in IAMT mode, since the 1100 * firmware will have already initialized them. We only initialize 1101 * them if the HW is not in IAMT mode. 1102 */ 1103 if (!(e1000_check_mng_mode(hw))) { 1104 /* Enable Electrical Idle on the PHY */ 1105 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1106 ret_val = e1000_write_phy_reg(hw, 1107 GG82563_PHY_PWR_MGMT_CTRL, 1108 data); 1109 if (ret_val) 1110 goto out; 1111 1112 ret_val = e1000_read_phy_reg(hw, 1113 GG82563_PHY_KMRN_MODE_CTRL, 1114 &data); 1115 if (ret_val) 1116 goto out; 1117 1118 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1119 ret_val = e1000_write_phy_reg(hw, 1120 GG82563_PHY_KMRN_MODE_CTRL, 1121 data); 1122 1123 if (ret_val) 1124 goto out; 1125 } 1126 1127 /* 1128 * Workaround: Disable padding in Kumeran interface in the MAC 1129 * and in the PHY to avoid CRC errors. 1130 */ 1131 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, &data); 1132 if (ret_val) 1133 goto out; 1134 1135 data |= GG82563_ICR_DIS_PADDING; 1136 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, data); 1137 if (ret_val) 1138 goto out; 1139 1140out: 1141 return ret_val; 1142} 1143 1144/** 1145 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1146 * @hw: pointer to the HW structure 1147 * 1148 * Essentially a wrapper for setting up all things "copper" related. 1149 * This is a function pointer entry point called by the mac module. 1150 **/ 1151STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1152{ 1153 u32 ctrl; 1154 s32 ret_val; 1155 u16 reg_data; 1156 1157 DEBUGFUNC("e1000_setup_copper_link_80003es2lan"); 1158 1159 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1160 ctrl |= E1000_CTRL_SLU; 1161 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1162 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1163 1164 /* 1165 * Set the mac to wait the maximum time between each 1166 * iteration and increase the max iterations when 1167 * polling the phy; this fixes erroneous timeouts at 10Mbps. 1168 */ 1169 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 1170 if (ret_val) 1171 goto out; 1172 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); 1173 if (ret_val) 1174 goto out; 1175 reg_data |= 0x3F; 1176 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); 1177 if (ret_val) 1178 goto out; 1179 ret_val = e1000_read_kmrn_reg(hw, 1180 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1181 ®_data); 1182 if (ret_val) 1183 goto out; 1184 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1185 ret_val = e1000_write_kmrn_reg(hw, 1186 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1187 reg_data); 1188 if (ret_val) 1189 goto out; 1190 1191 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1192 if (ret_val) 1193 goto out; 1194 1195 ret_val = e1000_setup_copper_link_generic(hw); 1196 1197out: 1198 return ret_val; 1199} 1200 1201/** 1202 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1203 * @hw: pointer to the HW structure 1204 * @duplex: current duplex setting 1205 * 1206 * Configure the KMRN interface by applying last minute quirks for 1207 * 10/100 operation. 1208 **/ 1209static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1210{ 1211 s32 ret_val = E1000_SUCCESS; 1212 u32 tipg; 1213 u32 i = 0; 1214 u16 reg_data, reg_data2; 1215 1216 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 1217 1218 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1219 ret_val = e1000_write_kmrn_reg(hw, 1220 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1221 reg_data); 1222 if (ret_val) 1223 goto out; 1224 1225 /* Configure Transmit Inter-Packet Gap */ 1226 tipg = E1000_READ_REG(hw, E1000_TIPG); 1227 tipg &= ~E1000_TIPG_IPGT_MASK; 1228 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1229 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1230 1231 1232 do { 1233 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1234 ®_data); 1235 if (ret_val) 1236 goto out; 1237 1238 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1239 ®_data2); 1240 if (ret_val) 1241 goto out; 1242 i++; 1243 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1244 1245 if (duplex == HALF_DUPLEX) 1246 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1247 else 1248 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1249 1250 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1251 1252out: 1253 return ret_val; 1254} 1255 1256/** 1257 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1258 * @hw: pointer to the HW structure 1259 * 1260 * Configure the KMRN interface by applying last minute quirks for 1261 * gigabit operation. 1262 **/ 1263static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1264{ 1265 s32 ret_val = E1000_SUCCESS; 1266 u16 reg_data, reg_data2; 1267 u32 tipg; 1268 u32 i = 0; 1269 1270 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 1271 1272 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1273 ret_val = e1000_write_kmrn_reg(hw, 1274 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1275 reg_data); 1276 if (ret_val) 1277 goto out; 1278 1279 /* Configure Transmit Inter-Packet Gap */ 1280 tipg = E1000_READ_REG(hw, E1000_TIPG); 1281 tipg &= ~E1000_TIPG_IPGT_MASK; 1282 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1283 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1284 1285 1286 do { 1287 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1288 ®_data); 1289 if (ret_val) 1290 goto out; 1291 1292 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1293 ®_data2); 1294 if (ret_val) 1295 goto out; 1296 i++; 1297 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1298 1299 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1300 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1301 1302out: 1303 return ret_val; 1304} 1305 1306/** 1307 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down 1308 * @hw: pointer to the HW structure 1309 * 1310 * In the case of a PHY power down to save power, or to turn off link during a 1311 * driver unload, or wake on lan is not enabled, remove the link. 1312 **/ 1313STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) 1314{ 1315 /* If the management interface is not enabled, then power down */ 1316 if (!(e1000_check_mng_mode(hw) || e1000_check_reset_block(hw))) 1317 e1000_power_down_phy_copper(hw); 1318 1319 return; 1320} 1321 1322/** 1323 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1324 * @hw: pointer to the HW structure 1325 * 1326 * Clears the hardware counters by reading the counter registers. 1327 **/ 1328STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1329{ 1330 volatile u32 temp; 1331 1332 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan"); 1333 1334 e1000_clear_hw_cntrs_base_generic(hw); 1335 1336 temp = E1000_READ_REG(hw, E1000_PRC64); 1337 temp = E1000_READ_REG(hw, E1000_PRC127); 1338 temp = E1000_READ_REG(hw, E1000_PRC255); 1339 temp = E1000_READ_REG(hw, E1000_PRC511); 1340 temp = E1000_READ_REG(hw, E1000_PRC1023); 1341 temp = E1000_READ_REG(hw, E1000_PRC1522); 1342 temp = E1000_READ_REG(hw, E1000_PTC64); 1343 temp = E1000_READ_REG(hw, E1000_PTC127); 1344 temp = E1000_READ_REG(hw, E1000_PTC255); 1345 temp = E1000_READ_REG(hw, E1000_PTC511); 1346 temp = E1000_READ_REG(hw, E1000_PTC1023); 1347 temp = E1000_READ_REG(hw, E1000_PTC1522); 1348 1349 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1350 temp = E1000_READ_REG(hw, E1000_RXERRC); 1351 temp = E1000_READ_REG(hw, E1000_TNCRS); 1352 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1353 temp = E1000_READ_REG(hw, E1000_TSCTC); 1354 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1355 1356 temp = E1000_READ_REG(hw, E1000_MGTPRC); 1357 temp = E1000_READ_REG(hw, E1000_MGTPDC); 1358 temp = E1000_READ_REG(hw, E1000_MGTPTC); 1359 1360 temp = E1000_READ_REG(hw, E1000_IAC); 1361 temp = E1000_READ_REG(hw, E1000_ICRXOC); 1362 1363 temp = E1000_READ_REG(hw, E1000_ICRXPTC); 1364 temp = E1000_READ_REG(hw, E1000_ICRXATC); 1365 temp = E1000_READ_REG(hw, E1000_ICTXPTC); 1366 temp = E1000_READ_REG(hw, E1000_ICTXATC); 1367 temp = E1000_READ_REG(hw, E1000_ICTXQEC); 1368 temp = E1000_READ_REG(hw, E1000_ICTXQMTC); 1369 temp = E1000_READ_REG(hw, E1000_ICRXDMTC); 1370} 1371