e1000_80003es2lan.c revision 169589
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/*$FreeBSD: head/sys/dev/em/e1000_80003es2lan.c 169589 2007-05-16 00:14:23Z jfv $*/ 34 35/* e1000_80003es2lan 36 */ 37 38#include "e1000_api.h" 39#include "e1000_80003es2lan.h" 40 41void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw); 42 43STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw); 44STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw); 45STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw); 46STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); 47STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw); 48STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); 49STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); 50STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 51 u32 offset, 52 u16 *data); 53STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 54 u32 offset, 55 u16 data); 56STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 57 u16 words, u16 *data); 58STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); 59STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); 60STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); 61STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 62 u16 *duplex); 63STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); 64STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); 65STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 66STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 67static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 68static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 69static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 70static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw); 71static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 72static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 73 74/* A table for the GG82563 cable length where the range is defined 75 * with a lower bound at "index" and the upper bound at 76 * "index + 5". 77 */ 78static const 79u16 e1000_gg82563_cable_length_table[] = 80 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; 81#define GG82563_CABLE_LENGTH_TABLE_SIZE \ 82 (sizeof(e1000_gg82563_cable_length_table) / \ 83 sizeof(e1000_gg82563_cable_length_table[0])) 84 85/** 86 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 87 * @hw: pointer to the HW structure 88 * 89 * This is a function pointer entry point called by the api module. 90 **/ 91STATIC s32 92e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 93{ 94 struct e1000_phy_info *phy = &hw->phy; 95 struct e1000_functions *func = &hw->func; 96 s32 ret_val = E1000_SUCCESS; 97 98 DEBUGFUNC("e1000_init_phy_params_80003es2lan"); 99 100 if (hw->media_type != e1000_media_type_copper) { 101 phy->type = e1000_phy_none; 102 goto out; 103 } 104 105 phy->addr = 1; 106 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 107 phy->reset_delay_us = 100; 108 phy->type = e1000_phy_gg82563; 109 110 func->acquire_phy = e1000_acquire_phy_80003es2lan; 111 func->check_polarity = e1000_check_polarity_m88; 112 func->check_reset_block = e1000_check_reset_block_generic; 113 func->commit_phy = e1000_phy_sw_reset_generic; 114 func->get_cfg_done = e1000_get_cfg_done_80003es2lan; 115 func->get_phy_info = e1000_get_phy_info_m88; 116 func->release_phy = e1000_release_phy_80003es2lan; 117 func->reset_phy = e1000_phy_hw_reset_generic; 118 func->set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 119 120 func->force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; 121 func->get_cable_length = e1000_get_cable_length_80003es2lan; 122 func->read_phy_reg = e1000_read_phy_reg_gg82563_80003es2lan; 123 func->write_phy_reg = e1000_write_phy_reg_gg82563_80003es2lan; 124 125 /* This can only be done after all function pointers are setup. */ 126 ret_val = e1000_get_phy_id(hw); 127 128 /* Verify phy id */ 129 if (phy->id != GG82563_E_PHY_ID) { 130 ret_val = -E1000_ERR_PHY; 131 goto out; 132 } 133 134out: 135 return ret_val; 136} 137 138/** 139 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 140 * @hw: pointer to the HW structure 141 * 142 * This is a function pointer entry point called by the api module. 143 **/ 144STATIC s32 145e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 146{ 147 struct e1000_nvm_info *nvm = &hw->nvm; 148 struct e1000_functions *func = &hw->func; 149 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 150 u16 size; 151 152 DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); 153 154 nvm->opcode_bits = 8; 155 nvm->delay_usec = 1; 156 switch (nvm->override) { 157 case e1000_nvm_override_spi_large: 158 nvm->page_size = 32; 159 nvm->address_bits = 16; 160 break; 161 case e1000_nvm_override_spi_small: 162 nvm->page_size = 8; 163 nvm->address_bits = 8; 164 break; 165 default: 166 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 167 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 168 break; 169 } 170 171 nvm->type = e1000_nvm_eeprom_spi; 172 173 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 174 E1000_EECD_SIZE_EX_SHIFT); 175 176 /* Added to a constant, "size" becomes the left-shift value 177 * for setting word_size. 178 */ 179 size += NVM_WORD_SIZE_BASE_SHIFT; 180 nvm->word_size = 1 << size; 181 182 /* Function Pointers */ 183 func->acquire_nvm = e1000_acquire_nvm_80003es2lan; 184 func->read_nvm = e1000_read_nvm_eerd; 185 func->release_nvm = e1000_release_nvm_80003es2lan; 186 func->update_nvm = e1000_update_nvm_checksum_generic; 187 func->valid_led_default = e1000_valid_led_default_generic; 188 func->validate_nvm = e1000_validate_nvm_checksum_generic; 189 func->write_nvm = e1000_write_nvm_80003es2lan; 190 191 return E1000_SUCCESS; 192} 193 194/** 195 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 196 * @hw: pointer to the HW structure 197 * 198 * This is a function pointer entry point called by the api module. 199 **/ 200STATIC s32 201e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 202{ 203 struct e1000_mac_info *mac = &hw->mac; 204 struct e1000_functions *func = &hw->func; 205 s32 ret_val = E1000_SUCCESS; 206 207 DEBUGFUNC("e1000_init_mac_params_80003es2lan"); 208 209 /* Set media type */ 210 switch (hw->device_id) { 211 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 212 hw->media_type = e1000_media_type_internal_serdes; 213 break; 214 default: 215 hw->media_type = e1000_media_type_copper; 216 break; 217 } 218 219 /* Set mta register count */ 220 mac->mta_reg_count = 128; 221 /* Set rar entry count */ 222 mac->rar_entry_count = E1000_RAR_ENTRIES; 223 /* Set if part includes ASF firmware */ 224 mac->asf_firmware_present = TRUE; 225 /* Set if manageability features are enabled. */ 226 mac->arc_subsystem_valid = 227 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 228 ? TRUE : FALSE; 229 230 /* Function pointers */ 231 232 /* bus type/speed/width */ 233 func->get_bus_info = e1000_get_bus_info_pcie_generic; 234 /* reset */ 235 func->reset_hw = e1000_reset_hw_80003es2lan; 236 /* hw initialization */ 237 func->init_hw = e1000_init_hw_80003es2lan; 238 /* link setup */ 239 func->setup_link = e1000_setup_link_generic; 240 /* physical interface link setup */ 241 func->setup_physical_interface = 242 (hw->media_type == e1000_media_type_copper) 243 ? e1000_setup_copper_link_80003es2lan 244 : e1000_setup_fiber_serdes_link_generic; 245 /* check for link */ 246 switch (hw->media_type) { 247 case e1000_media_type_copper: 248 func->check_for_link = e1000_check_for_copper_link_generic; 249 break; 250 case e1000_media_type_fiber: 251 func->check_for_link = e1000_check_for_fiber_link_generic; 252 break; 253 case e1000_media_type_internal_serdes: 254 func->check_for_link = e1000_check_for_serdes_link_generic; 255 break; 256 default: 257 ret_val = -E1000_ERR_CONFIG; 258 goto out; 259 break; 260 } 261 /* check management mode */ 262 func->check_mng_mode = e1000_check_mng_mode_generic; 263 /* multicast address update */ 264 func->mc_addr_list_update = e1000_mc_addr_list_update_generic; 265 /* writing VFTA */ 266 func->write_vfta = e1000_write_vfta_generic; 267 /* clearing VFTA */ 268 func->clear_vfta = e1000_clear_vfta_generic; 269 /* setting MTA */ 270 func->mta_set = e1000_mta_set_generic; 271 /* blink LED */ 272 func->blink_led = e1000_blink_led_generic; 273 /* setup LED */ 274 func->setup_led = e1000_setup_led_generic; 275 /* cleanup LED */ 276 func->cleanup_led = e1000_cleanup_led_generic; 277 /* turn on/off LED */ 278 func->led_on = e1000_led_on_generic; 279 func->led_off = e1000_led_off_generic; 280 /* remove device */ 281 func->remove_device = e1000_remove_device_generic; 282 /* clear hardware counters */ 283 func->clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; 284 /* link info */ 285 func->get_link_up_info = e1000_get_link_up_info_80003es2lan; 286 287out: 288 return ret_val; 289} 290 291/** 292 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. 293 * @hw: pointer to the HW structure 294 * 295 * The only function explicitly called by the api module to initialize 296 * all function pointers and parameters. 297 **/ 298void 299e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) 300{ 301 DEBUGFUNC("e1000_init_function_pointers_80003es2lan"); 302 303 hw->func.init_mac_params = e1000_init_mac_params_80003es2lan; 304 hw->func.init_nvm_params = e1000_init_nvm_params_80003es2lan; 305 hw->func.init_phy_params = e1000_init_phy_params_80003es2lan; 306} 307 308/** 309 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 310 * @hw: pointer to the HW structure 311 * 312 * A wrapper to acquire access rights to the correct PHY. This is a 313 * function pointer entry point called by the api module. 314 **/ 315STATIC s32 316e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 317{ 318 u16 mask; 319 320 DEBUGFUNC("e1000_acquire_phy_80003es2lan"); 321 322 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 323 324 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 325} 326 327/** 328 * e1000_release_phy_80003es2lan - Release rights to access PHY 329 * @hw: pointer to the HW structure 330 * 331 * A wrapper to release access rights to the correct PHY. This is a 332 * function pointer entry point called by the api module. 333 **/ 334STATIC void 335e1000_release_phy_80003es2lan(struct e1000_hw *hw) 336{ 337 u16 mask; 338 339 DEBUGFUNC("e1000_release_phy_80003es2lan"); 340 341 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 342 e1000_release_swfw_sync_80003es2lan(hw, mask); 343} 344 345/** 346 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 347 * @hw: pointer to the HW structure 348 * 349 * Acquire the semaphore to access the EEPROM. This is a function 350 * pointer entry point called by the api module. 351 **/ 352STATIC s32 353e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 354{ 355 s32 ret_val; 356 357 DEBUGFUNC("e1000_acquire_nvm_80003es2lan"); 358 359 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 360 if (ret_val) 361 goto out; 362 363 ret_val = e1000_acquire_nvm_generic(hw); 364 365 if (ret_val) 366 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 367 368out: 369 return ret_val; 370} 371 372/** 373 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 374 * @hw: pointer to the HW structure 375 * 376 * Release the semaphore used to access the EEPROM. This is a 377 * function pointer entry point called by the api module. 378 **/ 379STATIC void 380e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 381{ 382 DEBUGFUNC("e1000_release_nvm_80003es2lan"); 383 384 e1000_release_nvm_generic(hw); 385 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 386} 387 388/** 389 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore 390 * @hw: pointer to the HW structure 391 * @mask: specifies which semaphore to acquire 392 * 393 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 394 * will also specify which port we're acquiring the lock for. 395 **/ 396static s32 397e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 398{ 399 u32 swfw_sync; 400 u32 swmask = mask; 401 u32 fwmask = mask << 16; 402 s32 ret_val = E1000_SUCCESS; 403 s32 i = 0, timeout = 200; 404 405 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan"); 406 407 while (i < timeout) { 408 if (e1000_get_hw_semaphore_generic(hw)) { 409 ret_val = -E1000_ERR_SWFW_SYNC; 410 goto out; 411 } 412 413 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 414 if (!(swfw_sync & (fwmask | swmask))) 415 break; 416 417 /* Firmware currently using resource (fwmask) 418 * or other software thread using resource (swmask) */ 419 e1000_put_hw_semaphore_generic(hw); 420 msec_delay_irq(5); 421 i++; 422 } 423 424 if (i == timeout) { 425 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 426 ret_val = -E1000_ERR_SWFW_SYNC; 427 goto out; 428 } 429 430 swfw_sync |= swmask; 431 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 432 433 e1000_put_hw_semaphore_generic(hw); 434 435out: 436 return ret_val; 437} 438 439/** 440 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore 441 * @hw: pointer to the HW structure 442 * @mask: specifies which semaphore to acquire 443 * 444 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 445 * will also specify which port we're releasing the lock for. 446 **/ 447static void 448e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 449{ 450 u32 swfw_sync; 451 452 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan"); 453 454 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 455 /* Empty */ 456 457 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 458 swfw_sync &= ~mask; 459 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 460 461 e1000_put_hw_semaphore_generic(hw); 462} 463 464/** 465 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 466 * @hw: pointer to the HW structure 467 * @offset: offset of the register to read 468 * @data: pointer to the data returned from the operation 469 * 470 * Read the GG82563 PHY register. This is a function pointer entry 471 * point called by the api module. 472 **/ 473STATIC s32 474e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, u32 offset, 475 u16 *data) 476{ 477 s32 ret_val; 478 u32 page_select; 479 u16 temp; 480 481 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan"); 482 483 /* Select Configuration Page */ 484 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) 485 page_select = GG82563_PHY_PAGE_SELECT; 486 else { 487 /* Use Alternative Page Select register to access 488 * registers 30 and 31 489 */ 490 page_select = GG82563_PHY_PAGE_SELECT_ALT; 491 } 492 493 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 494 ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); 495 if (ret_val) 496 goto out; 497 498 /* The "ready" bit in the MDIC register may be incorrectly set 499 * before the device has completed the "Page Select" MDI 500 * transaction. So we wait 200us after each MDI command... 501 */ 502 usec_delay(200); 503 504 /* ...and verify the command was successful. */ 505 ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp); 506 507 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 508 ret_val = -E1000_ERR_PHY; 509 goto out; 510 } 511 512 usec_delay(200); 513 514 ret_val = e1000_read_phy_reg_m88(hw, 515 MAX_PHY_REG_ADDRESS & offset, 516 data); 517 518 usec_delay(200); 519 520out: 521 return ret_val; 522} 523 524/** 525 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 526 * @hw: pointer to the HW structure 527 * @offset: offset of the register to read 528 * @data: value to write to the register 529 * 530 * Write to the GG82563 PHY register. This is a function pointer entry 531 * point called by the api module. 532 **/ 533STATIC s32 534e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, u32 offset, 535 u16 data) 536{ 537 s32 ret_val; 538 u32 page_select; 539 u16 temp; 540 541 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan"); 542 543 /* Select Configuration Page */ 544 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) 545 page_select = GG82563_PHY_PAGE_SELECT; 546 else { 547 /* Use Alternative Page Select register to access 548 * registers 30 and 31 549 */ 550 page_select = GG82563_PHY_PAGE_SELECT_ALT; 551 } 552 553 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 554 ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); 555 if (ret_val) 556 goto out; 557 558 559 /* The "ready" bit in the MDIC register may be incorrectly set 560 * before the device has completed the "Page Select" MDI 561 * transaction. So we wait 200us after each MDI command... 562 */ 563 usec_delay(200); 564 565 /* ...and verify the command was successful. */ 566 ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp); 567 568 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 569 ret_val = -E1000_ERR_PHY; 570 goto out; 571 } 572 573 usec_delay(200); 574 575 ret_val = e1000_write_phy_reg_m88(hw, 576 MAX_PHY_REG_ADDRESS & offset, 577 data); 578 579 usec_delay(200); 580 581out: 582 return ret_val; 583} 584 585/** 586 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 587 * @hw: pointer to the HW structure 588 * @offset: offset of the register to read 589 * @words: number of words to write 590 * @data: buffer of data to write to the NVM 591 * 592 * Write "words" of data to the ESB2 NVM. This is a function 593 * pointer entry point called by the api module. 594 **/ 595STATIC s32 596e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 597 u16 words, u16 *data) 598{ 599 DEBUGFUNC("e1000_write_nvm_80003es2lan"); 600 601 return e1000_write_nvm_spi(hw, offset, words, data); 602} 603 604/** 605 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 606 * @hw: pointer to the HW structure 607 * 608 * Wait a specific amount of time for manageability processes to complete. 609 * This is a function pointer entry point called by the phy module. 610 **/ 611STATIC s32 612e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 613{ 614 s32 timeout = PHY_CFG_TIMEOUT; 615 s32 ret_val = E1000_SUCCESS; 616 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 617 618 DEBUGFUNC("e1000_get_cfg_done_80003es2lan"); 619 620 if (hw->bus.func == 1) 621 mask = E1000_NVM_CFG_DONE_PORT_1; 622 623 while (timeout) { 624 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 625 break; 626 msec_delay(1); 627 timeout--; 628 } 629 if (!timeout) { 630 DEBUGOUT("MNG configuration cycle has not completed.\n"); 631 ret_val = -E1000_ERR_RESET; 632 goto out; 633 } 634 635out: 636 return ret_val; 637} 638 639/** 640 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 641 * @hw: pointer to the HW structure 642 * 643 * Force the speed and duplex settings onto the PHY. This is a 644 * function pointer entry point called by the phy module. 645 **/ 646STATIC s32 647e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 648{ 649 s32 ret_val; 650 u16 phy_data; 651 boolean_t link; 652 653 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan"); 654 655 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 656 * forced whenever speed and duplex are forced. 657 */ 658 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 659 if (ret_val) 660 goto out; 661 662 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 663 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 664 if (ret_val) 665 goto out; 666 667 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); 668 669 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data); 670 if (ret_val) 671 goto out; 672 673 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 674 675 /* Reset the phy to commit changes. */ 676 phy_data |= MII_CR_RESET; 677 678 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data); 679 if (ret_val) 680 goto out; 681 682 usec_delay(1); 683 684 if (hw->phy.wait_for_link) { 685 DEBUGOUT("Waiting for forced speed/duplex link " 686 "on GG82563 phy.\n"); 687 688 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 689 100000, &link); 690 if (ret_val) 691 goto out; 692 693 if (!link) { 694 /* We didn't get link. 695 * Reset the DSP and cross our fingers. 696 */ 697 ret_val = e1000_phy_reset_dsp_generic(hw); 698 if (ret_val) 699 goto out; 700 } 701 702 /* Try once more */ 703 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 704 100000, &link); 705 if (ret_val) 706 goto out; 707 } 708 709 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 710 if (ret_val) 711 goto out; 712 713 /* Resetting the phy means we need to verify the TX_CLK corresponds 714 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 715 */ 716 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 717 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 718 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 719 else 720 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 721 722 /* In addition, we must re-enable CRS on Tx for both half and full 723 * duplex. 724 */ 725 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 726 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); 727 728out: 729 return ret_val; 730} 731 732/** 733 * e1000_get_cable_length_80003es2lan - Set approximate cable length 734 * @hw: pointer to the HW structure 735 * 736 * Find the approximate cable length as measured by the GG82563 PHY. 737 * This is a function pointer entry point called by the phy module. 738 **/ 739STATIC s32 740e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 741{ 742 struct e1000_phy_info *phy = &hw->phy; 743 s32 ret_val; 744 u16 phy_data, index; 745 746 DEBUGFUNC("e1000_get_cable_length_80003es2lan"); 747 748 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 749 if (ret_val) 750 goto out; 751 752 index = phy_data & GG82563_DSPD_CABLE_LENGTH; 753 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 754 phy->max_cable_length = e1000_gg82563_cable_length_table[index+5]; 755 756 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 757 758out: 759 return ret_val; 760} 761 762/** 763 * e1000_get_link_up_info_80003es2lan - Report speed and duplex 764 * @hw: pointer to the HW structure 765 * @speed: pointer to speed buffer 766 * @duplex: pointer to duplex buffer 767 * 768 * Retrieve the current speed and duplex configuration. 769 * This is a function pointer entry point called by the api module. 770 **/ 771STATIC s32 772e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, u16 *duplex) 773{ 774 s32 ret_val; 775 776 DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); 777 778 if (hw->media_type == e1000_media_type_copper) { 779 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, 780 speed, 781 duplex); 782 if (ret_val) 783 goto out; 784 if (*speed == SPEED_1000) 785 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 786 else 787 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, 788 *duplex); 789 } else 790 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, 791 speed, 792 duplex); 793 794out: 795 return ret_val; 796} 797 798/** 799 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 800 * @hw: pointer to the HW structure 801 * 802 * Perform a global reset to the ESB2 controller. 803 * This is a function pointer entry point called by the api module. 804 **/ 805STATIC s32 806e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 807{ 808 u32 ctrl, icr; 809 s32 ret_val; 810 811 DEBUGFUNC("e1000_reset_hw_80003es2lan"); 812 813 /* Prevent the PCI-E bus from sticking if there is no TLP connection 814 * on the last TLP read/write transaction when MAC is reset. 815 */ 816 ret_val = e1000_disable_pcie_master_generic(hw); 817 if (ret_val) { 818 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 819 } 820 821 DEBUGOUT("Masking off all interrupts\n"); 822 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 823 824 E1000_WRITE_REG(hw, E1000_RCTL, 0); 825 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 826 E1000_WRITE_FLUSH(hw); 827 828 msec_delay(10); 829 830 ctrl = E1000_READ_REG(hw, E1000_CTRL); 831 832 DEBUGOUT("Issuing a global reset to MAC\n"); 833 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 834 835 ret_val = e1000_get_auto_rd_done_generic(hw); 836 if (ret_val) 837 /* We don't want to continue accessing MAC registers. */ 838 goto out; 839 840 /* Clear any pending interrupt events. */ 841 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 842 icr = E1000_READ_REG(hw, E1000_ICR); 843 844out: 845 return ret_val; 846} 847 848/** 849 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 850 * @hw: pointer to the HW structure 851 * 852 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 853 * This is a function pointer entry point called by the api module. 854 **/ 855STATIC s32 856e1000_init_hw_80003es2lan(struct e1000_hw *hw) 857{ 858 struct e1000_mac_info *mac = &hw->mac; 859 u32 reg_data; 860 s32 ret_val; 861 u16 i; 862 863 DEBUGFUNC("e1000_init_hw_80003es2lan"); 864 865 e1000_initialize_hw_bits_80003es2lan(hw); 866 867 /* Initialize identification LED */ 868 ret_val = e1000_id_led_init_generic(hw); 869 if (ret_val) { 870 DEBUGOUT("Error initializing identification LED\n"); 871 goto out; 872 } 873 874 /* Disabling VLAN filtering */ 875 DEBUGOUT("Initializing the IEEE VLAN\n"); 876 e1000_clear_vfta(hw); 877 878 /* Setup the receive address. */ 879 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 880 881 /* Zero out the Multicast HASH table */ 882 DEBUGOUT("Zeroing the MTA\n"); 883 for (i = 0; i < mac->mta_reg_count; i++) 884 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 885 886 /* Setup link and flow control */ 887 ret_val = e1000_setup_link(hw); 888 889 /* Set the transmit descriptor write-back policy */ 890 reg_data = E1000_READ_REG(hw, E1000_TXDCTL); 891 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 892 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 893 E1000_WRITE_REG(hw, E1000_TXDCTL, reg_data); 894 895 /* ...for both queues. */ 896 reg_data = E1000_READ_REG(hw, E1000_TXDCTL1); 897 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 898 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 899 E1000_WRITE_REG(hw, E1000_TXDCTL1, reg_data); 900 901 /* Enable retransmit on late collisions */ 902 reg_data = E1000_READ_REG(hw, E1000_TCTL); 903 reg_data |= E1000_TCTL_RTLC; 904 E1000_WRITE_REG(hw, E1000_TCTL, reg_data); 905 906 /* Configure Gigabit Carry Extend Padding */ 907 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); 908 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 909 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 910 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); 911 912 /* Configure Transmit Inter-Packet Gap */ 913 reg_data = E1000_READ_REG(hw, E1000_TIPG); 914 reg_data &= ~E1000_TIPG_IPGT_MASK; 915 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 916 E1000_WRITE_REG(hw, E1000_TIPG, reg_data); 917 918 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 919 reg_data &= ~0x00100000; 920 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 921 922 /* Clear all of the statistics registers (clear on read). It is 923 * important that we do this after we have tried to establish link 924 * because the symbol error count will increment wildly if there 925 * is no link. 926 */ 927 e1000_clear_hw_cntrs_80003es2lan(hw); 928 929out: 930 return ret_val; 931} 932 933/** 934 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 935 * @hw: pointer to the HW structure 936 * 937 * Initializes required hardware-dependent bits needed for normal operation. 938 **/ 939static void 940e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 941{ 942 u32 reg; 943 944 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan"); 945 946 if (hw->mac.disable_hw_init_bits) 947 goto out; 948 949 /* Transmit Descriptor Control 0 */ 950 reg = E1000_READ_REG(hw, E1000_TXDCTL); 951 reg |= (1 << 22); 952 E1000_WRITE_REG(hw, E1000_TXDCTL, reg); 953 954 /* Transmit Descriptor Control 1 */ 955 reg = E1000_READ_REG(hw, E1000_TXDCTL1); 956 reg |= (1 << 22); 957 E1000_WRITE_REG(hw, E1000_TXDCTL1, reg); 958 959 /* Transmit Arbitration Control 0 */ 960 reg = E1000_READ_REG(hw, E1000_TARC0); 961 reg &= ~(0xF << 27); /* 30:27 */ 962 if (hw->media_type != e1000_media_type_copper) 963 reg &= ~(1 << 20); 964 E1000_WRITE_REG(hw, E1000_TARC0, reg); 965 966 /* Transmit Arbitration Control 1 */ 967 reg = E1000_READ_REG(hw, E1000_TARC1); 968 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 969 reg &= ~(1 << 28); 970 else 971 reg |= (1 << 28); 972 E1000_WRITE_REG(hw, E1000_TARC1, reg); 973 974out: 975 return; 976} 977 978/** 979 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 980 * @hw: pointer to the HW structure 981 * 982 * Setup some GG82563 PHY registers for obtaining link 983 **/ 984static s32 985e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 986{ 987 struct e1000_phy_info *phy = &hw->phy; 988 s32 ret_val; 989 u32 ctrl_ext; 990 u16 data; 991 992 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); 993 994 if (!phy->reset_disable) { 995 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 996 &data); 997 if (ret_val) 998 goto out; 999 1000 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1001 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 1002 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 1003 1004 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1005 data); 1006 if (ret_val) 1007 goto out; 1008 1009 /* Options: 1010 * MDI/MDI-X = 0 (default) 1011 * 0 - Auto for all speeds 1012 * 1 - MDI mode 1013 * 2 - MDI-X mode 1014 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1015 */ 1016 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &data); 1017 if (ret_val) 1018 goto out; 1019 1020 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1021 1022 switch (phy->mdix) { 1023 case 1: 1024 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1025 break; 1026 case 2: 1027 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1028 break; 1029 case 0: 1030 default: 1031 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1032 break; 1033 } 1034 1035 /* Options: 1036 * disable_polarity_correction = 0 (default) 1037 * Automatic Correction for Reversed Cable Polarity 1038 * 0 - Disabled 1039 * 1 - Enabled 1040 */ 1041 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1042 if (phy->disable_polarity_correction == TRUE) 1043 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1044 1045 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, data); 1046 if (ret_val) 1047 goto out; 1048 1049 /* SW Reset the PHY so all changes take effect */ 1050 ret_val = e1000_phy_commit(hw); 1051 if (ret_val) { 1052 DEBUGOUT("Error Resetting the PHY\n"); 1053 goto out; 1054 } 1055 1056 } 1057 1058 /* Bypass RX and TX FIFO's */ 1059 ret_val = e1000_write_kmrn_reg(hw, 1060 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, 1061 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 1062 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 1063 if (ret_val) 1064 goto out; 1065 1066 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); 1067 if (ret_val) 1068 goto out; 1069 1070 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1071 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); 1072 if (ret_val) 1073 goto out; 1074 1075 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1076 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 1077 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1078 1079 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 1080 if (ret_val) 1081 goto out; 1082 1083 /* Do not init these registers when the HW is in IAMT mode, since the 1084 * firmware will have already initialized them. We only initialize 1085 * them if the HW is not in IAMT mode. 1086 */ 1087 if (e1000_check_mng_mode(hw) == FALSE) { 1088 /* Enable Electrical Idle on the PHY */ 1089 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1090 ret_val = e1000_write_phy_reg(hw, 1091 GG82563_PHY_PWR_MGMT_CTRL, 1092 data); 1093 if (ret_val) 1094 goto out; 1095 1096 ret_val = e1000_read_phy_reg(hw, 1097 GG82563_PHY_KMRN_MODE_CTRL, 1098 &data); 1099 if (ret_val) 1100 goto out; 1101 1102 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1103 ret_val = e1000_write_phy_reg(hw, 1104 GG82563_PHY_KMRN_MODE_CTRL, 1105 data); 1106 1107 if (ret_val) 1108 goto out; 1109 } 1110 1111 /* Workaround: Disable padding in Kumeran interface in the MAC 1112 * and in the PHY to avoid CRC errors. 1113 */ 1114 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, &data); 1115 if (ret_val) 1116 goto out; 1117 1118 data |= GG82563_ICR_DIS_PADDING; 1119 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, data); 1120 if (ret_val) 1121 goto out; 1122 1123out: 1124 return ret_val; 1125} 1126 1127/** 1128 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1129 * @hw: pointer to the HW structure 1130 * 1131 * Essentially a wrapper for setting up all things "copper" related. 1132 * This is a function pointer entry point called by the mac module. 1133 **/ 1134STATIC s32 1135e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1136{ 1137 u32 ctrl; 1138 s32 ret_val; 1139 u16 reg_data; 1140 1141 DEBUGFUNC("e1000_setup_copper_link_80003es2lan"); 1142 1143 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1144 ctrl |= E1000_CTRL_SLU; 1145 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1146 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1147 1148 /* Set the mac to wait the maximum time between each 1149 * iteration and increase the max iterations when 1150 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 1151 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 1152 if (ret_val) 1153 goto out; 1154 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); 1155 if (ret_val) 1156 goto out; 1157 reg_data |= 0x3F; 1158 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); 1159 if (ret_val) 1160 goto out; 1161 ret_val = e1000_read_kmrn_reg(hw, 1162 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1163 ®_data); 1164 if (ret_val) 1165 goto out; 1166 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1167 ret_val = e1000_write_kmrn_reg(hw, 1168 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1169 reg_data); 1170 if (ret_val) 1171 goto out; 1172 1173 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1174 if (ret_val) 1175 goto out; 1176 1177 ret_val = e1000_setup_copper_link_generic(hw); 1178 1179out: 1180 return ret_val; 1181} 1182 1183/** 1184 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1185 * @hw: pointer to the HW structure 1186 * @duplex: current duplex setting 1187 * 1188 * Configure the KMRN interface by applying last minute quirks for 1189 * 10/100 operation. 1190 **/ 1191static s32 1192e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1193{ 1194 s32 ret_val = E1000_SUCCESS; 1195 u32 tipg; 1196 u32 i = 0; 1197 u16 reg_data, reg_data2; 1198 1199 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 1200 1201 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1202 ret_val = e1000_write_kmrn_reg(hw, 1203 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1204 reg_data); 1205 if (ret_val) 1206 goto out; 1207 1208 /* Configure Transmit Inter-Packet Gap */ 1209 tipg = E1000_READ_REG(hw, E1000_TIPG); 1210 tipg &= ~E1000_TIPG_IPGT_MASK; 1211 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1212 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1213 1214 1215 do { 1216 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1217 ®_data); 1218 if (ret_val) 1219 goto out; 1220 1221 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1222 ®_data2); 1223 if (ret_val) 1224 goto out; 1225 i++; 1226 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1227 1228 if (duplex == HALF_DUPLEX) 1229 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1230 else 1231 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1232 1233 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1234 1235out: 1236 return ret_val; 1237} 1238 1239/** 1240 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1241 * @hw: pointer to the HW structure 1242 * 1243 * Configure the KMRN interface by applying last minute quirks for 1244 * gigabit operation. 1245 **/ 1246static s32 1247e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1248{ 1249 s32 ret_val = E1000_SUCCESS; 1250 u16 reg_data, reg_data2; 1251 u32 tipg; 1252 u32 i = 0; 1253 1254 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 1255 1256 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1257 ret_val = e1000_write_kmrn_reg(hw, 1258 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1259 reg_data); 1260 if (ret_val) 1261 goto out; 1262 1263 /* Configure Transmit Inter-Packet Gap */ 1264 tipg = E1000_READ_REG(hw, E1000_TIPG); 1265 tipg &= ~E1000_TIPG_IPGT_MASK; 1266 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1267 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1268 1269 1270 do { 1271 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1272 ®_data); 1273 if (ret_val) 1274 goto out; 1275 1276 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1277 ®_data2); 1278 if (ret_val) 1279 goto out; 1280 i++; 1281 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1282 1283 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1284 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1285 1286out: 1287 return ret_val; 1288} 1289 1290/** 1291 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1292 * @hw: pointer to the HW structure 1293 * 1294 * Clears the hardware counters by reading the counter registers. 1295 **/ 1296STATIC void 1297e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1298{ 1299 volatile u32 temp; 1300 1301 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan"); 1302 1303 e1000_clear_hw_cntrs_base_generic(hw); 1304 1305 temp = E1000_READ_REG(hw, E1000_PRC64); 1306 temp = E1000_READ_REG(hw, E1000_PRC127); 1307 temp = E1000_READ_REG(hw, E1000_PRC255); 1308 temp = E1000_READ_REG(hw, E1000_PRC511); 1309 temp = E1000_READ_REG(hw, E1000_PRC1023); 1310 temp = E1000_READ_REG(hw, E1000_PRC1522); 1311 temp = E1000_READ_REG(hw, E1000_PTC64); 1312 temp = E1000_READ_REG(hw, E1000_PTC127); 1313 temp = E1000_READ_REG(hw, E1000_PTC255); 1314 temp = E1000_READ_REG(hw, E1000_PTC511); 1315 temp = E1000_READ_REG(hw, E1000_PTC1023); 1316 temp = E1000_READ_REG(hw, E1000_PTC1522); 1317 1318 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1319 temp = E1000_READ_REG(hw, E1000_RXERRC); 1320 temp = E1000_READ_REG(hw, E1000_TNCRS); 1321 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1322 temp = E1000_READ_REG(hw, E1000_TSCTC); 1323 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1324 1325 temp = E1000_READ_REG(hw, E1000_MGTPRC); 1326 temp = E1000_READ_REG(hw, E1000_MGTPDC); 1327 temp = E1000_READ_REG(hw, E1000_MGTPTC); 1328 1329 temp = E1000_READ_REG(hw, E1000_IAC); 1330 temp = E1000_READ_REG(hw, E1000_ICRXOC); 1331 1332 temp = E1000_READ_REG(hw, E1000_ICRXPTC); 1333 temp = E1000_READ_REG(hw, E1000_ICRXATC); 1334 temp = E1000_READ_REG(hw, E1000_ICTXPTC); 1335 temp = E1000_READ_REG(hw, E1000_ICTXATC); 1336 temp = E1000_READ_REG(hw, E1000_ICTXQEC); 1337 temp = E1000_READ_REG(hw, E1000_ICTXQMTC); 1338 temp = E1000_READ_REG(hw, E1000_ICRXDMTC); 1339} 1340