1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD$"); 31 32#include <dev/drm2/drmP.h> 33#include <dev/drm2/radeon/radeon_drm.h> 34#include "radeon.h" 35#include "radeon_asic.h" 36#include "radeon_mode.h" 37#include "r600d.h" 38#include "atom.h" 39#include "avivod.h" 40 41#define PFP_UCODE_SIZE 576 42#define PM4_UCODE_SIZE 1792 43#define RLC_UCODE_SIZE 768 44#define R700_PFP_UCODE_SIZE 848 45#define R700_PM4_UCODE_SIZE 1360 46#define R700_RLC_UCODE_SIZE 1024 47#define EVERGREEN_PFP_UCODE_SIZE 1120 48#define EVERGREEN_PM4_UCODE_SIZE 1376 49#define EVERGREEN_RLC_UCODE_SIZE 768 50#define CAYMAN_RLC_UCODE_SIZE 1024 51#define ARUBA_RLC_UCODE_SIZE 1536 52 53#ifdef DUMBBELL_WIP 54/* Firmware Names */ 55MODULE_FIRMWARE("radeon/R600_pfp.bin"); 56MODULE_FIRMWARE("radeon/R600_me.bin"); 57MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 58MODULE_FIRMWARE("radeon/RV610_me.bin"); 59MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 60MODULE_FIRMWARE("radeon/RV630_me.bin"); 61MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 62MODULE_FIRMWARE("radeon/RV620_me.bin"); 63MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 64MODULE_FIRMWARE("radeon/RV635_me.bin"); 65MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 66MODULE_FIRMWARE("radeon/RV670_me.bin"); 67MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 68MODULE_FIRMWARE("radeon/RS780_me.bin"); 69MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 70MODULE_FIRMWARE("radeon/RV770_me.bin"); 71MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 72MODULE_FIRMWARE("radeon/RV730_me.bin"); 73MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 74MODULE_FIRMWARE("radeon/RV710_me.bin"); 75MODULE_FIRMWARE("radeon/R600_rlc.bin"); 76MODULE_FIRMWARE("radeon/R700_rlc.bin"); 77MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 78MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 79MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 80MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 81MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 82MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 83MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 84MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 85MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 86MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 87MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 88MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 89MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 90MODULE_FIRMWARE("radeon/PALM_me.bin"); 91MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 92MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 93MODULE_FIRMWARE("radeon/SUMO_me.bin"); 94MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 95MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 96#endif /* DUMBBELL_WIP */ 97 98int r600_debugfs_mc_info_init(struct radeon_device *rdev); 99 100/* r600,rv610,rv630,rv620,rv635,rv670 */ 101static void r600_gpu_init(struct radeon_device *rdev); 102void r600_irq_disable(struct radeon_device *rdev); 103static void r600_pcie_gen2_enable(struct radeon_device *rdev); 104 105/* get temperature in millidegrees */ 106int rv6xx_get_temp(struct radeon_device *rdev) 107{ 108 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 109 ASIC_T_SHIFT; 110 int actual_temp = temp & 0xff; 111 112 if (temp & 0x100) 113 actual_temp -= 256; 114 115 return actual_temp * 1000; 116} 117 118void r600_pm_get_dynpm_state(struct radeon_device *rdev) 119{ 120 int i; 121 122 rdev->pm.dynpm_can_upclock = true; 123 rdev->pm.dynpm_can_downclock = true; 124 125 /* power state array is low to high, default is first */ 126 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 127 int min_power_state_index = 0; 128 129 if (rdev->pm.num_power_states > 2) 130 min_power_state_index = 1; 131 132 switch (rdev->pm.dynpm_planned_action) { 133 case DYNPM_ACTION_MINIMUM: 134 rdev->pm.requested_power_state_index = min_power_state_index; 135 rdev->pm.requested_clock_mode_index = 0; 136 rdev->pm.dynpm_can_downclock = false; 137 break; 138 case DYNPM_ACTION_DOWNCLOCK: 139 if (rdev->pm.current_power_state_index == min_power_state_index) { 140 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 141 rdev->pm.dynpm_can_downclock = false; 142 } else { 143 if (rdev->pm.active_crtc_count > 1) { 144 for (i = 0; i < rdev->pm.num_power_states; i++) { 145 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 146 continue; 147 else if (i >= rdev->pm.current_power_state_index) { 148 rdev->pm.requested_power_state_index = 149 rdev->pm.current_power_state_index; 150 break; 151 } else { 152 rdev->pm.requested_power_state_index = i; 153 break; 154 } 155 } 156 } else { 157 if (rdev->pm.current_power_state_index == 0) 158 rdev->pm.requested_power_state_index = 159 rdev->pm.num_power_states - 1; 160 else 161 rdev->pm.requested_power_state_index = 162 rdev->pm.current_power_state_index - 1; 163 } 164 } 165 rdev->pm.requested_clock_mode_index = 0; 166 /* don't use the power state if crtcs are active and no display flag is set */ 167 if ((rdev->pm.active_crtc_count > 0) && 168 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 169 clock_info[rdev->pm.requested_clock_mode_index].flags & 170 RADEON_PM_MODE_NO_DISPLAY)) { 171 rdev->pm.requested_power_state_index++; 172 } 173 break; 174 case DYNPM_ACTION_UPCLOCK: 175 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 176 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 177 rdev->pm.dynpm_can_upclock = false; 178 } else { 179 if (rdev->pm.active_crtc_count > 1) { 180 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 181 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 182 continue; 183 else if (i <= rdev->pm.current_power_state_index) { 184 rdev->pm.requested_power_state_index = 185 rdev->pm.current_power_state_index; 186 break; 187 } else { 188 rdev->pm.requested_power_state_index = i; 189 break; 190 } 191 } 192 } else 193 rdev->pm.requested_power_state_index = 194 rdev->pm.current_power_state_index + 1; 195 } 196 rdev->pm.requested_clock_mode_index = 0; 197 break; 198 case DYNPM_ACTION_DEFAULT: 199 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 200 rdev->pm.requested_clock_mode_index = 0; 201 rdev->pm.dynpm_can_upclock = false; 202 break; 203 case DYNPM_ACTION_NONE: 204 default: 205 DRM_ERROR("Requested mode for not defined action\n"); 206 return; 207 } 208 } else { 209 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 210 /* for now just select the first power state and switch between clock modes */ 211 /* power state array is low to high, default is first (0) */ 212 if (rdev->pm.active_crtc_count > 1) { 213 rdev->pm.requested_power_state_index = -1; 214 /* start at 1 as we don't want the default mode */ 215 for (i = 1; i < rdev->pm.num_power_states; i++) { 216 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 217 continue; 218 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 219 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 220 rdev->pm.requested_power_state_index = i; 221 break; 222 } 223 } 224 /* if nothing selected, grab the default state. */ 225 if (rdev->pm.requested_power_state_index == -1) 226 rdev->pm.requested_power_state_index = 0; 227 } else 228 rdev->pm.requested_power_state_index = 1; 229 230 switch (rdev->pm.dynpm_planned_action) { 231 case DYNPM_ACTION_MINIMUM: 232 rdev->pm.requested_clock_mode_index = 0; 233 rdev->pm.dynpm_can_downclock = false; 234 break; 235 case DYNPM_ACTION_DOWNCLOCK: 236 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 237 if (rdev->pm.current_clock_mode_index == 0) { 238 rdev->pm.requested_clock_mode_index = 0; 239 rdev->pm.dynpm_can_downclock = false; 240 } else 241 rdev->pm.requested_clock_mode_index = 242 rdev->pm.current_clock_mode_index - 1; 243 } else { 244 rdev->pm.requested_clock_mode_index = 0; 245 rdev->pm.dynpm_can_downclock = false; 246 } 247 /* don't use the power state if crtcs are active and no display flag is set */ 248 if ((rdev->pm.active_crtc_count > 0) && 249 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 250 clock_info[rdev->pm.requested_clock_mode_index].flags & 251 RADEON_PM_MODE_NO_DISPLAY)) { 252 rdev->pm.requested_clock_mode_index++; 253 } 254 break; 255 case DYNPM_ACTION_UPCLOCK: 256 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 257 if (rdev->pm.current_clock_mode_index == 258 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 259 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 260 rdev->pm.dynpm_can_upclock = false; 261 } else 262 rdev->pm.requested_clock_mode_index = 263 rdev->pm.current_clock_mode_index + 1; 264 } else { 265 rdev->pm.requested_clock_mode_index = 266 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 267 rdev->pm.dynpm_can_upclock = false; 268 } 269 break; 270 case DYNPM_ACTION_DEFAULT: 271 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 272 rdev->pm.requested_clock_mode_index = 0; 273 rdev->pm.dynpm_can_upclock = false; 274 break; 275 case DYNPM_ACTION_NONE: 276 default: 277 DRM_ERROR("Requested mode for not defined action\n"); 278 return; 279 } 280 } 281 282 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 283 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 284 clock_info[rdev->pm.requested_clock_mode_index].sclk, 285 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 286 clock_info[rdev->pm.requested_clock_mode_index].mclk, 287 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 288 pcie_lanes); 289} 290 291void rs780_pm_init_profile(struct radeon_device *rdev) 292{ 293 if (rdev->pm.num_power_states == 2) { 294 /* default */ 295 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 296 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 298 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 299 /* low sh */ 300 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 301 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 303 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 304 /* mid sh */ 305 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 306 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 308 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 309 /* high sh */ 310 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 314 /* low mh */ 315 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 316 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 318 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 319 /* mid mh */ 320 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 321 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 323 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 324 /* high mh */ 325 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 326 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 328 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 329 } else if (rdev->pm.num_power_states == 3) { 330 /* default */ 331 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 332 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 333 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 334 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 335 /* low sh */ 336 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 337 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 338 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 339 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 340 /* mid sh */ 341 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 342 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 343 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 344 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 345 /* high sh */ 346 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 347 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 348 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 349 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 350 /* low mh */ 351 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 352 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 353 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 354 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 355 /* mid mh */ 356 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 357 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 358 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 359 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 360 /* high mh */ 361 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 362 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 363 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 364 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 365 } else { 366 /* default */ 367 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 368 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 369 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 370 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 371 /* low sh */ 372 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 373 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 374 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 375 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 376 /* mid sh */ 377 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 378 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 379 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 380 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 381 /* high sh */ 382 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 383 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 384 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 385 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 386 /* low mh */ 387 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 388 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 389 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 390 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 391 /* mid mh */ 392 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 393 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 394 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 395 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 396 /* high mh */ 397 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 398 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 399 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 400 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 401 } 402} 403 404void r600_pm_init_profile(struct radeon_device *rdev) 405{ 406 int idx; 407 408 if (rdev->family == CHIP_R600) { 409 /* XXX */ 410 /* default */ 411 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 412 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 414 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 415 /* low sh */ 416 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 417 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 419 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 420 /* mid sh */ 421 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 422 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 424 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 425 /* high sh */ 426 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 427 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 429 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 430 /* low mh */ 431 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 432 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 434 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 435 /* mid mh */ 436 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 437 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 439 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 440 /* high mh */ 441 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 442 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 444 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 445 } else { 446 if (rdev->pm.num_power_states < 4) { 447 /* default */ 448 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 449 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 451 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 452 /* low sh */ 453 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 454 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 456 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 457 /* mid sh */ 458 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 459 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 461 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 462 /* high sh */ 463 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 464 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 466 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 467 /* low mh */ 468 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 469 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 471 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 472 /* low mh */ 473 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 474 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 476 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 477 /* high mh */ 478 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 479 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 481 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 482 } else { 483 /* default */ 484 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 485 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 488 /* low sh */ 489 if (rdev->flags & RADEON_IS_MOBILITY) 490 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 491 else 492 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 493 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 497 /* mid sh */ 498 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 502 /* high sh */ 503 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 504 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 506 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 507 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 508 /* low mh */ 509 if (rdev->flags & RADEON_IS_MOBILITY) 510 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 511 else 512 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 513 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 514 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 516 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 517 /* mid mh */ 518 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 519 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 521 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 522 /* high mh */ 523 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 524 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 527 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 528 } 529 } 530} 531 532void r600_pm_misc(struct radeon_device *rdev) 533{ 534 int req_ps_idx = rdev->pm.requested_power_state_index; 535 int req_cm_idx = rdev->pm.requested_clock_mode_index; 536 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 537 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 538 539 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 540 /* 0xff01 is a flag rather then an actual voltage */ 541 if (voltage->voltage == 0xff01) 542 return; 543 if (voltage->voltage != rdev->pm.current_vddc) { 544 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 545 rdev->pm.current_vddc = voltage->voltage; 546 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 547 } 548 } 549} 550 551bool r600_gui_idle(struct radeon_device *rdev) 552{ 553 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 554 return false; 555 else 556 return true; 557} 558 559/* hpd for digital panel detect/disconnect */ 560bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 561{ 562 bool connected = false; 563 564 if (ASIC_IS_DCE3(rdev)) { 565 switch (hpd) { 566 case RADEON_HPD_1: 567 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 568 connected = true; 569 break; 570 case RADEON_HPD_2: 571 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 572 connected = true; 573 break; 574 case RADEON_HPD_3: 575 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 576 connected = true; 577 break; 578 case RADEON_HPD_4: 579 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 580 connected = true; 581 break; 582 /* DCE 3.2 */ 583 case RADEON_HPD_5: 584 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 585 connected = true; 586 break; 587 case RADEON_HPD_6: 588 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 589 connected = true; 590 break; 591 default: 592 break; 593 } 594 } else { 595 switch (hpd) { 596 case RADEON_HPD_1: 597 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 598 connected = true; 599 break; 600 case RADEON_HPD_2: 601 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 602 connected = true; 603 break; 604 case RADEON_HPD_3: 605 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 606 connected = true; 607 break; 608 default: 609 break; 610 } 611 } 612 return connected; 613} 614 615void r600_hpd_set_polarity(struct radeon_device *rdev, 616 enum radeon_hpd_id hpd) 617{ 618 u32 tmp; 619 bool connected = r600_hpd_sense(rdev, hpd); 620 621 if (ASIC_IS_DCE3(rdev)) { 622 switch (hpd) { 623 case RADEON_HPD_1: 624 tmp = RREG32(DC_HPD1_INT_CONTROL); 625 if (connected) 626 tmp &= ~DC_HPDx_INT_POLARITY; 627 else 628 tmp |= DC_HPDx_INT_POLARITY; 629 WREG32(DC_HPD1_INT_CONTROL, tmp); 630 break; 631 case RADEON_HPD_2: 632 tmp = RREG32(DC_HPD2_INT_CONTROL); 633 if (connected) 634 tmp &= ~DC_HPDx_INT_POLARITY; 635 else 636 tmp |= DC_HPDx_INT_POLARITY; 637 WREG32(DC_HPD2_INT_CONTROL, tmp); 638 break; 639 case RADEON_HPD_3: 640 tmp = RREG32(DC_HPD3_INT_CONTROL); 641 if (connected) 642 tmp &= ~DC_HPDx_INT_POLARITY; 643 else 644 tmp |= DC_HPDx_INT_POLARITY; 645 WREG32(DC_HPD3_INT_CONTROL, tmp); 646 break; 647 case RADEON_HPD_4: 648 tmp = RREG32(DC_HPD4_INT_CONTROL); 649 if (connected) 650 tmp &= ~DC_HPDx_INT_POLARITY; 651 else 652 tmp |= DC_HPDx_INT_POLARITY; 653 WREG32(DC_HPD4_INT_CONTROL, tmp); 654 break; 655 case RADEON_HPD_5: 656 tmp = RREG32(DC_HPD5_INT_CONTROL); 657 if (connected) 658 tmp &= ~DC_HPDx_INT_POLARITY; 659 else 660 tmp |= DC_HPDx_INT_POLARITY; 661 WREG32(DC_HPD5_INT_CONTROL, tmp); 662 break; 663 /* DCE 3.2 */ 664 case RADEON_HPD_6: 665 tmp = RREG32(DC_HPD6_INT_CONTROL); 666 if (connected) 667 tmp &= ~DC_HPDx_INT_POLARITY; 668 else 669 tmp |= DC_HPDx_INT_POLARITY; 670 WREG32(DC_HPD6_INT_CONTROL, tmp); 671 break; 672 default: 673 break; 674 } 675 } else { 676 switch (hpd) { 677 case RADEON_HPD_1: 678 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 679 if (connected) 680 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 681 else 682 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 683 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 684 break; 685 case RADEON_HPD_2: 686 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 687 if (connected) 688 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 689 else 690 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 691 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 692 break; 693 case RADEON_HPD_3: 694 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 695 if (connected) 696 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 697 else 698 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 699 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 700 break; 701 default: 702 break; 703 } 704 } 705} 706 707void r600_hpd_init(struct radeon_device *rdev) 708{ 709 struct drm_device *dev = rdev->ddev; 710 struct drm_connector *connector; 711 unsigned enable = 0; 712 713 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 714 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 715 716 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 717 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 718 /* don't try to enable hpd on eDP or LVDS avoid breaking the 719 * aux dp channel on imac and help (but not completely fix) 720 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 721 */ 722 continue; 723 } 724 if (ASIC_IS_DCE3(rdev)) { 725 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 726 if (ASIC_IS_DCE32(rdev)) 727 tmp |= DC_HPDx_EN; 728 729 switch (radeon_connector->hpd.hpd) { 730 case RADEON_HPD_1: 731 WREG32(DC_HPD1_CONTROL, tmp); 732 break; 733 case RADEON_HPD_2: 734 WREG32(DC_HPD2_CONTROL, tmp); 735 break; 736 case RADEON_HPD_3: 737 WREG32(DC_HPD3_CONTROL, tmp); 738 break; 739 case RADEON_HPD_4: 740 WREG32(DC_HPD4_CONTROL, tmp); 741 break; 742 /* DCE 3.2 */ 743 case RADEON_HPD_5: 744 WREG32(DC_HPD5_CONTROL, tmp); 745 break; 746 case RADEON_HPD_6: 747 WREG32(DC_HPD6_CONTROL, tmp); 748 break; 749 default: 750 break; 751 } 752 } else { 753 switch (radeon_connector->hpd.hpd) { 754 case RADEON_HPD_1: 755 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 756 break; 757 case RADEON_HPD_2: 758 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 759 break; 760 case RADEON_HPD_3: 761 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 762 break; 763 default: 764 break; 765 } 766 } 767 enable |= 1 << radeon_connector->hpd.hpd; 768 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 769 } 770 radeon_irq_kms_enable_hpd(rdev, enable); 771} 772 773void r600_hpd_fini(struct radeon_device *rdev) 774{ 775 struct drm_device *dev = rdev->ddev; 776 struct drm_connector *connector; 777 unsigned disable = 0; 778 779 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 780 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 781 if (ASIC_IS_DCE3(rdev)) { 782 switch (radeon_connector->hpd.hpd) { 783 case RADEON_HPD_1: 784 WREG32(DC_HPD1_CONTROL, 0); 785 break; 786 case RADEON_HPD_2: 787 WREG32(DC_HPD2_CONTROL, 0); 788 break; 789 case RADEON_HPD_3: 790 WREG32(DC_HPD3_CONTROL, 0); 791 break; 792 case RADEON_HPD_4: 793 WREG32(DC_HPD4_CONTROL, 0); 794 break; 795 /* DCE 3.2 */ 796 case RADEON_HPD_5: 797 WREG32(DC_HPD5_CONTROL, 0); 798 break; 799 case RADEON_HPD_6: 800 WREG32(DC_HPD6_CONTROL, 0); 801 break; 802 default: 803 break; 804 } 805 } else { 806 switch (radeon_connector->hpd.hpd) { 807 case RADEON_HPD_1: 808 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 809 break; 810 case RADEON_HPD_2: 811 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 812 break; 813 case RADEON_HPD_3: 814 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 815 break; 816 default: 817 break; 818 } 819 } 820 disable |= 1 << radeon_connector->hpd.hpd; 821 } 822 radeon_irq_kms_disable_hpd(rdev, disable); 823} 824 825/* 826 * R600 PCIE GART 827 */ 828void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 829{ 830 unsigned i; 831 u32 tmp; 832 833 /* flush hdp cache so updates hit vram */ 834 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 835 !(rdev->flags & RADEON_IS_AGP)) { 836 volatile uint32_t *ptr = rdev->gart.ptr; 837 u32 tmp; 838 839 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 840 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 841 * This seems to cause problems on some AGP cards. Just use the old 842 * method for them. 843 */ 844 WREG32(HDP_DEBUG1, 0); 845 tmp = *ptr; 846 } else 847 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 848 849 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 850 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 851 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 852 for (i = 0; i < rdev->usec_timeout; i++) { 853 /* read MC_STATUS */ 854 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 855 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 856 if (tmp == 2) { 857 DRM_ERROR("[drm] r600 flush TLB failed\n"); 858 return; 859 } 860 if (tmp) { 861 return; 862 } 863 DRM_UDELAY(1); 864 } 865} 866 867int r600_pcie_gart_init(struct radeon_device *rdev) 868{ 869 int r; 870 871 if (rdev->gart.robj) { 872 DRM_ERROR("R600 PCIE GART already initialized\n"); 873 return 0; 874 } 875 /* Initialize common gart structure */ 876 r = radeon_gart_init(rdev); 877 if (r) 878 return r; 879 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 880 return radeon_gart_table_vram_alloc(rdev); 881} 882 883static int r600_pcie_gart_enable(struct radeon_device *rdev) 884{ 885 u32 tmp; 886 int r, i; 887 888 if (rdev->gart.robj == NULL) { 889 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 890 return -EINVAL; 891 } 892 r = radeon_gart_table_vram_pin(rdev); 893 if (r) 894 return r; 895 radeon_gart_restore(rdev); 896 897 /* Setup L2 cache */ 898 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 899 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 900 EFFECTIVE_L2_QUEUE_SIZE(7)); 901 WREG32(VM_L2_CNTL2, 0); 902 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 903 /* Setup TLB control */ 904 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 905 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 906 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 907 ENABLE_WAIT_L2_QUERY; 908 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 909 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 910 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 911 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 912 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 913 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 914 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 915 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 916 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 917 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 918 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 919 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 920 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 921 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 922 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 923 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 924 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 925 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 926 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 927 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 928 (u32)(rdev->dummy_page.addr >> 12)); 929 for (i = 1; i < 7; i++) 930 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 931 932 r600_pcie_gart_tlb_flush(rdev); 933 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 934 (unsigned)(rdev->mc.gtt_size >> 20), 935 (unsigned long long)rdev->gart.table_addr); 936 rdev->gart.ready = true; 937 return 0; 938} 939 940static void r600_pcie_gart_disable(struct radeon_device *rdev) 941{ 942 u32 tmp; 943 int i; 944 945 /* Disable all tables */ 946 for (i = 0; i < 7; i++) 947 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 948 949 /* Disable L2 cache */ 950 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 951 EFFECTIVE_L2_QUEUE_SIZE(7)); 952 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 953 /* Setup L1 TLB control */ 954 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 955 ENABLE_WAIT_L2_QUERY; 956 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 957 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 958 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 959 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 960 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 961 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 962 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 963 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 964 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 965 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 966 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 967 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 968 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 969 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 970 radeon_gart_table_vram_unpin(rdev); 971} 972 973static void r600_pcie_gart_fini(struct radeon_device *rdev) 974{ 975 radeon_gart_fini(rdev); 976 r600_pcie_gart_disable(rdev); 977 radeon_gart_table_vram_free(rdev); 978} 979 980static void r600_agp_enable(struct radeon_device *rdev) 981{ 982 u32 tmp; 983 int i; 984 985 /* Setup L2 cache */ 986 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 987 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 988 EFFECTIVE_L2_QUEUE_SIZE(7)); 989 WREG32(VM_L2_CNTL2, 0); 990 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 991 /* Setup TLB control */ 992 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 993 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 994 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 995 ENABLE_WAIT_L2_QUERY; 996 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 997 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 998 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 999 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1000 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1001 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1002 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1003 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1004 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1005 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1006 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1007 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1008 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1009 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1010 for (i = 0; i < 7; i++) 1011 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1012} 1013 1014int r600_mc_wait_for_idle(struct radeon_device *rdev) 1015{ 1016 unsigned i; 1017 u32 tmp; 1018 1019 for (i = 0; i < rdev->usec_timeout; i++) { 1020 /* read MC_STATUS */ 1021 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1022 if (!tmp) 1023 return 0; 1024 DRM_UDELAY(1); 1025 } 1026 return -1; 1027} 1028 1029static void r600_mc_program(struct radeon_device *rdev) 1030{ 1031 struct rv515_mc_save save; 1032 u32 tmp; 1033 int i, j; 1034 1035 /* Initialize HDP */ 1036 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1037 WREG32((0x2c14 + j), 0x00000000); 1038 WREG32((0x2c18 + j), 0x00000000); 1039 WREG32((0x2c1c + j), 0x00000000); 1040 WREG32((0x2c20 + j), 0x00000000); 1041 WREG32((0x2c24 + j), 0x00000000); 1042 } 1043 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1044 1045 rv515_mc_stop(rdev, &save); 1046 if (r600_mc_wait_for_idle(rdev)) { 1047 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1048 } 1049 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1050 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1051 /* Update configuration */ 1052 if (rdev->flags & RADEON_IS_AGP) { 1053 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1054 /* VRAM before AGP */ 1055 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1056 rdev->mc.vram_start >> 12); 1057 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1058 rdev->mc.gtt_end >> 12); 1059 } else { 1060 /* VRAM after AGP */ 1061 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1062 rdev->mc.gtt_start >> 12); 1063 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1064 rdev->mc.vram_end >> 12); 1065 } 1066 } else { 1067 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1068 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1069 } 1070 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1071 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1072 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1073 WREG32(MC_VM_FB_LOCATION, tmp); 1074 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1075 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1076 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1077 if (rdev->flags & RADEON_IS_AGP) { 1078 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1079 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1080 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1081 } else { 1082 WREG32(MC_VM_AGP_BASE, 0); 1083 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1084 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1085 } 1086 if (r600_mc_wait_for_idle(rdev)) { 1087 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1088 } 1089 rv515_mc_resume(rdev, &save); 1090 /* we need to own VRAM, so turn off the VGA renderer here 1091 * to stop it overwriting our objects */ 1092 rv515_vga_render_disable(rdev); 1093} 1094 1095/** 1096 * r600_vram_gtt_location - try to find VRAM & GTT location 1097 * @rdev: radeon device structure holding all necessary informations 1098 * @mc: memory controller structure holding memory informations 1099 * 1100 * Function will place try to place VRAM at same place as in CPU (PCI) 1101 * address space as some GPU seems to have issue when we reprogram at 1102 * different address space. 1103 * 1104 * If there is not enough space to fit the unvisible VRAM after the 1105 * aperture then we limit the VRAM size to the aperture. 1106 * 1107 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1108 * them to be in one from GPU point of view so that we can program GPU to 1109 * catch access outside them (weird GPU policy see ??). 1110 * 1111 * This function will never fails, worst case are limiting VRAM or GTT. 1112 * 1113 * Note: GTT start, end, size should be initialized before calling this 1114 * function on AGP platform. 1115 */ 1116static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1117{ 1118 u64 size_bf, size_af; 1119 1120 if (mc->mc_vram_size > 0xE0000000) { 1121 /* leave room for at least 512M GTT */ 1122 dev_warn(rdev->dev, "limiting VRAM\n"); 1123 mc->real_vram_size = 0xE0000000; 1124 mc->mc_vram_size = 0xE0000000; 1125 } 1126 if (rdev->flags & RADEON_IS_AGP) { 1127 size_bf = mc->gtt_start; 1128 size_af = 0xFFFFFFFF - mc->gtt_end; 1129 if (size_bf > size_af) { 1130 if (mc->mc_vram_size > size_bf) { 1131 dev_warn(rdev->dev, "limiting VRAM\n"); 1132 mc->real_vram_size = size_bf; 1133 mc->mc_vram_size = size_bf; 1134 } 1135 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1136 } else { 1137 if (mc->mc_vram_size > size_af) { 1138 dev_warn(rdev->dev, "limiting VRAM\n"); 1139 mc->real_vram_size = size_af; 1140 mc->mc_vram_size = size_af; 1141 } 1142 mc->vram_start = mc->gtt_end + 1; 1143 } 1144 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1145 dev_info(rdev->dev, "VRAM: %juM 0x%08jX - 0x%08jX (%juM used)\n", 1146 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start, 1147 (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20); 1148 } else { 1149 u64 base = 0; 1150 if (rdev->flags & RADEON_IS_IGP) { 1151 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1152 base <<= 24; 1153 } 1154 radeon_vram_location(rdev, &rdev->mc, base); 1155 rdev->mc.gtt_base_align = 0; 1156 radeon_gtt_location(rdev, mc); 1157 } 1158} 1159 1160static int r600_mc_init(struct radeon_device *rdev) 1161{ 1162 u32 tmp; 1163 int chansize, numchan; 1164 1165 /* Get VRAM informations */ 1166 rdev->mc.vram_is_ddr = true; 1167 tmp = RREG32(RAMCFG); 1168 if (tmp & CHANSIZE_OVERRIDE) { 1169 chansize = 16; 1170 } else if (tmp & CHANSIZE_MASK) { 1171 chansize = 64; 1172 } else { 1173 chansize = 32; 1174 } 1175 tmp = RREG32(CHMAP); 1176 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1177 case 0: 1178 default: 1179 numchan = 1; 1180 break; 1181 case 1: 1182 numchan = 2; 1183 break; 1184 case 2: 1185 numchan = 4; 1186 break; 1187 case 3: 1188 numchan = 8; 1189 break; 1190 } 1191 rdev->mc.vram_width = numchan * chansize; 1192 /* Could aper size report 0 ? */ 1193 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 1194 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 1195 /* Setup GPU memory space */ 1196 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1197 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1198 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1199 r600_vram_gtt_location(rdev, &rdev->mc); 1200 1201 if (rdev->flags & RADEON_IS_IGP) { 1202 rs690_pm_info(rdev); 1203 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1204 } 1205 radeon_update_bandwidth_info(rdev); 1206 return 0; 1207} 1208 1209int r600_vram_scratch_init(struct radeon_device *rdev) 1210{ 1211 int r; 1212 void *vram_scratch_ptr_ptr; 1213 1214 if (rdev->vram_scratch.robj == NULL) { 1215 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1216 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1217 NULL, &rdev->vram_scratch.robj); 1218 if (r) { 1219 return r; 1220 } 1221 } 1222 1223 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1224 if (unlikely(r != 0)) { 1225 radeon_bo_unref(&rdev->vram_scratch.robj); 1226 return r; 1227 } 1228 r = radeon_bo_pin(rdev->vram_scratch.robj, 1229 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1230 if (r) { 1231 radeon_bo_unreserve(rdev->vram_scratch.robj); 1232 radeon_bo_unref(&rdev->vram_scratch.robj); 1233 return r; 1234 } 1235 vram_scratch_ptr_ptr = &rdev->vram_scratch.ptr; 1236 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1237 vram_scratch_ptr_ptr); 1238 if (r) 1239 radeon_bo_unpin(rdev->vram_scratch.robj); 1240 radeon_bo_unreserve(rdev->vram_scratch.robj); 1241 if (r) 1242 radeon_bo_unref(&rdev->vram_scratch.robj); 1243 1244 return r; 1245} 1246 1247void r600_vram_scratch_fini(struct radeon_device *rdev) 1248{ 1249 int r; 1250 1251 if (rdev->vram_scratch.robj == NULL) { 1252 return; 1253 } 1254 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1255 if (likely(r == 0)) { 1256 radeon_bo_kunmap(rdev->vram_scratch.robj); 1257 radeon_bo_unpin(rdev->vram_scratch.robj); 1258 radeon_bo_unreserve(rdev->vram_scratch.robj); 1259 } 1260 radeon_bo_unref(&rdev->vram_scratch.robj); 1261} 1262 1263/* We doesn't check that the GPU really needs a reset we simply do the 1264 * reset, it's up to the caller to determine if the GPU needs one. We 1265 * might add an helper function to check that. 1266 */ 1267static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev) 1268{ 1269 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | 1270 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | 1271 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | 1272 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | 1273 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | 1274 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | 1275 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | 1276 S_008010_GUI_ACTIVE(1); 1277 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | 1278 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | 1279 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | 1280 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | 1281 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | 1282 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | 1283 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | 1284 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); 1285 u32 tmp; 1286 1287 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 1288 return; 1289 1290 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1291 RREG32(R_008010_GRBM_STATUS)); 1292 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1293 RREG32(R_008014_GRBM_STATUS2)); 1294 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1295 RREG32(R_000E50_SRBM_STATUS)); 1296 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1297 RREG32(CP_STALLED_STAT1)); 1298 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1299 RREG32(CP_STALLED_STAT2)); 1300 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1301 RREG32(CP_BUSY_STAT)); 1302 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1303 RREG32(CP_STAT)); 1304 1305 /* Disable CP parsing/prefetching */ 1306 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1307 1308 /* Check if any of the rendering block is busy and reset it */ 1309 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || 1310 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { 1311 tmp = S_008020_SOFT_RESET_CR(1) | 1312 S_008020_SOFT_RESET_DB(1) | 1313 S_008020_SOFT_RESET_CB(1) | 1314 S_008020_SOFT_RESET_PA(1) | 1315 S_008020_SOFT_RESET_SC(1) | 1316 S_008020_SOFT_RESET_SMX(1) | 1317 S_008020_SOFT_RESET_SPI(1) | 1318 S_008020_SOFT_RESET_SX(1) | 1319 S_008020_SOFT_RESET_SH(1) | 1320 S_008020_SOFT_RESET_TC(1) | 1321 S_008020_SOFT_RESET_TA(1) | 1322 S_008020_SOFT_RESET_VC(1) | 1323 S_008020_SOFT_RESET_VGT(1); 1324 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1325 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1326 RREG32(R_008020_GRBM_SOFT_RESET); 1327 DRM_MDELAY(15); 1328 WREG32(R_008020_GRBM_SOFT_RESET, 0); 1329 } 1330 /* Reset CP (we always reset CP) */ 1331 tmp = S_008020_SOFT_RESET_CP(1); 1332 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1333 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1334 RREG32(R_008020_GRBM_SOFT_RESET); 1335 DRM_MDELAY(15); 1336 WREG32(R_008020_GRBM_SOFT_RESET, 0); 1337 1338 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1339 RREG32(R_008010_GRBM_STATUS)); 1340 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1341 RREG32(R_008014_GRBM_STATUS2)); 1342 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1343 RREG32(R_000E50_SRBM_STATUS)); 1344 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1345 RREG32(CP_STALLED_STAT1)); 1346 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1347 RREG32(CP_STALLED_STAT2)); 1348 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1349 RREG32(CP_BUSY_STAT)); 1350 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1351 RREG32(CP_STAT)); 1352 1353} 1354 1355static void r600_gpu_soft_reset_dma(struct radeon_device *rdev) 1356{ 1357 u32 tmp; 1358 1359 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 1360 return; 1361 1362 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1363 RREG32(DMA_STATUS_REG)); 1364 1365 /* Disable DMA */ 1366 tmp = RREG32(DMA_RB_CNTL); 1367 tmp &= ~DMA_RB_ENABLE; 1368 WREG32(DMA_RB_CNTL, tmp); 1369 1370 /* Reset dma */ 1371 if (rdev->family >= CHIP_RV770) 1372 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA); 1373 else 1374 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); 1375 RREG32(SRBM_SOFT_RESET); 1376 DRM_UDELAY(50); 1377 WREG32(SRBM_SOFT_RESET, 0); 1378 1379 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1380 RREG32(DMA_STATUS_REG)); 1381} 1382 1383static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1384{ 1385 struct rv515_mc_save save; 1386 1387 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 1388 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE); 1389 1390 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 1391 reset_mask &= ~RADEON_RESET_DMA; 1392 1393 if (reset_mask == 0) 1394 return 0; 1395 1396 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1397 1398 rv515_mc_stop(rdev, &save); 1399 if (r600_mc_wait_for_idle(rdev)) { 1400 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1401 } 1402 1403 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) 1404 r600_gpu_soft_reset_gfx(rdev); 1405 1406 if (reset_mask & RADEON_RESET_DMA) 1407 r600_gpu_soft_reset_dma(rdev); 1408 1409 /* Wait a little for things to settle down */ 1410 DRM_MDELAY(1); 1411 1412 rv515_mc_resume(rdev, &save); 1413 return 0; 1414} 1415 1416bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1417{ 1418 u32 srbm_status; 1419 u32 grbm_status; 1420 u32 grbm_status2; 1421 1422 srbm_status = RREG32(R_000E50_SRBM_STATUS); 1423 grbm_status = RREG32(R_008010_GRBM_STATUS); 1424 grbm_status2 = RREG32(R_008014_GRBM_STATUS2); 1425 if (!G_008010_GUI_ACTIVE(grbm_status)) { 1426 radeon_ring_lockup_update(ring); 1427 return false; 1428 } 1429 /* force CP activities */ 1430 radeon_ring_force_activity(rdev, ring); 1431 return radeon_ring_test_lockup(rdev, ring); 1432} 1433 1434/** 1435 * r600_dma_is_lockup - Check if the DMA engine is locked up 1436 * 1437 * @rdev: radeon_device pointer 1438 * @ring: radeon_ring structure holding ring information 1439 * 1440 * Check if the async DMA engine is locked up (r6xx-evergreen). 1441 * Returns true if the engine appears to be locked up, false if not. 1442 */ 1443bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1444{ 1445 u32 dma_status_reg; 1446 1447 dma_status_reg = RREG32(DMA_STATUS_REG); 1448 if (dma_status_reg & DMA_IDLE) { 1449 radeon_ring_lockup_update(ring); 1450 return false; 1451 } 1452 /* force ring activities */ 1453 radeon_ring_force_activity(rdev, ring); 1454 return radeon_ring_test_lockup(rdev, ring); 1455} 1456 1457int r600_asic_reset(struct radeon_device *rdev) 1458{ 1459 return r600_gpu_soft_reset(rdev, (RADEON_RESET_GFX | 1460 RADEON_RESET_COMPUTE | 1461 RADEON_RESET_DMA)); 1462} 1463 1464u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1465 u32 tiling_pipe_num, 1466 u32 max_rb_num, 1467 u32 total_max_rb_num, 1468 u32 disabled_rb_mask) 1469{ 1470 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1471 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1472 u32 data = 0, mask = 1 << (max_rb_num - 1); 1473 unsigned i, j; 1474 1475 /* mask out the RBs that don't exist on that asic */ 1476 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1477 /* make sure at least one RB is available */ 1478 if ((tmp & 0xff) != 0xff) 1479 disabled_rb_mask = tmp; 1480 1481 rendering_pipe_num = 1 << tiling_pipe_num; 1482 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1483 KASSERT(rendering_pipe_num >= req_rb_num, ("rendering_pipe_num < req_rb_num")); 1484 1485 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1486 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1487 1488 if (rdev->family <= CHIP_RV740) { 1489 /* r6xx/r7xx */ 1490 rb_num_width = 2; 1491 } else { 1492 /* eg+ */ 1493 rb_num_width = 4; 1494 } 1495 1496 for (i = 0; i < max_rb_num; i++) { 1497 if (!(mask & disabled_rb_mask)) { 1498 for (j = 0; j < pipe_rb_ratio; j++) { 1499 data <<= rb_num_width; 1500 data |= max_rb_num - i - 1; 1501 } 1502 if (pipe_rb_remain) { 1503 data <<= rb_num_width; 1504 data |= max_rb_num - i - 1; 1505 pipe_rb_remain--; 1506 } 1507 } 1508 mask >>= 1; 1509 } 1510 1511 return data; 1512} 1513 1514int r600_count_pipe_bits(uint32_t val) 1515{ 1516 return hweight32(val); 1517} 1518 1519static void r600_gpu_init(struct radeon_device *rdev) 1520{ 1521 u32 tiling_config; 1522 u32 ramcfg; 1523 u32 cc_rb_backend_disable; 1524 u32 cc_gc_shader_pipe_config; 1525 u32 tmp; 1526 int i, j; 1527 u32 sq_config; 1528 u32 sq_gpr_resource_mgmt_1 = 0; 1529 u32 sq_gpr_resource_mgmt_2 = 0; 1530 u32 sq_thread_resource_mgmt = 0; 1531 u32 sq_stack_resource_mgmt_1 = 0; 1532 u32 sq_stack_resource_mgmt_2 = 0; 1533 u32 disabled_rb_mask; 1534 1535 rdev->config.r600.tiling_group_size = 256; 1536 switch (rdev->family) { 1537 case CHIP_R600: 1538 rdev->config.r600.max_pipes = 4; 1539 rdev->config.r600.max_tile_pipes = 8; 1540 rdev->config.r600.max_simds = 4; 1541 rdev->config.r600.max_backends = 4; 1542 rdev->config.r600.max_gprs = 256; 1543 rdev->config.r600.max_threads = 192; 1544 rdev->config.r600.max_stack_entries = 256; 1545 rdev->config.r600.max_hw_contexts = 8; 1546 rdev->config.r600.max_gs_threads = 16; 1547 rdev->config.r600.sx_max_export_size = 128; 1548 rdev->config.r600.sx_max_export_pos_size = 16; 1549 rdev->config.r600.sx_max_export_smx_size = 128; 1550 rdev->config.r600.sq_num_cf_insts = 2; 1551 break; 1552 case CHIP_RV630: 1553 case CHIP_RV635: 1554 rdev->config.r600.max_pipes = 2; 1555 rdev->config.r600.max_tile_pipes = 2; 1556 rdev->config.r600.max_simds = 3; 1557 rdev->config.r600.max_backends = 1; 1558 rdev->config.r600.max_gprs = 128; 1559 rdev->config.r600.max_threads = 192; 1560 rdev->config.r600.max_stack_entries = 128; 1561 rdev->config.r600.max_hw_contexts = 8; 1562 rdev->config.r600.max_gs_threads = 4; 1563 rdev->config.r600.sx_max_export_size = 128; 1564 rdev->config.r600.sx_max_export_pos_size = 16; 1565 rdev->config.r600.sx_max_export_smx_size = 128; 1566 rdev->config.r600.sq_num_cf_insts = 2; 1567 break; 1568 case CHIP_RV610: 1569 case CHIP_RV620: 1570 case CHIP_RS780: 1571 case CHIP_RS880: 1572 rdev->config.r600.max_pipes = 1; 1573 rdev->config.r600.max_tile_pipes = 1; 1574 rdev->config.r600.max_simds = 2; 1575 rdev->config.r600.max_backends = 1; 1576 rdev->config.r600.max_gprs = 128; 1577 rdev->config.r600.max_threads = 192; 1578 rdev->config.r600.max_stack_entries = 128; 1579 rdev->config.r600.max_hw_contexts = 4; 1580 rdev->config.r600.max_gs_threads = 4; 1581 rdev->config.r600.sx_max_export_size = 128; 1582 rdev->config.r600.sx_max_export_pos_size = 16; 1583 rdev->config.r600.sx_max_export_smx_size = 128; 1584 rdev->config.r600.sq_num_cf_insts = 1; 1585 break; 1586 case CHIP_RV670: 1587 rdev->config.r600.max_pipes = 4; 1588 rdev->config.r600.max_tile_pipes = 4; 1589 rdev->config.r600.max_simds = 4; 1590 rdev->config.r600.max_backends = 4; 1591 rdev->config.r600.max_gprs = 192; 1592 rdev->config.r600.max_threads = 192; 1593 rdev->config.r600.max_stack_entries = 256; 1594 rdev->config.r600.max_hw_contexts = 8; 1595 rdev->config.r600.max_gs_threads = 16; 1596 rdev->config.r600.sx_max_export_size = 128; 1597 rdev->config.r600.sx_max_export_pos_size = 16; 1598 rdev->config.r600.sx_max_export_smx_size = 128; 1599 rdev->config.r600.sq_num_cf_insts = 2; 1600 break; 1601 default: 1602 break; 1603 } 1604 1605 /* Initialize HDP */ 1606 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1607 WREG32((0x2c14 + j), 0x00000000); 1608 WREG32((0x2c18 + j), 0x00000000); 1609 WREG32((0x2c1c + j), 0x00000000); 1610 WREG32((0x2c20 + j), 0x00000000); 1611 WREG32((0x2c24 + j), 0x00000000); 1612 } 1613 1614 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1615 1616 /* Setup tiling */ 1617 tiling_config = 0; 1618 ramcfg = RREG32(RAMCFG); 1619 switch (rdev->config.r600.max_tile_pipes) { 1620 case 1: 1621 tiling_config |= PIPE_TILING(0); 1622 break; 1623 case 2: 1624 tiling_config |= PIPE_TILING(1); 1625 break; 1626 case 4: 1627 tiling_config |= PIPE_TILING(2); 1628 break; 1629 case 8: 1630 tiling_config |= PIPE_TILING(3); 1631 break; 1632 default: 1633 break; 1634 } 1635 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 1636 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1637 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1638 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1639 1640 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 1641 if (tmp > 3) { 1642 tiling_config |= ROW_TILING(3); 1643 tiling_config |= SAMPLE_SPLIT(3); 1644 } else { 1645 tiling_config |= ROW_TILING(tmp); 1646 tiling_config |= SAMPLE_SPLIT(tmp); 1647 } 1648 tiling_config |= BANK_SWAPS(1); 1649 1650 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1651 tmp = R6XX_MAX_BACKENDS - 1652 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK); 1653 if (tmp < rdev->config.r600.max_backends) { 1654 rdev->config.r600.max_backends = tmp; 1655 } 1656 1657 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 1658 tmp = R6XX_MAX_PIPES - 1659 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK); 1660 if (tmp < rdev->config.r600.max_pipes) { 1661 rdev->config.r600.max_pipes = tmp; 1662 } 1663 tmp = R6XX_MAX_SIMDS - 1664 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 1665 if (tmp < rdev->config.r600.max_simds) { 1666 rdev->config.r600.max_simds = tmp; 1667 } 1668 1669 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 1670 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 1671 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 1672 R6XX_MAX_BACKENDS, disabled_rb_mask); 1673 tiling_config |= tmp << 16; 1674 rdev->config.r600.backend_map = tmp; 1675 1676 rdev->config.r600.tile_config = tiling_config; 1677 WREG32(GB_TILING_CONFIG, tiling_config); 1678 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 1679 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 1680 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 1681 1682 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1683 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 1684 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1685 1686 /* Setup some CP states */ 1687 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 1688 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 1689 1690 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 1691 SYNC_WALKER | SYNC_ALIGNER)); 1692 /* Setup various GPU states */ 1693 if (rdev->family == CHIP_RV670) 1694 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 1695 1696 tmp = RREG32(SX_DEBUG_1); 1697 tmp |= SMX_EVENT_RELEASE; 1698 if ((rdev->family > CHIP_R600)) 1699 tmp |= ENABLE_NEW_SMX_ADDRESS; 1700 WREG32(SX_DEBUG_1, tmp); 1701 1702 if (((rdev->family) == CHIP_R600) || 1703 ((rdev->family) == CHIP_RV630) || 1704 ((rdev->family) == CHIP_RV610) || 1705 ((rdev->family) == CHIP_RV620) || 1706 ((rdev->family) == CHIP_RS780) || 1707 ((rdev->family) == CHIP_RS880)) { 1708 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 1709 } else { 1710 WREG32(DB_DEBUG, 0); 1711 } 1712 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 1713 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 1714 1715 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1716 WREG32(VGT_NUM_INSTANCES, 0); 1717 1718 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 1719 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 1720 1721 tmp = RREG32(SQ_MS_FIFO_SIZES); 1722 if (((rdev->family) == CHIP_RV610) || 1723 ((rdev->family) == CHIP_RV620) || 1724 ((rdev->family) == CHIP_RS780) || 1725 ((rdev->family) == CHIP_RS880)) { 1726 tmp = (CACHE_FIFO_SIZE(0xa) | 1727 FETCH_FIFO_HIWATER(0xa) | 1728 DONE_FIFO_HIWATER(0xe0) | 1729 ALU_UPDATE_FIFO_HIWATER(0x8)); 1730 } else if (((rdev->family) == CHIP_R600) || 1731 ((rdev->family) == CHIP_RV630)) { 1732 tmp &= ~DONE_FIFO_HIWATER(0xff); 1733 tmp |= DONE_FIFO_HIWATER(0x4); 1734 } 1735 WREG32(SQ_MS_FIFO_SIZES, tmp); 1736 1737 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1738 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1739 */ 1740 sq_config = RREG32(SQ_CONFIG); 1741 sq_config &= ~(PS_PRIO(3) | 1742 VS_PRIO(3) | 1743 GS_PRIO(3) | 1744 ES_PRIO(3)); 1745 sq_config |= (DX9_CONSTS | 1746 VC_ENABLE | 1747 PS_PRIO(0) | 1748 VS_PRIO(1) | 1749 GS_PRIO(2) | 1750 ES_PRIO(3)); 1751 1752 if ((rdev->family) == CHIP_R600) { 1753 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 1754 NUM_VS_GPRS(124) | 1755 NUM_CLAUSE_TEMP_GPRS(4)); 1756 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 1757 NUM_ES_GPRS(0)); 1758 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 1759 NUM_VS_THREADS(48) | 1760 NUM_GS_THREADS(4) | 1761 NUM_ES_THREADS(4)); 1762 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 1763 NUM_VS_STACK_ENTRIES(128)); 1764 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 1765 NUM_ES_STACK_ENTRIES(0)); 1766 } else if (((rdev->family) == CHIP_RV610) || 1767 ((rdev->family) == CHIP_RV620) || 1768 ((rdev->family) == CHIP_RS780) || 1769 ((rdev->family) == CHIP_RS880)) { 1770 /* no vertex cache */ 1771 sq_config &= ~VC_ENABLE; 1772 1773 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1774 NUM_VS_GPRS(44) | 1775 NUM_CLAUSE_TEMP_GPRS(2)); 1776 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1777 NUM_ES_GPRS(17)); 1778 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1779 NUM_VS_THREADS(78) | 1780 NUM_GS_THREADS(4) | 1781 NUM_ES_THREADS(31)); 1782 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1783 NUM_VS_STACK_ENTRIES(40)); 1784 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1785 NUM_ES_STACK_ENTRIES(16)); 1786 } else if (((rdev->family) == CHIP_RV630) || 1787 ((rdev->family) == CHIP_RV635)) { 1788 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1789 NUM_VS_GPRS(44) | 1790 NUM_CLAUSE_TEMP_GPRS(2)); 1791 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 1792 NUM_ES_GPRS(18)); 1793 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1794 NUM_VS_THREADS(78) | 1795 NUM_GS_THREADS(4) | 1796 NUM_ES_THREADS(31)); 1797 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1798 NUM_VS_STACK_ENTRIES(40)); 1799 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1800 NUM_ES_STACK_ENTRIES(16)); 1801 } else if ((rdev->family) == CHIP_RV670) { 1802 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1803 NUM_VS_GPRS(44) | 1804 NUM_CLAUSE_TEMP_GPRS(2)); 1805 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1806 NUM_ES_GPRS(17)); 1807 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1808 NUM_VS_THREADS(78) | 1809 NUM_GS_THREADS(4) | 1810 NUM_ES_THREADS(31)); 1811 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 1812 NUM_VS_STACK_ENTRIES(64)); 1813 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 1814 NUM_ES_STACK_ENTRIES(64)); 1815 } 1816 1817 WREG32(SQ_CONFIG, sq_config); 1818 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1819 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1820 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1821 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1822 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1823 1824 if (((rdev->family) == CHIP_RV610) || 1825 ((rdev->family) == CHIP_RV620) || 1826 ((rdev->family) == CHIP_RS780) || 1827 ((rdev->family) == CHIP_RS880)) { 1828 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 1829 } else { 1830 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 1831 } 1832 1833 /* More default values. 2D/3D driver should adjust as needed */ 1834 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 1835 S1_X(0x4) | S1_Y(0xc))); 1836 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 1837 S1_X(0x2) | S1_Y(0x2) | 1838 S2_X(0xa) | S2_Y(0x6) | 1839 S3_X(0x6) | S3_Y(0xa))); 1840 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 1841 S1_X(0x4) | S1_Y(0xc) | 1842 S2_X(0x1) | S2_Y(0x6) | 1843 S3_X(0xa) | S3_Y(0xe))); 1844 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 1845 S5_X(0x0) | S5_Y(0x0) | 1846 S6_X(0xb) | S6_Y(0x4) | 1847 S7_X(0x7) | S7_Y(0x8))); 1848 1849 WREG32(VGT_STRMOUT_EN, 0); 1850 tmp = rdev->config.r600.max_pipes * 16; 1851 switch (rdev->family) { 1852 case CHIP_RV610: 1853 case CHIP_RV620: 1854 case CHIP_RS780: 1855 case CHIP_RS880: 1856 tmp += 32; 1857 break; 1858 case CHIP_RV670: 1859 tmp += 128; 1860 break; 1861 default: 1862 break; 1863 } 1864 if (tmp > 256) { 1865 tmp = 256; 1866 } 1867 WREG32(VGT_ES_PER_GS, 128); 1868 WREG32(VGT_GS_PER_ES, tmp); 1869 WREG32(VGT_GS_PER_VS, 2); 1870 WREG32(VGT_GS_VERTEX_REUSE, 16); 1871 1872 /* more default values. 2D/3D driver should adjust as needed */ 1873 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1874 WREG32(VGT_STRMOUT_EN, 0); 1875 WREG32(SX_MISC, 0); 1876 WREG32(PA_SC_MODE_CNTL, 0); 1877 WREG32(PA_SC_AA_CONFIG, 0); 1878 WREG32(PA_SC_LINE_STIPPLE, 0); 1879 WREG32(SPI_INPUT_Z, 0); 1880 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 1881 WREG32(CB_COLOR7_FRAG, 0); 1882 1883 /* Clear render buffer base addresses */ 1884 WREG32(CB_COLOR0_BASE, 0); 1885 WREG32(CB_COLOR1_BASE, 0); 1886 WREG32(CB_COLOR2_BASE, 0); 1887 WREG32(CB_COLOR3_BASE, 0); 1888 WREG32(CB_COLOR4_BASE, 0); 1889 WREG32(CB_COLOR5_BASE, 0); 1890 WREG32(CB_COLOR6_BASE, 0); 1891 WREG32(CB_COLOR7_BASE, 0); 1892 WREG32(CB_COLOR7_FRAG, 0); 1893 1894 switch (rdev->family) { 1895 case CHIP_RV610: 1896 case CHIP_RV620: 1897 case CHIP_RS780: 1898 case CHIP_RS880: 1899 tmp = TC_L2_SIZE(8); 1900 break; 1901 case CHIP_RV630: 1902 case CHIP_RV635: 1903 tmp = TC_L2_SIZE(4); 1904 break; 1905 case CHIP_R600: 1906 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 1907 break; 1908 default: 1909 tmp = TC_L2_SIZE(0); 1910 break; 1911 } 1912 WREG32(TC_CNTL, tmp); 1913 1914 tmp = RREG32(HDP_HOST_PATH_CNTL); 1915 WREG32(HDP_HOST_PATH_CNTL, tmp); 1916 1917 tmp = RREG32(ARB_POP); 1918 tmp |= ENABLE_TC128; 1919 WREG32(ARB_POP, tmp); 1920 1921 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1922 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 1923 NUM_CLIP_SEQ(3))); 1924 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 1925 WREG32(VC_ENHANCE, 0); 1926} 1927 1928 1929/* 1930 * Indirect registers accessor 1931 */ 1932u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 1933{ 1934 u32 r; 1935 1936 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1937 (void)RREG32(PCIE_PORT_INDEX); 1938 r = RREG32(PCIE_PORT_DATA); 1939 return r; 1940} 1941 1942void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 1943{ 1944 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1945 (void)RREG32(PCIE_PORT_INDEX); 1946 WREG32(PCIE_PORT_DATA, (v)); 1947 (void)RREG32(PCIE_PORT_DATA); 1948} 1949 1950/* 1951 * CP & Ring 1952 */ 1953void r600_cp_stop(struct radeon_device *rdev) 1954{ 1955 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1956 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1957 WREG32(SCRATCH_UMSK, 0); 1958 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1959} 1960 1961int r600_init_microcode(struct radeon_device *rdev) 1962{ 1963 const char *chip_name; 1964 const char *rlc_chip_name; 1965 size_t pfp_req_size, me_req_size, rlc_req_size; 1966 char fw_name[30]; 1967 int err; 1968 1969 DRM_DEBUG("\n"); 1970 1971 switch (rdev->family) { 1972 case CHIP_R600: 1973 chip_name = "R600"; 1974 rlc_chip_name = "R600"; 1975 break; 1976 case CHIP_RV610: 1977 chip_name = "RV610"; 1978 rlc_chip_name = "R600"; 1979 break; 1980 case CHIP_RV630: 1981 chip_name = "RV630"; 1982 rlc_chip_name = "R600"; 1983 break; 1984 case CHIP_RV620: 1985 chip_name = "RV620"; 1986 rlc_chip_name = "R600"; 1987 break; 1988 case CHIP_RV635: 1989 chip_name = "RV635"; 1990 rlc_chip_name = "R600"; 1991 break; 1992 case CHIP_RV670: 1993 chip_name = "RV670"; 1994 rlc_chip_name = "R600"; 1995 break; 1996 case CHIP_RS780: 1997 case CHIP_RS880: 1998 chip_name = "RS780"; 1999 rlc_chip_name = "R600"; 2000 break; 2001 case CHIP_RV770: 2002 chip_name = "RV770"; 2003 rlc_chip_name = "R700"; 2004 break; 2005 case CHIP_RV730: 2006 case CHIP_RV740: 2007 chip_name = "RV730"; 2008 rlc_chip_name = "R700"; 2009 break; 2010 case CHIP_RV710: 2011 chip_name = "RV710"; 2012 rlc_chip_name = "R700"; 2013 break; 2014 case CHIP_CEDAR: 2015 chip_name = "CEDAR"; 2016 rlc_chip_name = "CEDAR"; 2017 break; 2018 case CHIP_REDWOOD: 2019 chip_name = "REDWOOD"; 2020 rlc_chip_name = "REDWOOD"; 2021 break; 2022 case CHIP_JUNIPER: 2023 chip_name = "JUNIPER"; 2024 rlc_chip_name = "JUNIPER"; 2025 break; 2026 case CHIP_CYPRESS: 2027 case CHIP_HEMLOCK: 2028 chip_name = "CYPRESS"; 2029 rlc_chip_name = "CYPRESS"; 2030 break; 2031 case CHIP_PALM: 2032 chip_name = "PALM"; 2033 rlc_chip_name = "SUMO"; 2034 break; 2035 case CHIP_SUMO: 2036 chip_name = "SUMO"; 2037 rlc_chip_name = "SUMO"; 2038 break; 2039 case CHIP_SUMO2: 2040 chip_name = "SUMO2"; 2041 rlc_chip_name = "SUMO"; 2042 break; 2043 default: panic("%s: Unsupported family %d", __func__, rdev->family); 2044 } 2045 2046 if (rdev->family >= CHIP_CEDAR) { 2047 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2048 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2049 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2050 } else if (rdev->family >= CHIP_RV770) { 2051 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2052 me_req_size = R700_PM4_UCODE_SIZE * 4; 2053 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2054 } else { 2055 pfp_req_size = PFP_UCODE_SIZE * 4; 2056 me_req_size = PM4_UCODE_SIZE * 12; 2057 rlc_req_size = RLC_UCODE_SIZE * 4; 2058 } 2059 2060 DRM_INFO("Loading %s Microcode\n", chip_name); 2061 err = 0; 2062 2063 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name); 2064 rdev->pfp_fw = firmware_get(fw_name); 2065 if (rdev->pfp_fw == NULL) { 2066 err = -ENOENT; 2067 goto out; 2068 } 2069 if (rdev->pfp_fw->datasize != pfp_req_size) { 2070 DRM_ERROR( 2071 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2072 rdev->pfp_fw->datasize, fw_name); 2073 err = -EINVAL; 2074 goto out; 2075 } 2076 2077 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name); 2078 rdev->me_fw = firmware_get(fw_name); 2079 if (rdev->me_fw == NULL) { 2080 err = -ENOENT; 2081 goto out; 2082 } 2083 if (rdev->me_fw->datasize != me_req_size) { 2084 DRM_ERROR( 2085 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2086 rdev->me_fw->datasize, fw_name); 2087 err = -EINVAL; 2088 } 2089 2090 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", rlc_chip_name); 2091 rdev->rlc_fw = firmware_get(fw_name); 2092 if (rdev->rlc_fw == NULL) { 2093 err = -ENOENT; 2094 goto out; 2095 } 2096 if (rdev->rlc_fw->datasize != rlc_req_size) { 2097 DRM_ERROR( 2098 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2099 rdev->rlc_fw->datasize, fw_name); 2100 err = -EINVAL; 2101 } 2102 2103out: 2104 if (err) { 2105 if (err != -EINVAL) 2106 DRM_ERROR( 2107 "r600_cp: Failed to load firmware \"%s\"\n", 2108 fw_name); 2109 if (rdev->pfp_fw != NULL) { 2110 firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD); 2111 rdev->pfp_fw = NULL; 2112 } 2113 if (rdev->me_fw != NULL) { 2114 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD); 2115 rdev->me_fw = NULL; 2116 } 2117 if (rdev->rlc_fw != NULL) { 2118 firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD); 2119 rdev->rlc_fw = NULL; 2120 } 2121 } 2122 return err; 2123} 2124 2125/** 2126 * r600_fini_microcode - drop the firmwares image references 2127 * 2128 * @rdev: radeon_device pointer 2129 * 2130 * Drop the pfp, me and rlc firmwares image references. 2131 * Called at driver shutdown. 2132 */ 2133void r600_fini_microcode(struct radeon_device *rdev) 2134{ 2135 2136 if (rdev->pfp_fw != NULL) { 2137 firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD); 2138 rdev->pfp_fw = NULL; 2139 } 2140 2141 if (rdev->me_fw != NULL) { 2142 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD); 2143 rdev->me_fw = NULL; 2144 } 2145 2146 if (rdev->rlc_fw != NULL) { 2147 firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD); 2148 rdev->rlc_fw = NULL; 2149 } 2150} 2151 2152static int r600_cp_load_microcode(struct radeon_device *rdev) 2153{ 2154 const __be32 *fw_data; 2155 int i; 2156 2157 if (!rdev->me_fw || !rdev->pfp_fw) 2158 return -EINVAL; 2159 2160 r600_cp_stop(rdev); 2161 2162 WREG32(CP_RB_CNTL, 2163#ifdef __BIG_ENDIAN 2164 BUF_SWAP_32BIT | 2165#endif 2166 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2167 2168 /* Reset cp */ 2169 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2170 RREG32(GRBM_SOFT_RESET); 2171 DRM_MDELAY(15); 2172 WREG32(GRBM_SOFT_RESET, 0); 2173 2174 WREG32(CP_ME_RAM_WADDR, 0); 2175 2176 fw_data = (const __be32 *)rdev->me_fw->data; 2177 WREG32(CP_ME_RAM_WADDR, 0); 2178 for (i = 0; i < PM4_UCODE_SIZE * 3; i++) 2179 WREG32(CP_ME_RAM_DATA, 2180 be32_to_cpup(fw_data++)); 2181 2182 fw_data = (const __be32 *)rdev->pfp_fw->data; 2183 WREG32(CP_PFP_UCODE_ADDR, 0); 2184 for (i = 0; i < PFP_UCODE_SIZE; i++) 2185 WREG32(CP_PFP_UCODE_DATA, 2186 be32_to_cpup(fw_data++)); 2187 2188 WREG32(CP_PFP_UCODE_ADDR, 0); 2189 WREG32(CP_ME_RAM_WADDR, 0); 2190 WREG32(CP_ME_RAM_RADDR, 0); 2191 return 0; 2192} 2193 2194int r600_cp_start(struct radeon_device *rdev) 2195{ 2196 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2197 int r; 2198 uint32_t cp_me; 2199 2200 r = radeon_ring_lock(rdev, ring, 7); 2201 if (r) { 2202 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2203 return r; 2204 } 2205 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2206 radeon_ring_write(ring, 0x1); 2207 if (rdev->family >= CHIP_RV770) { 2208 radeon_ring_write(ring, 0x0); 2209 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2210 } else { 2211 radeon_ring_write(ring, 0x3); 2212 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2213 } 2214 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2215 radeon_ring_write(ring, 0); 2216 radeon_ring_write(ring, 0); 2217 radeon_ring_unlock_commit(rdev, ring); 2218 2219 cp_me = 0xff; 2220 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2221 return 0; 2222} 2223 2224int r600_cp_resume(struct radeon_device *rdev) 2225{ 2226 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2227 u32 tmp; 2228 u32 rb_bufsz; 2229 int r; 2230 2231 /* Reset cp */ 2232 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2233 RREG32(GRBM_SOFT_RESET); 2234 DRM_MDELAY(15); 2235 WREG32(GRBM_SOFT_RESET, 0); 2236 2237 /* Set ring buffer size */ 2238 rb_bufsz = drm_order(ring->ring_size / 8); 2239 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2240#ifdef __BIG_ENDIAN 2241 tmp |= BUF_SWAP_32BIT; 2242#endif 2243 WREG32(CP_RB_CNTL, tmp); 2244 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2245 2246 /* Set the write pointer delay */ 2247 WREG32(CP_RB_WPTR_DELAY, 0); 2248 2249 /* Initialize the ring buffer's read and write pointers */ 2250 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2251 WREG32(CP_RB_RPTR_WR, 0); 2252 ring->wptr = 0; 2253 WREG32(CP_RB_WPTR, ring->wptr); 2254 2255 /* set the wb address whether it's enabled or not */ 2256 WREG32(CP_RB_RPTR_ADDR, 2257 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2258 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2259 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2260 2261 if (rdev->wb.enabled) 2262 WREG32(SCRATCH_UMSK, 0xff); 2263 else { 2264 tmp |= RB_NO_UPDATE; 2265 WREG32(SCRATCH_UMSK, 0); 2266 } 2267 2268 DRM_MDELAY(1); 2269 WREG32(CP_RB_CNTL, tmp); 2270 2271 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2272 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2273 2274 ring->rptr = RREG32(CP_RB_RPTR); 2275 2276 r600_cp_start(rdev); 2277 ring->ready = true; 2278 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2279 if (r) { 2280 ring->ready = false; 2281 return r; 2282 } 2283 return 0; 2284} 2285 2286void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2287{ 2288 u32 rb_bufsz; 2289 int r; 2290 2291 /* Align ring size */ 2292 rb_bufsz = drm_order(ring_size / 8); 2293 ring_size = (1 << (rb_bufsz + 1)) * 4; 2294 ring->ring_size = ring_size; 2295 ring->align_mask = 16 - 1; 2296 2297 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2298 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2299 if (r) { 2300 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2301 ring->rptr_save_reg = 0; 2302 } 2303 } 2304} 2305 2306void r600_cp_fini(struct radeon_device *rdev) 2307{ 2308 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2309 r600_cp_stop(rdev); 2310 radeon_ring_fini(rdev, ring); 2311 radeon_scratch_free(rdev, ring->rptr_save_reg); 2312} 2313 2314/* 2315 * DMA 2316 * Starting with R600, the GPU has an asynchronous 2317 * DMA engine. The programming model is very similar 2318 * to the 3D engine (ring buffer, IBs, etc.), but the 2319 * DMA controller has it's own packet format that is 2320 * different form the PM4 format used by the 3D engine. 2321 * It supports copying data, writing embedded data, 2322 * solid fills, and a number of other things. It also 2323 * has support for tiling/detiling of buffers. 2324 */ 2325/** 2326 * r600_dma_stop - stop the async dma engine 2327 * 2328 * @rdev: radeon_device pointer 2329 * 2330 * Stop the async dma engine (r6xx-evergreen). 2331 */ 2332void r600_dma_stop(struct radeon_device *rdev) 2333{ 2334 u32 rb_cntl = RREG32(DMA_RB_CNTL); 2335 2336 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2337 2338 rb_cntl &= ~DMA_RB_ENABLE; 2339 WREG32(DMA_RB_CNTL, rb_cntl); 2340 2341 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; 2342} 2343 2344/** 2345 * r600_dma_resume - setup and start the async dma engine 2346 * 2347 * @rdev: radeon_device pointer 2348 * 2349 * Set up the DMA ring buffer and enable it. (r6xx-evergreen). 2350 * Returns 0 for success, error for failure. 2351 */ 2352int r600_dma_resume(struct radeon_device *rdev) 2353{ 2354 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2355 u32 rb_cntl, dma_cntl, ib_cntl; 2356 u32 rb_bufsz; 2357 int r; 2358 2359 /* Reset dma */ 2360 if (rdev->family >= CHIP_RV770) 2361 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA); 2362 else 2363 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); 2364 RREG32(SRBM_SOFT_RESET); 2365 DRM_UDELAY(50); 2366 WREG32(SRBM_SOFT_RESET, 0); 2367 2368 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); 2369 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 2370 2371 /* Set ring buffer size in dwords */ 2372 rb_bufsz = drm_order(ring->ring_size / 4); 2373 rb_cntl = rb_bufsz << 1; 2374#ifdef __BIG_ENDIAN 2375 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; 2376#endif 2377 WREG32(DMA_RB_CNTL, rb_cntl); 2378 2379 /* Initialize the ring buffer's read and write pointers */ 2380 WREG32(DMA_RB_RPTR, 0); 2381 WREG32(DMA_RB_WPTR, 0); 2382 2383 /* set the wb address whether it's enabled or not */ 2384 WREG32(DMA_RB_RPTR_ADDR_HI, 2385 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); 2386 WREG32(DMA_RB_RPTR_ADDR_LO, 2387 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); 2388 2389 if (rdev->wb.enabled) 2390 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; 2391 2392 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); 2393 2394 /* enable DMA IBs */ 2395 ib_cntl = DMA_IB_ENABLE; 2396#ifdef __BIG_ENDIAN 2397 ib_cntl |= DMA_IB_SWAP_ENABLE; 2398#endif 2399 WREG32(DMA_IB_CNTL, ib_cntl); 2400 2401 dma_cntl = RREG32(DMA_CNTL); 2402 dma_cntl &= ~CTXEMPTY_INT_ENABLE; 2403 WREG32(DMA_CNTL, dma_cntl); 2404 2405 if (rdev->family >= CHIP_RV770) 2406 WREG32(DMA_MODE, 1); 2407 2408 ring->wptr = 0; 2409 WREG32(DMA_RB_WPTR, ring->wptr << 2); 2410 2411 ring->rptr = RREG32(DMA_RB_RPTR) >> 2; 2412 2413 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); 2414 2415 ring->ready = true; 2416 2417 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring); 2418 if (r) { 2419 ring->ready = false; 2420 return r; 2421 } 2422 2423 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2424 2425 return 0; 2426} 2427 2428/** 2429 * r600_dma_fini - tear down the async dma engine 2430 * 2431 * @rdev: radeon_device pointer 2432 * 2433 * Stop the async dma engine and free the ring (r6xx-evergreen). 2434 */ 2435void r600_dma_fini(struct radeon_device *rdev) 2436{ 2437 r600_dma_stop(rdev); 2438 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); 2439} 2440 2441/* 2442 * GPU scratch registers helpers function. 2443 */ 2444void r600_scratch_init(struct radeon_device *rdev) 2445{ 2446 int i; 2447 2448 rdev->scratch.num_reg = 7; 2449 rdev->scratch.reg_base = SCRATCH_REG0; 2450 for (i = 0; i < rdev->scratch.num_reg; i++) { 2451 rdev->scratch.free[i] = true; 2452 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2453 } 2454} 2455 2456int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2457{ 2458 uint32_t scratch; 2459 uint32_t tmp = 0; 2460 unsigned i; 2461 int r; 2462 2463 r = radeon_scratch_get(rdev, &scratch); 2464 if (r) { 2465 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2466 return r; 2467 } 2468 WREG32(scratch, 0xCAFEDEAD); 2469 r = radeon_ring_lock(rdev, ring, 3); 2470 if (r) { 2471 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2472 radeon_scratch_free(rdev, scratch); 2473 return r; 2474 } 2475 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2476 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2477 radeon_ring_write(ring, 0xDEADBEEF); 2478 radeon_ring_unlock_commit(rdev, ring); 2479 for (i = 0; i < rdev->usec_timeout; i++) { 2480 tmp = RREG32(scratch); 2481 if (tmp == 0xDEADBEEF) 2482 break; 2483 DRM_UDELAY(1); 2484 } 2485 if (i < rdev->usec_timeout) { 2486 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2487 } else { 2488 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2489 ring->idx, scratch, tmp); 2490 r = -EINVAL; 2491 } 2492 radeon_scratch_free(rdev, scratch); 2493 return r; 2494} 2495 2496/** 2497 * r600_dma_ring_test - simple async dma engine test 2498 * 2499 * @rdev: radeon_device pointer 2500 * @ring: radeon_ring structure holding ring information 2501 * 2502 * Test the DMA engine by writing using it to write an 2503 * value to memory. (r6xx-SI). 2504 * Returns 0 for success, error for failure. 2505 */ 2506int r600_dma_ring_test(struct radeon_device *rdev, 2507 struct radeon_ring *ring) 2508{ 2509 unsigned i; 2510 int r; 2511 volatile uint32_t *ptr = rdev->vram_scratch.ptr; 2512 u32 tmp; 2513 2514 if (!ptr) { 2515 DRM_ERROR("invalid vram scratch pointer\n"); 2516 return -EINVAL; 2517 } 2518 2519 tmp = 0xCAFEDEAD; 2520 *ptr = tmp; 2521 2522 r = radeon_ring_lock(rdev, ring, 4); 2523 if (r) { 2524 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); 2525 return r; 2526 } 2527 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 2528 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); 2529 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); 2530 radeon_ring_write(ring, 0xDEADBEEF); 2531 radeon_ring_unlock_commit(rdev, ring); 2532 2533 for (i = 0; i < rdev->usec_timeout; i++) { 2534 tmp = *ptr; 2535 if (tmp == 0xDEADBEEF) 2536 break; 2537 DRM_UDELAY(1); 2538 } 2539 2540 if (i < rdev->usec_timeout) { 2541 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2542 } else { 2543 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 2544 ring->idx, tmp); 2545 r = -EINVAL; 2546 } 2547 return r; 2548} 2549 2550/* 2551 * CP fences/semaphores 2552 */ 2553 2554void r600_fence_ring_emit(struct radeon_device *rdev, 2555 struct radeon_fence *fence) 2556{ 2557 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2558 2559 if (rdev->wb.use_event) { 2560 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2561 /* flush read cache over gart */ 2562 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2563 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2564 PACKET3_VC_ACTION_ENA | 2565 PACKET3_SH_ACTION_ENA); 2566 radeon_ring_write(ring, 0xFFFFFFFF); 2567 radeon_ring_write(ring, 0); 2568 radeon_ring_write(ring, 10); /* poll interval */ 2569 /* EVENT_WRITE_EOP - flush caches, send int */ 2570 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2571 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2572 radeon_ring_write(ring, addr & 0xffffffff); 2573 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2574 radeon_ring_write(ring, fence->seq); 2575 radeon_ring_write(ring, 0); 2576 } else { 2577 /* flush read cache over gart */ 2578 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2579 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2580 PACKET3_VC_ACTION_ENA | 2581 PACKET3_SH_ACTION_ENA); 2582 radeon_ring_write(ring, 0xFFFFFFFF); 2583 radeon_ring_write(ring, 0); 2584 radeon_ring_write(ring, 10); /* poll interval */ 2585 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2586 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2587 /* wait for 3D idle clean */ 2588 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2589 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2590 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2591 /* Emit fence sequence & fire IRQ */ 2592 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2593 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2594 radeon_ring_write(ring, fence->seq); 2595 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2596 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 2597 radeon_ring_write(ring, RB_INT_STAT); 2598 } 2599} 2600 2601void r600_semaphore_ring_emit(struct radeon_device *rdev, 2602 struct radeon_ring *ring, 2603 struct radeon_semaphore *semaphore, 2604 bool emit_wait) 2605{ 2606 uint64_t addr = semaphore->gpu_addr; 2607 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 2608 2609 if (rdev->family < CHIP_CAYMAN) 2610 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 2611 2612 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2613 radeon_ring_write(ring, addr & 0xffffffff); 2614 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 2615} 2616 2617/* 2618 * DMA fences/semaphores 2619 */ 2620 2621/** 2622 * r600_dma_fence_ring_emit - emit a fence on the DMA ring 2623 * 2624 * @rdev: radeon_device pointer 2625 * @fence: radeon fence object 2626 * 2627 * Add a DMA fence packet to the ring to write 2628 * the fence seq number and DMA trap packet to generate 2629 * an interrupt if needed (r6xx-r7xx). 2630 */ 2631void r600_dma_fence_ring_emit(struct radeon_device *rdev, 2632 struct radeon_fence *fence) 2633{ 2634 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2635 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2636 2637 /* write the fence */ 2638 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); 2639 radeon_ring_write(ring, addr & 0xfffffffc); 2640 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); 2641 radeon_ring_write(ring, lower_32_bits(fence->seq)); 2642 /* generate an interrupt */ 2643 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); 2644} 2645 2646/** 2647 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring 2648 * 2649 * @rdev: radeon_device pointer 2650 * @ring: radeon_ring structure holding ring information 2651 * @semaphore: radeon semaphore object 2652 * @emit_wait: wait or signal semaphore 2653 * 2654 * Add a DMA semaphore packet to the ring wait on or signal 2655 * other rings (r6xx-SI). 2656 */ 2657void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 2658 struct radeon_ring *ring, 2659 struct radeon_semaphore *semaphore, 2660 bool emit_wait) 2661{ 2662 u64 addr = semaphore->gpu_addr; 2663 u32 s = emit_wait ? 0 : 1; 2664 2665 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0)); 2666 radeon_ring_write(ring, addr & 0xfffffffc); 2667 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 2668} 2669 2670int r600_copy_blit(struct radeon_device *rdev, 2671 uint64_t src_offset, 2672 uint64_t dst_offset, 2673 unsigned num_gpu_pages, 2674 struct radeon_fence **fence) 2675{ 2676 struct radeon_semaphore *sem = NULL; 2677 struct radeon_sa_bo *vb = NULL; 2678 int r; 2679 2680 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem); 2681 if (r) { 2682 return r; 2683 } 2684 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb); 2685 r600_blit_done_copy(rdev, fence, vb, sem); 2686 return 0; 2687} 2688 2689/** 2690 * r600_copy_dma - copy pages using the DMA engine 2691 * 2692 * @rdev: radeon_device pointer 2693 * @src_offset: src GPU address 2694 * @dst_offset: dst GPU address 2695 * @num_gpu_pages: number of GPU pages to xfer 2696 * @fence: radeon fence object 2697 * 2698 * Copy GPU paging using the DMA engine (r6xx). 2699 * Used by the radeon ttm implementation to move pages if 2700 * registered as the asic copy callback. 2701 */ 2702int r600_copy_dma(struct radeon_device *rdev, 2703 uint64_t src_offset, uint64_t dst_offset, 2704 unsigned num_gpu_pages, 2705 struct radeon_fence **fence) 2706{ 2707 struct radeon_semaphore *sem = NULL; 2708 int ring_index = rdev->asic->copy.dma_ring_index; 2709 struct radeon_ring *ring = &rdev->ring[ring_index]; 2710 u32 size_in_dw, cur_size_in_dw; 2711 int i, num_loops; 2712 int r = 0; 2713 2714 r = radeon_semaphore_create(rdev, &sem); 2715 if (r) { 2716 DRM_ERROR("radeon: moving bo (%d).\n", r); 2717 return r; 2718 } 2719 2720 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; 2721 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE); 2722 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8); 2723 if (r) { 2724 DRM_ERROR("radeon: moving bo (%d).\n", r); 2725 radeon_semaphore_free(rdev, &sem, NULL); 2726 return r; 2727 } 2728 2729 if (radeon_fence_need_sync(*fence, ring->idx)) { 2730 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 2731 ring->idx); 2732 radeon_fence_note_sync(*fence, ring->idx); 2733 } else { 2734 radeon_semaphore_free(rdev, &sem, NULL); 2735 } 2736 2737 for (i = 0; i < num_loops; i++) { 2738 cur_size_in_dw = size_in_dw; 2739 if (cur_size_in_dw > 0xFFFE) 2740 cur_size_in_dw = 0xFFFE; 2741 size_in_dw -= cur_size_in_dw; 2742 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); 2743 radeon_ring_write(ring, dst_offset & 0xfffffffc); 2744 radeon_ring_write(ring, src_offset & 0xfffffffc); 2745 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | 2746 (upper_32_bits(src_offset) & 0xff))); 2747 src_offset += cur_size_in_dw * 4; 2748 dst_offset += cur_size_in_dw * 4; 2749 } 2750 2751 r = radeon_fence_emit(rdev, fence, ring->idx); 2752 if (r) { 2753 radeon_ring_unlock_undo(rdev, ring); 2754 return r; 2755 } 2756 2757 radeon_ring_unlock_commit(rdev, ring); 2758 radeon_semaphore_free(rdev, &sem, *fence); 2759 2760 return r; 2761} 2762 2763int r600_set_surface_reg(struct radeon_device *rdev, int reg, 2764 uint32_t tiling_flags, uint32_t pitch, 2765 uint32_t offset, uint32_t obj_size) 2766{ 2767 /* FIXME: implement */ 2768 return 0; 2769} 2770 2771void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 2772{ 2773 /* FIXME: implement */ 2774} 2775 2776static int r600_startup(struct radeon_device *rdev) 2777{ 2778 struct radeon_ring *ring; 2779 int r; 2780 2781 /* enable pcie gen2 link */ 2782 r600_pcie_gen2_enable(rdev); 2783 2784 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2785 r = r600_init_microcode(rdev); 2786 if (r) { 2787 DRM_ERROR("Failed to load firmware!\n"); 2788 return r; 2789 } 2790 } 2791 2792 r = r600_vram_scratch_init(rdev); 2793 if (r) 2794 return r; 2795 2796 r600_mc_program(rdev); 2797 if (rdev->flags & RADEON_IS_AGP) { 2798 r600_agp_enable(rdev); 2799 } else { 2800 r = r600_pcie_gart_enable(rdev); 2801 if (r) 2802 return r; 2803 } 2804 r600_gpu_init(rdev); 2805 r = r600_blit_init(rdev); 2806 if (r) { 2807 r600_blit_fini(rdev); 2808 rdev->asic->copy.copy = NULL; 2809 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 2810 } 2811 2812 /* allocate wb buffer */ 2813 r = radeon_wb_init(rdev); 2814 if (r) 2815 return r; 2816 2817 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 2818 if (r) { 2819 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2820 return r; 2821 } 2822 2823 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 2824 if (r) { 2825 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 2826 return r; 2827 } 2828 2829 /* Enable IRQ */ 2830 r = r600_irq_init(rdev); 2831 if (r) { 2832 DRM_ERROR("radeon: IH init failed (%d).\n", r); 2833 radeon_irq_kms_fini(rdev); 2834 return r; 2835 } 2836 r600_irq_set(rdev); 2837 2838 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2839 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 2840 R600_CP_RB_RPTR, R600_CP_RB_WPTR, 2841 0, 0xfffff, RADEON_CP_PACKET2); 2842 if (r) 2843 return r; 2844 2845 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2846 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 2847 DMA_RB_RPTR, DMA_RB_WPTR, 2848 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2849 if (r) 2850 return r; 2851 2852 r = r600_cp_load_microcode(rdev); 2853 if (r) 2854 return r; 2855 r = r600_cp_resume(rdev); 2856 if (r) 2857 return r; 2858 2859 r = r600_dma_resume(rdev); 2860 if (r) 2861 return r; 2862 2863 r = radeon_ib_pool_init(rdev); 2864 if (r) { 2865 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 2866 return r; 2867 } 2868 2869 r = r600_audio_init(rdev); 2870 if (r) { 2871 DRM_ERROR("radeon: audio init failed\n"); 2872 return r; 2873 } 2874 2875 return 0; 2876} 2877 2878void r600_vga_set_state(struct radeon_device *rdev, bool state) 2879{ 2880 uint32_t temp; 2881 2882 temp = RREG32(CONFIG_CNTL); 2883 if (state == false) { 2884 temp &= ~(1<<0); 2885 temp |= (1<<1); 2886 } else { 2887 temp &= ~(1<<1); 2888 } 2889 WREG32(CONFIG_CNTL, temp); 2890} 2891 2892int r600_resume(struct radeon_device *rdev) 2893{ 2894 int r; 2895 2896 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 2897 * posting will perform necessary task to bring back GPU into good 2898 * shape. 2899 */ 2900 /* post card */ 2901 atom_asic_init(rdev->mode_info.atom_context); 2902 2903 rdev->accel_working = true; 2904 r = r600_startup(rdev); 2905 if (r) { 2906 DRM_ERROR("r600 startup failed on resume\n"); 2907 rdev->accel_working = false; 2908 return r; 2909 } 2910 2911 return r; 2912} 2913 2914int r600_suspend(struct radeon_device *rdev) 2915{ 2916 r600_audio_fini(rdev); 2917 r600_cp_stop(rdev); 2918 r600_dma_stop(rdev); 2919 r600_irq_suspend(rdev); 2920 radeon_wb_disable(rdev); 2921 r600_pcie_gart_disable(rdev); 2922 2923 return 0; 2924} 2925 2926/* Plan is to move initialization in that function and use 2927 * helper function so that radeon_device_init pretty much 2928 * do nothing more than calling asic specific function. This 2929 * should also allow to remove a bunch of callback function 2930 * like vram_info. 2931 */ 2932int r600_init(struct radeon_device *rdev) 2933{ 2934 int r; 2935 2936 if (r600_debugfs_mc_info_init(rdev)) { 2937 DRM_ERROR("Failed to register debugfs file for mc !\n"); 2938 } 2939 /* Read BIOS */ 2940 if (!radeon_get_bios(rdev)) { 2941 if (ASIC_IS_AVIVO(rdev)) 2942 return -EINVAL; 2943 } 2944 /* Must be an ATOMBIOS */ 2945 if (!rdev->is_atom_bios) { 2946 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 2947 return -EINVAL; 2948 } 2949 r = radeon_atombios_init(rdev); 2950 if (r) 2951 return r; 2952 /* Post card if necessary */ 2953 if (!radeon_card_posted(rdev)) { 2954 if (!rdev->bios) { 2955 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 2956 return -EINVAL; 2957 } 2958 DRM_INFO("GPU not posted. posting now...\n"); 2959 atom_asic_init(rdev->mode_info.atom_context); 2960 } 2961 /* Initialize scratch registers */ 2962 r600_scratch_init(rdev); 2963 /* Initialize surface registers */ 2964 radeon_surface_init(rdev); 2965 /* Initialize clocks */ 2966 radeon_get_clock_info(rdev->ddev); 2967 /* Fence driver */ 2968 r = radeon_fence_driver_init(rdev); 2969 if (r) 2970 return r; 2971 if (rdev->flags & RADEON_IS_AGP) { 2972 r = radeon_agp_init(rdev); 2973 if (r) 2974 radeon_agp_disable(rdev); 2975 } 2976 r = r600_mc_init(rdev); 2977 if (r) 2978 return r; 2979 /* Memory manager */ 2980 r = radeon_bo_init(rdev); 2981 if (r) 2982 return r; 2983 2984 r = radeon_irq_kms_init(rdev); 2985 if (r) 2986 return r; 2987 2988 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 2989 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 2990 2991 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 2992 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 2993 2994 rdev->ih.ring_obj = NULL; 2995 r600_ih_ring_init(rdev, 64 * 1024); 2996 2997 r = r600_pcie_gart_init(rdev); 2998 if (r) 2999 return r; 3000 3001 rdev->accel_working = true; 3002 r = r600_startup(rdev); 3003 if (r) { 3004 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3005 r600_cp_fini(rdev); 3006 r600_dma_fini(rdev); 3007 r600_irq_fini(rdev); 3008 radeon_wb_fini(rdev); 3009 radeon_ib_pool_fini(rdev); 3010 radeon_irq_kms_fini(rdev); 3011 r600_pcie_gart_fini(rdev); 3012 rdev->accel_working = false; 3013 } 3014 3015 /* Don't start up if the ucode is missing. */ 3016 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3017 DRM_ERROR("radeon: ucode required for R600+.\n"); 3018 return -EINVAL; 3019 } 3020 3021 return 0; 3022} 3023 3024void r600_fini(struct radeon_device *rdev) 3025{ 3026 r600_audio_fini(rdev); 3027 r600_blit_fini(rdev); 3028 r600_cp_fini(rdev); 3029 r600_dma_fini(rdev); 3030 r600_irq_fini(rdev); 3031 radeon_wb_fini(rdev); 3032 radeon_ib_pool_fini(rdev); 3033 radeon_irq_kms_fini(rdev); 3034 r600_pcie_gart_fini(rdev); 3035 r600_vram_scratch_fini(rdev); 3036 radeon_agp_fini(rdev); 3037 radeon_gem_fini(rdev); 3038 radeon_fence_driver_fini(rdev); 3039 radeon_bo_fini(rdev); 3040 radeon_atombios_fini(rdev); 3041 r600_fini_microcode(rdev); 3042 free(rdev->bios, DRM_MEM_DRIVER); 3043 rdev->bios = NULL; 3044} 3045 3046 3047/* 3048 * CS stuff 3049 */ 3050void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3051{ 3052 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3053 u32 next_rptr; 3054 3055 if (ring->rptr_save_reg) { 3056 next_rptr = ring->wptr + 3 + 4; 3057 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3058 radeon_ring_write(ring, ((ring->rptr_save_reg - 3059 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3060 radeon_ring_write(ring, next_rptr); 3061 } else if (rdev->wb.enabled) { 3062 next_rptr = ring->wptr + 5 + 4; 3063 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3064 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3065 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3066 radeon_ring_write(ring, next_rptr); 3067 radeon_ring_write(ring, 0); 3068 } 3069 3070 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3071 radeon_ring_write(ring, 3072#ifdef __BIG_ENDIAN 3073 (2 << 0) | 3074#endif 3075 (ib->gpu_addr & 0xFFFFFFFC)); 3076 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3077 radeon_ring_write(ring, ib->length_dw); 3078} 3079 3080int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3081{ 3082 struct radeon_ib ib; 3083 uint32_t scratch; 3084 uint32_t tmp = 0; 3085 unsigned i; 3086 int r; 3087 3088 r = radeon_scratch_get(rdev, &scratch); 3089 if (r) { 3090 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3091 return r; 3092 } 3093 WREG32(scratch, 0xCAFEDEAD); 3094 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3095 if (r) { 3096 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3097 goto free_scratch; 3098 } 3099 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3100 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3101 ib.ptr[2] = 0xDEADBEEF; 3102 ib.length_dw = 3; 3103 r = radeon_ib_schedule(rdev, &ib, NULL); 3104 if (r) { 3105 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3106 goto free_ib; 3107 } 3108 r = radeon_fence_wait(ib.fence, false); 3109 if (r) { 3110 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3111 goto free_ib; 3112 } 3113 for (i = 0; i < rdev->usec_timeout; i++) { 3114 tmp = RREG32(scratch); 3115 if (tmp == 0xDEADBEEF) 3116 break; 3117 DRM_UDELAY(1); 3118 } 3119 if (i < rdev->usec_timeout) { 3120 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3121 } else { 3122 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3123 scratch, tmp); 3124 r = -EINVAL; 3125 } 3126free_ib: 3127 radeon_ib_free(rdev, &ib); 3128free_scratch: 3129 radeon_scratch_free(rdev, scratch); 3130 return r; 3131} 3132 3133/** 3134 * r600_dma_ib_test - test an IB on the DMA engine 3135 * 3136 * @rdev: radeon_device pointer 3137 * @ring: radeon_ring structure holding ring information 3138 * 3139 * Test a simple IB in the DMA ring (r6xx-SI). 3140 * Returns 0 on success, error on failure. 3141 */ 3142int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3143{ 3144 struct radeon_ib ib; 3145 unsigned i; 3146 int r; 3147 volatile uint32_t *ptr = rdev->vram_scratch.ptr; 3148 u32 tmp = 0; 3149 3150 if (!ptr) { 3151 DRM_ERROR("invalid vram scratch pointer\n"); 3152 return -EINVAL; 3153 } 3154 3155 tmp = 0xCAFEDEAD; 3156 *ptr = tmp; 3157 3158 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3159 if (r) { 3160 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3161 return r; 3162 } 3163 3164 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1); 3165 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; 3166 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff; 3167 ib.ptr[3] = 0xDEADBEEF; 3168 ib.length_dw = 4; 3169 3170 r = radeon_ib_schedule(rdev, &ib, NULL); 3171 if (r) { 3172 radeon_ib_free(rdev, &ib); 3173 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3174 return r; 3175 } 3176 r = radeon_fence_wait(ib.fence, false); 3177 if (r) { 3178 radeon_ib_free(rdev, &ib); 3179 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3180 return r; 3181 } 3182 for (i = 0; i < rdev->usec_timeout; i++) { 3183 tmp = *ptr; 3184 if (tmp == 0xDEADBEEF) 3185 break; 3186 DRM_UDELAY(1); 3187 } 3188 if (i < rdev->usec_timeout) { 3189 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3190 } else { 3191 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); 3192 r = -EINVAL; 3193 } 3194 radeon_ib_free(rdev, &ib); 3195 return r; 3196} 3197 3198/** 3199 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine 3200 * 3201 * @rdev: radeon_device pointer 3202 * @ib: IB object to schedule 3203 * 3204 * Schedule an IB in the DMA ring (r6xx-r7xx). 3205 */ 3206void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3207{ 3208 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3209 3210 if (rdev->wb.enabled) { 3211 u32 next_rptr = ring->wptr + 4; 3212 while ((next_rptr & 7) != 5) 3213 next_rptr++; 3214 next_rptr += 3; 3215 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 3216 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3217 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); 3218 radeon_ring_write(ring, next_rptr); 3219 } 3220 3221 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. 3222 * Pad as necessary with NOPs. 3223 */ 3224 while ((ring->wptr & 7) != 5) 3225 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3226 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0)); 3227 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); 3228 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); 3229 3230} 3231 3232/* 3233 * Interrupts 3234 * 3235 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3236 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3237 * writing to the ring and the GPU consuming, the GPU writes to the ring 3238 * and host consumes. As the host irq handler processes interrupts, it 3239 * increments the rptr. When the rptr catches up with the wptr, all the 3240 * current interrupts have been processed. 3241 */ 3242 3243void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3244{ 3245 u32 rb_bufsz; 3246 3247 /* Align ring size */ 3248 rb_bufsz = drm_order(ring_size / 4); 3249 ring_size = (1 << rb_bufsz) * 4; 3250 rdev->ih.ring_size = ring_size; 3251 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3252 rdev->ih.rptr = 0; 3253} 3254 3255int r600_ih_ring_alloc(struct radeon_device *rdev) 3256{ 3257 int r; 3258 void *ring_ptr; 3259 3260 /* Allocate ring buffer */ 3261 if (rdev->ih.ring_obj == NULL) { 3262 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3263 PAGE_SIZE, true, 3264 RADEON_GEM_DOMAIN_GTT, 3265 NULL, &rdev->ih.ring_obj); 3266 if (r) { 3267 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3268 return r; 3269 } 3270 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3271 if (unlikely(r != 0)) { 3272 radeon_bo_unref(&rdev->ih.ring_obj); 3273 return r; 3274 } 3275 r = radeon_bo_pin(rdev->ih.ring_obj, 3276 RADEON_GEM_DOMAIN_GTT, 3277 &rdev->ih.gpu_addr); 3278 if (r) { 3279 radeon_bo_unreserve(rdev->ih.ring_obj); 3280 radeon_bo_unref(&rdev->ih.ring_obj); 3281 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3282 return r; 3283 } 3284 ring_ptr = &rdev->ih.ring; 3285 r = radeon_bo_kmap(rdev->ih.ring_obj, 3286 ring_ptr); 3287 if (r) 3288 radeon_bo_unpin(rdev->ih.ring_obj); 3289 radeon_bo_unreserve(rdev->ih.ring_obj); 3290 if (r) { 3291 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3292 radeon_bo_unref(&rdev->ih.ring_obj); 3293 return r; 3294 } 3295 } 3296 return 0; 3297} 3298 3299void r600_ih_ring_fini(struct radeon_device *rdev) 3300{ 3301 int r; 3302 if (rdev->ih.ring_obj) { 3303 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3304 if (likely(r == 0)) { 3305 radeon_bo_kunmap(rdev->ih.ring_obj); 3306 radeon_bo_unpin(rdev->ih.ring_obj); 3307 radeon_bo_unreserve(rdev->ih.ring_obj); 3308 } 3309 radeon_bo_unref(&rdev->ih.ring_obj); 3310 rdev->ih.ring = NULL; 3311 rdev->ih.ring_obj = NULL; 3312 } 3313} 3314 3315void r600_rlc_stop(struct radeon_device *rdev) 3316{ 3317 3318 if ((rdev->family >= CHIP_RV770) && 3319 (rdev->family <= CHIP_RV740)) { 3320 /* r7xx asics need to soft reset RLC before halting */ 3321 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3322 RREG32(SRBM_SOFT_RESET); 3323 DRM_MDELAY(15); 3324 WREG32(SRBM_SOFT_RESET, 0); 3325 RREG32(SRBM_SOFT_RESET); 3326 } 3327 3328 WREG32(RLC_CNTL, 0); 3329} 3330 3331static void r600_rlc_start(struct radeon_device *rdev) 3332{ 3333 WREG32(RLC_CNTL, RLC_ENABLE); 3334} 3335 3336static int r600_rlc_init(struct radeon_device *rdev) 3337{ 3338 u32 i; 3339 const __be32 *fw_data; 3340 3341 if (!rdev->rlc_fw) 3342 return -EINVAL; 3343 3344 r600_rlc_stop(rdev); 3345 3346 WREG32(RLC_HB_CNTL, 0); 3347 3348 if (rdev->family == CHIP_ARUBA) { 3349 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); 3350 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); 3351 } 3352 if (rdev->family <= CHIP_CAYMAN) { 3353 WREG32(RLC_HB_BASE, 0); 3354 WREG32(RLC_HB_RPTR, 0); 3355 WREG32(RLC_HB_WPTR, 0); 3356 } 3357 if (rdev->family <= CHIP_CAICOS) { 3358 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3359 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3360 } 3361 WREG32(RLC_MC_CNTL, 0); 3362 WREG32(RLC_UCODE_CNTL, 0); 3363 3364 fw_data = (const __be32 *)rdev->rlc_fw->data; 3365 if (rdev->family >= CHIP_ARUBA) { 3366 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) { 3367 WREG32(RLC_UCODE_ADDR, i); 3368 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3369 } 3370 } else if (rdev->family >= CHIP_CAYMAN) { 3371 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) { 3372 WREG32(RLC_UCODE_ADDR, i); 3373 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3374 } 3375 } else if (rdev->family >= CHIP_CEDAR) { 3376 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) { 3377 WREG32(RLC_UCODE_ADDR, i); 3378 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3379 } 3380 } else if (rdev->family >= CHIP_RV770) { 3381 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3382 WREG32(RLC_UCODE_ADDR, i); 3383 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3384 } 3385 } else { 3386 for (i = 0; i < RLC_UCODE_SIZE; i++) { 3387 WREG32(RLC_UCODE_ADDR, i); 3388 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3389 } 3390 } 3391 WREG32(RLC_UCODE_ADDR, 0); 3392 3393 r600_rlc_start(rdev); 3394 3395 return 0; 3396} 3397 3398static void r600_enable_interrupts(struct radeon_device *rdev) 3399{ 3400 u32 ih_cntl = RREG32(IH_CNTL); 3401 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3402 3403 ih_cntl |= ENABLE_INTR; 3404 ih_rb_cntl |= IH_RB_ENABLE; 3405 WREG32(IH_CNTL, ih_cntl); 3406 WREG32(IH_RB_CNTL, ih_rb_cntl); 3407 rdev->ih.enabled = true; 3408} 3409 3410void r600_disable_interrupts(struct radeon_device *rdev) 3411{ 3412 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3413 u32 ih_cntl = RREG32(IH_CNTL); 3414 3415 ih_rb_cntl &= ~IH_RB_ENABLE; 3416 ih_cntl &= ~ENABLE_INTR; 3417 WREG32(IH_RB_CNTL, ih_rb_cntl); 3418 WREG32(IH_CNTL, ih_cntl); 3419 /* set rptr, wptr to 0 */ 3420 WREG32(IH_RB_RPTR, 0); 3421 WREG32(IH_RB_WPTR, 0); 3422 rdev->ih.enabled = false; 3423 rdev->ih.rptr = 0; 3424} 3425 3426static void r600_disable_interrupt_state(struct radeon_device *rdev) 3427{ 3428 u32 tmp; 3429 3430 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3431 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3432 WREG32(DMA_CNTL, tmp); 3433 WREG32(GRBM_INT_CNTL, 0); 3434 WREG32(DxMODE_INT_MASK, 0); 3435 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3436 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3437 if (ASIC_IS_DCE3(rdev)) { 3438 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3439 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3440 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3441 WREG32(DC_HPD1_INT_CONTROL, tmp); 3442 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3443 WREG32(DC_HPD2_INT_CONTROL, tmp); 3444 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3445 WREG32(DC_HPD3_INT_CONTROL, tmp); 3446 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3447 WREG32(DC_HPD4_INT_CONTROL, tmp); 3448 if (ASIC_IS_DCE32(rdev)) { 3449 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3450 WREG32(DC_HPD5_INT_CONTROL, tmp); 3451 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3452 WREG32(DC_HPD6_INT_CONTROL, tmp); 3453 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3454 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3455 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3456 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3457 } else { 3458 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3459 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3460 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3461 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3462 } 3463 } else { 3464 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3465 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3466 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3467 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3468 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3469 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3470 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3471 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3472 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3473 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3474 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3475 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3476 } 3477} 3478 3479int r600_irq_init(struct radeon_device *rdev) 3480{ 3481 int ret = 0; 3482 int rb_bufsz; 3483 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3484 3485 /* allocate ring */ 3486 ret = r600_ih_ring_alloc(rdev); 3487 if (ret) 3488 return ret; 3489 3490 /* disable irqs */ 3491 r600_disable_interrupts(rdev); 3492 3493 /* init rlc */ 3494 ret = r600_rlc_init(rdev); 3495 if (ret) { 3496 r600_ih_ring_fini(rdev); 3497 return ret; 3498 } 3499 3500 /* setup interrupt control */ 3501 /* set dummy read address to ring address */ 3502 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3503 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3504 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3505 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3506 */ 3507 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3508 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3509 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3510 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3511 3512 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3513 rb_bufsz = drm_order(rdev->ih.ring_size / 4); 3514 3515 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3516 IH_WPTR_OVERFLOW_CLEAR | 3517 (rb_bufsz << 1)); 3518 3519 if (rdev->wb.enabled) 3520 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3521 3522 /* set the writeback address whether it's enabled or not */ 3523 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3524 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3525 3526 WREG32(IH_RB_CNTL, ih_rb_cntl); 3527 3528 /* set rptr, wptr to 0 */ 3529 WREG32(IH_RB_RPTR, 0); 3530 WREG32(IH_RB_WPTR, 0); 3531 3532 /* Default settings for IH_CNTL (disabled at first) */ 3533 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 3534 /* RPTR_REARM only works if msi's are enabled */ 3535 if (rdev->msi_enabled) 3536 ih_cntl |= RPTR_REARM; 3537 WREG32(IH_CNTL, ih_cntl); 3538 3539 /* force the active interrupt state to all disabled */ 3540 if (rdev->family >= CHIP_CEDAR) 3541 evergreen_disable_interrupt_state(rdev); 3542 else 3543 r600_disable_interrupt_state(rdev); 3544 3545 /* at this point everything should be setup correctly to enable master */ 3546 pci_enable_busmaster(rdev->dev); 3547 3548 /* enable irqs */ 3549 r600_enable_interrupts(rdev); 3550 3551 return ret; 3552} 3553 3554void r600_irq_suspend(struct radeon_device *rdev) 3555{ 3556 r600_irq_disable(rdev); 3557 r600_rlc_stop(rdev); 3558} 3559 3560void r600_irq_fini(struct radeon_device *rdev) 3561{ 3562 r600_irq_suspend(rdev); 3563 r600_ih_ring_fini(rdev); 3564} 3565 3566int r600_irq_set(struct radeon_device *rdev) 3567{ 3568 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3569 u32 mode_int = 0; 3570 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3571 u32 grbm_int_cntl = 0; 3572 u32 hdmi0, hdmi1; 3573 u32 d1grph = 0, d2grph = 0; 3574 u32 dma_cntl; 3575 3576 if (!rdev->irq.installed) { 3577 DRM_ERROR("Can't enable IRQ/MSI because no handler is installed\n"); 3578 return -EINVAL; 3579 } 3580 /* don't enable anything if the ih is disabled */ 3581 if (!rdev->ih.enabled) { 3582 r600_disable_interrupts(rdev); 3583 /* force the active interrupt state to all disabled */ 3584 r600_disable_interrupt_state(rdev); 3585 return 0; 3586 } 3587 3588 if (ASIC_IS_DCE3(rdev)) { 3589 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3590 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3591 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3592 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3593 if (ASIC_IS_DCE32(rdev)) { 3594 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3595 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3596 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3597 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3598 } else { 3599 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3600 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3601 } 3602 } else { 3603 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3604 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3605 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3606 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3607 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3608 } 3609 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3610 3611 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3612 DRM_DEBUG("r600_irq_set: sw int\n"); 3613 cp_int_cntl |= RB_INT_ENABLE; 3614 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3615 } 3616 3617 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3618 DRM_DEBUG("r600_irq_set: sw int dma\n"); 3619 dma_cntl |= TRAP_ENABLE; 3620 } 3621 3622 if (rdev->irq.crtc_vblank_int[0] || 3623 atomic_read(&rdev->irq.pflip[0])) { 3624 DRM_DEBUG("r600_irq_set: vblank 0\n"); 3625 mode_int |= D1MODE_VBLANK_INT_MASK; 3626 } 3627 if (rdev->irq.crtc_vblank_int[1] || 3628 atomic_read(&rdev->irq.pflip[1])) { 3629 DRM_DEBUG("r600_irq_set: vblank 1\n"); 3630 mode_int |= D2MODE_VBLANK_INT_MASK; 3631 } 3632 if (rdev->irq.hpd[0]) { 3633 DRM_DEBUG("r600_irq_set: hpd 1\n"); 3634 hpd1 |= DC_HPDx_INT_EN; 3635 } 3636 if (rdev->irq.hpd[1]) { 3637 DRM_DEBUG("r600_irq_set: hpd 2\n"); 3638 hpd2 |= DC_HPDx_INT_EN; 3639 } 3640 if (rdev->irq.hpd[2]) { 3641 DRM_DEBUG("r600_irq_set: hpd 3\n"); 3642 hpd3 |= DC_HPDx_INT_EN; 3643 } 3644 if (rdev->irq.hpd[3]) { 3645 DRM_DEBUG("r600_irq_set: hpd 4\n"); 3646 hpd4 |= DC_HPDx_INT_EN; 3647 } 3648 if (rdev->irq.hpd[4]) { 3649 DRM_DEBUG("r600_irq_set: hpd 5\n"); 3650 hpd5 |= DC_HPDx_INT_EN; 3651 } 3652 if (rdev->irq.hpd[5]) { 3653 DRM_DEBUG("r600_irq_set: hpd 6\n"); 3654 hpd6 |= DC_HPDx_INT_EN; 3655 } 3656 if (rdev->irq.afmt[0]) { 3657 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3658 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3659 } 3660 if (rdev->irq.afmt[1]) { 3661 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3662 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3663 } 3664 3665 WREG32(CP_INT_CNTL, cp_int_cntl); 3666 WREG32(DMA_CNTL, dma_cntl); 3667 WREG32(DxMODE_INT_MASK, mode_int); 3668 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); 3669 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); 3670 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3671 if (ASIC_IS_DCE3(rdev)) { 3672 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3673 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3674 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3675 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3676 if (ASIC_IS_DCE32(rdev)) { 3677 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3678 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3679 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 3680 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 3681 } else { 3682 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3683 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3684 } 3685 } else { 3686 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 3687 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 3688 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 3689 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3690 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3691 } 3692 3693 return 0; 3694} 3695 3696static void r600_irq_ack(struct radeon_device *rdev) 3697{ 3698 u32 tmp; 3699 3700 if (ASIC_IS_DCE3(rdev)) { 3701 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 3702 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 3703 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 3704 if (ASIC_IS_DCE32(rdev)) { 3705 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 3706 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 3707 } else { 3708 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3709 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 3710 } 3711 } else { 3712 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3713 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3714 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 3715 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3716 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 3717 } 3718 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 3719 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 3720 3721 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3722 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3723 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3724 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3725 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 3726 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3727 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 3728 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3729 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 3730 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3731 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 3732 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3733 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3734 if (ASIC_IS_DCE3(rdev)) { 3735 tmp = RREG32(DC_HPD1_INT_CONTROL); 3736 tmp |= DC_HPDx_INT_ACK; 3737 WREG32(DC_HPD1_INT_CONTROL, tmp); 3738 } else { 3739 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 3740 tmp |= DC_HPDx_INT_ACK; 3741 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3742 } 3743 } 3744 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3745 if (ASIC_IS_DCE3(rdev)) { 3746 tmp = RREG32(DC_HPD2_INT_CONTROL); 3747 tmp |= DC_HPDx_INT_ACK; 3748 WREG32(DC_HPD2_INT_CONTROL, tmp); 3749 } else { 3750 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 3751 tmp |= DC_HPDx_INT_ACK; 3752 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3753 } 3754 } 3755 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3756 if (ASIC_IS_DCE3(rdev)) { 3757 tmp = RREG32(DC_HPD3_INT_CONTROL); 3758 tmp |= DC_HPDx_INT_ACK; 3759 WREG32(DC_HPD3_INT_CONTROL, tmp); 3760 } else { 3761 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 3762 tmp |= DC_HPDx_INT_ACK; 3763 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3764 } 3765 } 3766 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3767 tmp = RREG32(DC_HPD4_INT_CONTROL); 3768 tmp |= DC_HPDx_INT_ACK; 3769 WREG32(DC_HPD4_INT_CONTROL, tmp); 3770 } 3771 if (ASIC_IS_DCE32(rdev)) { 3772 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3773 tmp = RREG32(DC_HPD5_INT_CONTROL); 3774 tmp |= DC_HPDx_INT_ACK; 3775 WREG32(DC_HPD5_INT_CONTROL, tmp); 3776 } 3777 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3778 tmp = RREG32(DC_HPD5_INT_CONTROL); 3779 tmp |= DC_HPDx_INT_ACK; 3780 WREG32(DC_HPD6_INT_CONTROL, tmp); 3781 } 3782 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 3783 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 3784 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3785 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3786 } 3787 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 3788 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 3789 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3790 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3791 } 3792 } else { 3793 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 3794 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 3795 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3796 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3797 } 3798 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 3799 if (ASIC_IS_DCE3(rdev)) { 3800 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 3801 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3802 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3803 } else { 3804 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 3805 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3806 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3807 } 3808 } 3809 } 3810} 3811 3812void r600_irq_disable(struct radeon_device *rdev) 3813{ 3814 r600_disable_interrupts(rdev); 3815 /* Wait and acknowledge irq */ 3816 DRM_MDELAY(1); 3817 r600_irq_ack(rdev); 3818 r600_disable_interrupt_state(rdev); 3819} 3820 3821static u32 r600_get_ih_wptr(struct radeon_device *rdev) 3822{ 3823 u32 wptr, tmp; 3824 3825 if (rdev->wb.enabled) 3826 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 3827 else 3828 wptr = RREG32(IH_RB_WPTR); 3829 3830 if (wptr & RB_OVERFLOW) { 3831 /* When a ring buffer overflow happen start parsing interrupt 3832 * from the last not overwritten vector (wptr + 16). Hopefully 3833 * this should allow us to catchup. 3834 */ 3835 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 3836 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 3837 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 3838 tmp = RREG32(IH_RB_CNTL); 3839 tmp |= IH_WPTR_OVERFLOW_CLEAR; 3840 WREG32(IH_RB_CNTL, tmp); 3841 } 3842 return (wptr & rdev->ih.ptr_mask); 3843} 3844 3845/* r600 IV Ring 3846 * Each IV ring entry is 128 bits: 3847 * [7:0] - interrupt source id 3848 * [31:8] - reserved 3849 * [59:32] - interrupt source data 3850 * [127:60] - reserved 3851 * 3852 * The basic interrupt vector entries 3853 * are decoded as follows: 3854 * src_id src_data description 3855 * 1 0 D1 Vblank 3856 * 1 1 D1 Vline 3857 * 5 0 D2 Vblank 3858 * 5 1 D2 Vline 3859 * 19 0 FP Hot plug detection A 3860 * 19 1 FP Hot plug detection B 3861 * 19 2 DAC A auto-detection 3862 * 19 3 DAC B auto-detection 3863 * 21 4 HDMI block A 3864 * 21 5 HDMI block B 3865 * 176 - CP_INT RB 3866 * 177 - CP_INT IB1 3867 * 178 - CP_INT IB2 3868 * 181 - EOP Interrupt 3869 * 233 - GUI Idle 3870 * 3871 * Note, these are based on r600 and may need to be 3872 * adjusted or added to on newer asics 3873 */ 3874 3875irqreturn_t r600_irq_process(struct radeon_device *rdev) 3876{ 3877 u32 wptr; 3878 u32 rptr; 3879 u32 src_id, src_data; 3880 u32 ring_index; 3881 bool queue_hotplug = false; 3882 bool queue_hdmi = false; 3883 3884 if (!rdev->ih.enabled || rdev->shutdown) 3885 return IRQ_NONE; 3886 3887 /* No MSIs, need a dummy read to flush PCI DMAs */ 3888 if (!rdev->msi_enabled) 3889 RREG32(IH_RB_WPTR); 3890 3891 wptr = r600_get_ih_wptr(rdev); 3892 3893restart_ih: 3894 /* is somebody else already processing irqs? */ 3895 if (atomic_xchg(&rdev->ih.lock, 1)) 3896 return IRQ_NONE; 3897 3898 rptr = rdev->ih.rptr; 3899 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 3900 3901 /* Order reading of wptr vs. reading of IH ring data */ 3902 rmb(); 3903 3904 /* display interrupts */ 3905 r600_irq_ack(rdev); 3906 3907 while (rptr != wptr) { 3908 /* wptr/rptr are in bytes! */ 3909 ring_index = rptr / 4; 3910 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 3911 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 3912 3913 switch (src_id) { 3914 case 1: /* D1 vblank/vline */ 3915 switch (src_data) { 3916 case 0: /* D1 vblank */ 3917 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { 3918 if (rdev->irq.crtc_vblank_int[0]) { 3919 drm_handle_vblank(rdev->ddev, 0); 3920 rdev->pm.vblank_sync = true; 3921 DRM_WAKEUP(&rdev->irq.vblank_queue); 3922 } 3923 if (atomic_read(&rdev->irq.pflip[0])) 3924 radeon_crtc_handle_flip(rdev, 0); 3925 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 3926 DRM_DEBUG("IH: D1 vblank\n"); 3927 } 3928 break; 3929 case 1: /* D1 vline */ 3930 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { 3931 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 3932 DRM_DEBUG("IH: D1 vline\n"); 3933 } 3934 break; 3935 default: 3936 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3937 break; 3938 } 3939 break; 3940 case 5: /* D2 vblank/vline */ 3941 switch (src_data) { 3942 case 0: /* D2 vblank */ 3943 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { 3944 if (rdev->irq.crtc_vblank_int[1]) { 3945 drm_handle_vblank(rdev->ddev, 1); 3946 rdev->pm.vblank_sync = true; 3947 DRM_WAKEUP(&rdev->irq.vblank_queue); 3948 } 3949 if (atomic_read(&rdev->irq.pflip[1])) 3950 radeon_crtc_handle_flip(rdev, 1); 3951 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 3952 DRM_DEBUG("IH: D2 vblank\n"); 3953 } 3954 break; 3955 case 1: /* D1 vline */ 3956 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { 3957 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 3958 DRM_DEBUG("IH: D2 vline\n"); 3959 } 3960 break; 3961 default: 3962 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3963 break; 3964 } 3965 break; 3966 case 19: /* HPD/DAC hotplug */ 3967 switch (src_data) { 3968 case 0: 3969 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3970 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 3971 queue_hotplug = true; 3972 DRM_DEBUG("IH: HPD1\n"); 3973 } 3974 break; 3975 case 1: 3976 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3977 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 3978 queue_hotplug = true; 3979 DRM_DEBUG("IH: HPD2\n"); 3980 } 3981 break; 3982 case 4: 3983 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3984 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 3985 queue_hotplug = true; 3986 DRM_DEBUG("IH: HPD3\n"); 3987 } 3988 break; 3989 case 5: 3990 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3991 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 3992 queue_hotplug = true; 3993 DRM_DEBUG("IH: HPD4\n"); 3994 } 3995 break; 3996 case 10: 3997 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3998 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 3999 queue_hotplug = true; 4000 DRM_DEBUG("IH: HPD5\n"); 4001 } 4002 break; 4003 case 12: 4004 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 4005 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4006 queue_hotplug = true; 4007 DRM_DEBUG("IH: HPD6\n"); 4008 } 4009 break; 4010 default: 4011 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4012 break; 4013 } 4014 break; 4015 case 21: /* hdmi */ 4016 switch (src_data) { 4017 case 4: 4018 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4019 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4020 queue_hdmi = true; 4021 DRM_DEBUG("IH: HDMI0\n"); 4022 } 4023 break; 4024 case 5: 4025 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4026 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4027 queue_hdmi = true; 4028 DRM_DEBUG("IH: HDMI1\n"); 4029 } 4030 break; 4031 default: 4032 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4033 break; 4034 } 4035 break; 4036 case 176: /* CP_INT in ring buffer */ 4037 case 177: /* CP_INT in IB1 */ 4038 case 178: /* CP_INT in IB2 */ 4039 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4040 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4041 break; 4042 case 181: /* CP EOP event */ 4043 DRM_DEBUG("IH: CP EOP\n"); 4044 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4045 break; 4046 case 224: /* DMA trap event */ 4047 DRM_DEBUG("IH: DMA trap\n"); 4048 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4049 break; 4050 case 233: /* GUI IDLE */ 4051 DRM_DEBUG("IH: GUI idle\n"); 4052 break; 4053 default: 4054 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4055 break; 4056 } 4057 4058 /* wptr/rptr are in bytes! */ 4059 rptr += 16; 4060 rptr &= rdev->ih.ptr_mask; 4061 } 4062 if (queue_hotplug) 4063 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work); 4064 if (queue_hdmi) 4065 taskqueue_enqueue(rdev->tq, &rdev->audio_work); 4066 rdev->ih.rptr = rptr; 4067 WREG32(IH_RB_RPTR, rdev->ih.rptr); 4068 atomic_set(&rdev->ih.lock, 0); 4069 4070 /* make sure wptr hasn't changed while processing */ 4071 wptr = r600_get_ih_wptr(rdev); 4072 if (wptr != rptr) 4073 goto restart_ih; 4074 4075 return IRQ_HANDLED; 4076} 4077 4078/* 4079 * Debugfs info 4080 */ 4081#if defined(CONFIG_DEBUG_FS) 4082 4083static int r600_debugfs_mc_info(struct seq_file *m, void *data) 4084{ 4085 struct drm_info_node *node = (struct drm_info_node *) m->private; 4086 struct drm_device *dev = node->minor->dev; 4087 struct radeon_device *rdev = dev->dev_private; 4088 4089 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4090 DREG32_SYS(m, rdev, VM_L2_STATUS); 4091 return 0; 4092} 4093 4094static struct drm_info_list r600_mc_info_list[] = { 4095 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 4096}; 4097#endif 4098 4099int r600_debugfs_mc_info_init(struct radeon_device *rdev) 4100{ 4101#if defined(CONFIG_DEBUG_FS) 4102 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 4103#else 4104 return 0; 4105#endif 4106} 4107 4108/** 4109 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl 4110 * rdev: radeon device structure 4111 * bo: buffer object struct which userspace is waiting for idle 4112 * 4113 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed 4114 * through ring buffer, this leads to corruption in rendering, see 4115 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we 4116 * directly perform HDP flush by writing register through MMIO. 4117 */ 4118void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) 4119{ 4120 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4121 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4122 * This seems to cause problems on some AGP cards. Just use the old 4123 * method for them. 4124 */ 4125 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4126 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4127 volatile uint32_t *ptr = rdev->vram_scratch.ptr; 4128 u32 tmp; 4129 4130 WREG32(HDP_DEBUG1, 0); 4131 tmp = *ptr; 4132 } else 4133 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4134} 4135 4136void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4137{ 4138 u32 link_width_cntl, mask, target_reg; 4139 4140 if (rdev->flags & RADEON_IS_IGP) 4141 return; 4142 4143 if (!(rdev->flags & RADEON_IS_PCIE)) 4144 return; 4145 4146 /* x2 cards have a special sequence */ 4147 if (ASIC_IS_X2(rdev)) 4148 return; 4149 4150 /* FIXME wait for idle */ 4151 4152 switch (lanes) { 4153 case 0: 4154 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4155 break; 4156 case 1: 4157 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4158 break; 4159 case 2: 4160 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4161 break; 4162 case 4: 4163 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4164 break; 4165 case 8: 4166 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4167 break; 4168 case 12: 4169 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4170 break; 4171 case 16: 4172 default: 4173 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4174 break; 4175 } 4176 4177 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4178 4179 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 4180 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 4181 return; 4182 4183 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS) 4184 return; 4185 4186 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 4187 RADEON_PCIE_LC_RECONFIG_NOW | 4188 R600_PCIE_LC_RENEGOTIATE_EN | 4189 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4190 link_width_cntl |= mask; 4191 4192 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4193 4194 /* some northbridges can renegotiate the link rather than requiring 4195 * a complete re-config. 4196 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.) 4197 */ 4198 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT) 4199 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT; 4200 else 4201 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE; 4202 4203 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 4204 RADEON_PCIE_LC_RECONFIG_NOW)); 4205 4206 if (rdev->family >= CHIP_RV770) 4207 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX; 4208 else 4209 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX; 4210 4211 /* wait for lane set to complete */ 4212 link_width_cntl = RREG32(target_reg); 4213 while (link_width_cntl == 0xffffffff) 4214 link_width_cntl = RREG32(target_reg); 4215 4216} 4217 4218int r600_get_pcie_lanes(struct radeon_device *rdev) 4219{ 4220 u32 link_width_cntl; 4221 4222 if (rdev->flags & RADEON_IS_IGP) 4223 return 0; 4224 4225 if (!(rdev->flags & RADEON_IS_PCIE)) 4226 return 0; 4227 4228 /* x2 cards have a special sequence */ 4229 if (ASIC_IS_X2(rdev)) 4230 return 0; 4231 4232 /* FIXME wait for idle */ 4233 4234 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4235 4236 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4237 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4238 return 0; 4239 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4240 return 1; 4241 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4242 return 2; 4243 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4244 return 4; 4245 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4246 return 8; 4247 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4248 default: 4249 return 16; 4250 } 4251} 4252 4253static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4254{ 4255 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4256 u16 link_cntl2; 4257 u32 mask; 4258 int ret; 4259 4260 if (radeon_pcie_gen2 == 0) 4261 return; 4262 4263 if (rdev->flags & RADEON_IS_IGP) 4264 return; 4265 4266 if (!(rdev->flags & RADEON_IS_PCIE)) 4267 return; 4268 4269 /* x2 cards have a special sequence */ 4270 if (ASIC_IS_X2(rdev)) 4271 return; 4272 4273 /* only RV6xx+ chips are supported */ 4274 if (rdev->family <= CHIP_R600) 4275 return; 4276 4277 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 4278 if (ret != 0) 4279 return; 4280 4281 if (!(mask & DRM_PCIE_SPEED_50)) 4282 return; 4283 4284 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4285 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4286 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4287 return; 4288 } 4289 4290 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4291 4292 /* 55 nm r6xx asics */ 4293 if ((rdev->family == CHIP_RV670) || 4294 (rdev->family == CHIP_RV620) || 4295 (rdev->family == CHIP_RV635)) { 4296 /* advertise upconfig capability */ 4297 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4298 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4299 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4300 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4301 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4302 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4303 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4304 LC_RECONFIG_ARC_MISSING_ESCAPE); 4305 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4306 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4307 } else { 4308 link_width_cntl |= LC_UPCONFIGURE_DIS; 4309 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4310 } 4311 } 4312 4313 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4314 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4315 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4316 4317 /* 55 nm r6xx asics */ 4318 if ((rdev->family == CHIP_RV670) || 4319 (rdev->family == CHIP_RV620) || 4320 (rdev->family == CHIP_RV635)) { 4321 WREG32(MM_CFGREGS_CNTL, 0x8); 4322 link_cntl2 = RREG32(0x4088); 4323 WREG32(MM_CFGREGS_CNTL, 0); 4324 /* not supported yet */ 4325 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4326 return; 4327 } 4328 4329 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4330 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4331 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4332 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4333 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4334 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4335 4336 tmp = RREG32(0x541c); 4337 WREG32(0x541c, tmp | 0x8); 4338 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4339 link_cntl2 = RREG16(0x4088); 4340 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4341 link_cntl2 |= 0x2; 4342 WREG16(0x4088, link_cntl2); 4343 WREG32(MM_CFGREGS_CNTL, 0); 4344 4345 if ((rdev->family == CHIP_RV670) || 4346 (rdev->family == CHIP_RV620) || 4347 (rdev->family == CHIP_RV635)) { 4348 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL); 4349 training_cntl &= ~LC_POINT_7_PLUS_EN; 4350 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl); 4351 } else { 4352 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4353 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4354 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4355 } 4356 4357 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4358 speed_cntl |= LC_GEN2_EN_STRAP; 4359 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4360 4361 } else { 4362 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4363 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4364 if (1) 4365 link_width_cntl |= LC_UPCONFIGURE_DIS; 4366 else 4367 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4368 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4369 } 4370} 4371 4372/** 4373 * r600_get_gpu_clock - return GPU clock counter snapshot 4374 * 4375 * @rdev: radeon_device pointer 4376 * 4377 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4378 * Returns the 64 bit clock counter snapshot. 4379 */ 4380uint64_t r600_get_gpu_clock(struct radeon_device *rdev) 4381{ 4382 uint64_t clock; 4383 4384 sx_xlock(&rdev->gpu_clock_mutex); 4385 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4386 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4387 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4388 sx_xunlock(&rdev->gpu_clock_mutex); 4389 return clock; 4390} 4391