1235783Skib/* 2235783Skib * Copyright �� 2008 Intel Corporation 3235783Skib * 4235783Skib * Permission is hereby granted, free of charge, to any person obtaining a 5235783Skib * copy of this software and associated documentation files (the "Software"), 6235783Skib * to deal in the Software without restriction, including without limitation 7235783Skib * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8235783Skib * and/or sell copies of the Software, and to permit persons to whom the 9235783Skib * Software is furnished to do so, subject to the following conditions: 10235783Skib * 11235783Skib * The above copyright notice and this permission notice (including the next 12235783Skib * paragraph) shall be included in all copies or substantial portions of the 13235783Skib * Software. 14235783Skib * 15235783Skib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16235783Skib * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17235783Skib * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18235783Skib * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19235783Skib * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20235783Skib * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21235783Skib * IN THE SOFTWARE. 22235783Skib * 23235783Skib * Authors: 24235783Skib * Keith Packard <keithp@keithp.com> 25235783Skib * 26235783Skib */ 27235783Skib 28235783Skib#include <sys/cdefs.h> 29235783Skib__FBSDID("$FreeBSD$"); 30235783Skib 31235783Skib#include <dev/drm2/drmP.h> 32235783Skib#include <dev/drm2/drm.h> 33235783Skib#include <dev/drm2/drm_crtc.h> 34235783Skib#include <dev/drm2/drm_crtc_helper.h> 35235783Skib#include <dev/drm2/i915/i915_drm.h> 36235783Skib#include <dev/drm2/i915/i915_drv.h> 37235783Skib#include <dev/drm2/i915/intel_drv.h> 38235783Skib#include <dev/drm2/drm_dp_helper.h> 39235783Skib 40235783Skib#define DP_RECEIVER_CAP_SIZE 0xf 41235783Skib#define DP_LINK_STATUS_SIZE 6 42235783Skib#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 43235783Skib 44235783Skib#define DP_LINK_CONFIGURATION_SIZE 9 45235783Skib 46235783Skibstruct intel_dp { 47235783Skib struct intel_encoder base; 48235783Skib uint32_t output_reg; 49235783Skib uint32_t DP; 50235783Skib uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 51235783Skib bool has_audio; 52235783Skib enum hdmi_force_audio force_audio; 53235783Skib uint32_t color_range; 54235783Skib int dpms_mode; 55235783Skib uint8_t link_bw; 56235783Skib uint8_t lane_count; 57235783Skib uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; 58235783Skib device_t dp_iic_bus; 59235783Skib device_t adapter; 60235783Skib bool is_pch_edp; 61235783Skib uint8_t train_set[4]; 62235783Skib int panel_power_up_delay; 63235783Skib int panel_power_down_delay; 64235783Skib int panel_power_cycle_delay; 65235783Skib int backlight_on_delay; 66235783Skib int backlight_off_delay; 67235783Skib struct drm_display_mode *panel_fixed_mode; /* for eDP */ 68235783Skib struct timeout_task panel_vdd_task; 69235783Skib bool want_panel_vdd; 70235783Skib}; 71235783Skib 72235783Skib/** 73235783Skib * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 74235783Skib * @intel_dp: DP struct 75235783Skib * 76235783Skib * If a CPU or PCH DP output is attached to an eDP panel, this function 77235783Skib * will return true, and false otherwise. 78235783Skib */ 79235783Skibstatic bool is_edp(struct intel_dp *intel_dp) 80235783Skib{ 81235783Skib return intel_dp->base.type == INTEL_OUTPUT_EDP; 82235783Skib} 83235783Skib 84235783Skib/** 85235783Skib * is_pch_edp - is the port on the PCH and attached to an eDP panel? 86235783Skib * @intel_dp: DP struct 87235783Skib * 88235783Skib * Returns true if the given DP struct corresponds to a PCH DP port attached 89235783Skib * to an eDP panel, false otherwise. Helpful for determining whether we 90235783Skib * may need FDI resources for a given DP output or not. 91235783Skib */ 92235783Skibstatic bool is_pch_edp(struct intel_dp *intel_dp) 93235783Skib{ 94235783Skib return intel_dp->is_pch_edp; 95235783Skib} 96235783Skib 97235783Skib/** 98235783Skib * is_cpu_edp - is the port on the CPU and attached to an eDP panel? 99235783Skib * @intel_dp: DP struct 100235783Skib * 101235783Skib * Returns true if the given DP struct corresponds to a CPU eDP port. 102235783Skib */ 103235783Skibstatic bool is_cpu_edp(struct intel_dp *intel_dp) 104235783Skib{ 105235783Skib return is_edp(intel_dp) && !is_pch_edp(intel_dp); 106235783Skib} 107235783Skib 108235783Skibstatic struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 109235783Skib{ 110235783Skib return container_of(encoder, struct intel_dp, base.base); 111235783Skib} 112235783Skib 113235783Skibstatic struct intel_dp *intel_attached_dp(struct drm_connector *connector) 114235783Skib{ 115235783Skib return container_of(intel_attached_encoder(connector), 116235783Skib struct intel_dp, base); 117235783Skib} 118235783Skib 119235783Skib/** 120235783Skib * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? 121235783Skib * @encoder: DRM encoder 122235783Skib * 123235783Skib * Return true if @encoder corresponds to a PCH attached eDP panel. Needed 124235783Skib * by intel_display.c. 125235783Skib */ 126235783Skibbool intel_encoder_is_pch_edp(struct drm_encoder *encoder) 127235783Skib{ 128235783Skib struct intel_dp *intel_dp; 129235783Skib 130235783Skib if (!encoder) 131235783Skib return false; 132235783Skib 133235783Skib intel_dp = enc_to_intel_dp(encoder); 134235783Skib 135235783Skib return is_pch_edp(intel_dp); 136235783Skib} 137235783Skib 138235783Skibstatic void intel_dp_start_link_train(struct intel_dp *intel_dp); 139235783Skibstatic void intel_dp_complete_link_train(struct intel_dp *intel_dp); 140235783Skibstatic void intel_dp_link_down(struct intel_dp *intel_dp); 141235783Skib 142235783Skibvoid 143235783Skibintel_edp_link_config(struct intel_encoder *intel_encoder, 144235783Skib int *lane_num, int *link_bw) 145235783Skib{ 146235783Skib struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 147235783Skib 148235783Skib *lane_num = intel_dp->lane_count; 149235783Skib if (intel_dp->link_bw == DP_LINK_BW_1_62) 150235783Skib *link_bw = 162000; 151235783Skib else if (intel_dp->link_bw == DP_LINK_BW_2_7) 152235783Skib *link_bw = 270000; 153235783Skib} 154235783Skib 155235783Skibstatic int 156235783Skibintel_dp_max_lane_count(struct intel_dp *intel_dp) 157235783Skib{ 158235783Skib int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; 159235783Skib switch (max_lane_count) { 160235783Skib case 1: case 2: case 4: 161235783Skib break; 162235783Skib default: 163235783Skib max_lane_count = 4; 164235783Skib } 165235783Skib return max_lane_count; 166235783Skib} 167235783Skib 168235783Skibstatic int 169235783Skibintel_dp_max_link_bw(struct intel_dp *intel_dp) 170235783Skib{ 171235783Skib int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 172235783Skib 173235783Skib switch (max_link_bw) { 174235783Skib case DP_LINK_BW_1_62: 175235783Skib case DP_LINK_BW_2_7: 176235783Skib break; 177235783Skib default: 178235783Skib max_link_bw = DP_LINK_BW_1_62; 179235783Skib break; 180235783Skib } 181235783Skib return max_link_bw; 182235783Skib} 183235783Skib 184235783Skibstatic int 185235783Skibintel_dp_link_clock(uint8_t link_bw) 186235783Skib{ 187235783Skib if (link_bw == DP_LINK_BW_2_7) 188235783Skib return 270000; 189235783Skib else 190235783Skib return 162000; 191235783Skib} 192235783Skib 193235783Skib/* 194235783Skib * The units on the numbers in the next two are... bizarre. Examples will 195235783Skib * make it clearer; this one parallels an example in the eDP spec. 196235783Skib * 197235783Skib * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 198235783Skib * 199235783Skib * 270000 * 1 * 8 / 10 == 216000 200235783Skib * 201235783Skib * The actual data capacity of that configuration is 2.16Gbit/s, so the 202235783Skib * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 203235783Skib * or equivalently, kilopixels per second - so for 1680x1050R it'd be 204235783Skib * 119000. At 18bpp that's 2142000 kilobits per second. 205235783Skib * 206235783Skib * Thus the strange-looking division by 10 in intel_dp_link_required, to 207235783Skib * get the result in decakilobits instead of kilobits. 208235783Skib */ 209235783Skib 210235783Skibstatic int 211235783Skibintel_dp_link_required(int pixel_clock, int bpp) 212235783Skib{ 213235783Skib return (pixel_clock * bpp + 9) / 10; 214235783Skib} 215235783Skib 216235783Skibstatic int 217235783Skibintel_dp_max_data_rate(int max_link_clock, int max_lanes) 218235783Skib{ 219235783Skib return (max_link_clock * max_lanes * 8) / 10; 220235783Skib} 221235783Skib 222235783Skibstatic bool 223235783Skibintel_dp_adjust_dithering(struct intel_dp *intel_dp, 224261631Sdumbbell const struct drm_display_mode *mode, 225235783Skib struct drm_display_mode *adjusted_mode) 226235783Skib{ 227235783Skib int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); 228235783Skib int max_lanes = intel_dp_max_lane_count(intel_dp); 229235783Skib int max_rate, mode_rate; 230235783Skib 231235783Skib mode_rate = intel_dp_link_required(mode->clock, 24); 232235783Skib max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 233235783Skib 234235783Skib if (mode_rate > max_rate) { 235235783Skib mode_rate = intel_dp_link_required(mode->clock, 18); 236235783Skib if (mode_rate > max_rate) 237235783Skib return false; 238235783Skib 239235783Skib if (adjusted_mode) 240235783Skib adjusted_mode->private_flags 241235783Skib |= INTEL_MODE_DP_FORCE_6BPC; 242235783Skib 243235783Skib return true; 244235783Skib } 245235783Skib 246235783Skib return true; 247235783Skib} 248235783Skib 249235783Skibstatic int 250235783Skibintel_dp_mode_valid(struct drm_connector *connector, 251235783Skib struct drm_display_mode *mode) 252235783Skib{ 253235783Skib struct intel_dp *intel_dp = intel_attached_dp(connector); 254235783Skib 255235783Skib if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { 256235783Skib if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay) 257235783Skib return MODE_PANEL; 258235783Skib 259235783Skib if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay) 260235783Skib return MODE_PANEL; 261235783Skib } 262235783Skib 263235783Skib if (!intel_dp_adjust_dithering(intel_dp, mode, NULL)) 264235783Skib return MODE_CLOCK_HIGH; 265235783Skib 266235783Skib if (mode->clock < 10000) 267235783Skib return MODE_CLOCK_LOW; 268235783Skib 269235783Skib return MODE_OK; 270235783Skib} 271235783Skib 272235783Skibstatic uint32_t 273235783Skibpack_aux(uint8_t *src, int src_bytes) 274235783Skib{ 275235783Skib int i; 276235783Skib uint32_t v = 0; 277235783Skib 278235783Skib if (src_bytes > 4) 279235783Skib src_bytes = 4; 280235783Skib for (i = 0; i < src_bytes; i++) 281235783Skib v |= ((uint32_t) src[i]) << ((3-i) * 8); 282235783Skib return v; 283235783Skib} 284235783Skib 285235783Skibstatic void 286235783Skibunpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 287235783Skib{ 288235783Skib int i; 289235783Skib if (dst_bytes > 4) 290235783Skib dst_bytes = 4; 291235783Skib for (i = 0; i < dst_bytes; i++) 292235783Skib dst[i] = src >> ((3-i) * 8); 293235783Skib} 294235783Skib 295235783Skib/* hrawclock is 1/4 the FSB frequency */ 296235783Skibstatic int 297235783Skibintel_hrawclk(struct drm_device *dev) 298235783Skib{ 299235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 300235783Skib uint32_t clkcfg; 301235783Skib 302235783Skib clkcfg = I915_READ(CLKCFG); 303235783Skib switch (clkcfg & CLKCFG_FSB_MASK) { 304235783Skib case CLKCFG_FSB_400: 305235783Skib return 100; 306235783Skib case CLKCFG_FSB_533: 307235783Skib return 133; 308235783Skib case CLKCFG_FSB_667: 309235783Skib return 166; 310235783Skib case CLKCFG_FSB_800: 311235783Skib return 200; 312235783Skib case CLKCFG_FSB_1067: 313235783Skib return 266; 314235783Skib case CLKCFG_FSB_1333: 315235783Skib return 333; 316235783Skib /* these two are just a guess; one of them might be right */ 317235783Skib case CLKCFG_FSB_1600: 318235783Skib case CLKCFG_FSB_1600_ALT: 319235783Skib return 400; 320235783Skib default: 321235783Skib return 133; 322235783Skib } 323235783Skib} 324235783Skib 325235783Skibstatic bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) 326235783Skib{ 327235783Skib struct drm_device *dev = intel_dp->base.base.dev; 328235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 329235783Skib 330235783Skib return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; 331235783Skib} 332235783Skib 333235783Skibstatic bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) 334235783Skib{ 335235783Skib struct drm_device *dev = intel_dp->base.base.dev; 336235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 337235783Skib 338235783Skib return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; 339235783Skib} 340235783Skib 341235783Skibstatic void 342235783Skibintel_dp_check_edp(struct intel_dp *intel_dp) 343235783Skib{ 344235783Skib struct drm_device *dev = intel_dp->base.base.dev; 345235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 346235783Skib 347235783Skib if (!is_edp(intel_dp)) 348235783Skib return; 349235783Skib if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { 350235783Skib printf("eDP powered off while attempting aux channel communication.\n"); 351235783Skib DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 352235783Skib I915_READ(PCH_PP_STATUS), 353235783Skib I915_READ(PCH_PP_CONTROL)); 354235783Skib } 355235783Skib} 356235783Skib 357235783Skibstatic int 358235783Skibintel_dp_aux_ch(struct intel_dp *intel_dp, 359235783Skib uint8_t *send, int send_bytes, 360235783Skib uint8_t *recv, int recv_size) 361235783Skib{ 362235783Skib uint32_t output_reg = intel_dp->output_reg; 363235783Skib struct drm_device *dev = intel_dp->base.base.dev; 364235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 365235783Skib uint32_t ch_ctl = output_reg + 0x10; 366235783Skib uint32_t ch_data = ch_ctl + 4; 367235783Skib int i; 368235783Skib int recv_bytes; 369235783Skib uint32_t status; 370235783Skib uint32_t aux_clock_divider; 371235783Skib int try, precharge = 5; 372235783Skib 373235783Skib intel_dp_check_edp(intel_dp); 374235783Skib /* The clock divider is based off the hrawclk, 375235783Skib * and would like to run at 2MHz. So, take the 376235783Skib * hrawclk value and divide by 2 and use that 377235783Skib * 378235783Skib * Note that PCH attached eDP panels should use a 125MHz input 379235783Skib * clock divider. 380235783Skib */ 381235783Skib if (is_cpu_edp(intel_dp)) { 382235783Skib if (IS_GEN6(dev) || IS_GEN7(dev)) 383235783Skib aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ 384235783Skib else 385235783Skib aux_clock_divider = 225; /* eDP input clock at 450Mhz */ 386235783Skib } else if (HAS_PCH_SPLIT(dev)) 387235783Skib aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */ 388235783Skib else 389235783Skib aux_clock_divider = intel_hrawclk(dev) / 2; 390235783Skib 391235783Skib /* Try to wait for any previous AUX channel activity */ 392235783Skib for (try = 0; try < 3; try++) { 393235783Skib status = I915_READ(ch_ctl); 394235783Skib if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 395235783Skib break; 396235783Skib drm_msleep(1, "915ach"); 397235783Skib } 398235783Skib 399235783Skib if (try == 3) { 400235783Skib printf("dp_aux_ch not started status 0x%08x\n", 401235783Skib I915_READ(ch_ctl)); 402235783Skib return -EBUSY; 403235783Skib } 404235783Skib 405235783Skib /* Must try at least 3 times according to DP spec */ 406235783Skib for (try = 0; try < 5; try++) { 407235783Skib /* Load the send data into the aux channel data registers */ 408235783Skib for (i = 0; i < send_bytes; i += 4) 409235783Skib I915_WRITE(ch_data + i, 410235783Skib pack_aux(send + i, send_bytes - i)); 411235783Skib 412235783Skib /* Send the command and wait for it to complete */ 413235783Skib I915_WRITE(ch_ctl, 414235783Skib DP_AUX_CH_CTL_SEND_BUSY | 415235783Skib DP_AUX_CH_CTL_TIME_OUT_400us | 416235783Skib (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 417235783Skib (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 418235783Skib (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | 419235783Skib DP_AUX_CH_CTL_DONE | 420235783Skib DP_AUX_CH_CTL_TIME_OUT_ERROR | 421235783Skib DP_AUX_CH_CTL_RECEIVE_ERROR); 422235783Skib for (;;) { 423235783Skib status = I915_READ(ch_ctl); 424235783Skib if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 425235783Skib break; 426235783Skib DELAY(100); 427235783Skib } 428235783Skib 429235783Skib /* Clear done status and any errors */ 430235783Skib I915_WRITE(ch_ctl, 431235783Skib status | 432235783Skib DP_AUX_CH_CTL_DONE | 433235783Skib DP_AUX_CH_CTL_TIME_OUT_ERROR | 434235783Skib DP_AUX_CH_CTL_RECEIVE_ERROR); 435235783Skib 436235783Skib if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 437235783Skib DP_AUX_CH_CTL_RECEIVE_ERROR)) 438235783Skib continue; 439235783Skib if (status & DP_AUX_CH_CTL_DONE) 440235783Skib break; 441235783Skib } 442235783Skib 443235783Skib if ((status & DP_AUX_CH_CTL_DONE) == 0) { 444235783Skib DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 445235783Skib return -EBUSY; 446235783Skib } 447235783Skib 448235783Skib /* Check for timeout or receive error. 449235783Skib * Timeouts occur when the sink is not connected 450235783Skib */ 451235783Skib if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 452235783Skib DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 453235783Skib return -EIO; 454235783Skib } 455235783Skib 456235783Skib /* Timeouts occur when the device isn't connected, so they're 457235783Skib * "normal" -- don't fill the kernel log with these */ 458235783Skib if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 459235783Skib DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 460235783Skib return -ETIMEDOUT; 461235783Skib } 462235783Skib 463235783Skib /* Unload any bytes sent back from the other side */ 464235783Skib recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 465235783Skib DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 466235783Skib if (recv_bytes > recv_size) 467235783Skib recv_bytes = recv_size; 468235783Skib 469235783Skib for (i = 0; i < recv_bytes; i += 4) 470235783Skib unpack_aux(I915_READ(ch_data + i), 471235783Skib recv + i, recv_bytes - i); 472235783Skib 473235783Skib return recv_bytes; 474235783Skib} 475235783Skib 476235783Skib/* Write data to the aux channel in native mode */ 477235783Skibstatic int 478235783Skibintel_dp_aux_native_write(struct intel_dp *intel_dp, 479235783Skib uint16_t address, uint8_t *send, int send_bytes) 480235783Skib{ 481235783Skib int ret; 482235783Skib uint8_t msg[20]; 483235783Skib int msg_bytes; 484235783Skib uint8_t ack; 485235783Skib 486235783Skib intel_dp_check_edp(intel_dp); 487235783Skib if (send_bytes > 16) 488235783Skib return -1; 489235783Skib msg[0] = AUX_NATIVE_WRITE << 4; 490235783Skib msg[1] = address >> 8; 491235783Skib msg[2] = address & 0xff; 492235783Skib msg[3] = send_bytes - 1; 493235783Skib memcpy(&msg[4], send, send_bytes); 494235783Skib msg_bytes = send_bytes + 4; 495235783Skib for (;;) { 496235783Skib ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 497235783Skib if (ret < 0) 498235783Skib return ret; 499235783Skib if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 500235783Skib break; 501235783Skib else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 502235783Skib DELAY(100); 503235783Skib else 504235783Skib return -EIO; 505235783Skib } 506235783Skib return send_bytes; 507235783Skib} 508235783Skib 509235783Skib/* Write a single byte to the aux channel in native mode */ 510235783Skibstatic int 511235783Skibintel_dp_aux_native_write_1(struct intel_dp *intel_dp, 512235783Skib uint16_t address, uint8_t byte) 513235783Skib{ 514235783Skib return intel_dp_aux_native_write(intel_dp, address, &byte, 1); 515235783Skib} 516235783Skib 517235783Skib/* read bytes from a native aux channel */ 518235783Skibstatic int 519235783Skibintel_dp_aux_native_read(struct intel_dp *intel_dp, 520235783Skib uint16_t address, uint8_t *recv, int recv_bytes) 521235783Skib{ 522235783Skib uint8_t msg[4]; 523235783Skib int msg_bytes; 524235783Skib uint8_t reply[20]; 525235783Skib int reply_bytes; 526235783Skib uint8_t ack; 527235783Skib int ret; 528235783Skib 529235783Skib intel_dp_check_edp(intel_dp); 530235783Skib msg[0] = AUX_NATIVE_READ << 4; 531235783Skib msg[1] = address >> 8; 532235783Skib msg[2] = address & 0xff; 533235783Skib msg[3] = recv_bytes - 1; 534235783Skib 535235783Skib msg_bytes = 4; 536235783Skib reply_bytes = recv_bytes + 1; 537235783Skib 538235783Skib for (;;) { 539235783Skib ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 540235783Skib reply, reply_bytes); 541235783Skib if (ret == 0) 542235783Skib return -EPROTO; 543235783Skib if (ret < 0) 544235783Skib return ret; 545235783Skib ack = reply[0]; 546235783Skib if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { 547235783Skib memcpy(recv, reply + 1, ret - 1); 548235783Skib return ret - 1; 549235783Skib } 550235783Skib else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 551235783Skib DELAY(100); 552235783Skib else 553235783Skib return -EIO; 554235783Skib } 555235783Skib} 556235783Skib 557235783Skibstatic int 558235783Skibintel_dp_i2c_aux_ch(device_t idev, int mode, uint8_t write_byte, 559235783Skib uint8_t *read_byte) 560235783Skib{ 561235783Skib struct iic_dp_aux_data *data; 562235783Skib struct intel_dp *intel_dp; 563235783Skib uint16_t address; 564235783Skib uint8_t msg[5]; 565235783Skib uint8_t reply[2]; 566235783Skib unsigned retry; 567235783Skib int msg_bytes; 568235783Skib int reply_bytes; 569235783Skib int ret; 570235783Skib 571235783Skib data = device_get_softc(idev); 572235783Skib intel_dp = data->priv; 573235783Skib address = data->address; 574235783Skib 575235783Skib intel_dp_check_edp(intel_dp); 576235783Skib /* Set up the command byte */ 577235783Skib if (mode & MODE_I2C_READ) 578235783Skib msg[0] = AUX_I2C_READ << 4; 579235783Skib else 580235783Skib msg[0] = AUX_I2C_WRITE << 4; 581235783Skib 582235783Skib if (!(mode & MODE_I2C_STOP)) 583235783Skib msg[0] |= AUX_I2C_MOT << 4; 584235783Skib 585235783Skib msg[1] = address >> 8; 586235783Skib msg[2] = address; 587235783Skib 588235783Skib switch (mode) { 589235783Skib case MODE_I2C_WRITE: 590235783Skib msg[3] = 0; 591235783Skib msg[4] = write_byte; 592235783Skib msg_bytes = 5; 593235783Skib reply_bytes = 1; 594235783Skib break; 595235783Skib case MODE_I2C_READ: 596235783Skib msg[3] = 0; 597235783Skib msg_bytes = 4; 598235783Skib reply_bytes = 2; 599235783Skib break; 600235783Skib default: 601235783Skib msg_bytes = 3; 602235783Skib reply_bytes = 1; 603235783Skib break; 604235783Skib } 605235783Skib 606235783Skib for (retry = 0; retry < 5; retry++) { 607235783Skib ret = intel_dp_aux_ch(intel_dp, 608235783Skib msg, msg_bytes, 609235783Skib reply, reply_bytes); 610235783Skib if (ret < 0) { 611235783Skib DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 612235783Skib return (-ret); 613235783Skib } 614235783Skib 615235783Skib switch (reply[0] & AUX_NATIVE_REPLY_MASK) { 616235783Skib case AUX_NATIVE_REPLY_ACK: 617235783Skib /* I2C-over-AUX Reply field is only valid 618235783Skib * when paired with AUX ACK. 619235783Skib */ 620235783Skib break; 621235783Skib case AUX_NATIVE_REPLY_NACK: 622235783Skib DRM_DEBUG_KMS("aux_ch native nack\n"); 623235783Skib return (EREMOTEIO); 624235783Skib case AUX_NATIVE_REPLY_DEFER: 625235783Skib DELAY(100); 626235783Skib continue; 627235783Skib default: 628235783Skib DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 629235783Skib reply[0]); 630235783Skib return (EREMOTEIO); 631235783Skib } 632235783Skib 633235783Skib switch (reply[0] & AUX_I2C_REPLY_MASK) { 634235783Skib case AUX_I2C_REPLY_ACK: 635235783Skib if (mode == MODE_I2C_READ) { 636235783Skib *read_byte = reply[1]; 637235783Skib } 638235783Skib return (0/*reply_bytes - 1*/); 639235783Skib case AUX_I2C_REPLY_NACK: 640235783Skib DRM_DEBUG_KMS("aux_i2c nack\n"); 641235783Skib return (EREMOTEIO); 642235783Skib case AUX_I2C_REPLY_DEFER: 643235783Skib DRM_DEBUG_KMS("aux_i2c defer\n"); 644235783Skib DELAY(100); 645235783Skib break; 646235783Skib default: 647235783Skib DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 648235783Skib return (EREMOTEIO); 649235783Skib } 650235783Skib } 651235783Skib 652235783Skib DRM_ERROR("too many retries, giving up\n"); 653235783Skib return (EREMOTEIO); 654235783Skib} 655235783Skib 656235783Skibstatic void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); 657235783Skibstatic void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 658235783Skib 659235783Skibstatic int 660235783Skibintel_dp_i2c_init(struct intel_dp *intel_dp, 661235783Skib struct intel_connector *intel_connector, const char *name) 662235783Skib{ 663235783Skib int ret; 664235783Skib 665235783Skib DRM_DEBUG_KMS("i2c_init %s\n", name); 666235783Skib 667235783Skib ironlake_edp_panel_vdd_on(intel_dp); 668235783Skib ret = iic_dp_aux_add_bus(intel_connector->base.dev->device, name, 669235783Skib intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus, 670235783Skib &intel_dp->adapter); 671235783Skib ironlake_edp_panel_vdd_off(intel_dp, false); 672235783Skib return (ret); 673235783Skib} 674235783Skib 675235783Skibstatic bool 676261631Sdumbbellintel_dp_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, 677235783Skib struct drm_display_mode *adjusted_mode) 678235783Skib{ 679235783Skib struct drm_device *dev = encoder->dev; 680235783Skib struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 681235783Skib int lane_count, clock; 682235783Skib int max_lane_count = intel_dp_max_lane_count(intel_dp); 683235783Skib int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 684235783Skib int bpp; 685235783Skib static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 686235783Skib 687235783Skib if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { 688235783Skib intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode); 689235783Skib intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, 690235783Skib mode, adjusted_mode); 691235783Skib } 692235783Skib 693261630Sdumbbell if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, adjusted_mode)) 694235783Skib return false; 695235783Skib 696235783Skib bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24; 697235783Skib 698235783Skib for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 699235783Skib for (clock = 0; clock <= max_clock; clock++) { 700235783Skib int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 701235783Skib 702261630Sdumbbell if (intel_dp_link_required(adjusted_mode->clock, bpp) 703235783Skib <= link_avail) { 704235783Skib intel_dp->link_bw = bws[clock]; 705235783Skib intel_dp->lane_count = lane_count; 706235783Skib adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 707235783Skib DRM_DEBUG_KMS("Display port link bw %02x lane " 708235783Skib "count %d clock %d\n", 709235783Skib intel_dp->link_bw, intel_dp->lane_count, 710235783Skib adjusted_mode->clock); 711235783Skib return true; 712235783Skib } 713235783Skib } 714235783Skib } 715235783Skib 716235783Skib return false; 717235783Skib} 718235783Skib 719235783Skibstruct intel_dp_m_n { 720235783Skib uint32_t tu; 721235783Skib uint32_t gmch_m; 722235783Skib uint32_t gmch_n; 723235783Skib uint32_t link_m; 724235783Skib uint32_t link_n; 725235783Skib}; 726235783Skib 727235783Skibstatic void 728235783Skibintel_reduce_ratio(uint32_t *num, uint32_t *den) 729235783Skib{ 730235783Skib while (*num > 0xffffff || *den > 0xffffff) { 731235783Skib *num >>= 1; 732235783Skib *den >>= 1; 733235783Skib } 734235783Skib} 735235783Skib 736235783Skibstatic void 737235783Skibintel_dp_compute_m_n(int bpp, 738235783Skib int nlanes, 739235783Skib int pixel_clock, 740235783Skib int link_clock, 741235783Skib struct intel_dp_m_n *m_n) 742235783Skib{ 743235783Skib m_n->tu = 64; 744235783Skib m_n->gmch_m = (pixel_clock * bpp) >> 3; 745235783Skib m_n->gmch_n = link_clock * nlanes; 746235783Skib intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 747235783Skib m_n->link_m = pixel_clock; 748235783Skib m_n->link_n = link_clock; 749235783Skib intel_reduce_ratio(&m_n->link_m, &m_n->link_n); 750235783Skib} 751235783Skib 752235783Skibvoid 753235783Skibintel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 754235783Skib struct drm_display_mode *adjusted_mode) 755235783Skib{ 756235783Skib struct drm_device *dev = crtc->dev; 757235783Skib struct drm_mode_config *mode_config = &dev->mode_config; 758235783Skib struct drm_encoder *encoder; 759235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 760235783Skib struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 761235783Skib int lane_count = 4; 762235783Skib struct intel_dp_m_n m_n; 763235783Skib int pipe = intel_crtc->pipe; 764235783Skib 765235783Skib /* 766235783Skib * Find the lane count in the intel_encoder private 767235783Skib */ 768235783Skib list_for_each_entry(encoder, &mode_config->encoder_list, head) { 769235783Skib struct intel_dp *intel_dp; 770235783Skib 771235783Skib if (encoder->crtc != crtc) 772235783Skib continue; 773235783Skib 774235783Skib intel_dp = enc_to_intel_dp(encoder); 775235783Skib if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || 776235783Skib intel_dp->base.type == INTEL_OUTPUT_EDP) 777235783Skib { 778235783Skib lane_count = intel_dp->lane_count; 779235783Skib break; 780235783Skib } 781235783Skib } 782235783Skib 783235783Skib /* 784235783Skib * Compute the GMCH and Link ratios. The '3' here is 785235783Skib * the number of bytes_per_pixel post-LUT, which we always 786235783Skib * set up for 8-bits of R/G/B, or 3 bytes total. 787235783Skib */ 788235783Skib intel_dp_compute_m_n(intel_crtc->bpp, lane_count, 789235783Skib mode->clock, adjusted_mode->clock, &m_n); 790235783Skib 791235783Skib if (HAS_PCH_SPLIT(dev)) { 792235783Skib I915_WRITE(TRANSDATA_M1(pipe), 793235783Skib ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 794235783Skib m_n.gmch_m); 795235783Skib I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); 796235783Skib I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); 797235783Skib I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); 798235783Skib } else { 799235783Skib I915_WRITE(PIPE_GMCH_DATA_M(pipe), 800235783Skib ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 801235783Skib m_n.gmch_m); 802235783Skib I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); 803235783Skib I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); 804235783Skib I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); 805235783Skib } 806235783Skib} 807235783Skib 808235783Skibstatic void ironlake_edp_pll_on(struct drm_encoder *encoder); 809235783Skibstatic void ironlake_edp_pll_off(struct drm_encoder *encoder); 810235783Skib 811235783Skibstatic void 812235783Skibintel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 813235783Skib struct drm_display_mode *adjusted_mode) 814235783Skib{ 815235783Skib struct drm_device *dev = encoder->dev; 816235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 817235783Skib struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 818235783Skib struct drm_crtc *crtc = intel_dp->base.base.crtc; 819235783Skib struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 820235783Skib 821235783Skib /* Turn on the eDP PLL if needed */ 822235783Skib if (is_edp(intel_dp)) { 823235783Skib if (!is_pch_edp(intel_dp)) 824235783Skib ironlake_edp_pll_on(encoder); 825235783Skib else 826235783Skib ironlake_edp_pll_off(encoder); 827235783Skib } 828235783Skib 829235783Skib /* 830235783Skib * There are four kinds of DP registers: 831235783Skib * 832235783Skib * IBX PCH 833235783Skib * SNB CPU 834235783Skib * IVB CPU 835235783Skib * CPT PCH 836235783Skib * 837235783Skib * IBX PCH and CPU are the same for almost everything, 838235783Skib * except that the CPU DP PLL is configured in this 839235783Skib * register 840235783Skib * 841235783Skib * CPT PCH is quite different, having many bits moved 842235783Skib * to the TRANS_DP_CTL register instead. That 843235783Skib * configuration happens (oddly) in ironlake_pch_enable 844235783Skib */ 845235783Skib 846235783Skib /* Preserve the BIOS-computed detected bit. This is 847235783Skib * supposed to be read-only. 848235783Skib */ 849235783Skib intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 850235783Skib intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 851235783Skib 852235783Skib /* Handle DP bits in common between all three register formats */ 853235783Skib 854235783Skib intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 855235783Skib 856235783Skib switch (intel_dp->lane_count) { 857235783Skib case 1: 858235783Skib intel_dp->DP |= DP_PORT_WIDTH_1; 859235783Skib break; 860235783Skib case 2: 861235783Skib intel_dp->DP |= DP_PORT_WIDTH_2; 862235783Skib break; 863235783Skib case 4: 864235783Skib intel_dp->DP |= DP_PORT_WIDTH_4; 865235783Skib break; 866235783Skib } 867235783Skib if (intel_dp->has_audio) { 868235783Skib DRM_DEBUG_KMS("Enabling DP audio on pipe %c\n", 869235783Skib pipe_name(intel_crtc->pipe)); 870235783Skib intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 871235783Skib intel_write_eld(encoder, adjusted_mode); 872235783Skib } 873235783Skib memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 874235783Skib intel_dp->link_configuration[0] = intel_dp->link_bw; 875235783Skib intel_dp->link_configuration[1] = intel_dp->lane_count; 876235783Skib /* 877235783Skib * Check for DPCD version > 1.1 and enhanced framing support 878235783Skib */ 879235783Skib if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 880235783Skib (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { 881235783Skib intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 882235783Skib } 883235783Skib 884235783Skib /* Split out the IBX/CPU vs CPT settings */ 885235783Skib 886235783Skib if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { 887235783Skib if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 888235783Skib intel_dp->DP |= DP_SYNC_HS_HIGH; 889235783Skib if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 890235783Skib intel_dp->DP |= DP_SYNC_VS_HIGH; 891235783Skib intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 892235783Skib 893235783Skib if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) 894235783Skib intel_dp->DP |= DP_ENHANCED_FRAMING; 895235783Skib 896235783Skib intel_dp->DP |= intel_crtc->pipe << 29; 897235783Skib 898235783Skib /* don't miss out required setting for eDP */ 899235783Skib intel_dp->DP |= DP_PLL_ENABLE; 900235783Skib if (adjusted_mode->clock < 200000) 901235783Skib intel_dp->DP |= DP_PLL_FREQ_160MHZ; 902235783Skib else 903235783Skib intel_dp->DP |= DP_PLL_FREQ_270MHZ; 904235783Skib } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { 905235783Skib intel_dp->DP |= intel_dp->color_range; 906235783Skib 907235783Skib if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 908235783Skib intel_dp->DP |= DP_SYNC_HS_HIGH; 909235783Skib if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 910235783Skib intel_dp->DP |= DP_SYNC_VS_HIGH; 911235783Skib intel_dp->DP |= DP_LINK_TRAIN_OFF; 912235783Skib 913235783Skib if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) 914235783Skib intel_dp->DP |= DP_ENHANCED_FRAMING; 915235783Skib 916235783Skib if (intel_crtc->pipe == 1) 917235783Skib intel_dp->DP |= DP_PIPEB_SELECT; 918235783Skib 919235783Skib if (is_cpu_edp(intel_dp)) { 920235783Skib /* don't miss out required setting for eDP */ 921235783Skib intel_dp->DP |= DP_PLL_ENABLE; 922235783Skib if (adjusted_mode->clock < 200000) 923235783Skib intel_dp->DP |= DP_PLL_FREQ_160MHZ; 924235783Skib else 925235783Skib intel_dp->DP |= DP_PLL_FREQ_270MHZ; 926235783Skib } 927235783Skib } else { 928235783Skib intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 929235783Skib } 930235783Skib} 931235783Skib 932235783Skib#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 933235783Skib#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 934235783Skib 935235783Skib#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 936235783Skib#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 937235783Skib 938235783Skib#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 939235783Skib#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 940235783Skib 941235783Skibstatic void ironlake_wait_panel_status(struct intel_dp *intel_dp, 942235783Skib u32 mask, 943235783Skib u32 value) 944235783Skib{ 945235783Skib struct drm_device *dev = intel_dp->base.base.dev; 946235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 947235783Skib 948235783Skib DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 949235783Skib mask, value, 950235783Skib I915_READ(PCH_PP_STATUS), 951235783Skib I915_READ(PCH_PP_CONTROL)); 952235783Skib 953235783Skib if (_intel_wait_for(dev, 954235783Skib (I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10, "915iwp")) { 955235783Skib DRM_ERROR("Panel status timeout: status %08x control %08x\n", 956235783Skib I915_READ(PCH_PP_STATUS), 957235783Skib I915_READ(PCH_PP_CONTROL)); 958235783Skib } 959235783Skib} 960235783Skib 961235783Skibstatic void ironlake_wait_panel_on(struct intel_dp *intel_dp) 962235783Skib{ 963235783Skib DRM_DEBUG_KMS("Wait for panel power on\n"); 964235783Skib ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 965235783Skib} 966235783Skib 967235783Skibstatic void ironlake_wait_panel_off(struct intel_dp *intel_dp) 968235783Skib{ 969235783Skib DRM_DEBUG_KMS("Wait for panel power off time\n"); 970235783Skib ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 971235783Skib} 972235783Skib 973235783Skibstatic void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) 974235783Skib{ 975235783Skib DRM_DEBUG_KMS("Wait for panel power cycle\n"); 976235783Skib ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 977235783Skib} 978235783Skib 979235783Skib 980235783Skib/* Read the current pp_control value, unlocking the register if it 981235783Skib * is locked 982235783Skib */ 983235783Skib 984235783Skibstatic u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv) 985235783Skib{ 986235783Skib u32 control = I915_READ(PCH_PP_CONTROL); 987235783Skib 988235783Skib control &= ~PANEL_UNLOCK_MASK; 989235783Skib control |= PANEL_UNLOCK_REGS; 990235783Skib return control; 991235783Skib} 992235783Skib 993235783Skibstatic void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) 994235783Skib{ 995235783Skib struct drm_device *dev = intel_dp->base.base.dev; 996235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 997235783Skib u32 pp; 998235783Skib 999235783Skib if (!is_edp(intel_dp)) 1000235783Skib return; 1001235783Skib DRM_DEBUG_KMS("Turn eDP VDD on\n"); 1002235783Skib 1003235783Skib if (intel_dp->want_panel_vdd) 1004235783Skib printf("eDP VDD already requested on\n"); 1005235783Skib 1006235783Skib intel_dp->want_panel_vdd = true; 1007235783Skib 1008235783Skib if (ironlake_edp_have_panel_vdd(intel_dp)) { 1009235783Skib DRM_DEBUG_KMS("eDP VDD already on\n"); 1010235783Skib return; 1011235783Skib } 1012235783Skib 1013235783Skib if (!ironlake_edp_have_panel_power(intel_dp)) 1014235783Skib ironlake_wait_panel_power_cycle(intel_dp); 1015235783Skib 1016235783Skib pp = ironlake_get_pp_control(dev_priv); 1017235783Skib pp |= EDP_FORCE_VDD; 1018235783Skib I915_WRITE(PCH_PP_CONTROL, pp); 1019235783Skib POSTING_READ(PCH_PP_CONTROL); 1020235783Skib DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", 1021235783Skib I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); 1022235783Skib 1023235783Skib /* 1024235783Skib * If the panel wasn't on, delay before accessing aux channel 1025235783Skib */ 1026235783Skib if (!ironlake_edp_have_panel_power(intel_dp)) { 1027235783Skib DRM_DEBUG_KMS("eDP was not running\n"); 1028235783Skib drm_msleep(intel_dp->panel_power_up_delay, "915edpon"); 1029235783Skib } 1030235783Skib} 1031235783Skib 1032235783Skibstatic void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) 1033235783Skib{ 1034235783Skib struct drm_device *dev = intel_dp->base.base.dev; 1035235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 1036235783Skib u32 pp; 1037235783Skib 1038235783Skib if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { 1039235783Skib pp = ironlake_get_pp_control(dev_priv); 1040235783Skib pp &= ~EDP_FORCE_VDD; 1041235783Skib I915_WRITE(PCH_PP_CONTROL, pp); 1042235783Skib POSTING_READ(PCH_PP_CONTROL); 1043235783Skib 1044235783Skib /* Make sure sequencer is idle before allowing subsequent activity */ 1045235783Skib DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", 1046235783Skib I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); 1047235783Skib 1048235783Skib drm_msleep(intel_dp->panel_power_down_delay, "915vddo"); 1049235783Skib } 1050235783Skib} 1051235783Skib 1052235783Skibstatic void ironlake_panel_vdd_work(void *arg, int pending __unused) 1053235783Skib{ 1054235783Skib struct intel_dp *intel_dp = arg; 1055235783Skib struct drm_device *dev = intel_dp->base.base.dev; 1056235783Skib 1057235783Skib sx_xlock(&dev->mode_config.mutex); 1058235783Skib ironlake_panel_vdd_off_sync(intel_dp); 1059235783Skib sx_xunlock(&dev->mode_config.mutex); 1060235783Skib} 1061235783Skib 1062235783Skibstatic void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1063235783Skib{ 1064235783Skib if (!is_edp(intel_dp)) 1065235783Skib return; 1066235783Skib 1067235783Skib DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); 1068235783Skib if (!intel_dp->want_panel_vdd) 1069235783Skib printf("eDP VDD not forced on\n"); 1070235783Skib 1071235783Skib intel_dp->want_panel_vdd = false; 1072235783Skib 1073235783Skib if (sync) { 1074235783Skib ironlake_panel_vdd_off_sync(intel_dp); 1075235783Skib } else { 1076235783Skib /* 1077235783Skib * Queue the timer to fire a long 1078235783Skib * time from now (relative to the power down delay) 1079235783Skib * to keep the panel power up across a sequence of operations 1080235783Skib */ 1081235783Skib struct drm_i915_private *dev_priv = intel_dp->base.base.dev->dev_private; 1082235783Skib taskqueue_enqueue_timeout(dev_priv->tq, 1083235783Skib &intel_dp->panel_vdd_task, 1084235783Skib msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); 1085235783Skib } 1086235783Skib} 1087235783Skib 1088235783Skibstatic void ironlake_edp_panel_on(struct intel_dp *intel_dp) 1089235783Skib{ 1090235783Skib struct drm_device *dev = intel_dp->base.base.dev; 1091235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 1092235783Skib u32 pp; 1093235783Skib 1094235783Skib if (!is_edp(intel_dp)) 1095235783Skib return; 1096235783Skib 1097235783Skib DRM_DEBUG_KMS("Turn eDP power on\n"); 1098235783Skib 1099235783Skib if (ironlake_edp_have_panel_power(intel_dp)) { 1100235783Skib DRM_DEBUG_KMS("eDP power already on\n"); 1101235783Skib return; 1102235783Skib } 1103235783Skib 1104235783Skib ironlake_wait_panel_power_cycle(intel_dp); 1105235783Skib 1106235783Skib pp = ironlake_get_pp_control(dev_priv); 1107235783Skib if (IS_GEN5(dev)) { 1108235783Skib /* ILK workaround: disable reset around power sequence */ 1109235783Skib pp &= ~PANEL_POWER_RESET; 1110235783Skib I915_WRITE(PCH_PP_CONTROL, pp); 1111235783Skib POSTING_READ(PCH_PP_CONTROL); 1112235783Skib } 1113235783Skib 1114235783Skib pp |= POWER_TARGET_ON; 1115235783Skib if (!IS_GEN5(dev)) 1116235783Skib pp |= PANEL_POWER_RESET; 1117235783Skib 1118235783Skib I915_WRITE(PCH_PP_CONTROL, pp); 1119235783Skib POSTING_READ(PCH_PP_CONTROL); 1120235783Skib 1121235783Skib ironlake_wait_panel_on(intel_dp); 1122235783Skib 1123235783Skib if (IS_GEN5(dev)) { 1124235783Skib pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1125235783Skib I915_WRITE(PCH_PP_CONTROL, pp); 1126235783Skib POSTING_READ(PCH_PP_CONTROL); 1127235783Skib } 1128235783Skib} 1129235783Skib 1130235783Skibstatic void ironlake_edp_panel_off(struct intel_dp *intel_dp) 1131235783Skib{ 1132235783Skib struct drm_device *dev = intel_dp->base.base.dev; 1133235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 1134235783Skib u32 pp; 1135235783Skib 1136235783Skib if (!is_edp(intel_dp)) 1137235783Skib return; 1138235783Skib 1139235783Skib DRM_DEBUG_KMS("Turn eDP power off\n"); 1140235783Skib 1141235783Skib if (intel_dp->want_panel_vdd) 1142235783Skib printf("Cannot turn power off while VDD is on\n"); 1143235783Skib 1144235783Skib pp = ironlake_get_pp_control(dev_priv); 1145235783Skib pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); 1146235783Skib I915_WRITE(PCH_PP_CONTROL, pp); 1147235783Skib POSTING_READ(PCH_PP_CONTROL); 1148235783Skib 1149235783Skib ironlake_wait_panel_off(intel_dp); 1150235783Skib} 1151235783Skib 1152235783Skibstatic void ironlake_edp_backlight_on(struct intel_dp *intel_dp) 1153235783Skib{ 1154235783Skib struct drm_device *dev = intel_dp->base.base.dev; 1155235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 1156235783Skib u32 pp; 1157235783Skib 1158235783Skib if (!is_edp(intel_dp)) 1159235783Skib return; 1160235783Skib 1161235783Skib DRM_DEBUG_KMS("\n"); 1162235783Skib /* 1163235783Skib * If we enable the backlight right away following a panel power 1164235783Skib * on, we may see slight flicker as the panel syncs with the eDP 1165235783Skib * link. So delay a bit to make sure the image is solid before 1166235783Skib * allowing it to appear. 1167235783Skib */ 1168235783Skib drm_msleep(intel_dp->backlight_on_delay, "915ebo"); 1169235783Skib pp = ironlake_get_pp_control(dev_priv); 1170235783Skib pp |= EDP_BLC_ENABLE; 1171235783Skib I915_WRITE(PCH_PP_CONTROL, pp); 1172235783Skib POSTING_READ(PCH_PP_CONTROL); 1173235783Skib} 1174235783Skib 1175235783Skibstatic void ironlake_edp_backlight_off(struct intel_dp *intel_dp) 1176235783Skib{ 1177235783Skib struct drm_device *dev = intel_dp->base.base.dev; 1178235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 1179235783Skib u32 pp; 1180235783Skib 1181235783Skib if (!is_edp(intel_dp)) 1182235783Skib return; 1183235783Skib 1184235783Skib DRM_DEBUG_KMS("\n"); 1185235783Skib pp = ironlake_get_pp_control(dev_priv); 1186235783Skib pp &= ~EDP_BLC_ENABLE; 1187235783Skib I915_WRITE(PCH_PP_CONTROL, pp); 1188235783Skib POSTING_READ(PCH_PP_CONTROL); 1189235783Skib drm_msleep(intel_dp->backlight_off_delay, "915bo1"); 1190235783Skib} 1191235783Skib 1192235783Skibstatic void ironlake_edp_pll_on(struct drm_encoder *encoder) 1193235783Skib{ 1194235783Skib struct drm_device *dev = encoder->dev; 1195235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 1196235783Skib u32 dpa_ctl; 1197235783Skib 1198235783Skib DRM_DEBUG_KMS("\n"); 1199235783Skib dpa_ctl = I915_READ(DP_A); 1200235783Skib dpa_ctl |= DP_PLL_ENABLE; 1201235783Skib I915_WRITE(DP_A, dpa_ctl); 1202235783Skib POSTING_READ(DP_A); 1203235783Skib DELAY(200); 1204235783Skib} 1205235783Skib 1206235783Skibstatic void ironlake_edp_pll_off(struct drm_encoder *encoder) 1207235783Skib{ 1208235783Skib struct drm_device *dev = encoder->dev; 1209235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 1210235783Skib u32 dpa_ctl; 1211235783Skib 1212235783Skib dpa_ctl = I915_READ(DP_A); 1213235783Skib dpa_ctl &= ~DP_PLL_ENABLE; 1214235783Skib I915_WRITE(DP_A, dpa_ctl); 1215235783Skib POSTING_READ(DP_A); 1216235783Skib DELAY(200); 1217235783Skib} 1218235783Skib 1219235783Skib/* If the sink supports it, try to set the power state appropriately */ 1220235783Skibstatic void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1221235783Skib{ 1222235783Skib int ret, i; 1223235783Skib 1224235783Skib /* Should have a valid DPCD by this point */ 1225235783Skib if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1226235783Skib return; 1227235783Skib 1228235783Skib if (mode != DRM_MODE_DPMS_ON) { 1229235783Skib ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, 1230235783Skib DP_SET_POWER_D3); 1231235783Skib if (ret != 1) 1232235783Skib DRM_DEBUG("failed to write sink power state\n"); 1233235783Skib } else { 1234235783Skib /* 1235235783Skib * When turning on, we need to retry for 1ms to give the sink 1236235783Skib * time to wake up. 1237235783Skib */ 1238235783Skib for (i = 0; i < 3; i++) { 1239235783Skib ret = intel_dp_aux_native_write_1(intel_dp, 1240235783Skib DP_SET_POWER, 1241235783Skib DP_SET_POWER_D0); 1242235783Skib if (ret == 1) 1243235783Skib break; 1244235783Skib drm_msleep(1, "915dps"); 1245235783Skib } 1246235783Skib } 1247235783Skib} 1248235783Skib 1249235783Skibstatic void intel_dp_prepare(struct drm_encoder *encoder) 1250235783Skib{ 1251235783Skib struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1252235783Skib 1253235783Skib ironlake_edp_backlight_off(intel_dp); 1254235783Skib ironlake_edp_panel_off(intel_dp); 1255235783Skib 1256235783Skib /* Wake up the sink first */ 1257235783Skib ironlake_edp_panel_vdd_on(intel_dp); 1258235783Skib intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1259235783Skib intel_dp_link_down(intel_dp); 1260235783Skib ironlake_edp_panel_vdd_off(intel_dp, false); 1261235783Skib 1262235783Skib /* Make sure the panel is off before trying to 1263235783Skib * change the mode 1264235783Skib */ 1265235783Skib} 1266235783Skib 1267235783Skibstatic void intel_dp_commit(struct drm_encoder *encoder) 1268235783Skib{ 1269235783Skib struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1270235783Skib struct drm_device *dev = encoder->dev; 1271235783Skib struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); 1272235783Skib 1273235783Skib ironlake_edp_panel_vdd_on(intel_dp); 1274235783Skib intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1275235783Skib intel_dp_start_link_train(intel_dp); 1276235783Skib ironlake_edp_panel_on(intel_dp); 1277235783Skib ironlake_edp_panel_vdd_off(intel_dp, true); 1278235783Skib intel_dp_complete_link_train(intel_dp); 1279235783Skib ironlake_edp_backlight_on(intel_dp); 1280235783Skib 1281235783Skib intel_dp->dpms_mode = DRM_MODE_DPMS_ON; 1282235783Skib 1283235783Skib if (HAS_PCH_CPT(dev)) 1284235783Skib intel_cpt_verify_modeset(dev, intel_crtc->pipe); 1285235783Skib} 1286235783Skib 1287235783Skibstatic void 1288235783Skibintel_dp_dpms(struct drm_encoder *encoder, int mode) 1289235783Skib{ 1290235783Skib struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1291235783Skib struct drm_device *dev = encoder->dev; 1292235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 1293235783Skib uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1294235783Skib 1295235783Skib if (mode != DRM_MODE_DPMS_ON) { 1296235783Skib ironlake_edp_backlight_off(intel_dp); 1297235783Skib ironlake_edp_panel_off(intel_dp); 1298235783Skib 1299235783Skib ironlake_edp_panel_vdd_on(intel_dp); 1300235783Skib intel_dp_sink_dpms(intel_dp, mode); 1301235783Skib intel_dp_link_down(intel_dp); 1302235783Skib ironlake_edp_panel_vdd_off(intel_dp, false); 1303235783Skib 1304235783Skib if (is_cpu_edp(intel_dp)) 1305235783Skib ironlake_edp_pll_off(encoder); 1306235783Skib } else { 1307235783Skib if (is_cpu_edp(intel_dp)) 1308235783Skib ironlake_edp_pll_on(encoder); 1309235783Skib 1310235783Skib ironlake_edp_panel_vdd_on(intel_dp); 1311235783Skib intel_dp_sink_dpms(intel_dp, mode); 1312235783Skib if (!(dp_reg & DP_PORT_EN)) { 1313235783Skib intel_dp_start_link_train(intel_dp); 1314235783Skib ironlake_edp_panel_on(intel_dp); 1315235783Skib ironlake_edp_panel_vdd_off(intel_dp, true); 1316235783Skib intel_dp_complete_link_train(intel_dp); 1317235783Skib } else 1318235783Skib ironlake_edp_panel_vdd_off(intel_dp, false); 1319235783Skib ironlake_edp_backlight_on(intel_dp); 1320235783Skib } 1321235783Skib intel_dp->dpms_mode = mode; 1322235783Skib} 1323235783Skib/* 1324235783Skib * Native read with retry for link status and receiver capability reads for 1325235783Skib * cases where the sink may still be asleep. 1326235783Skib */ 1327235783Skibstatic bool 1328235783Skibintel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, 1329235783Skib uint8_t *recv, int recv_bytes) 1330235783Skib{ 1331235783Skib int ret, i; 1332235783Skib 1333235783Skib /* 1334235783Skib * Sinks are *supposed* to come up within 1ms from an off state, 1335235783Skib * but we're also supposed to retry 3 times per the spec. 1336235783Skib */ 1337235783Skib for (i = 0; i < 3; i++) { 1338235783Skib ret = intel_dp_aux_native_read(intel_dp, address, recv, 1339235783Skib recv_bytes); 1340235783Skib if (ret == recv_bytes) 1341235783Skib return true; 1342235783Skib drm_msleep(1, "915dpl"); 1343235783Skib } 1344235783Skib 1345235783Skib return false; 1346235783Skib} 1347235783Skib 1348235783Skib/* 1349235783Skib * Fetch AUX CH registers 0x202 - 0x207 which contain 1350235783Skib * link status information 1351235783Skib */ 1352235783Skibstatic bool 1353235783Skibintel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1354235783Skib{ 1355235783Skib return intel_dp_aux_native_read_retry(intel_dp, 1356235783Skib DP_LANE0_1_STATUS, 1357235783Skib link_status, 1358235783Skib DP_LINK_STATUS_SIZE); 1359235783Skib} 1360235783Skib 1361235783Skibstatic uint8_t 1362235783Skibintel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1363235783Skib int r) 1364235783Skib{ 1365235783Skib return link_status[r - DP_LANE0_1_STATUS]; 1366235783Skib} 1367235783Skib 1368235783Skibstatic uint8_t 1369235783Skibintel_get_adjust_request_voltage(uint8_t adjust_request[2], 1370235783Skib int lane) 1371235783Skib{ 1372235783Skib int s = ((lane & 1) ? 1373235783Skib DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 1374235783Skib DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 1375235783Skib uint8_t l = adjust_request[lane>>1]; 1376235783Skib 1377235783Skib return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 1378235783Skib} 1379235783Skib 1380235783Skibstatic uint8_t 1381235783Skibintel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2], 1382235783Skib int lane) 1383235783Skib{ 1384235783Skib int s = ((lane & 1) ? 1385235783Skib DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 1386235783Skib DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 1387235783Skib uint8_t l = adjust_request[lane>>1]; 1388235783Skib 1389235783Skib return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 1390235783Skib} 1391235783Skib 1392235783Skib 1393235783Skib#if 0 1394235783Skibstatic char *voltage_names[] = { 1395235783Skib "0.4V", "0.6V", "0.8V", "1.2V" 1396235783Skib}; 1397235783Skibstatic char *pre_emph_names[] = { 1398235783Skib "0dB", "3.5dB", "6dB", "9.5dB" 1399235783Skib}; 1400235783Skibstatic char *link_train_names[] = { 1401235783Skib "pattern 1", "pattern 2", "idle", "off" 1402235783Skib}; 1403235783Skib#endif 1404235783Skib 1405235783Skib/* 1406235783Skib * These are source-specific values; current Intel hardware supports 1407235783Skib * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 1408235783Skib */ 1409235783Skib 1410235783Skibstatic uint8_t 1411235783Skibintel_dp_voltage_max(struct intel_dp *intel_dp) 1412235783Skib{ 1413235783Skib struct drm_device *dev = intel_dp->base.base.dev; 1414235783Skib 1415235783Skib if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) 1416235783Skib return DP_TRAIN_VOLTAGE_SWING_800; 1417235783Skib else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) 1418235783Skib return DP_TRAIN_VOLTAGE_SWING_1200; 1419235783Skib else 1420235783Skib return DP_TRAIN_VOLTAGE_SWING_800; 1421235783Skib} 1422235783Skib 1423235783Skibstatic uint8_t 1424235783Skibintel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 1425235783Skib{ 1426235783Skib struct drm_device *dev = intel_dp->base.base.dev; 1427235783Skib 1428235783Skib if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { 1429235783Skib switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1430235783Skib case DP_TRAIN_VOLTAGE_SWING_400: 1431235783Skib return DP_TRAIN_PRE_EMPHASIS_6; 1432235783Skib case DP_TRAIN_VOLTAGE_SWING_600: 1433235783Skib case DP_TRAIN_VOLTAGE_SWING_800: 1434235783Skib return DP_TRAIN_PRE_EMPHASIS_3_5; 1435235783Skib default: 1436235783Skib return DP_TRAIN_PRE_EMPHASIS_0; 1437235783Skib } 1438235783Skib } else { 1439235783Skib switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1440235783Skib case DP_TRAIN_VOLTAGE_SWING_400: 1441235783Skib return DP_TRAIN_PRE_EMPHASIS_6; 1442235783Skib case DP_TRAIN_VOLTAGE_SWING_600: 1443235783Skib return DP_TRAIN_PRE_EMPHASIS_6; 1444235783Skib case DP_TRAIN_VOLTAGE_SWING_800: 1445235783Skib return DP_TRAIN_PRE_EMPHASIS_3_5; 1446235783Skib case DP_TRAIN_VOLTAGE_SWING_1200: 1447235783Skib default: 1448235783Skib return DP_TRAIN_PRE_EMPHASIS_0; 1449235783Skib } 1450235783Skib } 1451235783Skib} 1452235783Skib 1453235783Skibstatic void 1454235783Skibintel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1455235783Skib{ 1456235783Skib uint8_t v = 0; 1457235783Skib uint8_t p = 0; 1458235783Skib int lane; 1459235783Skib uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS); 1460235783Skib uint8_t voltage_max; 1461235783Skib uint8_t preemph_max; 1462235783Skib 1463235783Skib for (lane = 0; lane < intel_dp->lane_count; lane++) { 1464235783Skib uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane); 1465235783Skib uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane); 1466235783Skib 1467235783Skib if (this_v > v) 1468235783Skib v = this_v; 1469235783Skib if (this_p > p) 1470235783Skib p = this_p; 1471235783Skib } 1472235783Skib 1473235783Skib voltage_max = intel_dp_voltage_max(intel_dp); 1474235783Skib if (v >= voltage_max) 1475235783Skib v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 1476235783Skib 1477235783Skib preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 1478235783Skib if (p >= preemph_max) 1479235783Skib p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1480235783Skib 1481235783Skib for (lane = 0; lane < 4; lane++) 1482235783Skib intel_dp->train_set[lane] = v | p; 1483235783Skib} 1484235783Skib 1485235783Skibstatic uint32_t 1486235783Skibintel_dp_signal_levels(uint8_t train_set) 1487235783Skib{ 1488235783Skib uint32_t signal_levels = 0; 1489235783Skib 1490235783Skib switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 1491235783Skib case DP_TRAIN_VOLTAGE_SWING_400: 1492235783Skib default: 1493235783Skib signal_levels |= DP_VOLTAGE_0_4; 1494235783Skib break; 1495235783Skib case DP_TRAIN_VOLTAGE_SWING_600: 1496235783Skib signal_levels |= DP_VOLTAGE_0_6; 1497235783Skib break; 1498235783Skib case DP_TRAIN_VOLTAGE_SWING_800: 1499235783Skib signal_levels |= DP_VOLTAGE_0_8; 1500235783Skib break; 1501235783Skib case DP_TRAIN_VOLTAGE_SWING_1200: 1502235783Skib signal_levels |= DP_VOLTAGE_1_2; 1503235783Skib break; 1504235783Skib } 1505235783Skib switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 1506235783Skib case DP_TRAIN_PRE_EMPHASIS_0: 1507235783Skib default: 1508235783Skib signal_levels |= DP_PRE_EMPHASIS_0; 1509235783Skib break; 1510235783Skib case DP_TRAIN_PRE_EMPHASIS_3_5: 1511235783Skib signal_levels |= DP_PRE_EMPHASIS_3_5; 1512235783Skib break; 1513235783Skib case DP_TRAIN_PRE_EMPHASIS_6: 1514235783Skib signal_levels |= DP_PRE_EMPHASIS_6; 1515235783Skib break; 1516235783Skib case DP_TRAIN_PRE_EMPHASIS_9_5: 1517235783Skib signal_levels |= DP_PRE_EMPHASIS_9_5; 1518235783Skib break; 1519235783Skib } 1520235783Skib return signal_levels; 1521235783Skib} 1522235783Skib 1523235783Skib/* Gen6's DP voltage swing and pre-emphasis control */ 1524235783Skibstatic uint32_t 1525235783Skibintel_gen6_edp_signal_levels(uint8_t train_set) 1526235783Skib{ 1527235783Skib int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1528235783Skib DP_TRAIN_PRE_EMPHASIS_MASK); 1529235783Skib switch (signal_levels) { 1530235783Skib case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1531235783Skib case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1532235783Skib return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1533235783Skib case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1534235783Skib return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1535235783Skib case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1536235783Skib case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 1537235783Skib return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1538235783Skib case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1539235783Skib case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1540235783Skib return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1541235783Skib case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1542235783Skib case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 1543235783Skib return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1544235783Skib default: 1545235783Skib DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1546235783Skib "0x%x\n", signal_levels); 1547235783Skib return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1548235783Skib } 1549235783Skib} 1550235783Skib 1551235783Skib/* Gen7's DP voltage swing and pre-emphasis control */ 1552235783Skibstatic uint32_t 1553235783Skibintel_gen7_edp_signal_levels(uint8_t train_set) 1554235783Skib{ 1555235783Skib int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1556235783Skib DP_TRAIN_PRE_EMPHASIS_MASK); 1557235783Skib switch (signal_levels) { 1558235783Skib case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1559235783Skib return EDP_LINK_TRAIN_400MV_0DB_IVB; 1560235783Skib case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1561235783Skib return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 1562235783Skib case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1563235783Skib return EDP_LINK_TRAIN_400MV_6DB_IVB; 1564235783Skib 1565235783Skib case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1566235783Skib return EDP_LINK_TRAIN_600MV_0DB_IVB; 1567235783Skib case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1568235783Skib return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 1569235783Skib 1570235783Skib case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1571235783Skib return EDP_LINK_TRAIN_800MV_0DB_IVB; 1572235783Skib case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1573235783Skib return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 1574235783Skib 1575235783Skib default: 1576235783Skib DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1577235783Skib "0x%x\n", signal_levels); 1578235783Skib return EDP_LINK_TRAIN_500MV_0DB_IVB; 1579235783Skib } 1580235783Skib} 1581235783Skib 1582235783Skibstatic uint8_t 1583235783Skibintel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1584235783Skib int lane) 1585235783Skib{ 1586235783Skib int s = (lane & 1) * 4; 1587235783Skib uint8_t l = link_status[lane>>1]; 1588235783Skib 1589235783Skib return (l >> s) & 0xf; 1590235783Skib} 1591235783Skib 1592235783Skib/* Check for clock recovery is done on all channels */ 1593235783Skibstatic bool 1594235783Skibintel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) 1595235783Skib{ 1596235783Skib int lane; 1597235783Skib uint8_t lane_status; 1598235783Skib 1599235783Skib for (lane = 0; lane < lane_count; lane++) { 1600235783Skib lane_status = intel_get_lane_status(link_status, lane); 1601235783Skib if ((lane_status & DP_LANE_CR_DONE) == 0) 1602235783Skib return false; 1603235783Skib } 1604235783Skib return true; 1605235783Skib} 1606235783Skib 1607235783Skib/* Check to see if channel eq is done on all channels */ 1608235783Skib#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ 1609235783Skib DP_LANE_CHANNEL_EQ_DONE|\ 1610235783Skib DP_LANE_SYMBOL_LOCKED) 1611235783Skibstatic bool 1612235783Skibintel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1613235783Skib{ 1614235783Skib uint8_t lane_align; 1615235783Skib uint8_t lane_status; 1616235783Skib int lane; 1617235783Skib 1618235783Skib lane_align = intel_dp_link_status(link_status, 1619235783Skib DP_LANE_ALIGN_STATUS_UPDATED); 1620235783Skib if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 1621235783Skib return false; 1622235783Skib for (lane = 0; lane < intel_dp->lane_count; lane++) { 1623235783Skib lane_status = intel_get_lane_status(link_status, lane); 1624235783Skib if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) 1625235783Skib return false; 1626235783Skib } 1627235783Skib return true; 1628235783Skib} 1629235783Skib 1630235783Skibstatic bool 1631235783Skibintel_dp_set_link_train(struct intel_dp *intel_dp, 1632235783Skib uint32_t dp_reg_value, 1633235783Skib uint8_t dp_train_pat) 1634235783Skib{ 1635235783Skib struct drm_device *dev = intel_dp->base.base.dev; 1636235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 1637235783Skib int ret; 1638235783Skib 1639235783Skib I915_WRITE(intel_dp->output_reg, dp_reg_value); 1640235783Skib POSTING_READ(intel_dp->output_reg); 1641235783Skib 1642235783Skib intel_dp_aux_native_write_1(intel_dp, 1643235783Skib DP_TRAINING_PATTERN_SET, 1644235783Skib dp_train_pat); 1645235783Skib 1646235783Skib ret = intel_dp_aux_native_write(intel_dp, 1647235783Skib DP_TRAINING_LANE0_SET, 1648235783Skib intel_dp->train_set, 1649235783Skib intel_dp->lane_count); 1650235783Skib if (ret != intel_dp->lane_count) 1651235783Skib return false; 1652235783Skib 1653235783Skib return true; 1654235783Skib} 1655235783Skib 1656235783Skib/* Enable corresponding port and start training pattern 1 */ 1657235783Skibstatic void 1658235783Skibintel_dp_start_link_train(struct intel_dp *intel_dp) 1659235783Skib{ 1660235783Skib struct drm_device *dev = intel_dp->base.base.dev; 1661235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 1662235783Skib struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); 1663235783Skib int i; 1664235783Skib uint8_t voltage; 1665235783Skib bool clock_recovery = false; 1666235783Skib int voltage_tries, loop_tries; 1667235783Skib u32 reg; 1668235783Skib uint32_t DP = intel_dp->DP; 1669235783Skib 1670235783Skib /* Enable output, wait for it to become active */ 1671235783Skib I915_WRITE(intel_dp->output_reg, intel_dp->DP); 1672235783Skib POSTING_READ(intel_dp->output_reg); 1673235783Skib intel_wait_for_vblank(dev, intel_crtc->pipe); 1674235783Skib 1675235783Skib /* Write the link configuration data */ 1676235783Skib intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, 1677235783Skib intel_dp->link_configuration, 1678235783Skib DP_LINK_CONFIGURATION_SIZE); 1679235783Skib 1680235783Skib DP |= DP_PORT_EN; 1681235783Skib 1682235783Skib if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) 1683235783Skib DP &= ~DP_LINK_TRAIN_MASK_CPT; 1684235783Skib else 1685235783Skib DP &= ~DP_LINK_TRAIN_MASK; 1686235783Skib memset(intel_dp->train_set, 0, 4); 1687235783Skib voltage = 0xff; 1688235783Skib voltage_tries = 0; 1689235783Skib loop_tries = 0; 1690235783Skib clock_recovery = false; 1691235783Skib for (;;) { 1692235783Skib /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1693235783Skib uint8_t link_status[DP_LINK_STATUS_SIZE]; 1694235783Skib uint32_t signal_levels; 1695235783Skib 1696235783Skib 1697235783Skib if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { 1698235783Skib signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); 1699235783Skib DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; 1700235783Skib } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { 1701235783Skib signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1702235783Skib DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1703235783Skib } else { 1704235783Skib signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); 1705235783Skib DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels); 1706235783Skib DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1707235783Skib } 1708235783Skib 1709235783Skib if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) 1710235783Skib reg = DP | DP_LINK_TRAIN_PAT_1_CPT; 1711235783Skib else 1712235783Skib reg = DP | DP_LINK_TRAIN_PAT_1; 1713235783Skib 1714235783Skib if (!intel_dp_set_link_train(intel_dp, reg, 1715235783Skib DP_TRAINING_PATTERN_1)) 1716235783Skib break; 1717235783Skib /* Set training pattern 1 */ 1718235783Skib 1719235783Skib DELAY(100); 1720235783Skib if (!intel_dp_get_link_status(intel_dp, link_status)) { 1721235783Skib DRM_ERROR("failed to get link status\n"); 1722235783Skib break; 1723235783Skib } 1724235783Skib 1725235783Skib if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { 1726235783Skib DRM_DEBUG_KMS("clock recovery OK\n"); 1727235783Skib clock_recovery = true; 1728235783Skib break; 1729235783Skib } 1730235783Skib 1731235783Skib /* Check to see if we've tried the max voltage */ 1732235783Skib for (i = 0; i < intel_dp->lane_count; i++) 1733235783Skib if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1734235783Skib break; 1735235783Skib if (i == intel_dp->lane_count) { 1736235783Skib ++loop_tries; 1737235783Skib if (loop_tries == 5) { 1738235783Skib DRM_DEBUG_KMS("too many full retries, give up\n"); 1739235783Skib break; 1740235783Skib } 1741235783Skib memset(intel_dp->train_set, 0, 4); 1742235783Skib voltage_tries = 0; 1743235783Skib continue; 1744235783Skib } 1745235783Skib 1746235783Skib /* Check to see if we've tried the same voltage 5 times */ 1747235783Skib if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 1748235783Skib ++voltage_tries; 1749235783Skib if (voltage_tries == 5) { 1750235783Skib DRM_DEBUG_KMS("too many voltage retries, give up\n"); 1751235783Skib break; 1752235783Skib } 1753235783Skib } else 1754235783Skib voltage_tries = 0; 1755235783Skib voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1756235783Skib 1757235783Skib /* Compute new intel_dp->train_set as requested by target */ 1758235783Skib intel_get_adjust_train(intel_dp, link_status); 1759235783Skib } 1760235783Skib 1761235783Skib intel_dp->DP = DP; 1762235783Skib} 1763235783Skib 1764235783Skibstatic void 1765235783Skibintel_dp_complete_link_train(struct intel_dp *intel_dp) 1766235783Skib{ 1767235783Skib struct drm_device *dev = intel_dp->base.base.dev; 1768235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 1769235783Skib bool channel_eq = false; 1770235783Skib int tries, cr_tries; 1771235783Skib u32 reg; 1772235783Skib uint32_t DP = intel_dp->DP; 1773235783Skib 1774235783Skib /* channel equalization */ 1775235783Skib tries = 0; 1776235783Skib cr_tries = 0; 1777235783Skib channel_eq = false; 1778235783Skib for (;;) { 1779235783Skib /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1780235783Skib uint32_t signal_levels; 1781235783Skib uint8_t link_status[DP_LINK_STATUS_SIZE]; 1782235783Skib 1783235783Skib if (cr_tries > 5) { 1784235783Skib DRM_ERROR("failed to train DP, aborting\n"); 1785235783Skib intel_dp_link_down(intel_dp); 1786235783Skib break; 1787235783Skib } 1788235783Skib 1789235783Skib if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { 1790235783Skib signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); 1791235783Skib DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; 1792235783Skib } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { 1793235783Skib signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1794235783Skib DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1795235783Skib } else { 1796235783Skib signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); 1797235783Skib DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1798235783Skib } 1799235783Skib 1800235783Skib if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) 1801235783Skib reg = DP | DP_LINK_TRAIN_PAT_2_CPT; 1802235783Skib else 1803235783Skib reg = DP | DP_LINK_TRAIN_PAT_2; 1804235783Skib 1805235783Skib /* channel eq pattern */ 1806235783Skib if (!intel_dp_set_link_train(intel_dp, reg, 1807235783Skib DP_TRAINING_PATTERN_2)) 1808235783Skib break; 1809235783Skib 1810235783Skib DELAY(400); 1811235783Skib if (!intel_dp_get_link_status(intel_dp, link_status)) 1812235783Skib break; 1813235783Skib 1814235783Skib /* Make sure clock is still ok */ 1815235783Skib if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { 1816235783Skib intel_dp_start_link_train(intel_dp); 1817235783Skib cr_tries++; 1818235783Skib continue; 1819235783Skib } 1820235783Skib 1821235783Skib if (intel_channel_eq_ok(intel_dp, link_status)) { 1822235783Skib channel_eq = true; 1823235783Skib break; 1824235783Skib } 1825235783Skib 1826235783Skib /* Try 5 times, then try clock recovery if that fails */ 1827235783Skib if (tries > 5) { 1828235783Skib intel_dp_link_down(intel_dp); 1829235783Skib intel_dp_start_link_train(intel_dp); 1830235783Skib tries = 0; 1831235783Skib cr_tries++; 1832235783Skib continue; 1833235783Skib } 1834235783Skib 1835235783Skib /* Compute new intel_dp->train_set as requested by target */ 1836235783Skib intel_get_adjust_train(intel_dp, link_status); 1837235783Skib ++tries; 1838235783Skib } 1839235783Skib 1840235783Skib if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) 1841235783Skib reg = DP | DP_LINK_TRAIN_OFF_CPT; 1842235783Skib else 1843235783Skib reg = DP | DP_LINK_TRAIN_OFF; 1844235783Skib 1845235783Skib I915_WRITE(intel_dp->output_reg, reg); 1846235783Skib POSTING_READ(intel_dp->output_reg); 1847235783Skib intel_dp_aux_native_write_1(intel_dp, 1848235783Skib DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); 1849235783Skib} 1850235783Skib 1851235783Skibstatic void 1852235783Skibintel_dp_link_down(struct intel_dp *intel_dp) 1853235783Skib{ 1854235783Skib struct drm_device *dev = intel_dp->base.base.dev; 1855235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 1856235783Skib uint32_t DP = intel_dp->DP; 1857235783Skib 1858235783Skib if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) 1859235783Skib return; 1860235783Skib 1861235783Skib DRM_DEBUG_KMS("\n"); 1862235783Skib 1863235783Skib if (is_edp(intel_dp)) { 1864235783Skib DP &= ~DP_PLL_ENABLE; 1865235783Skib I915_WRITE(intel_dp->output_reg, DP); 1866235783Skib POSTING_READ(intel_dp->output_reg); 1867235783Skib DELAY(100); 1868235783Skib } 1869235783Skib 1870235783Skib if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { 1871235783Skib DP &= ~DP_LINK_TRAIN_MASK_CPT; 1872235783Skib I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 1873235783Skib } else { 1874235783Skib DP &= ~DP_LINK_TRAIN_MASK; 1875235783Skib I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1876235783Skib } 1877235783Skib POSTING_READ(intel_dp->output_reg); 1878235783Skib 1879235783Skib drm_msleep(17, "915dlo"); 1880235783Skib 1881235783Skib if (is_edp(intel_dp)) { 1882235783Skib if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) 1883235783Skib DP |= DP_LINK_TRAIN_OFF_CPT; 1884235783Skib else 1885235783Skib DP |= DP_LINK_TRAIN_OFF; 1886235783Skib } 1887235783Skib 1888235783Skib 1889235783Skib if (!HAS_PCH_CPT(dev) && 1890235783Skib I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 1891235783Skib struct drm_crtc *crtc = intel_dp->base.base.crtc; 1892235783Skib 1893235783Skib /* Hardware workaround: leaving our transcoder select 1894235783Skib * set to transcoder B while it's off will prevent the 1895235783Skib * corresponding HDMI output on transcoder A. 1896235783Skib * 1897235783Skib * Combine this with another hardware workaround: 1898235783Skib * transcoder select bit can only be cleared while the 1899235783Skib * port is enabled. 1900235783Skib */ 1901235783Skib DP &= ~DP_PIPEB_SELECT; 1902235783Skib I915_WRITE(intel_dp->output_reg, DP); 1903235783Skib 1904235783Skib /* Changes to enable or select take place the vblank 1905235783Skib * after being written. 1906235783Skib */ 1907235783Skib if (crtc == NULL) { 1908235783Skib /* We can arrive here never having been attached 1909235783Skib * to a CRTC, for instance, due to inheriting 1910235783Skib * random state from the BIOS. 1911235783Skib * 1912235783Skib * If the pipe is not running, play safe and 1913235783Skib * wait for the clocks to stabilise before 1914235783Skib * continuing. 1915235783Skib */ 1916235783Skib POSTING_READ(intel_dp->output_reg); 1917235783Skib drm_msleep(50, "915dla"); 1918235783Skib } else 1919235783Skib intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); 1920235783Skib } 1921235783Skib 1922235783Skib DP &= ~DP_AUDIO_OUTPUT_ENABLE; 1923235783Skib I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 1924235783Skib POSTING_READ(intel_dp->output_reg); 1925235783Skib drm_msleep(intel_dp->panel_power_down_delay, "915ldo"); 1926235783Skib} 1927235783Skib 1928235783Skibstatic bool 1929235783Skibintel_dp_get_dpcd(struct intel_dp *intel_dp) 1930235783Skib{ 1931235783Skib if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, 1932235783Skib sizeof(intel_dp->dpcd)) && 1933235783Skib (intel_dp->dpcd[DP_DPCD_REV] != 0)) { 1934235783Skib return true; 1935235783Skib } 1936235783Skib 1937235783Skib return false; 1938235783Skib} 1939235783Skib 1940235783Skibstatic bool 1941235783Skibintel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 1942235783Skib{ 1943235783Skib int ret; 1944235783Skib 1945235783Skib ret = intel_dp_aux_native_read_retry(intel_dp, 1946235783Skib DP_DEVICE_SERVICE_IRQ_VECTOR, 1947235783Skib sink_irq_vector, 1); 1948235783Skib if (!ret) 1949235783Skib return false; 1950235783Skib 1951235783Skib return true; 1952235783Skib} 1953235783Skib 1954235783Skibstatic void 1955235783Skibintel_dp_handle_test_request(struct intel_dp *intel_dp) 1956235783Skib{ 1957235783Skib /* NAK by default */ 1958235783Skib intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK); 1959235783Skib} 1960235783Skib 1961235783Skib/* 1962235783Skib * According to DP spec 1963235783Skib * 5.1.2: 1964235783Skib * 1. Read DPCD 1965235783Skib * 2. Configure link according to Receiver Capabilities 1966235783Skib * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 1967235783Skib * 4. Check link status on receipt of hot-plug interrupt 1968235783Skib */ 1969235783Skib 1970235783Skibstatic void 1971235783Skibintel_dp_check_link_status(struct intel_dp *intel_dp) 1972235783Skib{ 1973235783Skib u8 sink_irq_vector; 1974235783Skib u8 link_status[DP_LINK_STATUS_SIZE]; 1975235783Skib 1976235783Skib if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON) 1977235783Skib return; 1978235783Skib 1979235783Skib if (!intel_dp->base.base.crtc) 1980235783Skib return; 1981235783Skib 1982235783Skib /* Try to read receiver status if the link appears to be up */ 1983235783Skib if (!intel_dp_get_link_status(intel_dp, link_status)) { 1984235783Skib intel_dp_link_down(intel_dp); 1985235783Skib return; 1986235783Skib } 1987235783Skib 1988235783Skib /* Now read the DPCD to see if it's actually running */ 1989235783Skib if (!intel_dp_get_dpcd(intel_dp)) { 1990235783Skib intel_dp_link_down(intel_dp); 1991235783Skib return; 1992235783Skib } 1993235783Skib 1994235783Skib /* Try to read the source of the interrupt */ 1995235783Skib if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 1996235783Skib intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 1997235783Skib /* Clear interrupt source */ 1998235783Skib intel_dp_aux_native_write_1(intel_dp, 1999235783Skib DP_DEVICE_SERVICE_IRQ_VECTOR, 2000235783Skib sink_irq_vector); 2001235783Skib 2002235783Skib if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 2003235783Skib intel_dp_handle_test_request(intel_dp); 2004235783Skib if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 2005235783Skib DRM_DEBUG_KMS("CP or sink specific irq unhandled\n"); 2006235783Skib } 2007235783Skib 2008235783Skib if (!intel_channel_eq_ok(intel_dp, link_status)) { 2009235783Skib DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 2010235783Skib drm_get_encoder_name(&intel_dp->base.base)); 2011235783Skib intel_dp_start_link_train(intel_dp); 2012235783Skib intel_dp_complete_link_train(intel_dp); 2013235783Skib } 2014235783Skib} 2015235783Skib 2016235783Skibstatic enum drm_connector_status 2017235783Skibintel_dp_detect_dpcd(struct intel_dp *intel_dp) 2018235783Skib{ 2019235783Skib if (intel_dp_get_dpcd(intel_dp)) 2020235783Skib return connector_status_connected; 2021235783Skib return connector_status_disconnected; 2022235783Skib} 2023235783Skib 2024235783Skibstatic enum drm_connector_status 2025235783Skibironlake_dp_detect(struct intel_dp *intel_dp) 2026235783Skib{ 2027235783Skib enum drm_connector_status status; 2028235783Skib 2029235783Skib /* Can't disconnect eDP, but you can close the lid... */ 2030235783Skib if (is_edp(intel_dp)) { 2031235783Skib status = intel_panel_detect(intel_dp->base.base.dev); 2032235783Skib if (status == connector_status_unknown) 2033235783Skib status = connector_status_connected; 2034235783Skib return status; 2035235783Skib } 2036235783Skib 2037235783Skib return intel_dp_detect_dpcd(intel_dp); 2038235783Skib} 2039235783Skib 2040235783Skibstatic enum drm_connector_status 2041235783Skibg4x_dp_detect(struct intel_dp *intel_dp) 2042235783Skib{ 2043235783Skib struct drm_device *dev = intel_dp->base.base.dev; 2044235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 2045235783Skib uint32_t temp, bit; 2046235783Skib 2047235783Skib switch (intel_dp->output_reg) { 2048235783Skib case DP_B: 2049235783Skib bit = DPB_HOTPLUG_INT_STATUS; 2050235783Skib break; 2051235783Skib case DP_C: 2052235783Skib bit = DPC_HOTPLUG_INT_STATUS; 2053235783Skib break; 2054235783Skib case DP_D: 2055235783Skib bit = DPD_HOTPLUG_INT_STATUS; 2056235783Skib break; 2057235783Skib default: 2058235783Skib return connector_status_unknown; 2059235783Skib } 2060235783Skib 2061235783Skib temp = I915_READ(PORT_HOTPLUG_STAT); 2062235783Skib 2063235783Skib if ((temp & bit) == 0) 2064235783Skib return connector_status_disconnected; 2065235783Skib 2066235783Skib return intel_dp_detect_dpcd(intel_dp); 2067235783Skib} 2068235783Skib 2069235783Skibstatic struct edid * 2070235783Skibintel_dp_get_edid(struct drm_connector *connector, device_t adapter) 2071235783Skib{ 2072235783Skib struct intel_dp *intel_dp = intel_attached_dp(connector); 2073235783Skib struct edid *edid; 2074235783Skib 2075235783Skib ironlake_edp_panel_vdd_on(intel_dp); 2076235783Skib edid = drm_get_edid(connector, adapter); 2077235783Skib ironlake_edp_panel_vdd_off(intel_dp, false); 2078235783Skib return edid; 2079235783Skib} 2080235783Skib 2081235783Skibstatic int 2082235783Skibintel_dp_get_edid_modes(struct drm_connector *connector, device_t adapter) 2083235783Skib{ 2084235783Skib struct intel_dp *intel_dp = intel_attached_dp(connector); 2085235783Skib int ret; 2086235783Skib 2087235783Skib ironlake_edp_panel_vdd_on(intel_dp); 2088235783Skib ret = intel_ddc_get_modes(connector, adapter); 2089235783Skib ironlake_edp_panel_vdd_off(intel_dp, false); 2090235783Skib return ret; 2091235783Skib} 2092235783Skib 2093235783Skib 2094235783Skib/** 2095235783Skib * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. 2096235783Skib * 2097235783Skib * \return true if DP port is connected. 2098235783Skib * \return false if DP port is disconnected. 2099235783Skib */ 2100235783Skibstatic enum drm_connector_status 2101235783Skibintel_dp_detect(struct drm_connector *connector, bool force) 2102235783Skib{ 2103235783Skib struct intel_dp *intel_dp = intel_attached_dp(connector); 2104235783Skib struct drm_device *dev = intel_dp->base.base.dev; 2105235783Skib enum drm_connector_status status; 2106235783Skib struct edid *edid = NULL; 2107235783Skib 2108235783Skib intel_dp->has_audio = false; 2109235783Skib 2110235783Skib if (HAS_PCH_SPLIT(dev)) 2111235783Skib status = ironlake_dp_detect(intel_dp); 2112235783Skib else 2113235783Skib status = g4x_dp_detect(intel_dp); 2114235783Skib if (status != connector_status_connected) 2115235783Skib return status; 2116235783Skib 2117235783Skib if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 2118235783Skib intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 2119235783Skib } else { 2120235783Skib edid = intel_dp_get_edid(connector, intel_dp->adapter); 2121235783Skib if (edid) { 2122235783Skib intel_dp->has_audio = drm_detect_monitor_audio(edid); 2123235783Skib connector->display_info.raw_edid = NULL; 2124235783Skib free(edid, DRM_MEM_KMS); 2125235783Skib } 2126235783Skib } 2127235783Skib 2128235783Skib return connector_status_connected; 2129235783Skib} 2130235783Skib 2131235783Skibstatic int intel_dp_get_modes(struct drm_connector *connector) 2132235783Skib{ 2133235783Skib struct intel_dp *intel_dp = intel_attached_dp(connector); 2134235783Skib struct drm_device *dev = intel_dp->base.base.dev; 2135235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 2136235783Skib int ret; 2137235783Skib 2138235783Skib /* We should parse the EDID data and find out if it has an audio sink 2139235783Skib */ 2140235783Skib 2141235783Skib ret = intel_dp_get_edid_modes(connector, intel_dp->adapter); 2142235783Skib if (ret) { 2143235783Skib if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) { 2144235783Skib struct drm_display_mode *newmode; 2145235783Skib list_for_each_entry(newmode, &connector->probed_modes, 2146235783Skib head) { 2147235783Skib if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) { 2148235783Skib intel_dp->panel_fixed_mode = 2149235783Skib drm_mode_duplicate(dev, newmode); 2150235783Skib break; 2151235783Skib } 2152235783Skib } 2153235783Skib } 2154235783Skib return ret; 2155235783Skib } 2156235783Skib 2157235783Skib /* if eDP has no EDID, try to use fixed panel mode from VBT */ 2158235783Skib if (is_edp(intel_dp)) { 2159235783Skib /* initialize panel mode from VBT if available for eDP */ 2160235783Skib if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) { 2161235783Skib intel_dp->panel_fixed_mode = 2162235783Skib drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); 2163235783Skib if (intel_dp->panel_fixed_mode) { 2164235783Skib intel_dp->panel_fixed_mode->type |= 2165235783Skib DRM_MODE_TYPE_PREFERRED; 2166235783Skib } 2167235783Skib } 2168235783Skib if (intel_dp->panel_fixed_mode) { 2169235783Skib struct drm_display_mode *mode; 2170235783Skib mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode); 2171235783Skib drm_mode_probed_add(connector, mode); 2172235783Skib return 1; 2173235783Skib } 2174235783Skib } 2175235783Skib return 0; 2176235783Skib} 2177235783Skib 2178235783Skibstatic bool 2179235783Skibintel_dp_detect_audio(struct drm_connector *connector) 2180235783Skib{ 2181235783Skib struct intel_dp *intel_dp = intel_attached_dp(connector); 2182235783Skib struct edid *edid; 2183235783Skib bool has_audio = false; 2184235783Skib 2185235783Skib edid = intel_dp_get_edid(connector, intel_dp->adapter); 2186235783Skib if (edid) { 2187235783Skib has_audio = drm_detect_monitor_audio(edid); 2188235783Skib 2189235783Skib connector->display_info.raw_edid = NULL; 2190235783Skib free(edid, DRM_MEM_KMS); 2191235783Skib } 2192235783Skib 2193235783Skib return has_audio; 2194235783Skib} 2195235783Skib 2196235783Skibstatic int 2197235783Skibintel_dp_set_property(struct drm_connector *connector, 2198235783Skib struct drm_property *property, 2199235783Skib uint64_t val) 2200235783Skib{ 2201235783Skib struct drm_i915_private *dev_priv = connector->dev->dev_private; 2202235783Skib struct intel_dp *intel_dp = intel_attached_dp(connector); 2203235783Skib int ret; 2204235783Skib 2205235783Skib ret = drm_connector_property_set_value(connector, property, val); 2206235783Skib if (ret) 2207235783Skib return ret; 2208235783Skib 2209235783Skib if (property == dev_priv->force_audio_property) { 2210235783Skib int i = val; 2211235783Skib bool has_audio; 2212235783Skib 2213235783Skib if (i == intel_dp->force_audio) 2214235783Skib return 0; 2215235783Skib 2216235783Skib intel_dp->force_audio = i; 2217235783Skib 2218235783Skib if (i == HDMI_AUDIO_AUTO) 2219235783Skib has_audio = intel_dp_detect_audio(connector); 2220235783Skib else 2221235783Skib has_audio = (i == HDMI_AUDIO_ON); 2222235783Skib 2223235783Skib if (has_audio == intel_dp->has_audio) 2224235783Skib return 0; 2225235783Skib 2226235783Skib intel_dp->has_audio = has_audio; 2227235783Skib goto done; 2228235783Skib } 2229235783Skib 2230235783Skib if (property == dev_priv->broadcast_rgb_property) { 2231235783Skib if (val == !!intel_dp->color_range) 2232235783Skib return 0; 2233235783Skib 2234235783Skib intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; 2235235783Skib goto done; 2236235783Skib } 2237235783Skib 2238235783Skib return -EINVAL; 2239235783Skib 2240235783Skibdone: 2241235783Skib if (intel_dp->base.base.crtc) { 2242235783Skib struct drm_crtc *crtc = intel_dp->base.base.crtc; 2243235783Skib drm_crtc_helper_set_mode(crtc, &crtc->mode, 2244235783Skib crtc->x, crtc->y, 2245235783Skib crtc->fb); 2246235783Skib } 2247235783Skib 2248235783Skib return 0; 2249235783Skib} 2250235783Skib 2251235783Skibstatic void 2252235783Skibintel_dp_destroy(struct drm_connector *connector) 2253235783Skib{ 2254235783Skib struct drm_device *dev = connector->dev; 2255235783Skib 2256235783Skib if (intel_dpd_is_edp(dev)) 2257235783Skib intel_panel_destroy_backlight(dev); 2258235783Skib 2259235783Skib#if 0 2260235783Skib drm_sysfs_connector_remove(connector); 2261235783Skib#endif 2262235783Skib drm_connector_cleanup(connector); 2263235783Skib free(connector, DRM_MEM_KMS); 2264235783Skib} 2265235783Skib 2266235783Skibstatic void intel_dp_encoder_destroy(struct drm_encoder *encoder) 2267235783Skib{ 2268235783Skib struct drm_device *dev; 2269235783Skib struct intel_dp *intel_dp; 2270235783Skib 2271235783Skib intel_dp = enc_to_intel_dp(encoder); 2272235783Skib dev = encoder->dev; 2273235783Skib 2274235783Skib if (intel_dp->dp_iic_bus != NULL) { 2275235783Skib if (intel_dp->adapter != NULL) { 2276235783Skib device_delete_child(intel_dp->dp_iic_bus, 2277235783Skib intel_dp->adapter); 2278235783Skib } 2279235783Skib device_delete_child(dev->device, intel_dp->dp_iic_bus); 2280235783Skib } 2281235783Skib drm_encoder_cleanup(encoder); 2282235783Skib if (is_edp(intel_dp)) { 2283235783Skib struct drm_i915_private *dev_priv = intel_dp->base.base.dev->dev_private; 2284235783Skib 2285235783Skib taskqueue_cancel_timeout(dev_priv->tq, 2286235783Skib &intel_dp->panel_vdd_task, NULL); 2287235783Skib taskqueue_drain_timeout(dev_priv->tq, 2288235783Skib &intel_dp->panel_vdd_task); 2289235783Skib ironlake_panel_vdd_off_sync(intel_dp); 2290235783Skib } 2291235783Skib free(intel_dp, DRM_MEM_KMS); 2292235783Skib} 2293235783Skib 2294235783Skibstatic const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 2295235783Skib .dpms = intel_dp_dpms, 2296235783Skib .mode_fixup = intel_dp_mode_fixup, 2297235783Skib .prepare = intel_dp_prepare, 2298235783Skib .mode_set = intel_dp_mode_set, 2299235783Skib .commit = intel_dp_commit, 2300235783Skib}; 2301235783Skib 2302235783Skibstatic const struct drm_connector_funcs intel_dp_connector_funcs = { 2303235783Skib .dpms = drm_helper_connector_dpms, 2304235783Skib .detect = intel_dp_detect, 2305235783Skib .fill_modes = drm_helper_probe_single_connector_modes, 2306235783Skib .set_property = intel_dp_set_property, 2307235783Skib .destroy = intel_dp_destroy, 2308235783Skib}; 2309235783Skib 2310235783Skibstatic const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 2311235783Skib .get_modes = intel_dp_get_modes, 2312235783Skib .mode_valid = intel_dp_mode_valid, 2313235783Skib .best_encoder = intel_best_encoder, 2314235783Skib}; 2315235783Skib 2316235783Skibstatic const struct drm_encoder_funcs intel_dp_enc_funcs = { 2317235783Skib .destroy = intel_dp_encoder_destroy, 2318235783Skib}; 2319235783Skib 2320235783Skibstatic void 2321235783Skibintel_dp_hot_plug(struct intel_encoder *intel_encoder) 2322235783Skib{ 2323235783Skib struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 2324235783Skib 2325235783Skib intel_dp_check_link_status(intel_dp); 2326235783Skib} 2327235783Skib 2328235783Skib/* Return which DP Port should be selected for Transcoder DP control */ 2329235783Skibint 2330235783Skibintel_trans_dp_port_sel(struct drm_crtc *crtc) 2331235783Skib{ 2332235783Skib struct drm_device *dev = crtc->dev; 2333235783Skib struct drm_mode_config *mode_config = &dev->mode_config; 2334235783Skib struct drm_encoder *encoder; 2335235783Skib 2336235783Skib list_for_each_entry(encoder, &mode_config->encoder_list, head) { 2337235783Skib struct intel_dp *intel_dp; 2338235783Skib 2339235783Skib if (encoder->crtc != crtc) 2340235783Skib continue; 2341235783Skib 2342235783Skib intel_dp = enc_to_intel_dp(encoder); 2343235783Skib if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || 2344235783Skib intel_dp->base.type == INTEL_OUTPUT_EDP) 2345235783Skib return intel_dp->output_reg; 2346235783Skib } 2347235783Skib 2348235783Skib return -1; 2349235783Skib} 2350235783Skib 2351235783Skib/* check the VBT to see whether the eDP is on DP-D port */ 2352235783Skibbool intel_dpd_is_edp(struct drm_device *dev) 2353235783Skib{ 2354235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 2355235783Skib struct child_device_config *p_child; 2356235783Skib int i; 2357235783Skib 2358235783Skib if (!dev_priv->child_dev_num) 2359235783Skib return false; 2360235783Skib 2361235783Skib for (i = 0; i < dev_priv->child_dev_num; i++) { 2362235783Skib p_child = dev_priv->child_dev + i; 2363235783Skib 2364235783Skib if (p_child->dvo_port == PORT_IDPD && 2365235783Skib p_child->device_type == DEVICE_TYPE_eDP) 2366235783Skib return true; 2367235783Skib } 2368235783Skib return false; 2369235783Skib} 2370235783Skib 2371235783Skibstatic void 2372235783Skibintel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 2373235783Skib{ 2374235783Skib intel_attach_force_audio_property(connector); 2375235783Skib intel_attach_broadcast_rgb_property(connector); 2376235783Skib} 2377235783Skib 2378235783Skibvoid 2379235783Skibintel_dp_init(struct drm_device *dev, int output_reg) 2380235783Skib{ 2381235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 2382235783Skib struct drm_connector *connector; 2383235783Skib struct intel_dp *intel_dp; 2384235783Skib struct intel_encoder *intel_encoder; 2385235783Skib struct intel_connector *intel_connector; 2386235783Skib const char *name = NULL; 2387235783Skib int type; 2388235783Skib 2389235783Skib intel_dp = malloc(sizeof(struct intel_dp), DRM_MEM_KMS, 2390235783Skib M_WAITOK | M_ZERO); 2391235783Skib 2392235783Skib intel_dp->output_reg = output_reg; 2393235783Skib intel_dp->dpms_mode = -1; 2394235783Skib 2395235783Skib intel_connector = malloc(sizeof(struct intel_connector), DRM_MEM_KMS, 2396235783Skib M_WAITOK | M_ZERO); 2397235783Skib intel_encoder = &intel_dp->base; 2398235783Skib 2399235783Skib if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) 2400235783Skib if (intel_dpd_is_edp(dev)) 2401235783Skib intel_dp->is_pch_edp = true; 2402235783Skib 2403235783Skib if (output_reg == DP_A || is_pch_edp(intel_dp)) { 2404235783Skib type = DRM_MODE_CONNECTOR_eDP; 2405235783Skib intel_encoder->type = INTEL_OUTPUT_EDP; 2406235783Skib } else { 2407235783Skib type = DRM_MODE_CONNECTOR_DisplayPort; 2408235783Skib intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 2409235783Skib } 2410235783Skib 2411235783Skib connector = &intel_connector->base; 2412235783Skib drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 2413235783Skib drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 2414235783Skib 2415235783Skib connector->polled = DRM_CONNECTOR_POLL_HPD; 2416235783Skib 2417235783Skib if (output_reg == DP_B || output_reg == PCH_DP_B) 2418235783Skib intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); 2419235783Skib else if (output_reg == DP_C || output_reg == PCH_DP_C) 2420235783Skib intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); 2421235783Skib else if (output_reg == DP_D || output_reg == PCH_DP_D) 2422235783Skib intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); 2423235783Skib 2424235783Skib if (is_edp(intel_dp)) { 2425235783Skib intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); 2426235783Skib TIMEOUT_TASK_INIT(dev_priv->tq, &intel_dp->panel_vdd_task, 0, 2427235783Skib ironlake_panel_vdd_work, intel_dp); 2428235783Skib } 2429235783Skib 2430235783Skib intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2431235783Skib connector->interlace_allowed = true; 2432235783Skib connector->doublescan_allowed = 0; 2433235783Skib 2434235783Skib drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 2435235783Skib DRM_MODE_ENCODER_TMDS); 2436235783Skib drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); 2437235783Skib 2438235783Skib intel_connector_attach_encoder(intel_connector, intel_encoder); 2439235783Skib#if 0 2440235783Skib drm_sysfs_connector_add(connector); 2441235783Skib#endif 2442235783Skib 2443235783Skib /* Set up the DDC bus. */ 2444235783Skib switch (output_reg) { 2445235783Skib case DP_A: 2446235783Skib name = "DPDDC-A"; 2447235783Skib break; 2448235783Skib case DP_B: 2449235783Skib case PCH_DP_B: 2450235783Skib dev_priv->hotplug_supported_mask |= 2451235783Skib HDMIB_HOTPLUG_INT_STATUS; 2452235783Skib name = "DPDDC-B"; 2453235783Skib break; 2454235783Skib case DP_C: 2455235783Skib case PCH_DP_C: 2456235783Skib dev_priv->hotplug_supported_mask |= 2457235783Skib HDMIC_HOTPLUG_INT_STATUS; 2458235783Skib name = "DPDDC-C"; 2459235783Skib break; 2460235783Skib case DP_D: 2461235783Skib case PCH_DP_D: 2462235783Skib dev_priv->hotplug_supported_mask |= 2463235783Skib HDMID_HOTPLUG_INT_STATUS; 2464235783Skib name = "DPDDC-D"; 2465235783Skib break; 2466235783Skib } 2467235783Skib 2468235783Skib /* Cache some DPCD data in the eDP case */ 2469235783Skib if (is_edp(intel_dp)) { 2470235783Skib bool ret; 2471235783Skib struct edp_power_seq cur, vbt; 2472235783Skib u32 pp_on, pp_off, pp_div; 2473235783Skib 2474235783Skib pp_on = I915_READ(PCH_PP_ON_DELAYS); 2475235783Skib pp_off = I915_READ(PCH_PP_OFF_DELAYS); 2476235783Skib pp_div = I915_READ(PCH_PP_DIVISOR); 2477235783Skib 2478235783Skib /* Pull timing values out of registers */ 2479235783Skib cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 2480235783Skib PANEL_POWER_UP_DELAY_SHIFT; 2481235783Skib 2482235783Skib cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 2483235783Skib PANEL_LIGHT_ON_DELAY_SHIFT; 2484235783Skib 2485235783Skib cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 2486235783Skib PANEL_LIGHT_OFF_DELAY_SHIFT; 2487235783Skib 2488235783Skib cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 2489235783Skib PANEL_POWER_DOWN_DELAY_SHIFT; 2490235783Skib 2491235783Skib cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 2492235783Skib PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 2493235783Skib 2494235783Skib DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 2495235783Skib cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 2496235783Skib 2497235783Skib vbt = dev_priv->edp.pps; 2498235783Skib 2499235783Skib DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 2500235783Skib vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 2501235783Skib 2502235783Skib#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10) 2503235783Skib 2504235783Skib intel_dp->panel_power_up_delay = get_delay(t1_t3); 2505235783Skib intel_dp->backlight_on_delay = get_delay(t8); 2506235783Skib intel_dp->backlight_off_delay = get_delay(t9); 2507235783Skib intel_dp->panel_power_down_delay = get_delay(t10); 2508235783Skib intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 2509235783Skib 2510235783Skib DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 2511235783Skib intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 2512235783Skib intel_dp->panel_power_cycle_delay); 2513235783Skib 2514235783Skib DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 2515235783Skib intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 2516235783Skib 2517235783Skib ironlake_edp_panel_vdd_on(intel_dp); 2518235783Skib ret = intel_dp_get_dpcd(intel_dp); 2519235783Skib ironlake_edp_panel_vdd_off(intel_dp, false); 2520235783Skib 2521235783Skib if (ret) { 2522235783Skib if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 2523235783Skib dev_priv->no_aux_handshake = 2524235783Skib intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 2525235783Skib DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 2526235783Skib } else { 2527235783Skib /* if this fails, presume the device is a ghost */ 2528235783Skib DRM_INFO("failed to retrieve link info, disabling eDP\n"); 2529235783Skib intel_dp_encoder_destroy(&intel_dp->base.base); 2530235783Skib intel_dp_destroy(&intel_connector->base); 2531235783Skib return; 2532235783Skib } 2533235783Skib } 2534235783Skib 2535235783Skib intel_dp_i2c_init(intel_dp, intel_connector, name); 2536235783Skib 2537235783Skib intel_encoder->hot_plug = intel_dp_hot_plug; 2538235783Skib 2539235783Skib if (is_edp(intel_dp)) { 2540235783Skib dev_priv->int_edp_connector = connector; 2541235783Skib intel_panel_setup_backlight(dev); 2542235783Skib } 2543235783Skib 2544235783Skib intel_dp_add_properties(intel_dp, connector); 2545235783Skib 2546235783Skib /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2547235783Skib * 0xd. Failure to do so will result in spurious interrupts being 2548235783Skib * generated on the port when a cable is not attached. 2549235783Skib */ 2550235783Skib if (IS_G4X(dev) && !IS_GM45(dev)) { 2551235783Skib u32 temp = I915_READ(PEG_BAND_GAP_DATA); 2552235783Skib I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 2553235783Skib } 2554235783Skib} 2555