1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD$"); 30 31#include <dev/drm2/drmP.h> 32#include <dev/drm2/drm.h> 33#include <dev/drm2/drm_crtc.h> 34#include <dev/drm2/drm_crtc_helper.h> 35#include <dev/drm2/i915/i915_drm.h> 36#include <dev/drm2/i915/i915_drv.h> 37#include <dev/drm2/i915/intel_drv.h> 38#include <dev/drm2/drm_dp_helper.h> 39 40#define DP_RECEIVER_CAP_SIZE 0xf 41#define DP_LINK_STATUS_SIZE 6 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 43 44#define DP_LINK_CONFIGURATION_SIZE 9 45 46struct intel_dp { 47 struct intel_encoder base; 48 uint32_t output_reg; 49 uint32_t DP; 50 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 51 bool has_audio; 52 enum hdmi_force_audio force_audio; 53 uint32_t color_range; 54 int dpms_mode; 55 uint8_t link_bw; 56 uint8_t lane_count; 57 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; 58 device_t dp_iic_bus; 59 device_t adapter; 60 bool is_pch_edp; 61 uint8_t train_set[4]; 62 int panel_power_up_delay; 63 int panel_power_down_delay; 64 int panel_power_cycle_delay; 65 int backlight_on_delay; 66 int backlight_off_delay; 67 struct drm_display_mode *panel_fixed_mode; /* for eDP */ 68 struct timeout_task panel_vdd_task; 69 bool want_panel_vdd; 70}; 71 72/** 73 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 74 * @intel_dp: DP struct 75 * 76 * If a CPU or PCH DP output is attached to an eDP panel, this function 77 * will return true, and false otherwise. 78 */ 79static bool is_edp(struct intel_dp *intel_dp) 80{ 81 return intel_dp->base.type == INTEL_OUTPUT_EDP; 82} 83 84/** 85 * is_pch_edp - is the port on the PCH and attached to an eDP panel? 86 * @intel_dp: DP struct 87 * 88 * Returns true if the given DP struct corresponds to a PCH DP port attached 89 * to an eDP panel, false otherwise. Helpful for determining whether we 90 * may need FDI resources for a given DP output or not. 91 */ 92static bool is_pch_edp(struct intel_dp *intel_dp) 93{ 94 return intel_dp->is_pch_edp; 95} 96 97/** 98 * is_cpu_edp - is the port on the CPU and attached to an eDP panel? 99 * @intel_dp: DP struct 100 * 101 * Returns true if the given DP struct corresponds to a CPU eDP port. 102 */ 103static bool is_cpu_edp(struct intel_dp *intel_dp) 104{ 105 return is_edp(intel_dp) && !is_pch_edp(intel_dp); 106} 107 108static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 109{ 110 return container_of(encoder, struct intel_dp, base.base); 111} 112 113static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 114{ 115 return container_of(intel_attached_encoder(connector), 116 struct intel_dp, base); 117} 118 119/** 120 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? 121 * @encoder: DRM encoder 122 * 123 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed 124 * by intel_display.c. 125 */ 126bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) 127{ 128 struct intel_dp *intel_dp; 129 130 if (!encoder) 131 return false; 132 133 intel_dp = enc_to_intel_dp(encoder); 134 135 return is_pch_edp(intel_dp); 136} 137 138static void intel_dp_start_link_train(struct intel_dp *intel_dp); 139static void intel_dp_complete_link_train(struct intel_dp *intel_dp); 140static void intel_dp_link_down(struct intel_dp *intel_dp); 141 142void 143intel_edp_link_config(struct intel_encoder *intel_encoder, 144 int *lane_num, int *link_bw) 145{ 146 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 147 148 *lane_num = intel_dp->lane_count; 149 if (intel_dp->link_bw == DP_LINK_BW_1_62) 150 *link_bw = 162000; 151 else if (intel_dp->link_bw == DP_LINK_BW_2_7) 152 *link_bw = 270000; 153} 154 155static int 156intel_dp_max_lane_count(struct intel_dp *intel_dp) 157{ 158 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; 159 switch (max_lane_count) { 160 case 1: case 2: case 4: 161 break; 162 default: 163 max_lane_count = 4; 164 } 165 return max_lane_count; 166} 167 168static int 169intel_dp_max_link_bw(struct intel_dp *intel_dp) 170{ 171 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 172 173 switch (max_link_bw) { 174 case DP_LINK_BW_1_62: 175 case DP_LINK_BW_2_7: 176 break; 177 default: 178 max_link_bw = DP_LINK_BW_1_62; 179 break; 180 } 181 return max_link_bw; 182} 183 184static int 185intel_dp_link_clock(uint8_t link_bw) 186{ 187 if (link_bw == DP_LINK_BW_2_7) 188 return 270000; 189 else 190 return 162000; 191} 192 193/* 194 * The units on the numbers in the next two are... bizarre. Examples will 195 * make it clearer; this one parallels an example in the eDP spec. 196 * 197 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 198 * 199 * 270000 * 1 * 8 / 10 == 216000 200 * 201 * The actual data capacity of that configuration is 2.16Gbit/s, so the 202 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 203 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 204 * 119000. At 18bpp that's 2142000 kilobits per second. 205 * 206 * Thus the strange-looking division by 10 in intel_dp_link_required, to 207 * get the result in decakilobits instead of kilobits. 208 */ 209 210static int 211intel_dp_link_required(int pixel_clock, int bpp) 212{ 213 return (pixel_clock * bpp + 9) / 10; 214} 215 216static int 217intel_dp_max_data_rate(int max_link_clock, int max_lanes) 218{ 219 return (max_link_clock * max_lanes * 8) / 10; 220} 221 222static bool 223intel_dp_adjust_dithering(struct intel_dp *intel_dp, 224 const struct drm_display_mode *mode, 225 struct drm_display_mode *adjusted_mode) 226{ 227 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); 228 int max_lanes = intel_dp_max_lane_count(intel_dp); 229 int max_rate, mode_rate; 230 231 mode_rate = intel_dp_link_required(mode->clock, 24); 232 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 233 234 if (mode_rate > max_rate) { 235 mode_rate = intel_dp_link_required(mode->clock, 18); 236 if (mode_rate > max_rate) 237 return false; 238 239 if (adjusted_mode) 240 adjusted_mode->private_flags 241 |= INTEL_MODE_DP_FORCE_6BPC; 242 243 return true; 244 } 245 246 return true; 247} 248 249static int 250intel_dp_mode_valid(struct drm_connector *connector, 251 struct drm_display_mode *mode) 252{ 253 struct intel_dp *intel_dp = intel_attached_dp(connector); 254 255 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { 256 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay) 257 return MODE_PANEL; 258 259 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay) 260 return MODE_PANEL; 261 } 262 263 if (!intel_dp_adjust_dithering(intel_dp, mode, NULL)) 264 return MODE_CLOCK_HIGH; 265 266 if (mode->clock < 10000) 267 return MODE_CLOCK_LOW; 268 269 return MODE_OK; 270} 271 272static uint32_t 273pack_aux(uint8_t *src, int src_bytes) 274{ 275 int i; 276 uint32_t v = 0; 277 278 if (src_bytes > 4) 279 src_bytes = 4; 280 for (i = 0; i < src_bytes; i++) 281 v |= ((uint32_t) src[i]) << ((3-i) * 8); 282 return v; 283} 284 285static void 286unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 287{ 288 int i; 289 if (dst_bytes > 4) 290 dst_bytes = 4; 291 for (i = 0; i < dst_bytes; i++) 292 dst[i] = src >> ((3-i) * 8); 293} 294 295/* hrawclock is 1/4 the FSB frequency */ 296static int 297intel_hrawclk(struct drm_device *dev) 298{ 299 struct drm_i915_private *dev_priv = dev->dev_private; 300 uint32_t clkcfg; 301 302 clkcfg = I915_READ(CLKCFG); 303 switch (clkcfg & CLKCFG_FSB_MASK) { 304 case CLKCFG_FSB_400: 305 return 100; 306 case CLKCFG_FSB_533: 307 return 133; 308 case CLKCFG_FSB_667: 309 return 166; 310 case CLKCFG_FSB_800: 311 return 200; 312 case CLKCFG_FSB_1067: 313 return 266; 314 case CLKCFG_FSB_1333: 315 return 333; 316 /* these two are just a guess; one of them might be right */ 317 case CLKCFG_FSB_1600: 318 case CLKCFG_FSB_1600_ALT: 319 return 400; 320 default: 321 return 133; 322 } 323} 324 325static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) 326{ 327 struct drm_device *dev = intel_dp->base.base.dev; 328 struct drm_i915_private *dev_priv = dev->dev_private; 329 330 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; 331} 332 333static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) 334{ 335 struct drm_device *dev = intel_dp->base.base.dev; 336 struct drm_i915_private *dev_priv = dev->dev_private; 337 338 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; 339} 340 341static void 342intel_dp_check_edp(struct intel_dp *intel_dp) 343{ 344 struct drm_device *dev = intel_dp->base.base.dev; 345 struct drm_i915_private *dev_priv = dev->dev_private; 346 347 if (!is_edp(intel_dp)) 348 return; 349 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { 350 printf("eDP powered off while attempting aux channel communication.\n"); 351 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 352 I915_READ(PCH_PP_STATUS), 353 I915_READ(PCH_PP_CONTROL)); 354 } 355} 356 357static int 358intel_dp_aux_ch(struct intel_dp *intel_dp, 359 uint8_t *send, int send_bytes, 360 uint8_t *recv, int recv_size) 361{ 362 uint32_t output_reg = intel_dp->output_reg; 363 struct drm_device *dev = intel_dp->base.base.dev; 364 struct drm_i915_private *dev_priv = dev->dev_private; 365 uint32_t ch_ctl = output_reg + 0x10; 366 uint32_t ch_data = ch_ctl + 4; 367 int i; 368 int recv_bytes; 369 uint32_t status; 370 uint32_t aux_clock_divider; 371 int try, precharge = 5; 372 373 intel_dp_check_edp(intel_dp); 374 /* The clock divider is based off the hrawclk, 375 * and would like to run at 2MHz. So, take the 376 * hrawclk value and divide by 2 and use that 377 * 378 * Note that PCH attached eDP panels should use a 125MHz input 379 * clock divider. 380 */ 381 if (is_cpu_edp(intel_dp)) { 382 if (IS_GEN6(dev) || IS_GEN7(dev)) 383 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ 384 else 385 aux_clock_divider = 225; /* eDP input clock at 450Mhz */ 386 } else if (HAS_PCH_SPLIT(dev)) 387 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */ 388 else 389 aux_clock_divider = intel_hrawclk(dev) / 2; 390 391 /* Try to wait for any previous AUX channel activity */ 392 for (try = 0; try < 3; try++) { 393 status = I915_READ(ch_ctl); 394 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 395 break; 396 drm_msleep(1, "915ach"); 397 } 398 399 if (try == 3) { 400 printf("dp_aux_ch not started status 0x%08x\n", 401 I915_READ(ch_ctl)); 402 return -EBUSY; 403 } 404 405 /* Must try at least 3 times according to DP spec */ 406 for (try = 0; try < 5; try++) { 407 /* Load the send data into the aux channel data registers */ 408 for (i = 0; i < send_bytes; i += 4) 409 I915_WRITE(ch_data + i, 410 pack_aux(send + i, send_bytes - i)); 411 412 /* Send the command and wait for it to complete */ 413 I915_WRITE(ch_ctl, 414 DP_AUX_CH_CTL_SEND_BUSY | 415 DP_AUX_CH_CTL_TIME_OUT_400us | 416 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 417 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 418 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | 419 DP_AUX_CH_CTL_DONE | 420 DP_AUX_CH_CTL_TIME_OUT_ERROR | 421 DP_AUX_CH_CTL_RECEIVE_ERROR); 422 for (;;) { 423 status = I915_READ(ch_ctl); 424 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 425 break; 426 DELAY(100); 427 } 428 429 /* Clear done status and any errors */ 430 I915_WRITE(ch_ctl, 431 status | 432 DP_AUX_CH_CTL_DONE | 433 DP_AUX_CH_CTL_TIME_OUT_ERROR | 434 DP_AUX_CH_CTL_RECEIVE_ERROR); 435 436 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 437 DP_AUX_CH_CTL_RECEIVE_ERROR)) 438 continue; 439 if (status & DP_AUX_CH_CTL_DONE) 440 break; 441 } 442 443 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 444 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 445 return -EBUSY; 446 } 447 448 /* Check for timeout or receive error. 449 * Timeouts occur when the sink is not connected 450 */ 451 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 452 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 453 return -EIO; 454 } 455 456 /* Timeouts occur when the device isn't connected, so they're 457 * "normal" -- don't fill the kernel log with these */ 458 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 459 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 460 return -ETIMEDOUT; 461 } 462 463 /* Unload any bytes sent back from the other side */ 464 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 465 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 466 if (recv_bytes > recv_size) 467 recv_bytes = recv_size; 468 469 for (i = 0; i < recv_bytes; i += 4) 470 unpack_aux(I915_READ(ch_data + i), 471 recv + i, recv_bytes - i); 472 473 return recv_bytes; 474} 475 476/* Write data to the aux channel in native mode */ 477static int 478intel_dp_aux_native_write(struct intel_dp *intel_dp, 479 uint16_t address, uint8_t *send, int send_bytes) 480{ 481 int ret; 482 uint8_t msg[20]; 483 int msg_bytes; 484 uint8_t ack; 485 486 intel_dp_check_edp(intel_dp); 487 if (send_bytes > 16) 488 return -1; 489 msg[0] = AUX_NATIVE_WRITE << 4; 490 msg[1] = address >> 8; 491 msg[2] = address & 0xff; 492 msg[3] = send_bytes - 1; 493 memcpy(&msg[4], send, send_bytes); 494 msg_bytes = send_bytes + 4; 495 for (;;) { 496 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 497 if (ret < 0) 498 return ret; 499 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 500 break; 501 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 502 DELAY(100); 503 else 504 return -EIO; 505 } 506 return send_bytes; 507} 508 509/* Write a single byte to the aux channel in native mode */ 510static int 511intel_dp_aux_native_write_1(struct intel_dp *intel_dp, 512 uint16_t address, uint8_t byte) 513{ 514 return intel_dp_aux_native_write(intel_dp, address, &byte, 1); 515} 516 517/* read bytes from a native aux channel */ 518static int 519intel_dp_aux_native_read(struct intel_dp *intel_dp, 520 uint16_t address, uint8_t *recv, int recv_bytes) 521{ 522 uint8_t msg[4]; 523 int msg_bytes; 524 uint8_t reply[20]; 525 int reply_bytes; 526 uint8_t ack; 527 int ret; 528 529 intel_dp_check_edp(intel_dp); 530 msg[0] = AUX_NATIVE_READ << 4; 531 msg[1] = address >> 8; 532 msg[2] = address & 0xff; 533 msg[3] = recv_bytes - 1; 534 535 msg_bytes = 4; 536 reply_bytes = recv_bytes + 1; 537 538 for (;;) { 539 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 540 reply, reply_bytes); 541 if (ret == 0) 542 return -EPROTO; 543 if (ret < 0) 544 return ret; 545 ack = reply[0]; 546 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { 547 memcpy(recv, reply + 1, ret - 1); 548 return ret - 1; 549 } 550 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 551 DELAY(100); 552 else 553 return -EIO; 554 } 555} 556 557static int 558intel_dp_i2c_aux_ch(device_t idev, int mode, uint8_t write_byte, 559 uint8_t *read_byte) 560{ 561 struct iic_dp_aux_data *data; 562 struct intel_dp *intel_dp; 563 uint16_t address; 564 uint8_t msg[5]; 565 uint8_t reply[2]; 566 unsigned retry; 567 int msg_bytes; 568 int reply_bytes; 569 int ret; 570 571 data = device_get_softc(idev); 572 intel_dp = data->priv; 573 address = data->address; 574 575 intel_dp_check_edp(intel_dp); 576 /* Set up the command byte */ 577 if (mode & MODE_I2C_READ) 578 msg[0] = AUX_I2C_READ << 4; 579 else 580 msg[0] = AUX_I2C_WRITE << 4; 581 582 if (!(mode & MODE_I2C_STOP)) 583 msg[0] |= AUX_I2C_MOT << 4; 584 585 msg[1] = address >> 8; 586 msg[2] = address; 587 588 switch (mode) { 589 case MODE_I2C_WRITE: 590 msg[3] = 0; 591 msg[4] = write_byte; 592 msg_bytes = 5; 593 reply_bytes = 1; 594 break; 595 case MODE_I2C_READ: 596 msg[3] = 0; 597 msg_bytes = 4; 598 reply_bytes = 2; 599 break; 600 default: 601 msg_bytes = 3; 602 reply_bytes = 1; 603 break; 604 } 605 606 for (retry = 0; retry < 5; retry++) { 607 ret = intel_dp_aux_ch(intel_dp, 608 msg, msg_bytes, 609 reply, reply_bytes); 610 if (ret < 0) { 611 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 612 return (-ret); 613 } 614 615 switch (reply[0] & AUX_NATIVE_REPLY_MASK) { 616 case AUX_NATIVE_REPLY_ACK: 617 /* I2C-over-AUX Reply field is only valid 618 * when paired with AUX ACK. 619 */ 620 break; 621 case AUX_NATIVE_REPLY_NACK: 622 DRM_DEBUG_KMS("aux_ch native nack\n"); 623 return (EREMOTEIO); 624 case AUX_NATIVE_REPLY_DEFER: 625 DELAY(100); 626 continue; 627 default: 628 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 629 reply[0]); 630 return (EREMOTEIO); 631 } 632 633 switch (reply[0] & AUX_I2C_REPLY_MASK) { 634 case AUX_I2C_REPLY_ACK: 635 if (mode == MODE_I2C_READ) { 636 *read_byte = reply[1]; 637 } 638 return (0/*reply_bytes - 1*/); 639 case AUX_I2C_REPLY_NACK: 640 DRM_DEBUG_KMS("aux_i2c nack\n"); 641 return (EREMOTEIO); 642 case AUX_I2C_REPLY_DEFER: 643 DRM_DEBUG_KMS("aux_i2c defer\n"); 644 DELAY(100); 645 break; 646 default: 647 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 648 return (EREMOTEIO); 649 } 650 } 651 652 DRM_ERROR("too many retries, giving up\n"); 653 return (EREMOTEIO); 654} 655 656static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); 657static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 658 659static int 660intel_dp_i2c_init(struct intel_dp *intel_dp, 661 struct intel_connector *intel_connector, const char *name) 662{ 663 int ret; 664 665 DRM_DEBUG_KMS("i2c_init %s\n", name); 666 667 ironlake_edp_panel_vdd_on(intel_dp); 668 ret = iic_dp_aux_add_bus(intel_connector->base.dev->device, name, 669 intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus, 670 &intel_dp->adapter); 671 ironlake_edp_panel_vdd_off(intel_dp, false); 672 return (ret); 673} 674 675static bool 676intel_dp_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, 677 struct drm_display_mode *adjusted_mode) 678{ 679 struct drm_device *dev = encoder->dev; 680 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 681 int lane_count, clock; 682 int max_lane_count = intel_dp_max_lane_count(intel_dp); 683 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 684 int bpp; 685 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 686 687 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { 688 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode); 689 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, 690 mode, adjusted_mode); 691 } 692 693 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, adjusted_mode)) 694 return false; 695 696 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24; 697 698 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 699 for (clock = 0; clock <= max_clock; clock++) { 700 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 701 702 if (intel_dp_link_required(adjusted_mode->clock, bpp) 703 <= link_avail) { 704 intel_dp->link_bw = bws[clock]; 705 intel_dp->lane_count = lane_count; 706 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 707 DRM_DEBUG_KMS("Display port link bw %02x lane " 708 "count %d clock %d\n", 709 intel_dp->link_bw, intel_dp->lane_count, 710 adjusted_mode->clock); 711 return true; 712 } 713 } 714 } 715 716 return false; 717} 718 719struct intel_dp_m_n { 720 uint32_t tu; 721 uint32_t gmch_m; 722 uint32_t gmch_n; 723 uint32_t link_m; 724 uint32_t link_n; 725}; 726 727static void 728intel_reduce_ratio(uint32_t *num, uint32_t *den) 729{ 730 while (*num > 0xffffff || *den > 0xffffff) { 731 *num >>= 1; 732 *den >>= 1; 733 } 734} 735 736static void 737intel_dp_compute_m_n(int bpp, 738 int nlanes, 739 int pixel_clock, 740 int link_clock, 741 struct intel_dp_m_n *m_n) 742{ 743 m_n->tu = 64; 744 m_n->gmch_m = (pixel_clock * bpp) >> 3; 745 m_n->gmch_n = link_clock * nlanes; 746 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 747 m_n->link_m = pixel_clock; 748 m_n->link_n = link_clock; 749 intel_reduce_ratio(&m_n->link_m, &m_n->link_n); 750} 751 752void 753intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 754 struct drm_display_mode *adjusted_mode) 755{ 756 struct drm_device *dev = crtc->dev; 757 struct drm_mode_config *mode_config = &dev->mode_config; 758 struct drm_encoder *encoder; 759 struct drm_i915_private *dev_priv = dev->dev_private; 760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 761 int lane_count = 4; 762 struct intel_dp_m_n m_n; 763 int pipe = intel_crtc->pipe; 764 765 /* 766 * Find the lane count in the intel_encoder private 767 */ 768 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 769 struct intel_dp *intel_dp; 770 771 if (encoder->crtc != crtc) 772 continue; 773 774 intel_dp = enc_to_intel_dp(encoder); 775 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || 776 intel_dp->base.type == INTEL_OUTPUT_EDP) 777 { 778 lane_count = intel_dp->lane_count; 779 break; 780 } 781 } 782 783 /* 784 * Compute the GMCH and Link ratios. The '3' here is 785 * the number of bytes_per_pixel post-LUT, which we always 786 * set up for 8-bits of R/G/B, or 3 bytes total. 787 */ 788 intel_dp_compute_m_n(intel_crtc->bpp, lane_count, 789 mode->clock, adjusted_mode->clock, &m_n); 790 791 if (HAS_PCH_SPLIT(dev)) { 792 I915_WRITE(TRANSDATA_M1(pipe), 793 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 794 m_n.gmch_m); 795 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); 796 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); 797 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); 798 } else { 799 I915_WRITE(PIPE_GMCH_DATA_M(pipe), 800 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 801 m_n.gmch_m); 802 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); 803 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); 804 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); 805 } 806} 807 808static void ironlake_edp_pll_on(struct drm_encoder *encoder); 809static void ironlake_edp_pll_off(struct drm_encoder *encoder); 810 811static void 812intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 813 struct drm_display_mode *adjusted_mode) 814{ 815 struct drm_device *dev = encoder->dev; 816 struct drm_i915_private *dev_priv = dev->dev_private; 817 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 818 struct drm_crtc *crtc = intel_dp->base.base.crtc; 819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 820 821 /* Turn on the eDP PLL if needed */ 822 if (is_edp(intel_dp)) { 823 if (!is_pch_edp(intel_dp)) 824 ironlake_edp_pll_on(encoder); 825 else 826 ironlake_edp_pll_off(encoder); 827 } 828 829 /* 830 * There are four kinds of DP registers: 831 * 832 * IBX PCH 833 * SNB CPU 834 * IVB CPU 835 * CPT PCH 836 * 837 * IBX PCH and CPU are the same for almost everything, 838 * except that the CPU DP PLL is configured in this 839 * register 840 * 841 * CPT PCH is quite different, having many bits moved 842 * to the TRANS_DP_CTL register instead. That 843 * configuration happens (oddly) in ironlake_pch_enable 844 */ 845 846 /* Preserve the BIOS-computed detected bit. This is 847 * supposed to be read-only. 848 */ 849 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 850 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 851 852 /* Handle DP bits in common between all three register formats */ 853 854 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 855 856 switch (intel_dp->lane_count) { 857 case 1: 858 intel_dp->DP |= DP_PORT_WIDTH_1; 859 break; 860 case 2: 861 intel_dp->DP |= DP_PORT_WIDTH_2; 862 break; 863 case 4: 864 intel_dp->DP |= DP_PORT_WIDTH_4; 865 break; 866 } 867 if (intel_dp->has_audio) { 868 DRM_DEBUG_KMS("Enabling DP audio on pipe %c\n", 869 pipe_name(intel_crtc->pipe)); 870 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 871 intel_write_eld(encoder, adjusted_mode); 872 } 873 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 874 intel_dp->link_configuration[0] = intel_dp->link_bw; 875 intel_dp->link_configuration[1] = intel_dp->lane_count; 876 /* 877 * Check for DPCD version > 1.1 and enhanced framing support 878 */ 879 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 880 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { 881 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 882 } 883 884 /* Split out the IBX/CPU vs CPT settings */ 885 886 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { 887 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 888 intel_dp->DP |= DP_SYNC_HS_HIGH; 889 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 890 intel_dp->DP |= DP_SYNC_VS_HIGH; 891 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 892 893 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) 894 intel_dp->DP |= DP_ENHANCED_FRAMING; 895 896 intel_dp->DP |= intel_crtc->pipe << 29; 897 898 /* don't miss out required setting for eDP */ 899 intel_dp->DP |= DP_PLL_ENABLE; 900 if (adjusted_mode->clock < 200000) 901 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 902 else 903 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 904 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { 905 intel_dp->DP |= intel_dp->color_range; 906 907 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 908 intel_dp->DP |= DP_SYNC_HS_HIGH; 909 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 910 intel_dp->DP |= DP_SYNC_VS_HIGH; 911 intel_dp->DP |= DP_LINK_TRAIN_OFF; 912 913 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) 914 intel_dp->DP |= DP_ENHANCED_FRAMING; 915 916 if (intel_crtc->pipe == 1) 917 intel_dp->DP |= DP_PIPEB_SELECT; 918 919 if (is_cpu_edp(intel_dp)) { 920 /* don't miss out required setting for eDP */ 921 intel_dp->DP |= DP_PLL_ENABLE; 922 if (adjusted_mode->clock < 200000) 923 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 924 else 925 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 926 } 927 } else { 928 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 929 } 930} 931 932#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 933#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 934 935#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 936#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 937 938#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 939#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 940 941static void ironlake_wait_panel_status(struct intel_dp *intel_dp, 942 u32 mask, 943 u32 value) 944{ 945 struct drm_device *dev = intel_dp->base.base.dev; 946 struct drm_i915_private *dev_priv = dev->dev_private; 947 948 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 949 mask, value, 950 I915_READ(PCH_PP_STATUS), 951 I915_READ(PCH_PP_CONTROL)); 952 953 if (_intel_wait_for(dev, 954 (I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10, "915iwp")) { 955 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 956 I915_READ(PCH_PP_STATUS), 957 I915_READ(PCH_PP_CONTROL)); 958 } 959} 960 961static void ironlake_wait_panel_on(struct intel_dp *intel_dp) 962{ 963 DRM_DEBUG_KMS("Wait for panel power on\n"); 964 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 965} 966 967static void ironlake_wait_panel_off(struct intel_dp *intel_dp) 968{ 969 DRM_DEBUG_KMS("Wait for panel power off time\n"); 970 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 971} 972 973static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) 974{ 975 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 976 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 977} 978 979 980/* Read the current pp_control value, unlocking the register if it 981 * is locked 982 */ 983 984static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv) 985{ 986 u32 control = I915_READ(PCH_PP_CONTROL); 987 988 control &= ~PANEL_UNLOCK_MASK; 989 control |= PANEL_UNLOCK_REGS; 990 return control; 991} 992 993static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) 994{ 995 struct drm_device *dev = intel_dp->base.base.dev; 996 struct drm_i915_private *dev_priv = dev->dev_private; 997 u32 pp; 998 999 if (!is_edp(intel_dp)) 1000 return; 1001 DRM_DEBUG_KMS("Turn eDP VDD on\n"); 1002 1003 if (intel_dp->want_panel_vdd) 1004 printf("eDP VDD already requested on\n"); 1005 1006 intel_dp->want_panel_vdd = true; 1007 1008 if (ironlake_edp_have_panel_vdd(intel_dp)) { 1009 DRM_DEBUG_KMS("eDP VDD already on\n"); 1010 return; 1011 } 1012 1013 if (!ironlake_edp_have_panel_power(intel_dp)) 1014 ironlake_wait_panel_power_cycle(intel_dp); 1015 1016 pp = ironlake_get_pp_control(dev_priv); 1017 pp |= EDP_FORCE_VDD; 1018 I915_WRITE(PCH_PP_CONTROL, pp); 1019 POSTING_READ(PCH_PP_CONTROL); 1020 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", 1021 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); 1022 1023 /* 1024 * If the panel wasn't on, delay before accessing aux channel 1025 */ 1026 if (!ironlake_edp_have_panel_power(intel_dp)) { 1027 DRM_DEBUG_KMS("eDP was not running\n"); 1028 drm_msleep(intel_dp->panel_power_up_delay, "915edpon"); 1029 } 1030} 1031 1032static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) 1033{ 1034 struct drm_device *dev = intel_dp->base.base.dev; 1035 struct drm_i915_private *dev_priv = dev->dev_private; 1036 u32 pp; 1037 1038 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { 1039 pp = ironlake_get_pp_control(dev_priv); 1040 pp &= ~EDP_FORCE_VDD; 1041 I915_WRITE(PCH_PP_CONTROL, pp); 1042 POSTING_READ(PCH_PP_CONTROL); 1043 1044 /* Make sure sequencer is idle before allowing subsequent activity */ 1045 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", 1046 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); 1047 1048 drm_msleep(intel_dp->panel_power_down_delay, "915vddo"); 1049 } 1050} 1051 1052static void ironlake_panel_vdd_work(void *arg, int pending __unused) 1053{ 1054 struct intel_dp *intel_dp = arg; 1055 struct drm_device *dev = intel_dp->base.base.dev; 1056 1057 sx_xlock(&dev->mode_config.mutex); 1058 ironlake_panel_vdd_off_sync(intel_dp); 1059 sx_xunlock(&dev->mode_config.mutex); 1060} 1061 1062static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1063{ 1064 if (!is_edp(intel_dp)) 1065 return; 1066 1067 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); 1068 if (!intel_dp->want_panel_vdd) 1069 printf("eDP VDD not forced on\n"); 1070 1071 intel_dp->want_panel_vdd = false; 1072 1073 if (sync) { 1074 ironlake_panel_vdd_off_sync(intel_dp); 1075 } else { 1076 /* 1077 * Queue the timer to fire a long 1078 * time from now (relative to the power down delay) 1079 * to keep the panel power up across a sequence of operations 1080 */ 1081 struct drm_i915_private *dev_priv = intel_dp->base.base.dev->dev_private; 1082 taskqueue_enqueue_timeout(dev_priv->tq, 1083 &intel_dp->panel_vdd_task, 1084 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); 1085 } 1086} 1087 1088static void ironlake_edp_panel_on(struct intel_dp *intel_dp) 1089{ 1090 struct drm_device *dev = intel_dp->base.base.dev; 1091 struct drm_i915_private *dev_priv = dev->dev_private; 1092 u32 pp; 1093 1094 if (!is_edp(intel_dp)) 1095 return; 1096 1097 DRM_DEBUG_KMS("Turn eDP power on\n"); 1098 1099 if (ironlake_edp_have_panel_power(intel_dp)) { 1100 DRM_DEBUG_KMS("eDP power already on\n"); 1101 return; 1102 } 1103 1104 ironlake_wait_panel_power_cycle(intel_dp); 1105 1106 pp = ironlake_get_pp_control(dev_priv); 1107 if (IS_GEN5(dev)) { 1108 /* ILK workaround: disable reset around power sequence */ 1109 pp &= ~PANEL_POWER_RESET; 1110 I915_WRITE(PCH_PP_CONTROL, pp); 1111 POSTING_READ(PCH_PP_CONTROL); 1112 } 1113 1114 pp |= POWER_TARGET_ON; 1115 if (!IS_GEN5(dev)) 1116 pp |= PANEL_POWER_RESET; 1117 1118 I915_WRITE(PCH_PP_CONTROL, pp); 1119 POSTING_READ(PCH_PP_CONTROL); 1120 1121 ironlake_wait_panel_on(intel_dp); 1122 1123 if (IS_GEN5(dev)) { 1124 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1125 I915_WRITE(PCH_PP_CONTROL, pp); 1126 POSTING_READ(PCH_PP_CONTROL); 1127 } 1128} 1129 1130static void ironlake_edp_panel_off(struct intel_dp *intel_dp) 1131{ 1132 struct drm_device *dev = intel_dp->base.base.dev; 1133 struct drm_i915_private *dev_priv = dev->dev_private; 1134 u32 pp; 1135 1136 if (!is_edp(intel_dp)) 1137 return; 1138 1139 DRM_DEBUG_KMS("Turn eDP power off\n"); 1140 1141 if (intel_dp->want_panel_vdd) 1142 printf("Cannot turn power off while VDD is on\n"); 1143 1144 pp = ironlake_get_pp_control(dev_priv); 1145 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); 1146 I915_WRITE(PCH_PP_CONTROL, pp); 1147 POSTING_READ(PCH_PP_CONTROL); 1148 1149 ironlake_wait_panel_off(intel_dp); 1150} 1151 1152static void ironlake_edp_backlight_on(struct intel_dp *intel_dp) 1153{ 1154 struct drm_device *dev = intel_dp->base.base.dev; 1155 struct drm_i915_private *dev_priv = dev->dev_private; 1156 u32 pp; 1157 1158 if (!is_edp(intel_dp)) 1159 return; 1160 1161 DRM_DEBUG_KMS("\n"); 1162 /* 1163 * If we enable the backlight right away following a panel power 1164 * on, we may see slight flicker as the panel syncs with the eDP 1165 * link. So delay a bit to make sure the image is solid before 1166 * allowing it to appear. 1167 */ 1168 drm_msleep(intel_dp->backlight_on_delay, "915ebo"); 1169 pp = ironlake_get_pp_control(dev_priv); 1170 pp |= EDP_BLC_ENABLE; 1171 I915_WRITE(PCH_PP_CONTROL, pp); 1172 POSTING_READ(PCH_PP_CONTROL); 1173} 1174 1175static void ironlake_edp_backlight_off(struct intel_dp *intel_dp) 1176{ 1177 struct drm_device *dev = intel_dp->base.base.dev; 1178 struct drm_i915_private *dev_priv = dev->dev_private; 1179 u32 pp; 1180 1181 if (!is_edp(intel_dp)) 1182 return; 1183 1184 DRM_DEBUG_KMS("\n"); 1185 pp = ironlake_get_pp_control(dev_priv); 1186 pp &= ~EDP_BLC_ENABLE; 1187 I915_WRITE(PCH_PP_CONTROL, pp); 1188 POSTING_READ(PCH_PP_CONTROL); 1189 drm_msleep(intel_dp->backlight_off_delay, "915bo1"); 1190} 1191 1192static void ironlake_edp_pll_on(struct drm_encoder *encoder) 1193{ 1194 struct drm_device *dev = encoder->dev; 1195 struct drm_i915_private *dev_priv = dev->dev_private; 1196 u32 dpa_ctl; 1197 1198 DRM_DEBUG_KMS("\n"); 1199 dpa_ctl = I915_READ(DP_A); 1200 dpa_ctl |= DP_PLL_ENABLE; 1201 I915_WRITE(DP_A, dpa_ctl); 1202 POSTING_READ(DP_A); 1203 DELAY(200); 1204} 1205 1206static void ironlake_edp_pll_off(struct drm_encoder *encoder) 1207{ 1208 struct drm_device *dev = encoder->dev; 1209 struct drm_i915_private *dev_priv = dev->dev_private; 1210 u32 dpa_ctl; 1211 1212 dpa_ctl = I915_READ(DP_A); 1213 dpa_ctl &= ~DP_PLL_ENABLE; 1214 I915_WRITE(DP_A, dpa_ctl); 1215 POSTING_READ(DP_A); 1216 DELAY(200); 1217} 1218 1219/* If the sink supports it, try to set the power state appropriately */ 1220static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1221{ 1222 int ret, i; 1223 1224 /* Should have a valid DPCD by this point */ 1225 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1226 return; 1227 1228 if (mode != DRM_MODE_DPMS_ON) { 1229 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, 1230 DP_SET_POWER_D3); 1231 if (ret != 1) 1232 DRM_DEBUG("failed to write sink power state\n"); 1233 } else { 1234 /* 1235 * When turning on, we need to retry for 1ms to give the sink 1236 * time to wake up. 1237 */ 1238 for (i = 0; i < 3; i++) { 1239 ret = intel_dp_aux_native_write_1(intel_dp, 1240 DP_SET_POWER, 1241 DP_SET_POWER_D0); 1242 if (ret == 1) 1243 break; 1244 drm_msleep(1, "915dps"); 1245 } 1246 } 1247} 1248 1249static void intel_dp_prepare(struct drm_encoder *encoder) 1250{ 1251 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1252 1253 ironlake_edp_backlight_off(intel_dp); 1254 ironlake_edp_panel_off(intel_dp); 1255 1256 /* Wake up the sink first */ 1257 ironlake_edp_panel_vdd_on(intel_dp); 1258 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1259 intel_dp_link_down(intel_dp); 1260 ironlake_edp_panel_vdd_off(intel_dp, false); 1261 1262 /* Make sure the panel is off before trying to 1263 * change the mode 1264 */ 1265} 1266 1267static void intel_dp_commit(struct drm_encoder *encoder) 1268{ 1269 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1270 struct drm_device *dev = encoder->dev; 1271 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); 1272 1273 ironlake_edp_panel_vdd_on(intel_dp); 1274 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1275 intel_dp_start_link_train(intel_dp); 1276 ironlake_edp_panel_on(intel_dp); 1277 ironlake_edp_panel_vdd_off(intel_dp, true); 1278 intel_dp_complete_link_train(intel_dp); 1279 ironlake_edp_backlight_on(intel_dp); 1280 1281 intel_dp->dpms_mode = DRM_MODE_DPMS_ON; 1282 1283 if (HAS_PCH_CPT(dev)) 1284 intel_cpt_verify_modeset(dev, intel_crtc->pipe); 1285} 1286 1287static void 1288intel_dp_dpms(struct drm_encoder *encoder, int mode) 1289{ 1290 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1291 struct drm_device *dev = encoder->dev; 1292 struct drm_i915_private *dev_priv = dev->dev_private; 1293 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1294 1295 if (mode != DRM_MODE_DPMS_ON) { 1296 ironlake_edp_backlight_off(intel_dp); 1297 ironlake_edp_panel_off(intel_dp); 1298 1299 ironlake_edp_panel_vdd_on(intel_dp); 1300 intel_dp_sink_dpms(intel_dp, mode); 1301 intel_dp_link_down(intel_dp); 1302 ironlake_edp_panel_vdd_off(intel_dp, false); 1303 1304 if (is_cpu_edp(intel_dp)) 1305 ironlake_edp_pll_off(encoder); 1306 } else { 1307 if (is_cpu_edp(intel_dp)) 1308 ironlake_edp_pll_on(encoder); 1309 1310 ironlake_edp_panel_vdd_on(intel_dp); 1311 intel_dp_sink_dpms(intel_dp, mode); 1312 if (!(dp_reg & DP_PORT_EN)) { 1313 intel_dp_start_link_train(intel_dp); 1314 ironlake_edp_panel_on(intel_dp); 1315 ironlake_edp_panel_vdd_off(intel_dp, true); 1316 intel_dp_complete_link_train(intel_dp); 1317 } else 1318 ironlake_edp_panel_vdd_off(intel_dp, false); 1319 ironlake_edp_backlight_on(intel_dp); 1320 } 1321 intel_dp->dpms_mode = mode; 1322} 1323/* 1324 * Native read with retry for link status and receiver capability reads for 1325 * cases where the sink may still be asleep. 1326 */ 1327static bool 1328intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, 1329 uint8_t *recv, int recv_bytes) 1330{ 1331 int ret, i; 1332 1333 /* 1334 * Sinks are *supposed* to come up within 1ms from an off state, 1335 * but we're also supposed to retry 3 times per the spec. 1336 */ 1337 for (i = 0; i < 3; i++) { 1338 ret = intel_dp_aux_native_read(intel_dp, address, recv, 1339 recv_bytes); 1340 if (ret == recv_bytes) 1341 return true; 1342 drm_msleep(1, "915dpl"); 1343 } 1344 1345 return false; 1346} 1347 1348/* 1349 * Fetch AUX CH registers 0x202 - 0x207 which contain 1350 * link status information 1351 */ 1352static bool 1353intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1354{ 1355 return intel_dp_aux_native_read_retry(intel_dp, 1356 DP_LANE0_1_STATUS, 1357 link_status, 1358 DP_LINK_STATUS_SIZE); 1359} 1360 1361static uint8_t 1362intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1363 int r) 1364{ 1365 return link_status[r - DP_LANE0_1_STATUS]; 1366} 1367 1368static uint8_t 1369intel_get_adjust_request_voltage(uint8_t adjust_request[2], 1370 int lane) 1371{ 1372 int s = ((lane & 1) ? 1373 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 1374 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 1375 uint8_t l = adjust_request[lane>>1]; 1376 1377 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 1378} 1379 1380static uint8_t 1381intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2], 1382 int lane) 1383{ 1384 int s = ((lane & 1) ? 1385 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 1386 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 1387 uint8_t l = adjust_request[lane>>1]; 1388 1389 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 1390} 1391 1392 1393#if 0 1394static char *voltage_names[] = { 1395 "0.4V", "0.6V", "0.8V", "1.2V" 1396}; 1397static char *pre_emph_names[] = { 1398 "0dB", "3.5dB", "6dB", "9.5dB" 1399}; 1400static char *link_train_names[] = { 1401 "pattern 1", "pattern 2", "idle", "off" 1402}; 1403#endif 1404 1405/* 1406 * These are source-specific values; current Intel hardware supports 1407 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 1408 */ 1409 1410static uint8_t 1411intel_dp_voltage_max(struct intel_dp *intel_dp) 1412{ 1413 struct drm_device *dev = intel_dp->base.base.dev; 1414 1415 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) 1416 return DP_TRAIN_VOLTAGE_SWING_800; 1417 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) 1418 return DP_TRAIN_VOLTAGE_SWING_1200; 1419 else 1420 return DP_TRAIN_VOLTAGE_SWING_800; 1421} 1422 1423static uint8_t 1424intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 1425{ 1426 struct drm_device *dev = intel_dp->base.base.dev; 1427 1428 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { 1429 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1430 case DP_TRAIN_VOLTAGE_SWING_400: 1431 return DP_TRAIN_PRE_EMPHASIS_6; 1432 case DP_TRAIN_VOLTAGE_SWING_600: 1433 case DP_TRAIN_VOLTAGE_SWING_800: 1434 return DP_TRAIN_PRE_EMPHASIS_3_5; 1435 default: 1436 return DP_TRAIN_PRE_EMPHASIS_0; 1437 } 1438 } else { 1439 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1440 case DP_TRAIN_VOLTAGE_SWING_400: 1441 return DP_TRAIN_PRE_EMPHASIS_6; 1442 case DP_TRAIN_VOLTAGE_SWING_600: 1443 return DP_TRAIN_PRE_EMPHASIS_6; 1444 case DP_TRAIN_VOLTAGE_SWING_800: 1445 return DP_TRAIN_PRE_EMPHASIS_3_5; 1446 case DP_TRAIN_VOLTAGE_SWING_1200: 1447 default: 1448 return DP_TRAIN_PRE_EMPHASIS_0; 1449 } 1450 } 1451} 1452 1453static void 1454intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1455{ 1456 uint8_t v = 0; 1457 uint8_t p = 0; 1458 int lane; 1459 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS); 1460 uint8_t voltage_max; 1461 uint8_t preemph_max; 1462 1463 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1464 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane); 1465 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane); 1466 1467 if (this_v > v) 1468 v = this_v; 1469 if (this_p > p) 1470 p = this_p; 1471 } 1472 1473 voltage_max = intel_dp_voltage_max(intel_dp); 1474 if (v >= voltage_max) 1475 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 1476 1477 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 1478 if (p >= preemph_max) 1479 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1480 1481 for (lane = 0; lane < 4; lane++) 1482 intel_dp->train_set[lane] = v | p; 1483} 1484 1485static uint32_t 1486intel_dp_signal_levels(uint8_t train_set) 1487{ 1488 uint32_t signal_levels = 0; 1489 1490 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 1491 case DP_TRAIN_VOLTAGE_SWING_400: 1492 default: 1493 signal_levels |= DP_VOLTAGE_0_4; 1494 break; 1495 case DP_TRAIN_VOLTAGE_SWING_600: 1496 signal_levels |= DP_VOLTAGE_0_6; 1497 break; 1498 case DP_TRAIN_VOLTAGE_SWING_800: 1499 signal_levels |= DP_VOLTAGE_0_8; 1500 break; 1501 case DP_TRAIN_VOLTAGE_SWING_1200: 1502 signal_levels |= DP_VOLTAGE_1_2; 1503 break; 1504 } 1505 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 1506 case DP_TRAIN_PRE_EMPHASIS_0: 1507 default: 1508 signal_levels |= DP_PRE_EMPHASIS_0; 1509 break; 1510 case DP_TRAIN_PRE_EMPHASIS_3_5: 1511 signal_levels |= DP_PRE_EMPHASIS_3_5; 1512 break; 1513 case DP_TRAIN_PRE_EMPHASIS_6: 1514 signal_levels |= DP_PRE_EMPHASIS_6; 1515 break; 1516 case DP_TRAIN_PRE_EMPHASIS_9_5: 1517 signal_levels |= DP_PRE_EMPHASIS_9_5; 1518 break; 1519 } 1520 return signal_levels; 1521} 1522 1523/* Gen6's DP voltage swing and pre-emphasis control */ 1524static uint32_t 1525intel_gen6_edp_signal_levels(uint8_t train_set) 1526{ 1527 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1528 DP_TRAIN_PRE_EMPHASIS_MASK); 1529 switch (signal_levels) { 1530 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1531 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1532 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1533 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1534 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1535 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1536 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 1537 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1538 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1539 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1540 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1541 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1542 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 1543 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1544 default: 1545 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1546 "0x%x\n", signal_levels); 1547 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1548 } 1549} 1550 1551/* Gen7's DP voltage swing and pre-emphasis control */ 1552static uint32_t 1553intel_gen7_edp_signal_levels(uint8_t train_set) 1554{ 1555 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1556 DP_TRAIN_PRE_EMPHASIS_MASK); 1557 switch (signal_levels) { 1558 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1559 return EDP_LINK_TRAIN_400MV_0DB_IVB; 1560 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1561 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 1562 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1563 return EDP_LINK_TRAIN_400MV_6DB_IVB; 1564 1565 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1566 return EDP_LINK_TRAIN_600MV_0DB_IVB; 1567 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1568 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 1569 1570 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1571 return EDP_LINK_TRAIN_800MV_0DB_IVB; 1572 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1573 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 1574 1575 default: 1576 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1577 "0x%x\n", signal_levels); 1578 return EDP_LINK_TRAIN_500MV_0DB_IVB; 1579 } 1580} 1581 1582static uint8_t 1583intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1584 int lane) 1585{ 1586 int s = (lane & 1) * 4; 1587 uint8_t l = link_status[lane>>1]; 1588 1589 return (l >> s) & 0xf; 1590} 1591 1592/* Check for clock recovery is done on all channels */ 1593static bool 1594intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) 1595{ 1596 int lane; 1597 uint8_t lane_status; 1598 1599 for (lane = 0; lane < lane_count; lane++) { 1600 lane_status = intel_get_lane_status(link_status, lane); 1601 if ((lane_status & DP_LANE_CR_DONE) == 0) 1602 return false; 1603 } 1604 return true; 1605} 1606 1607/* Check to see if channel eq is done on all channels */ 1608#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ 1609 DP_LANE_CHANNEL_EQ_DONE|\ 1610 DP_LANE_SYMBOL_LOCKED) 1611static bool 1612intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1613{ 1614 uint8_t lane_align; 1615 uint8_t lane_status; 1616 int lane; 1617 1618 lane_align = intel_dp_link_status(link_status, 1619 DP_LANE_ALIGN_STATUS_UPDATED); 1620 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 1621 return false; 1622 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1623 lane_status = intel_get_lane_status(link_status, lane); 1624 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) 1625 return false; 1626 } 1627 return true; 1628} 1629 1630static bool 1631intel_dp_set_link_train(struct intel_dp *intel_dp, 1632 uint32_t dp_reg_value, 1633 uint8_t dp_train_pat) 1634{ 1635 struct drm_device *dev = intel_dp->base.base.dev; 1636 struct drm_i915_private *dev_priv = dev->dev_private; 1637 int ret; 1638 1639 I915_WRITE(intel_dp->output_reg, dp_reg_value); 1640 POSTING_READ(intel_dp->output_reg); 1641 1642 intel_dp_aux_native_write_1(intel_dp, 1643 DP_TRAINING_PATTERN_SET, 1644 dp_train_pat); 1645 1646 ret = intel_dp_aux_native_write(intel_dp, 1647 DP_TRAINING_LANE0_SET, 1648 intel_dp->train_set, 1649 intel_dp->lane_count); 1650 if (ret != intel_dp->lane_count) 1651 return false; 1652 1653 return true; 1654} 1655 1656/* Enable corresponding port and start training pattern 1 */ 1657static void 1658intel_dp_start_link_train(struct intel_dp *intel_dp) 1659{ 1660 struct drm_device *dev = intel_dp->base.base.dev; 1661 struct drm_i915_private *dev_priv = dev->dev_private; 1662 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); 1663 int i; 1664 uint8_t voltage; 1665 bool clock_recovery = false; 1666 int voltage_tries, loop_tries; 1667 u32 reg; 1668 uint32_t DP = intel_dp->DP; 1669 1670 /* Enable output, wait for it to become active */ 1671 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 1672 POSTING_READ(intel_dp->output_reg); 1673 intel_wait_for_vblank(dev, intel_crtc->pipe); 1674 1675 /* Write the link configuration data */ 1676 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, 1677 intel_dp->link_configuration, 1678 DP_LINK_CONFIGURATION_SIZE); 1679 1680 DP |= DP_PORT_EN; 1681 1682 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) 1683 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1684 else 1685 DP &= ~DP_LINK_TRAIN_MASK; 1686 memset(intel_dp->train_set, 0, 4); 1687 voltage = 0xff; 1688 voltage_tries = 0; 1689 loop_tries = 0; 1690 clock_recovery = false; 1691 for (;;) { 1692 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1693 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1694 uint32_t signal_levels; 1695 1696 1697 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { 1698 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); 1699 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; 1700 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { 1701 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1702 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1703 } else { 1704 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); 1705 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels); 1706 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1707 } 1708 1709 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) 1710 reg = DP | DP_LINK_TRAIN_PAT_1_CPT; 1711 else 1712 reg = DP | DP_LINK_TRAIN_PAT_1; 1713 1714 if (!intel_dp_set_link_train(intel_dp, reg, 1715 DP_TRAINING_PATTERN_1)) 1716 break; 1717 /* Set training pattern 1 */ 1718 1719 DELAY(100); 1720 if (!intel_dp_get_link_status(intel_dp, link_status)) { 1721 DRM_ERROR("failed to get link status\n"); 1722 break; 1723 } 1724 1725 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { 1726 DRM_DEBUG_KMS("clock recovery OK\n"); 1727 clock_recovery = true; 1728 break; 1729 } 1730 1731 /* Check to see if we've tried the max voltage */ 1732 for (i = 0; i < intel_dp->lane_count; i++) 1733 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1734 break; 1735 if (i == intel_dp->lane_count) { 1736 ++loop_tries; 1737 if (loop_tries == 5) { 1738 DRM_DEBUG_KMS("too many full retries, give up\n"); 1739 break; 1740 } 1741 memset(intel_dp->train_set, 0, 4); 1742 voltage_tries = 0; 1743 continue; 1744 } 1745 1746 /* Check to see if we've tried the same voltage 5 times */ 1747 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 1748 ++voltage_tries; 1749 if (voltage_tries == 5) { 1750 DRM_DEBUG_KMS("too many voltage retries, give up\n"); 1751 break; 1752 } 1753 } else 1754 voltage_tries = 0; 1755 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1756 1757 /* Compute new intel_dp->train_set as requested by target */ 1758 intel_get_adjust_train(intel_dp, link_status); 1759 } 1760 1761 intel_dp->DP = DP; 1762} 1763 1764static void 1765intel_dp_complete_link_train(struct intel_dp *intel_dp) 1766{ 1767 struct drm_device *dev = intel_dp->base.base.dev; 1768 struct drm_i915_private *dev_priv = dev->dev_private; 1769 bool channel_eq = false; 1770 int tries, cr_tries; 1771 u32 reg; 1772 uint32_t DP = intel_dp->DP; 1773 1774 /* channel equalization */ 1775 tries = 0; 1776 cr_tries = 0; 1777 channel_eq = false; 1778 for (;;) { 1779 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1780 uint32_t signal_levels; 1781 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1782 1783 if (cr_tries > 5) { 1784 DRM_ERROR("failed to train DP, aborting\n"); 1785 intel_dp_link_down(intel_dp); 1786 break; 1787 } 1788 1789 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { 1790 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); 1791 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; 1792 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { 1793 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1794 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1795 } else { 1796 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); 1797 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1798 } 1799 1800 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) 1801 reg = DP | DP_LINK_TRAIN_PAT_2_CPT; 1802 else 1803 reg = DP | DP_LINK_TRAIN_PAT_2; 1804 1805 /* channel eq pattern */ 1806 if (!intel_dp_set_link_train(intel_dp, reg, 1807 DP_TRAINING_PATTERN_2)) 1808 break; 1809 1810 DELAY(400); 1811 if (!intel_dp_get_link_status(intel_dp, link_status)) 1812 break; 1813 1814 /* Make sure clock is still ok */ 1815 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { 1816 intel_dp_start_link_train(intel_dp); 1817 cr_tries++; 1818 continue; 1819 } 1820 1821 if (intel_channel_eq_ok(intel_dp, link_status)) { 1822 channel_eq = true; 1823 break; 1824 } 1825 1826 /* Try 5 times, then try clock recovery if that fails */ 1827 if (tries > 5) { 1828 intel_dp_link_down(intel_dp); 1829 intel_dp_start_link_train(intel_dp); 1830 tries = 0; 1831 cr_tries++; 1832 continue; 1833 } 1834 1835 /* Compute new intel_dp->train_set as requested by target */ 1836 intel_get_adjust_train(intel_dp, link_status); 1837 ++tries; 1838 } 1839 1840 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) 1841 reg = DP | DP_LINK_TRAIN_OFF_CPT; 1842 else 1843 reg = DP | DP_LINK_TRAIN_OFF; 1844 1845 I915_WRITE(intel_dp->output_reg, reg); 1846 POSTING_READ(intel_dp->output_reg); 1847 intel_dp_aux_native_write_1(intel_dp, 1848 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); 1849} 1850 1851static void 1852intel_dp_link_down(struct intel_dp *intel_dp) 1853{ 1854 struct drm_device *dev = intel_dp->base.base.dev; 1855 struct drm_i915_private *dev_priv = dev->dev_private; 1856 uint32_t DP = intel_dp->DP; 1857 1858 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) 1859 return; 1860 1861 DRM_DEBUG_KMS("\n"); 1862 1863 if (is_edp(intel_dp)) { 1864 DP &= ~DP_PLL_ENABLE; 1865 I915_WRITE(intel_dp->output_reg, DP); 1866 POSTING_READ(intel_dp->output_reg); 1867 DELAY(100); 1868 } 1869 1870 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { 1871 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1872 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 1873 } else { 1874 DP &= ~DP_LINK_TRAIN_MASK; 1875 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1876 } 1877 POSTING_READ(intel_dp->output_reg); 1878 1879 drm_msleep(17, "915dlo"); 1880 1881 if (is_edp(intel_dp)) { 1882 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) 1883 DP |= DP_LINK_TRAIN_OFF_CPT; 1884 else 1885 DP |= DP_LINK_TRAIN_OFF; 1886 } 1887 1888 1889 if (!HAS_PCH_CPT(dev) && 1890 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 1891 struct drm_crtc *crtc = intel_dp->base.base.crtc; 1892 1893 /* Hardware workaround: leaving our transcoder select 1894 * set to transcoder B while it's off will prevent the 1895 * corresponding HDMI output on transcoder A. 1896 * 1897 * Combine this with another hardware workaround: 1898 * transcoder select bit can only be cleared while the 1899 * port is enabled. 1900 */ 1901 DP &= ~DP_PIPEB_SELECT; 1902 I915_WRITE(intel_dp->output_reg, DP); 1903 1904 /* Changes to enable or select take place the vblank 1905 * after being written. 1906 */ 1907 if (crtc == NULL) { 1908 /* We can arrive here never having been attached 1909 * to a CRTC, for instance, due to inheriting 1910 * random state from the BIOS. 1911 * 1912 * If the pipe is not running, play safe and 1913 * wait for the clocks to stabilise before 1914 * continuing. 1915 */ 1916 POSTING_READ(intel_dp->output_reg); 1917 drm_msleep(50, "915dla"); 1918 } else 1919 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); 1920 } 1921 1922 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 1923 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 1924 POSTING_READ(intel_dp->output_reg); 1925 drm_msleep(intel_dp->panel_power_down_delay, "915ldo"); 1926} 1927 1928static bool 1929intel_dp_get_dpcd(struct intel_dp *intel_dp) 1930{ 1931 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, 1932 sizeof(intel_dp->dpcd)) && 1933 (intel_dp->dpcd[DP_DPCD_REV] != 0)) { 1934 return true; 1935 } 1936 1937 return false; 1938} 1939 1940static bool 1941intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 1942{ 1943 int ret; 1944 1945 ret = intel_dp_aux_native_read_retry(intel_dp, 1946 DP_DEVICE_SERVICE_IRQ_VECTOR, 1947 sink_irq_vector, 1); 1948 if (!ret) 1949 return false; 1950 1951 return true; 1952} 1953 1954static void 1955intel_dp_handle_test_request(struct intel_dp *intel_dp) 1956{ 1957 /* NAK by default */ 1958 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK); 1959} 1960 1961/* 1962 * According to DP spec 1963 * 5.1.2: 1964 * 1. Read DPCD 1965 * 2. Configure link according to Receiver Capabilities 1966 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 1967 * 4. Check link status on receipt of hot-plug interrupt 1968 */ 1969 1970static void 1971intel_dp_check_link_status(struct intel_dp *intel_dp) 1972{ 1973 u8 sink_irq_vector; 1974 u8 link_status[DP_LINK_STATUS_SIZE]; 1975 1976 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON) 1977 return; 1978 1979 if (!intel_dp->base.base.crtc) 1980 return; 1981 1982 /* Try to read receiver status if the link appears to be up */ 1983 if (!intel_dp_get_link_status(intel_dp, link_status)) { 1984 intel_dp_link_down(intel_dp); 1985 return; 1986 } 1987 1988 /* Now read the DPCD to see if it's actually running */ 1989 if (!intel_dp_get_dpcd(intel_dp)) { 1990 intel_dp_link_down(intel_dp); 1991 return; 1992 } 1993 1994 /* Try to read the source of the interrupt */ 1995 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 1996 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 1997 /* Clear interrupt source */ 1998 intel_dp_aux_native_write_1(intel_dp, 1999 DP_DEVICE_SERVICE_IRQ_VECTOR, 2000 sink_irq_vector); 2001 2002 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 2003 intel_dp_handle_test_request(intel_dp); 2004 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 2005 DRM_DEBUG_KMS("CP or sink specific irq unhandled\n"); 2006 } 2007 2008 if (!intel_channel_eq_ok(intel_dp, link_status)) { 2009 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 2010 drm_get_encoder_name(&intel_dp->base.base)); 2011 intel_dp_start_link_train(intel_dp); 2012 intel_dp_complete_link_train(intel_dp); 2013 } 2014} 2015 2016static enum drm_connector_status 2017intel_dp_detect_dpcd(struct intel_dp *intel_dp) 2018{ 2019 if (intel_dp_get_dpcd(intel_dp)) 2020 return connector_status_connected; 2021 return connector_status_disconnected; 2022} 2023 2024static enum drm_connector_status 2025ironlake_dp_detect(struct intel_dp *intel_dp) 2026{ 2027 enum drm_connector_status status; 2028 2029 /* Can't disconnect eDP, but you can close the lid... */ 2030 if (is_edp(intel_dp)) { 2031 status = intel_panel_detect(intel_dp->base.base.dev); 2032 if (status == connector_status_unknown) 2033 status = connector_status_connected; 2034 return status; 2035 } 2036 2037 return intel_dp_detect_dpcd(intel_dp); 2038} 2039 2040static enum drm_connector_status 2041g4x_dp_detect(struct intel_dp *intel_dp) 2042{ 2043 struct drm_device *dev = intel_dp->base.base.dev; 2044 struct drm_i915_private *dev_priv = dev->dev_private; 2045 uint32_t temp, bit; 2046 2047 switch (intel_dp->output_reg) { 2048 case DP_B: 2049 bit = DPB_HOTPLUG_INT_STATUS; 2050 break; 2051 case DP_C: 2052 bit = DPC_HOTPLUG_INT_STATUS; 2053 break; 2054 case DP_D: 2055 bit = DPD_HOTPLUG_INT_STATUS; 2056 break; 2057 default: 2058 return connector_status_unknown; 2059 } 2060 2061 temp = I915_READ(PORT_HOTPLUG_STAT); 2062 2063 if ((temp & bit) == 0) 2064 return connector_status_disconnected; 2065 2066 return intel_dp_detect_dpcd(intel_dp); 2067} 2068 2069static struct edid * 2070intel_dp_get_edid(struct drm_connector *connector, device_t adapter) 2071{ 2072 struct intel_dp *intel_dp = intel_attached_dp(connector); 2073 struct edid *edid; 2074 2075 ironlake_edp_panel_vdd_on(intel_dp); 2076 edid = drm_get_edid(connector, adapter); 2077 ironlake_edp_panel_vdd_off(intel_dp, false); 2078 return edid; 2079} 2080 2081static int 2082intel_dp_get_edid_modes(struct drm_connector *connector, device_t adapter) 2083{ 2084 struct intel_dp *intel_dp = intel_attached_dp(connector); 2085 int ret; 2086 2087 ironlake_edp_panel_vdd_on(intel_dp); 2088 ret = intel_ddc_get_modes(connector, adapter); 2089 ironlake_edp_panel_vdd_off(intel_dp, false); 2090 return ret; 2091} 2092 2093 2094/** 2095 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. 2096 * 2097 * \return true if DP port is connected. 2098 * \return false if DP port is disconnected. 2099 */ 2100static enum drm_connector_status 2101intel_dp_detect(struct drm_connector *connector, bool force) 2102{ 2103 struct intel_dp *intel_dp = intel_attached_dp(connector); 2104 struct drm_device *dev = intel_dp->base.base.dev; 2105 enum drm_connector_status status; 2106 struct edid *edid = NULL; 2107 2108 intel_dp->has_audio = false; 2109 2110 if (HAS_PCH_SPLIT(dev)) 2111 status = ironlake_dp_detect(intel_dp); 2112 else 2113 status = g4x_dp_detect(intel_dp); 2114 if (status != connector_status_connected) 2115 return status; 2116 2117 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 2118 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 2119 } else { 2120 edid = intel_dp_get_edid(connector, intel_dp->adapter); 2121 if (edid) { 2122 intel_dp->has_audio = drm_detect_monitor_audio(edid); 2123 connector->display_info.raw_edid = NULL; 2124 free(edid, DRM_MEM_KMS); 2125 } 2126 } 2127 2128 return connector_status_connected; 2129} 2130 2131static int intel_dp_get_modes(struct drm_connector *connector) 2132{ 2133 struct intel_dp *intel_dp = intel_attached_dp(connector); 2134 struct drm_device *dev = intel_dp->base.base.dev; 2135 struct drm_i915_private *dev_priv = dev->dev_private; 2136 int ret; 2137 2138 /* We should parse the EDID data and find out if it has an audio sink 2139 */ 2140 2141 ret = intel_dp_get_edid_modes(connector, intel_dp->adapter); 2142 if (ret) { 2143 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) { 2144 struct drm_display_mode *newmode; 2145 list_for_each_entry(newmode, &connector->probed_modes, 2146 head) { 2147 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) { 2148 intel_dp->panel_fixed_mode = 2149 drm_mode_duplicate(dev, newmode); 2150 break; 2151 } 2152 } 2153 } 2154 return ret; 2155 } 2156 2157 /* if eDP has no EDID, try to use fixed panel mode from VBT */ 2158 if (is_edp(intel_dp)) { 2159 /* initialize panel mode from VBT if available for eDP */ 2160 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) { 2161 intel_dp->panel_fixed_mode = 2162 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); 2163 if (intel_dp->panel_fixed_mode) { 2164 intel_dp->panel_fixed_mode->type |= 2165 DRM_MODE_TYPE_PREFERRED; 2166 } 2167 } 2168 if (intel_dp->panel_fixed_mode) { 2169 struct drm_display_mode *mode; 2170 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode); 2171 drm_mode_probed_add(connector, mode); 2172 return 1; 2173 } 2174 } 2175 return 0; 2176} 2177 2178static bool 2179intel_dp_detect_audio(struct drm_connector *connector) 2180{ 2181 struct intel_dp *intel_dp = intel_attached_dp(connector); 2182 struct edid *edid; 2183 bool has_audio = false; 2184 2185 edid = intel_dp_get_edid(connector, intel_dp->adapter); 2186 if (edid) { 2187 has_audio = drm_detect_monitor_audio(edid); 2188 2189 connector->display_info.raw_edid = NULL; 2190 free(edid, DRM_MEM_KMS); 2191 } 2192 2193 return has_audio; 2194} 2195 2196static int 2197intel_dp_set_property(struct drm_connector *connector, 2198 struct drm_property *property, 2199 uint64_t val) 2200{ 2201 struct drm_i915_private *dev_priv = connector->dev->dev_private; 2202 struct intel_dp *intel_dp = intel_attached_dp(connector); 2203 int ret; 2204 2205 ret = drm_connector_property_set_value(connector, property, val); 2206 if (ret) 2207 return ret; 2208 2209 if (property == dev_priv->force_audio_property) { 2210 int i = val; 2211 bool has_audio; 2212 2213 if (i == intel_dp->force_audio) 2214 return 0; 2215 2216 intel_dp->force_audio = i; 2217 2218 if (i == HDMI_AUDIO_AUTO) 2219 has_audio = intel_dp_detect_audio(connector); 2220 else 2221 has_audio = (i == HDMI_AUDIO_ON); 2222 2223 if (has_audio == intel_dp->has_audio) 2224 return 0; 2225 2226 intel_dp->has_audio = has_audio; 2227 goto done; 2228 } 2229 2230 if (property == dev_priv->broadcast_rgb_property) { 2231 if (val == !!intel_dp->color_range) 2232 return 0; 2233 2234 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; 2235 goto done; 2236 } 2237 2238 return -EINVAL; 2239 2240done: 2241 if (intel_dp->base.base.crtc) { 2242 struct drm_crtc *crtc = intel_dp->base.base.crtc; 2243 drm_crtc_helper_set_mode(crtc, &crtc->mode, 2244 crtc->x, crtc->y, 2245 crtc->fb); 2246 } 2247 2248 return 0; 2249} 2250 2251static void 2252intel_dp_destroy(struct drm_connector *connector) 2253{ 2254 struct drm_device *dev = connector->dev; 2255 2256 if (intel_dpd_is_edp(dev)) 2257 intel_panel_destroy_backlight(dev); 2258 2259#if 0 2260 drm_sysfs_connector_remove(connector); 2261#endif 2262 drm_connector_cleanup(connector); 2263 free(connector, DRM_MEM_KMS); 2264} 2265 2266static void intel_dp_encoder_destroy(struct drm_encoder *encoder) 2267{ 2268 struct drm_device *dev; 2269 struct intel_dp *intel_dp; 2270 2271 intel_dp = enc_to_intel_dp(encoder); 2272 dev = encoder->dev; 2273 2274 if (intel_dp->dp_iic_bus != NULL) { 2275 if (intel_dp->adapter != NULL) { 2276 device_delete_child(intel_dp->dp_iic_bus, 2277 intel_dp->adapter); 2278 } 2279 device_delete_child(dev->device, intel_dp->dp_iic_bus); 2280 } 2281 drm_encoder_cleanup(encoder); 2282 if (is_edp(intel_dp)) { 2283 struct drm_i915_private *dev_priv = intel_dp->base.base.dev->dev_private; 2284 2285 taskqueue_cancel_timeout(dev_priv->tq, 2286 &intel_dp->panel_vdd_task, NULL); 2287 taskqueue_drain_timeout(dev_priv->tq, 2288 &intel_dp->panel_vdd_task); 2289 ironlake_panel_vdd_off_sync(intel_dp); 2290 } 2291 free(intel_dp, DRM_MEM_KMS); 2292} 2293 2294static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 2295 .dpms = intel_dp_dpms, 2296 .mode_fixup = intel_dp_mode_fixup, 2297 .prepare = intel_dp_prepare, 2298 .mode_set = intel_dp_mode_set, 2299 .commit = intel_dp_commit, 2300}; 2301 2302static const struct drm_connector_funcs intel_dp_connector_funcs = { 2303 .dpms = drm_helper_connector_dpms, 2304 .detect = intel_dp_detect, 2305 .fill_modes = drm_helper_probe_single_connector_modes, 2306 .set_property = intel_dp_set_property, 2307 .destroy = intel_dp_destroy, 2308}; 2309 2310static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 2311 .get_modes = intel_dp_get_modes, 2312 .mode_valid = intel_dp_mode_valid, 2313 .best_encoder = intel_best_encoder, 2314}; 2315 2316static const struct drm_encoder_funcs intel_dp_enc_funcs = { 2317 .destroy = intel_dp_encoder_destroy, 2318}; 2319 2320static void 2321intel_dp_hot_plug(struct intel_encoder *intel_encoder) 2322{ 2323 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 2324 2325 intel_dp_check_link_status(intel_dp); 2326} 2327 2328/* Return which DP Port should be selected for Transcoder DP control */ 2329int 2330intel_trans_dp_port_sel(struct drm_crtc *crtc) 2331{ 2332 struct drm_device *dev = crtc->dev; 2333 struct drm_mode_config *mode_config = &dev->mode_config; 2334 struct drm_encoder *encoder; 2335 2336 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 2337 struct intel_dp *intel_dp; 2338 2339 if (encoder->crtc != crtc) 2340 continue; 2341 2342 intel_dp = enc_to_intel_dp(encoder); 2343 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || 2344 intel_dp->base.type == INTEL_OUTPUT_EDP) 2345 return intel_dp->output_reg; 2346 } 2347 2348 return -1; 2349} 2350 2351/* check the VBT to see whether the eDP is on DP-D port */ 2352bool intel_dpd_is_edp(struct drm_device *dev) 2353{ 2354 struct drm_i915_private *dev_priv = dev->dev_private; 2355 struct child_device_config *p_child; 2356 int i; 2357 2358 if (!dev_priv->child_dev_num) 2359 return false; 2360 2361 for (i = 0; i < dev_priv->child_dev_num; i++) { 2362 p_child = dev_priv->child_dev + i; 2363 2364 if (p_child->dvo_port == PORT_IDPD && 2365 p_child->device_type == DEVICE_TYPE_eDP) 2366 return true; 2367 } 2368 return false; 2369} 2370 2371static void 2372intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 2373{ 2374 intel_attach_force_audio_property(connector); 2375 intel_attach_broadcast_rgb_property(connector); 2376} 2377 2378void 2379intel_dp_init(struct drm_device *dev, int output_reg) 2380{ 2381 struct drm_i915_private *dev_priv = dev->dev_private; 2382 struct drm_connector *connector; 2383 struct intel_dp *intel_dp; 2384 struct intel_encoder *intel_encoder; 2385 struct intel_connector *intel_connector; 2386 const char *name = NULL; 2387 int type; 2388 2389 intel_dp = malloc(sizeof(struct intel_dp), DRM_MEM_KMS, 2390 M_WAITOK | M_ZERO); 2391 2392 intel_dp->output_reg = output_reg; 2393 intel_dp->dpms_mode = -1; 2394 2395 intel_connector = malloc(sizeof(struct intel_connector), DRM_MEM_KMS, 2396 M_WAITOK | M_ZERO); 2397 intel_encoder = &intel_dp->base; 2398 2399 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) 2400 if (intel_dpd_is_edp(dev)) 2401 intel_dp->is_pch_edp = true; 2402 2403 if (output_reg == DP_A || is_pch_edp(intel_dp)) { 2404 type = DRM_MODE_CONNECTOR_eDP; 2405 intel_encoder->type = INTEL_OUTPUT_EDP; 2406 } else { 2407 type = DRM_MODE_CONNECTOR_DisplayPort; 2408 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 2409 } 2410 2411 connector = &intel_connector->base; 2412 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 2413 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 2414 2415 connector->polled = DRM_CONNECTOR_POLL_HPD; 2416 2417 if (output_reg == DP_B || output_reg == PCH_DP_B) 2418 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); 2419 else if (output_reg == DP_C || output_reg == PCH_DP_C) 2420 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); 2421 else if (output_reg == DP_D || output_reg == PCH_DP_D) 2422 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); 2423 2424 if (is_edp(intel_dp)) { 2425 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); 2426 TIMEOUT_TASK_INIT(dev_priv->tq, &intel_dp->panel_vdd_task, 0, 2427 ironlake_panel_vdd_work, intel_dp); 2428 } 2429 2430 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2431 connector->interlace_allowed = true; 2432 connector->doublescan_allowed = 0; 2433 2434 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 2435 DRM_MODE_ENCODER_TMDS); 2436 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); 2437 2438 intel_connector_attach_encoder(intel_connector, intel_encoder); 2439#if 0 2440 drm_sysfs_connector_add(connector); 2441#endif 2442 2443 /* Set up the DDC bus. */ 2444 switch (output_reg) { 2445 case DP_A: 2446 name = "DPDDC-A"; 2447 break; 2448 case DP_B: 2449 case PCH_DP_B: 2450 dev_priv->hotplug_supported_mask |= 2451 HDMIB_HOTPLUG_INT_STATUS; 2452 name = "DPDDC-B"; 2453 break; 2454 case DP_C: 2455 case PCH_DP_C: 2456 dev_priv->hotplug_supported_mask |= 2457 HDMIC_HOTPLUG_INT_STATUS; 2458 name = "DPDDC-C"; 2459 break; 2460 case DP_D: 2461 case PCH_DP_D: 2462 dev_priv->hotplug_supported_mask |= 2463 HDMID_HOTPLUG_INT_STATUS; 2464 name = "DPDDC-D"; 2465 break; 2466 } 2467 2468 /* Cache some DPCD data in the eDP case */ 2469 if (is_edp(intel_dp)) { 2470 bool ret; 2471 struct edp_power_seq cur, vbt; 2472 u32 pp_on, pp_off, pp_div; 2473 2474 pp_on = I915_READ(PCH_PP_ON_DELAYS); 2475 pp_off = I915_READ(PCH_PP_OFF_DELAYS); 2476 pp_div = I915_READ(PCH_PP_DIVISOR); 2477 2478 /* Pull timing values out of registers */ 2479 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 2480 PANEL_POWER_UP_DELAY_SHIFT; 2481 2482 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 2483 PANEL_LIGHT_ON_DELAY_SHIFT; 2484 2485 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 2486 PANEL_LIGHT_OFF_DELAY_SHIFT; 2487 2488 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 2489 PANEL_POWER_DOWN_DELAY_SHIFT; 2490 2491 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 2492 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 2493 2494 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 2495 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 2496 2497 vbt = dev_priv->edp.pps; 2498 2499 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 2500 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 2501 2502#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10) 2503 2504 intel_dp->panel_power_up_delay = get_delay(t1_t3); 2505 intel_dp->backlight_on_delay = get_delay(t8); 2506 intel_dp->backlight_off_delay = get_delay(t9); 2507 intel_dp->panel_power_down_delay = get_delay(t10); 2508 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 2509 2510 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 2511 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 2512 intel_dp->panel_power_cycle_delay); 2513 2514 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 2515 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 2516 2517 ironlake_edp_panel_vdd_on(intel_dp); 2518 ret = intel_dp_get_dpcd(intel_dp); 2519 ironlake_edp_panel_vdd_off(intel_dp, false); 2520 2521 if (ret) { 2522 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 2523 dev_priv->no_aux_handshake = 2524 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 2525 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 2526 } else { 2527 /* if this fails, presume the device is a ghost */ 2528 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 2529 intel_dp_encoder_destroy(&intel_dp->base.base); 2530 intel_dp_destroy(&intel_connector->base); 2531 return; 2532 } 2533 } 2534 2535 intel_dp_i2c_init(intel_dp, intel_connector, name); 2536 2537 intel_encoder->hot_plug = intel_dp_hot_plug; 2538 2539 if (is_edp(intel_dp)) { 2540 dev_priv->int_edp_connector = connector; 2541 intel_panel_setup_backlight(dev); 2542 } 2543 2544 intel_dp_add_properties(intel_dp, connector); 2545 2546 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2547 * 0xd. Failure to do so will result in spurious interrupts being 2548 * generated on the port when a cable is not attached. 2549 */ 2550 if (IS_G4X(dev) && !IS_GM45(dev)) { 2551 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 2552 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 2553 } 2554} 2555