common.h revision 252495
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/9/sys/dev/cxgbe/common/common.h 252495 2013-07-02 04:27:16Z np $ 27 * 28 */ 29 30#ifndef __CHELSIO_COMMON_H 31#define __CHELSIO_COMMON_H 32 33#include "t4_hw.h" 34 35 36enum { 37 MAX_NPORTS = 4, /* max # of ports */ 38 SERNUM_LEN = 24, /* Serial # length */ 39 EC_LEN = 16, /* E/C length */ 40 ID_LEN = 16, /* ID length */ 41 PN_LEN = 16, /* Part Number length */ 42 MACADDR_LEN = 12, /* MAC Address length */ 43}; 44 45enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 46 47enum { 48 MEMWIN0_APERTURE = 2048, 49 MEMWIN0_BASE = 0x1b800, 50 MEMWIN1_APERTURE = 32768, 51 MEMWIN1_BASE = 0x28000, 52 53 MEMWIN2_APERTURE_T4 = 65536, 54 MEMWIN2_BASE_T4 = 0x30000, 55 56 MEMWIN2_APERTURE_T5 = 128 * 1024, 57 MEMWIN2_BASE_T5 = 0x60000, 58}; 59 60enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 61 62enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 63 64enum { 65 PAUSE_RX = 1 << 0, 66 PAUSE_TX = 1 << 1, 67 PAUSE_AUTONEG = 1 << 2 68}; 69 70#define FW_VERSION_MAJOR_T4 1 71#define FW_VERSION_MINOR_T4 8 72#define FW_VERSION_MICRO_T4 4 73#define FW_VERSION_BUILD_T4 0 74 75#define FW_VERSION_MAJOR_T5 0 76#define FW_VERSION_MINOR_T5 5 77#define FW_VERSION_MICRO_T5 18 78#define FW_VERSION_BUILD_T5 0 79 80struct memwin { 81 uint32_t base; 82 uint32_t aperture; 83}; 84 85struct port_stats { 86 u64 tx_octets; /* total # of octets in good frames */ 87 u64 tx_frames; /* all good frames */ 88 u64 tx_bcast_frames; /* all broadcast frames */ 89 u64 tx_mcast_frames; /* all multicast frames */ 90 u64 tx_ucast_frames; /* all unicast frames */ 91 u64 tx_error_frames; /* all error frames */ 92 93 u64 tx_frames_64; /* # of Tx frames in a particular range */ 94 u64 tx_frames_65_127; 95 u64 tx_frames_128_255; 96 u64 tx_frames_256_511; 97 u64 tx_frames_512_1023; 98 u64 tx_frames_1024_1518; 99 u64 tx_frames_1519_max; 100 101 u64 tx_drop; /* # of dropped Tx frames */ 102 u64 tx_pause; /* # of transmitted pause frames */ 103 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 104 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 105 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 106 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 107 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 108 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 109 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 110 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 111 112 u64 rx_octets; /* total # of octets in good frames */ 113 u64 rx_frames; /* all good frames */ 114 u64 rx_bcast_frames; /* all broadcast frames */ 115 u64 rx_mcast_frames; /* all multicast frames */ 116 u64 rx_ucast_frames; /* all unicast frames */ 117 u64 rx_too_long; /* # of frames exceeding MTU */ 118 u64 rx_jabber; /* # of jabber frames */ 119 u64 rx_fcs_err; /* # of received frames with bad FCS */ 120 u64 rx_len_err; /* # of received frames with length error */ 121 u64 rx_symbol_err; /* symbol errors */ 122 u64 rx_runt; /* # of short frames */ 123 124 u64 rx_frames_64; /* # of Rx frames in a particular range */ 125 u64 rx_frames_65_127; 126 u64 rx_frames_128_255; 127 u64 rx_frames_256_511; 128 u64 rx_frames_512_1023; 129 u64 rx_frames_1024_1518; 130 u64 rx_frames_1519_max; 131 132 u64 rx_pause; /* # of received pause frames */ 133 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 134 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 135 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 136 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 137 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 138 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 139 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 140 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 141 142 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 143 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 144 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 145 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 146 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 147 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 148 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 149 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 150}; 151 152struct lb_port_stats { 153 u64 octets; 154 u64 frames; 155 u64 bcast_frames; 156 u64 mcast_frames; 157 u64 ucast_frames; 158 u64 error_frames; 159 160 u64 frames_64; 161 u64 frames_65_127; 162 u64 frames_128_255; 163 u64 frames_256_511; 164 u64 frames_512_1023; 165 u64 frames_1024_1518; 166 u64 frames_1519_max; 167 168 u64 drop; 169 170 u64 ovflow0; 171 u64 ovflow1; 172 u64 ovflow2; 173 u64 ovflow3; 174 u64 trunc0; 175 u64 trunc1; 176 u64 trunc2; 177 u64 trunc3; 178}; 179 180struct tp_tcp_stats { 181 u32 tcpOutRsts; 182 u64 tcpInSegs; 183 u64 tcpOutSegs; 184 u64 tcpRetransSegs; 185}; 186 187struct tp_usm_stats { 188 u32 frames; 189 u32 drops; 190 u64 octets; 191}; 192 193struct tp_fcoe_stats { 194 u32 framesDDP; 195 u32 framesDrop; 196 u64 octetsDDP; 197}; 198 199struct tp_err_stats { 200 u32 macInErrs[4]; 201 u32 hdrInErrs[4]; 202 u32 tcpInErrs[4]; 203 u32 tnlCongDrops[4]; 204 u32 ofldChanDrops[4]; 205 u32 tnlTxDrops[4]; 206 u32 ofldVlanDrops[4]; 207 u32 tcp6InErrs[4]; 208 u32 ofldNoNeigh; 209 u32 ofldCongDefer; 210}; 211 212struct tp_proxy_stats { 213 u32 proxy[4]; 214}; 215 216struct tp_cpl_stats { 217 u32 req[4]; 218 u32 rsp[4]; 219}; 220 221struct tp_rdma_stats { 222 u32 rqe_dfr_mod; 223 u32 rqe_dfr_pkt; 224}; 225 226struct tp_params { 227 unsigned int ntxchan; /* # of Tx channels */ 228 unsigned int tre; /* log2 of core clocks per TP tick */ 229 unsigned int dack_re; /* DACK timer resolution */ 230 unsigned int la_mask; /* what events are recorded by TP LA */ 231 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 232}; 233 234struct vpd_params { 235 unsigned int cclk; 236 u8 ec[EC_LEN + 1]; 237 u8 sn[SERNUM_LEN + 1]; 238 u8 id[ID_LEN + 1]; 239 u8 pn[PN_LEN + 1]; 240 u8 na[MACADDR_LEN + 1]; 241}; 242 243struct pci_params { 244 unsigned int vpd_cap_addr; 245 unsigned short speed; 246 unsigned short width; 247}; 248 249/* 250 * Firmware device log. 251 */ 252struct devlog_params { 253 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 254 u32 start; /* start of log in firmware memory */ 255 u32 size; /* size of log */ 256}; 257 258struct adapter_params { 259 struct tp_params tp; 260 struct vpd_params vpd; 261 struct pci_params pci; 262 struct devlog_params devlog; 263 264 unsigned int sf_size; /* serial flash size in bytes */ 265 unsigned int sf_nsec; /* # of flash sectors */ 266 267 unsigned int fw_vers; 268 unsigned int tp_vers; 269 270 unsigned short mtus[NMTUS]; 271 unsigned short a_wnd[NCCTRL_WIN]; 272 unsigned short b_wnd[NCCTRL_WIN]; 273 274 unsigned int mc_size; /* MC memory size */ 275 unsigned int nfilters; /* size of filter region */ 276 277 unsigned int cim_la_size; 278 279 uint8_t nports; /* # of ethernet ports */ 280 uint8_t portvec; 281 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */ 282 unsigned int rev:4; /* chip revision */ 283 unsigned int fpga:1; /* this is an FPGA */ 284 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card 285 resources for TOE operation. */ 286 unsigned int bypass:1; /* this is a bypass card */ 287 288 unsigned int ofldq_wr_cred; 289}; 290 291#define CHELSIO_T4 0x4 292#define CHELSIO_T5 0x5 293 294struct trace_params { 295 u32 data[TRACE_LEN / 4]; 296 u32 mask[TRACE_LEN / 4]; 297 unsigned short snap_len; 298 unsigned short min_len; 299 unsigned char skip_ofst; 300 unsigned char skip_len; 301 unsigned char invert; 302 unsigned char port; 303}; 304 305struct link_config { 306 unsigned short supported; /* link capabilities */ 307 unsigned short advertising; /* advertised capabilities */ 308 unsigned short requested_speed; /* speed user has requested */ 309 unsigned short speed; /* actual link speed */ 310 unsigned char requested_fc; /* flow control user has requested */ 311 unsigned char fc; /* actual link flow control */ 312 unsigned char autoneg; /* autonegotiating? */ 313 unsigned char link_ok; /* link up? */ 314}; 315 316#include "adapter.h" 317 318#ifndef PCI_VENDOR_ID_CHELSIO 319# define PCI_VENDOR_ID_CHELSIO 0x1425 320#endif 321 322#define for_each_port(adapter, iter) \ 323 for (iter = 0; iter < (adapter)->params.nports; ++iter) 324 325static inline int is_offload(const struct adapter *adap) 326{ 327 return adap->params.offload; 328} 329 330static inline int chip_id(struct adapter *adap) 331{ 332 return adap->params.chipid; 333} 334 335static inline int chip_rev(struct adapter *adap) 336{ 337 return adap->params.rev; 338} 339 340static inline int is_t4(struct adapter *adap) 341{ 342 return adap->params.chipid == CHELSIO_T4; 343} 344 345static inline int is_t5(struct adapter *adap) 346{ 347 return adap->params.chipid == CHELSIO_T5; 348} 349 350static inline int is_fpga(struct adapter *adap) 351{ 352 return adap->params.fpga; 353} 354 355static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 356{ 357 return adap->params.vpd.cclk / 1000; 358} 359 360static inline unsigned int us_to_core_ticks(const struct adapter *adap, 361 unsigned int us) 362{ 363 return (us * adap->params.vpd.cclk) / 1000; 364} 365 366static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 367 unsigned int ticks) 368{ 369 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 370} 371 372void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val); 373int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, int polarity, 374 int attempts, int delay, u32 *valp); 375 376static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 377 int polarity, int attempts, int delay) 378{ 379 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 380 delay, NULL); 381} 382 383int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 384 void *rpl, bool sleep_ok); 385 386static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 387 int size, void *rpl) 388{ 389 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 390} 391 392static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 393 int size, void *rpl) 394{ 395 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 396} 397 398void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 399 unsigned int data_reg, u32 *vals, unsigned int nregs, 400 unsigned int start_idx); 401void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 402 unsigned int data_reg, const u32 *vals, 403 unsigned int nregs, unsigned int start_idx); 404 405u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg); 406 407struct fw_filter_wr; 408 409void t4_intr_enable(struct adapter *adapter); 410void t4_intr_disable(struct adapter *adapter); 411void t4_intr_clear(struct adapter *adapter); 412int t4_slow_intr_handler(struct adapter *adapter); 413 414int t4_hash_mac_addr(const u8 *addr); 415int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, 416 struct link_config *lc); 417int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 418int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 419int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 420int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 421int t4_seeprom_wp(struct adapter *adapter, int enable); 422int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, 423 u32 *data, int byte_oriented); 424int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 425int t4_load_boot(struct adapter *adap, u8 *boot_data, 426 unsigned int boot_addr, unsigned int size); 427int t4_flash_cfg_addr(struct adapter *adapter); 428int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 429int t4_get_fw_version(struct adapter *adapter, u32 *vers); 430int t4_get_tp_version(struct adapter *adapter, u32 *vers); 431int t4_check_fw_version(struct adapter *adapter); 432int t4_init_hw(struct adapter *adapter, u32 fw_params); 433int t4_prep_adapter(struct adapter *adapter); 434int t4_port_init(struct port_info *p, int mbox, int pf, int vf); 435int t4_reinit_adapter(struct adapter *adap); 436void t4_fatal_err(struct adapter *adapter); 437int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 438 int filter_index, int enable); 439void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 440 int filter_index, int *enabled); 441int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 442 int start, int n, const u16 *rspq, unsigned int nrspq); 443int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 444 unsigned int flags); 445int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 446 unsigned int flags, unsigned int defq); 447int t4_read_rss(struct adapter *adapter, u16 *entries); 448void t4_read_rss_key(struct adapter *adapter, u32 *key); 449void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 450void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, u32 *valp); 451void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, u32 val); 452void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 453 u32 *vfl, u32 *vfh); 454void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 455 u32 vfl, u32 vfh); 456u32 t4_read_rss_pf_map(struct adapter *adapter); 457void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap); 458u32 t4_read_rss_pf_mask(struct adapter *adapter); 459void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask); 460int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 461void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 462void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 463void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 464int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 465int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 466int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 467 unsigned int *valp); 468int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 469 const unsigned int *valp); 470int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 471 unsigned int *valp); 472int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 473void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 474 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); 475void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 476int t4_mc_read(struct adapter *adap, int idx, u32 addr, 477 __be32 *data, u64 *parity); 478int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); 479int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, 480 __be32 *data); 481 482void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 483void t4_get_port_stats_offset(struct adapter *adap, int idx, 484 struct port_stats *stats, 485 struct port_stats *offset); 486void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 487void t4_clr_port_stats(struct adapter *adap, int idx); 488 489void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 490void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 491void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 492void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 493 unsigned int *ipg); 494void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 495 unsigned int mask, unsigned int val); 496void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 497void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 498void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st); 499void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 500void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 501void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 502void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 503 struct tp_tcp_stats *v6); 504void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 505 struct tp_fcoe_stats *st); 506void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 507 const unsigned short *alpha, const unsigned short *beta); 508 509void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 510 511int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps); 512int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg); 513int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 514 unsigned int start, unsigned int n); 515void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 516int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map); 517void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 518 519void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr); 520int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 521 u64 mask0, u64 mask1, unsigned int crc, bool enable); 522 523int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 524 enum dev_master master, enum dev_state *state); 525int t4_fw_bye(struct adapter *adap, unsigned int mbox); 526int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 527int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force); 528int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 529int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 530 const u8 *fw_data, unsigned int size, int force); 531int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 532int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 533 unsigned int vf, unsigned int nparams, const u32 *params, 534 u32 *val); 535int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 536 unsigned int vf, unsigned int nparams, const u32 *params, 537 const u32 *val); 538int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 539 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 540 unsigned int rxqi, unsigned int rxq, unsigned int tc, 541 unsigned int vi, unsigned int cmask, unsigned int pmask, 542 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); 543int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 544 unsigned int port, unsigned int pf, unsigned int vf, 545 unsigned int nmac, u8 *mac, unsigned int *rss_size, 546 unsigned int portfunc, unsigned int idstype); 547int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 548 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 549 unsigned int *rss_size); 550int t4_free_vi(struct adapter *adap, unsigned int mbox, 551 unsigned int pf, unsigned int vf, 552 unsigned int viid); 553int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 554 int mtu, int promisc, int all_multi, int bcast, int vlanex, 555 bool sleep_ok); 556int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, 557 bool free, unsigned int naddr, const u8 **addr, u16 *idx, 558 u64 *hash, bool sleep_ok); 559int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 560 int idx, const u8 *addr, bool persist, bool add_smt); 561int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 562 bool ucast, u64 vec, bool sleep_ok); 563int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 564 bool rx_en, bool tx_en); 565int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 566 unsigned int nblinks); 567int t4_i2c_rd(struct adapter *adap, unsigned int mbox, unsigned int port_id, 568 u8 dev_addr, u8 offset, u8 *valp); 569int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 570 unsigned int mmd, unsigned int reg, unsigned int *valp); 571int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 572 unsigned int mmd, unsigned int reg, unsigned int val); 573int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start, 574 unsigned int pf, unsigned int vf, unsigned int iqid, 575 unsigned int fl0id, unsigned int fl1id); 576int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 577 unsigned int vf, unsigned int iqtype, unsigned int iqid, 578 unsigned int fl0id, unsigned int fl1id); 579int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 580 unsigned int vf, unsigned int eqid); 581int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 582 unsigned int vf, unsigned int eqid); 583int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 584 unsigned int vf, unsigned int eqid); 585int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 586 enum ctxt_type ctype, u32 *data); 587int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 588 u32 *data); 589int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 590int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 591int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val); 592#endif /* __CHELSIO_COMMON_H */ 593