1255736Sdavidch/*- 2265796Sdavidcs * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 3255736Sdavidch * 4255736Sdavidch * Redistribution and use in source and binary forms, with or without 5255736Sdavidch * modification, are permitted provided that the following conditions 6255736Sdavidch * are met: 7255736Sdavidch * 8255736Sdavidch * 1. Redistributions of source code must retain the above copyright 9255736Sdavidch * notice, this list of conditions and the following disclaimer. 10255736Sdavidch * 2. Redistributions in binary form must reproduce the above copyright 11255736Sdavidch * notice, this list of conditions and the following disclaimer in the 12255736Sdavidch * documentation and/or other materials provided with the distribution. 13255736Sdavidch * 14255736Sdavidch * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 15255736Sdavidch * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16255736Sdavidch * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17255736Sdavidch * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18255736Sdavidch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19255736Sdavidch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20255736Sdavidch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21255736Sdavidch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22255736Sdavidch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23255736Sdavidch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24255736Sdavidch * THE POSSIBILITY OF SUCH DAMAGE. 25255736Sdavidch */ 26255736Sdavidch 27255736Sdavidch#include <sys/cdefs.h> 28255736Sdavidch__FBSDID("$FreeBSD$"); 29255736Sdavidch 30255736Sdavidch#ifndef ECORE_HSI_H 31255736Sdavidch#define ECORE_HSI_H 32255736Sdavidch 33255736Sdavidch#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 34255736Sdavidch 35255736Sdavidchstruct license_key { 36255736Sdavidch uint32_t reserved[6]; 37255736Sdavidch 38255736Sdavidch uint32_t max_iscsi_conn; 39255736Sdavidch#define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 40255736Sdavidch#define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0 41255736Sdavidch#define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 42255736Sdavidch#define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16 43255736Sdavidch 44255736Sdavidch uint32_t reserved_a; 45255736Sdavidch 46255736Sdavidch uint32_t max_fcoe_conn; 47255736Sdavidch#define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 48255736Sdavidch#define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0 49255736Sdavidch#define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 50255736Sdavidch#define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16 51255736Sdavidch 52255736Sdavidch uint32_t reserved_b[4]; 53255736Sdavidch}; 54255736Sdavidch 55255736Sdavidchtypedef struct license_key license_key_t; 56255736Sdavidch 57255736Sdavidch 58255736Sdavidch/**************************************************************************** 59255736Sdavidch * Shared HW configuration * 60255736Sdavidch ****************************************************************************/ 61255736Sdavidch#define PIN_CFG_NA 0x00000000 62255736Sdavidch#define PIN_CFG_GPIO0_P0 0x00000001 63255736Sdavidch#define PIN_CFG_GPIO1_P0 0x00000002 64255736Sdavidch#define PIN_CFG_GPIO2_P0 0x00000003 65255736Sdavidch#define PIN_CFG_GPIO3_P0 0x00000004 66255736Sdavidch#define PIN_CFG_GPIO0_P1 0x00000005 67255736Sdavidch#define PIN_CFG_GPIO1_P1 0x00000006 68255736Sdavidch#define PIN_CFG_GPIO2_P1 0x00000007 69255736Sdavidch#define PIN_CFG_GPIO3_P1 0x00000008 70255736Sdavidch#define PIN_CFG_EPIO0 0x00000009 71255736Sdavidch#define PIN_CFG_EPIO1 0x0000000a 72255736Sdavidch#define PIN_CFG_EPIO2 0x0000000b 73255736Sdavidch#define PIN_CFG_EPIO3 0x0000000c 74255736Sdavidch#define PIN_CFG_EPIO4 0x0000000d 75255736Sdavidch#define PIN_CFG_EPIO5 0x0000000e 76255736Sdavidch#define PIN_CFG_EPIO6 0x0000000f 77255736Sdavidch#define PIN_CFG_EPIO7 0x00000010 78255736Sdavidch#define PIN_CFG_EPIO8 0x00000011 79255736Sdavidch#define PIN_CFG_EPIO9 0x00000012 80255736Sdavidch#define PIN_CFG_EPIO10 0x00000013 81255736Sdavidch#define PIN_CFG_EPIO11 0x00000014 82255736Sdavidch#define PIN_CFG_EPIO12 0x00000015 83255736Sdavidch#define PIN_CFG_EPIO13 0x00000016 84255736Sdavidch#define PIN_CFG_EPIO14 0x00000017 85255736Sdavidch#define PIN_CFG_EPIO15 0x00000018 86255736Sdavidch#define PIN_CFG_EPIO16 0x00000019 87255736Sdavidch#define PIN_CFG_EPIO17 0x0000001a 88255736Sdavidch#define PIN_CFG_EPIO18 0x0000001b 89255736Sdavidch#define PIN_CFG_EPIO19 0x0000001c 90255736Sdavidch#define PIN_CFG_EPIO20 0x0000001d 91255736Sdavidch#define PIN_CFG_EPIO21 0x0000001e 92255736Sdavidch#define PIN_CFG_EPIO22 0x0000001f 93255736Sdavidch#define PIN_CFG_EPIO23 0x00000020 94255736Sdavidch#define PIN_CFG_EPIO24 0x00000021 95255736Sdavidch#define PIN_CFG_EPIO25 0x00000022 96255736Sdavidch#define PIN_CFG_EPIO26 0x00000023 97255736Sdavidch#define PIN_CFG_EPIO27 0x00000024 98255736Sdavidch#define PIN_CFG_EPIO28 0x00000025 99255736Sdavidch#define PIN_CFG_EPIO29 0x00000026 100255736Sdavidch#define PIN_CFG_EPIO30 0x00000027 101255736Sdavidch#define PIN_CFG_EPIO31 0x00000028 102255736Sdavidch 103255736Sdavidch/* EPIO definition */ 104255736Sdavidch#define EPIO_CFG_NA 0x00000000 105255736Sdavidch#define EPIO_CFG_EPIO0 0x00000001 106255736Sdavidch#define EPIO_CFG_EPIO1 0x00000002 107255736Sdavidch#define EPIO_CFG_EPIO2 0x00000003 108255736Sdavidch#define EPIO_CFG_EPIO3 0x00000004 109255736Sdavidch#define EPIO_CFG_EPIO4 0x00000005 110255736Sdavidch#define EPIO_CFG_EPIO5 0x00000006 111255736Sdavidch#define EPIO_CFG_EPIO6 0x00000007 112255736Sdavidch#define EPIO_CFG_EPIO7 0x00000008 113255736Sdavidch#define EPIO_CFG_EPIO8 0x00000009 114255736Sdavidch#define EPIO_CFG_EPIO9 0x0000000a 115255736Sdavidch#define EPIO_CFG_EPIO10 0x0000000b 116255736Sdavidch#define EPIO_CFG_EPIO11 0x0000000c 117255736Sdavidch#define EPIO_CFG_EPIO12 0x0000000d 118255736Sdavidch#define EPIO_CFG_EPIO13 0x0000000e 119255736Sdavidch#define EPIO_CFG_EPIO14 0x0000000f 120255736Sdavidch#define EPIO_CFG_EPIO15 0x00000010 121255736Sdavidch#define EPIO_CFG_EPIO16 0x00000011 122255736Sdavidch#define EPIO_CFG_EPIO17 0x00000012 123255736Sdavidch#define EPIO_CFG_EPIO18 0x00000013 124255736Sdavidch#define EPIO_CFG_EPIO19 0x00000014 125255736Sdavidch#define EPIO_CFG_EPIO20 0x00000015 126255736Sdavidch#define EPIO_CFG_EPIO21 0x00000016 127255736Sdavidch#define EPIO_CFG_EPIO22 0x00000017 128255736Sdavidch#define EPIO_CFG_EPIO23 0x00000018 129255736Sdavidch#define EPIO_CFG_EPIO24 0x00000019 130255736Sdavidch#define EPIO_CFG_EPIO25 0x0000001a 131255736Sdavidch#define EPIO_CFG_EPIO26 0x0000001b 132255736Sdavidch#define EPIO_CFG_EPIO27 0x0000001c 133255736Sdavidch#define EPIO_CFG_EPIO28 0x0000001d 134255736Sdavidch#define EPIO_CFG_EPIO29 0x0000001e 135255736Sdavidch#define EPIO_CFG_EPIO30 0x0000001f 136255736Sdavidch#define EPIO_CFG_EPIO31 0x00000020 137255736Sdavidch 138255736Sdavidchstruct mac_addr { 139255736Sdavidch uint32_t upper; 140255736Sdavidch uint32_t lower; 141255736Sdavidch}; 142255736Sdavidch 143255736Sdavidch 144255736Sdavidchstruct shared_hw_cfg { /* NVRAM Offset */ 145255736Sdavidch /* Up to 16 bytes of NULL-terminated string */ 146255736Sdavidch uint8_t part_num[16]; /* 0x104 */ 147255736Sdavidch 148255736Sdavidch uint32_t config; /* 0x114 */ 149255736Sdavidch #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 150255736Sdavidch #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 151255736Sdavidch #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 152255736Sdavidch #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 153255736Sdavidch 154255736Sdavidch #define SHARED_HW_CFG_PORT_SWAP 0x00000004 155255736Sdavidch 156255736Sdavidch #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 157255736Sdavidch 158255736Sdavidch #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 159255736Sdavidch #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 160255736Sdavidch 161255736Sdavidch #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 162255736Sdavidch #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 163255736Sdavidch /* Whatever MFW found in NVM 164255736Sdavidch (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 165255736Sdavidch #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 166255736Sdavidch #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 167255736Sdavidch #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 168255736Sdavidch #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 169255736Sdavidch /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 170255736Sdavidch (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 171255736Sdavidch #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 172255736Sdavidch /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 173255736Sdavidch (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 174255736Sdavidch #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 175255736Sdavidch /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 176255736Sdavidch (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 177255736Sdavidch #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 178255736Sdavidch 179255736Sdavidch /* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For 180255736Sdavidch backwards compatibility, value of 0 is disabling this feature. 181255736Sdavidch That means that though 0 is a valid value, it cannot be 182255736Sdavidch configured. */ 183255736Sdavidch #define SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000 184255736Sdavidch #define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT 12 185255736Sdavidch 186255736Sdavidch #define SHARED_HW_CFG_LED_MODE_MASK 0x000F0000 187255736Sdavidch #define SHARED_HW_CFG_LED_MODE_SHIFT 16 188255736Sdavidch #define SHARED_HW_CFG_LED_MAC1 0x00000000 189255736Sdavidch #define SHARED_HW_CFG_LED_PHY1 0x00010000 190255736Sdavidch #define SHARED_HW_CFG_LED_PHY2 0x00020000 191255736Sdavidch #define SHARED_HW_CFG_LED_PHY3 0x00030000 192255736Sdavidch #define SHARED_HW_CFG_LED_MAC2 0x00040000 193255736Sdavidch #define SHARED_HW_CFG_LED_PHY4 0x00050000 194255736Sdavidch #define SHARED_HW_CFG_LED_PHY5 0x00060000 195255736Sdavidch #define SHARED_HW_CFG_LED_PHY6 0x00070000 196255736Sdavidch #define SHARED_HW_CFG_LED_MAC3 0x00080000 197255736Sdavidch #define SHARED_HW_CFG_LED_PHY7 0x00090000 198255736Sdavidch #define SHARED_HW_CFG_LED_PHY9 0x000a0000 199255736Sdavidch #define SHARED_HW_CFG_LED_PHY11 0x000b0000 200255736Sdavidch #define SHARED_HW_CFG_LED_MAC4 0x000c0000 201255736Sdavidch #define SHARED_HW_CFG_LED_PHY8 0x000d0000 202255736Sdavidch #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 203255736Sdavidch #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000 204255736Sdavidch 205255736Sdavidch #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 206255736Sdavidch #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 207255736Sdavidch #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 208255736Sdavidch 209255736Sdavidch #define SHARED_HW_CFG_ATC_MASK 0x80000000 210255736Sdavidch #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 211255736Sdavidch #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 212255736Sdavidch 213255736Sdavidch uint32_t config2; /* 0x118 */ 214255736Sdavidch 215255736Sdavidch #define SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100 216255736Sdavidch #define SHARED_HW_CFG_PCIE_GEN2_SHIFT 8 217255736Sdavidch #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 218255736Sdavidch #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 219255736Sdavidch 220255736Sdavidch #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 221255736Sdavidch #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 222255736Sdavidch #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 223255736Sdavidch 224255736Sdavidch #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 225255736Sdavidch 226255736Sdavidch 227255736Sdavidch /* Output low when PERST is asserted */ 228255736Sdavidch #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 229255736Sdavidch #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 230255736Sdavidch #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 231255736Sdavidch 232255736Sdavidch #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 233255736Sdavidch #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 234255736Sdavidch #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 235255736Sdavidch #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 236255736Sdavidch #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 237255736Sdavidch #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 238255736Sdavidch 239255736Sdavidch /* The fan failure mechanism is usually related to the PHY type 240255736Sdavidch since the power consumption of the board is determined by the PHY. 241255736Sdavidch Currently, fan is required for most designs with SFX7101, BCM8727 242255736Sdavidch and BCM8481. If a fan is not required for a board which uses one 243255736Sdavidch of those PHYs, this field should be set to "Disabled". If a fan is 244255736Sdavidch required for a different PHY type, this option should be set to 245255736Sdavidch "Enabled". The fan failure indication is expected on SPIO5 */ 246255736Sdavidch #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 247255736Sdavidch #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 248255736Sdavidch #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 249255736Sdavidch #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 250255736Sdavidch #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 251255736Sdavidch 252255736Sdavidch /* ASPM Power Management support */ 253255736Sdavidch #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 254255736Sdavidch #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 255255736Sdavidch #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 256255736Sdavidch #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 257255736Sdavidch #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 258255736Sdavidch #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 259255736Sdavidch 260255736Sdavidch /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 261255736Sdavidch tl_control_0 (register 0x2800) */ 262255736Sdavidch #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 263255736Sdavidch #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 264255736Sdavidch #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 265255736Sdavidch 266255736Sdavidch 267255736Sdavidch /* Set the MDC/MDIO access for the first external phy */ 268255736Sdavidch #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 269255736Sdavidch #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 270255736Sdavidch #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 271255736Sdavidch #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 272255736Sdavidch #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 273255736Sdavidch #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 274255736Sdavidch #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 275255736Sdavidch 276255736Sdavidch /* Set the MDC/MDIO access for the second external phy */ 277255736Sdavidch #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 278255736Sdavidch #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 279255736Sdavidch #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 280255736Sdavidch #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 281255736Sdavidch #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 282255736Sdavidch #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 283255736Sdavidch #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 284255736Sdavidch 285255736Sdavidch /* Max number of PF MSIX vectors */ 286255736Sdavidch uint32_t config_3; /* 0x11C */ 287255736Sdavidch #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F 288255736Sdavidch #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0 289255736Sdavidch 290255736Sdavidch uint32_t ump_nc_si_config; /* 0x120 */ 291255736Sdavidch #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 292255736Sdavidch #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 293255736Sdavidch #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 294255736Sdavidch #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 295255736Sdavidch #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 296255736Sdavidch #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 297255736Sdavidch 298255736Sdavidch /* Reserved bits: 226-230 */ 299255736Sdavidch 300255736Sdavidch /* The output pin template BSC_SEL which selects the I2C for this 301255736Sdavidch port in the I2C Mux */ 302255736Sdavidch uint32_t board; /* 0x124 */ 303255736Sdavidch #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 304255736Sdavidch #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 305255736Sdavidch 306255736Sdavidch #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 307255736Sdavidch #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 308255736Sdavidch /* Use the PIN_CFG_XXX defines on top */ 309255736Sdavidch #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000 310255736Sdavidch #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 311255736Sdavidch 312255736Sdavidch #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000 313255736Sdavidch #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 314255736Sdavidch 315255736Sdavidch #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000 316255736Sdavidch #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 317255736Sdavidch 318255736Sdavidch uint32_t wc_lane_config; /* 0x128 */ 319255736Sdavidch #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 320255736Sdavidch #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 321255736Sdavidch #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 322255736Sdavidch #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 323255736Sdavidch #define SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8 324255736Sdavidch #define SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827 325255736Sdavidch #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 326255736Sdavidch #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 327255736Sdavidch #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 328255736Sdavidch #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 329255736Sdavidch #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 330255736Sdavidch #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 331255736Sdavidch 332255736Sdavidch /* TX lane Polarity swap */ 333255736Sdavidch #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 334255736Sdavidch #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 335255736Sdavidch #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 336255736Sdavidch #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 337255736Sdavidch /* TX lane Polarity swap */ 338255736Sdavidch #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 339255736Sdavidch #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 340255736Sdavidch #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 341255736Sdavidch #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 342255736Sdavidch 343255736Sdavidch /* Selects the port layout of the board */ 344255736Sdavidch #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 345255736Sdavidch #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 346255736Sdavidch #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 347255736Sdavidch #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 348255736Sdavidch #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 349255736Sdavidch #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 350255736Sdavidch #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 351255736Sdavidch #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 352255736Sdavidch}; 353255736Sdavidch 354255736Sdavidch 355255736Sdavidch/**************************************************************************** 356255736Sdavidch * Port HW configuration * 357255736Sdavidch ****************************************************************************/ 358255736Sdavidchstruct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 359255736Sdavidch 360255736Sdavidch uint32_t pci_id; 361255736Sdavidch #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF 362255736Sdavidch #define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0 363255736Sdavidch 364255736Sdavidch #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000 365255736Sdavidch #define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT 16 366255736Sdavidch 367255736Sdavidch uint32_t pci_sub_id; 368255736Sdavidch #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF 369255736Sdavidch #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0 370255736Sdavidch 371255736Sdavidch #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000 372255736Sdavidch #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT 16 373255736Sdavidch 374255736Sdavidch uint32_t power_dissipated; 375255736Sdavidch #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF 376255736Sdavidch #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 377255736Sdavidch #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00 378255736Sdavidch #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 379255736Sdavidch #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000 380255736Sdavidch #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 381255736Sdavidch #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000 382255736Sdavidch #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 383255736Sdavidch 384255736Sdavidch uint32_t power_consumed; 385255736Sdavidch #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF 386255736Sdavidch #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 387255736Sdavidch #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00 388255736Sdavidch #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 389255736Sdavidch #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000 390255736Sdavidch #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 391255736Sdavidch #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000 392255736Sdavidch #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 393255736Sdavidch 394255736Sdavidch uint32_t mac_upper; 395255736Sdavidch uint32_t mac_lower; /* 0x140 */ 396255736Sdavidch #define PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF 397255736Sdavidch #define PORT_HW_CFG_UPPERMAC_SHIFT 0 398255736Sdavidch 399255736Sdavidch 400255736Sdavidch uint32_t iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 401255736Sdavidch uint32_t iscsi_mac_lower; 402255736Sdavidch 403255736Sdavidch uint32_t rdma_mac_upper; /* Upper 16 bits are always zeroes */ 404255736Sdavidch uint32_t rdma_mac_lower; 405255736Sdavidch 406255736Sdavidch uint32_t serdes_config; 407255736Sdavidch #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF 408255736Sdavidch #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 409255736Sdavidch 410255736Sdavidch #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000 411255736Sdavidch #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 412255736Sdavidch 413255736Sdavidch 414255736Sdavidch /* Default values: 2P-64, 4P-32 */ 415255736Sdavidch uint32_t reserved; 416255736Sdavidch 417255736Sdavidch uint32_t vf_config; /* 0x15C */ 418255736Sdavidch #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 419255736Sdavidch #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 420255736Sdavidch 421255736Sdavidch uint32_t mf_pci_id; /* 0x160 */ 422255736Sdavidch #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 423255736Sdavidch #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 424255736Sdavidch 425255736Sdavidch /* Controls the TX laser of the SFP+ module */ 426255736Sdavidch uint32_t sfp_ctrl; /* 0x164 */ 427255736Sdavidch #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 428255736Sdavidch #define PORT_HW_CFG_TX_LASER_SHIFT 0 429255736Sdavidch #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 430255736Sdavidch #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 431255736Sdavidch #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 432255736Sdavidch #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 433255736Sdavidch #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 434255736Sdavidch 435255736Sdavidch /* Controls the fault module LED of the SFP+ */ 436255736Sdavidch #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 437255736Sdavidch #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 438255736Sdavidch #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 439255736Sdavidch #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 440255736Sdavidch #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 441255736Sdavidch #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 442255736Sdavidch #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 443255736Sdavidch 444255736Sdavidch /* The output pin TX_DIS that controls the TX laser of the SFP+ 445255736Sdavidch module. Use the PIN_CFG_XXX defines on top */ 446255736Sdavidch uint32_t e3_sfp_ctrl; /* 0x168 */ 447255736Sdavidch #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 448255736Sdavidch #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 449255736Sdavidch 450255736Sdavidch /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 451255736Sdavidch #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 452255736Sdavidch #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 453255736Sdavidch 454255736Sdavidch /* The input pin MOD_ABS that indicates whether SFP+ module is 455255736Sdavidch present or not. Use the PIN_CFG_XXX defines on top */ 456255736Sdavidch #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 457255736Sdavidch #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 458255736Sdavidch 459255736Sdavidch /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 460255736Sdavidch module. Use the PIN_CFG_XXX defines on top */ 461255736Sdavidch #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 462255736Sdavidch #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 463255736Sdavidch 464255736Sdavidch /* 465255736Sdavidch * The input pin which signals module transmit fault. Use the 466255736Sdavidch * PIN_CFG_XXX defines on top 467255736Sdavidch */ 468255736Sdavidch uint32_t e3_cmn_pin_cfg; /* 0x16C */ 469255736Sdavidch #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 470255736Sdavidch #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 471255736Sdavidch 472255736Sdavidch /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 473255736Sdavidch top */ 474255736Sdavidch #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 475255736Sdavidch #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 476255736Sdavidch 477255736Sdavidch /* 478255736Sdavidch * The output pin which powers down the PHY. Use the PIN_CFG_XXX 479255736Sdavidch * defines on top 480255736Sdavidch */ 481255736Sdavidch #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 482255736Sdavidch #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 483255736Sdavidch 484255736Sdavidch /* The output pin values BSC_SEL which selects the I2C for this port 485255736Sdavidch in the I2C Mux */ 486255736Sdavidch #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 487255736Sdavidch #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 488255736Sdavidch 489255736Sdavidch 490255736Sdavidch /* 491255736Sdavidch * The input pin I_FAULT which indicate over-current has occurred. 492255736Sdavidch * Use the PIN_CFG_XXX defines on top 493255736Sdavidch */ 494255736Sdavidch uint32_t e3_cmn_pin_cfg1; /* 0x170 */ 495255736Sdavidch #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 496255736Sdavidch #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 497255736Sdavidch 498255736Sdavidch /* pause on host ring */ 499255736Sdavidch uint32_t generic_features; /* 0x174 */ 500255736Sdavidch #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 501255736Sdavidch #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 502255736Sdavidch #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 503255736Sdavidch #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 504255736Sdavidch 505255736Sdavidch /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 506255736Sdavidch * LOM recommended and tested value is 0xBEB2. Using a different 507255736Sdavidch * value means using a value not tested by BRCM 508255736Sdavidch */ 509255736Sdavidch uint32_t sfi_tap_values; /* 0x178 */ 510255736Sdavidch #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF 511255736Sdavidch #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 512255736Sdavidch 513255736Sdavidch /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested 514255736Sdavidch * value is 0x2. LOM recommended and tested value is 0x2. Using a 515255736Sdavidch * different value means using a value not tested by BRCM 516255736Sdavidch */ 517255736Sdavidch #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 518255736Sdavidch #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 519255736Sdavidch 520255736Sdavidch uint32_t reserved0[5]; /* 0x17c */ 521255736Sdavidch 522255736Sdavidch uint32_t aeu_int_mask; /* 0x190 */ 523255736Sdavidch 524255736Sdavidch uint32_t media_type; /* 0x194 */ 525255736Sdavidch #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 526255736Sdavidch #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 527255736Sdavidch 528255736Sdavidch #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 529255736Sdavidch #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 530255736Sdavidch 531255736Sdavidch #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 532255736Sdavidch #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 533255736Sdavidch 534255736Sdavidch /* 4 times 16 bits for all 4 lanes. In case external PHY is present 535255736Sdavidch (not direct mode), those values will not take effect on the 4 XGXS 536255736Sdavidch lanes. For some external PHYs (such as 8706 and 8726) the values 537255736Sdavidch will be used to configure the external PHY in those cases, not 538255736Sdavidch all 4 values are needed. */ 539255736Sdavidch uint16_t xgxs_config_rx[4]; /* 0x198 */ 540255736Sdavidch uint16_t xgxs_config_tx[4]; /* 0x1A0 */ 541255736Sdavidch 542255736Sdavidch 543255736Sdavidch /* For storing FCOE mac on shared memory */ 544255736Sdavidch uint32_t fcoe_fip_mac_upper; 545255736Sdavidch #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 546255736Sdavidch #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 547255736Sdavidch uint32_t fcoe_fip_mac_lower; 548255736Sdavidch 549255736Sdavidch uint32_t fcoe_wwn_port_name_upper; 550255736Sdavidch uint32_t fcoe_wwn_port_name_lower; 551255736Sdavidch 552255736Sdavidch uint32_t fcoe_wwn_node_name_upper; 553255736Sdavidch uint32_t fcoe_wwn_node_name_lower; 554255736Sdavidch 555255736Sdavidch /* wwpn for npiv enabled */ 556255736Sdavidch uint32_t wwpn_for_npiv_config; /* 0x1C0 */ 557255736Sdavidch #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001 558255736Sdavidch #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0 559255736Sdavidch #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000 560255736Sdavidch #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001 561255736Sdavidch 562255736Sdavidch /* wwpn for npiv valid addresses */ 563255736Sdavidch uint32_t wwpn_for_npiv_valid_addresses; /* 0x1C4 */ 564255736Sdavidch #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF 565255736Sdavidch #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0 566255736Sdavidch 567255736Sdavidch struct mac_addr wwpn_for_niv_macs[16]; 568255736Sdavidch 569255736Sdavidch /* Reserved bits: 2272-2336 For storing FCOE mac on shared memory */ 570255736Sdavidch uint32_t Reserved1[14]; 571255736Sdavidch 572255736Sdavidch uint32_t pf_allocation; /* 0x280 */ 573255736Sdavidch /* number of vfs per PF, if 0 - sriov disabled */ 574255736Sdavidch #define PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF 575255736Sdavidch #define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0 576255736Sdavidch 577255736Sdavidch /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 578255736Sdavidch 84833 only */ 579255736Sdavidch uint32_t xgbt_phy_cfg; /* 0x284 */ 580255736Sdavidch #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 581255736Sdavidch #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 582255736Sdavidch 583255736Sdavidch uint32_t default_cfg; /* 0x288 */ 584255736Sdavidch #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 585255736Sdavidch #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 586255736Sdavidch #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 587255736Sdavidch #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 588255736Sdavidch #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 589255736Sdavidch #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 590255736Sdavidch 591255736Sdavidch #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 592255736Sdavidch #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 593255736Sdavidch #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 594255736Sdavidch #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 595255736Sdavidch #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 596255736Sdavidch #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 597255736Sdavidch 598255736Sdavidch #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 599255736Sdavidch #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 600255736Sdavidch #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 601255736Sdavidch #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 602255736Sdavidch #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 603255736Sdavidch #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 604255736Sdavidch 605255736Sdavidch #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 606255736Sdavidch #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 607255736Sdavidch #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 608255736Sdavidch #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 609255736Sdavidch #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 610255736Sdavidch #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 611255736Sdavidch 612255736Sdavidch /* When KR link is required to be set to force which is not 613255736Sdavidch KR-compliant, this parameter determine what is the trigger for it. 614255736Sdavidch When GPIO is selected, low input will force the speed. Currently 615255736Sdavidch default speed is 1G. In the future, it may be widen to select the 616255736Sdavidch forced speed in with another parameter. Note when force-1G is 617255736Sdavidch enabled, it override option 56: Link Speed option. */ 618255736Sdavidch #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 619255736Sdavidch #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 620255736Sdavidch #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 621255736Sdavidch #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 622255736Sdavidch #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 623255736Sdavidch #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 624255736Sdavidch #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 625255736Sdavidch #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 626255736Sdavidch #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 627255736Sdavidch #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 628255736Sdavidch #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 629255736Sdavidch #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 630255736Sdavidch /* Enable to determine with which GPIO to reset the external phy */ 631255736Sdavidch #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 632255736Sdavidch #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 633255736Sdavidch #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 634255736Sdavidch #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 635255736Sdavidch #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 636255736Sdavidch #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 637255736Sdavidch #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 638255736Sdavidch #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 639255736Sdavidch #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 640255736Sdavidch #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 641255736Sdavidch #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 642255736Sdavidch 643255736Sdavidch /* Enable BAM on KR */ 644255736Sdavidch #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 645255736Sdavidch #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 646255736Sdavidch #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 647255736Sdavidch #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 648255736Sdavidch 649255736Sdavidch /* Enable Common Mode Sense */ 650255736Sdavidch #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 651255736Sdavidch #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 652255736Sdavidch #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 653255736Sdavidch #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 654255736Sdavidch 655255736Sdavidch /* Determine the Serdes electrical interface */ 656255736Sdavidch #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 657255736Sdavidch #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 658255736Sdavidch #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 659255736Sdavidch #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 660255736Sdavidch #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 661255736Sdavidch #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 662255736Sdavidch #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 663255736Sdavidch #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 664255736Sdavidch 665255736Sdavidch /* SFP+ main TAP and post TAP volumes */ 666255736Sdavidch #define PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000 667255736Sdavidch #define PORT_HW_CFG_TAP_LEVELS_SHIFT 28 668255736Sdavidch #define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000 669255736Sdavidch #define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000 670255736Sdavidch #define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000 671255736Sdavidch #define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000 672255736Sdavidch #define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000 673255736Sdavidch #define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000 674255736Sdavidch 675255736Sdavidch uint32_t speed_capability_mask2; /* 0x28C */ 676255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 677255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 678255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 679255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002 680255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004 681255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 682255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 683255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020 684255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 685255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 686255736Sdavidch 687255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 688255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 689255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 690255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000 691255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000 692255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 693255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 694255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000 695255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 696255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 697255736Sdavidch 698255736Sdavidch 699255736Sdavidch /* In the case where two media types (e.g. copper and fiber) are 700255736Sdavidch present and electrically active at the same time, PHY Selection 701255736Sdavidch will determine which of the two PHYs will be designated as the 702255736Sdavidch Active PHY and used for a connection to the network. */ 703255736Sdavidch uint32_t multi_phy_config; /* 0x290 */ 704255736Sdavidch #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 705255736Sdavidch #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 706255736Sdavidch #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 707255736Sdavidch #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 708255736Sdavidch #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 709255736Sdavidch #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 710255736Sdavidch #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 711255736Sdavidch 712255736Sdavidch /* When enabled, all second phy nvram parameters will be swapped 713255736Sdavidch with the first phy parameters */ 714255736Sdavidch #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 715255736Sdavidch #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 716255736Sdavidch #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 717255736Sdavidch #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 718255736Sdavidch 719255736Sdavidch 720255736Sdavidch /* Address of the second external phy */ 721255736Sdavidch uint32_t external_phy_config2; /* 0x294 */ 722255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 723255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 724255736Sdavidch 725255736Sdavidch /* The second XGXS external PHY type */ 726255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 727255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 728255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 729255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 730255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 731255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 732255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 733255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 734255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 735255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 736255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 737255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 738255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 739255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 740255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 741255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 742255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 743255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 744255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 745255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100 746255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 747255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 748255736Sdavidch 749255736Sdavidch 750255736Sdavidch /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 751255736Sdavidch 8706, 8726 and 8727) not all 4 values are needed. */ 752255736Sdavidch uint16_t xgxs_config2_rx[4]; /* 0x296 */ 753255736Sdavidch uint16_t xgxs_config2_tx[4]; /* 0x2A0 */ 754255736Sdavidch 755255736Sdavidch uint32_t lane_config; 756255736Sdavidch #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 757255736Sdavidch #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 758255736Sdavidch /* AN and forced */ 759255736Sdavidch #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 760255736Sdavidch /* forced only */ 761255736Sdavidch #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 762255736Sdavidch /* forced only */ 763255736Sdavidch #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 764255736Sdavidch /* forced only */ 765255736Sdavidch #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 766255736Sdavidch #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 767255736Sdavidch #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 768255736Sdavidch #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 769255736Sdavidch #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 770255736Sdavidch #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000 771255736Sdavidch #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 772255736Sdavidch 773255736Sdavidch /* Indicate whether to swap the external phy polarity */ 774255736Sdavidch #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 775255736Sdavidch #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 776255736Sdavidch #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 777255736Sdavidch 778255736Sdavidch 779255736Sdavidch uint32_t external_phy_config; 780255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF 781255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 782255736Sdavidch 783255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00 784255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 785255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 786255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 787255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 788255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 789255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 790255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 791255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 792255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 793255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 794255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 795255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 796255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 797255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 798255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 799255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 800255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 801255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 802255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100 803255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 804255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 805255736Sdavidch #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 806255736Sdavidch 807255736Sdavidch #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000 808255736Sdavidch #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 809255736Sdavidch 810255736Sdavidch #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000 811255736Sdavidch #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 812255736Sdavidch #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 813255736Sdavidch #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 814255736Sdavidch #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 815255736Sdavidch #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 816255736Sdavidch 817255736Sdavidch uint32_t speed_capability_mask; 818255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF 819255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 820255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 821255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 822255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 823255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 824255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 825255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 826255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 827255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 828255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 829255736Sdavidch 830255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000 831255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 832255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 833255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 834255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 835255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 836255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 837255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 838255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 839255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 840255736Sdavidch #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 841255736Sdavidch 842255736Sdavidch /* A place to hold the original MAC address as a backup */ 843255736Sdavidch uint32_t backup_mac_upper; /* 0x2B4 */ 844255736Sdavidch uint32_t backup_mac_lower; /* 0x2B8 */ 845255736Sdavidch 846255736Sdavidch}; 847255736Sdavidch 848255736Sdavidch 849255736Sdavidch/**************************************************************************** 850255736Sdavidch * Shared Feature configuration * 851255736Sdavidch ****************************************************************************/ 852255736Sdavidchstruct shared_feat_cfg { /* NVRAM Offset */ 853255736Sdavidch 854255736Sdavidch uint32_t config; /* 0x450 */ 855255736Sdavidch #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 856255736Sdavidch 857255736Sdavidch /* Use NVRAM values instead of HW default values */ 858255736Sdavidch #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 859255736Sdavidch 0x00000002 860255736Sdavidch #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 861255736Sdavidch 0x00000000 862255736Sdavidch #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 863255736Sdavidch 0x00000002 864255736Sdavidch 865255736Sdavidch #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 866255736Sdavidch #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 867255736Sdavidch #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 868255736Sdavidch 869255736Sdavidch #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 870255736Sdavidch #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 871255736Sdavidch 872255736Sdavidch /* Override the OTP back to single function mode. When using GPIO, 873255736Sdavidch high means only SF, 0 is according to CLP configuration */ 874255736Sdavidch #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 875255736Sdavidch #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 876255736Sdavidch #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 877255736Sdavidch #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 878255736Sdavidch #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 879255736Sdavidch #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 880255736Sdavidch #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 881255736Sdavidch 882255736Sdavidch /* Act as if the FCoE license is invalid */ 883255736Sdavidch #define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000 884255736Sdavidch 885255736Sdavidch /* Force FLR capability to all ports */ 886255736Sdavidch #define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000 887255736Sdavidch 888255736Sdavidch /* Act as if the iSCSI license is invalid */ 889255736Sdavidch #define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000 890255736Sdavidch #define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT 14 891255736Sdavidch #define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000 892255736Sdavidch #define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000 893255736Sdavidch 894255736Sdavidch /* The interval in seconds between sending LLDP packets. Set to zero 895255736Sdavidch to disable the feature */ 896255736Sdavidch #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000 897255736Sdavidch #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 898255736Sdavidch 899255736Sdavidch /* The assigned device type ID for LLDP usage */ 900255736Sdavidch #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000 901255736Sdavidch #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 902255736Sdavidch 903255736Sdavidch}; 904255736Sdavidch 905255736Sdavidch 906255736Sdavidch/**************************************************************************** 907255736Sdavidch * Port Feature configuration * 908255736Sdavidch ****************************************************************************/ 909255736Sdavidchstruct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 910255736Sdavidch 911255736Sdavidch uint32_t config; 912255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F 913255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0 914255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000 915255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001 916255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002 917255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003 918255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004 919255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005 920255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006 921255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007 922255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008 923255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009 924255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a 925255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b 926255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c 927255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d 928255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e 929255736Sdavidch #define PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f 930255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0 931255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_SHIFT 4 932255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000 933255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010 934255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020 935255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030 936255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040 937255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050 938255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060 939255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070 940255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080 941255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090 942255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0 943255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0 944255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0 945255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0 946255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0 947255736Sdavidch #define PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0 948255736Sdavidch 949255736Sdavidch #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 950255736Sdavidch #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 951255736Sdavidch #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 952255736Sdavidch 953255736Sdavidch #define PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200 954255736Sdavidch #define PORT_FEAT_CFG_AUTOGREEEN_SHIFT 9 955255736Sdavidch #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000 956255736Sdavidch #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200 957255736Sdavidch 958255736Sdavidch #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 959255736Sdavidch #define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT 10 960255736Sdavidch #define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000 961255736Sdavidch #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 962255736Sdavidch #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 963255736Sdavidch #define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00 964255736Sdavidch 965255736Sdavidch #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 966255736Sdavidch #define PORT_FEATURE_EN_SIZE_SHIFT 24 967255736Sdavidch #define PORT_FEATURE_WOL_ENABLED 0x01000000 968255736Sdavidch #define PORT_FEATURE_MBA_ENABLED 0x02000000 969255736Sdavidch #define PORT_FEATURE_MFW_ENABLED 0x04000000 970255736Sdavidch 971255736Sdavidch /* Advertise expansion ROM even if MBA is disabled */ 972255736Sdavidch #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 973255736Sdavidch #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 974255736Sdavidch #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 975255736Sdavidch 976255736Sdavidch /* Check the optic vendor via i2c against a list of approved modules 977255736Sdavidch in a separate nvram image */ 978255736Sdavidch #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000 979255736Sdavidch #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 980255736Sdavidch #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 981255736Sdavidch 0x00000000 982255736Sdavidch #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 983255736Sdavidch 0x20000000 984255736Sdavidch #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 985255736Sdavidch #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 986255736Sdavidch 987255736Sdavidch uint32_t wol_config; 988255736Sdavidch /* Default is used when driver sets to "auto" mode */ 989255736Sdavidch #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 990255736Sdavidch 991255736Sdavidch uint32_t mba_config; 992255736Sdavidch #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 993255736Sdavidch #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 994255736Sdavidch #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 995255736Sdavidch #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 996255736Sdavidch #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 997255736Sdavidch #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 998255736Sdavidch #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 999255736Sdavidch #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 1000255736Sdavidch 1001255736Sdavidch #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 1002255736Sdavidch #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 1003255736Sdavidch 1004255736Sdavidch #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 1005255736Sdavidch #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 1006255736Sdavidch #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 1007255736Sdavidch #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 1008255736Sdavidch 1009255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000 1010255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 1011255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 1012255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 1013255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 1014255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 1015255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 1016255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 1017255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 1018255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 1019255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 1020255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 1021255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 1022255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 1023255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 1024255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 1025255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 1026255736Sdavidch #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 1027255736Sdavidch #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000 1028255736Sdavidch #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 1029255736Sdavidch #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 1030255736Sdavidch #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 1031255736Sdavidch #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 1032255736Sdavidch #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 1033255736Sdavidch #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 1034255736Sdavidch #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 1035255736Sdavidch #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000 1036255736Sdavidch #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 1037255736Sdavidch #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 1038255736Sdavidch #define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000 1039255736Sdavidch #define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000 1040255736Sdavidch #define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000 1041255736Sdavidch #define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000 1042255736Sdavidch #define PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000 1043255736Sdavidch #define PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000 1044255736Sdavidch #define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000 1045255736Sdavidch #define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000 1046255736Sdavidch 1047255736Sdavidch uint32_t Reserved0; /* 0x460 */ 1048255736Sdavidch 1049255736Sdavidch uint32_t mba_vlan_cfg; 1050255736Sdavidch #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF 1051255736Sdavidch #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1052255736Sdavidch #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1053260252Sedavis #define PORT_FEATUTE_BOFM_CFGD_EN 0x00020000 1054260252Sedavis #define PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000 1055260252Sedavis #define PORT_FEATURE_BOFM_CFGD_VEN 0x00080000 1056255736Sdavidch 1057255736Sdavidch uint32_t Reserved1; 1058255736Sdavidch uint32_t smbus_config; 1059255736Sdavidch #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1060255736Sdavidch #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1061255736Sdavidch 1062255736Sdavidch uint32_t vf_config; 1063255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F 1064255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1065255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1066255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1067255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1068255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1069255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1070255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1071255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1072255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1073255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1074255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1075255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1076255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1077255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1078255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1079255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1080255736Sdavidch #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1081255736Sdavidch 1082255736Sdavidch uint32_t link_config; /* Used as HW defaults for the driver */ 1083255736Sdavidch 1084255736Sdavidch #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1085255736Sdavidch #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1086255736Sdavidch #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1087255736Sdavidch #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1088255736Sdavidch #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1089255736Sdavidch #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1090255736Sdavidch #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1091255736Sdavidch #define PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500 1092255736Sdavidch #define PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600 1093255736Sdavidch #define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700 1094255736Sdavidch 1095255736Sdavidch #define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000 1096255736Sdavidch #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1097255736Sdavidch #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1098260252Sedavis #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000 1099260252Sedavis #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000 1100255736Sdavidch #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1101255736Sdavidch #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1102255736Sdavidch #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1103255736Sdavidch #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1104255736Sdavidch #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1105255736Sdavidch #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1106255736Sdavidch 1107255736Sdavidch #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1108255736Sdavidch #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1109255736Sdavidch /* (forced) low speed switch (< 10G) */ 1110255736Sdavidch #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1111255736Sdavidch /* (forced) high speed switch (>= 10G) */ 1112255736Sdavidch #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1113255736Sdavidch #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1114255736Sdavidch #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1115255736Sdavidch 1116255736Sdavidch 1117255736Sdavidch /* The default for MCP link configuration, 1118255736Sdavidch uses the same defines as link_config */ 1119255736Sdavidch uint32_t mfw_wol_link_cfg; 1120255736Sdavidch 1121255736Sdavidch /* The default for the driver of the second external phy, 1122255736Sdavidch uses the same defines as link_config */ 1123255736Sdavidch uint32_t link_config2; /* 0x47C */ 1124255736Sdavidch 1125255736Sdavidch /* The default for MCP of the second external phy, 1126255736Sdavidch uses the same defines as link_config */ 1127255736Sdavidch uint32_t mfw_wol_link_cfg2; /* 0x480 */ 1128255736Sdavidch 1129255736Sdavidch 1130255736Sdavidch /* EEE power saving mode */ 1131255736Sdavidch uint32_t eee_power_mode; /* 0x484 */ 1132255736Sdavidch #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF 1133255736Sdavidch #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 1134255736Sdavidch #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 1135255736Sdavidch #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 1136255736Sdavidch #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 1137255736Sdavidch #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 1138255736Sdavidch 1139255736Sdavidch 1140255736Sdavidch uint32_t Reserved2[16]; /* 0x488 */ 1141255736Sdavidch}; 1142255736Sdavidch 1143255736Sdavidch/**************************************************************************** 1144255736Sdavidch * Device Information * 1145255736Sdavidch ****************************************************************************/ 1146255736Sdavidchstruct shm_dev_info { /* size */ 1147255736Sdavidch 1148255736Sdavidch uint32_t bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1149255736Sdavidch 1150255736Sdavidch struct shared_hw_cfg shared_hw_config; /* 40 */ 1151255736Sdavidch 1152255736Sdavidch struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1153255736Sdavidch 1154255736Sdavidch struct shared_feat_cfg shared_feature_config; /* 4 */ 1155255736Sdavidch 1156255736Sdavidch struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1157255736Sdavidch 1158255736Sdavidch}; 1159255736Sdavidch 1160255736Sdavidchstruct extended_dev_info_shared_cfg { /* NVRAM OFFSET */ 1161255736Sdavidch 1162255736Sdavidch /* Threshold in celcius to start using the fan */ 1163255736Sdavidch uint32_t temperature_monitor1; /* 0x4000 */ 1164255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F 1165255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0 1166255736Sdavidch 1167255736Sdavidch /* Threshold in celcius to shut down the board */ 1168255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00 1169255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT 8 1170255736Sdavidch 1171255736Sdavidch /* EPIO of fan temperature status */ 1172255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000 1173255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT 16 1174255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000 1175255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000 1176255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000 1177255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000 1178255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000 1179255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000 1180255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000 1181255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000 1182255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000 1183255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000 1184255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000 1185255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000 1186255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000 1187255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000 1188255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000 1189255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000 1190255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000 1191255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000 1192255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000 1193255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000 1194255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000 1195255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000 1196255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000 1197255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000 1198255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000 1199255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000 1200255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000 1201255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000 1202255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000 1203255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000 1204255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000 1205255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000 1206255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000 1207255736Sdavidch 1208255736Sdavidch /* EPIO of shut down temperature status */ 1209255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000 1210255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT 24 1211255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000 1212255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000 1213255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000 1214255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000 1215255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000 1216255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000 1217255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000 1218255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000 1219255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000 1220255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000 1221255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000 1222255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000 1223255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000 1224255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000 1225255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000 1226255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000 1227255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000 1228255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000 1229255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000 1230255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000 1231255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000 1232255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000 1233255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000 1234255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000 1235255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000 1236255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000 1237255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000 1238255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000 1239255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000 1240255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000 1241255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000 1242255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000 1243255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000 1244255736Sdavidch 1245255736Sdavidch 1246255736Sdavidch /* EPIO of shut down temperature status */ 1247255736Sdavidch uint32_t temperature_monitor2; /* 0x4004 */ 1248255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF 1249255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0 1250255736Sdavidch 1251255736Sdavidch 1252255736Sdavidch /* MFW flavor to be used */ 1253255736Sdavidch uint32_t mfw_cfg; /* 0x4008 */ 1254255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF 1255255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0 1256255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000 1257255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001 1258255736Sdavidch 1259255736Sdavidch /* Should NIC data query remain enabled upon last drv unload */ 1260255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100 1261255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT 8 1262255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000 1263255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100 1264255736Sdavidch 1265255736Sdavidch /* Hide DCBX feature in CCM/BACS menus */ 1266255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000 1267255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16 1268255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000 1269255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000 1270255736Sdavidch 1271255736Sdavidch uint32_t smbus_config; /* 0x400C */ 1272255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF 1273255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0 1274255736Sdavidch 1275255736Sdavidch /* Switching regulator loop gain */ 1276255736Sdavidch uint32_t board_cfg; /* 0x4010 */ 1277255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F 1278255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0 1279255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000 1280255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008 1281255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009 1282255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a 1283255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b 1284255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c 1285255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d 1286255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e 1287255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f 1288255736Sdavidch 1289255736Sdavidch /* whether shadow swim feature is supported */ 1290255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100 1291255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT 8 1292255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000 1293255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100 1294255736Sdavidch 1295255736Sdavidch /* whether to show/hide SRIOV menu in CCM */ 1296255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200 1297255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT 9 1298255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000 1299255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200 1300255736Sdavidch 1301260425Sedavis /* Overide PCIE revision ID when enabled the, 1302260425Sedavis revision ID will set to B1=='0x11' */ 1303260425Sedavis #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400 1304260425Sedavis #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT 10 1305260425Sedavis #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000 1306260425Sedavis #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400 1307260425Sedavis 1308255736Sdavidch /* Threshold in celcius for max continuous operation */ 1309255736Sdavidch uint32_t temperature_report; /* 0x4014 */ 1310255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F 1311255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0 1312255736Sdavidch 1313255736Sdavidch /* Threshold in celcius for sensor caution */ 1314255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00 1315255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT 8 1316255736Sdavidch 1317255736Sdavidch /* wwn node prefix to be used (unless value is 0) */ 1318255736Sdavidch uint32_t wwn_prefix; /* 0x4018 */ 1319255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF 1320255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0 1321255736Sdavidch 1322255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00 1323255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT 8 1324255736Sdavidch 1325255736Sdavidch /* wwn port prefix to be used (unless value is 0) */ 1326255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000 1327255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT 16 1328255736Sdavidch 1329255736Sdavidch /* wwn port prefix to be used (unless value is 0) */ 1330255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000 1331255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT 24 1332255736Sdavidch 1333255736Sdavidch /* General debug nvm cfg */ 1334255736Sdavidch uint32_t dbg_cfg_flags; /* 0x401C */ 1335255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF 1336255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0 1337255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001 1338255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002 1339255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004 1340255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008 1341255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010 1342255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020 1343255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040 1344255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080 1345255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100 1346255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200 1347255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400 1348255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800 1349255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000 1350255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000 1351255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000 1352255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000 1353255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000 1354255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000 1355255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000 1356255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000 1357255736Sdavidch 1358255736Sdavidch /* Debug signet rx threshold */ 1359255736Sdavidch uint32_t dbg_rx_sigdet_threshold; /* 0x4020 */ 1360255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007 1361255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0 1362255736Sdavidch 1363255736Sdavidch /* Enable IFFE feature */ 1364255736Sdavidch uint32_t iffe_features; /* 0x4024 */ 1365255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001 1366255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0 1367255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000 1368255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001 1369255736Sdavidch 1370255736Sdavidch /* Allowable port enablement (bitmask for ports 3-1) */ 1371255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E 1372255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT 1 1373255736Sdavidch 1374255736Sdavidch /* Allow iSCSI offload override */ 1375255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010 1376255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT 4 1377255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000 1378255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010 1379255736Sdavidch 1380255736Sdavidch /* Allow FCoE offload override */ 1381255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020 1382255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT 5 1383255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000 1384255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020 1385255736Sdavidch 1386255736Sdavidch /* Tie to adaptor */ 1387255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000 1388255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT 15 1389255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000 1390255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000 1391255736Sdavidch 1392255736Sdavidch /* Currently enabled port(s) (bitmask for ports 3-1) */ 1393255736Sdavidch uint32_t current_iffe_mask; /* 0x4028 */ 1394255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E 1395255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT 1 1396255736Sdavidch 1397255736Sdavidch /* Current iSCSI offload */ 1398255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010 1399255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT 4 1400255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000 1401255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010 1402255736Sdavidch 1403255736Sdavidch /* Current FCoE offload */ 1404255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020 1405255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT 5 1406255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000 1407255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020 1408255736Sdavidch 1409255736Sdavidch /* FW set this pin to "0" (assert) these signal if either of its MAC 1410255736Sdavidch * or PHY specific threshold values is exceeded. 1411255736Sdavidch * Values are standard GPIO/EPIO pins. 1412255736Sdavidch */ 1413255736Sdavidch uint32_t threshold_pin; /* 0x402C */ 1414255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF 1415255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0 1416255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00 1417255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT 8 1418255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000 1419255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT 16 1420255736Sdavidch 1421255736Sdavidch /* MAC die temperature threshold in Celsius. */ 1422255736Sdavidch uint32_t mac_threshold_val; /* 0x4030 */ 1423255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF 1424255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0 1425255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00 1426255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8 1427255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000 1428255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16 1429255736Sdavidch 1430255736Sdavidch /* PHY die temperature threshold in Celsius. */ 1431255736Sdavidch uint32_t phy_threshold_val; /* 0x4034 */ 1432255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF 1433255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0 1434255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00 1435255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8 1436255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000 1437255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16 1438255736Sdavidch 1439255736Sdavidch /* External pins to communicate with host. 1440255736Sdavidch * Values are standard GPIO/EPIO pins. 1441255736Sdavidch */ 1442255736Sdavidch uint32_t host_pin; /* 0x4038 */ 1443255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF 1444255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0 1445255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00 1446255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT 8 1447255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000 1448255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16 1449255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000 1450255736Sdavidch #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24 1451255736Sdavidch}; 1452255736Sdavidch 1453255736Sdavidch 1454255736Sdavidch#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1455255736Sdavidch #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1456255736Sdavidch#endif 1457255736Sdavidch 1458255736Sdavidch#define FUNC_0 0 1459255736Sdavidch#define FUNC_1 1 1460255736Sdavidch#define FUNC_2 2 1461255736Sdavidch#define FUNC_3 3 1462255736Sdavidch#define FUNC_4 4 1463255736Sdavidch#define FUNC_5 5 1464255736Sdavidch#define FUNC_6 6 1465255736Sdavidch#define FUNC_7 7 1466255736Sdavidch#define E1_FUNC_MAX 2 1467255736Sdavidch#define E1H_FUNC_MAX 8 1468255736Sdavidch#define E2_FUNC_MAX 4 /* per path */ 1469255736Sdavidch 1470255736Sdavidch#define VN_0 0 1471255736Sdavidch#define VN_1 1 1472255736Sdavidch#define VN_2 2 1473255736Sdavidch#define VN_3 3 1474255736Sdavidch#define E1VN_MAX 1 1475255736Sdavidch#define E1HVN_MAX 4 1476255736Sdavidch 1477255736Sdavidch#define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1478255736Sdavidch/* This value (in milliseconds) determines the frequency of the driver 1479255736Sdavidch * issuing the PULSE message code. The firmware monitors this periodic 1480255736Sdavidch * pulse to determine when to switch to an OS-absent mode. */ 1481255736Sdavidch#define DRV_PULSE_PERIOD_MS 250 1482255736Sdavidch 1483255736Sdavidch/* This value (in milliseconds) determines how long the driver should 1484255736Sdavidch * wait for an acknowledgement from the firmware before timing out. Once 1485255736Sdavidch * the firmware has timed out, the driver will assume there is no firmware 1486255736Sdavidch * running and there won't be any firmware-driver synchronization during a 1487255736Sdavidch * driver reset. */ 1488255736Sdavidch#define FW_ACK_TIME_OUT_MS 5000 1489255736Sdavidch 1490255736Sdavidch#define FW_ACK_POLL_TIME_MS 1 1491255736Sdavidch 1492255736Sdavidch#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1493255736Sdavidch 1494255736Sdavidch#define MFW_TRACE_SIGNATURE 0x54524342 1495255736Sdavidch 1496255736Sdavidch/**************************************************************************** 1497255736Sdavidch * Driver <-> FW Mailbox * 1498255736Sdavidch ****************************************************************************/ 1499255736Sdavidchstruct drv_port_mb { 1500255736Sdavidch 1501255736Sdavidch uint32_t link_status; 1502255736Sdavidch /* Driver should update this field on any link change event */ 1503255736Sdavidch 1504255736Sdavidch #define LINK_STATUS_NONE (0<<0) 1505255736Sdavidch #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1506255736Sdavidch #define LINK_STATUS_LINK_UP 0x00000001 1507255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1508255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1509255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1510255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1511255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1512255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1513255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1514255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1515255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1516255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1517255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1518255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1519255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1520255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1521255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1522255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1523255736Sdavidch #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1524255736Sdavidch 1525255736Sdavidch #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1526255736Sdavidch #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1527255736Sdavidch 1528255736Sdavidch #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1529255736Sdavidch #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1530255736Sdavidch #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1531255736Sdavidch 1532255736Sdavidch #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1533255736Sdavidch #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1534255736Sdavidch #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1535255736Sdavidch #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1536255736Sdavidch #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1537255736Sdavidch #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1538255736Sdavidch #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1539255736Sdavidch 1540255736Sdavidch #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1541255736Sdavidch #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1542255736Sdavidch 1543255736Sdavidch #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1544255736Sdavidch #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1545255736Sdavidch 1546255736Sdavidch #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1547255736Sdavidch #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1548255736Sdavidch #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1549255736Sdavidch #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1550255736Sdavidch #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1551255736Sdavidch 1552255736Sdavidch #define LINK_STATUS_SERDES_LINK 0x00100000 1553255736Sdavidch 1554255736Sdavidch #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1555255736Sdavidch #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1556255736Sdavidch #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1557255736Sdavidch #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1558255736Sdavidch 1559255736Sdavidch #define LINK_STATUS_PFC_ENABLED 0x20000000 1560255736Sdavidch 1561255736Sdavidch #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1562255736Sdavidch #define LINK_STATUS_SFP_TX_FAULT 0x80000000 1563255736Sdavidch 1564255736Sdavidch uint32_t port_stx; 1565255736Sdavidch 1566255736Sdavidch uint32_t stat_nig_timer; 1567255736Sdavidch 1568255736Sdavidch /* MCP firmware does not use this field */ 1569255736Sdavidch uint32_t ext_phy_fw_version; 1570255736Sdavidch 1571255736Sdavidch}; 1572255736Sdavidch 1573255736Sdavidch 1574255736Sdavidchstruct drv_func_mb { 1575255736Sdavidch 1576255736Sdavidch uint32_t drv_mb_header; 1577255736Sdavidch #define DRV_MSG_CODE_MASK 0xffff0000 1578255736Sdavidch #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1579255736Sdavidch #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1580255736Sdavidch #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1581255736Sdavidch #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1582255736Sdavidch #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1583255736Sdavidch #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1584255736Sdavidch #define DRV_MSG_CODE_DCC_OK 0x30000000 1585255736Sdavidch #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1586255736Sdavidch #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1587255736Sdavidch #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1588255736Sdavidch #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1589255736Sdavidch #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1590255736Sdavidch #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1591255736Sdavidch #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1592255736Sdavidch #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1593255736Sdavidch 1594255736Sdavidch /* 1595255736Sdavidch * The optic module verification command requires bootcode 1596255736Sdavidch * v5.0.6 or later, te specific optic module verification command 1597255736Sdavidch * requires bootcode v5.2.12 or later 1598255736Sdavidch */ 1599255736Sdavidch #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1600255736Sdavidch #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1601255736Sdavidch #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1602255736Sdavidch #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1603255736Sdavidch #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 1604255736Sdavidch #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 1605255736Sdavidch #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1606255736Sdavidch #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201 1607255736Sdavidch #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1608255736Sdavidch #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 1609255736Sdavidch 1610255736Sdavidch #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1611255736Sdavidch #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1612255736Sdavidch #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 1613255736Sdavidch 1614255736Sdavidch #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1615255736Sdavidch 1616255736Sdavidch #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 1617255736Sdavidch #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 1618255736Sdavidch #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 1619255736Sdavidch #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 1620255736Sdavidch #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 1621255736Sdavidch 1622255736Sdavidch #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 1623255736Sdavidch #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 1624255736Sdavidch 1625255736Sdavidch #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 1626255736Sdavidch 1627255736Sdavidch #define DRV_MSG_CODE_RMMOD 0xdb000000 1628255736Sdavidch #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f 1629255736Sdavidch 1630255736Sdavidch #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1631255736Sdavidch #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1632255736Sdavidch #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1633255736Sdavidch 1634255736Sdavidch #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1635255736Sdavidch 1636255736Sdavidch #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 1637255736Sdavidch #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 1638255736Sdavidch 1639255736Sdavidch #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1640255736Sdavidch #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1641255736Sdavidch #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1642255736Sdavidch #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1643255736Sdavidch 1644255736Sdavidch #define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000 1645255736Sdavidch #define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000 1646255736Sdavidch 1647255736Sdavidch #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1648255736Sdavidch 1649255736Sdavidch uint32_t drv_mb_param; 1650255736Sdavidch #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1651255736Sdavidch #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1652255736Sdavidch 1653255736Sdavidch #define DRV_MSG_CODE_UNLOAD_NON_D3_POWER 0x00000001 1654255736Sdavidch #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 1655255736Sdavidch 1656255736Sdavidch #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a 1657255736Sdavidch #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000 1658255736Sdavidch 1659255736Sdavidch #define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001 1660260252Sedavis #define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ 0x00000002 1661255736Sdavidch 1662255736Sdavidch uint32_t fw_mb_header; 1663255736Sdavidch #define FW_MSG_CODE_MASK 0xffff0000 1664255736Sdavidch #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1665255736Sdavidch #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1666255736Sdavidch #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1667255736Sdavidch /* Load common chip is supported from bc 6.0.0 */ 1668255736Sdavidch #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1669255736Sdavidch #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1670255736Sdavidch 1671255736Sdavidch #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1672255736Sdavidch #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1673255736Sdavidch #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1674255736Sdavidch #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1675255736Sdavidch #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1676255736Sdavidch #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1677255736Sdavidch #define FW_MSG_CODE_DCC_DONE 0x30100000 1678255736Sdavidch #define FW_MSG_CODE_LLDP_DONE 0x40100000 1679255736Sdavidch #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1680255736Sdavidch #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1681255736Sdavidch #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1682255736Sdavidch #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1683255736Sdavidch #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1684255736Sdavidch #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1685255736Sdavidch #define FW_MSG_CODE_NO_KEY 0x80f00000 1686255736Sdavidch #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1687255736Sdavidch #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1688255736Sdavidch #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1689255736Sdavidch #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1690255736Sdavidch #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1691255736Sdavidch #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1692255736Sdavidch #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1693255736Sdavidch #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1694255736Sdavidch #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1695255736Sdavidch #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1696255736Sdavidch #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 1697255736Sdavidch 1698255736Sdavidch #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 1699255736Sdavidch #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 1700255736Sdavidch #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 1701255736Sdavidch #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 1702255736Sdavidch #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 1703255736Sdavidch 1704255736Sdavidch #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 1705255736Sdavidch #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 1706255736Sdavidch 1707255736Sdavidch #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 1708255736Sdavidch 1709255736Sdavidch #define FW_MSG_CODE_RMMOD_ACK 0xdb100000 1710255736Sdavidch 1711255736Sdavidch #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1712255736Sdavidch #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1713255736Sdavidch 1714255736Sdavidch #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1715255736Sdavidch 1716255736Sdavidch #define FW_MSG_CODE_FLR_ACK 0x02000000 1717255736Sdavidch #define FW_MSG_CODE_FLR_NACK 0x02100000 1718255736Sdavidch 1719255736Sdavidch #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1720255736Sdavidch #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1721255736Sdavidch #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1722255736Sdavidch #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1723255736Sdavidch 1724255736Sdavidch #define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000 1725255736Sdavidch #define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000 1726255736Sdavidch 1727255736Sdavidch #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1728255736Sdavidch 1729255736Sdavidch uint32_t fw_mb_param; 1730255736Sdavidch 1731255736Sdavidch #define FW_PARAM_INVALID_IMG 0xffffffff 1732255736Sdavidch 1733255736Sdavidch uint32_t drv_pulse_mb; 1734255736Sdavidch #define DRV_PULSE_SEQ_MASK 0x00007fff 1735255736Sdavidch #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1736255736Sdavidch /* 1737255736Sdavidch * The system time is in the format of 1738255736Sdavidch * (year-2001)*12*32 + month*32 + day. 1739255736Sdavidch */ 1740255736Sdavidch #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1741255736Sdavidch /* 1742255736Sdavidch * Indicate to the firmware not to go into the 1743255736Sdavidch * OS-absent when it is not getting driver pulse. 1744255736Sdavidch * This is used for debugging as well for PXE(MBA). 1745255736Sdavidch */ 1746255736Sdavidch 1747255736Sdavidch uint32_t mcp_pulse_mb; 1748255736Sdavidch #define MCP_PULSE_SEQ_MASK 0x00007fff 1749255736Sdavidch #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1750255736Sdavidch /* Indicates to the driver not to assert due to lack 1751255736Sdavidch * of MCP response */ 1752255736Sdavidch #define MCP_EVENT_MASK 0xffff0000 1753255736Sdavidch #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1754255736Sdavidch 1755255736Sdavidch uint32_t iscsi_boot_signature; 1756255736Sdavidch uint32_t iscsi_boot_block_offset; 1757255736Sdavidch 1758255736Sdavidch uint32_t drv_status; 1759255736Sdavidch #define DRV_STATUS_PMF 0x00000001 1760255736Sdavidch #define DRV_STATUS_VF_DISABLED 0x00000002 1761255736Sdavidch #define DRV_STATUS_SET_MF_BW 0x00000004 1762255736Sdavidch #define DRV_STATUS_LINK_EVENT 0x00000008 1763255736Sdavidch 1764255736Sdavidch #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1765255736Sdavidch #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1766255736Sdavidch #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1767255736Sdavidch #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1768255736Sdavidch #define DRV_STATUS_DCC_RESERVED1 0x00000800 1769255736Sdavidch #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1770255736Sdavidch #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1771255736Sdavidch 1772255736Sdavidch #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1773255736Sdavidch #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1774255736Sdavidch #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 1775255736Sdavidch #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 1776255736Sdavidch #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 1777255736Sdavidch #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 1778255736Sdavidch #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 1779255736Sdavidch 1780255736Sdavidch #define DRV_STATUS_DRV_INFO_REQ 0x04000000 1781255736Sdavidch 1782255736Sdavidch #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 1783255736Sdavidch 1784255736Sdavidch uint32_t virt_mac_upper; 1785255736Sdavidch #define VIRT_MAC_SIGN_MASK 0xffff0000 1786255736Sdavidch #define VIRT_MAC_SIGNATURE 0x564d0000 1787255736Sdavidch uint32_t virt_mac_lower; 1788255736Sdavidch 1789255736Sdavidch}; 1790255736Sdavidch 1791255736Sdavidch 1792255736Sdavidch/**************************************************************************** 1793255736Sdavidch * Management firmware state * 1794255736Sdavidch ****************************************************************************/ 1795255736Sdavidch/* Allocate 440 bytes for management firmware */ 1796255736Sdavidch#define MGMTFW_STATE_WORD_SIZE 110 1797255736Sdavidch 1798255736Sdavidchstruct mgmtfw_state { 1799255736Sdavidch uint32_t opaque[MGMTFW_STATE_WORD_SIZE]; 1800255736Sdavidch}; 1801255736Sdavidch 1802255736Sdavidch 1803255736Sdavidch/**************************************************************************** 1804255736Sdavidch * Multi-Function configuration * 1805255736Sdavidch ****************************************************************************/ 1806255736Sdavidchstruct shared_mf_cfg { 1807255736Sdavidch 1808255736Sdavidch uint32_t clp_mb; 1809255736Sdavidch #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1810255736Sdavidch /* set by CLP */ 1811255736Sdavidch #define SHARED_MF_CLP_EXIT 0x00000001 1812255736Sdavidch /* set by MCP */ 1813255736Sdavidch #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1814255736Sdavidch 1815255736Sdavidch}; 1816255736Sdavidch 1817255736Sdavidchstruct port_mf_cfg { 1818255736Sdavidch 1819255736Sdavidch uint32_t dynamic_cfg; /* device control channel */ 1820255736Sdavidch #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1821255736Sdavidch #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1822255736Sdavidch #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1823255736Sdavidch 1824255736Sdavidch uint32_t reserved[1]; 1825255736Sdavidch 1826255736Sdavidch}; 1827255736Sdavidch 1828255736Sdavidchstruct func_mf_cfg { 1829255736Sdavidch 1830255736Sdavidch uint32_t config; 1831255736Sdavidch /* E/R/I/D */ 1832255736Sdavidch /* function 0 of each port cannot be hidden */ 1833255736Sdavidch #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1834255736Sdavidch 1835255736Sdavidch #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1836255736Sdavidch #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1837255736Sdavidch #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1838255736Sdavidch #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1839255736Sdavidch #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1840255736Sdavidch #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1841255736Sdavidch FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1842255736Sdavidch 1843255736Sdavidch #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1844255736Sdavidch #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1845255736Sdavidch 1846255736Sdavidch #define FUNC_MF_CFG_FUNC_BOOT_MASK 0x00000060 1847255736Sdavidch #define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL 0x00000000 1848255736Sdavidch #define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED 0x00000020 1849255736Sdavidch #define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED 0x00000040 1850255736Sdavidch 1851255736Sdavidch /* PRI */ 1852255736Sdavidch /* 0 - low priority, 3 - high priority */ 1853255736Sdavidch #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1854255736Sdavidch #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1855255736Sdavidch #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1856255736Sdavidch 1857255736Sdavidch /* MINBW, MAXBW */ 1858255736Sdavidch /* value range - 0..100, increments in 100Mbps */ 1859255736Sdavidch #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1860255736Sdavidch #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1861255736Sdavidch #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1862255736Sdavidch #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1863255736Sdavidch #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1864255736Sdavidch #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1865255736Sdavidch 1866255736Sdavidch uint32_t mac_upper; /* MAC */ 1867255736Sdavidch #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1868255736Sdavidch #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1869255736Sdavidch #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1870255736Sdavidch uint32_t mac_lower; 1871255736Sdavidch #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1872255736Sdavidch 1873255736Sdavidch uint32_t e1hov_tag; /* VNI */ 1874255736Sdavidch #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1875255736Sdavidch #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1876255736Sdavidch #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1877255736Sdavidch 1878255736Sdavidch /* afex default VLAN ID - 12 bits */ 1879255736Sdavidch #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 1880255736Sdavidch #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 1881255736Sdavidch 1882255736Sdavidch uint32_t afex_config; 1883255736Sdavidch #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff 1884255736Sdavidch #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 1885255736Sdavidch #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 1886255736Sdavidch #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 1887255736Sdavidch #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 1888255736Sdavidch #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 1889255736Sdavidch #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 1890255736Sdavidch 1891255736Sdavidch uint32_t pf_allocation; 1892255736Sdavidch /* number of vfs in function, if 0 - sriov disabled */ 1893255736Sdavidch #define FUNC_MF_CFG_NUMBER_OF_VFS_MASK 0x000000FF 1894255736Sdavidch #define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT 0 1895255736Sdavidch}; 1896255736Sdavidch 1897255736Sdavidchenum mf_cfg_afex_vlan_mode { 1898255736Sdavidch FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, 1899255736Sdavidch FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, 1900255736Sdavidch FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE 1901255736Sdavidch}; 1902255736Sdavidch 1903255736Sdavidch/* This structure is not applicable and should not be accessed on 57711 */ 1904255736Sdavidchstruct func_ext_cfg { 1905255736Sdavidch uint32_t func_cfg; 1906255736Sdavidch #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F 1907255736Sdavidch #define MACP_FUNC_CFG_FLAGS_SHIFT 0 1908255736Sdavidch #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 1909255736Sdavidch #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 1910255736Sdavidch #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 1911255736Sdavidch #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 1912255736Sdavidch #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 1913255736Sdavidch 1914255736Sdavidch uint32_t iscsi_mac_addr_upper; 1915255736Sdavidch uint32_t iscsi_mac_addr_lower; 1916255736Sdavidch 1917255736Sdavidch uint32_t fcoe_mac_addr_upper; 1918255736Sdavidch uint32_t fcoe_mac_addr_lower; 1919255736Sdavidch 1920255736Sdavidch uint32_t fcoe_wwn_port_name_upper; 1921255736Sdavidch uint32_t fcoe_wwn_port_name_lower; 1922255736Sdavidch 1923255736Sdavidch uint32_t fcoe_wwn_node_name_upper; 1924255736Sdavidch uint32_t fcoe_wwn_node_name_lower; 1925255736Sdavidch 1926255736Sdavidch uint32_t preserve_data; 1927255736Sdavidch #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 1928255736Sdavidch #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 1929255736Sdavidch #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 1930255736Sdavidch #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 1931255736Sdavidch #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 1932255736Sdavidch #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 1933255736Sdavidch}; 1934255736Sdavidch 1935255736Sdavidchstruct mf_cfg { 1936255736Sdavidch 1937255736Sdavidch struct shared_mf_cfg shared_mf_config; /* 0x4 */ 1938255736Sdavidch struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; 1939255736Sdavidch /* 0x10*2=0x20 */ 1940255736Sdavidch /* for all chips, there are 8 mf functions */ 1941255736Sdavidch struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 1942255736Sdavidch /* 1943255736Sdavidch * Extended configuration per function - this array does not exist and 1944255736Sdavidch * should not be accessed on 57711 1945255736Sdavidch */ 1946255736Sdavidch struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 1947255736Sdavidch}; /* 0x224 */ 1948255736Sdavidch 1949255736Sdavidch/**************************************************************************** 1950255736Sdavidch * Shared Memory Region * 1951255736Sdavidch ****************************************************************************/ 1952255736Sdavidchstruct shmem_region { /* SharedMem Offset (size) */ 1953255736Sdavidch 1954255736Sdavidch uint32_t validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 1955255736Sdavidch #define SHR_MEM_FORMAT_REV_MASK 0xff000000 1956255736Sdavidch #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 1957255736Sdavidch /* validity bits */ 1958255736Sdavidch #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 1959255736Sdavidch #define SHR_MEM_VALIDITY_MB 0x00200000 1960255736Sdavidch #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 1961255736Sdavidch #define SHR_MEM_VALIDITY_RESERVED 0x00000007 1962255736Sdavidch /* One licensing bit should be set */ 1963255736Sdavidch #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 1964255736Sdavidch #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 1965255736Sdavidch #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 1966255736Sdavidch #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 1967255736Sdavidch /* Active MFW */ 1968255736Sdavidch #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 1969255736Sdavidch #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 1970255736Sdavidch #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 1971255736Sdavidch #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 1972255736Sdavidch #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 1973255736Sdavidch #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 1974255736Sdavidch 1975255736Sdavidch struct shm_dev_info dev_info; /* 0x8 (0x438) */ 1976255736Sdavidch 1977255736Sdavidch license_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 1978255736Sdavidch 1979255736Sdavidch /* FW information (for internal FW use) */ 1980255736Sdavidch uint32_t fw_info_fio_offset; /* 0x4a8 (0x4) */ 1981255736Sdavidch struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 1982255736Sdavidch 1983255736Sdavidch struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 1984255736Sdavidch 1985255736Sdavidch 1986255736Sdavidch#ifdef BMAPI 1987255736Sdavidch /* This is a variable length array */ 1988255736Sdavidch /* the number of function depends on the chip type */ 1989255736Sdavidch struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1990255736Sdavidch#else 1991255736Sdavidch /* the number of function depends on the chip type */ 1992255736Sdavidch struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1993255736Sdavidch#endif /* BMAPI */ 1994255736Sdavidch 1995255736Sdavidch}; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 1996255736Sdavidch 1997255736Sdavidch/**************************************************************************** 1998255736Sdavidch * Shared Memory 2 Region * 1999255736Sdavidch ****************************************************************************/ 2000255736Sdavidch/* The fw_flr_ack is actually built in the following way: */ 2001255736Sdavidch/* 8 bit: PF ack */ 2002255736Sdavidch/* 64 bit: VF ack */ 2003255736Sdavidch/* 8 bit: ios_dis_ack */ 2004255736Sdavidch/* In order to maintain endianity in the mailbox hsi, we want to keep using */ 2005255736Sdavidch/* uint32_t. The fw must have the VF right after the PF since this is how it */ 2006255736Sdavidch/* access arrays(it expects always the VF to reside after the PF, and that */ 2007255736Sdavidch/* makes the calculation much easier for it. ) */ 2008255736Sdavidch/* In order to answer both limitations, and keep the struct small, the code */ 2009255736Sdavidch/* will abuse the structure defined here to achieve the actual partition */ 2010255736Sdavidch/* above */ 2011255736Sdavidch/****************************************************************************/ 2012255736Sdavidchstruct fw_flr_ack { 2013255736Sdavidch uint32_t pf_ack; 2014255736Sdavidch uint32_t vf_ack[1]; 2015255736Sdavidch uint32_t iov_dis_ack; 2016255736Sdavidch}; 2017255736Sdavidch 2018255736Sdavidchstruct fw_flr_mb { 2019255736Sdavidch uint32_t aggint; 2020255736Sdavidch uint32_t opgen_addr; 2021255736Sdavidch struct fw_flr_ack ack; 2022255736Sdavidch}; 2023255736Sdavidch 2024255736Sdavidchstruct eee_remote_vals { 2025255736Sdavidch uint32_t tx_tw; 2026255736Sdavidch uint32_t rx_tw; 2027255736Sdavidch}; 2028255736Sdavidch 2029255736Sdavidch/**** SUPPORT FOR SHMEM ARRRAYS *** 2030255736Sdavidch * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 2031255736Sdavidch * define arrays with storage types smaller then unsigned dwords. 2032255736Sdavidch * The macros below add generic support for SHMEM arrays with numeric elements 2033255736Sdavidch * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 2034255736Sdavidch * array with individual bit-filed elements accessed using shifts and masks. 2035255736Sdavidch * 2036255736Sdavidch */ 2037255736Sdavidch 2038255736Sdavidch/* eb is the bitwidth of a single element */ 2039255736Sdavidch#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 2040255736Sdavidch#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 2041255736Sdavidch 2042255736Sdavidch/* the bit-position macro allows the used to flip the order of the arrays 2043255736Sdavidch * elements on a per byte or word boundary. 2044255736Sdavidch * 2045255736Sdavidch * example: an array with 8 entries each 4 bit wide. This array will fit into 2046255736Sdavidch * a single dword. The diagrmas below show the array order of the nibbles. 2047255736Sdavidch * 2048255736Sdavidch * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 2049255736Sdavidch * 2050255736Sdavidch * | | | | 2051255736Sdavidch * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 2052255736Sdavidch * | | | | 2053255736Sdavidch * 2054255736Sdavidch * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 2055255736Sdavidch * 2056255736Sdavidch * | | | | 2057255736Sdavidch * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 2058255736Sdavidch * | | | | 2059255736Sdavidch * 2060255736Sdavidch * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 2061255736Sdavidch * 2062255736Sdavidch * | | | | 2063255736Sdavidch * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 2064255736Sdavidch * | | | | 2065255736Sdavidch */ 2066255736Sdavidch#define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 2067255736Sdavidch ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 2068255736Sdavidch (((i)%((fb)/(eb))) * (eb))) 2069255736Sdavidch 2070255736Sdavidch#define SHMEM_ARRAY_GET(a, i, eb, fb) \ 2071255736Sdavidch ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 2072255736Sdavidch SHMEM_ARRAY_MASK(eb)) 2073255736Sdavidch 2074255736Sdavidch#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 2075255736Sdavidchdo { \ 2076255736Sdavidch a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 2077255736Sdavidch SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 2078255736Sdavidch a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 2079255736Sdavidch SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 2080255736Sdavidch} while (0) 2081255736Sdavidch 2082255736Sdavidch 2083255736Sdavidch/****START OF DCBX STRUCTURES DECLARATIONS****/ 2084255736Sdavidch#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 2085255736Sdavidch#define DCBX_PRI_PG_BITWIDTH 4 2086255736Sdavidch#define DCBX_PRI_PG_FBITS 8 2087255736Sdavidch#define DCBX_PRI_PG_GET(a, i) \ 2088255736Sdavidch SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 2089255736Sdavidch#define DCBX_PRI_PG_SET(a, i, val) \ 2090255736Sdavidch SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 2091255736Sdavidch#define DCBX_MAX_NUM_PG_BW_ENTRIES 8 2092255736Sdavidch#define DCBX_BW_PG_BITWIDTH 8 2093255736Sdavidch#define DCBX_PG_BW_GET(a, i) \ 2094255736Sdavidch SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 2095255736Sdavidch#define DCBX_PG_BW_SET(a, i, val) \ 2096255736Sdavidch SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 2097255736Sdavidch#define DCBX_STRICT_PRI_PG 15 2098255736Sdavidch#define DCBX_MAX_APP_PROTOCOL 16 2099255736Sdavidch#define DCBX_MAX_APP_LOCAL 32 2100255736Sdavidch#define FCOE_APP_IDX 0 2101255736Sdavidch#define ISCSI_APP_IDX 1 2102255736Sdavidch#define PREDEFINED_APP_IDX_MAX 2 2103255736Sdavidch 2104255736Sdavidch 2105255736Sdavidch/* Big/Little endian have the same representation. */ 2106255736Sdavidchstruct dcbx_ets_feature { 2107255736Sdavidch /* 2108255736Sdavidch * For Admin MIB - is this feature supported by the 2109255736Sdavidch * driver | For Local MIB - should this feature be enabled. 2110255736Sdavidch */ 2111255736Sdavidch uint32_t enabled; 2112255736Sdavidch uint32_t pg_bw_tbl[2]; 2113255736Sdavidch uint32_t pri_pg_tbl[1]; 2114255736Sdavidch}; 2115255736Sdavidch 2116255736Sdavidch/* Driver structure in LE */ 2117255736Sdavidchstruct dcbx_pfc_feature { 2118255736Sdavidch#ifdef __BIG_ENDIAN 2119255736Sdavidch uint8_t pri_en_bitmap; 2120255736Sdavidch #define DCBX_PFC_PRI_0 0x01 2121255736Sdavidch #define DCBX_PFC_PRI_1 0x02 2122255736Sdavidch #define DCBX_PFC_PRI_2 0x04 2123255736Sdavidch #define DCBX_PFC_PRI_3 0x08 2124255736Sdavidch #define DCBX_PFC_PRI_4 0x10 2125255736Sdavidch #define DCBX_PFC_PRI_5 0x20 2126255736Sdavidch #define DCBX_PFC_PRI_6 0x40 2127255736Sdavidch #define DCBX_PFC_PRI_7 0x80 2128255736Sdavidch uint8_t pfc_caps; 2129255736Sdavidch uint8_t reserved; 2130255736Sdavidch uint8_t enabled; 2131255736Sdavidch#elif defined(__LITTLE_ENDIAN) 2132255736Sdavidch uint8_t enabled; 2133255736Sdavidch uint8_t reserved; 2134255736Sdavidch uint8_t pfc_caps; 2135255736Sdavidch uint8_t pri_en_bitmap; 2136255736Sdavidch #define DCBX_PFC_PRI_0 0x01 2137255736Sdavidch #define DCBX_PFC_PRI_1 0x02 2138255736Sdavidch #define DCBX_PFC_PRI_2 0x04 2139255736Sdavidch #define DCBX_PFC_PRI_3 0x08 2140255736Sdavidch #define DCBX_PFC_PRI_4 0x10 2141255736Sdavidch #define DCBX_PFC_PRI_5 0x20 2142255736Sdavidch #define DCBX_PFC_PRI_6 0x40 2143255736Sdavidch #define DCBX_PFC_PRI_7 0x80 2144255736Sdavidch#endif 2145255736Sdavidch}; 2146255736Sdavidch 2147255736Sdavidchstruct dcbx_app_priority_entry { 2148255736Sdavidch#ifdef __BIG_ENDIAN 2149255736Sdavidch uint16_t app_id; 2150255736Sdavidch uint8_t pri_bitmap; 2151255736Sdavidch uint8_t appBitfield; 2152255736Sdavidch #define DCBX_APP_ENTRY_VALID 0x01 2153255736Sdavidch #define DCBX_APP_ENTRY_SF_MASK 0x30 2154255736Sdavidch #define DCBX_APP_ENTRY_SF_SHIFT 4 2155255736Sdavidch #define DCBX_APP_SF_ETH_TYPE 0x10 2156255736Sdavidch #define DCBX_APP_SF_PORT 0x20 2157255736Sdavidch#elif defined(__LITTLE_ENDIAN) 2158255736Sdavidch uint8_t appBitfield; 2159255736Sdavidch #define DCBX_APP_ENTRY_VALID 0x01 2160255736Sdavidch #define DCBX_APP_ENTRY_SF_MASK 0x30 2161255736Sdavidch #define DCBX_APP_ENTRY_SF_SHIFT 4 2162255736Sdavidch #define DCBX_APP_SF_ETH_TYPE 0x10 2163255736Sdavidch #define DCBX_APP_SF_PORT 0x20 2164255736Sdavidch uint8_t pri_bitmap; 2165255736Sdavidch uint16_t app_id; 2166255736Sdavidch#endif 2167255736Sdavidch}; 2168255736Sdavidch 2169255736Sdavidch 2170255736Sdavidch/* FW structure in BE */ 2171255736Sdavidchstruct dcbx_app_priority_feature { 2172255736Sdavidch#ifdef __BIG_ENDIAN 2173255736Sdavidch uint8_t reserved; 2174255736Sdavidch uint8_t default_pri; 2175255736Sdavidch uint8_t tc_supported; 2176255736Sdavidch uint8_t enabled; 2177255736Sdavidch#elif defined(__LITTLE_ENDIAN) 2178255736Sdavidch uint8_t enabled; 2179255736Sdavidch uint8_t tc_supported; 2180255736Sdavidch uint8_t default_pri; 2181255736Sdavidch uint8_t reserved; 2182255736Sdavidch#endif 2183255736Sdavidch struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 2184255736Sdavidch}; 2185255736Sdavidch 2186255736Sdavidch/* FW structure in BE */ 2187255736Sdavidchstruct dcbx_features { 2188255736Sdavidch /* PG feature */ 2189255736Sdavidch struct dcbx_ets_feature ets; 2190255736Sdavidch /* PFC feature */ 2191255736Sdavidch struct dcbx_pfc_feature pfc; 2192255736Sdavidch /* APP feature */ 2193255736Sdavidch struct dcbx_app_priority_feature app; 2194255736Sdavidch}; 2195255736Sdavidch 2196255736Sdavidch/* LLDP protocol parameters */ 2197255736Sdavidch/* FW structure in BE */ 2198255736Sdavidchstruct lldp_params { 2199255736Sdavidch#ifdef __BIG_ENDIAN 2200255736Sdavidch uint8_t msg_fast_tx_interval; 2201255736Sdavidch uint8_t msg_tx_hold; 2202255736Sdavidch uint8_t msg_tx_interval; 2203255736Sdavidch uint8_t admin_status; 2204255736Sdavidch #define LLDP_TX_ONLY 0x01 2205255736Sdavidch #define LLDP_RX_ONLY 0x02 2206255736Sdavidch #define LLDP_TX_RX 0x03 2207255736Sdavidch #define LLDP_DISABLED 0x04 2208255736Sdavidch uint8_t reserved1; 2209255736Sdavidch uint8_t tx_fast; 2210255736Sdavidch uint8_t tx_crd_max; 2211255736Sdavidch uint8_t tx_crd; 2212255736Sdavidch#elif defined(__LITTLE_ENDIAN) 2213255736Sdavidch uint8_t admin_status; 2214255736Sdavidch #define LLDP_TX_ONLY 0x01 2215255736Sdavidch #define LLDP_RX_ONLY 0x02 2216255736Sdavidch #define LLDP_TX_RX 0x03 2217255736Sdavidch #define LLDP_DISABLED 0x04 2218255736Sdavidch uint8_t msg_tx_interval; 2219255736Sdavidch uint8_t msg_tx_hold; 2220255736Sdavidch uint8_t msg_fast_tx_interval; 2221255736Sdavidch uint8_t tx_crd; 2222255736Sdavidch uint8_t tx_crd_max; 2223255736Sdavidch uint8_t tx_fast; 2224255736Sdavidch uint8_t reserved1; 2225255736Sdavidch#endif 2226255736Sdavidch #define REM_CHASSIS_ID_STAT_LEN 4 2227255736Sdavidch #define REM_PORT_ID_STAT_LEN 4 2228255736Sdavidch /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 2229255736Sdavidch uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 2230255736Sdavidch /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 2231255736Sdavidch uint32_t peer_port_id[REM_PORT_ID_STAT_LEN]; 2232255736Sdavidch}; 2233255736Sdavidch 2234255736Sdavidchstruct lldp_dcbx_stat { 2235255736Sdavidch #define LOCAL_CHASSIS_ID_STAT_LEN 2 2236255736Sdavidch #define LOCAL_PORT_ID_STAT_LEN 2 2237255736Sdavidch /* Holds local Chassis ID 8B payload of constant subtype 4. */ 2238255736Sdavidch uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 2239255736Sdavidch /* Holds local Port ID 8B payload of constant subtype 3. */ 2240255736Sdavidch uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN]; 2241255736Sdavidch /* Number of DCBX frames transmitted. */ 2242255736Sdavidch uint32_t num_tx_dcbx_pkts; 2243255736Sdavidch /* Number of DCBX frames received. */ 2244255736Sdavidch uint32_t num_rx_dcbx_pkts; 2245255736Sdavidch}; 2246255736Sdavidch 2247255736Sdavidch/* ADMIN MIB - DCBX local machine default configuration. */ 2248255736Sdavidchstruct lldp_admin_mib { 2249255736Sdavidch uint32_t ver_cfg_flags; 2250255736Sdavidch #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 2251255736Sdavidch #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 2252255736Sdavidch #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 2253255736Sdavidch #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 2254255736Sdavidch #define DCBX_ETS_RECO_VALID 0x00000010 2255255736Sdavidch #define DCBX_ETS_WILLING 0x00000020 2256255736Sdavidch #define DCBX_PFC_WILLING 0x00000040 2257255736Sdavidch #define DCBX_APP_WILLING 0x00000080 2258255736Sdavidch #define DCBX_VERSION_CEE 0x00000100 2259255736Sdavidch #define DCBX_VERSION_IEEE 0x00000200 2260255736Sdavidch #define DCBX_DCBX_ENABLED 0x00000400 2261255736Sdavidch #define DCBX_CEE_VERSION_MASK 0x0000f000 2262255736Sdavidch #define DCBX_CEE_VERSION_SHIFT 12 2263255736Sdavidch #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 2264255736Sdavidch #define DCBX_CEE_MAX_VERSION_SHIFT 16 2265255736Sdavidch struct dcbx_features features; 2266255736Sdavidch}; 2267255736Sdavidch 2268255736Sdavidch/* REMOTE MIB - remote machine DCBX configuration. */ 2269255736Sdavidchstruct lldp_remote_mib { 2270255736Sdavidch uint32_t prefix_seq_num; 2271255736Sdavidch uint32_t flags; 2272255736Sdavidch #define DCBX_ETS_TLV_RX 0x00000001 2273255736Sdavidch #define DCBX_PFC_TLV_RX 0x00000002 2274255736Sdavidch #define DCBX_APP_TLV_RX 0x00000004 2275255736Sdavidch #define DCBX_ETS_RX_ERROR 0x00000010 2276255736Sdavidch #define DCBX_PFC_RX_ERROR 0x00000020 2277255736Sdavidch #define DCBX_APP_RX_ERROR 0x00000040 2278255736Sdavidch #define DCBX_ETS_REM_WILLING 0x00000100 2279255736Sdavidch #define DCBX_PFC_REM_WILLING 0x00000200 2280255736Sdavidch #define DCBX_APP_REM_WILLING 0x00000400 2281255736Sdavidch #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 2282255736Sdavidch #define DCBX_REMOTE_MIB_VALID 0x00002000 2283255736Sdavidch struct dcbx_features features; 2284255736Sdavidch uint32_t suffix_seq_num; 2285255736Sdavidch}; 2286255736Sdavidch 2287255736Sdavidch/* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 2288255736Sdavidchstruct lldp_local_mib { 2289255736Sdavidch uint32_t prefix_seq_num; 2290255736Sdavidch /* Indicates if there is mismatch with negotiation results. */ 2291255736Sdavidch uint32_t error; 2292255736Sdavidch #define DCBX_LOCAL_ETS_ERROR 0x00000001 2293255736Sdavidch #define DCBX_LOCAL_PFC_ERROR 0x00000002 2294255736Sdavidch #define DCBX_LOCAL_APP_ERROR 0x00000004 2295255736Sdavidch #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 2296255736Sdavidch #define DCBX_LOCAL_APP_MISMATCH 0x00000020 2297255736Sdavidch #define DCBX_REMOTE_MIB_ERROR 0x00000040 2298255736Sdavidch #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 2299255736Sdavidch #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 2300255736Sdavidch #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 2301255736Sdavidch struct dcbx_features features; 2302255736Sdavidch uint32_t suffix_seq_num; 2303255736Sdavidch}; 2304255736Sdavidch 2305255736Sdavidchstruct lldp_local_mib_ext { 2306255736Sdavidch uint32_t prefix_seq_num; 2307255736Sdavidch /* APP TLV extension - 16 more entries for negotiation results*/ 2308255736Sdavidch struct dcbx_app_priority_entry app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL]; 2309255736Sdavidch uint32_t suffix_seq_num; 2310255736Sdavidch}; 2311255736Sdavidch/***END OF DCBX STRUCTURES DECLARATIONS***/ 2312255736Sdavidch 2313255736Sdavidch/***********************************************************/ 2314255736Sdavidch/* Elink section */ 2315255736Sdavidch/***********************************************************/ 2316255736Sdavidch#define SHMEM_LINK_CONFIG_SIZE 2 2317255736Sdavidchstruct shmem_lfa { 2318255736Sdavidch uint32_t req_duplex; 2319255736Sdavidch #define REQ_DUPLEX_PHY0_MASK 0x0000ffff 2320255736Sdavidch #define REQ_DUPLEX_PHY0_SHIFT 0 2321255736Sdavidch #define REQ_DUPLEX_PHY1_MASK 0xffff0000 2322255736Sdavidch #define REQ_DUPLEX_PHY1_SHIFT 16 2323255736Sdavidch uint32_t req_flow_ctrl; 2324255736Sdavidch #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff 2325255736Sdavidch #define REQ_FLOW_CTRL_PHY0_SHIFT 0 2326255736Sdavidch #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 2327255736Sdavidch #define REQ_FLOW_CTRL_PHY1_SHIFT 16 2328255736Sdavidch uint32_t req_line_speed; /* Also determine AutoNeg */ 2329255736Sdavidch #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff 2330255736Sdavidch #define REQ_LINE_SPD_PHY0_SHIFT 0 2331255736Sdavidch #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 2332255736Sdavidch #define REQ_LINE_SPD_PHY1_SHIFT 16 2333255736Sdavidch uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; 2334255736Sdavidch uint32_t additional_config; 2335255736Sdavidch #define REQ_FC_AUTO_ADV_MASK 0x0000ffff 2336255736Sdavidch #define REQ_FC_AUTO_ADV0_SHIFT 0 2337255736Sdavidch #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 2338255736Sdavidch uint32_t lfa_sts; 2339255736Sdavidch #define LFA_LINK_FLAP_REASON_OFFSET 0 2340255736Sdavidch #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 2341255736Sdavidch #define LFA_LINK_DOWN 0x1 2342255736Sdavidch #define LFA_LOOPBACK_ENABLED 0x2 2343255736Sdavidch #define LFA_DUPLEX_MISMATCH 0x3 2344255736Sdavidch #define LFA_MFW_IS_TOO_OLD 0x4 2345255736Sdavidch #define LFA_LINK_SPEED_MISMATCH 0x5 2346255736Sdavidch #define LFA_FLOW_CTRL_MISMATCH 0x6 2347255736Sdavidch #define LFA_SPEED_CAP_MISMATCH 0x7 2348255736Sdavidch #define LFA_DCC_LFA_DISABLED 0x8 2349255736Sdavidch #define LFA_EEE_MISMATCH 0x9 2350255736Sdavidch 2351255736Sdavidch #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 2352255736Sdavidch #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 2353255736Sdavidch 2354255736Sdavidch #define LINK_FLAP_COUNT_OFFSET 16 2355255736Sdavidch #define LINK_FLAP_COUNT_MASK 0x00ff0000 2356255736Sdavidch 2357255736Sdavidch #define LFA_FLAGS_MASK 0xff000000 2358255736Sdavidch #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) 2359255736Sdavidch 2360255736Sdavidch}; 2361255736Sdavidch 2362255736Sdavidchstruct shmem2_region { 2363255736Sdavidch 2364255736Sdavidch uint32_t size; /* 0x0000 */ 2365255736Sdavidch 2366255736Sdavidch uint32_t dcc_support; /* 0x0004 */ 2367255736Sdavidch #define SHMEM_DCC_SUPPORT_NONE 0x00000000 2368255736Sdavidch #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 2369255736Sdavidch #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 2370255736Sdavidch #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 2371255736Sdavidch #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 2372255736Sdavidch #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 2373255736Sdavidch 2374255736Sdavidch uint32_t ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 2375255736Sdavidch /* 2376255736Sdavidch * For backwards compatibility, if the mf_cfg_addr does not exist 2377255736Sdavidch * (the size filed is smaller than 0xc) the mf_cfg resides at the 2378255736Sdavidch * end of struct shmem_region 2379255736Sdavidch */ 2380255736Sdavidch uint32_t mf_cfg_addr; /* 0x0010 */ 2381255736Sdavidch #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 2382255736Sdavidch 2383255736Sdavidch struct fw_flr_mb flr_mb; /* 0x0014 */ 2384255736Sdavidch uint32_t dcbx_lldp_params_offset; /* 0x0028 */ 2385255736Sdavidch #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 2386255736Sdavidch uint32_t dcbx_neg_res_offset; /* 0x002c */ 2387255736Sdavidch #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 2388255736Sdavidch uint32_t dcbx_remote_mib_offset; /* 0x0030 */ 2389255736Sdavidch #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 2390255736Sdavidch /* 2391255736Sdavidch * The other shmemX_base_addr holds the other path's shmem address 2392255736Sdavidch * required for example in case of common phy init, or for path1 to know 2393255736Sdavidch * the address of mcp debug trace which is located in offset from shmem 2394255736Sdavidch * of path0 2395255736Sdavidch */ 2396255736Sdavidch uint32_t other_shmem_base_addr; /* 0x0034 */ 2397255736Sdavidch uint32_t other_shmem2_base_addr; /* 0x0038 */ 2398255736Sdavidch /* 2399255736Sdavidch * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 2400255736Sdavidch * which were disabled/flred 2401255736Sdavidch */ 2402255736Sdavidch uint32_t mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 2403255736Sdavidch 2404255736Sdavidch /* 2405255736Sdavidch * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 2406255736Sdavidch * VFs 2407255736Sdavidch */ 2408255736Sdavidch uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 2409255736Sdavidch 2410255736Sdavidch uint32_t dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 2411255736Sdavidch #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 2412255736Sdavidch 2413255736Sdavidch /* 2414255736Sdavidch * edebug_driver_if field is used to transfer messages between edebug 2415255736Sdavidch * app to the driver through shmem2. 2416255736Sdavidch * 2417255736Sdavidch * message format: 2418255736Sdavidch * bits 0-2 - function number / instance of driver to perform request 2419255736Sdavidch * bits 3-5 - op code / is_ack? 2420255736Sdavidch * bits 6-63 - data 2421255736Sdavidch */ 2422255736Sdavidch uint32_t edebug_driver_if[2]; /* 0x0068 */ 2423255736Sdavidch #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 2424255736Sdavidch #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 2425255736Sdavidch #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 2426255736Sdavidch 2427255736Sdavidch uint32_t nvm_retain_bitmap_addr; /* 0x0070 */ 2428255736Sdavidch 2429255736Sdavidch /* afex support of that driver */ 2430255736Sdavidch uint32_t afex_driver_support; /* 0x0074 */ 2431255736Sdavidch #define SHMEM_AFEX_VERSION_MASK 0x100f 2432255736Sdavidch #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 2433255736Sdavidch #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 2434255736Sdavidch 2435255736Sdavidch /* driver receives addr in scratchpad to which it should respond */ 2436255736Sdavidch uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX]; 2437255736Sdavidch 2438255736Sdavidch /* 2439255736Sdavidch * generic params from MCP to driver (value depends on the msg sent 2440255736Sdavidch * to driver 2441255736Sdavidch */ 2442255736Sdavidch uint32_t afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ 2443255736Sdavidch uint32_t afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ 2444255736Sdavidch 2445255736Sdavidch uint32_t swim_base_addr; /* 0x0108 */ 2446255736Sdavidch uint32_t swim_funcs; 2447255736Sdavidch uint32_t swim_main_cb; 2448255736Sdavidch 2449255736Sdavidch /* 2450255736Sdavidch * bitmap notifying which VIF profiles stored in nvram are enabled by 2451255736Sdavidch * switch 2452255736Sdavidch */ 2453255736Sdavidch uint32_t afex_profiles_enabled[2]; 2454255736Sdavidch 2455255736Sdavidch /* generic flags controlled by the driver */ 2456255736Sdavidch uint32_t drv_flags; 2457255736Sdavidch #define DRV_FLAGS_DCB_CONFIGURED 0x0 2458255736Sdavidch #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 2459255736Sdavidch #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 2460255736Sdavidch 2461255736Sdavidch #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \ 2462255736Sdavidch (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \ 2463255736Sdavidch (1 << DRV_FLAGS_DCB_MFW_CONFIGURED)) 2464255736Sdavidch /* Port offset*/ 2465255736Sdavidch #define DRV_FLAGS_P0_OFFSET 0 2466255736Sdavidch #define DRV_FLAGS_P1_OFFSET 16 2467255736Sdavidch #define DRV_FLAGS_GET_PORT_OFFSET(_port) ((0 == _port) ? \ 2468255736Sdavidch DRV_FLAGS_P0_OFFSET : \ 2469255736Sdavidch DRV_FLAGS_P1_OFFSET) 2470255736Sdavidch 2471255736Sdavidch #define DRV_FLAGS_GET_PORT_MASK(_port) (DRV_FLAGS_PORT_MASK << \ 2472255736Sdavidch DRV_FLAGS_GET_PORT_OFFSET(_port)) 2473255736Sdavidch 2474255736Sdavidch #define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port) (1 << ( \ 2475255736Sdavidch (_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port))) 2476255736Sdavidch 2477255736Sdavidch /* pointer to extended dev_info shared data copied from nvm image */ 2478255736Sdavidch uint32_t extended_dev_info_shared_addr; 2479255736Sdavidch uint32_t ncsi_oem_data_addr; 2480255736Sdavidch 2481255736Sdavidch uint32_t sensor_data_addr; 2482255736Sdavidch uint32_t buffer_block_addr; 2483255736Sdavidch uint32_t sensor_data_req_update_interval; 2484255736Sdavidch uint32_t temperature_in_half_celsius; 2485255736Sdavidch uint32_t glob_struct_in_host; 2486255736Sdavidch 2487255736Sdavidch uint32_t dcbx_neg_res_ext_offset; 2488255736Sdavidch #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 2489255736Sdavidch 2490255736Sdavidch uint32_t drv_capabilities_flag[E2_FUNC_MAX]; 2491255736Sdavidch #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 2492255736Sdavidch #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 2493255736Sdavidch #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 2494255736Sdavidch #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 2495255736Sdavidch 2496255736Sdavidch uint32_t extended_dev_info_shared_cfg_size; 2497255736Sdavidch 2498255736Sdavidch uint32_t dcbx_en[PORT_MAX]; 2499255736Sdavidch 2500255736Sdavidch /* The offset points to the multi threaded meta structure */ 2501255736Sdavidch uint32_t multi_thread_data_offset; 2502255736Sdavidch 2503255736Sdavidch /* address of DMAable host address holding values from the drivers */ 2504255736Sdavidch uint32_t drv_info_host_addr_lo; 2505255736Sdavidch uint32_t drv_info_host_addr_hi; 2506255736Sdavidch 2507255736Sdavidch /* general values written by the MFW (such as current version) */ 2508255736Sdavidch uint32_t drv_info_control; 2509255736Sdavidch #define DRV_INFO_CONTROL_VER_MASK 0x000000ff 2510255736Sdavidch #define DRV_INFO_CONTROL_VER_SHIFT 0 2511255736Sdavidch #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 2512255736Sdavidch #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 2513255736Sdavidch uint32_t ibft_host_addr; /* initialized by option ROM */ 2514255736Sdavidch 2515255736Sdavidch struct eee_remote_vals eee_remote_vals[PORT_MAX]; 2516255736Sdavidch uint32_t pf_allocation[E2_FUNC_MAX]; 2517255736Sdavidch #define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */ 2518255736Sdavidch #define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0 2519255736Sdavidch 2520255736Sdavidch /* the status of EEE auto-negotiation 2521255736Sdavidch * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. 2522255736Sdavidch * bits 19:16 the supported modes for EEE. 2523255736Sdavidch * bits 23:20 the speeds advertised for EEE. 2524255736Sdavidch * bits 27:24 the speeds the Link partner advertised for EEE. 2525255736Sdavidch * The supported/adv. modes in bits 27:19 originate from the 2526255736Sdavidch * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 2527255736Sdavidch * bit 28 when 1'b1 EEE was requested. 2528255736Sdavidch * bit 29 when 1'b1 tx lpi was requested. 2529255736Sdavidch * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff 2530255736Sdavidch * 30:29 are 2'b11. 2531255736Sdavidch * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as 2532255736Sdavidch * value. When 1'b1 those bits contains a value times 16 microseconds. 2533255736Sdavidch */ 2534255736Sdavidch uint32_t eee_status[PORT_MAX]; 2535255736Sdavidch #define SHMEM_EEE_TIMER_MASK 0x0000ffff 2536255736Sdavidch #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 2537255736Sdavidch #define SHMEM_EEE_SUPPORTED_SHIFT 16 2538255736Sdavidch #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 2539255736Sdavidch #define SHMEM_EEE_100M_ADV (1<<0) 2540255736Sdavidch #define SHMEM_EEE_1G_ADV (1<<1) 2541255736Sdavidch #define SHMEM_EEE_10G_ADV (1<<2) 2542255736Sdavidch #define SHMEM_EEE_ADV_STATUS_SHIFT 20 2543255736Sdavidch #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 2544255736Sdavidch #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 2545255736Sdavidch #define SHMEM_EEE_REQUESTED_BIT 0x10000000 2546255736Sdavidch #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 2547255736Sdavidch #define SHMEM_EEE_ACTIVE_BIT 0x40000000 2548255736Sdavidch #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 2549255736Sdavidch 2550255736Sdavidch uint32_t sizeof_port_stats; 2551255736Sdavidch 2552255736Sdavidch /* Link Flap Avoidance */ 2553255736Sdavidch uint32_t lfa_host_addr[PORT_MAX]; 2554255736Sdavidch 2555255736Sdavidch /* External PHY temperature in deg C. */ 2556255736Sdavidch uint32_t extphy_temps_in_celsius; 2557255736Sdavidch #define EXTPHY1_TEMP_MASK 0x0000ffff 2558255736Sdavidch #define EXTPHY1_TEMP_SHIFT 0 2559255736Sdavidch 2560255736Sdavidch uint32_t ocdata_info_addr; /* Offset 0x148 */ 2561255736Sdavidch uint32_t drv_func_info_addr; /* Offset 0x14C */ 2562255736Sdavidch uint32_t drv_func_info_size; /* Offset 0x150 */ 2563255736Sdavidch uint32_t link_attr_sync[PORT_MAX]; /* Offset 0x154 */ 2564255736Sdavidch #define LINK_ATTR_SYNC_KR2_ENABLE (1<<0) 2565260252Sedavis 2566260252Sedavis uint32_t ibft_host_addr_hi; /* Initialize by uEFI ROM */ 2567255736Sdavidch}; 2568255736Sdavidch 2569255736Sdavidch 2570255736Sdavidchstruct emac_stats { 2571255736Sdavidch uint32_t rx_stat_ifhcinoctets; 2572255736Sdavidch uint32_t rx_stat_ifhcinbadoctets; 2573255736Sdavidch uint32_t rx_stat_etherstatsfragments; 2574255736Sdavidch uint32_t rx_stat_ifhcinucastpkts; 2575255736Sdavidch uint32_t rx_stat_ifhcinmulticastpkts; 2576255736Sdavidch uint32_t rx_stat_ifhcinbroadcastpkts; 2577255736Sdavidch uint32_t rx_stat_dot3statsfcserrors; 2578255736Sdavidch uint32_t rx_stat_dot3statsalignmenterrors; 2579255736Sdavidch uint32_t rx_stat_dot3statscarriersenseerrors; 2580255736Sdavidch uint32_t rx_stat_xonpauseframesreceived; 2581255736Sdavidch uint32_t rx_stat_xoffpauseframesreceived; 2582255736Sdavidch uint32_t rx_stat_maccontrolframesreceived; 2583255736Sdavidch uint32_t rx_stat_xoffstateentered; 2584255736Sdavidch uint32_t rx_stat_dot3statsframestoolong; 2585255736Sdavidch uint32_t rx_stat_etherstatsjabbers; 2586255736Sdavidch uint32_t rx_stat_etherstatsundersizepkts; 2587255736Sdavidch uint32_t rx_stat_etherstatspkts64octets; 2588255736Sdavidch uint32_t rx_stat_etherstatspkts65octetsto127octets; 2589255736Sdavidch uint32_t rx_stat_etherstatspkts128octetsto255octets; 2590255736Sdavidch uint32_t rx_stat_etherstatspkts256octetsto511octets; 2591255736Sdavidch uint32_t rx_stat_etherstatspkts512octetsto1023octets; 2592255736Sdavidch uint32_t rx_stat_etherstatspkts1024octetsto1522octets; 2593255736Sdavidch uint32_t rx_stat_etherstatspktsover1522octets; 2594255736Sdavidch 2595255736Sdavidch uint32_t rx_stat_falsecarriererrors; 2596255736Sdavidch 2597255736Sdavidch uint32_t tx_stat_ifhcoutoctets; 2598255736Sdavidch uint32_t tx_stat_ifhcoutbadoctets; 2599255736Sdavidch uint32_t tx_stat_etherstatscollisions; 2600255736Sdavidch uint32_t tx_stat_outxonsent; 2601255736Sdavidch uint32_t tx_stat_outxoffsent; 2602255736Sdavidch uint32_t tx_stat_flowcontroldone; 2603255736Sdavidch uint32_t tx_stat_dot3statssinglecollisionframes; 2604255736Sdavidch uint32_t tx_stat_dot3statsmultiplecollisionframes; 2605255736Sdavidch uint32_t tx_stat_dot3statsdeferredtransmissions; 2606255736Sdavidch uint32_t tx_stat_dot3statsexcessivecollisions; 2607255736Sdavidch uint32_t tx_stat_dot3statslatecollisions; 2608255736Sdavidch uint32_t tx_stat_ifhcoutucastpkts; 2609255736Sdavidch uint32_t tx_stat_ifhcoutmulticastpkts; 2610255736Sdavidch uint32_t tx_stat_ifhcoutbroadcastpkts; 2611255736Sdavidch uint32_t tx_stat_etherstatspkts64octets; 2612255736Sdavidch uint32_t tx_stat_etherstatspkts65octetsto127octets; 2613255736Sdavidch uint32_t tx_stat_etherstatspkts128octetsto255octets; 2614255736Sdavidch uint32_t tx_stat_etherstatspkts256octetsto511octets; 2615255736Sdavidch uint32_t tx_stat_etherstatspkts512octetsto1023octets; 2616255736Sdavidch uint32_t tx_stat_etherstatspkts1024octetsto1522octets; 2617255736Sdavidch uint32_t tx_stat_etherstatspktsover1522octets; 2618255736Sdavidch uint32_t tx_stat_dot3statsinternalmactransmiterrors; 2619255736Sdavidch}; 2620255736Sdavidch 2621255736Sdavidch 2622255736Sdavidchstruct bmac1_stats { 2623255736Sdavidch uint32_t tx_stat_gtpkt_lo; 2624255736Sdavidch uint32_t tx_stat_gtpkt_hi; 2625255736Sdavidch uint32_t tx_stat_gtxpf_lo; 2626255736Sdavidch uint32_t tx_stat_gtxpf_hi; 2627255736Sdavidch uint32_t tx_stat_gtfcs_lo; 2628255736Sdavidch uint32_t tx_stat_gtfcs_hi; 2629255736Sdavidch uint32_t tx_stat_gtmca_lo; 2630255736Sdavidch uint32_t tx_stat_gtmca_hi; 2631255736Sdavidch uint32_t tx_stat_gtbca_lo; 2632255736Sdavidch uint32_t tx_stat_gtbca_hi; 2633255736Sdavidch uint32_t tx_stat_gtfrg_lo; 2634255736Sdavidch uint32_t tx_stat_gtfrg_hi; 2635255736Sdavidch uint32_t tx_stat_gtovr_lo; 2636255736Sdavidch uint32_t tx_stat_gtovr_hi; 2637255736Sdavidch uint32_t tx_stat_gt64_lo; 2638255736Sdavidch uint32_t tx_stat_gt64_hi; 2639255736Sdavidch uint32_t tx_stat_gt127_lo; 2640255736Sdavidch uint32_t tx_stat_gt127_hi; 2641255736Sdavidch uint32_t tx_stat_gt255_lo; 2642255736Sdavidch uint32_t tx_stat_gt255_hi; 2643255736Sdavidch uint32_t tx_stat_gt511_lo; 2644255736Sdavidch uint32_t tx_stat_gt511_hi; 2645255736Sdavidch uint32_t tx_stat_gt1023_lo; 2646255736Sdavidch uint32_t tx_stat_gt1023_hi; 2647255736Sdavidch uint32_t tx_stat_gt1518_lo; 2648255736Sdavidch uint32_t tx_stat_gt1518_hi; 2649255736Sdavidch uint32_t tx_stat_gt2047_lo; 2650255736Sdavidch uint32_t tx_stat_gt2047_hi; 2651255736Sdavidch uint32_t tx_stat_gt4095_lo; 2652255736Sdavidch uint32_t tx_stat_gt4095_hi; 2653255736Sdavidch uint32_t tx_stat_gt9216_lo; 2654255736Sdavidch uint32_t tx_stat_gt9216_hi; 2655255736Sdavidch uint32_t tx_stat_gt16383_lo; 2656255736Sdavidch uint32_t tx_stat_gt16383_hi; 2657255736Sdavidch uint32_t tx_stat_gtmax_lo; 2658255736Sdavidch uint32_t tx_stat_gtmax_hi; 2659255736Sdavidch uint32_t tx_stat_gtufl_lo; 2660255736Sdavidch uint32_t tx_stat_gtufl_hi; 2661255736Sdavidch uint32_t tx_stat_gterr_lo; 2662255736Sdavidch uint32_t tx_stat_gterr_hi; 2663255736Sdavidch uint32_t tx_stat_gtbyt_lo; 2664255736Sdavidch uint32_t tx_stat_gtbyt_hi; 2665255736Sdavidch 2666255736Sdavidch uint32_t rx_stat_gr64_lo; 2667255736Sdavidch uint32_t rx_stat_gr64_hi; 2668255736Sdavidch uint32_t rx_stat_gr127_lo; 2669255736Sdavidch uint32_t rx_stat_gr127_hi; 2670255736Sdavidch uint32_t rx_stat_gr255_lo; 2671255736Sdavidch uint32_t rx_stat_gr255_hi; 2672255736Sdavidch uint32_t rx_stat_gr511_lo; 2673255736Sdavidch uint32_t rx_stat_gr511_hi; 2674255736Sdavidch uint32_t rx_stat_gr1023_lo; 2675255736Sdavidch uint32_t rx_stat_gr1023_hi; 2676255736Sdavidch uint32_t rx_stat_gr1518_lo; 2677255736Sdavidch uint32_t rx_stat_gr1518_hi; 2678255736Sdavidch uint32_t rx_stat_gr2047_lo; 2679255736Sdavidch uint32_t rx_stat_gr2047_hi; 2680255736Sdavidch uint32_t rx_stat_gr4095_lo; 2681255736Sdavidch uint32_t rx_stat_gr4095_hi; 2682255736Sdavidch uint32_t rx_stat_gr9216_lo; 2683255736Sdavidch uint32_t rx_stat_gr9216_hi; 2684255736Sdavidch uint32_t rx_stat_gr16383_lo; 2685255736Sdavidch uint32_t rx_stat_gr16383_hi; 2686255736Sdavidch uint32_t rx_stat_grmax_lo; 2687255736Sdavidch uint32_t rx_stat_grmax_hi; 2688255736Sdavidch uint32_t rx_stat_grpkt_lo; 2689255736Sdavidch uint32_t rx_stat_grpkt_hi; 2690255736Sdavidch uint32_t rx_stat_grfcs_lo; 2691255736Sdavidch uint32_t rx_stat_grfcs_hi; 2692255736Sdavidch uint32_t rx_stat_grmca_lo; 2693255736Sdavidch uint32_t rx_stat_grmca_hi; 2694255736Sdavidch uint32_t rx_stat_grbca_lo; 2695255736Sdavidch uint32_t rx_stat_grbca_hi; 2696255736Sdavidch uint32_t rx_stat_grxcf_lo; 2697255736Sdavidch uint32_t rx_stat_grxcf_hi; 2698255736Sdavidch uint32_t rx_stat_grxpf_lo; 2699255736Sdavidch uint32_t rx_stat_grxpf_hi; 2700255736Sdavidch uint32_t rx_stat_grxuo_lo; 2701255736Sdavidch uint32_t rx_stat_grxuo_hi; 2702255736Sdavidch uint32_t rx_stat_grjbr_lo; 2703255736Sdavidch uint32_t rx_stat_grjbr_hi; 2704255736Sdavidch uint32_t rx_stat_grovr_lo; 2705255736Sdavidch uint32_t rx_stat_grovr_hi; 2706255736Sdavidch uint32_t rx_stat_grflr_lo; 2707255736Sdavidch uint32_t rx_stat_grflr_hi; 2708255736Sdavidch uint32_t rx_stat_grmeg_lo; 2709255736Sdavidch uint32_t rx_stat_grmeg_hi; 2710255736Sdavidch uint32_t rx_stat_grmeb_lo; 2711255736Sdavidch uint32_t rx_stat_grmeb_hi; 2712255736Sdavidch uint32_t rx_stat_grbyt_lo; 2713255736Sdavidch uint32_t rx_stat_grbyt_hi; 2714255736Sdavidch uint32_t rx_stat_grund_lo; 2715255736Sdavidch uint32_t rx_stat_grund_hi; 2716255736Sdavidch uint32_t rx_stat_grfrg_lo; 2717255736Sdavidch uint32_t rx_stat_grfrg_hi; 2718255736Sdavidch uint32_t rx_stat_grerb_lo; 2719255736Sdavidch uint32_t rx_stat_grerb_hi; 2720255736Sdavidch uint32_t rx_stat_grfre_lo; 2721255736Sdavidch uint32_t rx_stat_grfre_hi; 2722255736Sdavidch uint32_t rx_stat_gripj_lo; 2723255736Sdavidch uint32_t rx_stat_gripj_hi; 2724255736Sdavidch}; 2725255736Sdavidch 2726255736Sdavidchstruct bmac2_stats { 2727255736Sdavidch uint32_t tx_stat_gtpk_lo; /* gtpok */ 2728255736Sdavidch uint32_t tx_stat_gtpk_hi; /* gtpok */ 2729255736Sdavidch uint32_t tx_stat_gtxpf_lo; /* gtpf */ 2730255736Sdavidch uint32_t tx_stat_gtxpf_hi; /* gtpf */ 2731255736Sdavidch uint32_t tx_stat_gtpp_lo; /* NEW BMAC2 */ 2732255736Sdavidch uint32_t tx_stat_gtpp_hi; /* NEW BMAC2 */ 2733255736Sdavidch uint32_t tx_stat_gtfcs_lo; 2734255736Sdavidch uint32_t tx_stat_gtfcs_hi; 2735255736Sdavidch uint32_t tx_stat_gtuca_lo; /* NEW BMAC2 */ 2736255736Sdavidch uint32_t tx_stat_gtuca_hi; /* NEW BMAC2 */ 2737255736Sdavidch uint32_t tx_stat_gtmca_lo; 2738255736Sdavidch uint32_t tx_stat_gtmca_hi; 2739255736Sdavidch uint32_t tx_stat_gtbca_lo; 2740255736Sdavidch uint32_t tx_stat_gtbca_hi; 2741255736Sdavidch uint32_t tx_stat_gtovr_lo; 2742255736Sdavidch uint32_t tx_stat_gtovr_hi; 2743255736Sdavidch uint32_t tx_stat_gtfrg_lo; 2744255736Sdavidch uint32_t tx_stat_gtfrg_hi; 2745255736Sdavidch uint32_t tx_stat_gtpkt1_lo; /* gtpkt */ 2746255736Sdavidch uint32_t tx_stat_gtpkt1_hi; /* gtpkt */ 2747255736Sdavidch uint32_t tx_stat_gt64_lo; 2748255736Sdavidch uint32_t tx_stat_gt64_hi; 2749255736Sdavidch uint32_t tx_stat_gt127_lo; 2750255736Sdavidch uint32_t tx_stat_gt127_hi; 2751255736Sdavidch uint32_t tx_stat_gt255_lo; 2752255736Sdavidch uint32_t tx_stat_gt255_hi; 2753255736Sdavidch uint32_t tx_stat_gt511_lo; 2754255736Sdavidch uint32_t tx_stat_gt511_hi; 2755255736Sdavidch uint32_t tx_stat_gt1023_lo; 2756255736Sdavidch uint32_t tx_stat_gt1023_hi; 2757255736Sdavidch uint32_t tx_stat_gt1518_lo; 2758255736Sdavidch uint32_t tx_stat_gt1518_hi; 2759255736Sdavidch uint32_t tx_stat_gt2047_lo; 2760255736Sdavidch uint32_t tx_stat_gt2047_hi; 2761255736Sdavidch uint32_t tx_stat_gt4095_lo; 2762255736Sdavidch uint32_t tx_stat_gt4095_hi; 2763255736Sdavidch uint32_t tx_stat_gt9216_lo; 2764255736Sdavidch uint32_t tx_stat_gt9216_hi; 2765255736Sdavidch uint32_t tx_stat_gt16383_lo; 2766255736Sdavidch uint32_t tx_stat_gt16383_hi; 2767255736Sdavidch uint32_t tx_stat_gtmax_lo; 2768255736Sdavidch uint32_t tx_stat_gtmax_hi; 2769255736Sdavidch uint32_t tx_stat_gtufl_lo; 2770255736Sdavidch uint32_t tx_stat_gtufl_hi; 2771255736Sdavidch uint32_t tx_stat_gterr_lo; 2772255736Sdavidch uint32_t tx_stat_gterr_hi; 2773255736Sdavidch uint32_t tx_stat_gtbyt_lo; 2774255736Sdavidch uint32_t tx_stat_gtbyt_hi; 2775255736Sdavidch 2776255736Sdavidch uint32_t rx_stat_gr64_lo; 2777255736Sdavidch uint32_t rx_stat_gr64_hi; 2778255736Sdavidch uint32_t rx_stat_gr127_lo; 2779255736Sdavidch uint32_t rx_stat_gr127_hi; 2780255736Sdavidch uint32_t rx_stat_gr255_lo; 2781255736Sdavidch uint32_t rx_stat_gr255_hi; 2782255736Sdavidch uint32_t rx_stat_gr511_lo; 2783255736Sdavidch uint32_t rx_stat_gr511_hi; 2784255736Sdavidch uint32_t rx_stat_gr1023_lo; 2785255736Sdavidch uint32_t rx_stat_gr1023_hi; 2786255736Sdavidch uint32_t rx_stat_gr1518_lo; 2787255736Sdavidch uint32_t rx_stat_gr1518_hi; 2788255736Sdavidch uint32_t rx_stat_gr2047_lo; 2789255736Sdavidch uint32_t rx_stat_gr2047_hi; 2790255736Sdavidch uint32_t rx_stat_gr4095_lo; 2791255736Sdavidch uint32_t rx_stat_gr4095_hi; 2792255736Sdavidch uint32_t rx_stat_gr9216_lo; 2793255736Sdavidch uint32_t rx_stat_gr9216_hi; 2794255736Sdavidch uint32_t rx_stat_gr16383_lo; 2795255736Sdavidch uint32_t rx_stat_gr16383_hi; 2796255736Sdavidch uint32_t rx_stat_grmax_lo; 2797255736Sdavidch uint32_t rx_stat_grmax_hi; 2798255736Sdavidch uint32_t rx_stat_grpkt_lo; 2799255736Sdavidch uint32_t rx_stat_grpkt_hi; 2800255736Sdavidch uint32_t rx_stat_grfcs_lo; 2801255736Sdavidch uint32_t rx_stat_grfcs_hi; 2802255736Sdavidch uint32_t rx_stat_gruca_lo; 2803255736Sdavidch uint32_t rx_stat_gruca_hi; 2804255736Sdavidch uint32_t rx_stat_grmca_lo; 2805255736Sdavidch uint32_t rx_stat_grmca_hi; 2806255736Sdavidch uint32_t rx_stat_grbca_lo; 2807255736Sdavidch uint32_t rx_stat_grbca_hi; 2808255736Sdavidch uint32_t rx_stat_grxpf_lo; /* grpf */ 2809255736Sdavidch uint32_t rx_stat_grxpf_hi; /* grpf */ 2810255736Sdavidch uint32_t rx_stat_grpp_lo; 2811255736Sdavidch uint32_t rx_stat_grpp_hi; 2812255736Sdavidch uint32_t rx_stat_grxuo_lo; /* gruo */ 2813255736Sdavidch uint32_t rx_stat_grxuo_hi; /* gruo */ 2814255736Sdavidch uint32_t rx_stat_grjbr_lo; 2815255736Sdavidch uint32_t rx_stat_grjbr_hi; 2816255736Sdavidch uint32_t rx_stat_grovr_lo; 2817255736Sdavidch uint32_t rx_stat_grovr_hi; 2818255736Sdavidch uint32_t rx_stat_grxcf_lo; /* grcf */ 2819255736Sdavidch uint32_t rx_stat_grxcf_hi; /* grcf */ 2820255736Sdavidch uint32_t rx_stat_grflr_lo; 2821255736Sdavidch uint32_t rx_stat_grflr_hi; 2822255736Sdavidch uint32_t rx_stat_grpok_lo; 2823255736Sdavidch uint32_t rx_stat_grpok_hi; 2824255736Sdavidch uint32_t rx_stat_grmeg_lo; 2825255736Sdavidch uint32_t rx_stat_grmeg_hi; 2826255736Sdavidch uint32_t rx_stat_grmeb_lo; 2827255736Sdavidch uint32_t rx_stat_grmeb_hi; 2828255736Sdavidch uint32_t rx_stat_grbyt_lo; 2829255736Sdavidch uint32_t rx_stat_grbyt_hi; 2830255736Sdavidch uint32_t rx_stat_grund_lo; 2831255736Sdavidch uint32_t rx_stat_grund_hi; 2832255736Sdavidch uint32_t rx_stat_grfrg_lo; 2833255736Sdavidch uint32_t rx_stat_grfrg_hi; 2834255736Sdavidch uint32_t rx_stat_grerb_lo; /* grerrbyt */ 2835255736Sdavidch uint32_t rx_stat_grerb_hi; /* grerrbyt */ 2836255736Sdavidch uint32_t rx_stat_grfre_lo; /* grfrerr */ 2837255736Sdavidch uint32_t rx_stat_grfre_hi; /* grfrerr */ 2838255736Sdavidch uint32_t rx_stat_gripj_lo; 2839255736Sdavidch uint32_t rx_stat_gripj_hi; 2840255736Sdavidch}; 2841255736Sdavidch 2842255736Sdavidchstruct mstat_stats { 2843255736Sdavidch struct { 2844255736Sdavidch /* OTE MSTAT on E3 has a bug where this register's contents are 2845255736Sdavidch * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 2846255736Sdavidch */ 2847255736Sdavidch uint32_t tx_gtxpok_lo; 2848255736Sdavidch uint32_t tx_gtxpok_hi; 2849255736Sdavidch uint32_t tx_gtxpf_lo; 2850255736Sdavidch uint32_t tx_gtxpf_hi; 2851255736Sdavidch uint32_t tx_gtxpp_lo; 2852255736Sdavidch uint32_t tx_gtxpp_hi; 2853255736Sdavidch uint32_t tx_gtfcs_lo; 2854255736Sdavidch uint32_t tx_gtfcs_hi; 2855255736Sdavidch uint32_t tx_gtuca_lo; 2856255736Sdavidch uint32_t tx_gtuca_hi; 2857255736Sdavidch uint32_t tx_gtmca_lo; 2858255736Sdavidch uint32_t tx_gtmca_hi; 2859255736Sdavidch uint32_t tx_gtgca_lo; 2860255736Sdavidch uint32_t tx_gtgca_hi; 2861255736Sdavidch uint32_t tx_gtpkt_lo; 2862255736Sdavidch uint32_t tx_gtpkt_hi; 2863255736Sdavidch uint32_t tx_gt64_lo; 2864255736Sdavidch uint32_t tx_gt64_hi; 2865255736Sdavidch uint32_t tx_gt127_lo; 2866255736Sdavidch uint32_t tx_gt127_hi; 2867255736Sdavidch uint32_t tx_gt255_lo; 2868255736Sdavidch uint32_t tx_gt255_hi; 2869255736Sdavidch uint32_t tx_gt511_lo; 2870255736Sdavidch uint32_t tx_gt511_hi; 2871255736Sdavidch uint32_t tx_gt1023_lo; 2872255736Sdavidch uint32_t tx_gt1023_hi; 2873255736Sdavidch uint32_t tx_gt1518_lo; 2874255736Sdavidch uint32_t tx_gt1518_hi; 2875255736Sdavidch uint32_t tx_gt2047_lo; 2876255736Sdavidch uint32_t tx_gt2047_hi; 2877255736Sdavidch uint32_t tx_gt4095_lo; 2878255736Sdavidch uint32_t tx_gt4095_hi; 2879255736Sdavidch uint32_t tx_gt9216_lo; 2880255736Sdavidch uint32_t tx_gt9216_hi; 2881255736Sdavidch uint32_t tx_gt16383_lo; 2882255736Sdavidch uint32_t tx_gt16383_hi; 2883255736Sdavidch uint32_t tx_gtufl_lo; 2884255736Sdavidch uint32_t tx_gtufl_hi; 2885255736Sdavidch uint32_t tx_gterr_lo; 2886255736Sdavidch uint32_t tx_gterr_hi; 2887255736Sdavidch uint32_t tx_gtbyt_lo; 2888255736Sdavidch uint32_t tx_gtbyt_hi; 2889255736Sdavidch uint32_t tx_collisions_lo; 2890255736Sdavidch uint32_t tx_collisions_hi; 2891255736Sdavidch uint32_t tx_singlecollision_lo; 2892255736Sdavidch uint32_t tx_singlecollision_hi; 2893255736Sdavidch uint32_t tx_multiplecollisions_lo; 2894255736Sdavidch uint32_t tx_multiplecollisions_hi; 2895255736Sdavidch uint32_t tx_deferred_lo; 2896255736Sdavidch uint32_t tx_deferred_hi; 2897255736Sdavidch uint32_t tx_excessivecollisions_lo; 2898255736Sdavidch uint32_t tx_excessivecollisions_hi; 2899255736Sdavidch uint32_t tx_latecollisions_lo; 2900255736Sdavidch uint32_t tx_latecollisions_hi; 2901255736Sdavidch } stats_tx; 2902255736Sdavidch 2903255736Sdavidch struct { 2904255736Sdavidch uint32_t rx_gr64_lo; 2905255736Sdavidch uint32_t rx_gr64_hi; 2906255736Sdavidch uint32_t rx_gr127_lo; 2907255736Sdavidch uint32_t rx_gr127_hi; 2908255736Sdavidch uint32_t rx_gr255_lo; 2909255736Sdavidch uint32_t rx_gr255_hi; 2910255736Sdavidch uint32_t rx_gr511_lo; 2911255736Sdavidch uint32_t rx_gr511_hi; 2912255736Sdavidch uint32_t rx_gr1023_lo; 2913255736Sdavidch uint32_t rx_gr1023_hi; 2914255736Sdavidch uint32_t rx_gr1518_lo; 2915255736Sdavidch uint32_t rx_gr1518_hi; 2916255736Sdavidch uint32_t rx_gr2047_lo; 2917255736Sdavidch uint32_t rx_gr2047_hi; 2918255736Sdavidch uint32_t rx_gr4095_lo; 2919255736Sdavidch uint32_t rx_gr4095_hi; 2920255736Sdavidch uint32_t rx_gr9216_lo; 2921255736Sdavidch uint32_t rx_gr9216_hi; 2922255736Sdavidch uint32_t rx_gr16383_lo; 2923255736Sdavidch uint32_t rx_gr16383_hi; 2924255736Sdavidch uint32_t rx_grpkt_lo; 2925255736Sdavidch uint32_t rx_grpkt_hi; 2926255736Sdavidch uint32_t rx_grfcs_lo; 2927255736Sdavidch uint32_t rx_grfcs_hi; 2928255736Sdavidch uint32_t rx_gruca_lo; 2929255736Sdavidch uint32_t rx_gruca_hi; 2930255736Sdavidch uint32_t rx_grmca_lo; 2931255736Sdavidch uint32_t rx_grmca_hi; 2932255736Sdavidch uint32_t rx_grbca_lo; 2933255736Sdavidch uint32_t rx_grbca_hi; 2934255736Sdavidch uint32_t rx_grxpf_lo; 2935255736Sdavidch uint32_t rx_grxpf_hi; 2936255736Sdavidch uint32_t rx_grxpp_lo; 2937255736Sdavidch uint32_t rx_grxpp_hi; 2938255736Sdavidch uint32_t rx_grxuo_lo; 2939255736Sdavidch uint32_t rx_grxuo_hi; 2940255736Sdavidch uint32_t rx_grovr_lo; 2941255736Sdavidch uint32_t rx_grovr_hi; 2942255736Sdavidch uint32_t rx_grxcf_lo; 2943255736Sdavidch uint32_t rx_grxcf_hi; 2944255736Sdavidch uint32_t rx_grflr_lo; 2945255736Sdavidch uint32_t rx_grflr_hi; 2946255736Sdavidch uint32_t rx_grpok_lo; 2947255736Sdavidch uint32_t rx_grpok_hi; 2948255736Sdavidch uint32_t rx_grbyt_lo; 2949255736Sdavidch uint32_t rx_grbyt_hi; 2950255736Sdavidch uint32_t rx_grund_lo; 2951255736Sdavidch uint32_t rx_grund_hi; 2952255736Sdavidch uint32_t rx_grfrg_lo; 2953255736Sdavidch uint32_t rx_grfrg_hi; 2954255736Sdavidch uint32_t rx_grerb_lo; 2955255736Sdavidch uint32_t rx_grerb_hi; 2956255736Sdavidch uint32_t rx_grfre_lo; 2957255736Sdavidch uint32_t rx_grfre_hi; 2958255736Sdavidch 2959255736Sdavidch uint32_t rx_alignmenterrors_lo; 2960255736Sdavidch uint32_t rx_alignmenterrors_hi; 2961255736Sdavidch uint32_t rx_falsecarrier_lo; 2962255736Sdavidch uint32_t rx_falsecarrier_hi; 2963255736Sdavidch uint32_t rx_llfcmsgcnt_lo; 2964255736Sdavidch uint32_t rx_llfcmsgcnt_hi; 2965255736Sdavidch } stats_rx; 2966255736Sdavidch}; 2967255736Sdavidch 2968255736Sdavidchunion mac_stats { 2969255736Sdavidch struct emac_stats emac_stats; 2970255736Sdavidch struct bmac1_stats bmac1_stats; 2971255736Sdavidch struct bmac2_stats bmac2_stats; 2972255736Sdavidch struct mstat_stats mstat_stats; 2973255736Sdavidch}; 2974255736Sdavidch 2975255736Sdavidch 2976255736Sdavidchstruct mac_stx { 2977255736Sdavidch /* in_bad_octets */ 2978255736Sdavidch uint32_t rx_stat_ifhcinbadoctets_hi; 2979255736Sdavidch uint32_t rx_stat_ifhcinbadoctets_lo; 2980255736Sdavidch 2981255736Sdavidch /* out_bad_octets */ 2982255736Sdavidch uint32_t tx_stat_ifhcoutbadoctets_hi; 2983255736Sdavidch uint32_t tx_stat_ifhcoutbadoctets_lo; 2984255736Sdavidch 2985255736Sdavidch /* crc_receive_errors */ 2986255736Sdavidch uint32_t rx_stat_dot3statsfcserrors_hi; 2987255736Sdavidch uint32_t rx_stat_dot3statsfcserrors_lo; 2988255736Sdavidch /* alignment_errors */ 2989255736Sdavidch uint32_t rx_stat_dot3statsalignmenterrors_hi; 2990255736Sdavidch uint32_t rx_stat_dot3statsalignmenterrors_lo; 2991255736Sdavidch /* carrier_sense_errors */ 2992255736Sdavidch uint32_t rx_stat_dot3statscarriersenseerrors_hi; 2993255736Sdavidch uint32_t rx_stat_dot3statscarriersenseerrors_lo; 2994255736Sdavidch /* false_carrier_detections */ 2995255736Sdavidch uint32_t rx_stat_falsecarriererrors_hi; 2996255736Sdavidch uint32_t rx_stat_falsecarriererrors_lo; 2997255736Sdavidch 2998255736Sdavidch /* runt_packets_received */ 2999255736Sdavidch uint32_t rx_stat_etherstatsundersizepkts_hi; 3000255736Sdavidch uint32_t rx_stat_etherstatsundersizepkts_lo; 3001255736Sdavidch /* jabber_packets_received */ 3002255736Sdavidch uint32_t rx_stat_dot3statsframestoolong_hi; 3003255736Sdavidch uint32_t rx_stat_dot3statsframestoolong_lo; 3004255736Sdavidch 3005255736Sdavidch /* error_runt_packets_received */ 3006255736Sdavidch uint32_t rx_stat_etherstatsfragments_hi; 3007255736Sdavidch uint32_t rx_stat_etherstatsfragments_lo; 3008255736Sdavidch /* error_jabber_packets_received */ 3009255736Sdavidch uint32_t rx_stat_etherstatsjabbers_hi; 3010255736Sdavidch uint32_t rx_stat_etherstatsjabbers_lo; 3011255736Sdavidch 3012255736Sdavidch /* control_frames_received */ 3013255736Sdavidch uint32_t rx_stat_maccontrolframesreceived_hi; 3014255736Sdavidch uint32_t rx_stat_maccontrolframesreceived_lo; 3015255736Sdavidch uint32_t rx_stat_mac_xpf_hi; 3016255736Sdavidch uint32_t rx_stat_mac_xpf_lo; 3017255736Sdavidch uint32_t rx_stat_mac_xcf_hi; 3018255736Sdavidch uint32_t rx_stat_mac_xcf_lo; 3019255736Sdavidch 3020255736Sdavidch /* xoff_state_entered */ 3021255736Sdavidch uint32_t rx_stat_xoffstateentered_hi; 3022255736Sdavidch uint32_t rx_stat_xoffstateentered_lo; 3023255736Sdavidch /* pause_xon_frames_received */ 3024255736Sdavidch uint32_t rx_stat_xonpauseframesreceived_hi; 3025255736Sdavidch uint32_t rx_stat_xonpauseframesreceived_lo; 3026255736Sdavidch /* pause_xoff_frames_received */ 3027255736Sdavidch uint32_t rx_stat_xoffpauseframesreceived_hi; 3028255736Sdavidch uint32_t rx_stat_xoffpauseframesreceived_lo; 3029255736Sdavidch /* pause_xon_frames_transmitted */ 3030255736Sdavidch uint32_t tx_stat_outxonsent_hi; 3031255736Sdavidch uint32_t tx_stat_outxonsent_lo; 3032255736Sdavidch /* pause_xoff_frames_transmitted */ 3033255736Sdavidch uint32_t tx_stat_outxoffsent_hi; 3034255736Sdavidch uint32_t tx_stat_outxoffsent_lo; 3035255736Sdavidch /* flow_control_done */ 3036255736Sdavidch uint32_t tx_stat_flowcontroldone_hi; 3037255736Sdavidch uint32_t tx_stat_flowcontroldone_lo; 3038255736Sdavidch 3039255736Sdavidch /* ether_stats_collisions */ 3040255736Sdavidch uint32_t tx_stat_etherstatscollisions_hi; 3041255736Sdavidch uint32_t tx_stat_etherstatscollisions_lo; 3042255736Sdavidch /* single_collision_transmit_frames */ 3043255736Sdavidch uint32_t tx_stat_dot3statssinglecollisionframes_hi; 3044255736Sdavidch uint32_t tx_stat_dot3statssinglecollisionframes_lo; 3045255736Sdavidch /* multiple_collision_transmit_frames */ 3046255736Sdavidch uint32_t tx_stat_dot3statsmultiplecollisionframes_hi; 3047255736Sdavidch uint32_t tx_stat_dot3statsmultiplecollisionframes_lo; 3048255736Sdavidch /* deferred_transmissions */ 3049255736Sdavidch uint32_t tx_stat_dot3statsdeferredtransmissions_hi; 3050255736Sdavidch uint32_t tx_stat_dot3statsdeferredtransmissions_lo; 3051255736Sdavidch /* excessive_collision_frames */ 3052255736Sdavidch uint32_t tx_stat_dot3statsexcessivecollisions_hi; 3053255736Sdavidch uint32_t tx_stat_dot3statsexcessivecollisions_lo; 3054255736Sdavidch /* late_collision_frames */ 3055255736Sdavidch uint32_t tx_stat_dot3statslatecollisions_hi; 3056255736Sdavidch uint32_t tx_stat_dot3statslatecollisions_lo; 3057255736Sdavidch 3058255736Sdavidch /* frames_transmitted_64_bytes */ 3059255736Sdavidch uint32_t tx_stat_etherstatspkts64octets_hi; 3060255736Sdavidch uint32_t tx_stat_etherstatspkts64octets_lo; 3061255736Sdavidch /* frames_transmitted_65_127_bytes */ 3062255736Sdavidch uint32_t tx_stat_etherstatspkts65octetsto127octets_hi; 3063255736Sdavidch uint32_t tx_stat_etherstatspkts65octetsto127octets_lo; 3064255736Sdavidch /* frames_transmitted_128_255_bytes */ 3065255736Sdavidch uint32_t tx_stat_etherstatspkts128octetsto255octets_hi; 3066255736Sdavidch uint32_t tx_stat_etherstatspkts128octetsto255octets_lo; 3067255736Sdavidch /* frames_transmitted_256_511_bytes */ 3068255736Sdavidch uint32_t tx_stat_etherstatspkts256octetsto511octets_hi; 3069255736Sdavidch uint32_t tx_stat_etherstatspkts256octetsto511octets_lo; 3070255736Sdavidch /* frames_transmitted_512_1023_bytes */ 3071255736Sdavidch uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi; 3072255736Sdavidch uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo; 3073255736Sdavidch /* frames_transmitted_1024_1522_bytes */ 3074255736Sdavidch uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi; 3075255736Sdavidch uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo; 3076255736Sdavidch /* frames_transmitted_1523_9022_bytes */ 3077255736Sdavidch uint32_t tx_stat_etherstatspktsover1522octets_hi; 3078255736Sdavidch uint32_t tx_stat_etherstatspktsover1522octets_lo; 3079255736Sdavidch uint32_t tx_stat_mac_2047_hi; 3080255736Sdavidch uint32_t tx_stat_mac_2047_lo; 3081255736Sdavidch uint32_t tx_stat_mac_4095_hi; 3082255736Sdavidch uint32_t tx_stat_mac_4095_lo; 3083255736Sdavidch uint32_t tx_stat_mac_9216_hi; 3084255736Sdavidch uint32_t tx_stat_mac_9216_lo; 3085255736Sdavidch uint32_t tx_stat_mac_16383_hi; 3086255736Sdavidch uint32_t tx_stat_mac_16383_lo; 3087255736Sdavidch 3088255736Sdavidch /* internal_mac_transmit_errors */ 3089255736Sdavidch uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi; 3090255736Sdavidch uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo; 3091255736Sdavidch 3092255736Sdavidch /* if_out_discards */ 3093255736Sdavidch uint32_t tx_stat_mac_ufl_hi; 3094255736Sdavidch uint32_t tx_stat_mac_ufl_lo; 3095255736Sdavidch}; 3096255736Sdavidch 3097255736Sdavidch 3098255736Sdavidch#define MAC_STX_IDX_MAX 2 3099255736Sdavidch 3100255736Sdavidchstruct host_port_stats { 3101255736Sdavidch uint32_t host_port_stats_counter; 3102255736Sdavidch 3103255736Sdavidch struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 3104255736Sdavidch 3105255736Sdavidch uint32_t brb_drop_hi; 3106255736Sdavidch uint32_t brb_drop_lo; 3107255736Sdavidch 3108255736Sdavidch uint32_t not_used; /* obsolete as of MFW 7.2.1 */ 3109255736Sdavidch 3110255736Sdavidch uint32_t pfc_frames_tx_hi; 3111255736Sdavidch uint32_t pfc_frames_tx_lo; 3112255736Sdavidch uint32_t pfc_frames_rx_hi; 3113255736Sdavidch uint32_t pfc_frames_rx_lo; 3114255736Sdavidch 3115255736Sdavidch uint32_t eee_lpi_count_hi; 3116255736Sdavidch uint32_t eee_lpi_count_lo; 3117255736Sdavidch}; 3118255736Sdavidch 3119255736Sdavidch 3120255736Sdavidchstruct host_func_stats { 3121255736Sdavidch uint32_t host_func_stats_start; 3122255736Sdavidch 3123255736Sdavidch uint32_t total_bytes_received_hi; 3124255736Sdavidch uint32_t total_bytes_received_lo; 3125255736Sdavidch 3126255736Sdavidch uint32_t total_bytes_transmitted_hi; 3127255736Sdavidch uint32_t total_bytes_transmitted_lo; 3128255736Sdavidch 3129255736Sdavidch uint32_t total_unicast_packets_received_hi; 3130255736Sdavidch uint32_t total_unicast_packets_received_lo; 3131255736Sdavidch 3132255736Sdavidch uint32_t total_multicast_packets_received_hi; 3133255736Sdavidch uint32_t total_multicast_packets_received_lo; 3134255736Sdavidch 3135255736Sdavidch uint32_t total_broadcast_packets_received_hi; 3136255736Sdavidch uint32_t total_broadcast_packets_received_lo; 3137255736Sdavidch 3138255736Sdavidch uint32_t total_unicast_packets_transmitted_hi; 3139255736Sdavidch uint32_t total_unicast_packets_transmitted_lo; 3140255736Sdavidch 3141255736Sdavidch uint32_t total_multicast_packets_transmitted_hi; 3142255736Sdavidch uint32_t total_multicast_packets_transmitted_lo; 3143255736Sdavidch 3144255736Sdavidch uint32_t total_broadcast_packets_transmitted_hi; 3145255736Sdavidch uint32_t total_broadcast_packets_transmitted_lo; 3146255736Sdavidch 3147255736Sdavidch uint32_t valid_bytes_received_hi; 3148255736Sdavidch uint32_t valid_bytes_received_lo; 3149255736Sdavidch 3150255736Sdavidch uint32_t host_func_stats_end; 3151255736Sdavidch}; 3152255736Sdavidch 3153255736Sdavidch/* VIC definitions */ 3154255736Sdavidch#define VICSTATST_UIF_INDEX 2 3155255736Sdavidch 3156255736Sdavidch/* 3157255736Sdavidch * stats collected for afex. 3158255736Sdavidch * NOTE: structure is exactly as expected to be received by the switch. 3159255736Sdavidch * order must remain exactly as is unless protocol changes ! 3160255736Sdavidch */ 3161255736Sdavidchstruct afex_stats { 3162255736Sdavidch uint32_t tx_unicast_frames_hi; 3163255736Sdavidch uint32_t tx_unicast_frames_lo; 3164255736Sdavidch uint32_t tx_unicast_bytes_hi; 3165255736Sdavidch uint32_t tx_unicast_bytes_lo; 3166255736Sdavidch uint32_t tx_multicast_frames_hi; 3167255736Sdavidch uint32_t tx_multicast_frames_lo; 3168255736Sdavidch uint32_t tx_multicast_bytes_hi; 3169255736Sdavidch uint32_t tx_multicast_bytes_lo; 3170255736Sdavidch uint32_t tx_broadcast_frames_hi; 3171255736Sdavidch uint32_t tx_broadcast_frames_lo; 3172255736Sdavidch uint32_t tx_broadcast_bytes_hi; 3173255736Sdavidch uint32_t tx_broadcast_bytes_lo; 3174255736Sdavidch uint32_t tx_frames_discarded_hi; 3175255736Sdavidch uint32_t tx_frames_discarded_lo; 3176255736Sdavidch uint32_t tx_frames_dropped_hi; 3177255736Sdavidch uint32_t tx_frames_dropped_lo; 3178255736Sdavidch 3179255736Sdavidch uint32_t rx_unicast_frames_hi; 3180255736Sdavidch uint32_t rx_unicast_frames_lo; 3181255736Sdavidch uint32_t rx_unicast_bytes_hi; 3182255736Sdavidch uint32_t rx_unicast_bytes_lo; 3183255736Sdavidch uint32_t rx_multicast_frames_hi; 3184255736Sdavidch uint32_t rx_multicast_frames_lo; 3185255736Sdavidch uint32_t rx_multicast_bytes_hi; 3186255736Sdavidch uint32_t rx_multicast_bytes_lo; 3187255736Sdavidch uint32_t rx_broadcast_frames_hi; 3188255736Sdavidch uint32_t rx_broadcast_frames_lo; 3189255736Sdavidch uint32_t rx_broadcast_bytes_hi; 3190255736Sdavidch uint32_t rx_broadcast_bytes_lo; 3191255736Sdavidch uint32_t rx_frames_discarded_hi; 3192255736Sdavidch uint32_t rx_frames_discarded_lo; 3193255736Sdavidch uint32_t rx_frames_dropped_hi; 3194255736Sdavidch uint32_t rx_frames_dropped_lo; 3195255736Sdavidch}; 3196255736Sdavidch 3197255736Sdavidch/* To maintain backward compatibility between FW and drivers, new elements */ 3198255736Sdavidch/* should be added to the end of the structure. */ 3199255736Sdavidch 3200255736Sdavidch/* Per Port Statistics */ 3201255736Sdavidchstruct port_info { 3202255736Sdavidch uint32_t size; /* size of this structure (i.e. sizeof(port_info)) */ 3203255736Sdavidch uint32_t enabled; /* 0 =Disabled, 1= Enabled */ 3204255736Sdavidch uint32_t link_speed; /* multiplier of 100Mb */ 3205255736Sdavidch uint32_t wol_support; /* WoL Support (i.e. Non-Zero if WOL supported ) */ 3206255736Sdavidch uint32_t flow_control; /* 802.3X Flow Ctrl. 0=off 1=RX 2=TX 3=RX&TX.*/ 3207255736Sdavidch uint32_t flex10; /* Flex10 mode enabled. non zero = yes */ 3208255736Sdavidch uint32_t rx_drops; /* RX Discards. Counters roll over, never reset */ 3209255736Sdavidch uint32_t rx_errors; /* RX Errors. Physical Port Stats L95, All PFs and NC-SI. 3210255736Sdavidch This is flagged by Consumer as an error. */ 3211255736Sdavidch uint32_t rx_uncast_lo; /* RX Unicast Packets. Free running counters: */ 3212255736Sdavidch uint32_t rx_uncast_hi; /* RX Unicast Packets. Free running counters: */ 3213255736Sdavidch uint32_t rx_mcast_lo; /* RX Multicast Packets */ 3214255736Sdavidch uint32_t rx_mcast_hi; /* RX Multicast Packets */ 3215255736Sdavidch uint32_t rx_bcast_lo; /* RX Broadcast Packets */ 3216255736Sdavidch uint32_t rx_bcast_hi; /* RX Broadcast Packets */ 3217255736Sdavidch uint32_t tx_uncast_lo; /* TX Unicast Packets */ 3218255736Sdavidch uint32_t tx_uncast_hi; /* TX Unicast Packets */ 3219255736Sdavidch uint32_t tx_mcast_lo; /* TX Multicast Packets */ 3220255736Sdavidch uint32_t tx_mcast_hi; /* TX Multicast Packets */ 3221255736Sdavidch uint32_t tx_bcast_lo; /* TX Broadcast Packets */ 3222255736Sdavidch uint32_t tx_bcast_hi; /* TX Broadcast Packets */ 3223255736Sdavidch uint32_t tx_errors; /* TX Errors */ 3224255736Sdavidch uint32_t tx_discards; /* TX Discards */ 3225255736Sdavidch uint32_t rx_frames_lo; /* RX Frames received */ 3226255736Sdavidch uint32_t rx_frames_hi; /* RX Frames received */ 3227255736Sdavidch uint32_t rx_bytes_lo; /* RX Bytes received */ 3228255736Sdavidch uint32_t rx_bytes_hi; /* RX Bytes received */ 3229255736Sdavidch uint32_t tx_frames_lo; /* TX Frames sent */ 3230255736Sdavidch uint32_t tx_frames_hi; /* TX Frames sent */ 3231255736Sdavidch uint32_t tx_bytes_lo; /* TX Bytes sent */ 3232255736Sdavidch uint32_t tx_bytes_hi; /* TX Bytes sent */ 3233255736Sdavidch uint32_t link_status; /* Port P Link Status. 1:0 bit for port enabled. 3234255736Sdavidch 1:1 bit for link good, 3235255736Sdavidch 2:1 Set if link changed between last poll. */ 3236255736Sdavidch uint32_t tx_pfc_frames_lo; /* PFC Frames sent. */ 3237255736Sdavidch uint32_t tx_pfc_frames_hi; /* PFC Frames sent. */ 3238255736Sdavidch uint32_t rx_pfc_frames_lo; /* PFC Frames Received. */ 3239255736Sdavidch uint32_t rx_pfc_frames_hi; /* PFC Frames Received. */ 3240255736Sdavidch}; 3241255736Sdavidch 3242255736Sdavidch 3243255736Sdavidch#define BCM_5710_FW_MAJOR_VERSION 7 3244255736Sdavidch#define BCM_5710_FW_MINOR_VERSION 8 3245255736Sdavidch#define BCM_5710_FW_REVISION_VERSION 51 3246255736Sdavidch#define BCM_5710_FW_ENGINEERING_VERSION 0 3247255736Sdavidch#define BCM_5710_FW_COMPILE_FLAGS 1 3248255736Sdavidch 3249255736Sdavidch 3250255736Sdavidch/* 3251255736Sdavidch * attention bits $$KEEP_ENDIANNESS$$ 3252255736Sdavidch */ 3253255736Sdavidchstruct atten_sp_status_block 3254255736Sdavidch{ 3255255736Sdavidch uint32_t attn_bits /* 16 bit of attention signal lines */; 3256255736Sdavidch uint32_t attn_bits_ack /* 16 bit of attention signal ack */; 3257255736Sdavidch uint8_t status_block_id /* status block id */; 3258255736Sdavidch uint8_t reserved0 /* resreved for padding */; 3259255736Sdavidch uint16_t attn_bits_index /* attention bits running index */; 3260255736Sdavidch uint32_t reserved1 /* resreved for padding */; 3261255736Sdavidch}; 3262255736Sdavidch 3263255736Sdavidch 3264255736Sdavidch/* 3265255736Sdavidch * The eth aggregative context of Cstorm 3266255736Sdavidch */ 3267255736Sdavidchstruct cstorm_eth_ag_context 3268255736Sdavidch{ 3269255736Sdavidch uint32_t __reserved0[10]; 3270255736Sdavidch}; 3271255736Sdavidch 3272255736Sdavidch 3273255736Sdavidch/* 3274255736Sdavidch * dmae command structure 3275255736Sdavidch */ 3276255736Sdavidchstruct dmae_command 3277255736Sdavidch{ 3278255736Sdavidch uint32_t opcode; 3279255736Sdavidch#define DMAE_COMMAND_SRC (0x1<<0) /* BitField opcode Whether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The source is the GRC. */ 3280255736Sdavidch#define DMAE_COMMAND_SRC_SHIFT 0 3281255736Sdavidch#define DMAE_COMMAND_DST (0x3<<1) /* BitField opcode The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */ 3282255736Sdavidch#define DMAE_COMMAND_DST_SHIFT 1 3283255736Sdavidch#define DMAE_COMMAND_C_DST (0x1<<3) /* BitField opcode The destination of the completion: 0-PCIe 1-GRC */ 3284255736Sdavidch#define DMAE_COMMAND_C_DST_SHIFT 3 3285255736Sdavidch#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) /* BitField opcode Whether to write a completion word to the completion destination: 0-Do not write a completion word 1-Write the completion word */ 3286255736Sdavidch#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 3287255736Sdavidch#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) /* BitField opcode Whether to write a CRC word to the completion destination 0-Do not write a CRC word 1-Write a CRC word */ 3288255736Sdavidch#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 3289255736Sdavidch#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) /* BitField opcode The CRC word should be taken from the DMAE GRC space from address 9+X, where X is the value in these bits. */ 3290255736Sdavidch#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 3291255736Sdavidch#define DMAE_COMMAND_ENDIANITY (0x3<<9) /* BitField opcode swapping mode. */ 3292255736Sdavidch#define DMAE_COMMAND_ENDIANITY_SHIFT 9 3293255736Sdavidch#define DMAE_COMMAND_PORT (0x1<<11) /* BitField opcode Which network port ID to present to the PCI request interface */ 3294255736Sdavidch#define DMAE_COMMAND_PORT_SHIFT 11 3295255736Sdavidch#define DMAE_COMMAND_CRC_RESET (0x1<<12) /* BitField opcode reset crc result */ 3296255736Sdavidch#define DMAE_COMMAND_CRC_RESET_SHIFT 12 3297255736Sdavidch#define DMAE_COMMAND_SRC_RESET (0x1<<13) /* BitField opcode reset source address in next go */ 3298255736Sdavidch#define DMAE_COMMAND_SRC_RESET_SHIFT 13 3299255736Sdavidch#define DMAE_COMMAND_DST_RESET (0x1<<14) /* BitField opcode reset dest address in next go */ 3300255736Sdavidch#define DMAE_COMMAND_DST_RESET_SHIFT 14 3301255736Sdavidch#define DMAE_COMMAND_E1HVN (0x3<<15) /* BitField opcode vnic number E2 and onwards source vnic */ 3302255736Sdavidch#define DMAE_COMMAND_E1HVN_SHIFT 15 3303255736Sdavidch#define DMAE_COMMAND_DST_VN (0x3<<17) /* BitField opcode E2 and onwards dest vnic */ 3304255736Sdavidch#define DMAE_COMMAND_DST_VN_SHIFT 17 3305255736Sdavidch#define DMAE_COMMAND_C_FUNC (0x1<<19) /* BitField opcode E2 and onwards which function gets the completion src_vn(e1hvn)-0 dst_vn-1 */ 3306255736Sdavidch#define DMAE_COMMAND_C_FUNC_SHIFT 19 3307255736Sdavidch#define DMAE_COMMAND_ERR_POLICY (0x3<<20) /* BitField opcode E2 and onwards what to do when theres a completion and a PCI error regular-0 error indication-1 no completion-2 */ 3308255736Sdavidch#define DMAE_COMMAND_ERR_POLICY_SHIFT 20 3309255736Sdavidch#define DMAE_COMMAND_RESERVED0 (0x3FF<<22) /* BitField opcode */ 3310255736Sdavidch#define DMAE_COMMAND_RESERVED0_SHIFT 22 3311255736Sdavidch uint32_t src_addr_lo /* source address low/grc address */; 3312255736Sdavidch uint32_t src_addr_hi /* source address hi */; 3313255736Sdavidch uint32_t dst_addr_lo /* dest address low/grc address */; 3314255736Sdavidch uint32_t dst_addr_hi /* dest address hi */; 3315255736Sdavidch#if defined(__BIG_ENDIAN) 3316255736Sdavidch uint16_t opcode_iov; 3317255736Sdavidch#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */ 3318255736Sdavidch#define DMAE_COMMAND_SRC_VFID_SHIFT 0 3319255736Sdavidch#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */ 3320255736Sdavidch#define DMAE_COMMAND_SRC_VFPF_SHIFT 6 3321255736Sdavidch#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3322255736Sdavidch#define DMAE_COMMAND_RESERVED1_SHIFT 7 3323255736Sdavidch#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */ 3324255736Sdavidch#define DMAE_COMMAND_DST_VFID_SHIFT 8 3325255736Sdavidch#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */ 3326255736Sdavidch#define DMAE_COMMAND_DST_VFPF_SHIFT 14 3327255736Sdavidch#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3328255736Sdavidch#define DMAE_COMMAND_RESERVED2_SHIFT 15 3329255736Sdavidch uint16_t len /* copy length */; 3330255736Sdavidch#elif defined(__LITTLE_ENDIAN) 3331255736Sdavidch uint16_t len /* copy length */; 3332255736Sdavidch uint16_t opcode_iov; 3333255736Sdavidch#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */ 3334255736Sdavidch#define DMAE_COMMAND_SRC_VFID_SHIFT 0 3335255736Sdavidch#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */ 3336255736Sdavidch#define DMAE_COMMAND_SRC_VFPF_SHIFT 6 3337255736Sdavidch#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3338255736Sdavidch#define DMAE_COMMAND_RESERVED1_SHIFT 7 3339255736Sdavidch#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */ 3340255736Sdavidch#define DMAE_COMMAND_DST_VFID_SHIFT 8 3341255736Sdavidch#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */ 3342255736Sdavidch#define DMAE_COMMAND_DST_VFPF_SHIFT 14 3343255736Sdavidch#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3344255736Sdavidch#define DMAE_COMMAND_RESERVED2_SHIFT 15 3345255736Sdavidch#endif 3346255736Sdavidch uint32_t comp_addr_lo /* completion address low/grc address */; 3347255736Sdavidch uint32_t comp_addr_hi /* completion address hi */; 3348255736Sdavidch uint32_t comp_val /* value to write to completion address */; 3349255736Sdavidch uint32_t crc32 /* crc32 result */; 3350255736Sdavidch uint32_t crc32_c /* crc32_c result */; 3351255736Sdavidch#if defined(__BIG_ENDIAN) 3352255736Sdavidch uint16_t crc16_c /* crc16_c result */; 3353255736Sdavidch uint16_t crc16 /* crc16 result */; 3354255736Sdavidch#elif defined(__LITTLE_ENDIAN) 3355255736Sdavidch uint16_t crc16 /* crc16 result */; 3356255736Sdavidch uint16_t crc16_c /* crc16_c result */; 3357255736Sdavidch#endif 3358255736Sdavidch#if defined(__BIG_ENDIAN) 3359255736Sdavidch uint16_t reserved3; 3360255736Sdavidch uint16_t crc_t10 /* crc_t10 result */; 3361255736Sdavidch#elif defined(__LITTLE_ENDIAN) 3362255736Sdavidch uint16_t crc_t10 /* crc_t10 result */; 3363255736Sdavidch uint16_t reserved3; 3364255736Sdavidch#endif 3365255736Sdavidch#if defined(__BIG_ENDIAN) 3366255736Sdavidch uint16_t xsum8 /* checksum8 result */; 3367255736Sdavidch uint16_t xsum16 /* checksum16 result */; 3368255736Sdavidch#elif defined(__LITTLE_ENDIAN) 3369255736Sdavidch uint16_t xsum16 /* checksum16 result */; 3370255736Sdavidch uint16_t xsum8 /* checksum8 result */; 3371255736Sdavidch#endif 3372255736Sdavidch}; 3373255736Sdavidch 3374255736Sdavidch 3375255736Sdavidch/* 3376255736Sdavidch * common data for all protocols 3377255736Sdavidch */ 3378255736Sdavidchstruct doorbell_hdr 3379255736Sdavidch{ 3380255736Sdavidch uint8_t header; 3381255736Sdavidch#define DOORBELL_HDR_RX (0x1<<0) /* BitField header 1 for rx doorbell, 0 for tx doorbell */ 3382255736Sdavidch#define DOORBELL_HDR_RX_SHIFT 0 3383255736Sdavidch#define DOORBELL_HDR_DB_TYPE (0x1<<1) /* BitField header 0 for normal doorbell, 1 for advertise wnd doorbell */ 3384255736Sdavidch#define DOORBELL_HDR_DB_TYPE_SHIFT 1 3385255736Sdavidch#define DOORBELL_HDR_DPM_SIZE (0x3<<2) /* BitField header rdma tx only: DPM transaction size specifier (64/128/256/512 bytes) */ 3386255736Sdavidch#define DOORBELL_HDR_DPM_SIZE_SHIFT 2 3387255736Sdavidch#define DOORBELL_HDR_CONN_TYPE (0xF<<4) /* BitField header connection type */ 3388255736Sdavidch#define DOORBELL_HDR_CONN_TYPE_SHIFT 4 3389255736Sdavidch}; 3390255736Sdavidch 3391255736Sdavidch/* 3392255736Sdavidch * Ethernet doorbell 3393255736Sdavidch */ 3394255736Sdavidchstruct eth_tx_doorbell 3395255736Sdavidch{ 3396255736Sdavidch#if defined(__BIG_ENDIAN) 3397255736Sdavidch uint16_t npackets /* number of data bytes that were added in the doorbell */; 3398255736Sdavidch uint8_t params; 3399255736Sdavidch#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ 3400255736Sdavidch#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3401255736Sdavidch#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ 3402255736Sdavidch#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3403255736Sdavidch#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */ 3404255736Sdavidch#define ETH_TX_DOORBELL_SPARE_SHIFT 7 3405255736Sdavidch struct doorbell_hdr hdr; 3406255736Sdavidch#elif defined(__LITTLE_ENDIAN) 3407255736Sdavidch struct doorbell_hdr hdr; 3408255736Sdavidch uint8_t params; 3409255736Sdavidch#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ 3410255736Sdavidch#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3411255736Sdavidch#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ 3412255736Sdavidch#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3413255736Sdavidch#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */ 3414255736Sdavidch#define ETH_TX_DOORBELL_SPARE_SHIFT 7 3415255736Sdavidch uint16_t npackets /* number of data bytes that were added in the doorbell */; 3416255736Sdavidch#endif 3417255736Sdavidch}; 3418255736Sdavidch 3419255736Sdavidch 3420255736Sdavidch/* 3421255736Sdavidch * 3 lines. status block $$KEEP_ENDIANNESS$$ 3422255736Sdavidch */ 3423255736Sdavidchstruct hc_status_block_e1x 3424255736Sdavidch{ 3425255736Sdavidch uint16_t index_values[HC_SB_MAX_INDICES_E1X] /* indices reported by cstorm */; 3426255736Sdavidch uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */; 3427255736Sdavidch uint32_t rsrv[11]; 3428255736Sdavidch}; 3429255736Sdavidch 3430255736Sdavidch/* 3431255736Sdavidch * host status block 3432255736Sdavidch */ 3433255736Sdavidchstruct host_hc_status_block_e1x 3434255736Sdavidch{ 3435255736Sdavidch struct hc_status_block_e1x sb /* fast path indices */; 3436255736Sdavidch}; 3437255736Sdavidch 3438255736Sdavidch 3439255736Sdavidch/* 3440255736Sdavidch * 3 lines. status block $$KEEP_ENDIANNESS$$ 3441255736Sdavidch */ 3442255736Sdavidchstruct hc_status_block_e2 3443255736Sdavidch{ 3444255736Sdavidch uint16_t index_values[HC_SB_MAX_INDICES_E2] /* indices reported by cstorm */; 3445255736Sdavidch uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */; 3446255736Sdavidch uint32_t reserved[11]; 3447255736Sdavidch}; 3448255736Sdavidch 3449255736Sdavidch/* 3450255736Sdavidch * host status block 3451255736Sdavidch */ 3452255736Sdavidchstruct host_hc_status_block_e2 3453255736Sdavidch{ 3454255736Sdavidch struct hc_status_block_e2 sb /* fast path indices */; 3455255736Sdavidch}; 3456255736Sdavidch 3457255736Sdavidch 3458255736Sdavidch/* 3459255736Sdavidch * 5 lines. slow-path status block $$KEEP_ENDIANNESS$$ 3460255736Sdavidch */ 3461255736Sdavidchstruct hc_sp_status_block 3462255736Sdavidch{ 3463255736Sdavidch uint16_t index_values[HC_SP_SB_MAX_INDICES] /* indices reported by cstorm */; 3464255736Sdavidch uint16_t running_index /* Status Block running index */; 3465255736Sdavidch uint16_t rsrv; 3466255736Sdavidch uint32_t rsrv1; 3467255736Sdavidch}; 3468255736Sdavidch 3469255736Sdavidch/* 3470255736Sdavidch * host status block 3471255736Sdavidch */ 3472255736Sdavidchstruct host_sp_status_block 3473255736Sdavidch{ 3474255736Sdavidch struct atten_sp_status_block atten_status_block /* attention bits section */; 3475255736Sdavidch struct hc_sp_status_block sp_sb /* slow path indices */; 3476255736Sdavidch}; 3477255736Sdavidch 3478255736Sdavidch 3479255736Sdavidch/* 3480255736Sdavidch * IGU driver acknowledgment register 3481255736Sdavidch */ 3482255736Sdavidchstruct igu_ack_register 3483255736Sdavidch{ 3484255736Sdavidch#if defined(__BIG_ENDIAN) 3485255736Sdavidch uint16_t sb_id_and_flags; 3486255736Sdavidch#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */ 3487255736Sdavidch#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3488255736Sdavidch#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ 3489255736Sdavidch#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3490255736Sdavidch#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */ 3491255736Sdavidch#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3492255736Sdavidch#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ 3493255736Sdavidch#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3494255736Sdavidch#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */ 3495255736Sdavidch#define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3496255736Sdavidch uint16_t status_block_index /* status block index acknowledgement */; 3497255736Sdavidch#elif defined(__LITTLE_ENDIAN) 3498255736Sdavidch uint16_t status_block_index /* status block index acknowledgement */; 3499255736Sdavidch uint16_t sb_id_and_flags; 3500255736Sdavidch#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */ 3501255736Sdavidch#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3502255736Sdavidch#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ 3503255736Sdavidch#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3504255736Sdavidch#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */ 3505255736Sdavidch#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3506255736Sdavidch#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ 3507255736Sdavidch#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3508255736Sdavidch#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */ 3509255736Sdavidch#define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3510255736Sdavidch#endif 3511255736Sdavidch}; 3512255736Sdavidch 3513255736Sdavidch 3514255736Sdavidch/* 3515255736Sdavidch * IGU driver acknowledgement register 3516255736Sdavidch */ 3517255736Sdavidchstruct igu_backward_compatible 3518255736Sdavidch{ 3519255736Sdavidch uint32_t sb_id_and_flags; 3520255736Sdavidch#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /* BitField sb_id_and_flags */ 3521255736Sdavidch#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 3522255736Sdavidch#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /* BitField sb_id_and_flags */ 3523255736Sdavidch#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 3524255736Sdavidch#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ 3525255736Sdavidch#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 3526255736Sdavidch#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* BitField sb_id_and_flags if set, acknowledges status block index */ 3527255736Sdavidch#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 3528255736Sdavidch#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ 3529255736Sdavidch#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 3530255736Sdavidch#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /* BitField sb_id_and_flags */ 3531255736Sdavidch#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 3532255736Sdavidch uint32_t reserved_2; 3533255736Sdavidch}; 3534255736Sdavidch 3535255736Sdavidch 3536255736Sdavidch/* 3537255736Sdavidch * IGU driver acknowledgement register 3538255736Sdavidch */ 3539255736Sdavidchstruct igu_regular 3540255736Sdavidch{ 3541255736Sdavidch uint32_t sb_id_and_flags; 3542255736Sdavidch#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) /* BitField sb_id_and_flags */ 3543255736Sdavidch#define IGU_REGULAR_SB_INDEX_SHIFT 0 3544255736Sdavidch#define IGU_REGULAR_RESERVED0 (0x1<<20) /* BitField sb_id_and_flags */ 3545255736Sdavidch#define IGU_REGULAR_RESERVED0_SHIFT 20 3546255736Sdavidch#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 21-23 (use enum igu_seg_access) */ 3547255736Sdavidch#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 3548255736Sdavidch#define IGU_REGULAR_BUPDATE (0x1<<24) /* BitField sb_id_and_flags */ 3549255736Sdavidch#define IGU_REGULAR_BUPDATE_SHIFT 24 3550255736Sdavidch#define IGU_REGULAR_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop (use enum igu_int_cmd) */ 3551255736Sdavidch#define IGU_REGULAR_ENABLE_INT_SHIFT 25 3552255736Sdavidch#define IGU_REGULAR_RESERVED_1 (0x1<<27) /* BitField sb_id_and_flags */ 3553255736Sdavidch#define IGU_REGULAR_RESERVED_1_SHIFT 27 3554255736Sdavidch#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* BitField sb_id_and_flags */ 3555255736Sdavidch#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 3556255736Sdavidch#define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags */ 3557255736Sdavidch#define IGU_REGULAR_CLEANUP_SET_SHIFT 30 3558255736Sdavidch#define IGU_REGULAR_BCLEANUP (0x1<<31) /* BitField sb_id_and_flags */ 3559255736Sdavidch#define IGU_REGULAR_BCLEANUP_SHIFT 31 3560255736Sdavidch uint32_t reserved_2; 3561255736Sdavidch}; 3562255736Sdavidch 3563255736Sdavidch/* 3564255736Sdavidch * IGU driver acknowledgement register 3565255736Sdavidch */ 3566255736Sdavidchunion igu_consprod_reg 3567255736Sdavidch{ 3568255736Sdavidch struct igu_regular regular; 3569255736Sdavidch struct igu_backward_compatible backward_compatible; 3570255736Sdavidch}; 3571255736Sdavidch 3572255736Sdavidch 3573255736Sdavidch/* 3574255736Sdavidch * Igu control commands 3575255736Sdavidch */ 3576255736Sdavidchenum igu_ctrl_cmd 3577255736Sdavidch{ 3578255736Sdavidch IGU_CTRL_CMD_TYPE_RD, 3579255736Sdavidch IGU_CTRL_CMD_TYPE_WR, 3580255736Sdavidch MAX_IGU_CTRL_CMD}; 3581255736Sdavidch 3582255736Sdavidch 3583255736Sdavidch/* 3584255736Sdavidch * Control register for the IGU command register 3585255736Sdavidch */ 3586255736Sdavidchstruct igu_ctrl_reg 3587255736Sdavidch{ 3588255736Sdavidch uint32_t ctrl_data; 3589255736Sdavidch#define IGU_CTRL_REG_ADDRESS (0xFFF<<0) /* BitField ctrl_data */ 3590255736Sdavidch#define IGU_CTRL_REG_ADDRESS_SHIFT 0 3591255736Sdavidch#define IGU_CTRL_REG_FID (0x7F<<12) /* BitField ctrl_data */ 3592255736Sdavidch#define IGU_CTRL_REG_FID_SHIFT 12 3593255736Sdavidch#define IGU_CTRL_REG_RESERVED (0x1<<19) /* BitField ctrl_data */ 3594255736Sdavidch#define IGU_CTRL_REG_RESERVED_SHIFT 19 3595255736Sdavidch#define IGU_CTRL_REG_TYPE (0x1<<20) /* BitField ctrl_data (use enum igu_ctrl_cmd) */ 3596255736Sdavidch#define IGU_CTRL_REG_TYPE_SHIFT 20 3597255736Sdavidch#define IGU_CTRL_REG_UNUSED (0x7FF<<21) /* BitField ctrl_data */ 3598255736Sdavidch#define IGU_CTRL_REG_UNUSED_SHIFT 21 3599255736Sdavidch}; 3600255736Sdavidch 3601255736Sdavidch 3602255736Sdavidch/* 3603255736Sdavidch * Igu interrupt command 3604255736Sdavidch */ 3605255736Sdavidchenum igu_int_cmd 3606255736Sdavidch{ 3607255736Sdavidch IGU_INT_ENABLE, 3608255736Sdavidch IGU_INT_DISABLE, 3609255736Sdavidch IGU_INT_NOP, 3610255736Sdavidch IGU_INT_NOP2, 3611255736Sdavidch MAX_IGU_INT_CMD}; 3612255736Sdavidch 3613255736Sdavidch 3614255736Sdavidch/* 3615255736Sdavidch * Igu segments 3616255736Sdavidch */ 3617255736Sdavidchenum igu_seg_access 3618255736Sdavidch{ 3619255736Sdavidch IGU_SEG_ACCESS_NORM, 3620255736Sdavidch IGU_SEG_ACCESS_DEF, 3621255736Sdavidch IGU_SEG_ACCESS_ATTN, 3622255736Sdavidch MAX_IGU_SEG_ACCESS}; 3623255736Sdavidch 3624255736Sdavidch 3625255736Sdavidch/* 3626255736Sdavidch * Parser parsing flags field 3627255736Sdavidch */ 3628255736Sdavidchstruct parsing_flags 3629255736Sdavidch{ 3630255736Sdavidch uint16_t flags; 3631255736Sdavidch#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags 0=non-unicast, 1=unicast (use enum prs_flags_eth_addr_type) */ 3632255736Sdavidch#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 3633255736Sdavidch#define PARSING_FLAGS_VLAN (0x1<<1) /* BitField flagscontext flags 0 or 1 */ 3634255736Sdavidch#define PARSING_FLAGS_VLAN_SHIFT 1 3635255736Sdavidch#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) /* BitField flagscontext flags 0 or 1 */ 3636255736Sdavidch#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 3637255736Sdavidch#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags 0=un-known, 1=Ipv4, 2=Ipv6,3=LLC SNAP un-known. LLC SNAP here refers only to LLC/SNAP packets that do not have Ipv4 or Ipv6 above them. Ipv4 and Ipv6 indications are even if they are over LLC/SNAP and not directly over Ethernet (use enum prs_flags_over_eth) */ 3638255736Sdavidch#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 3639255736Sdavidch#define PARSING_FLAGS_IP_OPTIONS (0x1<<5) /* BitField flagscontext flags 0=no IP options / extension headers. 1=IP options / extension header exist */ 3640255736Sdavidch#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 3641255736Sdavidch#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) /* BitField flagscontext flags 0=non-fragmented, 1=fragmented */ 3642255736Sdavidch#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 3643255736Sdavidch#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) /* BitField flagscontext flags 0=un-known, 1=TCP, 2=UDP (use enum prs_flags_over_ip) */ 3644255736Sdavidch#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 3645255736Sdavidch#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) /* BitField flagscontext flags 0=packet with data, 1=pure-ACK (use enum prs_flags_ack_type) */ 3646255736Sdavidch#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 3647255736Sdavidch#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) /* BitField flagscontext flags 0=no TCP options. 1=TCP options */ 3648255736Sdavidch#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 3649255736Sdavidch#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* BitField flagscontext flags According to the TCP header options parsing */ 3650255736Sdavidch#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 3651255736Sdavidch#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* BitField flagscontext flags connection match in searcher indication */ 3652255736Sdavidch#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 3653255736Sdavidch#define PARSING_FLAGS_LLC_SNAP (0x1<<13) /* BitField flagscontext flags LLC SNAP indication */ 3654255736Sdavidch#define PARSING_FLAGS_LLC_SNAP_SHIFT 13 3655255736Sdavidch#define PARSING_FLAGS_RESERVED0 (0x3<<14) /* BitField flagscontext flags */ 3656255736Sdavidch#define PARSING_FLAGS_RESERVED0_SHIFT 14 3657255736Sdavidch}; 3658255736Sdavidch 3659255736Sdavidch 3660255736Sdavidch/* 3661255736Sdavidch * Parsing flags for TCP ACK type 3662255736Sdavidch */ 3663255736Sdavidchenum prs_flags_ack_type 3664255736Sdavidch{ 3665255736Sdavidch PRS_FLAG_PUREACK_PIGGY, 3666255736Sdavidch PRS_FLAG_PUREACK_PURE, 3667255736Sdavidch MAX_PRS_FLAGS_ACK_TYPE}; 3668255736Sdavidch 3669255736Sdavidch 3670255736Sdavidch/* 3671255736Sdavidch * Parsing flags for Ethernet address type 3672255736Sdavidch */ 3673255736Sdavidchenum prs_flags_eth_addr_type 3674255736Sdavidch{ 3675255736Sdavidch PRS_FLAG_ETHTYPE_NON_UNICAST, 3676255736Sdavidch PRS_FLAG_ETHTYPE_UNICAST, 3677255736Sdavidch MAX_PRS_FLAGS_ETH_ADDR_TYPE}; 3678255736Sdavidch 3679255736Sdavidch 3680255736Sdavidch/* 3681255736Sdavidch * Parsing flags for over-ethernet protocol 3682255736Sdavidch */ 3683255736Sdavidchenum prs_flags_over_eth 3684255736Sdavidch{ 3685255736Sdavidch PRS_FLAG_OVERETH_UNKNOWN, 3686255736Sdavidch PRS_FLAG_OVERETH_IPV4, 3687255736Sdavidch PRS_FLAG_OVERETH_IPV6, 3688255736Sdavidch PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 3689255736Sdavidch MAX_PRS_FLAGS_OVER_ETH}; 3690255736Sdavidch 3691255736Sdavidch 3692255736Sdavidch/* 3693255736Sdavidch * Parsing flags for over-IP protocol 3694255736Sdavidch */ 3695255736Sdavidchenum prs_flags_over_ip 3696255736Sdavidch{ 3697255736Sdavidch PRS_FLAG_OVERIP_UNKNOWN, 3698255736Sdavidch PRS_FLAG_OVERIP_TCP, 3699255736Sdavidch PRS_FLAG_OVERIP_UDP, 3700255736Sdavidch MAX_PRS_FLAGS_OVER_IP}; 3701255736Sdavidch 3702255736Sdavidch 3703255736Sdavidch/* 3704255736Sdavidch * SDM operation gen command (generate aggregative interrupt) 3705255736Sdavidch */ 3706255736Sdavidchstruct sdm_op_gen 3707255736Sdavidch{ 3708255736Sdavidch uint32_t command; 3709255736Sdavidch#define SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* BitField commandcomp_param and comp_type thread ID/aggr interrupt number/counter depending on the completion type */ 3710255736Sdavidch#define SDM_OP_GEN_COMP_PARAM_SHIFT 0 3711255736Sdavidch#define SDM_OP_GEN_COMP_TYPE (0x7<<5) /* BitField commandcomp_param and comp_type Direct messages to CM / PCI switch are not supported in operation_gen completion */ 3712255736Sdavidch#define SDM_OP_GEN_COMP_TYPE_SHIFT 5 3713255736Sdavidch#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* BitField commandcomp_param and comp_type bit index in aggregated interrupt vector */ 3714255736Sdavidch#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 3715255736Sdavidch#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* BitField commandcomp_param and comp_type */ 3716255736Sdavidch#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 3717255736Sdavidch#define SDM_OP_GEN_RESERVED (0x7FFF<<17) /* BitField commandcomp_param and comp_type */ 3718255736Sdavidch#define SDM_OP_GEN_RESERVED_SHIFT 17 3719255736Sdavidch}; 3720255736Sdavidch 3721255736Sdavidch 3722255736Sdavidch/* 3723255736Sdavidch * Timers connection context 3724255736Sdavidch */ 3725255736Sdavidchstruct timers_block_context 3726255736Sdavidch{ 3727255736Sdavidch uint32_t __reserved_0 /* data of client 0 of the timers block*/; 3728255736Sdavidch uint32_t __reserved_1 /* data of client 1 of the timers block*/; 3729255736Sdavidch uint32_t __reserved_2 /* data of client 2 of the timers block*/; 3730255736Sdavidch uint32_t flags; 3731255736Sdavidch#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* BitField flagscontext flags number of active timers running */ 3732255736Sdavidch#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 3733255736Sdavidch#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* BitField flagscontext flags flag: is connection valid (should be set by driver to 1 in toe/iscsi connections) */ 3734255736Sdavidch#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 3735255736Sdavidch#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) /* BitField flagscontext flags */ 3736255736Sdavidch#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 3737255736Sdavidch}; 3738255736Sdavidch 3739255736Sdavidch 3740255736Sdavidch/* 3741255736Sdavidch * The eth aggregative context of Tstorm 3742255736Sdavidch */ 3743255736Sdavidchstruct tstorm_eth_ag_context 3744255736Sdavidch{ 3745255736Sdavidch uint32_t __reserved0[14]; 3746255736Sdavidch}; 3747255736Sdavidch 3748255736Sdavidch 3749255736Sdavidch/* 3750255736Sdavidch * The eth aggregative context of Ustorm 3751255736Sdavidch */ 3752255736Sdavidchstruct ustorm_eth_ag_context 3753255736Sdavidch{ 3754255736Sdavidch uint32_t __reserved0; 3755255736Sdavidch#if defined(__BIG_ENDIAN) 3756255736Sdavidch uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 3757255736Sdavidch uint8_t __reserved2; 3758255736Sdavidch uint16_t __reserved1; 3759255736Sdavidch#elif defined(__LITTLE_ENDIAN) 3760255736Sdavidch uint16_t __reserved1; 3761255736Sdavidch uint8_t __reserved2; 3762255736Sdavidch uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 3763255736Sdavidch#endif 3764255736Sdavidch uint32_t __reserved3[6]; 3765255736Sdavidch}; 3766255736Sdavidch 3767255736Sdavidch 3768255736Sdavidch/* 3769255736Sdavidch * The eth aggregative context of Xstorm 3770255736Sdavidch */ 3771255736Sdavidchstruct xstorm_eth_ag_context 3772255736Sdavidch{ 3773255736Sdavidch uint32_t reserved0; 3774255736Sdavidch#if defined(__BIG_ENDIAN) 3775255736Sdavidch uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 3776255736Sdavidch uint8_t reserved2; 3777255736Sdavidch uint16_t reserved1; 3778255736Sdavidch#elif defined(__LITTLE_ENDIAN) 3779255736Sdavidch uint16_t reserved1; 3780255736Sdavidch uint8_t reserved2; 3781255736Sdavidch uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 3782255736Sdavidch#endif 3783255736Sdavidch uint32_t reserved3[30]; 3784255736Sdavidch}; 3785255736Sdavidch 3786255736Sdavidch 3787255736Sdavidch/* 3788255736Sdavidch * doorbell message sent to the chip 3789255736Sdavidch */ 3790255736Sdavidchstruct doorbell 3791255736Sdavidch{ 3792255736Sdavidch#if defined(__BIG_ENDIAN) 3793255736Sdavidch uint16_t zero_fill2 /* driver must zero this field! */; 3794255736Sdavidch uint8_t zero_fill1 /* driver must zero this field! */; 3795255736Sdavidch struct doorbell_hdr header; 3796255736Sdavidch#elif defined(__LITTLE_ENDIAN) 3797255736Sdavidch struct doorbell_hdr header; 3798255736Sdavidch uint8_t zero_fill1 /* driver must zero this field! */; 3799255736Sdavidch uint16_t zero_fill2 /* driver must zero this field! */; 3800255736Sdavidch#endif 3801255736Sdavidch}; 3802255736Sdavidch 3803255736Sdavidch 3804255736Sdavidch/* 3805255736Sdavidch * doorbell message sent to the chip 3806255736Sdavidch */ 3807255736Sdavidchstruct doorbell_set_prod 3808255736Sdavidch{ 3809255736Sdavidch#if defined(__BIG_ENDIAN) 3810255736Sdavidch uint16_t prod /* Producer index to be set */; 3811255736Sdavidch uint8_t zero_fill1 /* driver must zero this field! */; 3812255736Sdavidch struct doorbell_hdr header; 3813255736Sdavidch#elif defined(__LITTLE_ENDIAN) 3814255736Sdavidch struct doorbell_hdr header; 3815255736Sdavidch uint8_t zero_fill1 /* driver must zero this field! */; 3816255736Sdavidch uint16_t prod /* Producer index to be set */; 3817255736Sdavidch#endif 3818255736Sdavidch}; 3819255736Sdavidch 3820255736Sdavidch 3821255736Sdavidchstruct regpair 3822255736Sdavidch{ 3823255736Sdavidch uint32_t lo /* low word for reg-pair */; 3824255736Sdavidch uint32_t hi /* high word for reg-pair */; 3825255736Sdavidch}; 3826255736Sdavidch 3827255736Sdavidch 3828255736Sdavidchstruct regpair_native 3829255736Sdavidch{ 3830255736Sdavidch uint32_t lo /* low word for reg-pair */; 3831255736Sdavidch uint32_t hi /* high word for reg-pair */; 3832255736Sdavidch}; 3833255736Sdavidch 3834255736Sdavidch 3835255736Sdavidch/* 3836255736Sdavidch * Classify rule opcodes in E2/E3 3837255736Sdavidch */ 3838255736Sdavidchenum classify_rule 3839255736Sdavidch{ 3840255736Sdavidch CLASSIFY_RULE_OPCODE_MAC /* Add/remove a MAC address */, 3841255736Sdavidch CLASSIFY_RULE_OPCODE_VLAN /* Add/remove a VLAN */, 3842255736Sdavidch CLASSIFY_RULE_OPCODE_PAIR /* Add/remove a MAC-VLAN pair */, 3843255736Sdavidch MAX_CLASSIFY_RULE}; 3844255736Sdavidch 3845255736Sdavidch 3846255736Sdavidch/* 3847255736Sdavidch * Classify rule types in E2/E3 3848255736Sdavidch */ 3849255736Sdavidchenum classify_rule_action_type 3850255736Sdavidch{ 3851255736Sdavidch CLASSIFY_RULE_REMOVE, 3852255736Sdavidch CLASSIFY_RULE_ADD, 3853255736Sdavidch MAX_CLASSIFY_RULE_ACTION_TYPE}; 3854255736Sdavidch 3855255736Sdavidch 3856255736Sdavidch/* 3857255736Sdavidch * client init ramrod data $$KEEP_ENDIANNESS$$ 3858255736Sdavidch */ 3859255736Sdavidchstruct client_init_general_data 3860255736Sdavidch{ 3861255736Sdavidch uint8_t client_id /* client_id */; 3862255736Sdavidch uint8_t statistics_counter_id /* statistics counter id */; 3863255736Sdavidch uint8_t statistics_en_flg /* statistics en flg */; 3864255736Sdavidch uint8_t is_fcoe_flg /* is this an fcoe connection. (1 bit is used) */; 3865255736Sdavidch uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */; 3866255736Sdavidch uint8_t sp_client_id /* the slow path rings client Id. */; 3867255736Sdavidch uint16_t mtu /* Host MTU from client config */; 3868255736Sdavidch uint8_t statistics_zero_flg /* if set FW will reset the statistic counter of this client */; 3869255736Sdavidch uint8_t func_id /* PCI function ID (0-71) */; 3870255736Sdavidch uint8_t cos /* The connection cos, if applicable */; 3871255736Sdavidch uint8_t traffic_type; 3872255736Sdavidch uint32_t reserved0; 3873255736Sdavidch}; 3874255736Sdavidch 3875255736Sdavidch 3876255736Sdavidch/* 3877255736Sdavidch * client init rx data $$KEEP_ENDIANNESS$$ 3878255736Sdavidch */ 3879255736Sdavidchstruct client_init_rx_data 3880255736Sdavidch{ 3881255736Sdavidch uint8_t tpa_en; 3882255736Sdavidch#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* BitField tpa_entpa_enable tpa enable flg ipv4 */ 3883255736Sdavidch#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 3884255736Sdavidch#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* BitField tpa_entpa_enable tpa enable flg ipv6 */ 3885255736Sdavidch#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 3886255736Sdavidch#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* BitField tpa_entpa_enable tpa mode (LRO or GRO) (use enum tpa_mode) */ 3887255736Sdavidch#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 3888255736Sdavidch#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* BitField tpa_entpa_enable */ 3889255736Sdavidch#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 3890255736Sdavidch uint8_t vmqueue_mode_en_flg /* If set, working in VMQueue mode (always consume one sge) */; 3891255736Sdavidch uint8_t extra_data_over_sgl_en_flg /* if set, put over sgl data from end of input message */; 3892255736Sdavidch uint8_t cache_line_alignment_log_size /* The log size of cache line alignment in bytes. Must be a power of 2. */; 3893255736Sdavidch uint8_t enable_dynamic_hc /* If set, dynamic HC is enabled */; 3894255736Sdavidch uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */; 3895255736Sdavidch uint8_t client_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this client rx producers */; 3896255736Sdavidch uint8_t drop_ip_cs_err_flg /* If set, this client drops packets with IP checksum error */; 3897255736Sdavidch uint8_t drop_tcp_cs_err_flg /* If set, this client drops packets with TCP checksum error */; 3898255736Sdavidch uint8_t drop_ttl0_flg /* If set, this client drops packets with TTL=0 */; 3899255736Sdavidch uint8_t drop_udp_cs_err_flg /* If set, this client drops packets with UDP checksum error */; 3900255736Sdavidch uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client */; 3901255736Sdavidch uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client */; 3902255736Sdavidch uint8_t status_block_id /* rx status block id */; 3903255736Sdavidch uint8_t rx_sb_index_number /* status block indices */; 3904255736Sdavidch uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */; 3905255736Sdavidch uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */; 3906255736Sdavidch uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */; 3907255736Sdavidch uint16_t max_bytes_on_bd /* Maximum bytes that can be placed on a BD. The BD allocated size should include 2 more bytes (ip alignment) and alignment size (in case the address is not aligned) */; 3908255736Sdavidch uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */; 3909255736Sdavidch uint8_t approx_mcast_engine_id /* In Everest2, if is_approx_mcast is set, this field specified which approximate multicast engine is associate with this client */; 3910255736Sdavidch uint8_t rss_engine_id /* In Everest2, if rss_mode is set, this field specified which RSS engine is associate with this client */; 3911255736Sdavidch struct regpair bd_page_base /* BD page base address at the host */; 3912255736Sdavidch struct regpair sge_page_base /* SGE page base address at the host */; 3913255736Sdavidch struct regpair cqe_page_base /* Completion queue base address */; 3914255736Sdavidch uint8_t is_leading_rss; 3915255736Sdavidch uint8_t is_approx_mcast; 3916255736Sdavidch uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */; 3917255736Sdavidch uint16_t state; 3918255736Sdavidch#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* BitField staterx filters state drop all unicast packets */ 3919255736Sdavidch#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 3920255736Sdavidch#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* BitField staterx filters state accept all unicast packets (subject to vlan) */ 3921255736Sdavidch#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 3922255736Sdavidch#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField staterx filters state accept all unmatched unicast packets (subject to vlan) */ 3923255736Sdavidch#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3924255736Sdavidch#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* BitField staterx filters state drop all multicast packets */ 3925255736Sdavidch#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 3926255736Sdavidch#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* BitField staterx filters state accept all multicast packets (subject to vlan) */ 3927255736Sdavidch#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 3928255736Sdavidch#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* BitField staterx filters state accept all broadcast packets (subject to vlan) */ 3929255736Sdavidch#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 3930255736Sdavidch#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* BitField staterx filters state accept packets matched only by MAC (without checking vlan) */ 3931255736Sdavidch#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 3932255736Sdavidch#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /* BitField staterx filters state */ 3933255736Sdavidch#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 3934255736Sdavidch uint16_t cqe_pause_thr_low /* number of remaining cqes under which, we send pause message */; 3935255736Sdavidch uint16_t cqe_pause_thr_high /* number of remaining cqes above which, we send un-pause message */; 3936255736Sdavidch uint16_t bd_pause_thr_low /* number of remaining bds under which, we send pause message */; 3937255736Sdavidch uint16_t bd_pause_thr_high /* number of remaining bds above which, we send un-pause message */; 3938255736Sdavidch uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */; 3939255736Sdavidch uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */; 3940255736Sdavidch uint16_t rx_cos_mask /* the bits that will be set on pfc/ safc paket whith will be genratet when this ring is full. for regular flow control set this to 1 */; 3941255736Sdavidch uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */; 3942255736Sdavidch uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */; 3943255736Sdavidch uint32_t reserved6[2]; 3944255736Sdavidch}; 3945255736Sdavidch 3946255736Sdavidch/* 3947255736Sdavidch * client init tx data $$KEEP_ENDIANNESS$$ 3948255736Sdavidch */ 3949255736Sdavidchstruct client_init_tx_data 3950255736Sdavidch{ 3951255736Sdavidch uint8_t enforce_security_flg /* if set, security checks will be made for this connection */; 3952255736Sdavidch uint8_t tx_status_block_id /* the number of status block to update */; 3953255736Sdavidch uint8_t tx_sb_index_number /* the index to use inside the status block */; 3954255736Sdavidch uint8_t tss_leading_client_id /* client ID of the leading TSS client, for TX classification source knock out */; 3955255736Sdavidch uint8_t tx_switching_flg /* if set, tx switching will be done to packets on this connection */; 3956255736Sdavidch uint8_t anti_spoofing_flg /* if set, anti spoofing check will be done to packets on this connection */; 3957255736Sdavidch uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */; 3958255736Sdavidch struct regpair tx_bd_page_base /* BD page base address at the host for TxBdCons */; 3959255736Sdavidch uint16_t state; 3960255736Sdavidch#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* BitField statetx filters state accept all unicast packets (subject to vlan) */ 3961255736Sdavidch#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 3962255736Sdavidch#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* BitField statetx filters state accept all multicast packets (subject to vlan) */ 3963255736Sdavidch#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 3964255736Sdavidch#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* BitField statetx filters state accept all broadcast packets (subject to vlan) */ 3965255736Sdavidch#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 3966255736Sdavidch#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* BitField statetx filters state accept packets matched only by MAC (without checking vlan) */ 3967255736Sdavidch#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 3968255736Sdavidch#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /* BitField statetx filters state */ 3969255736Sdavidch#define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4 3970255736Sdavidch uint8_t default_vlan_flg /* is default vlan valid for this client. */; 3971255736Sdavidch uint8_t force_default_pri_flg /* if set, force default priority */; 3972255736Sdavidch uint8_t tunnel_lso_inc_ip_id /* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header */; 3973255736Sdavidch uint8_t refuse_outband_vlan_flg /* if set, the FW will not add outband vlan on packet (even if will exist on BD). */; 3974255736Sdavidch uint8_t tunnel_non_lso_pcsum_location /* In case of non-Lso encapsulated packets with L4 checksum offload, the pseudo checksum location - on packet or on BD. */; 3975255736Sdavidch uint8_t tunnel_non_lso_outer_ip_csum_location /* In case of non-Lso encapsulated packets with outer L3 ip checksum offload, the pseudo checksum location - on packet or on BD. */; 3976255736Sdavidch}; 3977255736Sdavidch 3978255736Sdavidch/* 3979255736Sdavidch * client init ramrod data $$KEEP_ENDIANNESS$$ 3980255736Sdavidch */ 3981255736Sdavidchstruct client_init_ramrod_data 3982255736Sdavidch{ 3983255736Sdavidch struct client_init_general_data general /* client init general data */; 3984255736Sdavidch struct client_init_rx_data rx /* client init rx data */; 3985255736Sdavidch struct client_init_tx_data tx /* client init tx data */; 3986255736Sdavidch}; 3987255736Sdavidch 3988255736Sdavidch 3989255736Sdavidch/* 3990255736Sdavidch * client update ramrod data $$KEEP_ENDIANNESS$$ 3991255736Sdavidch */ 3992255736Sdavidchstruct client_update_ramrod_data 3993255736Sdavidch{ 3994255736Sdavidch uint8_t client_id /* the client to update */; 3995255736Sdavidch uint8_t func_id /* PCI function ID this client belongs to (0-71) */; 3996255736Sdavidch uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client, will be change according to change flag */; 3997255736Sdavidch uint8_t inner_vlan_removal_change_flg /* If set, inner VLAN removal flag will be set according to the enable flag */; 3998255736Sdavidch uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client, will be change according to change flag */; 3999255736Sdavidch uint8_t outer_vlan_removal_change_flg /* If set, outer VLAN removal flag will be set according to the enable flag */; 4000255736Sdavidch uint8_t anti_spoofing_enable_flg /* If set, anti spoofing is enabled for this client, will be change according to change flag */; 4001255736Sdavidch uint8_t anti_spoofing_change_flg /* If set, anti spoofing flag will be set according to anti spoofing flag */; 4002255736Sdavidch uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */; 4003255736Sdavidch uint8_t activate_change_flg /* If set, activate_flg will be checked */; 4004255736Sdavidch uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */; 4005255736Sdavidch uint8_t default_vlan_enable_flg; 4006255736Sdavidch uint8_t default_vlan_change_flg; 4007255736Sdavidch uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */; 4008255736Sdavidch uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */; 4009255736Sdavidch uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */; 4010255736Sdavidch uint8_t silent_vlan_change_flg; 4011255736Sdavidch uint8_t refuse_outband_vlan_flg /* If set, the FW will not add outband vlan on packet (even if will exist on BD). */; 4012255736Sdavidch uint8_t refuse_outband_vlan_change_flg /* If set, refuse_outband_vlan_flg will be updated. */; 4013255736Sdavidch uint8_t tx_switching_flg /* If set, tx switching will be done to packets on this connection. */; 4014255736Sdavidch uint8_t tx_switching_change_flg /* If set, tx_switching_flg will be updated. */; 4015255736Sdavidch uint32_t reserved1; 4016255736Sdavidch uint32_t echo /* echo value to be sent to driver on event ring */; 4017255736Sdavidch}; 4018255736Sdavidch 4019255736Sdavidch 4020255736Sdavidch/* 4021255736Sdavidch * The eth storm context of Cstorm 4022255736Sdavidch */ 4023255736Sdavidchstruct cstorm_eth_st_context 4024255736Sdavidch{ 4025255736Sdavidch uint32_t __reserved0[4]; 4026255736Sdavidch}; 4027255736Sdavidch 4028255736Sdavidch 4029255736Sdavidchstruct double_regpair 4030255736Sdavidch{ 4031255736Sdavidch uint32_t regpair0_lo /* low word for reg-pair0 */; 4032255736Sdavidch uint32_t regpair0_hi /* high word for reg-pair0 */; 4033255736Sdavidch uint32_t regpair1_lo /* low word for reg-pair1 */; 4034255736Sdavidch uint32_t regpair1_hi /* high word for reg-pair1 */; 4035255736Sdavidch}; 4036255736Sdavidch 4037255736Sdavidch 4038255736Sdavidch/* 4039255736Sdavidch * Ethernet address typesm used in ethernet tx BDs 4040255736Sdavidch */ 4041255736Sdavidchenum eth_addr_type 4042255736Sdavidch{ 4043255736Sdavidch UNKNOWN_ADDRESS, 4044255736Sdavidch UNICAST_ADDRESS, 4045255736Sdavidch MULTICAST_ADDRESS, 4046255736Sdavidch BROADCAST_ADDRESS, 4047255736Sdavidch MAX_ETH_ADDR_TYPE}; 4048255736Sdavidch 4049255736Sdavidch 4050255736Sdavidch/* 4051255736Sdavidch * $$KEEP_ENDIANNESS$$ 4052255736Sdavidch */ 4053255736Sdavidchstruct eth_classify_cmd_header 4054255736Sdavidch{ 4055255736Sdavidch uint8_t cmd_general_data; 4056255736Sdavidch#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ 4057255736Sdavidch#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 4058255736Sdavidch#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ 4059255736Sdavidch#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 4060255736Sdavidch#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* BitField cmd_general_data command opcode for MAC/VLAN/PAIR (use enum classify_rule) */ 4061255736Sdavidch#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 4062255736Sdavidch#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* BitField cmd_general_data (use enum classify_rule_action_type) */ 4063255736Sdavidch#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 4064255736Sdavidch#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* BitField cmd_general_data */ 4065255736Sdavidch#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 4066255736Sdavidch uint8_t func_id /* the function id */; 4067255736Sdavidch uint8_t client_id; 4068255736Sdavidch uint8_t reserved1; 4069255736Sdavidch}; 4070255736Sdavidch 4071255736Sdavidch 4072255736Sdavidch/* 4073255736Sdavidch * header for eth classification config ramrod $$KEEP_ENDIANNESS$$ 4074255736Sdavidch */ 4075255736Sdavidchstruct eth_classify_header 4076255736Sdavidch{ 4077255736Sdavidch uint8_t rule_cnt /* number of rules in classification config ramrod */; 4078255736Sdavidch uint8_t reserved0; 4079255736Sdavidch uint16_t reserved1; 4080255736Sdavidch uint32_t echo /* echo value to be sent to driver on event ring */; 4081255736Sdavidch}; 4082255736Sdavidch 4083255736Sdavidch 4084255736Sdavidch/* 4085255736Sdavidch * Command for adding/removing a MAC classification rule $$KEEP_ENDIANNESS$$ 4086255736Sdavidch */ 4087255736Sdavidchstruct eth_classify_mac_cmd 4088255736Sdavidch{ 4089255736Sdavidch struct eth_classify_cmd_header header; 4090255736Sdavidch uint16_t reserved0; 4091255736Sdavidch uint16_t inner_mac; 4092255736Sdavidch uint16_t mac_lsb; 4093255736Sdavidch uint16_t mac_mid; 4094255736Sdavidch uint16_t mac_msb; 4095255736Sdavidch uint16_t reserved1; 4096255736Sdavidch}; 4097255736Sdavidch 4098255736Sdavidch 4099255736Sdavidch/* 4100255736Sdavidch * Command for adding/removing a MAC-VLAN pair classification rule $$KEEP_ENDIANNESS$$ 4101255736Sdavidch */ 4102255736Sdavidchstruct eth_classify_pair_cmd 4103255736Sdavidch{ 4104255736Sdavidch struct eth_classify_cmd_header header; 4105255736Sdavidch uint16_t reserved0; 4106255736Sdavidch uint16_t inner_mac; 4107255736Sdavidch uint16_t mac_lsb; 4108255736Sdavidch uint16_t mac_mid; 4109255736Sdavidch uint16_t mac_msb; 4110255736Sdavidch uint16_t vlan; 4111255736Sdavidch}; 4112255736Sdavidch 4113255736Sdavidch 4114255736Sdavidch/* 4115255736Sdavidch * Command for adding/removing a VLAN classification rule $$KEEP_ENDIANNESS$$ 4116255736Sdavidch */ 4117255736Sdavidchstruct eth_classify_vlan_cmd 4118255736Sdavidch{ 4119255736Sdavidch struct eth_classify_cmd_header header; 4120255736Sdavidch uint32_t reserved0; 4121255736Sdavidch uint32_t reserved1; 4122255736Sdavidch uint16_t reserved2; 4123255736Sdavidch uint16_t vlan; 4124255736Sdavidch}; 4125255736Sdavidch 4126255736Sdavidch/* 4127255736Sdavidch * union for eth classification rule $$KEEP_ENDIANNESS$$ 4128255736Sdavidch */ 4129255736Sdavidchunion eth_classify_rule_cmd 4130255736Sdavidch{ 4131255736Sdavidch struct eth_classify_mac_cmd mac; 4132255736Sdavidch struct eth_classify_vlan_cmd vlan; 4133255736Sdavidch struct eth_classify_pair_cmd pair; 4134255736Sdavidch}; 4135255736Sdavidch 4136255736Sdavidch/* 4137255736Sdavidch * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$ 4138255736Sdavidch */ 4139255736Sdavidchstruct eth_classify_rules_ramrod_data 4140255736Sdavidch{ 4141255736Sdavidch struct eth_classify_header header; 4142255736Sdavidch union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 4143255736Sdavidch}; 4144255736Sdavidch 4145255736Sdavidch 4146255736Sdavidch/* 4147255736Sdavidch * The data contain client ID need to the ramrod $$KEEP_ENDIANNESS$$ 4148255736Sdavidch */ 4149255736Sdavidchstruct eth_common_ramrod_data 4150255736Sdavidch{ 4151255736Sdavidch uint32_t client_id /* id of this client. (5 bits are used) */; 4152255736Sdavidch uint32_t reserved1; 4153255736Sdavidch}; 4154255736Sdavidch 4155255736Sdavidch 4156255736Sdavidch/* 4157255736Sdavidch * The eth storm context of Ustorm 4158255736Sdavidch */ 4159255736Sdavidchstruct ustorm_eth_st_context 4160255736Sdavidch{ 4161255736Sdavidch uint32_t reserved0[52]; 4162255736Sdavidch}; 4163255736Sdavidch 4164255736Sdavidch/* 4165255736Sdavidch * The eth storm context of Tstorm 4166255736Sdavidch */ 4167255736Sdavidchstruct tstorm_eth_st_context 4168255736Sdavidch{ 4169255736Sdavidch uint32_t __reserved0[28]; 4170255736Sdavidch}; 4171255736Sdavidch 4172255736Sdavidch/* 4173255736Sdavidch * The eth storm context of Xstorm 4174255736Sdavidch */ 4175255736Sdavidchstruct xstorm_eth_st_context 4176255736Sdavidch{ 4177255736Sdavidch uint32_t reserved0[60]; 4178255736Sdavidch}; 4179255736Sdavidch 4180255736Sdavidch/* 4181255736Sdavidch * Ethernet connection context 4182255736Sdavidch */ 4183255736Sdavidchstruct eth_context 4184255736Sdavidch{ 4185255736Sdavidch struct ustorm_eth_st_context ustorm_st_context /* Ustorm storm context */; 4186255736Sdavidch struct tstorm_eth_st_context tstorm_st_context /* Tstorm storm context */; 4187255736Sdavidch struct xstorm_eth_ag_context xstorm_ag_context /* Xstorm aggregative context */; 4188255736Sdavidch struct tstorm_eth_ag_context tstorm_ag_context /* Tstorm aggregative context */; 4189255736Sdavidch struct cstorm_eth_ag_context cstorm_ag_context /* Cstorm aggregative context */; 4190255736Sdavidch struct ustorm_eth_ag_context ustorm_ag_context /* Ustorm aggregative context */; 4191255736Sdavidch struct timers_block_context timers_context /* Timers block context */; 4192255736Sdavidch struct xstorm_eth_st_context xstorm_st_context /* Xstorm storm context */; 4193255736Sdavidch struct cstorm_eth_st_context cstorm_st_context /* Cstorm storm context */; 4194255736Sdavidch}; 4195255736Sdavidch 4196255736Sdavidch 4197255736Sdavidch/* 4198255736Sdavidch * union for sgl and raw data. 4199255736Sdavidch */ 4200255736Sdavidchunion eth_sgl_or_raw_data 4201255736Sdavidch{ 4202255736Sdavidch uint16_t sgl[8] /* Scatter-gather list of SGEs used by this packet. This list includes the indices of the SGEs. */; 4203255736Sdavidch uint32_t raw_data[4] /* raw data from Tstorm to the driver. */; 4204255736Sdavidch}; 4205255736Sdavidch 4206255736Sdavidch/* 4207255736Sdavidch * eth FP end aggregation CQE parameters struct $$KEEP_ENDIANNESS$$ 4208255736Sdavidch */ 4209255736Sdavidchstruct eth_end_agg_rx_cqe 4210255736Sdavidch{ 4211255736Sdavidch uint8_t type_error_flags; 4212255736Sdavidch#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */ 4213255736Sdavidch#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 4214255736Sdavidch#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */ 4215255736Sdavidch#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 4216255736Sdavidch#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* BitField type_error_flags */ 4217255736Sdavidch#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 4218255736Sdavidch uint8_t reserved1; 4219255736Sdavidch uint8_t queue_index /* The aggregation queue index of this packet */; 4220255736Sdavidch uint8_t reserved2; 4221255736Sdavidch uint32_t timestamp_delta /* timestamp delta between first packet to last packet in aggregation */; 4222255736Sdavidch uint16_t num_of_coalesced_segs /* Num of coalesced segments. */; 4223255736Sdavidch uint16_t pkt_len /* Packet length */; 4224255736Sdavidch uint8_t pure_ack_count /* Number of pure acks coalesced. */; 4225255736Sdavidch uint8_t reserved3; 4226255736Sdavidch uint16_t reserved4; 4227255736Sdavidch union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */; 4228255736Sdavidch uint32_t reserved5[8]; 4229255736Sdavidch}; 4230255736Sdavidch 4231255736Sdavidch 4232255736Sdavidch/* 4233255736Sdavidch * regular eth FP CQE parameters struct $$KEEP_ENDIANNESS$$ 4234255736Sdavidch */ 4235255736Sdavidchstruct eth_fast_path_rx_cqe 4236255736Sdavidch{ 4237255736Sdavidch uint8_t type_error_flags; 4238255736Sdavidch#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */ 4239255736Sdavidch#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 4240255736Sdavidch#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */ 4241255736Sdavidch#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 4242255736Sdavidch#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* BitField type_error_flags Physical layer errors */ 4243255736Sdavidch#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 4244255736Sdavidch#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* BitField type_error_flags IP checksum error */ 4245255736Sdavidch#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 4246255736Sdavidch#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* BitField type_error_flags TCP/UDP checksum error */ 4247255736Sdavidch#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 4248255736Sdavidch#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) /* BitField type_error_flags */ 4249255736Sdavidch#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 4250255736Sdavidch uint8_t status_flags; 4251255736Sdavidch#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* BitField status_flags (use enum eth_rss_hash_type) */ 4252255736Sdavidch#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 4253255736Sdavidch#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* BitField status_flags RSS hashing on/off */ 4254255736Sdavidch#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 4255255736Sdavidch#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* BitField status_flags if set to 1, this is a broadcast packet */ 4256255736Sdavidch#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 4257255736Sdavidch#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* BitField status_flags if set to 1, the MAC address was matched in the tstorm CAM search */ 4258255736Sdavidch#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 4259255736Sdavidch#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* BitField status_flags IP checksum validation was not performed (if packet is not IPv4) */ 4260255736Sdavidch#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 4261255736Sdavidch#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* BitField status_flags TCP/UDP checksum validation was not performed (if packet is not TCP/UDP or IPv6 extheaders exist) */ 4262255736Sdavidch#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 4263255736Sdavidch uint8_t queue_index /* The aggregation queue index of this packet */; 4264255736Sdavidch uint8_t placement_offset /* Placement offset from the start of the BD, in bytes */; 4265255736Sdavidch uint32_t rss_hash_result /* RSS toeplitz hash result */; 4266255736Sdavidch uint16_t vlan_tag /* Ethernet VLAN tag field */; 4267255736Sdavidch uint16_t pkt_len_or_gro_seg_len /* Packet length (for non-TPA CQE) or GRO Segment Length (for TPA in GRO Mode) otherwise 0 */; 4268255736Sdavidch uint16_t len_on_bd /* Number of bytes placed on the BD */; 4269255736Sdavidch struct parsing_flags pars_flags; 4270255736Sdavidch union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */; 4271255736Sdavidch uint32_t reserved1[8]; 4272255736Sdavidch}; 4273255736Sdavidch 4274255736Sdavidch 4275255736Sdavidch/* 4276255736Sdavidch * Command for setting classification flags for a client $$KEEP_ENDIANNESS$$ 4277255736Sdavidch */ 4278255736Sdavidchstruct eth_filter_rules_cmd 4279255736Sdavidch{ 4280255736Sdavidch uint8_t cmd_general_data; 4281255736Sdavidch#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ 4282255736Sdavidch#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 4283255736Sdavidch#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ 4284255736Sdavidch#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 4285255736Sdavidch#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* BitField cmd_general_data */ 4286255736Sdavidch#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 4287255736Sdavidch uint8_t func_id /* the function id */; 4288255736Sdavidch uint8_t client_id /* the client id */; 4289255736Sdavidch uint8_t reserved1; 4290255736Sdavidch uint16_t state; 4291255736Sdavidch#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* BitField state drop all unicast packets */ 4292255736Sdavidch#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 4293255736Sdavidch#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* BitField state accept all unicast packets (subject to vlan) */ 4294255736Sdavidch#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 4295255736Sdavidch#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField state accept all unmatched unicast packets */ 4296255736Sdavidch#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 4297255736Sdavidch#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* BitField state drop all multicast packets */ 4298255736Sdavidch#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 4299255736Sdavidch#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* BitField state accept all multicast packets (subject to vlan) */ 4300255736Sdavidch#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 4301255736Sdavidch#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* BitField state accept all broadcast packets (subject to vlan) */ 4302255736Sdavidch#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 4303255736Sdavidch#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* BitField state accept packets matched only by MAC (without checking vlan) */ 4304255736Sdavidch#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 4305255736Sdavidch#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /* BitField state */ 4306255736Sdavidch#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 4307255736Sdavidch uint16_t reserved3; 4308255736Sdavidch struct regpair reserved4; 4309255736Sdavidch}; 4310255736Sdavidch 4311255736Sdavidch 4312255736Sdavidch/* 4313255736Sdavidch * parameters for eth classification filters ramrod $$KEEP_ENDIANNESS$$ 4314255736Sdavidch */ 4315255736Sdavidchstruct eth_filter_rules_ramrod_data 4316255736Sdavidch{ 4317255736Sdavidch struct eth_classify_header header; 4318255736Sdavidch struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 4319255736Sdavidch}; 4320255736Sdavidch 4321255736Sdavidch 4322255736Sdavidch/* 4323255736Sdavidch * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$ 4324255736Sdavidch */ 4325255736Sdavidchstruct eth_general_rules_ramrod_data 4326255736Sdavidch{ 4327255736Sdavidch struct eth_classify_header header; 4328255736Sdavidch union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 4329255736Sdavidch}; 4330255736Sdavidch 4331255736Sdavidch 4332255736Sdavidch/* 4333255736Sdavidch * The data for Halt ramrod 4334255736Sdavidch */ 4335255736Sdavidchstruct eth_halt_ramrod_data 4336255736Sdavidch{ 4337255736Sdavidch uint32_t client_id /* id of this client. (5 bits are used) */; 4338255736Sdavidch uint32_t reserved0; 4339255736Sdavidch}; 4340255736Sdavidch 4341255736Sdavidch 4342255736Sdavidch/* 4343255736Sdavidch * destination and source mac address. 4344255736Sdavidch */ 4345255736Sdavidchstruct eth_mac_addresses 4346255736Sdavidch{ 4347255736Sdavidch#if defined(__BIG_ENDIAN) 4348255736Sdavidch uint16_t dst_mid /* destination mac address 16 middle bits */; 4349255736Sdavidch uint16_t dst_lo /* destination mac address 16 low bits */; 4350255736Sdavidch#elif defined(__LITTLE_ENDIAN) 4351255736Sdavidch uint16_t dst_lo /* destination mac address 16 low bits */; 4352255736Sdavidch uint16_t dst_mid /* destination mac address 16 middle bits */; 4353255736Sdavidch#endif 4354255736Sdavidch#if defined(__BIG_ENDIAN) 4355255736Sdavidch uint16_t src_lo /* source mac address 16 low bits */; 4356255736Sdavidch uint16_t dst_hi /* destination mac address 16 high bits */; 4357255736Sdavidch#elif defined(__LITTLE_ENDIAN) 4358255736Sdavidch uint16_t dst_hi /* destination mac address 16 high bits */; 4359255736Sdavidch uint16_t src_lo /* source mac address 16 low bits */; 4360255736Sdavidch#endif 4361255736Sdavidch#if defined(__BIG_ENDIAN) 4362255736Sdavidch uint16_t src_hi /* source mac address 16 high bits */; 4363255736Sdavidch uint16_t src_mid /* source mac address 16 middle bits */; 4364255736Sdavidch#elif defined(__LITTLE_ENDIAN) 4365255736Sdavidch uint16_t src_mid /* source mac address 16 middle bits */; 4366255736Sdavidch uint16_t src_hi /* source mac address 16 high bits */; 4367255736Sdavidch#endif 4368255736Sdavidch}; 4369255736Sdavidch 4370255736Sdavidch 4371255736Sdavidch/* 4372255736Sdavidch * tunneling related data. 4373255736Sdavidch */ 4374255736Sdavidchstruct eth_tunnel_data 4375255736Sdavidch{ 4376255736Sdavidch#if defined(__BIG_ENDIAN) 4377255736Sdavidch uint16_t dst_mid /* destination mac address 16 middle bits */; 4378255736Sdavidch uint16_t dst_lo /* destination mac address 16 low bits */; 4379255736Sdavidch#elif defined(__LITTLE_ENDIAN) 4380255736Sdavidch uint16_t dst_lo /* destination mac address 16 low bits */; 4381255736Sdavidch uint16_t dst_mid /* destination mac address 16 middle bits */; 4382255736Sdavidch#endif 4383255736Sdavidch#if defined(__BIG_ENDIAN) 4384255736Sdavidch uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */; 4385255736Sdavidch uint16_t dst_hi /* destination mac address 16 high bits */; 4386255736Sdavidch#elif defined(__LITTLE_ENDIAN) 4387255736Sdavidch uint16_t dst_hi /* destination mac address 16 high bits */; 4388255736Sdavidch uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */; 4389255736Sdavidch#endif 4390255736Sdavidch#if defined(__BIG_ENDIAN) 4391255736Sdavidch uint8_t flags; 4392255736Sdavidch#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */ 4393255736Sdavidch#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0 4394255736Sdavidch#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */ 4395255736Sdavidch#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1 4396255736Sdavidch uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */; 4397255736Sdavidch uint16_t pseudo_csum /* Pseudo checksum with length field=0 */; 4398255736Sdavidch#elif defined(__LITTLE_ENDIAN) 4399255736Sdavidch uint16_t pseudo_csum /* Pseudo checksum with length field=0 */; 4400255736Sdavidch uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */; 4401255736Sdavidch uint8_t flags; 4402255736Sdavidch#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */ 4403255736Sdavidch#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0 4404255736Sdavidch#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */ 4405255736Sdavidch#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1 4406255736Sdavidch#endif 4407255736Sdavidch}; 4408255736Sdavidch 4409255736Sdavidch/* 4410255736Sdavidch * union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). 4411255736Sdavidch */ 4412255736Sdavidchunion eth_mac_addr_or_tunnel_data 4413255736Sdavidch{ 4414255736Sdavidch struct eth_mac_addresses mac_addr /* destination and source mac addresses. */; 4415255736Sdavidch struct eth_tunnel_data tunnel_data /* tunneling related data. */; 4416255736Sdavidch}; 4417255736Sdavidch 4418255736Sdavidch 4419255736Sdavidch/* 4420255736Sdavidch * Command for setting multicast classification for a client $$KEEP_ENDIANNESS$$ 4421255736Sdavidch */ 4422255736Sdavidchstruct eth_multicast_rules_cmd 4423255736Sdavidch{ 4424255736Sdavidch uint8_t cmd_general_data; 4425255736Sdavidch#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ 4426255736Sdavidch#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 4427255736Sdavidch#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ 4428255736Sdavidch#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 4429255736Sdavidch#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) /* BitField cmd_general_data 1 for add rule, 0 for remove rule */ 4430255736Sdavidch#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 4431255736Sdavidch#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* BitField cmd_general_data */ 4432255736Sdavidch#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 4433255736Sdavidch uint8_t func_id /* the function id */; 4434255736Sdavidch uint8_t bin_id /* the bin to add this function to (0-255) */; 4435255736Sdavidch uint8_t engine_id /* the approximate multicast engine id */; 4436255736Sdavidch uint32_t reserved2; 4437255736Sdavidch struct regpair reserved3; 4438255736Sdavidch}; 4439255736Sdavidch 4440255736Sdavidch 4441255736Sdavidch/* 4442255736Sdavidch * parameters for multicast classification ramrod $$KEEP_ENDIANNESS$$ 4443255736Sdavidch */ 4444255736Sdavidchstruct eth_multicast_rules_ramrod_data 4445255736Sdavidch{ 4446255736Sdavidch struct eth_classify_header header; 4447255736Sdavidch struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 4448255736Sdavidch}; 4449255736Sdavidch 4450255736Sdavidch 4451255736Sdavidch/* 4452255736Sdavidch * Place holder for ramrods protocol specific data 4453255736Sdavidch */ 4454255736Sdavidchstruct ramrod_data 4455255736Sdavidch{ 4456255736Sdavidch uint32_t data_lo; 4457255736Sdavidch uint32_t data_hi; 4458255736Sdavidch}; 4459255736Sdavidch 4460255736Sdavidch/* 4461255736Sdavidch * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 4462255736Sdavidch */ 4463255736Sdavidchunion eth_ramrod_data 4464255736Sdavidch{ 4465255736Sdavidch struct ramrod_data general; 4466255736Sdavidch}; 4467255736Sdavidch 4468255736Sdavidch 4469255736Sdavidch/* 4470255736Sdavidch * RSS toeplitz hash type, as reported in CQE 4471255736Sdavidch */ 4472255736Sdavidchenum eth_rss_hash_type 4473255736Sdavidch{ 4474255736Sdavidch DEFAULT_HASH_TYPE, 4475255736Sdavidch IPV4_HASH_TYPE, 4476255736Sdavidch TCP_IPV4_HASH_TYPE, 4477255736Sdavidch IPV6_HASH_TYPE, 4478255736Sdavidch TCP_IPV6_HASH_TYPE, 4479255736Sdavidch VLAN_PRI_HASH_TYPE, 4480255736Sdavidch E1HOV_PRI_HASH_TYPE, 4481255736Sdavidch DSCP_HASH_TYPE, 4482255736Sdavidch MAX_ETH_RSS_HASH_TYPE}; 4483255736Sdavidch 4484255736Sdavidch 4485255736Sdavidch/* 4486255736Sdavidch * Ethernet RSS mode 4487255736Sdavidch */ 4488255736Sdavidchenum eth_rss_mode 4489255736Sdavidch{ 4490255736Sdavidch ETH_RSS_MODE_DISABLED, 4491255736Sdavidch ETH_RSS_MODE_ESX51 /* RSS mode for Vmware ESX 5.1 (Only do RSS if packet is UDP with dst port that matches the UDP 4-tuble Destination Port mask and value) */, 4492255736Sdavidch ETH_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */, 4493255736Sdavidch ETH_RSS_MODE_VLAN_PRI /* RSS based on inner-vlan priority field */, 4494255736Sdavidch ETH_RSS_MODE_E1HOV_PRI /* RSS based on outer-vlan priority field */, 4495255736Sdavidch ETH_RSS_MODE_IP_DSCP /* RSS based on IPv4 DSCP field */, 4496255736Sdavidch MAX_ETH_RSS_MODE}; 4497255736Sdavidch 4498255736Sdavidch 4499255736Sdavidch/* 4500255736Sdavidch * parameters for RSS update ramrod (E2) $$KEEP_ENDIANNESS$$ 4501255736Sdavidch */ 4502255736Sdavidchstruct eth_rss_update_ramrod_data 4503255736Sdavidch{ 4504255736Sdavidch uint8_t rss_engine_id; 4505255736Sdavidch uint8_t capabilities; 4506255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 2-tupple capability */ 4507255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 4508255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for TCP */ 4509255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 4510255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for UDP */ 4511255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 4512255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 2-tupple capability */ 4513255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 4514255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for TCP */ 4515255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 4516255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for UDP */ 4517255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 4518255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) /* BitField capabilitiesFunction RSS capabilities configuration of the 5-tupple capability */ 4519255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6 4520255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) /* BitField capabilitiesFunction RSS capabilities if set update the rss keys */ 4521255736Sdavidch#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7 4522255736Sdavidch uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */; 4523255736Sdavidch uint8_t rss_mode /* The RSS mode for this function */; 4524255736Sdavidch uint16_t udp_4tuple_dst_port_mask /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */; 4525255736Sdavidch uint16_t udp_4tuple_dst_port_value /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */; 4526255736Sdavidch uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE] /* RSS indirection table */; 4527255736Sdavidch uint32_t rss_key[T_ETH_RSS_KEY] /* RSS key supplied as by OS */; 4528255736Sdavidch uint32_t echo; 4529255736Sdavidch uint32_t reserved3; 4530255736Sdavidch}; 4531255736Sdavidch 4532255736Sdavidch 4533255736Sdavidch/* 4534255736Sdavidch * The eth Rx Buffer Descriptor 4535255736Sdavidch */ 4536255736Sdavidchstruct eth_rx_bd 4537255736Sdavidch{ 4538255736Sdavidch uint32_t addr_lo /* Single continuous buffer low pointer */; 4539255736Sdavidch uint32_t addr_hi /* Single continuous buffer high pointer */; 4540255736Sdavidch}; 4541255736Sdavidch 4542255736Sdavidch 4543255736Sdavidch/* 4544255736Sdavidch * Eth Rx Cqe structure- general structure for ramrods $$KEEP_ENDIANNESS$$ 4545255736Sdavidch */ 4546255736Sdavidchstruct common_ramrod_eth_rx_cqe 4547255736Sdavidch{ 4548255736Sdavidch uint8_t ramrod_type; 4549255736Sdavidch#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* BitField ramrod_type (use enum eth_rx_cqe_type) */ 4550255736Sdavidch#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 4551255736Sdavidch#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* BitField ramrod_type */ 4552255736Sdavidch#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 4553255736Sdavidch#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* BitField ramrod_type */ 4554255736Sdavidch#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 4555255736Sdavidch uint8_t conn_type /* only 3 bits are used */; 4556255736Sdavidch uint16_t reserved1 /* protocol specific data */; 4557255736Sdavidch uint32_t conn_and_cmd_data; 4558255736Sdavidch#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */ 4559255736Sdavidch#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 4560255736Sdavidch#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use RamrodCommandIdEnum */ 4561255736Sdavidch#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 4562255736Sdavidch struct ramrod_data protocol_data /* protocol specific data */; 4563255736Sdavidch uint32_t echo; 4564255736Sdavidch uint32_t reserved2[11]; 4565255736Sdavidch}; 4566255736Sdavidch 4567255736Sdavidch/* 4568255736Sdavidch * Rx Last CQE in page (in ETH) 4569255736Sdavidch */ 4570255736Sdavidchstruct eth_rx_cqe_next_page 4571255736Sdavidch{ 4572255736Sdavidch uint32_t addr_lo /* Next page low pointer */; 4573255736Sdavidch uint32_t addr_hi /* Next page high pointer */; 4574255736Sdavidch uint32_t reserved[14]; 4575255736Sdavidch}; 4576255736Sdavidch 4577255736Sdavidch/* 4578255736Sdavidch * union for all eth rx cqe types (fix their sizes) 4579255736Sdavidch */ 4580255736Sdavidchunion eth_rx_cqe 4581255736Sdavidch{ 4582255736Sdavidch struct eth_fast_path_rx_cqe fast_path_cqe; 4583255736Sdavidch struct common_ramrod_eth_rx_cqe ramrod_cqe; 4584255736Sdavidch struct eth_rx_cqe_next_page next_page_cqe; 4585255736Sdavidch struct eth_end_agg_rx_cqe end_agg_cqe; 4586255736Sdavidch}; 4587255736Sdavidch 4588255736Sdavidch 4589255736Sdavidch/* 4590255736Sdavidch * Values for RX ETH CQE type field 4591255736Sdavidch */ 4592255736Sdavidchenum eth_rx_cqe_type 4593255736Sdavidch{ 4594255736Sdavidch RX_ETH_CQE_TYPE_ETH_FASTPATH /* Fast path CQE */, 4595255736Sdavidch RX_ETH_CQE_TYPE_ETH_RAMROD /* Slow path CQE */, 4596255736Sdavidch RX_ETH_CQE_TYPE_ETH_START_AGG /* Fast path CQE */, 4597255736Sdavidch RX_ETH_CQE_TYPE_ETH_STOP_AGG /* Slow path CQE */, 4598255736Sdavidch MAX_ETH_RX_CQE_TYPE}; 4599255736Sdavidch 4600255736Sdavidch 4601255736Sdavidch/* 4602255736Sdavidch * Type of SGL/Raw field in ETH RX fast path CQE 4603255736Sdavidch */ 4604255736Sdavidchenum eth_rx_fp_sel 4605255736Sdavidch{ 4606255736Sdavidch ETH_FP_CQE_REGULAR /* Regular CQE- no extra data */, 4607255736Sdavidch ETH_FP_CQE_RAW /* Extra data is raw data- iscsi OOO */, 4608255736Sdavidch MAX_ETH_RX_FP_SEL}; 4609255736Sdavidch 4610255736Sdavidch 4611255736Sdavidch/* 4612255736Sdavidch * The eth Rx SGE Descriptor 4613255736Sdavidch */ 4614255736Sdavidchstruct eth_rx_sge 4615255736Sdavidch{ 4616255736Sdavidch uint32_t addr_lo /* Single continuous buffer low pointer */; 4617255736Sdavidch uint32_t addr_hi /* Single continuous buffer high pointer */; 4618255736Sdavidch}; 4619255736Sdavidch 4620255736Sdavidch 4621255736Sdavidch/* 4622255736Sdavidch * common data for all protocols $$KEEP_ENDIANNESS$$ 4623255736Sdavidch */ 4624255736Sdavidchstruct spe_hdr 4625255736Sdavidch{ 4626255736Sdavidch uint32_t conn_and_cmd_data; 4627255736Sdavidch#define SPE_HDR_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */ 4628255736Sdavidch#define SPE_HDR_CID_SHIFT 0 4629255736Sdavidch#define SPE_HDR_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use enum common_spqe_cmd_id/eth_spqe_cmd_id/toe_spqe_cmd_id */ 4630255736Sdavidch#define SPE_HDR_CMD_ID_SHIFT 24 4631255736Sdavidch uint16_t type; 4632255736Sdavidch#define SPE_HDR_CONN_TYPE (0xFF<<0) /* BitField type connection type. (3 bits are used) (use enum connection_type) */ 4633255736Sdavidch#define SPE_HDR_CONN_TYPE_SHIFT 0 4634255736Sdavidch#define SPE_HDR_FUNCTION_ID (0xFF<<8) /* BitField type */ 4635255736Sdavidch#define SPE_HDR_FUNCTION_ID_SHIFT 8 4636255736Sdavidch uint16_t reserved1; 4637255736Sdavidch}; 4638255736Sdavidch 4639255736Sdavidch/* 4640255736Sdavidch * specific data for ethernet slow path element 4641255736Sdavidch */ 4642255736Sdavidchunion eth_specific_data 4643255736Sdavidch{ 4644255736Sdavidch uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */; 4645255736Sdavidch struct regpair client_update_ramrod_data /* The address of the data for client update ramrod */; 4646255736Sdavidch struct regpair client_init_ramrod_init_data /* The data for client setup ramrod */; 4647255736Sdavidch struct eth_halt_ramrod_data halt_ramrod_data /* Includes the client id to be deleted */; 4648255736Sdavidch struct regpair update_data_addr /* physical address of the eth_rss_update_ramrod_data struct, as allocated by the driver */; 4649255736Sdavidch struct eth_common_ramrod_data common_ramrod_data /* The data contain client ID need to the ramrod */; 4650255736Sdavidch struct regpair classify_cfg_addr /* physical address of the eth_classify_rules_ramrod_data struct, as allocated by the driver */; 4651255736Sdavidch struct regpair filter_cfg_addr /* physical address of the eth_filter_cfg_ramrod_data struct, as allocated by the driver */; 4652255736Sdavidch struct regpair mcast_cfg_addr /* physical address of the eth_mcast_cfg_ramrod_data struct, as allocated by the driver */; 4653255736Sdavidch}; 4654255736Sdavidch 4655255736Sdavidch/* 4656255736Sdavidch * Ethernet slow path element 4657255736Sdavidch */ 4658255736Sdavidchstruct eth_spe 4659255736Sdavidch{ 4660255736Sdavidch struct spe_hdr hdr /* common data for all protocols */; 4661255736Sdavidch union eth_specific_data data /* data specific to ethernet protocol */; 4662255736Sdavidch}; 4663255736Sdavidch 4664255736Sdavidch 4665255736Sdavidch/* 4666255736Sdavidch * Ethernet command ID for slow path elements 4667255736Sdavidch */ 4668255736Sdavidchenum eth_spqe_cmd_id 4669255736Sdavidch{ 4670255736Sdavidch RAMROD_CMD_ID_ETH_UNUSED, 4671255736Sdavidch RAMROD_CMD_ID_ETH_CLIENT_SETUP /* Setup a new L2 client */, 4672255736Sdavidch RAMROD_CMD_ID_ETH_HALT /* Halt an L2 client */, 4673255736Sdavidch RAMROD_CMD_ID_ETH_FORWARD_SETUP /* Setup a new FW channel */, 4674255736Sdavidch RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP /* Setup a new Tx only queue */, 4675255736Sdavidch RAMROD_CMD_ID_ETH_CLIENT_UPDATE /* Update an L2 client configuration */, 4676255736Sdavidch RAMROD_CMD_ID_ETH_EMPTY /* Empty ramrod - used to synchronize iSCSI OOO */, 4677255736Sdavidch RAMROD_CMD_ID_ETH_TERMINATE /* Terminate an L2 client */, 4678255736Sdavidch RAMROD_CMD_ID_ETH_TPA_UPDATE /* update the tpa roles in L2 client */, 4679255736Sdavidch RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, 4680255736Sdavidch RAMROD_CMD_ID_ETH_FILTER_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, 4681255736Sdavidch RAMROD_CMD_ID_ETH_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */, 4682255736Sdavidch RAMROD_CMD_ID_ETH_RSS_UPDATE /* Update RSS configuration */, 4683255736Sdavidch RAMROD_CMD_ID_ETH_SET_MAC /* Update RSS configuration */, 4684255736Sdavidch MAX_ETH_SPQE_CMD_ID}; 4685255736Sdavidch 4686255736Sdavidch 4687255736Sdavidch/* 4688255736Sdavidch * eth tpa update command 4689255736Sdavidch */ 4690255736Sdavidchenum eth_tpa_update_command 4691255736Sdavidch{ 4692255736Sdavidch TPA_UPDATE_NONE_COMMAND /* nop command */, 4693255736Sdavidch TPA_UPDATE_ENABLE_COMMAND /* enable command */, 4694255736Sdavidch TPA_UPDATE_DISABLE_COMMAND /* disable command */, 4695255736Sdavidch MAX_ETH_TPA_UPDATE_COMMAND}; 4696255736Sdavidch 4697255736Sdavidch 4698255736Sdavidch/* 4699255736Sdavidch * In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header 4700255736Sdavidch */ 4701255736Sdavidchenum eth_tunnel_lso_inc_ip_id 4702255736Sdavidch{ 4703255736Sdavidch EXT_HEADER /* Increment IP ID of external header (HW works on external, FW works on internal */, 4704255736Sdavidch INT_HEADER /* Increment IP ID of internal header (HW works on internal, FW works on external */, 4705255736Sdavidch MAX_ETH_TUNNEL_LSO_INC_IP_ID}; 4706255736Sdavidch 4707255736Sdavidch 4708255736Sdavidch/* 4709255736Sdavidch * In case tunnel exist and L4 checksum offload (or outer ip header checksum), the pseudo checksum location, on packet or on BD. 4710255736Sdavidch */ 4711255736Sdavidchenum eth_tunnel_non_lso_csum_location 4712255736Sdavidch{ 4713255736Sdavidch CSUM_ON_PKT /* checksum is on the packet. */, 4714255736Sdavidch CSUM_ON_BD /* checksum is on the BD. */, 4715255736Sdavidch MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION}; 4716255736Sdavidch 4717255736Sdavidch 4718255736Sdavidch/* 4719255736Sdavidch * Tx regular BD structure $$KEEP_ENDIANNESS$$ 4720255736Sdavidch */ 4721255736Sdavidchstruct eth_tx_bd 4722255736Sdavidch{ 4723255736Sdavidch uint32_t addr_lo /* Single continuous buffer low pointer */; 4724255736Sdavidch uint32_t addr_hi /* Single continuous buffer high pointer */; 4725255736Sdavidch uint16_t total_pkt_bytes /* Size of the entire packet, valid for non-LSO packets */; 4726255736Sdavidch uint16_t nbytes /* Size of the data represented by the BD */; 4727255736Sdavidch uint8_t reserved[4] /* keeps same size as other eth tx bd types */; 4728255736Sdavidch}; 4729255736Sdavidch 4730255736Sdavidch 4731255736Sdavidch/* 4732255736Sdavidch * structure for easy accessibility to assembler 4733255736Sdavidch */ 4734255736Sdavidchstruct eth_tx_bd_flags 4735255736Sdavidch{ 4736255736Sdavidch uint8_t as_bitfield; 4737255736Sdavidch#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* BitField as_bitfield IP CKSUM flag,Relevant in START */ 4738255736Sdavidch#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 4739255736Sdavidch#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* BitField as_bitfield L4 CKSUM flag,Relevant in START */ 4740255736Sdavidch#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 4741255736Sdavidch#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* BitField as_bitfield 00 - no vlan; 01 - inband Vlan; 10 outband Vlan (use enum eth_tx_vlan_type) */ 4742255736Sdavidch#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 4743255736Sdavidch#define ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* BitField as_bitfield Start of packet BD */ 4744255736Sdavidch#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 4745255736Sdavidch#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* BitField as_bitfield flag that indicates that the current packet is a udp packet */ 4746255736Sdavidch#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 4747255736Sdavidch#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* BitField as_bitfield LSO flag, Relevant in START */ 4748255736Sdavidch#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 4749255736Sdavidch#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* BitField as_bitfield set in case ipV6 packet, Relevant in START */ 4750255736Sdavidch#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 4751255736Sdavidch}; 4752255736Sdavidch 4753255736Sdavidch/* 4754255736Sdavidch * The eth Tx Buffer Descriptor $$KEEP_ENDIANNESS$$ 4755255736Sdavidch */ 4756255736Sdavidchstruct eth_tx_start_bd 4757255736Sdavidch{ 4758255736Sdavidch uint32_t addr_lo /* Single continuous buffer low pointer */; 4759255736Sdavidch uint32_t addr_hi /* Single continuous buffer high pointer */; 4760255736Sdavidch uint16_t nbd /* Num of BDs in packet: include parsInfoBD, Relevant in START(only in Everest) */; 4761255736Sdavidch uint16_t nbytes /* Size of the data represented by the BD */; 4762255736Sdavidch uint16_t vlan_or_ethertype /* Vlan structure: vlan_id is in lsb, then cfi and then priority vlan_id 12 bits (lsb), cfi 1 bit, priority 3 bits. In E2, this field should be set with etherType for VFs with no vlan */; 4763255736Sdavidch struct eth_tx_bd_flags bd_flags; 4764255736Sdavidch uint8_t general_data; 4765255736Sdavidch#define ETH_TX_START_BD_HDR_NBDS (0xF<<0) /* BitField general_data contains the number of BDs that contain Ethernet/IP/TCP headers, for full/partial LSO modes */ 4766255736Sdavidch#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 4767255736Sdavidch#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* BitField general_data force vlan mode according to bds (vlan mode can change accroding to global configuration) */ 4768255736Sdavidch#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 4769255736Sdavidch#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* BitField general_data Determines the number of parsing BDs in packet. Number of parsing BDs in packet is (parse_nbds+1). */ 4770255736Sdavidch#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 4771255736Sdavidch#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* BitField general_data set in case of tunneling encapsulated packet */ 4772255736Sdavidch#define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7 4773255736Sdavidch}; 4774255736Sdavidch 4775255736Sdavidch/* 4776255736Sdavidch * Tx parsing BD structure for ETH E1/E1h $$KEEP_ENDIANNESS$$ 4777255736Sdavidch */ 4778255736Sdavidchstruct eth_tx_parse_bd_e1x 4779255736Sdavidch{ 4780255736Sdavidch uint16_t global_data; 4781255736Sdavidch#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* BitField global_data IP header Offset in WORDs from start of packet */ 4782255736Sdavidch#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 4783255736Sdavidch#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* BitField global_data marks ethernet address type (use enum eth_addr_type) */ 4784255736Sdavidch#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 4785255736Sdavidch#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* BitField global_data */ 4786255736Sdavidch#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 4787255736Sdavidch#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* BitField global_data */ 4788255736Sdavidch#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 4789255736Sdavidch#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */ 4790255736Sdavidch#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 4791255736Sdavidch#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) /* BitField global_data reserved bit, should be set with 0 */ 4792255736Sdavidch#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 4793255736Sdavidch uint8_t tcp_flags; 4794255736Sdavidch#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */ 4795255736Sdavidch#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 4796255736Sdavidch#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */ 4797255736Sdavidch#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 4798255736Sdavidch#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */ 4799255736Sdavidch#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 4800255736Sdavidch#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */ 4801255736Sdavidch#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 4802255736Sdavidch#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */ 4803255736Sdavidch#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 4804255736Sdavidch#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */ 4805255736Sdavidch#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 4806255736Sdavidch#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */ 4807255736Sdavidch#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 4808255736Sdavidch#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */ 4809255736Sdavidch#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 4810255736Sdavidch uint8_t ip_hlen_w /* IP header length in WORDs */; 4811255736Sdavidch uint16_t total_hlen_w /* IP+TCP+ETH */; 4812255736Sdavidch uint16_t tcp_pseudo_csum /* Checksum of pseudo header with length field=0 */; 4813255736Sdavidch uint16_t lso_mss /* for LSO mode */; 4814255736Sdavidch uint16_t ip_id /* for LSO mode */; 4815255736Sdavidch uint32_t tcp_send_seq /* for LSO mode */; 4816255736Sdavidch}; 4817255736Sdavidch 4818255736Sdavidch/* 4819255736Sdavidch * Tx parsing BD structure for ETH E2 $$KEEP_ENDIANNESS$$ 4820255736Sdavidch */ 4821255736Sdavidchstruct eth_tx_parse_bd_e2 4822255736Sdavidch{ 4823255736Sdavidch union eth_mac_addr_or_tunnel_data data /* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). */; 4824255736Sdavidch uint32_t parsing_data; 4825255736Sdavidch#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /* BitField parsing_data TCP/UDP header Offset in WORDs from start of packet */ 4826255736Sdavidch#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0 4827255736Sdavidch#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* BitField parsing_data TCP header size in DOUBLE WORDS */ 4828255736Sdavidch#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 4829255736Sdavidch#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* BitField parsing_data a flag to indicate an ipv6 packet with extension headers. If set on LSO packet, pseudo CS should be placed in TCP CS field without length field */ 4830255736Sdavidch#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 4831255736Sdavidch#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) /* BitField parsing_data for LSO mode */ 4832255736Sdavidch#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 4833255736Sdavidch#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* BitField parsing_data marks ethernet address type (use enum eth_addr_type) */ 4834255736Sdavidch#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 4835255736Sdavidch}; 4836255736Sdavidch 4837255736Sdavidch/* 4838255736Sdavidch * Tx 2nd parsing BD structure for ETH packet $$KEEP_ENDIANNESS$$ 4839255736Sdavidch */ 4840255736Sdavidchstruct eth_tx_parse_2nd_bd 4841255736Sdavidch{ 4842255736Sdavidch uint16_t global_data; 4843255736Sdavidch#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* BitField global_data Outer IP header offset in WORDs (16-bit) from start of packet */ 4844255736Sdavidch#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 4845255736Sdavidch#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) /* BitField global_data should be set with 0 */ 4846255736Sdavidch#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4 4847255736Sdavidch#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* BitField global_data */ 4848255736Sdavidch#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 4849255736Sdavidch#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */ 4850255736Sdavidch#define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6 4851255736Sdavidch#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* BitField global_data Set in case UDP header exists in tunnel outer hedears. */ 4852255736Sdavidch#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 4853255736Sdavidch#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* BitField global_data Outer IP header length in WORDs (16-bit). Valid only for IpV4. */ 4854255736Sdavidch#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 4855255736Sdavidch#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) /* BitField global_data should be set with 0 */ 4856255736Sdavidch#define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13 4857255736Sdavidch uint16_t reserved2; 4858255736Sdavidch uint8_t tcp_flags; 4859255736Sdavidch#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */ 4860255736Sdavidch#define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 4861255736Sdavidch#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */ 4862255736Sdavidch#define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1 4863255736Sdavidch#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */ 4864255736Sdavidch#define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2 4865255736Sdavidch#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */ 4866255736Sdavidch#define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3 4867255736Sdavidch#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */ 4868255736Sdavidch#define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4 4869255736Sdavidch#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */ 4870255736Sdavidch#define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5 4871255736Sdavidch#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */ 4872255736Sdavidch#define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 4873255736Sdavidch#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */ 4874255736Sdavidch#define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 4875255736Sdavidch uint8_t reserved3; 4876255736Sdavidch uint8_t tunnel_udp_hdr_start_w /* Offset (in WORDs) from start of packet to tunnel UDP header. (if exist) */; 4877255736Sdavidch uint8_t fw_ip_hdr_to_payload_w /* In IpV4, the length (in WORDs) from the FW IpV4 header start to the payload start. In IpV6, the length (in WORDs) from the FW IpV6 header end to the payload start. However, if extension headers are included, their length is counted here as well. */; 4878255736Sdavidch uint16_t fw_ip_csum_wo_len_flags_frag /* For the IP header which is set by the FW, the IP checksum without length, flags and fragment offset. */; 4879255736Sdavidch uint16_t hw_ip_id /* The IP ID to be set by HW for LSO packets in tunnel mode. */; 4880255736Sdavidch uint32_t tcp_send_seq /* The TCP sequence number for LSO packets. */; 4881255736Sdavidch}; 4882255736Sdavidch 4883255736Sdavidch/* 4884255736Sdavidch * The last BD in the BD memory will hold a pointer to the next BD memory 4885255736Sdavidch */ 4886255736Sdavidchstruct eth_tx_next_bd 4887255736Sdavidch{ 4888255736Sdavidch uint32_t addr_lo /* Single continuous buffer low pointer */; 4889255736Sdavidch uint32_t addr_hi /* Single continuous buffer high pointer */; 4890255736Sdavidch uint8_t reserved[8] /* keeps same size as other eth tx bd types */; 4891255736Sdavidch}; 4892255736Sdavidch 4893255736Sdavidch/* 4894255736Sdavidch * union for 4 Bd types 4895255736Sdavidch */ 4896255736Sdavidchunion eth_tx_bd_types 4897255736Sdavidch{ 4898255736Sdavidch struct eth_tx_start_bd start_bd /* the first bd in a packets */; 4899255736Sdavidch struct eth_tx_bd reg_bd /* the common bd */; 4900255736Sdavidch struct eth_tx_parse_bd_e1x parse_bd_e1x /* parsing info BD for e1/e1h */; 4901255736Sdavidch struct eth_tx_parse_bd_e2 parse_bd_e2 /* parsing info BD for e2 */; 4902255736Sdavidch struct eth_tx_parse_2nd_bd parse_2nd_bd /* 2nd parsing info BD */; 4903255736Sdavidch struct eth_tx_next_bd next_bd /* Bd that contains the address of the next page */; 4904255736Sdavidch}; 4905255736Sdavidch 4906255736Sdavidch/* 4907255736Sdavidch * array of 13 bds as appears in the eth xstorm context 4908255736Sdavidch */ 4909255736Sdavidchstruct eth_tx_bds_array 4910255736Sdavidch{ 4911255736Sdavidch union eth_tx_bd_types bds[13]; 4912255736Sdavidch}; 4913255736Sdavidch 4914255736Sdavidch 4915255736Sdavidch/* 4916255736Sdavidch * VLAN mode on TX BDs 4917255736Sdavidch */ 4918255736Sdavidchenum eth_tx_vlan_type 4919255736Sdavidch{ 4920255736Sdavidch X_ETH_NO_VLAN, 4921255736Sdavidch X_ETH_OUTBAND_VLAN, 4922255736Sdavidch X_ETH_INBAND_VLAN, 4923255736Sdavidch X_ETH_FW_ADDED_VLAN /* Driver should not use this! */, 4924255736Sdavidch MAX_ETH_TX_VLAN_TYPE}; 4925255736Sdavidch 4926255736Sdavidch 4927255736Sdavidch/* 4928255736Sdavidch * Ethernet VLAN filtering mode in E1x 4929255736Sdavidch */ 4930255736Sdavidchenum eth_vlan_filter_mode 4931255736Sdavidch{ 4932255736Sdavidch ETH_VLAN_FILTER_ANY_VLAN /* Dont filter by vlan */, 4933255736Sdavidch ETH_VLAN_FILTER_SPECIFIC_VLAN /* Only the vlan_id is allowed */, 4934255736Sdavidch ETH_VLAN_FILTER_CLASSIFY /* Vlan will be added to CAM for classification */, 4935255736Sdavidch MAX_ETH_VLAN_FILTER_MODE}; 4936255736Sdavidch 4937255736Sdavidch 4938255736Sdavidch/* 4939255736Sdavidch * MAC filtering configuration command header $$KEEP_ENDIANNESS$$ 4940255736Sdavidch */ 4941255736Sdavidchstruct mac_configuration_hdr 4942255736Sdavidch{ 4943255736Sdavidch uint8_t length /* number of entries valid in this command (6 bits) */; 4944255736Sdavidch uint8_t offset /* offset of the first entry in the list */; 4945255736Sdavidch uint16_t client_id /* the client id which this ramrod is sent on. 5b is used. */; 4946255736Sdavidch uint32_t echo /* echo value to be sent to driver on event ring */; 4947255736Sdavidch}; 4948255736Sdavidch 4949255736Sdavidch/* 4950255736Sdavidch * MAC address in list for ramrod $$KEEP_ENDIANNESS$$ 4951255736Sdavidch */ 4952255736Sdavidchstruct mac_configuration_entry 4953255736Sdavidch{ 4954255736Sdavidch uint16_t lsb_mac_addr /* 2 LSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */; 4955255736Sdavidch uint16_t middle_mac_addr /* 2 middle bytes of MAC address (should be given in big endien - driver should do hton to this number!!!) */; 4956255736Sdavidch uint16_t msb_mac_addr /* 2 MSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */; 4957255736Sdavidch uint16_t vlan_id /* The inner vlan id (12b). Used either in vlan_in_cam for mac_valn pair or for vlan filtering */; 4958255736Sdavidch uint8_t pf_id /* The pf id, for multi function mode */; 4959255736Sdavidch uint8_t flags; 4960255736Sdavidch#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* BitField flags configures the action to be done in cam (used only is slow path handlers) (use enum set_mac_action_type) */ 4961255736Sdavidch#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 4962255736Sdavidch#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* BitField flags If set, this MAC also belongs to RDMA client */ 4963255736Sdavidch#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 4964255736Sdavidch#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* BitField flags (use enum eth_vlan_filter_mode) */ 4965255736Sdavidch#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 4966255736Sdavidch#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags BitField flags 0 - cant remove vlan 1 - can remove vlan. relevant only to everest1 */ 4967255736Sdavidch#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 4968255736Sdavidch#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) /* BitField flags BitField flags 0 - not broadcast 1 - broadcast. relevant only to everest1 */ 4969255736Sdavidch#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 4970255736Sdavidch#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* BitField flags */ 4971255736Sdavidch#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 4972255736Sdavidch uint16_t reserved0; 4973255736Sdavidch uint32_t clients_bit_vector /* Bit vector for the clients which should receive this MAC. */; 4974255736Sdavidch}; 4975255736Sdavidch 4976255736Sdavidch/* 4977255736Sdavidch * MAC filtering configuration command 4978255736Sdavidch */ 4979255736Sdavidchstruct mac_configuration_cmd 4980255736Sdavidch{ 4981255736Sdavidch struct mac_configuration_hdr hdr /* header */; 4982255736Sdavidch struct mac_configuration_entry config_table[64] /* table of 64 MAC configuration entries: addresses and target table entries */; 4983255736Sdavidch}; 4984255736Sdavidch 4985255736Sdavidch 4986255736Sdavidch/* 4987255736Sdavidch * Set-MAC command type (in E1x) 4988255736Sdavidch */ 4989255736Sdavidchenum set_mac_action_type 4990255736Sdavidch{ 4991255736Sdavidch T_ETH_MAC_COMMAND_INVALIDATE, 4992255736Sdavidch T_ETH_MAC_COMMAND_SET, 4993255736Sdavidch MAX_SET_MAC_ACTION_TYPE}; 4994255736Sdavidch 4995255736Sdavidch 4996255736Sdavidch/* 4997255736Sdavidch * Ethernet TPA Modes 4998255736Sdavidch */ 4999255736Sdavidchenum tpa_mode 5000255736Sdavidch{ 5001255736Sdavidch TPA_LRO /* LRO mode TPA */, 5002255736Sdavidch TPA_GRO /* GRO mode TPA */, 5003255736Sdavidch MAX_TPA_MODE}; 5004255736Sdavidch 5005255736Sdavidch 5006255736Sdavidch/* 5007255736Sdavidch * tpa update ramrod data $$KEEP_ENDIANNESS$$ 5008255736Sdavidch */ 5009255736Sdavidchstruct tpa_update_ramrod_data 5010255736Sdavidch{ 5011255736Sdavidch uint8_t update_ipv4 /* none, enable or disable */; 5012255736Sdavidch uint8_t update_ipv6 /* none, enable or disable */; 5013255736Sdavidch uint8_t client_id /* client init flow control data */; 5014255736Sdavidch uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */; 5015255736Sdavidch uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */; 5016255736Sdavidch uint8_t complete_on_both_clients /* If set and the client has different sp_client, completion will be sent to both rings */; 5017255736Sdavidch uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */; 5018255736Sdavidch uint8_t tpa_mode /* TPA mode to use (LRO or GRO) */; 5019255736Sdavidch uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */; 5020255736Sdavidch uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */; 5021255736Sdavidch uint32_t sge_page_base_lo /* The address to fetch the next sges from (low) */; 5022255736Sdavidch uint32_t sge_page_base_hi /* The address to fetch the next sges from (high) */; 5023255736Sdavidch uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */; 5024255736Sdavidch uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */; 5025255736Sdavidch}; 5026255736Sdavidch 5027255736Sdavidch 5028255736Sdavidch/* 5029255736Sdavidch * approximate-match multicast filtering for E1H per function in Tstorm 5030255736Sdavidch */ 5031255736Sdavidchstruct tstorm_eth_approximate_match_multicast_filtering 5032255736Sdavidch{ 5033255736Sdavidch uint32_t mcast_add_hash_bit_array[8] /* Bit array for multicast hash filtering.Each bit supports a hash function result if to accept this multicast dst address. */; 5034255736Sdavidch}; 5035255736Sdavidch 5036255736Sdavidch 5037255736Sdavidch/* 5038255736Sdavidch * Common configuration parameters per function in Tstorm $$KEEP_ENDIANNESS$$ 5039255736Sdavidch */ 5040255736Sdavidchstruct tstorm_eth_function_common_config 5041255736Sdavidch{ 5042255736Sdavidch uint16_t config_flags; 5043255736Sdavidch#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */ 5044255736Sdavidch#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 5045255736Sdavidch#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 4-tupple capability */ 5046255736Sdavidch#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 5047255736Sdavidch#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */ 5048255736Sdavidch#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 5049255736Sdavidch#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV6 4-tupple capability */ 5050255736Sdavidch#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 5051255736Sdavidch#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* BitField config_flagsGeneral configuration flags RSS mode of operation (use enum eth_rss_mode) */ 5052255736Sdavidch#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 5053255736Sdavidch#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuration flags 0 - Dont filter by vlan, 1 - Filter according to the vlans specificied in mac_filter_config */ 5054255736Sdavidch#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 5055255736Sdavidch#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* BitField config_flagsGeneral configuration flags */ 5056255736Sdavidch#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 5057255736Sdavidch uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */; 5058255736Sdavidch uint8_t reserved1; 5059255736Sdavidch uint16_t vlan_id[2] /* VLANs of this function. VLAN filtering is determine according to vlan_filtering_enable. */; 5060255736Sdavidch}; 5061255736Sdavidch 5062255736Sdavidch 5063255736Sdavidch/* 5064255736Sdavidch * MAC filtering configuration parameters per port in Tstorm $$KEEP_ENDIANNESS$$ 5065255736Sdavidch */ 5066255736Sdavidchstruct tstorm_eth_mac_filter_config 5067255736Sdavidch{ 5068255736Sdavidch uint32_t ucast_drop_all /* bit vector in which the clients which drop all unicast packets are set */; 5069255736Sdavidch uint32_t ucast_accept_all /* bit vector in which clients that accept all unicast packets are set */; 5070255736Sdavidch uint32_t mcast_drop_all /* bit vector in which the clients which drop all multicast packets are set */; 5071255736Sdavidch uint32_t mcast_accept_all /* bit vector in which clients that accept all multicast packets are set */; 5072255736Sdavidch uint32_t bcast_accept_all /* bit vector in which clients that accept all broadcast packets are set */; 5073255736Sdavidch uint32_t vlan_filter[2] /* bit vector for VLAN filtering. Clients which enforce filtering of vlan[x] should be marked in vlan_filter[x]. In E1 only vlan_filter[1] is checked. The primary vlan is taken from the CAM target table. */; 5074255736Sdavidch uint32_t unmatched_unicast /* bit vector in which clients that accept unmatched unicast packets are set */; 5075255736Sdavidch}; 5076255736Sdavidch 5077255736Sdavidch 5078255736Sdavidch/* 5079255736Sdavidch * tx only queue init ramrod data $$KEEP_ENDIANNESS$$ 5080255736Sdavidch */ 5081255736Sdavidchstruct tx_queue_init_ramrod_data 5082255736Sdavidch{ 5083255736Sdavidch struct client_init_general_data general /* client init general data */; 5084255736Sdavidch struct client_init_tx_data tx /* client init tx data */; 5085255736Sdavidch}; 5086255736Sdavidch 5087255736Sdavidch 5088255736Sdavidch/* 5089255736Sdavidch * Three RX producers for ETH 5090255736Sdavidch */ 5091255736Sdavidchstruct ustorm_eth_rx_producers 5092255736Sdavidch{ 5093255736Sdavidch#if defined(__BIG_ENDIAN) 5094255736Sdavidch uint16_t bd_prod /* Producer of the RX BD ring */; 5095255736Sdavidch uint16_t cqe_prod /* Producer of the RX CQE ring */; 5096255736Sdavidch#elif defined(__LITTLE_ENDIAN) 5097255736Sdavidch uint16_t cqe_prod /* Producer of the RX CQE ring */; 5098255736Sdavidch uint16_t bd_prod /* Producer of the RX BD ring */; 5099255736Sdavidch#endif 5100255736Sdavidch#if defined(__BIG_ENDIAN) 5101255736Sdavidch uint16_t reserved; 5102255736Sdavidch uint16_t sge_prod /* Producer of the RX SGE ring */; 5103255736Sdavidch#elif defined(__LITTLE_ENDIAN) 5104255736Sdavidch uint16_t sge_prod /* Producer of the RX SGE ring */; 5105255736Sdavidch uint16_t reserved; 5106255736Sdavidch#endif 5107255736Sdavidch}; 5108255736Sdavidch 5109255736Sdavidch 5110255736Sdavidch/* 5111255736Sdavidch * The data afex vif list ramrod need $$KEEP_ENDIANNESS$$ 5112255736Sdavidch */ 5113255736Sdavidchstruct afex_vif_list_ramrod_data 5114255736Sdavidch{ 5115255736Sdavidch uint8_t afex_vif_list_command /* set get, clear all a VIF list id defined by enum vif_list_rule_kind */; 5116255736Sdavidch uint8_t func_bit_map /* the function bit map to set */; 5117255736Sdavidch uint16_t vif_list_index /* the VIF list, in a per pf vector to add this function to */; 5118255736Sdavidch uint8_t func_to_clear /* the func id to clear in case of clear func mode */; 5119255736Sdavidch uint8_t echo; 5120255736Sdavidch uint16_t reserved1; 5121255736Sdavidch}; 5122255736Sdavidch 5123255736Sdavidch 5124255736Sdavidch/* 5125255736Sdavidch * cfc delete event data $$KEEP_ENDIANNESS$$ 5126255736Sdavidch */ 5127255736Sdavidchstruct cfc_del_event_data 5128255736Sdavidch{ 5129255736Sdavidch uint32_t cid /* cid of deleted connection */; 5130255736Sdavidch uint32_t reserved0; 5131255736Sdavidch uint32_t reserved1; 5132255736Sdavidch}; 5133255736Sdavidch 5134255736Sdavidch 5135255736Sdavidch/* 5136255736Sdavidch * per-port SAFC demo variables 5137255736Sdavidch */ 5138255736Sdavidchstruct cmng_flags_per_port 5139255736Sdavidch{ 5140255736Sdavidch uint32_t cmng_enables; 5141255736Sdavidch#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between vnics */ 5142255736Sdavidch#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 5143255736Sdavidch#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable rate shaping between vnics */ 5144255736Sdavidch#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 5145255736Sdavidch#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between COSes */ 5146255736Sdavidch#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 5147255736Sdavidch#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes (use enum fairness_mode) */ 5148255736Sdavidch#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 5149255736Sdavidch#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes reserved */ 5150255736Sdavidch#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 5151255736Sdavidch uint32_t __reserved1; 5152255736Sdavidch}; 5153255736Sdavidch 5154255736Sdavidch 5155255736Sdavidch/* 5156255736Sdavidch * per-port rate shaping variables 5157255736Sdavidch */ 5158255736Sdavidchstruct rate_shaping_vars_per_port 5159255736Sdavidch{ 5160255736Sdavidch uint32_t rs_periodic_timeout /* timeout of periodic timer */; 5161255736Sdavidch uint32_t rs_threshold /* threshold, below which we start to stop queues */; 5162255736Sdavidch}; 5163255736Sdavidch 5164255736Sdavidch/* 5165255736Sdavidch * per-port fairness variables 5166255736Sdavidch */ 5167255736Sdavidchstruct fairness_vars_per_port 5168255736Sdavidch{ 5169255736Sdavidch uint32_t upper_bound /* Quota for a protocol/vnic */; 5170255736Sdavidch uint32_t fair_threshold /* almost-empty threshold */; 5171255736Sdavidch uint32_t fairness_timeout /* timeout of fairness timer */; 5172255736Sdavidch uint32_t reserved0; 5173255736Sdavidch}; 5174255736Sdavidch 5175255736Sdavidch/* 5176255736Sdavidch * per-port SAFC variables 5177255736Sdavidch */ 5178255736Sdavidchstruct safc_struct_per_port 5179255736Sdavidch{ 5180255736Sdavidch#if defined(__BIG_ENDIAN) 5181255736Sdavidch uint16_t __reserved1; 5182255736Sdavidch uint8_t __reserved0; 5183255736Sdavidch uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */; 5184255736Sdavidch#elif defined(__LITTLE_ENDIAN) 5185255736Sdavidch uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */; 5186255736Sdavidch uint8_t __reserved0; 5187255736Sdavidch uint16_t __reserved1; 5188255736Sdavidch#endif 5189255736Sdavidch uint8_t cos_to_traffic_types[MAX_COS_NUMBER] /* translate cos to service traffics types */; 5190255736Sdavidch uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS] /* QM pause mask for each class of service in the SAFC frame */; 5191255736Sdavidch}; 5192255736Sdavidch 5193255736Sdavidch/* 5194255736Sdavidch * Per-port congestion management variables 5195255736Sdavidch */ 5196255736Sdavidchstruct cmng_struct_per_port 5197255736Sdavidch{ 5198255736Sdavidch struct rate_shaping_vars_per_port rs_vars; 5199255736Sdavidch struct fairness_vars_per_port fair_vars; 5200255736Sdavidch struct safc_struct_per_port safc_vars; 5201255736Sdavidch struct cmng_flags_per_port flags; 5202255736Sdavidch}; 5203255736Sdavidch 5204255736Sdavidch/* 5205255736Sdavidch * a single rate shaping counter. can be used as protocol or vnic counter 5206255736Sdavidch */ 5207255736Sdavidchstruct rate_shaping_counter 5208255736Sdavidch{ 5209255736Sdavidch uint32_t quota /* Quota for a protocol/vnic */; 5210255736Sdavidch#if defined(__BIG_ENDIAN) 5211255736Sdavidch uint16_t __reserved0; 5212255736Sdavidch uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */; 5213255736Sdavidch#elif defined(__LITTLE_ENDIAN) 5214255736Sdavidch uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */; 5215255736Sdavidch uint16_t __reserved0; 5216255736Sdavidch#endif 5217255736Sdavidch}; 5218255736Sdavidch 5219255736Sdavidch/* 5220255736Sdavidch * per-vnic rate shaping variables 5221255736Sdavidch */ 5222255736Sdavidchstruct rate_shaping_vars_per_vn 5223255736Sdavidch{ 5224255736Sdavidch struct rate_shaping_counter vn_counter /* per-vnic counter */; 5225255736Sdavidch}; 5226255736Sdavidch 5227255736Sdavidch/* 5228255736Sdavidch * per-vnic fairness variables 5229255736Sdavidch */ 5230255736Sdavidchstruct fairness_vars_per_vn 5231255736Sdavidch{ 5232255736Sdavidch uint32_t cos_credit_delta[MAX_COS_NUMBER] /* used for incrementing the credit */; 5233255736Sdavidch uint32_t vn_credit_delta /* used for incrementing the credit */; 5234255736Sdavidch uint32_t __reserved0; 5235255736Sdavidch}; 5236255736Sdavidch 5237255736Sdavidch/* 5238255736Sdavidch * cmng port init state 5239255736Sdavidch */ 5240255736Sdavidchstruct cmng_vnic 5241255736Sdavidch{ 5242255736Sdavidch struct rate_shaping_vars_per_vn vnic_max_rate[4]; 5243255736Sdavidch struct fairness_vars_per_vn vnic_min_rate[4]; 5244255736Sdavidch}; 5245255736Sdavidch 5246255736Sdavidch/* 5247255736Sdavidch * cmng port init state 5248255736Sdavidch */ 5249255736Sdavidchstruct cmng_init 5250255736Sdavidch{ 5251255736Sdavidch struct cmng_struct_per_port port; 5252255736Sdavidch struct cmng_vnic vnic; 5253255736Sdavidch}; 5254255736Sdavidch 5255255736Sdavidch 5256255736Sdavidch/* 5257255736Sdavidch * driver parameters for congestion management init, all rates are in Mbps 5258255736Sdavidch */ 5259255736Sdavidchstruct cmng_init_input 5260255736Sdavidch{ 5261255736Sdavidch uint32_t port_rate; 5262255736Sdavidch uint16_t vnic_min_rate[4] /* rates are in Mbps */; 5263255736Sdavidch uint16_t vnic_max_rate[4] /* rates are in Mbps */; 5264255736Sdavidch uint16_t cos_min_rate[MAX_COS_NUMBER] /* rates are in Mbps */; 5265255736Sdavidch uint16_t cos_to_pause_mask[MAX_COS_NUMBER]; 5266255736Sdavidch struct cmng_flags_per_port flags; 5267255736Sdavidch}; 5268255736Sdavidch 5269255736Sdavidch 5270255736Sdavidch/* 5271255736Sdavidch * Protocol-common command ID for slow path elements 5272255736Sdavidch */ 5273255736Sdavidchenum common_spqe_cmd_id 5274255736Sdavidch{ 5275255736Sdavidch RAMROD_CMD_ID_COMMON_UNUSED, 5276255736Sdavidch RAMROD_CMD_ID_COMMON_FUNCTION_START /* Start a function (for PFs only) */, 5277255736Sdavidch RAMROD_CMD_ID_COMMON_FUNCTION_STOP /* Stop a function (for PFs only) */, 5278255736Sdavidch RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE /* niv update function */, 5279255736Sdavidch RAMROD_CMD_ID_COMMON_CFC_DEL /* Delete a connection from CFC */, 5280255736Sdavidch RAMROD_CMD_ID_COMMON_CFC_DEL_WB /* Delete a connection from CFC (with write back) */, 5281255736Sdavidch RAMROD_CMD_ID_COMMON_STAT_QUERY /* Collect statistics counters */, 5282255736Sdavidch RAMROD_CMD_ID_COMMON_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */, 5283255736Sdavidch RAMROD_CMD_ID_COMMON_START_TRAFFIC /* Start Tx traffic (after DCB updates) */, 5284255736Sdavidch RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS /* niv vif lists */, 5285255736Sdavidch RAMROD_CMD_ID_COMMON_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */, 5286255736Sdavidch MAX_COMMON_SPQE_CMD_ID}; 5287255736Sdavidch 5288255736Sdavidch 5289255736Sdavidch/* 5290255736Sdavidch * Per-protocol connection types 5291255736Sdavidch */ 5292255736Sdavidchenum connection_type 5293255736Sdavidch{ 5294255736Sdavidch ETH_CONNECTION_TYPE /* Ethernet */, 5295255736Sdavidch TOE_CONNECTION_TYPE /* TOE */, 5296255736Sdavidch RDMA_CONNECTION_TYPE /* RDMA */, 5297255736Sdavidch ISCSI_CONNECTION_TYPE /* iSCSI */, 5298255736Sdavidch FCOE_CONNECTION_TYPE /* FCoE */, 5299255736Sdavidch RESERVED_CONNECTION_TYPE_0, 5300255736Sdavidch RESERVED_CONNECTION_TYPE_1, 5301255736Sdavidch RESERVED_CONNECTION_TYPE_2, 5302255736Sdavidch NONE_CONNECTION_TYPE /* General- used for common slow path */, 5303255736Sdavidch MAX_CONNECTION_TYPE}; 5304255736Sdavidch 5305255736Sdavidch 5306255736Sdavidch/* 5307255736Sdavidch * Cos modes 5308255736Sdavidch */ 5309255736Sdavidchenum cos_mode 5310255736Sdavidch{ 5311255736Sdavidch OVERRIDE_COS /* Firmware deduce cos according to DCB */, 5312255736Sdavidch STATIC_COS /* Firmware has constant queues per CoS */, 5313255736Sdavidch FW_WRR /* Firmware keep fairness between different CoSes */, 5314255736Sdavidch MAX_COS_MODE}; 5315255736Sdavidch 5316255736Sdavidch 5317255736Sdavidch/* 5318255736Sdavidch * Dynamic HC counters set by the driver 5319255736Sdavidch */ 5320255736Sdavidchstruct hc_dynamic_drv_counter 5321255736Sdavidch{ 5322255736Sdavidch uint32_t val[HC_SB_MAX_DYNAMIC_INDICES] /* 4 bytes * 4 indices = 2 lines */; 5323255736Sdavidch}; 5324255736Sdavidch 5325255736Sdavidch/* 5326255736Sdavidch * zone A per-queue data 5327255736Sdavidch */ 5328255736Sdavidchstruct cstorm_queue_zone_data 5329255736Sdavidch{ 5330255736Sdavidch struct hc_dynamic_drv_counter hc_dyn_drv_cnt /* 4 bytes * 4 indices = 2 lines */; 5331255736Sdavidch struct regpair reserved[2]; 5332255736Sdavidch}; 5333255736Sdavidch 5334255736Sdavidch 5335255736Sdavidch/* 5336255736Sdavidch * Vf-PF channel data in cstorm ram (non-triggered zone) 5337255736Sdavidch */ 5338255736Sdavidchstruct vf_pf_channel_zone_data 5339255736Sdavidch{ 5340255736Sdavidch uint32_t msg_addr_lo /* the message address on VF memory */; 5341255736Sdavidch uint32_t msg_addr_hi /* the message address on VF memory */; 5342255736Sdavidch}; 5343255736Sdavidch 5344255736Sdavidch/* 5345255736Sdavidch * zone for VF non-triggered data 5346255736Sdavidch */ 5347255736Sdavidchstruct non_trigger_vf_zone 5348255736Sdavidch{ 5349255736Sdavidch struct vf_pf_channel_zone_data vf_pf_channel /* vf-pf channel zone data */; 5350255736Sdavidch}; 5351255736Sdavidch 5352255736Sdavidch/* 5353255736Sdavidch * Vf-PF channel trigger zone in cstorm ram 5354255736Sdavidch */ 5355255736Sdavidchstruct vf_pf_channel_zone_trigger 5356255736Sdavidch{ 5357255736Sdavidch uint8_t addr_valid /* indicates that a vf-pf message is pending. MUST be set AFTER the message address. */; 5358255736Sdavidch}; 5359255736Sdavidch 5360255736Sdavidch/* 5361255736Sdavidch * zone that triggers the in-bound interrupt 5362255736Sdavidch */ 5363255736Sdavidchstruct trigger_vf_zone 5364255736Sdavidch{ 5365255736Sdavidch#if defined(__BIG_ENDIAN) 5366255736Sdavidch uint16_t reserved1; 5367255736Sdavidch uint8_t reserved0; 5368255736Sdavidch struct vf_pf_channel_zone_trigger vf_pf_channel; 5369255736Sdavidch#elif defined(__LITTLE_ENDIAN) 5370255736Sdavidch struct vf_pf_channel_zone_trigger vf_pf_channel; 5371255736Sdavidch uint8_t reserved0; 5372255736Sdavidch uint16_t reserved1; 5373255736Sdavidch#endif 5374255736Sdavidch uint32_t reserved2; 5375255736Sdavidch}; 5376255736Sdavidch 5377255736Sdavidch/* 5378255736Sdavidch * zone B per-VF data 5379255736Sdavidch */ 5380255736Sdavidchstruct cstorm_vf_zone_data 5381255736Sdavidch{ 5382255736Sdavidch struct non_trigger_vf_zone non_trigger /* zone for VF non-triggered data */; 5383255736Sdavidch struct trigger_vf_zone trigger /* zone that triggers the in-bound interrupt */; 5384255736Sdavidch}; 5385255736Sdavidch 5386255736Sdavidch 5387255736Sdavidch/* 5388255736Sdavidch * Dynamic host coalescing init parameters, per state machine 5389255736Sdavidch */ 5390255736Sdavidchstruct dynamic_hc_sm_config 5391255736Sdavidch{ 5392255736Sdavidch uint32_t threshold[3] /* thresholds of number of outstanding bytes */; 5393255736Sdavidch uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES] /* bytes difference of each protocol is shifted right by this value */; 5394255736Sdavidch uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 0 for each protocol, in units of usec */; 5395255736Sdavidch uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 1 for each protocol, in units of usec */; 5396255736Sdavidch uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 2 for each protocol, in units of usec */; 5397255736Sdavidch uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 3 for each protocol, in units of usec */; 5398255736Sdavidch}; 5399255736Sdavidch 5400255736Sdavidch/* 5401255736Sdavidch * Dynamic host coalescing init parameters 5402255736Sdavidch */ 5403255736Sdavidchstruct dynamic_hc_config 5404255736Sdavidch{ 5405255736Sdavidch struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM] /* Configuration per state machine */; 5406255736Sdavidch}; 5407255736Sdavidch 5408255736Sdavidch 5409255736Sdavidchstruct e2_integ_data 5410255736Sdavidch{ 5411255736Sdavidch#if defined(__BIG_ENDIAN) 5412255736Sdavidch uint8_t flags; 5413255736Sdavidch#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */ 5414255736Sdavidch#define E2_INTEG_DATA_TESTING_EN_SHIFT 0 5415255736Sdavidch#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */ 5416255736Sdavidch#define E2_INTEG_DATA_LB_TX_SHIFT 1 5417255736Sdavidch#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */ 5418255736Sdavidch#define E2_INTEG_DATA_COS_TX_SHIFT 2 5419255736Sdavidch#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */ 5420255736Sdavidch#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 5421255736Sdavidch#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */ 5422255736Sdavidch#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 5423255736Sdavidch#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */ 5424255736Sdavidch#define E2_INTEG_DATA_RESERVED_SHIFT 5 5425255736Sdavidch uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */; 5426255736Sdavidch uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5427255736Sdavidch uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5428255736Sdavidch#elif defined(__LITTLE_ENDIAN) 5429255736Sdavidch uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5430255736Sdavidch uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5431255736Sdavidch uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */; 5432255736Sdavidch uint8_t flags; 5433255736Sdavidch#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */ 5434255736Sdavidch#define E2_INTEG_DATA_TESTING_EN_SHIFT 0 5435255736Sdavidch#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */ 5436255736Sdavidch#define E2_INTEG_DATA_LB_TX_SHIFT 1 5437255736Sdavidch#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */ 5438255736Sdavidch#define E2_INTEG_DATA_COS_TX_SHIFT 2 5439255736Sdavidch#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */ 5440255736Sdavidch#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 5441255736Sdavidch#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */ 5442255736Sdavidch#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 5443255736Sdavidch#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */ 5444255736Sdavidch#define E2_INTEG_DATA_RESERVED_SHIFT 5 5445255736Sdavidch#endif 5446255736Sdavidch#if defined(__BIG_ENDIAN) 5447255736Sdavidch uint16_t reserved3; 5448255736Sdavidch uint8_t reserved2; 5449255736Sdavidch uint8_t ramEn /* context area reserved for reading enable bit from ram */; 5450255736Sdavidch#elif defined(__LITTLE_ENDIAN) 5451255736Sdavidch uint8_t ramEn /* context area reserved for reading enable bit from ram */; 5452255736Sdavidch uint8_t reserved2; 5453255736Sdavidch uint16_t reserved3; 5454255736Sdavidch#endif 5455255736Sdavidch}; 5456255736Sdavidch 5457255736Sdavidch 5458255736Sdavidch/* 5459255736Sdavidch * set mac event data $$KEEP_ENDIANNESS$$ 5460255736Sdavidch */ 5461255736Sdavidchstruct eth_event_data 5462255736Sdavidch{ 5463255736Sdavidch uint32_t echo /* set mac echo data to return to driver */; 5464255736Sdavidch uint32_t reserved0; 5465255736Sdavidch uint32_t reserved1; 5466255736Sdavidch}; 5467255736Sdavidch 5468255736Sdavidch 5469255736Sdavidch/* 5470255736Sdavidch * pf-vf event data $$KEEP_ENDIANNESS$$ 5471255736Sdavidch */ 5472255736Sdavidchstruct vf_pf_event_data 5473255736Sdavidch{ 5474255736Sdavidch uint8_t vf_id /* VF ID (0-63) */; 5475255736Sdavidch uint8_t reserved0; 5476255736Sdavidch uint16_t reserved1; 5477255736Sdavidch uint32_t msg_addr_lo /* message address on Vf (low 32 bits) */; 5478255736Sdavidch uint32_t msg_addr_hi /* message address on Vf (high 32 bits) */; 5479255736Sdavidch}; 5480255736Sdavidch 5481255736Sdavidch/* 5482255736Sdavidch * VF FLR event data $$KEEP_ENDIANNESS$$ 5483255736Sdavidch */ 5484255736Sdavidchstruct vf_flr_event_data 5485255736Sdavidch{ 5486255736Sdavidch uint8_t vf_id /* VF ID (0-63) */; 5487255736Sdavidch uint8_t reserved0; 5488255736Sdavidch uint16_t reserved1; 5489255736Sdavidch uint32_t reserved2; 5490255736Sdavidch uint32_t reserved3; 5491255736Sdavidch}; 5492255736Sdavidch 5493255736Sdavidch/* 5494255736Sdavidch * malicious VF event data $$KEEP_ENDIANNESS$$ 5495255736Sdavidch */ 5496255736Sdavidchstruct malicious_vf_event_data 5497255736Sdavidch{ 5498255736Sdavidch uint8_t vf_id /* VF ID (0-63) */; 5499255736Sdavidch uint8_t err_id /* reason for malicious notification */; 5500255736Sdavidch uint16_t reserved1; 5501255736Sdavidch uint32_t reserved2; 5502255736Sdavidch uint32_t reserved3; 5503255736Sdavidch}; 5504255736Sdavidch 5505255736Sdavidch/* 5506255736Sdavidch * vif list event data $$KEEP_ENDIANNESS$$ 5507255736Sdavidch */ 5508255736Sdavidchstruct vif_list_event_data 5509255736Sdavidch{ 5510255736Sdavidch uint8_t func_bit_map /* bit map of pf indice */; 5511255736Sdavidch uint8_t echo; 5512255736Sdavidch uint16_t reserved0; 5513255736Sdavidch uint32_t reserved1; 5514255736Sdavidch uint32_t reserved2; 5515255736Sdavidch}; 5516255736Sdavidch 5517255736Sdavidch/* 5518255736Sdavidch * function update event data $$KEEP_ENDIANNESS$$ 5519255736Sdavidch */ 5520255736Sdavidchstruct function_update_event_data 5521255736Sdavidch{ 5522255736Sdavidch uint8_t echo; 5523255736Sdavidch uint8_t reserved; 5524255736Sdavidch uint16_t reserved0; 5525255736Sdavidch uint32_t reserved1; 5526255736Sdavidch uint32_t reserved2; 5527255736Sdavidch}; 5528255736Sdavidch 5529255736Sdavidch/* 5530255736Sdavidch * union for all event ring message types 5531255736Sdavidch */ 5532255736Sdavidchunion event_data 5533255736Sdavidch{ 5534255736Sdavidch struct vf_pf_event_data vf_pf_event /* vf-pf event data */; 5535255736Sdavidch struct eth_event_data eth_event /* set mac event data */; 5536255736Sdavidch struct cfc_del_event_data cfc_del_event /* cfc delete event data */; 5537255736Sdavidch struct vf_flr_event_data vf_flr_event /* vf flr event data */; 5538255736Sdavidch struct malicious_vf_event_data malicious_vf_event /* malicious vf event data */; 5539255736Sdavidch struct vif_list_event_data vif_list_event /* vif list event data */; 5540255736Sdavidch struct function_update_event_data function_update_event /* function update event data */; 5541255736Sdavidch}; 5542255736Sdavidch 5543255736Sdavidch 5544255736Sdavidch/* 5545255736Sdavidch * per PF event ring data 5546255736Sdavidch */ 5547255736Sdavidchstruct event_ring_data 5548255736Sdavidch{ 5549255736Sdavidch struct regpair_native base_addr /* ring base address */; 5550255736Sdavidch#if defined(__BIG_ENDIAN) 5551255736Sdavidch uint8_t index_id /* index ID within the status block */; 5552255736Sdavidch uint8_t sb_id /* status block ID */; 5553255736Sdavidch uint16_t producer /* event ring producer */; 5554255736Sdavidch#elif defined(__LITTLE_ENDIAN) 5555255736Sdavidch uint16_t producer /* event ring producer */; 5556255736Sdavidch uint8_t sb_id /* status block ID */; 5557255736Sdavidch uint8_t index_id /* index ID within the status block */; 5558255736Sdavidch#endif 5559255736Sdavidch uint32_t reserved0; 5560255736Sdavidch}; 5561255736Sdavidch 5562255736Sdavidch 5563255736Sdavidch/* 5564255736Sdavidch * event ring message element (each element is 128 bits) $$KEEP_ENDIANNESS$$ 5565255736Sdavidch */ 5566255736Sdavidchstruct event_ring_msg 5567255736Sdavidch{ 5568255736Sdavidch uint8_t opcode; 5569255736Sdavidch uint8_t error /* error on the mesasage */; 5570255736Sdavidch uint16_t reserved1; 5571255736Sdavidch union event_data data /* message data (96 bits data) */; 5572255736Sdavidch}; 5573255736Sdavidch 5574255736Sdavidch/* 5575255736Sdavidch * event ring next page element (128 bits) 5576255736Sdavidch */ 5577255736Sdavidchstruct event_ring_next 5578255736Sdavidch{ 5579255736Sdavidch struct regpair addr /* Address of the next page of the ring */; 5580255736Sdavidch uint32_t reserved[2]; 5581255736Sdavidch}; 5582255736Sdavidch 5583255736Sdavidch/* 5584255736Sdavidch * union for event ring element types (each element is 128 bits) 5585255736Sdavidch */ 5586255736Sdavidchunion event_ring_elem 5587255736Sdavidch{ 5588255736Sdavidch struct event_ring_msg message /* event ring message */; 5589255736Sdavidch struct event_ring_next next_page /* event ring next page */; 5590255736Sdavidch}; 5591255736Sdavidch 5592255736Sdavidch 5593255736Sdavidch/* 5594255736Sdavidch * Common event ring opcodes 5595255736Sdavidch */ 5596255736Sdavidchenum event_ring_opcode 5597255736Sdavidch{ 5598255736Sdavidch EVENT_RING_OPCODE_VF_PF_CHANNEL, 5599255736Sdavidch EVENT_RING_OPCODE_FUNCTION_START /* Start a function (for PFs only) */, 5600255736Sdavidch EVENT_RING_OPCODE_FUNCTION_STOP /* Stop a function (for PFs only) */, 5601255736Sdavidch EVENT_RING_OPCODE_CFC_DEL /* Delete a connection from CFC */, 5602255736Sdavidch EVENT_RING_OPCODE_CFC_DEL_WB /* Delete a connection from CFC (with write back) */, 5603255736Sdavidch EVENT_RING_OPCODE_STAT_QUERY /* Collect statistics counters */, 5604255736Sdavidch EVENT_RING_OPCODE_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */, 5605255736Sdavidch EVENT_RING_OPCODE_START_TRAFFIC /* Start Tx traffic (after DCB updates) */, 5606255736Sdavidch EVENT_RING_OPCODE_VF_FLR /* VF FLR indication for PF */, 5607255736Sdavidch EVENT_RING_OPCODE_MALICIOUS_VF /* Malicious VF operation detected */, 5608255736Sdavidch EVENT_RING_OPCODE_FORWARD_SETUP /* Initialize forward channel */, 5609255736Sdavidch EVENT_RING_OPCODE_RSS_UPDATE_RULES /* Update RSS configuration */, 5610255736Sdavidch EVENT_RING_OPCODE_FUNCTION_UPDATE /* function update */, 5611255736Sdavidch EVENT_RING_OPCODE_AFEX_VIF_LISTS /* event ring opcode niv vif lists */, 5612255736Sdavidch EVENT_RING_OPCODE_SET_MAC /* Add/remove MAC (in E1x only) */, 5613255736Sdavidch EVENT_RING_OPCODE_CLASSIFICATION_RULES /* Add/remove MAC or VLAN (in E2/E3 only) */, 5614255736Sdavidch EVENT_RING_OPCODE_FILTERS_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, 5615255736Sdavidch EVENT_RING_OPCODE_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */, 5616255736Sdavidch EVENT_RING_OPCODE_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */, 5617255736Sdavidch MAX_EVENT_RING_OPCODE}; 5618255736Sdavidch 5619255736Sdavidch 5620255736Sdavidch/* 5621255736Sdavidch * Modes for fairness algorithm 5622255736Sdavidch */ 5623255736Sdavidchenum fairness_mode 5624255736Sdavidch{ 5625255736Sdavidch FAIRNESS_COS_WRR_MODE /* Weighted round robin mode (used in Google) */, 5626255736Sdavidch FAIRNESS_COS_ETS_MODE /* ETS mode (used in FCoE) */, 5627255736Sdavidch MAX_FAIRNESS_MODE}; 5628255736Sdavidch 5629255736Sdavidch 5630255736Sdavidch/* 5631255736Sdavidch * Priority and cos $$KEEP_ENDIANNESS$$ 5632255736Sdavidch */ 5633255736Sdavidchstruct priority_cos 5634255736Sdavidch{ 5635255736Sdavidch uint8_t priority /* Priority */; 5636255736Sdavidch uint8_t cos /* Cos */; 5637255736Sdavidch uint16_t reserved1; 5638255736Sdavidch}; 5639255736Sdavidch 5640255736Sdavidch/* 5641255736Sdavidch * The data for flow control configuration $$KEEP_ENDIANNESS$$ 5642255736Sdavidch */ 5643255736Sdavidchstruct flow_control_configuration 5644255736Sdavidch{ 5645255736Sdavidch struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES] /* traffic_type to priority cos */; 5646255736Sdavidch uint8_t dcb_enabled /* If DCB mode is enabled then traffic class to priority array is fully initialized and there must be inner VLAN */; 5647255736Sdavidch uint8_t dcb_version /* DCB version Increase by one on each DCB update */; 5648255736Sdavidch uint8_t dont_add_pri_0 /* In case, the priority is 0, and the packet has no vlan, the firmware wont add vlan */; 5649255736Sdavidch uint8_t reserved1; 5650255736Sdavidch uint32_t reserved2; 5651255736Sdavidch}; 5652255736Sdavidch 5653255736Sdavidch 5654255736Sdavidch/* 5655255736Sdavidch * $$KEEP_ENDIANNESS$$ 5656255736Sdavidch */ 5657255736Sdavidchstruct function_start_data 5658255736Sdavidch{ 5659255736Sdavidch uint8_t function_mode /* the function mode */; 5660255736Sdavidch uint8_t allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independant function mode. (E2/E3 Only) */; 5661255736Sdavidch uint16_t sd_vlan_tag /* value of Vlan in case of switch depended multi-function mode */; 5662255736Sdavidch uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */; 5663255736Sdavidch uint8_t path_id; 5664255736Sdavidch uint8_t network_cos_mode /* The cos mode for network traffic. */; 5665255736Sdavidch uint8_t dmae_cmd_id /* The DMAE command id to use for FW DMAE transactions */; 5666255736Sdavidch uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */; 5667255736Sdavidch uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */; 5668255736Sdavidch uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */; 5669255736Sdavidch uint16_t reserved1[2]; 5670255736Sdavidch}; 5671255736Sdavidch 5672255736Sdavidch 5673255736Sdavidch/* 5674255736Sdavidch * $$KEEP_ENDIANNESS$$ 5675255736Sdavidch */ 5676255736Sdavidchstruct function_update_data 5677255736Sdavidch{ 5678255736Sdavidch uint8_t vif_id_change_flg /* If set, vif_id will be checked */; 5679255736Sdavidch uint8_t afex_default_vlan_change_flg /* If set, afex_default_vlan will be checked */; 5680255736Sdavidch uint8_t allowed_priorities_change_flg /* If set, allowed_priorities will be checked */; 5681255736Sdavidch uint8_t network_cos_mode_change_flg /* If set, network_cos_mode will be checked */; 5682255736Sdavidch uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */; 5683255736Sdavidch uint16_t afex_default_vlan /* value of default Vlan in case of NIV mf */; 5684255736Sdavidch uint8_t allowed_priorities /* bit vector of allowed Vlan priorities for this VIF */; 5685255736Sdavidch uint8_t network_cos_mode /* The cos mode for network traffic. */; 5686255736Sdavidch uint8_t lb_mode_en_change_flg /* If set, lb_mode_en will be checked */; 5687255736Sdavidch uint8_t lb_mode_en /* If set, niv loopback mode will be enabled */; 5688255736Sdavidch uint8_t tx_switch_suspend_change_flg /* If set, tx_switch_suspend will be checked */; 5689255736Sdavidch uint8_t tx_switch_suspend /* If set, TX switching TO this function will be disabled and packets will be dropped */; 5690255736Sdavidch uint8_t echo; 5691255736Sdavidch uint8_t reserved1; 5692255736Sdavidch uint8_t update_gre_cfg_flg /* If set, GRE config for the function will be updated according to the gre_tunnel_rss and nvgre_clss_en fields */; 5693255736Sdavidch uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */; 5694255736Sdavidch uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */; 5695255736Sdavidch uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */; 5696255736Sdavidch uint32_t reserved3; 5697255736Sdavidch}; 5698255736Sdavidch 5699255736Sdavidch 5700255736Sdavidch/* 5701255736Sdavidch * FW version stored in the Xstorm RAM 5702255736Sdavidch */ 5703255736Sdavidchstruct fw_version 5704255736Sdavidch{ 5705255736Sdavidch#if defined(__BIG_ENDIAN) 5706255736Sdavidch uint8_t engineering /* firmware current engineering version */; 5707255736Sdavidch uint8_t revision /* firmware current revision version */; 5708255736Sdavidch uint8_t minor /* firmware current minor version */; 5709255736Sdavidch uint8_t major /* firmware current major version */; 5710255736Sdavidch#elif defined(__LITTLE_ENDIAN) 5711255736Sdavidch uint8_t major /* firmware current major version */; 5712255736Sdavidch uint8_t minor /* firmware current minor version */; 5713255736Sdavidch uint8_t revision /* firmware current revision version */; 5714255736Sdavidch uint8_t engineering /* firmware current engineering version */; 5715255736Sdavidch#endif 5716255736Sdavidch uint32_t flags; 5717255736Sdavidch#define FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */ 5718255736Sdavidch#define FW_VERSION_OPTIMIZED_SHIFT 0 5719255736Sdavidch#define FW_VERSION_BIG_ENDIEN (0x1<<1) /* BitField flags if set, this is big-endien ASM */ 5720255736Sdavidch#define FW_VERSION_BIG_ENDIEN_SHIFT 1 5721255736Sdavidch#define FW_VERSION_CHIP_VERSION (0x3<<2) /* BitField flags 0 - E1, 1 - E1H */ 5722255736Sdavidch#define FW_VERSION_CHIP_VERSION_SHIFT 2 5723255736Sdavidch#define __FW_VERSION_RESERVED (0xFFFFFFF<<4) /* BitField flags */ 5724255736Sdavidch#define __FW_VERSION_RESERVED_SHIFT 4 5725255736Sdavidch}; 5726255736Sdavidch 5727255736Sdavidch 5728255736Sdavidch/* 5729255736Sdavidch * GRE RSS Mode 5730255736Sdavidch */ 5731255736Sdavidchenum gre_rss_mode 5732255736Sdavidch{ 5733255736Sdavidch GRE_OUTER_HEADERS_RSS /* RSS for GRE Packets is performed on the outer headers */, 5734255736Sdavidch GRE_INNER_HEADERS_RSS /* RSS for GRE Packets is performed on the inner headers */, 5735255736Sdavidch NVGRE_KEY_ENTROPY_RSS /* RSS for NVGRE Packets is done based on a hash containing the entropy bits from the GRE Key Field (gre_tunnel must be NVGRE_TUNNEL) */, 5736255736Sdavidch MAX_GRE_RSS_MODE}; 5737255736Sdavidch 5738255736Sdavidch 5739255736Sdavidch/* 5740255736Sdavidch * GRE Tunnel Mode 5741255736Sdavidch */ 5742255736Sdavidchenum gre_tunnel_type 5743255736Sdavidch{ 5744255736Sdavidch NO_GRE_TUNNEL, 5745255736Sdavidch NVGRE_TUNNEL /* NV-GRE Tunneling Microsoft L2 over GRE. GRE header contains mandatory Key Field. */, 5746255736Sdavidch L2GRE_TUNNEL /* L2-GRE Tunneling General L2 over GRE. GRE can contain Key field with Tenant ID and Sequence Field */, 5747255736Sdavidch IPGRE_TUNNEL /* IP-GRE Tunneling IP over GRE. GRE may contain Key field with Tenant ID, Sequence Field and/or Checksum Field */, 5748255736Sdavidch MAX_GRE_TUNNEL_TYPE}; 5749255736Sdavidch 5750255736Sdavidch 5751255736Sdavidch/* 5752255736Sdavidch * Dynamic Host-Coalescing - Driver(host) counters 5753255736Sdavidch */ 5754255736Sdavidchstruct hc_dynamic_sb_drv_counters 5755255736Sdavidch{ 5756255736Sdavidch uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES] /* Dynamic HC counters written by drivers */; 5757255736Sdavidch}; 5758255736Sdavidch 5759255736Sdavidch 5760255736Sdavidch/* 5761255736Sdavidch * 2 bytes. configuration/state parameters for a single protocol index 5762255736Sdavidch */ 5763255736Sdavidchstruct hc_index_data 5764255736Sdavidch{ 5765255736Sdavidch#if defined(__BIG_ENDIAN) 5766255736Sdavidch uint8_t flags; 5767255736Sdavidch#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */ 5768255736Sdavidch#define HC_INDEX_DATA_SM_ID_SHIFT 0 5769255736Sdavidch#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */ 5770255736Sdavidch#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5771255736Sdavidch#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */ 5772255736Sdavidch#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5773255736Sdavidch#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */ 5774255736Sdavidch#define HC_INDEX_DATA_RESERVE_SHIFT 3 5775255736Sdavidch uint8_t timeout /* the timeout values for this index. Units are 4 usec */; 5776255736Sdavidch#elif defined(__LITTLE_ENDIAN) 5777255736Sdavidch uint8_t timeout /* the timeout values for this index. Units are 4 usec */; 5778255736Sdavidch uint8_t flags; 5779255736Sdavidch#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */ 5780255736Sdavidch#define HC_INDEX_DATA_SM_ID_SHIFT 0 5781255736Sdavidch#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */ 5782255736Sdavidch#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5783255736Sdavidch#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */ 5784255736Sdavidch#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5785255736Sdavidch#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */ 5786255736Sdavidch#define HC_INDEX_DATA_RESERVE_SHIFT 3 5787255736Sdavidch#endif 5788255736Sdavidch}; 5789255736Sdavidch 5790255736Sdavidch 5791255736Sdavidch/* 5792255736Sdavidch * HC state-machine 5793255736Sdavidch */ 5794255736Sdavidchstruct hc_status_block_sm 5795255736Sdavidch{ 5796255736Sdavidch#if defined(__BIG_ENDIAN) 5797255736Sdavidch uint8_t igu_seg_id; 5798255736Sdavidch uint8_t igu_sb_id /* sb_id within the IGU */; 5799255736Sdavidch uint8_t timer_value /* Determines the time_to_expire */; 5800255736Sdavidch uint8_t __flags; 5801255736Sdavidch#elif defined(__LITTLE_ENDIAN) 5802255736Sdavidch uint8_t __flags; 5803255736Sdavidch uint8_t timer_value /* Determines the time_to_expire */; 5804255736Sdavidch uint8_t igu_sb_id /* sb_id within the IGU */; 5805255736Sdavidch uint8_t igu_seg_id; 5806255736Sdavidch#endif 5807255736Sdavidch uint32_t time_to_expire /* The time in which it expects to wake up */; 5808255736Sdavidch}; 5809255736Sdavidch 5810255736Sdavidch/* 5811255736Sdavidch * hold PCI identification variables- used in various places in firmware 5812255736Sdavidch */ 5813255736Sdavidchstruct pci_entity 5814255736Sdavidch{ 5815255736Sdavidch#if defined(__BIG_ENDIAN) 5816255736Sdavidch uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */; 5817255736Sdavidch uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */; 5818255736Sdavidch uint8_t vnic_id /* Virtual NIC ID (0-3) */; 5819255736Sdavidch uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */; 5820255736Sdavidch#elif defined(__LITTLE_ENDIAN) 5821255736Sdavidch uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */; 5822255736Sdavidch uint8_t vnic_id /* Virtual NIC ID (0-3) */; 5823255736Sdavidch uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */; 5824255736Sdavidch uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */; 5825255736Sdavidch#endif 5826255736Sdavidch}; 5827255736Sdavidch 5828255736Sdavidch/* 5829255736Sdavidch * The fast-path status block meta-data, common to all chips 5830255736Sdavidch */ 5831255736Sdavidchstruct hc_sb_data 5832255736Sdavidch{ 5833255736Sdavidch struct regpair_native host_sb_addr /* Host status block address */; 5834255736Sdavidch struct hc_status_block_sm state_machine[HC_SB_MAX_SM] /* Holds the state machines of the status block */; 5835255736Sdavidch struct pci_entity p_func /* vnic / port of the status block to be set by the driver */; 5836255736Sdavidch#if defined(__BIG_ENDIAN) 5837255736Sdavidch uint8_t rsrv0; 5838255736Sdavidch uint8_t state; 5839255736Sdavidch uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */; 5840255736Sdavidch uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */; 5841255736Sdavidch#elif defined(__LITTLE_ENDIAN) 5842255736Sdavidch uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */; 5843255736Sdavidch uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */; 5844255736Sdavidch uint8_t state; 5845255736Sdavidch uint8_t rsrv0; 5846255736Sdavidch#endif 5847255736Sdavidch struct regpair_native rsrv1[2]; 5848255736Sdavidch}; 5849255736Sdavidch 5850255736Sdavidch 5851255736Sdavidch/* 5852255736Sdavidch * Segment types for host coaslescing 5853255736Sdavidch */ 5854255736Sdavidchenum hc_segment 5855255736Sdavidch{ 5856255736Sdavidch HC_REGULAR_SEGMENT, 5857255736Sdavidch HC_DEFAULT_SEGMENT, 5858255736Sdavidch MAX_HC_SEGMENT}; 5859255736Sdavidch 5860255736Sdavidch 5861255736Sdavidch/* 5862255736Sdavidch * The fast-path status block meta-data 5863255736Sdavidch */ 5864255736Sdavidchstruct hc_sp_status_block_data 5865255736Sdavidch{ 5866255736Sdavidch struct regpair_native host_sb_addr /* Host status block address */; 5867255736Sdavidch#if defined(__BIG_ENDIAN) 5868255736Sdavidch uint8_t rsrv1; 5869255736Sdavidch uint8_t state; 5870255736Sdavidch uint8_t igu_seg_id /* segment id of the IGU */; 5871255736Sdavidch uint8_t igu_sb_id /* sb_id within the IGU */; 5872255736Sdavidch#elif defined(__LITTLE_ENDIAN) 5873255736Sdavidch uint8_t igu_sb_id /* sb_id within the IGU */; 5874255736Sdavidch uint8_t igu_seg_id /* segment id of the IGU */; 5875255736Sdavidch uint8_t state; 5876255736Sdavidch uint8_t rsrv1; 5877255736Sdavidch#endif 5878255736Sdavidch struct pci_entity p_func /* vnic / port of the status block to be set by the driver */; 5879255736Sdavidch}; 5880255736Sdavidch 5881255736Sdavidch 5882255736Sdavidch/* 5883255736Sdavidch * The fast-path status block meta-data 5884255736Sdavidch */ 5885255736Sdavidchstruct hc_status_block_data_e1x 5886255736Sdavidch{ 5887255736Sdavidch struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X] /* configuration/state parameters for a single protocol index */; 5888255736Sdavidch struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */; 5889255736Sdavidch}; 5890255736Sdavidch 5891255736Sdavidch 5892255736Sdavidch/* 5893255736Sdavidch * The fast-path status block meta-data 5894255736Sdavidch */ 5895255736Sdavidchstruct hc_status_block_data_e2 5896255736Sdavidch{ 5897255736Sdavidch struct hc_index_data index_data[HC_SB_MAX_INDICES_E2] /* configuration/state parameters for a single protocol index */; 5898255736Sdavidch struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */; 5899255736Sdavidch}; 5900255736Sdavidch 5901255736Sdavidch 5902255736Sdavidch/* 5903255736Sdavidch * IGU block operartion modes (in Everest2) 5904255736Sdavidch */ 5905255736Sdavidchenum igu_mode 5906255736Sdavidch{ 5907255736Sdavidch HC_IGU_BC_MODE /* Backward compatible mode */, 5908255736Sdavidch HC_IGU_NBC_MODE /* Non-backward compatible mode */, 5909255736Sdavidch MAX_IGU_MODE}; 5910255736Sdavidch 5911255736Sdavidch 5912255736Sdavidch/* 5913255736Sdavidch * IP versions 5914255736Sdavidch */ 5915255736Sdavidchenum ip_ver 5916255736Sdavidch{ 5917255736Sdavidch IP_V4, 5918255736Sdavidch IP_V6, 5919255736Sdavidch MAX_IP_VER}; 5920255736Sdavidch 5921255736Sdavidch 5922255736Sdavidch/* 5923255736Sdavidch * Malicious VF error ID 5924255736Sdavidch */ 5925255736Sdavidchenum malicious_vf_error_id 5926255736Sdavidch{ 5927255736Sdavidch VF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */, 5928255736Sdavidch ETH_ILLEGAL_BD_LENGTHS /* TX BD lengths error was detected */, 5929255736Sdavidch ETH_PACKET_TOO_SHORT /* TX packet is shorter then reported on BDs */, 5930255736Sdavidch ETH_PAYLOAD_TOO_BIG /* TX packet is greater then MTU */, 5931255736Sdavidch ETH_ILLEGAL_ETH_TYPE /* TX packet reported without VLAN but eth type is 0x8100 */, 5932255736Sdavidch ETH_ILLEGAL_LSO_HDR_LEN /* LSO header length on BDs and on hdr_nbd do not match */, 5933255736Sdavidch ETH_TOO_MANY_BDS /* Tx packet has too many BDs */, 5934255736Sdavidch ETH_ZERO_HDR_NBDS /* hdr_nbds field is zero */, 5935255736Sdavidch ETH_START_BD_NOT_SET /* start_bd should be set on first TX BD in packet */, 5936255736Sdavidch ETH_ILLEGAL_PARSE_NBDS /* Tx packet with parse_nbds field which is not legal */, 5937255736Sdavidch ETH_IPV6_AND_CHECKSUM /* Tx packet with IP checksum on IPv6 */, 5938255736Sdavidch ETH_VLAN_FLG_INCORRECT /* Tx packet with incorrect VLAN flag */, 5939255736Sdavidch ETH_ILLEGAL_LSO_MSS /* Tx LSO packet with illegal MSS value */, 5940255736Sdavidch ETH_TUNNEL_NOT_SUPPORTED /* Tunneling packets are not supported in current connection */, 5941255736Sdavidch MAX_MALICIOUS_VF_ERROR_ID}; 5942255736Sdavidch 5943255736Sdavidch 5944255736Sdavidch/* 5945255736Sdavidch * Multi-function modes 5946255736Sdavidch */ 5947255736Sdavidchenum mf_mode 5948255736Sdavidch{ 5949255736Sdavidch SINGLE_FUNCTION, 5950255736Sdavidch MULTI_FUNCTION_SD /* Switch dependent (vlan based) */, 5951255736Sdavidch MULTI_FUNCTION_SI /* Switch independent (mac based) */, 5952255736Sdavidch MULTI_FUNCTION_AFEX /* Switch dependent (niv based) */, 5953255736Sdavidch MAX_MF_MODE}; 5954255736Sdavidch 5955255736Sdavidch 5956255736Sdavidch/* 5957255736Sdavidch * Protocol-common statistics collected by the Tstorm (per pf) $$KEEP_ENDIANNESS$$ 5958255736Sdavidch */ 5959255736Sdavidchstruct tstorm_per_pf_stats 5960255736Sdavidch{ 5961255736Sdavidch struct regpair rcv_error_bytes /* number of bytes received with errors */; 5962255736Sdavidch}; 5963255736Sdavidch 5964255736Sdavidch/* 5965255736Sdavidch * $$KEEP_ENDIANNESS$$ 5966255736Sdavidch */ 5967255736Sdavidchstruct per_pf_stats 5968255736Sdavidch{ 5969255736Sdavidch struct tstorm_per_pf_stats tstorm_pf_statistics; 5970255736Sdavidch}; 5971255736Sdavidch 5972255736Sdavidch 5973255736Sdavidch/* 5974255736Sdavidch * Protocol-common statistics collected by the Tstorm (per port) $$KEEP_ENDIANNESS$$ 5975255736Sdavidch */ 5976255736Sdavidchstruct tstorm_per_port_stats 5977255736Sdavidch{ 5978255736Sdavidch uint32_t mac_discard /* number of packets with mac errors */; 5979255736Sdavidch uint32_t mac_filter_discard /* the number of good frames dropped because of no perfect match to MAC/VLAN address */; 5980255736Sdavidch uint32_t brb_truncate_discard /* the number of packtes that were dropped because they were truncated in BRB */; 5981255736Sdavidch uint32_t mf_tag_discard /* the number of good frames dropped because of no match to the outer vlan/VNtag */; 5982255736Sdavidch uint32_t packet_drop /* general packet drop conter- incremented for every packet drop */; 5983255736Sdavidch uint32_t reserved; 5984255736Sdavidch}; 5985255736Sdavidch 5986255736Sdavidch/* 5987255736Sdavidch * $$KEEP_ENDIANNESS$$ 5988255736Sdavidch */ 5989255736Sdavidchstruct per_port_stats 5990255736Sdavidch{ 5991255736Sdavidch struct tstorm_per_port_stats tstorm_port_statistics; 5992255736Sdavidch}; 5993255736Sdavidch 5994255736Sdavidch 5995255736Sdavidch/* 5996255736Sdavidch * Protocol-common statistics collected by the Tstorm (per client) $$KEEP_ENDIANNESS$$ 5997255736Sdavidch */ 5998255736Sdavidchstruct tstorm_per_queue_stats 5999255736Sdavidch{ 6000255736Sdavidch struct regpair rcv_ucast_bytes /* number of bytes in unicast packets received without errors and pass the filter */; 6001255736Sdavidch uint32_t rcv_ucast_pkts /* number of unicast packets received without errors and pass the filter */; 6002255736Sdavidch uint32_t checksum_discard /* number of total packets received with checksum error */; 6003255736Sdavidch struct regpair rcv_bcast_bytes /* number of bytes in broadcast packets received without errors and pass the filter */; 6004255736Sdavidch uint32_t rcv_bcast_pkts /* number of packets in broadcast packets received without errors and pass the filter */; 6005255736Sdavidch uint32_t pkts_too_big_discard /* number of too long packets received */; 6006255736Sdavidch struct regpair rcv_mcast_bytes /* number of bytes in multicast packets received without errors and pass the filter */; 6007255736Sdavidch uint32_t rcv_mcast_pkts /* number of packets in multicast packets received without errors and pass the filter */; 6008255736Sdavidch uint32_t ttl0_discard /* the number of good frames dropped because of TTL=0 */; 6009255736Sdavidch uint16_t no_buff_discard; 6010255736Sdavidch uint16_t reserved0; 6011255736Sdavidch uint32_t reserved1; 6012255736Sdavidch}; 6013255736Sdavidch 6014255736Sdavidch/* 6015255736Sdavidch * Protocol-common statistics collected by the Ustorm (per client) $$KEEP_ENDIANNESS$$ 6016255736Sdavidch */ 6017255736Sdavidchstruct ustorm_per_queue_stats 6018255736Sdavidch{ 6019255736Sdavidch struct regpair ucast_no_buff_bytes /* the number of unicast bytes received from network dropped because of no buffer at host */; 6020255736Sdavidch struct regpair mcast_no_buff_bytes /* the number of multicast bytes received from network dropped because of no buffer at host */; 6021255736Sdavidch struct regpair bcast_no_buff_bytes /* the number of broadcast bytes received from network dropped because of no buffer at host */; 6022255736Sdavidch uint32_t ucast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; 6023255736Sdavidch uint32_t mcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; 6024255736Sdavidch uint32_t bcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; 6025255736Sdavidch uint32_t coalesced_pkts /* the number of packets coalesced in all aggregations */; 6026255736Sdavidch struct regpair coalesced_bytes /* the number of bytes coalesced in all aggregations */; 6027255736Sdavidch uint32_t coalesced_events /* the number of aggregations */; 6028255736Sdavidch uint32_t coalesced_aborts /* the number of exception which avoid aggregation */; 6029255736Sdavidch}; 6030255736Sdavidch 6031255736Sdavidch/* 6032255736Sdavidch * Protocol-common statistics collected by the Xstorm (per client) $$KEEP_ENDIANNESS$$ 6033255736Sdavidch */ 6034255736Sdavidchstruct xstorm_per_queue_stats 6035255736Sdavidch{ 6036255736Sdavidch struct regpair ucast_bytes_sent /* number of total bytes sent without errors */; 6037255736Sdavidch struct regpair mcast_bytes_sent /* number of total bytes sent without errors */; 6038255736Sdavidch struct regpair bcast_bytes_sent /* number of total bytes sent without errors */; 6039255736Sdavidch uint32_t ucast_pkts_sent /* number of total packets sent without errors */; 6040255736Sdavidch uint32_t mcast_pkts_sent /* number of total packets sent without errors */; 6041255736Sdavidch uint32_t bcast_pkts_sent /* number of total packets sent without errors */; 6042255736Sdavidch uint32_t error_drop_pkts /* number of total packets drooped due to errors */; 6043255736Sdavidch}; 6044255736Sdavidch 6045255736Sdavidch/* 6046255736Sdavidch * $$KEEP_ENDIANNESS$$ 6047255736Sdavidch */ 6048255736Sdavidchstruct per_queue_stats 6049255736Sdavidch{ 6050255736Sdavidch struct tstorm_per_queue_stats tstorm_queue_statistics; 6051255736Sdavidch struct ustorm_per_queue_stats ustorm_queue_statistics; 6052255736Sdavidch struct xstorm_per_queue_stats xstorm_queue_statistics; 6053255736Sdavidch}; 6054255736Sdavidch 6055255736Sdavidch 6056255736Sdavidch/* 6057255736Sdavidch * FW version stored in first line of pram $$KEEP_ENDIANNESS$$ 6058255736Sdavidch */ 6059255736Sdavidchstruct pram_fw_version 6060255736Sdavidch{ 6061255736Sdavidch uint8_t major /* firmware current major version */; 6062255736Sdavidch uint8_t minor /* firmware current minor version */; 6063255736Sdavidch uint8_t revision /* firmware current revision version */; 6064255736Sdavidch uint8_t engineering /* firmware current engineering version */; 6065255736Sdavidch uint8_t flags; 6066255736Sdavidch#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */ 6067255736Sdavidch#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 6068255736Sdavidch#define PRAM_FW_VERSION_STORM_ID (0x3<<1) /* BitField flags storm_id identification */ 6069255736Sdavidch#define PRAM_FW_VERSION_STORM_ID_SHIFT 1 6070255736Sdavidch#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* BitField flags if set, this is big-endien ASM */ 6071255736Sdavidch#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 6072255736Sdavidch#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) /* BitField flags 0 - E1, 1 - E1H */ 6073255736Sdavidch#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 6074255736Sdavidch#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* BitField flags */ 6075255736Sdavidch#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 6076255736Sdavidch}; 6077255736Sdavidch 6078255736Sdavidch 6079255736Sdavidch/* 6080255736Sdavidch * Ethernet slow path element 6081255736Sdavidch */ 6082255736Sdavidchunion protocol_common_specific_data 6083255736Sdavidch{ 6084255736Sdavidch uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */; 6085255736Sdavidch struct regpair phy_address /* SPE physical address */; 6086255736Sdavidch struct regpair mac_config_addr /* physical address of the MAC configuration command, as allocated by the driver */; 6087255736Sdavidch struct afex_vif_list_ramrod_data afex_vif_list_data /* The data afex vif list ramrod need */; 6088255736Sdavidch}; 6089255736Sdavidch 6090255736Sdavidch/* 6091255736Sdavidch * The send queue element 6092255736Sdavidch */ 6093255736Sdavidchstruct protocol_common_spe 6094255736Sdavidch{ 6095255736Sdavidch struct spe_hdr hdr /* SPE header */; 6096255736Sdavidch union protocol_common_specific_data data /* data specific to common protocol */; 6097255736Sdavidch}; 6098255736Sdavidch 6099255736Sdavidch 6100255736Sdavidch/* 6101255736Sdavidch * The data for the Set Timesync Ramrod $$KEEP_ENDIANNESS$$ 6102255736Sdavidch */ 6103255736Sdavidchstruct set_timesync_ramrod_data 6104255736Sdavidch{ 6105255736Sdavidch uint8_t drift_adjust_cmd /* Timesync Drift Adjust Command */; 6106255736Sdavidch uint8_t offset_cmd /* Timesync Offset Command */; 6107255736Sdavidch uint8_t add_sub_drift_adjust_value /* Whether to add(1)/subtract(0) Drift Adjust Value from the Offset */; 6108255736Sdavidch uint8_t drift_adjust_value /* Drift Adjust Value (in ns) */; 6109255736Sdavidch uint32_t drift_adjust_period /* Drift Adjust Period (in us) */; 6110255736Sdavidch struct regpair offset_delta /* Timesync Offset Delta (in ns) */; 6111255736Sdavidch}; 6112255736Sdavidch 6113255736Sdavidch 6114255736Sdavidch/* 6115255736Sdavidch * The send queue element 6116255736Sdavidch */ 6117255736Sdavidchstruct slow_path_element 6118255736Sdavidch{ 6119255736Sdavidch struct spe_hdr hdr /* common data for all protocols */; 6120255736Sdavidch struct regpair protocol_data /* additional data specific to the protocol */; 6121255736Sdavidch}; 6122255736Sdavidch 6123255736Sdavidch 6124255736Sdavidch/* 6125255736Sdavidch * Protocol-common statistics counter $$KEEP_ENDIANNESS$$ 6126255736Sdavidch */ 6127255736Sdavidchstruct stats_counter 6128255736Sdavidch{ 6129255736Sdavidch uint16_t xstats_counter /* xstorm statistics counter */; 6130255736Sdavidch uint16_t reserved0; 6131255736Sdavidch uint32_t reserved1; 6132255736Sdavidch uint16_t tstats_counter /* tstorm statistics counter */; 6133255736Sdavidch uint16_t reserved2; 6134255736Sdavidch uint32_t reserved3; 6135255736Sdavidch uint16_t ustats_counter /* ustorm statistics counter */; 6136255736Sdavidch uint16_t reserved4; 6137255736Sdavidch uint32_t reserved5; 6138255736Sdavidch uint16_t cstats_counter /* ustorm statistics counter */; 6139255736Sdavidch uint16_t reserved6; 6140255736Sdavidch uint32_t reserved7; 6141255736Sdavidch}; 6142255736Sdavidch 6143255736Sdavidch 6144255736Sdavidch/* 6145255736Sdavidch * $$KEEP_ENDIANNESS$$ 6146255736Sdavidch */ 6147255736Sdavidchstruct stats_query_entry 6148255736Sdavidch{ 6149255736Sdavidch uint8_t kind; 6150255736Sdavidch uint8_t index /* queue index */; 6151255736Sdavidch uint16_t funcID /* the func the statistic will send to */; 6152255736Sdavidch uint32_t reserved; 6153255736Sdavidch struct regpair address /* pxp address */; 6154255736Sdavidch}; 6155255736Sdavidch 6156255736Sdavidch/* 6157255736Sdavidch * statistic command $$KEEP_ENDIANNESS$$ 6158255736Sdavidch */ 6159255736Sdavidchstruct stats_query_cmd_group 6160255736Sdavidch{ 6161255736Sdavidch struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 6162255736Sdavidch}; 6163255736Sdavidch 6164255736Sdavidch 6165255736Sdavidch/* 6166255736Sdavidch * statistic command header $$KEEP_ENDIANNESS$$ 6167255736Sdavidch */ 6168255736Sdavidchstruct stats_query_header 6169255736Sdavidch{ 6170255736Sdavidch uint8_t cmd_num /* command number */; 6171255736Sdavidch uint8_t reserved0; 6172255736Sdavidch uint16_t drv_stats_counter; 6173255736Sdavidch uint32_t reserved1; 6174255736Sdavidch struct regpair stats_counters_addrs /* stats counter */; 6175255736Sdavidch}; 6176255736Sdavidch 6177255736Sdavidch 6178255736Sdavidch/* 6179255736Sdavidch * Types of statistcis query entry 6180255736Sdavidch */ 6181255736Sdavidchenum stats_query_type 6182255736Sdavidch{ 6183255736Sdavidch STATS_TYPE_QUEUE, 6184255736Sdavidch STATS_TYPE_PORT, 6185255736Sdavidch STATS_TYPE_PF, 6186255736Sdavidch STATS_TYPE_TOE, 6187255736Sdavidch STATS_TYPE_FCOE, 6188255736Sdavidch MAX_STATS_QUERY_TYPE}; 6189255736Sdavidch 6190255736Sdavidch 6191255736Sdavidch/* 6192255736Sdavidch * Indicate of the function status block state 6193255736Sdavidch */ 6194255736Sdavidchenum status_block_state 6195255736Sdavidch{ 6196255736Sdavidch SB_DISABLED, 6197255736Sdavidch SB_ENABLED, 6198255736Sdavidch SB_CLEANED, 6199255736Sdavidch MAX_STATUS_BLOCK_STATE}; 6200255736Sdavidch 6201255736Sdavidch 6202255736Sdavidch/* 6203255736Sdavidch * Storm IDs (including attentions for IGU related enums) 6204255736Sdavidch */ 6205255736Sdavidchenum storm_id 6206255736Sdavidch{ 6207255736Sdavidch USTORM_ID, 6208255736Sdavidch CSTORM_ID, 6209255736Sdavidch XSTORM_ID, 6210255736Sdavidch TSTORM_ID, 6211255736Sdavidch ATTENTION_ID, 6212255736Sdavidch MAX_STORM_ID}; 6213255736Sdavidch 6214255736Sdavidch 6215255736Sdavidch/* 6216255736Sdavidch * Taffic types used in ETS and flow control algorithms 6217255736Sdavidch */ 6218255736Sdavidchenum traffic_type 6219255736Sdavidch{ 6220255736Sdavidch LLFC_TRAFFIC_TYPE_NW /* Networking */, 6221255736Sdavidch LLFC_TRAFFIC_TYPE_FCOE /* FCoE */, 6222255736Sdavidch LLFC_TRAFFIC_TYPE_ISCSI /* iSCSI */, 6223255736Sdavidch MAX_TRAFFIC_TYPE}; 6224255736Sdavidch 6225255736Sdavidch 6226255736Sdavidch/* 6227255736Sdavidch * zone A per-queue data 6228255736Sdavidch */ 6229255736Sdavidchstruct tstorm_queue_zone_data 6230255736Sdavidch{ 6231255736Sdavidch struct regpair reserved[4]; 6232255736Sdavidch}; 6233255736Sdavidch 6234255736Sdavidch 6235255736Sdavidch/* 6236255736Sdavidch * zone B per-VF data 6237255736Sdavidch */ 6238255736Sdavidchstruct tstorm_vf_zone_data 6239255736Sdavidch{ 6240255736Sdavidch struct regpair reserved; 6241255736Sdavidch}; 6242255736Sdavidch 6243255736Sdavidch 6244255736Sdavidch/* 6245255736Sdavidch * Add or Subtract Value for Set Timesync Ramrod 6246255736Sdavidch */ 6247255736Sdavidchenum ts_add_sub_value 6248255736Sdavidch{ 6249255736Sdavidch TS_SUB_VALUE /* Subtract Value */, 6250255736Sdavidch TS_ADD_VALUE /* Add Value */, 6251255736Sdavidch MAX_TS_ADD_SUB_VALUE}; 6252255736Sdavidch 6253255736Sdavidch 6254255736Sdavidch/* 6255255736Sdavidch * Drift-Adjust Commands for Set Timesync Ramrod 6256255736Sdavidch */ 6257255736Sdavidchenum ts_drift_adjust_cmd 6258255736Sdavidch{ 6259255736Sdavidch TS_DRIFT_ADJUST_KEEP /* Keep Drift-Adjust at current values */, 6260255736Sdavidch TS_DRIFT_ADJUST_SET /* Set Drift-Adjust */, 6261255736Sdavidch TS_DRIFT_ADJUST_RESET /* Reset Drift-Adjust */, 6262255736Sdavidch MAX_TS_DRIFT_ADJUST_CMD}; 6263255736Sdavidch 6264255736Sdavidch 6265255736Sdavidch/* 6266255736Sdavidch * Offset Commands for Set Timesync Ramrod 6267255736Sdavidch */ 6268255736Sdavidchenum ts_offset_cmd 6269255736Sdavidch{ 6270255736Sdavidch TS_OFFSET_KEEP /* Keep Offset at current values */, 6271255736Sdavidch TS_OFFSET_INC /* Increase Offset by Offset Delta */, 6272255736Sdavidch TS_OFFSET_DEC /* Decrease Offset by Offset Delta */, 6273255736Sdavidch MAX_TS_OFFSET_CMD}; 6274255736Sdavidch 6275255736Sdavidch 6276255736Sdavidch/* 6277255736Sdavidch * zone A per-queue data 6278255736Sdavidch */ 6279255736Sdavidchstruct ustorm_queue_zone_data 6280255736Sdavidch{ 6281255736Sdavidch struct ustorm_eth_rx_producers eth_rx_producers /* ETH RX rings producers */; 6282255736Sdavidch struct regpair reserved[3]; 6283255736Sdavidch}; 6284255736Sdavidch 6285255736Sdavidch 6286255736Sdavidch/* 6287255736Sdavidch * zone B per-VF data 6288255736Sdavidch */ 6289255736Sdavidchstruct ustorm_vf_zone_data 6290255736Sdavidch{ 6291255736Sdavidch struct regpair reserved; 6292255736Sdavidch}; 6293255736Sdavidch 6294255736Sdavidch 6295255736Sdavidch/* 6296255736Sdavidch * data per VF-PF channel 6297255736Sdavidch */ 6298255736Sdavidchstruct vf_pf_channel_data 6299255736Sdavidch{ 6300255736Sdavidch#if defined(__BIG_ENDIAN) 6301255736Sdavidch uint16_t reserved0; 6302255736Sdavidch uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */; 6303255736Sdavidch uint8_t state /* channel state (ready / waiting for ack) */; 6304255736Sdavidch#elif defined(__LITTLE_ENDIAN) 6305255736Sdavidch uint8_t state /* channel state (ready / waiting for ack) */; 6306255736Sdavidch uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */; 6307255736Sdavidch uint16_t reserved0; 6308255736Sdavidch#endif 6309255736Sdavidch uint32_t reserved1; 6310255736Sdavidch}; 6311255736Sdavidch 6312255736Sdavidch 6313255736Sdavidch/* 6314255736Sdavidch * State of VF-PF channel 6315255736Sdavidch */ 6316255736Sdavidchenum vf_pf_channel_state 6317255736Sdavidch{ 6318255736Sdavidch VF_PF_CHANNEL_STATE_READY /* Channel is ready to accept a message from VF */, 6319255736Sdavidch VF_PF_CHANNEL_STATE_WAITING_FOR_ACK /* Channel waits for an ACK from PF */, 6320255736Sdavidch MAX_VF_PF_CHANNEL_STATE}; 6321255736Sdavidch 6322255736Sdavidch 6323255736Sdavidch/* 6324255736Sdavidch * vif_list_rule_kind 6325255736Sdavidch */ 6326255736Sdavidchenum vif_list_rule_kind 6327255736Sdavidch{ 6328255736Sdavidch VIF_LIST_RULE_SET, 6329255736Sdavidch VIF_LIST_RULE_GET, 6330255736Sdavidch VIF_LIST_RULE_CLEAR_ALL, 6331255736Sdavidch VIF_LIST_RULE_CLEAR_FUNC, 6332255736Sdavidch MAX_VIF_LIST_RULE_KIND}; 6333255736Sdavidch 6334255736Sdavidch 6335255736Sdavidch/* 6336255736Sdavidch * zone A per-queue data 6337255736Sdavidch */ 6338255736Sdavidchstruct xstorm_queue_zone_data 6339255736Sdavidch{ 6340255736Sdavidch struct regpair reserved[4]; 6341255736Sdavidch}; 6342255736Sdavidch 6343255736Sdavidch 6344255736Sdavidch/* 6345255736Sdavidch * zone B per-VF data 6346255736Sdavidch */ 6347255736Sdavidchstruct xstorm_vf_zone_data 6348255736Sdavidch{ 6349255736Sdavidch struct regpair reserved; 6350255736Sdavidch}; 6351255736Sdavidch 6352255736Sdavidch 6353255736Sdavidch#endif /* ECORE_HSI_H */ 6354255736Sdavidch 6355