1/*- 2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#ifndef ECORE_HSI_H 31#define ECORE_HSI_H 32 33#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 34 35struct license_key { 36 uint32_t reserved[6]; 37 38 uint32_t max_iscsi_conn; 39#define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 40#define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0 41#define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 42#define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16 43 44 uint32_t reserved_a; 45 46 uint32_t max_fcoe_conn; 47#define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 48#define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0 49#define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 50#define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16 51 52 uint32_t reserved_b[4]; 53}; 54 55typedef struct license_key license_key_t; 56 57 58/**************************************************************************** 59 * Shared HW configuration * 60 ****************************************************************************/ 61#define PIN_CFG_NA 0x00000000 62#define PIN_CFG_GPIO0_P0 0x00000001 63#define PIN_CFG_GPIO1_P0 0x00000002 64#define PIN_CFG_GPIO2_P0 0x00000003 65#define PIN_CFG_GPIO3_P0 0x00000004 66#define PIN_CFG_GPIO0_P1 0x00000005 67#define PIN_CFG_GPIO1_P1 0x00000006 68#define PIN_CFG_GPIO2_P1 0x00000007 69#define PIN_CFG_GPIO3_P1 0x00000008 70#define PIN_CFG_EPIO0 0x00000009 71#define PIN_CFG_EPIO1 0x0000000a 72#define PIN_CFG_EPIO2 0x0000000b 73#define PIN_CFG_EPIO3 0x0000000c 74#define PIN_CFG_EPIO4 0x0000000d 75#define PIN_CFG_EPIO5 0x0000000e 76#define PIN_CFG_EPIO6 0x0000000f 77#define PIN_CFG_EPIO7 0x00000010 78#define PIN_CFG_EPIO8 0x00000011 79#define PIN_CFG_EPIO9 0x00000012 80#define PIN_CFG_EPIO10 0x00000013 81#define PIN_CFG_EPIO11 0x00000014 82#define PIN_CFG_EPIO12 0x00000015 83#define PIN_CFG_EPIO13 0x00000016 84#define PIN_CFG_EPIO14 0x00000017 85#define PIN_CFG_EPIO15 0x00000018 86#define PIN_CFG_EPIO16 0x00000019 87#define PIN_CFG_EPIO17 0x0000001a 88#define PIN_CFG_EPIO18 0x0000001b 89#define PIN_CFG_EPIO19 0x0000001c 90#define PIN_CFG_EPIO20 0x0000001d 91#define PIN_CFG_EPIO21 0x0000001e 92#define PIN_CFG_EPIO22 0x0000001f 93#define PIN_CFG_EPIO23 0x00000020 94#define PIN_CFG_EPIO24 0x00000021 95#define PIN_CFG_EPIO25 0x00000022 96#define PIN_CFG_EPIO26 0x00000023 97#define PIN_CFG_EPIO27 0x00000024 98#define PIN_CFG_EPIO28 0x00000025 99#define PIN_CFG_EPIO29 0x00000026 100#define PIN_CFG_EPIO30 0x00000027 101#define PIN_CFG_EPIO31 0x00000028 102 103/* EPIO definition */ 104#define EPIO_CFG_NA 0x00000000 105#define EPIO_CFG_EPIO0 0x00000001 106#define EPIO_CFG_EPIO1 0x00000002 107#define EPIO_CFG_EPIO2 0x00000003 108#define EPIO_CFG_EPIO3 0x00000004 109#define EPIO_CFG_EPIO4 0x00000005 110#define EPIO_CFG_EPIO5 0x00000006 111#define EPIO_CFG_EPIO6 0x00000007 112#define EPIO_CFG_EPIO7 0x00000008 113#define EPIO_CFG_EPIO8 0x00000009 114#define EPIO_CFG_EPIO9 0x0000000a 115#define EPIO_CFG_EPIO10 0x0000000b 116#define EPIO_CFG_EPIO11 0x0000000c 117#define EPIO_CFG_EPIO12 0x0000000d 118#define EPIO_CFG_EPIO13 0x0000000e 119#define EPIO_CFG_EPIO14 0x0000000f 120#define EPIO_CFG_EPIO15 0x00000010 121#define EPIO_CFG_EPIO16 0x00000011 122#define EPIO_CFG_EPIO17 0x00000012 123#define EPIO_CFG_EPIO18 0x00000013 124#define EPIO_CFG_EPIO19 0x00000014 125#define EPIO_CFG_EPIO20 0x00000015 126#define EPIO_CFG_EPIO21 0x00000016 127#define EPIO_CFG_EPIO22 0x00000017 128#define EPIO_CFG_EPIO23 0x00000018 129#define EPIO_CFG_EPIO24 0x00000019 130#define EPIO_CFG_EPIO25 0x0000001a 131#define EPIO_CFG_EPIO26 0x0000001b 132#define EPIO_CFG_EPIO27 0x0000001c 133#define EPIO_CFG_EPIO28 0x0000001d 134#define EPIO_CFG_EPIO29 0x0000001e 135#define EPIO_CFG_EPIO30 0x0000001f 136#define EPIO_CFG_EPIO31 0x00000020 137 138struct mac_addr { 139 uint32_t upper; 140 uint32_t lower; 141}; 142 143 144struct shared_hw_cfg { /* NVRAM Offset */ 145 /* Up to 16 bytes of NULL-terminated string */ 146 uint8_t part_num[16]; /* 0x104 */ 147 148 uint32_t config; /* 0x114 */ 149 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 150 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 151 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 152 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 153 154 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 155 156 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 157 158 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 159 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 160 161 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 162 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 163 /* Whatever MFW found in NVM 164 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 165 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 166 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 167 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 168 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 169 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 170 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 171 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 172 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 173 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 174 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 175 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 176 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 177 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 178 179 /* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For 180 backwards compatibility, value of 0 is disabling this feature. 181 That means that though 0 is a valid value, it cannot be 182 configured. */ 183 #define SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000 184 #define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT 12 185 186 #define SHARED_HW_CFG_LED_MODE_MASK 0x000F0000 187 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 188 #define SHARED_HW_CFG_LED_MAC1 0x00000000 189 #define SHARED_HW_CFG_LED_PHY1 0x00010000 190 #define SHARED_HW_CFG_LED_PHY2 0x00020000 191 #define SHARED_HW_CFG_LED_PHY3 0x00030000 192 #define SHARED_HW_CFG_LED_MAC2 0x00040000 193 #define SHARED_HW_CFG_LED_PHY4 0x00050000 194 #define SHARED_HW_CFG_LED_PHY5 0x00060000 195 #define SHARED_HW_CFG_LED_PHY6 0x00070000 196 #define SHARED_HW_CFG_LED_MAC3 0x00080000 197 #define SHARED_HW_CFG_LED_PHY7 0x00090000 198 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 199 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 200 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 201 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 202 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 203 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000 204 205 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 206 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 207 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 208 209 #define SHARED_HW_CFG_ATC_MASK 0x80000000 210 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 211 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 212 213 uint32_t config2; /* 0x118 */ 214 215 #define SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100 216 #define SHARED_HW_CFG_PCIE_GEN2_SHIFT 8 217 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 218 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 219 220 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 221 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 222 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 223 224 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 225 226 227 /* Output low when PERST is asserted */ 228 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 229 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 230 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 231 232 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 233 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 234 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 235 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 236 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 237 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 238 239 /* The fan failure mechanism is usually related to the PHY type 240 since the power consumption of the board is determined by the PHY. 241 Currently, fan is required for most designs with SFX7101, BCM8727 242 and BCM8481. If a fan is not required for a board which uses one 243 of those PHYs, this field should be set to "Disabled". If a fan is 244 required for a different PHY type, this option should be set to 245 "Enabled". The fan failure indication is expected on SPIO5 */ 246 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 247 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 248 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 249 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 250 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 251 252 /* ASPM Power Management support */ 253 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 254 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 255 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 256 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 257 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 258 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 259 260 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 261 tl_control_0 (register 0x2800) */ 262 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 263 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 264 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 265 266 267 /* Set the MDC/MDIO access for the first external phy */ 268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 273 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 275 276 /* Set the MDC/MDIO access for the second external phy */ 277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 282 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 283 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 284 285 /* Max number of PF MSIX vectors */ 286 uint32_t config_3; /* 0x11C */ 287 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F 288 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0 289 290 uint32_t ump_nc_si_config; /* 0x120 */ 291 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 292 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 293 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 294 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 297 298 /* Reserved bits: 226-230 */ 299 300 /* The output pin template BSC_SEL which selects the I2C for this 301 port in the I2C Mux */ 302 uint32_t board; /* 0x124 */ 303 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 304 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 305 306 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 307 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 308 /* Use the PIN_CFG_XXX defines on top */ 309 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000 310 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 311 312 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000 313 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 314 315 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000 316 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 317 318 uint32_t wc_lane_config; /* 0x128 */ 319 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 320 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 321 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 322 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 323 #define SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8 324 #define SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827 325 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 326 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 327 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 328 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 329 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 330 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 331 332 /* TX lane Polarity swap */ 333 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 334 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 335 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 336 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 337 /* TX lane Polarity swap */ 338 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 339 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 340 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 341 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 342 343 /* Selects the port layout of the board */ 344 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 345 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 346 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 347 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 348 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 352}; 353 354 355/**************************************************************************** 356 * Port HW configuration * 357 ****************************************************************************/ 358struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 359 360 uint32_t pci_id; 361 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF 362 #define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0 363 364 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000 365 #define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT 16 366 367 uint32_t pci_sub_id; 368 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF 369 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0 370 371 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000 372 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT 16 373 374 uint32_t power_dissipated; 375 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF 376 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 377 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00 378 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 379 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000 380 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 381 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000 382 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 383 384 uint32_t power_consumed; 385 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF 386 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 387 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00 388 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 389 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000 390 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 391 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000 392 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 393 394 uint32_t mac_upper; 395 uint32_t mac_lower; /* 0x140 */ 396 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF 397 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 398 399 400 uint32_t iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 401 uint32_t iscsi_mac_lower; 402 403 uint32_t rdma_mac_upper; /* Upper 16 bits are always zeroes */ 404 uint32_t rdma_mac_lower; 405 406 uint32_t serdes_config; 407 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF 408 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 409 410 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000 411 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 412 413 414 /* Default values: 2P-64, 4P-32 */ 415 uint32_t reserved; 416 417 uint32_t vf_config; /* 0x15C */ 418 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 419 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 420 421 uint32_t mf_pci_id; /* 0x160 */ 422 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 423 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 424 425 /* Controls the TX laser of the SFP+ module */ 426 uint32_t sfp_ctrl; /* 0x164 */ 427 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 428 #define PORT_HW_CFG_TX_LASER_SHIFT 0 429 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 430 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 431 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 432 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 433 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 434 435 /* Controls the fault module LED of the SFP+ */ 436 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 437 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 438 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 439 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 440 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 441 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 442 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 443 444 /* The output pin TX_DIS that controls the TX laser of the SFP+ 445 module. Use the PIN_CFG_XXX defines on top */ 446 uint32_t e3_sfp_ctrl; /* 0x168 */ 447 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 448 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 449 450 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 451 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 452 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 453 454 /* The input pin MOD_ABS that indicates whether SFP+ module is 455 present or not. Use the PIN_CFG_XXX defines on top */ 456 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 457 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 458 459 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 460 module. Use the PIN_CFG_XXX defines on top */ 461 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 462 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 463 464 /* 465 * The input pin which signals module transmit fault. Use the 466 * PIN_CFG_XXX defines on top 467 */ 468 uint32_t e3_cmn_pin_cfg; /* 0x16C */ 469 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 470 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 471 472 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 473 top */ 474 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 475 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 476 477 /* 478 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 479 * defines on top 480 */ 481 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 482 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 483 484 /* The output pin values BSC_SEL which selects the I2C for this port 485 in the I2C Mux */ 486 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 487 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 488 489 490 /* 491 * The input pin I_FAULT which indicate over-current has occurred. 492 * Use the PIN_CFG_XXX defines on top 493 */ 494 uint32_t e3_cmn_pin_cfg1; /* 0x170 */ 495 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 496 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 497 498 /* pause on host ring */ 499 uint32_t generic_features; /* 0x174 */ 500 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 501 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 502 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 503 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 504 505 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 506 * LOM recommended and tested value is 0xBEB2. Using a different 507 * value means using a value not tested by BRCM 508 */ 509 uint32_t sfi_tap_values; /* 0x178 */ 510 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF 511 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 512 513 /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested 514 * value is 0x2. LOM recommended and tested value is 0x2. Using a 515 * different value means using a value not tested by BRCM 516 */ 517 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 518 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 519 520 uint32_t reserved0[5]; /* 0x17c */ 521 522 uint32_t aeu_int_mask; /* 0x190 */ 523 524 uint32_t media_type; /* 0x194 */ 525 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 526 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 527 528 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 529 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 530 531 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 532 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 533 534 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 535 (not direct mode), those values will not take effect on the 4 XGXS 536 lanes. For some external PHYs (such as 8706 and 8726) the values 537 will be used to configure the external PHY in those cases, not 538 all 4 values are needed. */ 539 uint16_t xgxs_config_rx[4]; /* 0x198 */ 540 uint16_t xgxs_config_tx[4]; /* 0x1A0 */ 541 542 543 /* For storing FCOE mac on shared memory */ 544 uint32_t fcoe_fip_mac_upper; 545 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 546 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 547 uint32_t fcoe_fip_mac_lower; 548 549 uint32_t fcoe_wwn_port_name_upper; 550 uint32_t fcoe_wwn_port_name_lower; 551 552 uint32_t fcoe_wwn_node_name_upper; 553 uint32_t fcoe_wwn_node_name_lower; 554 555 /* wwpn for npiv enabled */ 556 uint32_t wwpn_for_npiv_config; /* 0x1C0 */ 557 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001 558 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0 559 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000 560 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001 561 562 /* wwpn for npiv valid addresses */ 563 uint32_t wwpn_for_npiv_valid_addresses; /* 0x1C4 */ 564 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF 565 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0 566 567 struct mac_addr wwpn_for_niv_macs[16]; 568 569 /* Reserved bits: 2272-2336 For storing FCOE mac on shared memory */ 570 uint32_t Reserved1[14]; 571 572 uint32_t pf_allocation; /* 0x280 */ 573 /* number of vfs per PF, if 0 - sriov disabled */ 574 #define PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF 575 #define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0 576 577 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 578 84833 only */ 579 uint32_t xgbt_phy_cfg; /* 0x284 */ 580 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 581 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 582 583 uint32_t default_cfg; /* 0x288 */ 584 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 585 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 586 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 587 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 588 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 589 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 590 591 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 592 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 593 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 594 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 595 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 596 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 597 598 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 599 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 600 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 601 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 602 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 603 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 604 605 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 606 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 607 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 608 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 609 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 610 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 611 612 /* When KR link is required to be set to force which is not 613 KR-compliant, this parameter determine what is the trigger for it. 614 When GPIO is selected, low input will force the speed. Currently 615 default speed is 1G. In the future, it may be widen to select the 616 forced speed in with another parameter. Note when force-1G is 617 enabled, it override option 56: Link Speed option. */ 618 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 619 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 620 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 621 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 622 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 623 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 624 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 625 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 626 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 627 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 628 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 629 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 630 /* Enable to determine with which GPIO to reset the external phy */ 631 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 632 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 633 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 634 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 635 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 636 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 637 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 638 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 639 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 640 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 641 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 642 643 /* Enable BAM on KR */ 644 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 645 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 646 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 647 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 648 649 /* Enable Common Mode Sense */ 650 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 651 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 652 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 653 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 654 655 /* Determine the Serdes electrical interface */ 656 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 657 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 658 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 659 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 660 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 661 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 662 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 663 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 664 665 /* SFP+ main TAP and post TAP volumes */ 666 #define PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000 667 #define PORT_HW_CFG_TAP_LEVELS_SHIFT 28 668 #define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000 669 #define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000 670 #define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000 671 #define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000 672 #define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000 673 #define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000 674 675 uint32_t speed_capability_mask2; /* 0x28C */ 676 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 677 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 678 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 679 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002 680 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004 681 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 682 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 683 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020 684 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 685 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 686 687 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 688 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 689 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 690 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000 691 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000 692 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 693 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 694 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000 695 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 696 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 697 698 699 /* In the case where two media types (e.g. copper and fiber) are 700 present and electrically active at the same time, PHY Selection 701 will determine which of the two PHYs will be designated as the 702 Active PHY and used for a connection to the network. */ 703 uint32_t multi_phy_config; /* 0x290 */ 704 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 705 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 706 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 707 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 708 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 709 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 710 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 711 712 /* When enabled, all second phy nvram parameters will be swapped 713 with the first phy parameters */ 714 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 715 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 716 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 717 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 718 719 720 /* Address of the second external phy */ 721 uint32_t external_phy_config2; /* 0x294 */ 722 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 723 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 724 725 /* The second XGXS external PHY type */ 726 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 727 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 728 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 729 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 730 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 731 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 732 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 733 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 734 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 735 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 736 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 737 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 738 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 739 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 740 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 741 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 742 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 743 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 744 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 745 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100 746 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 747 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 748 749 750 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 751 8706, 8726 and 8727) not all 4 values are needed. */ 752 uint16_t xgxs_config2_rx[4]; /* 0x296 */ 753 uint16_t xgxs_config2_tx[4]; /* 0x2A0 */ 754 755 uint32_t lane_config; 756 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 757 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 758 /* AN and forced */ 759 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 760 /* forced only */ 761 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 762 /* forced only */ 763 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 764 /* forced only */ 765 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 766 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 767 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 768 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 769 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 770 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000 771 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 772 773 /* Indicate whether to swap the external phy polarity */ 774 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 775 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 776 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 777 778 779 uint32_t external_phy_config; 780 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF 781 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 782 783 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00 784 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 785 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 786 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 787 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 788 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 789 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 790 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 791 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 792 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 793 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 794 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 795 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 796 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 797 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 798 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 799 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 800 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 801 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 802 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100 803 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 804 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 805 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 806 807 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000 808 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 809 810 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000 811 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 812 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 813 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 814 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 815 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 816 817 uint32_t speed_capability_mask; 818 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF 819 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 820 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 821 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 822 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 823 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 824 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 825 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 826 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 827 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 828 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 829 830 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000 831 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 832 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 833 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 834 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 835 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 836 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 837 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 838 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 839 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 840 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 841 842 /* A place to hold the original MAC address as a backup */ 843 uint32_t backup_mac_upper; /* 0x2B4 */ 844 uint32_t backup_mac_lower; /* 0x2B8 */ 845 846}; 847 848 849/**************************************************************************** 850 * Shared Feature configuration * 851 ****************************************************************************/ 852struct shared_feat_cfg { /* NVRAM Offset */ 853 854 uint32_t config; /* 0x450 */ 855 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 856 857 /* Use NVRAM values instead of HW default values */ 858 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 859 0x00000002 860 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 861 0x00000000 862 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 863 0x00000002 864 865 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 866 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 867 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 868 869 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 870 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 871 872 /* Override the OTP back to single function mode. When using GPIO, 873 high means only SF, 0 is according to CLP configuration */ 874 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 875 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 876 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 877 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 878 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 879 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 880 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 881 882 /* Act as if the FCoE license is invalid */ 883 #define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000 884 885 /* Force FLR capability to all ports */ 886 #define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000 887 888 /* Act as if the iSCSI license is invalid */ 889 #define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000 890 #define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT 14 891 #define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000 892 #define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000 893 894 /* The interval in seconds between sending LLDP packets. Set to zero 895 to disable the feature */ 896 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000 897 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 898 899 /* The assigned device type ID for LLDP usage */ 900 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000 901 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 902 903}; 904 905 906/**************************************************************************** 907 * Port Feature configuration * 908 ****************************************************************************/ 909struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 910 911 uint32_t config; 912 #define PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F 913 #define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0 914 #define PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000 915 #define PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001 916 #define PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002 917 #define PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003 918 #define PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004 919 #define PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005 920 #define PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006 921 #define PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007 922 #define PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008 923 #define PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009 924 #define PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a 925 #define PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b 926 #define PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c 927 #define PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d 928 #define PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e 929 #define PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f 930 #define PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0 931 #define PORT_FEAT_CFG_BAR2_SIZE_SHIFT 4 932 #define PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000 933 #define PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010 934 #define PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020 935 #define PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030 936 #define PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040 937 #define PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050 938 #define PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060 939 #define PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070 940 #define PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080 941 #define PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090 942 #define PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0 943 #define PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0 944 #define PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0 945 #define PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0 946 #define PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0 947 #define PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0 948 949 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 950 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 951 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 952 953 #define PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200 954 #define PORT_FEAT_CFG_AUTOGREEEN_SHIFT 9 955 #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000 956 #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200 957 958 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 959 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT 10 960 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000 961 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 962 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 963 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00 964 965 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 966 #define PORT_FEATURE_EN_SIZE_SHIFT 24 967 #define PORT_FEATURE_WOL_ENABLED 0x01000000 968 #define PORT_FEATURE_MBA_ENABLED 0x02000000 969 #define PORT_FEATURE_MFW_ENABLED 0x04000000 970 971 /* Advertise expansion ROM even if MBA is disabled */ 972 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 973 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 974 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 975 976 /* Check the optic vendor via i2c against a list of approved modules 977 in a separate nvram image */ 978 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000 979 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 980 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 981 0x00000000 982 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 983 0x20000000 984 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 985 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 986 987 uint32_t wol_config; 988 /* Default is used when driver sets to "auto" mode */ 989 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 990 991 uint32_t mba_config; 992 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 993 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 994 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 995 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 996 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 997 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 998 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 999 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 1000 1001 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 1002 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 1003 1004 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 1005 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 1006 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 1007 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 1008 1009 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000 1010 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 1011 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 1012 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 1013 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 1014 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 1015 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 1016 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 1017 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 1018 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 1019 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 1020 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 1021 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 1022 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 1023 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 1024 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 1025 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 1026 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 1027 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000 1028 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 1029 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 1030 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 1031 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 1032 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 1033 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 1034 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 1035 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000 1036 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 1037 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 1038 #define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000 1039 #define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000 1040 #define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000 1041 #define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000 1042 #define PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000 1043 #define PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000 1044 #define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000 1045 #define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000 1046 1047 uint32_t Reserved0; /* 0x460 */ 1048 1049 uint32_t mba_vlan_cfg; 1050 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF 1051 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1052 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1053 #define PORT_FEATUTE_BOFM_CFGD_EN 0x00020000 1054 #define PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000 1055 #define PORT_FEATURE_BOFM_CFGD_VEN 0x00080000 1056 1057 uint32_t Reserved1; 1058 uint32_t smbus_config; 1059 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1060 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1061 1062 uint32_t vf_config; 1063 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F 1064 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1065 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1066 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1067 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1068 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1069 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1070 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1071 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1072 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1073 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1074 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1075 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1076 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1077 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1078 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1079 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1080 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1081 1082 uint32_t link_config; /* Used as HW defaults for the driver */ 1083 1084 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1085 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1086 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1087 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1088 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1089 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1090 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1091 #define PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500 1092 #define PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600 1093 #define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700 1094 1095 #define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000 1096 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1097 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1098 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000 1099 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000 1100 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1101 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1102 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1103 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1104 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1105 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1106 1107 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1108 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1109 /* (forced) low speed switch (< 10G) */ 1110 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1111 /* (forced) high speed switch (>= 10G) */ 1112 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1113 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1114 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1115 1116 1117 /* The default for MCP link configuration, 1118 uses the same defines as link_config */ 1119 uint32_t mfw_wol_link_cfg; 1120 1121 /* The default for the driver of the second external phy, 1122 uses the same defines as link_config */ 1123 uint32_t link_config2; /* 0x47C */ 1124 1125 /* The default for MCP of the second external phy, 1126 uses the same defines as link_config */ 1127 uint32_t mfw_wol_link_cfg2; /* 0x480 */ 1128 1129 1130 /* EEE power saving mode */ 1131 uint32_t eee_power_mode; /* 0x484 */ 1132 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF 1133 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 1134 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 1135 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 1136 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 1137 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 1138 1139 1140 uint32_t Reserved2[16]; /* 0x488 */ 1141}; 1142 1143/**************************************************************************** 1144 * Device Information * 1145 ****************************************************************************/ 1146struct shm_dev_info { /* size */ 1147 1148 uint32_t bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1149 1150 struct shared_hw_cfg shared_hw_config; /* 40 */ 1151 1152 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1153 1154 struct shared_feat_cfg shared_feature_config; /* 4 */ 1155 1156 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1157 1158}; 1159 1160struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */ 1161 1162 /* Threshold in celcius to start using the fan */ 1163 uint32_t temperature_monitor1; /* 0x4000 */ 1164 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F 1165 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0 1166 1167 /* Threshold in celcius to shut down the board */ 1168 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00 1169 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT 8 1170 1171 /* EPIO of fan temperature status */ 1172 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000 1173 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT 16 1174 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000 1175 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000 1176 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000 1177 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000 1178 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000 1179 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000 1180 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000 1181 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000 1182 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000 1183 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000 1184 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000 1185 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000 1186 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000 1187 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000 1188 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000 1189 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000 1190 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000 1191 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000 1192 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000 1193 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000 1194 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000 1195 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000 1196 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000 1197 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000 1198 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000 1199 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000 1200 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000 1201 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000 1202 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000 1203 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000 1204 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000 1205 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000 1206 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000 1207 1208 /* EPIO of shut down temperature status */ 1209 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000 1210 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT 24 1211 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000 1212 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000 1213 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000 1214 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000 1215 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000 1216 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000 1217 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000 1218 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000 1219 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000 1220 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000 1221 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000 1222 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000 1223 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000 1224 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000 1225 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000 1226 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000 1227 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000 1228 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000 1229 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000 1230 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000 1231 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000 1232 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000 1233 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000 1234 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000 1235 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000 1236 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000 1237 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000 1238 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000 1239 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000 1240 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000 1241 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000 1242 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000 1243 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000 1244 1245 1246 /* EPIO of shut down temperature status */ 1247 uint32_t temperature_monitor2; /* 0x4004 */ 1248 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF 1249 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0 1250 1251 1252 /* MFW flavor to be used */ 1253 uint32_t mfw_cfg; /* 0x4008 */ 1254 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF 1255 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0 1256 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000 1257 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001 1258 1259 /* Should NIC data query remain enabled upon last drv unload */ 1260 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100 1261 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT 8 1262 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000 1263 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100 1264 1265 /* Hide DCBX feature in CCM/BACS menus */ 1266 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000 1267 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16 1268 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000 1269 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000 1270 1271 uint32_t smbus_config; /* 0x400C */ 1272 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF 1273 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0 1274 1275 /* Switching regulator loop gain */ 1276 uint32_t board_cfg; /* 0x4010 */ 1277 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F 1278 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0 1279 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000 1280 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008 1281 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009 1282 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a 1283 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b 1284 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c 1285 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d 1286 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e 1287 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f 1288 1289 /* whether shadow swim feature is supported */ 1290 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100 1291 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT 8 1292 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000 1293 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100 1294 1295 /* whether to show/hide SRIOV menu in CCM */ 1296 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200 1297 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT 9 1298 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000 1299 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200 1300 1301 /* Overide PCIE revision ID when enabled the, 1302 revision ID will set to B1=='0x11' */ 1303 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400 1304 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT 10 1305 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000 1306 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400 1307 1308 /* Threshold in celcius for max continuous operation */ 1309 uint32_t temperature_report; /* 0x4014 */ 1310 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F 1311 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0 1312 1313 /* Threshold in celcius for sensor caution */ 1314 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00 1315 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT 8 1316 1317 /* wwn node prefix to be used (unless value is 0) */ 1318 uint32_t wwn_prefix; /* 0x4018 */ 1319 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF 1320 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0 1321 1322 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00 1323 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT 8 1324 1325 /* wwn port prefix to be used (unless value is 0) */ 1326 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000 1327 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT 16 1328 1329 /* wwn port prefix to be used (unless value is 0) */ 1330 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000 1331 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT 24 1332 1333 /* General debug nvm cfg */ 1334 uint32_t dbg_cfg_flags; /* 0x401C */ 1335 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF 1336 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0 1337 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001 1338 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002 1339 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004 1340 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008 1341 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010 1342 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020 1343 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040 1344 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080 1345 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100 1346 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200 1347 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400 1348 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800 1349 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000 1350 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000 1351 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000 1352 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000 1353 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000 1354 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000 1355 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000 1356 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000 1357 1358 /* Debug signet rx threshold */ 1359 uint32_t dbg_rx_sigdet_threshold; /* 0x4020 */ 1360 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007 1361 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0 1362 1363 /* Enable IFFE feature */ 1364 uint32_t iffe_features; /* 0x4024 */ 1365 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001 1366 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0 1367 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000 1368 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001 1369 1370 /* Allowable port enablement (bitmask for ports 3-1) */ 1371 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E 1372 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT 1 1373 1374 /* Allow iSCSI offload override */ 1375 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010 1376 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT 4 1377 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000 1378 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010 1379 1380 /* Allow FCoE offload override */ 1381 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020 1382 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT 5 1383 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000 1384 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020 1385 1386 /* Tie to adaptor */ 1387 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000 1388 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT 15 1389 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000 1390 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000 1391 1392 /* Currently enabled port(s) (bitmask for ports 3-1) */ 1393 uint32_t current_iffe_mask; /* 0x4028 */ 1394 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E 1395 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT 1 1396 1397 /* Current iSCSI offload */ 1398 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010 1399 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT 4 1400 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000 1401 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010 1402 1403 /* Current FCoE offload */ 1404 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020 1405 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT 5 1406 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000 1407 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020 1408 1409 /* FW set this pin to "0" (assert) these signal if either of its MAC 1410 * or PHY specific threshold values is exceeded. 1411 * Values are standard GPIO/EPIO pins. 1412 */ 1413 uint32_t threshold_pin; /* 0x402C */ 1414 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF 1415 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0 1416 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00 1417 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT 8 1418 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000 1419 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT 16 1420 1421 /* MAC die temperature threshold in Celsius. */ 1422 uint32_t mac_threshold_val; /* 0x4030 */ 1423 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF 1424 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0 1425 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00 1426 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8 1427 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000 1428 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16 1429 1430 /* PHY die temperature threshold in Celsius. */ 1431 uint32_t phy_threshold_val; /* 0x4034 */ 1432 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF 1433 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0 1434 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00 1435 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8 1436 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000 1437 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16 1438 1439 /* External pins to communicate with host. 1440 * Values are standard GPIO/EPIO pins. 1441 */ 1442 uint32_t host_pin; /* 0x4038 */ 1443 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF 1444 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0 1445 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00 1446 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT 8 1447 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000 1448 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16 1449 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000 1450 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24 1451}; 1452 1453 1454#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1455 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1456#endif 1457 1458#define FUNC_0 0 1459#define FUNC_1 1 1460#define FUNC_2 2 1461#define FUNC_3 3 1462#define FUNC_4 4 1463#define FUNC_5 5 1464#define FUNC_6 6 1465#define FUNC_7 7 1466#define E1_FUNC_MAX 2 1467#define E1H_FUNC_MAX 8 1468#define E2_FUNC_MAX 4 /* per path */ 1469 1470#define VN_0 0 1471#define VN_1 1 1472#define VN_2 2 1473#define VN_3 3 1474#define E1VN_MAX 1 1475#define E1HVN_MAX 4 1476 1477#define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1478/* This value (in milliseconds) determines the frequency of the driver 1479 * issuing the PULSE message code. The firmware monitors this periodic 1480 * pulse to determine when to switch to an OS-absent mode. */ 1481#define DRV_PULSE_PERIOD_MS 250 1482 1483/* This value (in milliseconds) determines how long the driver should 1484 * wait for an acknowledgement from the firmware before timing out. Once 1485 * the firmware has timed out, the driver will assume there is no firmware 1486 * running and there won't be any firmware-driver synchronization during a 1487 * driver reset. */ 1488#define FW_ACK_TIME_OUT_MS 5000 1489 1490#define FW_ACK_POLL_TIME_MS 1 1491 1492#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1493 1494#define MFW_TRACE_SIGNATURE 0x54524342 1495 1496/**************************************************************************** 1497 * Driver <-> FW Mailbox * 1498 ****************************************************************************/ 1499struct drv_port_mb { 1500 1501 uint32_t link_status; 1502 /* Driver should update this field on any link change event */ 1503 1504 #define LINK_STATUS_NONE (0<<0) 1505 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1506 #define LINK_STATUS_LINK_UP 0x00000001 1507 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1508 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1509 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1510 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1511 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1512 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1513 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1514 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1515 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1516 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1517 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1518 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1519 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1520 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1521 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1522 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1523 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1524 1525 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1526 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1527 1528 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1529 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1530 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1531 1532 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1533 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1534 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1535 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1536 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1537 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1538 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1539 1540 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1541 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1542 1543 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1544 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1545 1546 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1547 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1548 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1549 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1550 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1551 1552 #define LINK_STATUS_SERDES_LINK 0x00100000 1553 1554 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1555 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1556 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1557 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1558 1559 #define LINK_STATUS_PFC_ENABLED 0x20000000 1560 1561 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1562 #define LINK_STATUS_SFP_TX_FAULT 0x80000000 1563 1564 uint32_t port_stx; 1565 1566 uint32_t stat_nig_timer; 1567 1568 /* MCP firmware does not use this field */ 1569 uint32_t ext_phy_fw_version; 1570 1571}; 1572 1573 1574struct drv_func_mb { 1575 1576 uint32_t drv_mb_header; 1577 #define DRV_MSG_CODE_MASK 0xffff0000 1578 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1579 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1580 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1581 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1582 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1583 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1584 #define DRV_MSG_CODE_DCC_OK 0x30000000 1585 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1586 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1587 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1588 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1589 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1590 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1591 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1592 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1593 1594 /* 1595 * The optic module verification command requires bootcode 1596 * v5.0.6 or later, te specific optic module verification command 1597 * requires bootcode v5.2.12 or later 1598 */ 1599 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1600 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1601 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1602 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1603 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 1604 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 1605 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1606 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201 1607 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1608 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 1609 1610 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1611 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1612 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 1613 1614 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1615 1616 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 1617 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 1618 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 1619 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 1620 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 1621 1622 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 1623 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 1624 1625 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 1626 1627 #define DRV_MSG_CODE_RMMOD 0xdb000000 1628 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f 1629 1630 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1631 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1632 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1633 1634 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1635 1636 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 1637 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 1638 1639 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1640 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1641 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1642 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1643 1644 #define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000 1645 #define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000 1646 1647 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1648 1649 uint32_t drv_mb_param; 1650 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1651 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1652 1653 #define DRV_MSG_CODE_UNLOAD_NON_D3_POWER 0x00000001 1654 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 1655 1656 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a 1657 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000 1658 1659 #define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001 1660 #define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ 0x00000002 1661 1662 uint32_t fw_mb_header; 1663 #define FW_MSG_CODE_MASK 0xffff0000 1664 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1665 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1666 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1667 /* Load common chip is supported from bc 6.0.0 */ 1668 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1669 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1670 1671 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1672 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1673 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1674 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1675 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1676 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1677 #define FW_MSG_CODE_DCC_DONE 0x30100000 1678 #define FW_MSG_CODE_LLDP_DONE 0x40100000 1679 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1680 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1681 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1682 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1683 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1684 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1685 #define FW_MSG_CODE_NO_KEY 0x80f00000 1686 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1687 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1688 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1689 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1690 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1691 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1692 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1693 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1694 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1695 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1696 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 1697 1698 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 1699 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 1700 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 1701 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 1702 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 1703 1704 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 1705 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 1706 1707 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 1708 1709 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000 1710 1711 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1712 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1713 1714 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1715 1716 #define FW_MSG_CODE_FLR_ACK 0x02000000 1717 #define FW_MSG_CODE_FLR_NACK 0x02100000 1718 1719 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1720 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1721 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1722 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1723 1724 #define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000 1725 #define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000 1726 1727 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1728 1729 uint32_t fw_mb_param; 1730 1731 #define FW_PARAM_INVALID_IMG 0xffffffff 1732 1733 uint32_t drv_pulse_mb; 1734 #define DRV_PULSE_SEQ_MASK 0x00007fff 1735 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1736 /* 1737 * The system time is in the format of 1738 * (year-2001)*12*32 + month*32 + day. 1739 */ 1740 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1741 /* 1742 * Indicate to the firmware not to go into the 1743 * OS-absent when it is not getting driver pulse. 1744 * This is used for debugging as well for PXE(MBA). 1745 */ 1746 1747 uint32_t mcp_pulse_mb; 1748 #define MCP_PULSE_SEQ_MASK 0x00007fff 1749 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1750 /* Indicates to the driver not to assert due to lack 1751 * of MCP response */ 1752 #define MCP_EVENT_MASK 0xffff0000 1753 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1754 1755 uint32_t iscsi_boot_signature; 1756 uint32_t iscsi_boot_block_offset; 1757 1758 uint32_t drv_status; 1759 #define DRV_STATUS_PMF 0x00000001 1760 #define DRV_STATUS_VF_DISABLED 0x00000002 1761 #define DRV_STATUS_SET_MF_BW 0x00000004 1762 #define DRV_STATUS_LINK_EVENT 0x00000008 1763 1764 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1765 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1766 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1767 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1768 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1769 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1770 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1771 1772 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1773 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1774 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 1775 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 1776 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 1777 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 1778 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 1779 1780 #define DRV_STATUS_DRV_INFO_REQ 0x04000000 1781 1782 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 1783 1784 uint32_t virt_mac_upper; 1785 #define VIRT_MAC_SIGN_MASK 0xffff0000 1786 #define VIRT_MAC_SIGNATURE 0x564d0000 1787 uint32_t virt_mac_lower; 1788 1789}; 1790 1791 1792/**************************************************************************** 1793 * Management firmware state * 1794 ****************************************************************************/ 1795/* Allocate 440 bytes for management firmware */ 1796#define MGMTFW_STATE_WORD_SIZE 110 1797 1798struct mgmtfw_state { 1799 uint32_t opaque[MGMTFW_STATE_WORD_SIZE]; 1800}; 1801 1802 1803/**************************************************************************** 1804 * Multi-Function configuration * 1805 ****************************************************************************/ 1806struct shared_mf_cfg { 1807 1808 uint32_t clp_mb; 1809 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1810 /* set by CLP */ 1811 #define SHARED_MF_CLP_EXIT 0x00000001 1812 /* set by MCP */ 1813 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1814 1815}; 1816 1817struct port_mf_cfg { 1818 1819 uint32_t dynamic_cfg; /* device control channel */ 1820 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1821 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1822 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1823 1824 uint32_t reserved[1]; 1825 1826}; 1827 1828struct func_mf_cfg { 1829 1830 uint32_t config; 1831 /* E/R/I/D */ 1832 /* function 0 of each port cannot be hidden */ 1833 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1834 1835 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1836 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1837 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1838 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1839 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1840 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1841 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1842 1843 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1844 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1845 1846 #define FUNC_MF_CFG_FUNC_BOOT_MASK 0x00000060 1847 #define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL 0x00000000 1848 #define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED 0x00000020 1849 #define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED 0x00000040 1850 1851 /* PRI */ 1852 /* 0 - low priority, 3 - high priority */ 1853 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1854 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1855 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1856 1857 /* MINBW, MAXBW */ 1858 /* value range - 0..100, increments in 100Mbps */ 1859 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1860 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1861 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1862 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1863 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1864 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1865 1866 uint32_t mac_upper; /* MAC */ 1867 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1868 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1869 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1870 uint32_t mac_lower; 1871 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1872 1873 uint32_t e1hov_tag; /* VNI */ 1874 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1875 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1876 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1877 1878 /* afex default VLAN ID - 12 bits */ 1879 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 1880 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 1881 1882 uint32_t afex_config; 1883 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff 1884 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 1885 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 1886 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 1887 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 1888 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 1889 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 1890 1891 uint32_t pf_allocation; 1892 /* number of vfs in function, if 0 - sriov disabled */ 1893 #define FUNC_MF_CFG_NUMBER_OF_VFS_MASK 0x000000FF 1894 #define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT 0 1895}; 1896 1897enum mf_cfg_afex_vlan_mode { 1898 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, 1899 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, 1900 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE 1901}; 1902 1903/* This structure is not applicable and should not be accessed on 57711 */ 1904struct func_ext_cfg { 1905 uint32_t func_cfg; 1906 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F 1907 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 1908 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 1909 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 1910 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 1911 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 1912 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 1913 1914 uint32_t iscsi_mac_addr_upper; 1915 uint32_t iscsi_mac_addr_lower; 1916 1917 uint32_t fcoe_mac_addr_upper; 1918 uint32_t fcoe_mac_addr_lower; 1919 1920 uint32_t fcoe_wwn_port_name_upper; 1921 uint32_t fcoe_wwn_port_name_lower; 1922 1923 uint32_t fcoe_wwn_node_name_upper; 1924 uint32_t fcoe_wwn_node_name_lower; 1925 1926 uint32_t preserve_data; 1927 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 1928 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 1929 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 1930 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 1931 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 1932 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 1933}; 1934 1935struct mf_cfg { 1936 1937 struct shared_mf_cfg shared_mf_config; /* 0x4 */ 1938 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; 1939 /* 0x10*2=0x20 */ 1940 /* for all chips, there are 8 mf functions */ 1941 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 1942 /* 1943 * Extended configuration per function - this array does not exist and 1944 * should not be accessed on 57711 1945 */ 1946 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 1947}; /* 0x224 */ 1948 1949/**************************************************************************** 1950 * Shared Memory Region * 1951 ****************************************************************************/ 1952struct shmem_region { /* SharedMem Offset (size) */ 1953 1954 uint32_t validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 1955 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 1956 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 1957 /* validity bits */ 1958 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 1959 #define SHR_MEM_VALIDITY_MB 0x00200000 1960 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 1961 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 1962 /* One licensing bit should be set */ 1963 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 1964 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 1965 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 1966 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 1967 /* Active MFW */ 1968 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 1969 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 1970 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 1971 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 1972 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 1973 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 1974 1975 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 1976 1977 license_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 1978 1979 /* FW information (for internal FW use) */ 1980 uint32_t fw_info_fio_offset; /* 0x4a8 (0x4) */ 1981 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 1982 1983 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 1984 1985 1986#ifdef BMAPI 1987 /* This is a variable length array */ 1988 /* the number of function depends on the chip type */ 1989 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1990#else 1991 /* the number of function depends on the chip type */ 1992 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1993#endif /* BMAPI */ 1994 1995}; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 1996 1997/**************************************************************************** 1998 * Shared Memory 2 Region * 1999 ****************************************************************************/ 2000/* The fw_flr_ack is actually built in the following way: */ 2001/* 8 bit: PF ack */ 2002/* 64 bit: VF ack */ 2003/* 8 bit: ios_dis_ack */ 2004/* In order to maintain endianity in the mailbox hsi, we want to keep using */ 2005/* uint32_t. The fw must have the VF right after the PF since this is how it */ 2006/* access arrays(it expects always the VF to reside after the PF, and that */ 2007/* makes the calculation much easier for it. ) */ 2008/* In order to answer both limitations, and keep the struct small, the code */ 2009/* will abuse the structure defined here to achieve the actual partition */ 2010/* above */ 2011/****************************************************************************/ 2012struct fw_flr_ack { 2013 uint32_t pf_ack; 2014 uint32_t vf_ack[1]; 2015 uint32_t iov_dis_ack; 2016}; 2017 2018struct fw_flr_mb { 2019 uint32_t aggint; 2020 uint32_t opgen_addr; 2021 struct fw_flr_ack ack; 2022}; 2023 2024struct eee_remote_vals { 2025 uint32_t tx_tw; 2026 uint32_t rx_tw; 2027}; 2028 2029/**** SUPPORT FOR SHMEM ARRRAYS *** 2030 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 2031 * define arrays with storage types smaller then unsigned dwords. 2032 * The macros below add generic support for SHMEM arrays with numeric elements 2033 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 2034 * array with individual bit-filed elements accessed using shifts and masks. 2035 * 2036 */ 2037 2038/* eb is the bitwidth of a single element */ 2039#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 2040#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 2041 2042/* the bit-position macro allows the used to flip the order of the arrays 2043 * elements on a per byte or word boundary. 2044 * 2045 * example: an array with 8 entries each 4 bit wide. This array will fit into 2046 * a single dword. The diagrmas below show the array order of the nibbles. 2047 * 2048 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 2049 * 2050 * | | | | 2051 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 2052 * | | | | 2053 * 2054 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 2055 * 2056 * | | | | 2057 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 2058 * | | | | 2059 * 2060 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 2061 * 2062 * | | | | 2063 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 2064 * | | | | 2065 */ 2066#define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 2067 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 2068 (((i)%((fb)/(eb))) * (eb))) 2069 2070#define SHMEM_ARRAY_GET(a, i, eb, fb) \ 2071 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 2072 SHMEM_ARRAY_MASK(eb)) 2073 2074#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 2075do { \ 2076 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 2077 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 2078 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 2079 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 2080} while (0) 2081 2082 2083/****START OF DCBX STRUCTURES DECLARATIONS****/ 2084#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 2085#define DCBX_PRI_PG_BITWIDTH 4 2086#define DCBX_PRI_PG_FBITS 8 2087#define DCBX_PRI_PG_GET(a, i) \ 2088 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 2089#define DCBX_PRI_PG_SET(a, i, val) \ 2090 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 2091#define DCBX_MAX_NUM_PG_BW_ENTRIES 8 2092#define DCBX_BW_PG_BITWIDTH 8 2093#define DCBX_PG_BW_GET(a, i) \ 2094 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 2095#define DCBX_PG_BW_SET(a, i, val) \ 2096 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 2097#define DCBX_STRICT_PRI_PG 15 2098#define DCBX_MAX_APP_PROTOCOL 16 2099#define DCBX_MAX_APP_LOCAL 32 2100#define FCOE_APP_IDX 0 2101#define ISCSI_APP_IDX 1 2102#define PREDEFINED_APP_IDX_MAX 2 2103 2104 2105/* Big/Little endian have the same representation. */ 2106struct dcbx_ets_feature { 2107 /* 2108 * For Admin MIB - is this feature supported by the 2109 * driver | For Local MIB - should this feature be enabled. 2110 */ 2111 uint32_t enabled; 2112 uint32_t pg_bw_tbl[2]; 2113 uint32_t pri_pg_tbl[1]; 2114}; 2115 2116/* Driver structure in LE */ 2117struct dcbx_pfc_feature { 2118#ifdef __BIG_ENDIAN 2119 uint8_t pri_en_bitmap; 2120 #define DCBX_PFC_PRI_0 0x01 2121 #define DCBX_PFC_PRI_1 0x02 2122 #define DCBX_PFC_PRI_2 0x04 2123 #define DCBX_PFC_PRI_3 0x08 2124 #define DCBX_PFC_PRI_4 0x10 2125 #define DCBX_PFC_PRI_5 0x20 2126 #define DCBX_PFC_PRI_6 0x40 2127 #define DCBX_PFC_PRI_7 0x80 2128 uint8_t pfc_caps; 2129 uint8_t reserved; 2130 uint8_t enabled; 2131#elif defined(__LITTLE_ENDIAN) 2132 uint8_t enabled; 2133 uint8_t reserved; 2134 uint8_t pfc_caps; 2135 uint8_t pri_en_bitmap; 2136 #define DCBX_PFC_PRI_0 0x01 2137 #define DCBX_PFC_PRI_1 0x02 2138 #define DCBX_PFC_PRI_2 0x04 2139 #define DCBX_PFC_PRI_3 0x08 2140 #define DCBX_PFC_PRI_4 0x10 2141 #define DCBX_PFC_PRI_5 0x20 2142 #define DCBX_PFC_PRI_6 0x40 2143 #define DCBX_PFC_PRI_7 0x80 2144#endif 2145}; 2146 2147struct dcbx_app_priority_entry { 2148#ifdef __BIG_ENDIAN 2149 uint16_t app_id; 2150 uint8_t pri_bitmap; 2151 uint8_t appBitfield; 2152 #define DCBX_APP_ENTRY_VALID 0x01 2153 #define DCBX_APP_ENTRY_SF_MASK 0x30 2154 #define DCBX_APP_ENTRY_SF_SHIFT 4 2155 #define DCBX_APP_SF_ETH_TYPE 0x10 2156 #define DCBX_APP_SF_PORT 0x20 2157#elif defined(__LITTLE_ENDIAN) 2158 uint8_t appBitfield; 2159 #define DCBX_APP_ENTRY_VALID 0x01 2160 #define DCBX_APP_ENTRY_SF_MASK 0x30 2161 #define DCBX_APP_ENTRY_SF_SHIFT 4 2162 #define DCBX_APP_SF_ETH_TYPE 0x10 2163 #define DCBX_APP_SF_PORT 0x20 2164 uint8_t pri_bitmap; 2165 uint16_t app_id; 2166#endif 2167}; 2168 2169 2170/* FW structure in BE */ 2171struct dcbx_app_priority_feature { 2172#ifdef __BIG_ENDIAN 2173 uint8_t reserved; 2174 uint8_t default_pri; 2175 uint8_t tc_supported; 2176 uint8_t enabled; 2177#elif defined(__LITTLE_ENDIAN) 2178 uint8_t enabled; 2179 uint8_t tc_supported; 2180 uint8_t default_pri; 2181 uint8_t reserved; 2182#endif 2183 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 2184}; 2185 2186/* FW structure in BE */ 2187struct dcbx_features { 2188 /* PG feature */ 2189 struct dcbx_ets_feature ets; 2190 /* PFC feature */ 2191 struct dcbx_pfc_feature pfc; 2192 /* APP feature */ 2193 struct dcbx_app_priority_feature app; 2194}; 2195 2196/* LLDP protocol parameters */ 2197/* FW structure in BE */ 2198struct lldp_params { 2199#ifdef __BIG_ENDIAN 2200 uint8_t msg_fast_tx_interval; 2201 uint8_t msg_tx_hold; 2202 uint8_t msg_tx_interval; 2203 uint8_t admin_status; 2204 #define LLDP_TX_ONLY 0x01 2205 #define LLDP_RX_ONLY 0x02 2206 #define LLDP_TX_RX 0x03 2207 #define LLDP_DISABLED 0x04 2208 uint8_t reserved1; 2209 uint8_t tx_fast; 2210 uint8_t tx_crd_max; 2211 uint8_t tx_crd; 2212#elif defined(__LITTLE_ENDIAN) 2213 uint8_t admin_status; 2214 #define LLDP_TX_ONLY 0x01 2215 #define LLDP_RX_ONLY 0x02 2216 #define LLDP_TX_RX 0x03 2217 #define LLDP_DISABLED 0x04 2218 uint8_t msg_tx_interval; 2219 uint8_t msg_tx_hold; 2220 uint8_t msg_fast_tx_interval; 2221 uint8_t tx_crd; 2222 uint8_t tx_crd_max; 2223 uint8_t tx_fast; 2224 uint8_t reserved1; 2225#endif 2226 #define REM_CHASSIS_ID_STAT_LEN 4 2227 #define REM_PORT_ID_STAT_LEN 4 2228 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 2229 uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 2230 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 2231 uint32_t peer_port_id[REM_PORT_ID_STAT_LEN]; 2232}; 2233 2234struct lldp_dcbx_stat { 2235 #define LOCAL_CHASSIS_ID_STAT_LEN 2 2236 #define LOCAL_PORT_ID_STAT_LEN 2 2237 /* Holds local Chassis ID 8B payload of constant subtype 4. */ 2238 uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 2239 /* Holds local Port ID 8B payload of constant subtype 3. */ 2240 uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN]; 2241 /* Number of DCBX frames transmitted. */ 2242 uint32_t num_tx_dcbx_pkts; 2243 /* Number of DCBX frames received. */ 2244 uint32_t num_rx_dcbx_pkts; 2245}; 2246 2247/* ADMIN MIB - DCBX local machine default configuration. */ 2248struct lldp_admin_mib { 2249 uint32_t ver_cfg_flags; 2250 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 2251 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 2252 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 2253 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 2254 #define DCBX_ETS_RECO_VALID 0x00000010 2255 #define DCBX_ETS_WILLING 0x00000020 2256 #define DCBX_PFC_WILLING 0x00000040 2257 #define DCBX_APP_WILLING 0x00000080 2258 #define DCBX_VERSION_CEE 0x00000100 2259 #define DCBX_VERSION_IEEE 0x00000200 2260 #define DCBX_DCBX_ENABLED 0x00000400 2261 #define DCBX_CEE_VERSION_MASK 0x0000f000 2262 #define DCBX_CEE_VERSION_SHIFT 12 2263 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 2264 #define DCBX_CEE_MAX_VERSION_SHIFT 16 2265 struct dcbx_features features; 2266}; 2267 2268/* REMOTE MIB - remote machine DCBX configuration. */ 2269struct lldp_remote_mib { 2270 uint32_t prefix_seq_num; 2271 uint32_t flags; 2272 #define DCBX_ETS_TLV_RX 0x00000001 2273 #define DCBX_PFC_TLV_RX 0x00000002 2274 #define DCBX_APP_TLV_RX 0x00000004 2275 #define DCBX_ETS_RX_ERROR 0x00000010 2276 #define DCBX_PFC_RX_ERROR 0x00000020 2277 #define DCBX_APP_RX_ERROR 0x00000040 2278 #define DCBX_ETS_REM_WILLING 0x00000100 2279 #define DCBX_PFC_REM_WILLING 0x00000200 2280 #define DCBX_APP_REM_WILLING 0x00000400 2281 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 2282 #define DCBX_REMOTE_MIB_VALID 0x00002000 2283 struct dcbx_features features; 2284 uint32_t suffix_seq_num; 2285}; 2286 2287/* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 2288struct lldp_local_mib { 2289 uint32_t prefix_seq_num; 2290 /* Indicates if there is mismatch with negotiation results. */ 2291 uint32_t error; 2292 #define DCBX_LOCAL_ETS_ERROR 0x00000001 2293 #define DCBX_LOCAL_PFC_ERROR 0x00000002 2294 #define DCBX_LOCAL_APP_ERROR 0x00000004 2295 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 2296 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 2297 #define DCBX_REMOTE_MIB_ERROR 0x00000040 2298 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 2299 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 2300 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 2301 struct dcbx_features features; 2302 uint32_t suffix_seq_num; 2303}; 2304 2305struct lldp_local_mib_ext { 2306 uint32_t prefix_seq_num; 2307 /* APP TLV extension - 16 more entries for negotiation results*/ 2308 struct dcbx_app_priority_entry app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL]; 2309 uint32_t suffix_seq_num; 2310}; 2311/***END OF DCBX STRUCTURES DECLARATIONS***/ 2312 2313/***********************************************************/ 2314/* Elink section */ 2315/***********************************************************/ 2316#define SHMEM_LINK_CONFIG_SIZE 2 2317struct shmem_lfa { 2318 uint32_t req_duplex; 2319 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff 2320 #define REQ_DUPLEX_PHY0_SHIFT 0 2321 #define REQ_DUPLEX_PHY1_MASK 0xffff0000 2322 #define REQ_DUPLEX_PHY1_SHIFT 16 2323 uint32_t req_flow_ctrl; 2324 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff 2325 #define REQ_FLOW_CTRL_PHY0_SHIFT 0 2326 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 2327 #define REQ_FLOW_CTRL_PHY1_SHIFT 16 2328 uint32_t req_line_speed; /* Also determine AutoNeg */ 2329 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff 2330 #define REQ_LINE_SPD_PHY0_SHIFT 0 2331 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 2332 #define REQ_LINE_SPD_PHY1_SHIFT 16 2333 uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; 2334 uint32_t additional_config; 2335 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff 2336 #define REQ_FC_AUTO_ADV0_SHIFT 0 2337 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 2338 uint32_t lfa_sts; 2339 #define LFA_LINK_FLAP_REASON_OFFSET 0 2340 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 2341 #define LFA_LINK_DOWN 0x1 2342 #define LFA_LOOPBACK_ENABLED 0x2 2343 #define LFA_DUPLEX_MISMATCH 0x3 2344 #define LFA_MFW_IS_TOO_OLD 0x4 2345 #define LFA_LINK_SPEED_MISMATCH 0x5 2346 #define LFA_FLOW_CTRL_MISMATCH 0x6 2347 #define LFA_SPEED_CAP_MISMATCH 0x7 2348 #define LFA_DCC_LFA_DISABLED 0x8 2349 #define LFA_EEE_MISMATCH 0x9 2350 2351 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 2352 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 2353 2354 #define LINK_FLAP_COUNT_OFFSET 16 2355 #define LINK_FLAP_COUNT_MASK 0x00ff0000 2356 2357 #define LFA_FLAGS_MASK 0xff000000 2358 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) 2359 2360}; 2361 2362struct shmem2_region { 2363 2364 uint32_t size; /* 0x0000 */ 2365 2366 uint32_t dcc_support; /* 0x0004 */ 2367 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 2368 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 2369 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 2370 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 2371 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 2372 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 2373 2374 uint32_t ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 2375 /* 2376 * For backwards compatibility, if the mf_cfg_addr does not exist 2377 * (the size filed is smaller than 0xc) the mf_cfg resides at the 2378 * end of struct shmem_region 2379 */ 2380 uint32_t mf_cfg_addr; /* 0x0010 */ 2381 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 2382 2383 struct fw_flr_mb flr_mb; /* 0x0014 */ 2384 uint32_t dcbx_lldp_params_offset; /* 0x0028 */ 2385 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 2386 uint32_t dcbx_neg_res_offset; /* 0x002c */ 2387 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 2388 uint32_t dcbx_remote_mib_offset; /* 0x0030 */ 2389 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 2390 /* 2391 * The other shmemX_base_addr holds the other path's shmem address 2392 * required for example in case of common phy init, or for path1 to know 2393 * the address of mcp debug trace which is located in offset from shmem 2394 * of path0 2395 */ 2396 uint32_t other_shmem_base_addr; /* 0x0034 */ 2397 uint32_t other_shmem2_base_addr; /* 0x0038 */ 2398 /* 2399 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 2400 * which were disabled/flred 2401 */ 2402 uint32_t mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 2403 2404 /* 2405 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 2406 * VFs 2407 */ 2408 uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 2409 2410 uint32_t dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 2411 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 2412 2413 /* 2414 * edebug_driver_if field is used to transfer messages between edebug 2415 * app to the driver through shmem2. 2416 * 2417 * message format: 2418 * bits 0-2 - function number / instance of driver to perform request 2419 * bits 3-5 - op code / is_ack? 2420 * bits 6-63 - data 2421 */ 2422 uint32_t edebug_driver_if[2]; /* 0x0068 */ 2423 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 2424 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 2425 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 2426 2427 uint32_t nvm_retain_bitmap_addr; /* 0x0070 */ 2428 2429 /* afex support of that driver */ 2430 uint32_t afex_driver_support; /* 0x0074 */ 2431 #define SHMEM_AFEX_VERSION_MASK 0x100f 2432 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 2433 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 2434 2435 /* driver receives addr in scratchpad to which it should respond */ 2436 uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX]; 2437 2438 /* 2439 * generic params from MCP to driver (value depends on the msg sent 2440 * to driver 2441 */ 2442 uint32_t afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ 2443 uint32_t afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ 2444 2445 uint32_t swim_base_addr; /* 0x0108 */ 2446 uint32_t swim_funcs; 2447 uint32_t swim_main_cb; 2448 2449 /* 2450 * bitmap notifying which VIF profiles stored in nvram are enabled by 2451 * switch 2452 */ 2453 uint32_t afex_profiles_enabled[2]; 2454 2455 /* generic flags controlled by the driver */ 2456 uint32_t drv_flags; 2457 #define DRV_FLAGS_DCB_CONFIGURED 0x0 2458 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 2459 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 2460 2461 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \ 2462 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \ 2463 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED)) 2464 /* Port offset*/ 2465 #define DRV_FLAGS_P0_OFFSET 0 2466 #define DRV_FLAGS_P1_OFFSET 16 2467 #define DRV_FLAGS_GET_PORT_OFFSET(_port) ((0 == _port) ? \ 2468 DRV_FLAGS_P0_OFFSET : \ 2469 DRV_FLAGS_P1_OFFSET) 2470 2471 #define DRV_FLAGS_GET_PORT_MASK(_port) (DRV_FLAGS_PORT_MASK << \ 2472 DRV_FLAGS_GET_PORT_OFFSET(_port)) 2473 2474 #define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port) (1 << ( \ 2475 (_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port))) 2476 2477 /* pointer to extended dev_info shared data copied from nvm image */ 2478 uint32_t extended_dev_info_shared_addr; 2479 uint32_t ncsi_oem_data_addr; 2480 2481 uint32_t sensor_data_addr; 2482 uint32_t buffer_block_addr; 2483 uint32_t sensor_data_req_update_interval; 2484 uint32_t temperature_in_half_celsius; 2485 uint32_t glob_struct_in_host; 2486 2487 uint32_t dcbx_neg_res_ext_offset; 2488 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 2489 2490 uint32_t drv_capabilities_flag[E2_FUNC_MAX]; 2491 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 2492 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 2493 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 2494 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 2495 2496 uint32_t extended_dev_info_shared_cfg_size; 2497 2498 uint32_t dcbx_en[PORT_MAX]; 2499 2500 /* The offset points to the multi threaded meta structure */ 2501 uint32_t multi_thread_data_offset; 2502 2503 /* address of DMAable host address holding values from the drivers */ 2504 uint32_t drv_info_host_addr_lo; 2505 uint32_t drv_info_host_addr_hi; 2506 2507 /* general values written by the MFW (such as current version) */ 2508 uint32_t drv_info_control; 2509 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff 2510 #define DRV_INFO_CONTROL_VER_SHIFT 0 2511 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 2512 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 2513 uint32_t ibft_host_addr; /* initialized by option ROM */ 2514 2515 struct eee_remote_vals eee_remote_vals[PORT_MAX]; 2516 uint32_t pf_allocation[E2_FUNC_MAX]; 2517 #define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */ 2518 #define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0 2519 2520 /* the status of EEE auto-negotiation 2521 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. 2522 * bits 19:16 the supported modes for EEE. 2523 * bits 23:20 the speeds advertised for EEE. 2524 * bits 27:24 the speeds the Link partner advertised for EEE. 2525 * The supported/adv. modes in bits 27:19 originate from the 2526 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 2527 * bit 28 when 1'b1 EEE was requested. 2528 * bit 29 when 1'b1 tx lpi was requested. 2529 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff 2530 * 30:29 are 2'b11. 2531 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as 2532 * value. When 1'b1 those bits contains a value times 16 microseconds. 2533 */ 2534 uint32_t eee_status[PORT_MAX]; 2535 #define SHMEM_EEE_TIMER_MASK 0x0000ffff 2536 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 2537 #define SHMEM_EEE_SUPPORTED_SHIFT 16 2538 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 2539 #define SHMEM_EEE_100M_ADV (1<<0) 2540 #define SHMEM_EEE_1G_ADV (1<<1) 2541 #define SHMEM_EEE_10G_ADV (1<<2) 2542 #define SHMEM_EEE_ADV_STATUS_SHIFT 20 2543 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 2544 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 2545 #define SHMEM_EEE_REQUESTED_BIT 0x10000000 2546 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 2547 #define SHMEM_EEE_ACTIVE_BIT 0x40000000 2548 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 2549 2550 uint32_t sizeof_port_stats; 2551 2552 /* Link Flap Avoidance */ 2553 uint32_t lfa_host_addr[PORT_MAX]; 2554 2555 /* External PHY temperature in deg C. */ 2556 uint32_t extphy_temps_in_celsius; 2557 #define EXTPHY1_TEMP_MASK 0x0000ffff 2558 #define EXTPHY1_TEMP_SHIFT 0 2559 2560 uint32_t ocdata_info_addr; /* Offset 0x148 */ 2561 uint32_t drv_func_info_addr; /* Offset 0x14C */ 2562 uint32_t drv_func_info_size; /* Offset 0x150 */ 2563 uint32_t link_attr_sync[PORT_MAX]; /* Offset 0x154 */ 2564 #define LINK_ATTR_SYNC_KR2_ENABLE (1<<0) 2565 2566 uint32_t ibft_host_addr_hi; /* Initialize by uEFI ROM */ 2567}; 2568 2569 2570struct emac_stats { 2571 uint32_t rx_stat_ifhcinoctets; 2572 uint32_t rx_stat_ifhcinbadoctets; 2573 uint32_t rx_stat_etherstatsfragments; 2574 uint32_t rx_stat_ifhcinucastpkts; 2575 uint32_t rx_stat_ifhcinmulticastpkts; 2576 uint32_t rx_stat_ifhcinbroadcastpkts; 2577 uint32_t rx_stat_dot3statsfcserrors; 2578 uint32_t rx_stat_dot3statsalignmenterrors; 2579 uint32_t rx_stat_dot3statscarriersenseerrors; 2580 uint32_t rx_stat_xonpauseframesreceived; 2581 uint32_t rx_stat_xoffpauseframesreceived; 2582 uint32_t rx_stat_maccontrolframesreceived; 2583 uint32_t rx_stat_xoffstateentered; 2584 uint32_t rx_stat_dot3statsframestoolong; 2585 uint32_t rx_stat_etherstatsjabbers; 2586 uint32_t rx_stat_etherstatsundersizepkts; 2587 uint32_t rx_stat_etherstatspkts64octets; 2588 uint32_t rx_stat_etherstatspkts65octetsto127octets; 2589 uint32_t rx_stat_etherstatspkts128octetsto255octets; 2590 uint32_t rx_stat_etherstatspkts256octetsto511octets; 2591 uint32_t rx_stat_etherstatspkts512octetsto1023octets; 2592 uint32_t rx_stat_etherstatspkts1024octetsto1522octets; 2593 uint32_t rx_stat_etherstatspktsover1522octets; 2594 2595 uint32_t rx_stat_falsecarriererrors; 2596 2597 uint32_t tx_stat_ifhcoutoctets; 2598 uint32_t tx_stat_ifhcoutbadoctets; 2599 uint32_t tx_stat_etherstatscollisions; 2600 uint32_t tx_stat_outxonsent; 2601 uint32_t tx_stat_outxoffsent; 2602 uint32_t tx_stat_flowcontroldone; 2603 uint32_t tx_stat_dot3statssinglecollisionframes; 2604 uint32_t tx_stat_dot3statsmultiplecollisionframes; 2605 uint32_t tx_stat_dot3statsdeferredtransmissions; 2606 uint32_t tx_stat_dot3statsexcessivecollisions; 2607 uint32_t tx_stat_dot3statslatecollisions; 2608 uint32_t tx_stat_ifhcoutucastpkts; 2609 uint32_t tx_stat_ifhcoutmulticastpkts; 2610 uint32_t tx_stat_ifhcoutbroadcastpkts; 2611 uint32_t tx_stat_etherstatspkts64octets; 2612 uint32_t tx_stat_etherstatspkts65octetsto127octets; 2613 uint32_t tx_stat_etherstatspkts128octetsto255octets; 2614 uint32_t tx_stat_etherstatspkts256octetsto511octets; 2615 uint32_t tx_stat_etherstatspkts512octetsto1023octets; 2616 uint32_t tx_stat_etherstatspkts1024octetsto1522octets; 2617 uint32_t tx_stat_etherstatspktsover1522octets; 2618 uint32_t tx_stat_dot3statsinternalmactransmiterrors; 2619}; 2620 2621 2622struct bmac1_stats { 2623 uint32_t tx_stat_gtpkt_lo; 2624 uint32_t tx_stat_gtpkt_hi; 2625 uint32_t tx_stat_gtxpf_lo; 2626 uint32_t tx_stat_gtxpf_hi; 2627 uint32_t tx_stat_gtfcs_lo; 2628 uint32_t tx_stat_gtfcs_hi; 2629 uint32_t tx_stat_gtmca_lo; 2630 uint32_t tx_stat_gtmca_hi; 2631 uint32_t tx_stat_gtbca_lo; 2632 uint32_t tx_stat_gtbca_hi; 2633 uint32_t tx_stat_gtfrg_lo; 2634 uint32_t tx_stat_gtfrg_hi; 2635 uint32_t tx_stat_gtovr_lo; 2636 uint32_t tx_stat_gtovr_hi; 2637 uint32_t tx_stat_gt64_lo; 2638 uint32_t tx_stat_gt64_hi; 2639 uint32_t tx_stat_gt127_lo; 2640 uint32_t tx_stat_gt127_hi; 2641 uint32_t tx_stat_gt255_lo; 2642 uint32_t tx_stat_gt255_hi; 2643 uint32_t tx_stat_gt511_lo; 2644 uint32_t tx_stat_gt511_hi; 2645 uint32_t tx_stat_gt1023_lo; 2646 uint32_t tx_stat_gt1023_hi; 2647 uint32_t tx_stat_gt1518_lo; 2648 uint32_t tx_stat_gt1518_hi; 2649 uint32_t tx_stat_gt2047_lo; 2650 uint32_t tx_stat_gt2047_hi; 2651 uint32_t tx_stat_gt4095_lo; 2652 uint32_t tx_stat_gt4095_hi; 2653 uint32_t tx_stat_gt9216_lo; 2654 uint32_t tx_stat_gt9216_hi; 2655 uint32_t tx_stat_gt16383_lo; 2656 uint32_t tx_stat_gt16383_hi; 2657 uint32_t tx_stat_gtmax_lo; 2658 uint32_t tx_stat_gtmax_hi; 2659 uint32_t tx_stat_gtufl_lo; 2660 uint32_t tx_stat_gtufl_hi; 2661 uint32_t tx_stat_gterr_lo; 2662 uint32_t tx_stat_gterr_hi; 2663 uint32_t tx_stat_gtbyt_lo; 2664 uint32_t tx_stat_gtbyt_hi; 2665 2666 uint32_t rx_stat_gr64_lo; 2667 uint32_t rx_stat_gr64_hi; 2668 uint32_t rx_stat_gr127_lo; 2669 uint32_t rx_stat_gr127_hi; 2670 uint32_t rx_stat_gr255_lo; 2671 uint32_t rx_stat_gr255_hi; 2672 uint32_t rx_stat_gr511_lo; 2673 uint32_t rx_stat_gr511_hi; 2674 uint32_t rx_stat_gr1023_lo; 2675 uint32_t rx_stat_gr1023_hi; 2676 uint32_t rx_stat_gr1518_lo; 2677 uint32_t rx_stat_gr1518_hi; 2678 uint32_t rx_stat_gr2047_lo; 2679 uint32_t rx_stat_gr2047_hi; 2680 uint32_t rx_stat_gr4095_lo; 2681 uint32_t rx_stat_gr4095_hi; 2682 uint32_t rx_stat_gr9216_lo; 2683 uint32_t rx_stat_gr9216_hi; 2684 uint32_t rx_stat_gr16383_lo; 2685 uint32_t rx_stat_gr16383_hi; 2686 uint32_t rx_stat_grmax_lo; 2687 uint32_t rx_stat_grmax_hi; 2688 uint32_t rx_stat_grpkt_lo; 2689 uint32_t rx_stat_grpkt_hi; 2690 uint32_t rx_stat_grfcs_lo; 2691 uint32_t rx_stat_grfcs_hi; 2692 uint32_t rx_stat_grmca_lo; 2693 uint32_t rx_stat_grmca_hi; 2694 uint32_t rx_stat_grbca_lo; 2695 uint32_t rx_stat_grbca_hi; 2696 uint32_t rx_stat_grxcf_lo; 2697 uint32_t rx_stat_grxcf_hi; 2698 uint32_t rx_stat_grxpf_lo; 2699 uint32_t rx_stat_grxpf_hi; 2700 uint32_t rx_stat_grxuo_lo; 2701 uint32_t rx_stat_grxuo_hi; 2702 uint32_t rx_stat_grjbr_lo; 2703 uint32_t rx_stat_grjbr_hi; 2704 uint32_t rx_stat_grovr_lo; 2705 uint32_t rx_stat_grovr_hi; 2706 uint32_t rx_stat_grflr_lo; 2707 uint32_t rx_stat_grflr_hi; 2708 uint32_t rx_stat_grmeg_lo; 2709 uint32_t rx_stat_grmeg_hi; 2710 uint32_t rx_stat_grmeb_lo; 2711 uint32_t rx_stat_grmeb_hi; 2712 uint32_t rx_stat_grbyt_lo; 2713 uint32_t rx_stat_grbyt_hi; 2714 uint32_t rx_stat_grund_lo; 2715 uint32_t rx_stat_grund_hi; 2716 uint32_t rx_stat_grfrg_lo; 2717 uint32_t rx_stat_grfrg_hi; 2718 uint32_t rx_stat_grerb_lo; 2719 uint32_t rx_stat_grerb_hi; 2720 uint32_t rx_stat_grfre_lo; 2721 uint32_t rx_stat_grfre_hi; 2722 uint32_t rx_stat_gripj_lo; 2723 uint32_t rx_stat_gripj_hi; 2724}; 2725 2726struct bmac2_stats { 2727 uint32_t tx_stat_gtpk_lo; /* gtpok */ 2728 uint32_t tx_stat_gtpk_hi; /* gtpok */ 2729 uint32_t tx_stat_gtxpf_lo; /* gtpf */ 2730 uint32_t tx_stat_gtxpf_hi; /* gtpf */ 2731 uint32_t tx_stat_gtpp_lo; /* NEW BMAC2 */ 2732 uint32_t tx_stat_gtpp_hi; /* NEW BMAC2 */ 2733 uint32_t tx_stat_gtfcs_lo; 2734 uint32_t tx_stat_gtfcs_hi; 2735 uint32_t tx_stat_gtuca_lo; /* NEW BMAC2 */ 2736 uint32_t tx_stat_gtuca_hi; /* NEW BMAC2 */ 2737 uint32_t tx_stat_gtmca_lo; 2738 uint32_t tx_stat_gtmca_hi; 2739 uint32_t tx_stat_gtbca_lo; 2740 uint32_t tx_stat_gtbca_hi; 2741 uint32_t tx_stat_gtovr_lo; 2742 uint32_t tx_stat_gtovr_hi; 2743 uint32_t tx_stat_gtfrg_lo; 2744 uint32_t tx_stat_gtfrg_hi; 2745 uint32_t tx_stat_gtpkt1_lo; /* gtpkt */ 2746 uint32_t tx_stat_gtpkt1_hi; /* gtpkt */ 2747 uint32_t tx_stat_gt64_lo; 2748 uint32_t tx_stat_gt64_hi; 2749 uint32_t tx_stat_gt127_lo; 2750 uint32_t tx_stat_gt127_hi; 2751 uint32_t tx_stat_gt255_lo; 2752 uint32_t tx_stat_gt255_hi; 2753 uint32_t tx_stat_gt511_lo; 2754 uint32_t tx_stat_gt511_hi; 2755 uint32_t tx_stat_gt1023_lo; 2756 uint32_t tx_stat_gt1023_hi; 2757 uint32_t tx_stat_gt1518_lo; 2758 uint32_t tx_stat_gt1518_hi; 2759 uint32_t tx_stat_gt2047_lo; 2760 uint32_t tx_stat_gt2047_hi; 2761 uint32_t tx_stat_gt4095_lo; 2762 uint32_t tx_stat_gt4095_hi; 2763 uint32_t tx_stat_gt9216_lo; 2764 uint32_t tx_stat_gt9216_hi; 2765 uint32_t tx_stat_gt16383_lo; 2766 uint32_t tx_stat_gt16383_hi; 2767 uint32_t tx_stat_gtmax_lo; 2768 uint32_t tx_stat_gtmax_hi; 2769 uint32_t tx_stat_gtufl_lo; 2770 uint32_t tx_stat_gtufl_hi; 2771 uint32_t tx_stat_gterr_lo; 2772 uint32_t tx_stat_gterr_hi; 2773 uint32_t tx_stat_gtbyt_lo; 2774 uint32_t tx_stat_gtbyt_hi; 2775 2776 uint32_t rx_stat_gr64_lo; 2777 uint32_t rx_stat_gr64_hi; 2778 uint32_t rx_stat_gr127_lo; 2779 uint32_t rx_stat_gr127_hi; 2780 uint32_t rx_stat_gr255_lo; 2781 uint32_t rx_stat_gr255_hi; 2782 uint32_t rx_stat_gr511_lo; 2783 uint32_t rx_stat_gr511_hi; 2784 uint32_t rx_stat_gr1023_lo; 2785 uint32_t rx_stat_gr1023_hi; 2786 uint32_t rx_stat_gr1518_lo; 2787 uint32_t rx_stat_gr1518_hi; 2788 uint32_t rx_stat_gr2047_lo; 2789 uint32_t rx_stat_gr2047_hi; 2790 uint32_t rx_stat_gr4095_lo; 2791 uint32_t rx_stat_gr4095_hi; 2792 uint32_t rx_stat_gr9216_lo; 2793 uint32_t rx_stat_gr9216_hi; 2794 uint32_t rx_stat_gr16383_lo; 2795 uint32_t rx_stat_gr16383_hi; 2796 uint32_t rx_stat_grmax_lo; 2797 uint32_t rx_stat_grmax_hi; 2798 uint32_t rx_stat_grpkt_lo; 2799 uint32_t rx_stat_grpkt_hi; 2800 uint32_t rx_stat_grfcs_lo; 2801 uint32_t rx_stat_grfcs_hi; 2802 uint32_t rx_stat_gruca_lo; 2803 uint32_t rx_stat_gruca_hi; 2804 uint32_t rx_stat_grmca_lo; 2805 uint32_t rx_stat_grmca_hi; 2806 uint32_t rx_stat_grbca_lo; 2807 uint32_t rx_stat_grbca_hi; 2808 uint32_t rx_stat_grxpf_lo; /* grpf */ 2809 uint32_t rx_stat_grxpf_hi; /* grpf */ 2810 uint32_t rx_stat_grpp_lo; 2811 uint32_t rx_stat_grpp_hi; 2812 uint32_t rx_stat_grxuo_lo; /* gruo */ 2813 uint32_t rx_stat_grxuo_hi; /* gruo */ 2814 uint32_t rx_stat_grjbr_lo; 2815 uint32_t rx_stat_grjbr_hi; 2816 uint32_t rx_stat_grovr_lo; 2817 uint32_t rx_stat_grovr_hi; 2818 uint32_t rx_stat_grxcf_lo; /* grcf */ 2819 uint32_t rx_stat_grxcf_hi; /* grcf */ 2820 uint32_t rx_stat_grflr_lo; 2821 uint32_t rx_stat_grflr_hi; 2822 uint32_t rx_stat_grpok_lo; 2823 uint32_t rx_stat_grpok_hi; 2824 uint32_t rx_stat_grmeg_lo; 2825 uint32_t rx_stat_grmeg_hi; 2826 uint32_t rx_stat_grmeb_lo; 2827 uint32_t rx_stat_grmeb_hi; 2828 uint32_t rx_stat_grbyt_lo; 2829 uint32_t rx_stat_grbyt_hi; 2830 uint32_t rx_stat_grund_lo; 2831 uint32_t rx_stat_grund_hi; 2832 uint32_t rx_stat_grfrg_lo; 2833 uint32_t rx_stat_grfrg_hi; 2834 uint32_t rx_stat_grerb_lo; /* grerrbyt */ 2835 uint32_t rx_stat_grerb_hi; /* grerrbyt */ 2836 uint32_t rx_stat_grfre_lo; /* grfrerr */ 2837 uint32_t rx_stat_grfre_hi; /* grfrerr */ 2838 uint32_t rx_stat_gripj_lo; 2839 uint32_t rx_stat_gripj_hi; 2840}; 2841 2842struct mstat_stats { 2843 struct { 2844 /* OTE MSTAT on E3 has a bug where this register's contents are 2845 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 2846 */ 2847 uint32_t tx_gtxpok_lo; 2848 uint32_t tx_gtxpok_hi; 2849 uint32_t tx_gtxpf_lo; 2850 uint32_t tx_gtxpf_hi; 2851 uint32_t tx_gtxpp_lo; 2852 uint32_t tx_gtxpp_hi; 2853 uint32_t tx_gtfcs_lo; 2854 uint32_t tx_gtfcs_hi; 2855 uint32_t tx_gtuca_lo; 2856 uint32_t tx_gtuca_hi; 2857 uint32_t tx_gtmca_lo; 2858 uint32_t tx_gtmca_hi; 2859 uint32_t tx_gtgca_lo; 2860 uint32_t tx_gtgca_hi; 2861 uint32_t tx_gtpkt_lo; 2862 uint32_t tx_gtpkt_hi; 2863 uint32_t tx_gt64_lo; 2864 uint32_t tx_gt64_hi; 2865 uint32_t tx_gt127_lo; 2866 uint32_t tx_gt127_hi; 2867 uint32_t tx_gt255_lo; 2868 uint32_t tx_gt255_hi; 2869 uint32_t tx_gt511_lo; 2870 uint32_t tx_gt511_hi; 2871 uint32_t tx_gt1023_lo; 2872 uint32_t tx_gt1023_hi; 2873 uint32_t tx_gt1518_lo; 2874 uint32_t tx_gt1518_hi; 2875 uint32_t tx_gt2047_lo; 2876 uint32_t tx_gt2047_hi; 2877 uint32_t tx_gt4095_lo; 2878 uint32_t tx_gt4095_hi; 2879 uint32_t tx_gt9216_lo; 2880 uint32_t tx_gt9216_hi; 2881 uint32_t tx_gt16383_lo; 2882 uint32_t tx_gt16383_hi; 2883 uint32_t tx_gtufl_lo; 2884 uint32_t tx_gtufl_hi; 2885 uint32_t tx_gterr_lo; 2886 uint32_t tx_gterr_hi; 2887 uint32_t tx_gtbyt_lo; 2888 uint32_t tx_gtbyt_hi; 2889 uint32_t tx_collisions_lo; 2890 uint32_t tx_collisions_hi; 2891 uint32_t tx_singlecollision_lo; 2892 uint32_t tx_singlecollision_hi; 2893 uint32_t tx_multiplecollisions_lo; 2894 uint32_t tx_multiplecollisions_hi; 2895 uint32_t tx_deferred_lo; 2896 uint32_t tx_deferred_hi; 2897 uint32_t tx_excessivecollisions_lo; 2898 uint32_t tx_excessivecollisions_hi; 2899 uint32_t tx_latecollisions_lo; 2900 uint32_t tx_latecollisions_hi; 2901 } stats_tx; 2902 2903 struct { 2904 uint32_t rx_gr64_lo; 2905 uint32_t rx_gr64_hi; 2906 uint32_t rx_gr127_lo; 2907 uint32_t rx_gr127_hi; 2908 uint32_t rx_gr255_lo; 2909 uint32_t rx_gr255_hi; 2910 uint32_t rx_gr511_lo; 2911 uint32_t rx_gr511_hi; 2912 uint32_t rx_gr1023_lo; 2913 uint32_t rx_gr1023_hi; 2914 uint32_t rx_gr1518_lo; 2915 uint32_t rx_gr1518_hi; 2916 uint32_t rx_gr2047_lo; 2917 uint32_t rx_gr2047_hi; 2918 uint32_t rx_gr4095_lo; 2919 uint32_t rx_gr4095_hi; 2920 uint32_t rx_gr9216_lo; 2921 uint32_t rx_gr9216_hi; 2922 uint32_t rx_gr16383_lo; 2923 uint32_t rx_gr16383_hi; 2924 uint32_t rx_grpkt_lo; 2925 uint32_t rx_grpkt_hi; 2926 uint32_t rx_grfcs_lo; 2927 uint32_t rx_grfcs_hi; 2928 uint32_t rx_gruca_lo; 2929 uint32_t rx_gruca_hi; 2930 uint32_t rx_grmca_lo; 2931 uint32_t rx_grmca_hi; 2932 uint32_t rx_grbca_lo; 2933 uint32_t rx_grbca_hi; 2934 uint32_t rx_grxpf_lo; 2935 uint32_t rx_grxpf_hi; 2936 uint32_t rx_grxpp_lo; 2937 uint32_t rx_grxpp_hi; 2938 uint32_t rx_grxuo_lo; 2939 uint32_t rx_grxuo_hi; 2940 uint32_t rx_grovr_lo; 2941 uint32_t rx_grovr_hi; 2942 uint32_t rx_grxcf_lo; 2943 uint32_t rx_grxcf_hi; 2944 uint32_t rx_grflr_lo; 2945 uint32_t rx_grflr_hi; 2946 uint32_t rx_grpok_lo; 2947 uint32_t rx_grpok_hi; 2948 uint32_t rx_grbyt_lo; 2949 uint32_t rx_grbyt_hi; 2950 uint32_t rx_grund_lo; 2951 uint32_t rx_grund_hi; 2952 uint32_t rx_grfrg_lo; 2953 uint32_t rx_grfrg_hi; 2954 uint32_t rx_grerb_lo; 2955 uint32_t rx_grerb_hi; 2956 uint32_t rx_grfre_lo; 2957 uint32_t rx_grfre_hi; 2958 2959 uint32_t rx_alignmenterrors_lo; 2960 uint32_t rx_alignmenterrors_hi; 2961 uint32_t rx_falsecarrier_lo; 2962 uint32_t rx_falsecarrier_hi; 2963 uint32_t rx_llfcmsgcnt_lo; 2964 uint32_t rx_llfcmsgcnt_hi; 2965 } stats_rx; 2966}; 2967 2968union mac_stats { 2969 struct emac_stats emac_stats; 2970 struct bmac1_stats bmac1_stats; 2971 struct bmac2_stats bmac2_stats; 2972 struct mstat_stats mstat_stats; 2973}; 2974 2975 2976struct mac_stx { 2977 /* in_bad_octets */ 2978 uint32_t rx_stat_ifhcinbadoctets_hi; 2979 uint32_t rx_stat_ifhcinbadoctets_lo; 2980 2981 /* out_bad_octets */ 2982 uint32_t tx_stat_ifhcoutbadoctets_hi; 2983 uint32_t tx_stat_ifhcoutbadoctets_lo; 2984 2985 /* crc_receive_errors */ 2986 uint32_t rx_stat_dot3statsfcserrors_hi; 2987 uint32_t rx_stat_dot3statsfcserrors_lo; 2988 /* alignment_errors */ 2989 uint32_t rx_stat_dot3statsalignmenterrors_hi; 2990 uint32_t rx_stat_dot3statsalignmenterrors_lo; 2991 /* carrier_sense_errors */ 2992 uint32_t rx_stat_dot3statscarriersenseerrors_hi; 2993 uint32_t rx_stat_dot3statscarriersenseerrors_lo; 2994 /* false_carrier_detections */ 2995 uint32_t rx_stat_falsecarriererrors_hi; 2996 uint32_t rx_stat_falsecarriererrors_lo; 2997 2998 /* runt_packets_received */ 2999 uint32_t rx_stat_etherstatsundersizepkts_hi; 3000 uint32_t rx_stat_etherstatsundersizepkts_lo; 3001 /* jabber_packets_received */ 3002 uint32_t rx_stat_dot3statsframestoolong_hi; 3003 uint32_t rx_stat_dot3statsframestoolong_lo; 3004 3005 /* error_runt_packets_received */ 3006 uint32_t rx_stat_etherstatsfragments_hi; 3007 uint32_t rx_stat_etherstatsfragments_lo; 3008 /* error_jabber_packets_received */ 3009 uint32_t rx_stat_etherstatsjabbers_hi; 3010 uint32_t rx_stat_etherstatsjabbers_lo; 3011 3012 /* control_frames_received */ 3013 uint32_t rx_stat_maccontrolframesreceived_hi; 3014 uint32_t rx_stat_maccontrolframesreceived_lo; 3015 uint32_t rx_stat_mac_xpf_hi; 3016 uint32_t rx_stat_mac_xpf_lo; 3017 uint32_t rx_stat_mac_xcf_hi; 3018 uint32_t rx_stat_mac_xcf_lo; 3019 3020 /* xoff_state_entered */ 3021 uint32_t rx_stat_xoffstateentered_hi; 3022 uint32_t rx_stat_xoffstateentered_lo; 3023 /* pause_xon_frames_received */ 3024 uint32_t rx_stat_xonpauseframesreceived_hi; 3025 uint32_t rx_stat_xonpauseframesreceived_lo; 3026 /* pause_xoff_frames_received */ 3027 uint32_t rx_stat_xoffpauseframesreceived_hi; 3028 uint32_t rx_stat_xoffpauseframesreceived_lo; 3029 /* pause_xon_frames_transmitted */ 3030 uint32_t tx_stat_outxonsent_hi; 3031 uint32_t tx_stat_outxonsent_lo; 3032 /* pause_xoff_frames_transmitted */ 3033 uint32_t tx_stat_outxoffsent_hi; 3034 uint32_t tx_stat_outxoffsent_lo; 3035 /* flow_control_done */ 3036 uint32_t tx_stat_flowcontroldone_hi; 3037 uint32_t tx_stat_flowcontroldone_lo; 3038 3039 /* ether_stats_collisions */ 3040 uint32_t tx_stat_etherstatscollisions_hi; 3041 uint32_t tx_stat_etherstatscollisions_lo; 3042 /* single_collision_transmit_frames */ 3043 uint32_t tx_stat_dot3statssinglecollisionframes_hi; 3044 uint32_t tx_stat_dot3statssinglecollisionframes_lo; 3045 /* multiple_collision_transmit_frames */ 3046 uint32_t tx_stat_dot3statsmultiplecollisionframes_hi; 3047 uint32_t tx_stat_dot3statsmultiplecollisionframes_lo; 3048 /* deferred_transmissions */ 3049 uint32_t tx_stat_dot3statsdeferredtransmissions_hi; 3050 uint32_t tx_stat_dot3statsdeferredtransmissions_lo; 3051 /* excessive_collision_frames */ 3052 uint32_t tx_stat_dot3statsexcessivecollisions_hi; 3053 uint32_t tx_stat_dot3statsexcessivecollisions_lo; 3054 /* late_collision_frames */ 3055 uint32_t tx_stat_dot3statslatecollisions_hi; 3056 uint32_t tx_stat_dot3statslatecollisions_lo; 3057 3058 /* frames_transmitted_64_bytes */ 3059 uint32_t tx_stat_etherstatspkts64octets_hi; 3060 uint32_t tx_stat_etherstatspkts64octets_lo; 3061 /* frames_transmitted_65_127_bytes */ 3062 uint32_t tx_stat_etherstatspkts65octetsto127octets_hi; 3063 uint32_t tx_stat_etherstatspkts65octetsto127octets_lo; 3064 /* frames_transmitted_128_255_bytes */ 3065 uint32_t tx_stat_etherstatspkts128octetsto255octets_hi; 3066 uint32_t tx_stat_etherstatspkts128octetsto255octets_lo; 3067 /* frames_transmitted_256_511_bytes */ 3068 uint32_t tx_stat_etherstatspkts256octetsto511octets_hi; 3069 uint32_t tx_stat_etherstatspkts256octetsto511octets_lo; 3070 /* frames_transmitted_512_1023_bytes */ 3071 uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi; 3072 uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo; 3073 /* frames_transmitted_1024_1522_bytes */ 3074 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi; 3075 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo; 3076 /* frames_transmitted_1523_9022_bytes */ 3077 uint32_t tx_stat_etherstatspktsover1522octets_hi; 3078 uint32_t tx_stat_etherstatspktsover1522octets_lo; 3079 uint32_t tx_stat_mac_2047_hi; 3080 uint32_t tx_stat_mac_2047_lo; 3081 uint32_t tx_stat_mac_4095_hi; 3082 uint32_t tx_stat_mac_4095_lo; 3083 uint32_t tx_stat_mac_9216_hi; 3084 uint32_t tx_stat_mac_9216_lo; 3085 uint32_t tx_stat_mac_16383_hi; 3086 uint32_t tx_stat_mac_16383_lo; 3087 3088 /* internal_mac_transmit_errors */ 3089 uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi; 3090 uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo; 3091 3092 /* if_out_discards */ 3093 uint32_t tx_stat_mac_ufl_hi; 3094 uint32_t tx_stat_mac_ufl_lo; 3095}; 3096 3097 3098#define MAC_STX_IDX_MAX 2 3099 3100struct host_port_stats { 3101 uint32_t host_port_stats_counter; 3102 3103 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 3104 3105 uint32_t brb_drop_hi; 3106 uint32_t brb_drop_lo; 3107 3108 uint32_t not_used; /* obsolete as of MFW 7.2.1 */ 3109 3110 uint32_t pfc_frames_tx_hi; 3111 uint32_t pfc_frames_tx_lo; 3112 uint32_t pfc_frames_rx_hi; 3113 uint32_t pfc_frames_rx_lo; 3114 3115 uint32_t eee_lpi_count_hi; 3116 uint32_t eee_lpi_count_lo; 3117}; 3118 3119 3120struct host_func_stats { 3121 uint32_t host_func_stats_start; 3122 3123 uint32_t total_bytes_received_hi; 3124 uint32_t total_bytes_received_lo; 3125 3126 uint32_t total_bytes_transmitted_hi; 3127 uint32_t total_bytes_transmitted_lo; 3128 3129 uint32_t total_unicast_packets_received_hi; 3130 uint32_t total_unicast_packets_received_lo; 3131 3132 uint32_t total_multicast_packets_received_hi; 3133 uint32_t total_multicast_packets_received_lo; 3134 3135 uint32_t total_broadcast_packets_received_hi; 3136 uint32_t total_broadcast_packets_received_lo; 3137 3138 uint32_t total_unicast_packets_transmitted_hi; 3139 uint32_t total_unicast_packets_transmitted_lo; 3140 3141 uint32_t total_multicast_packets_transmitted_hi; 3142 uint32_t total_multicast_packets_transmitted_lo; 3143 3144 uint32_t total_broadcast_packets_transmitted_hi; 3145 uint32_t total_broadcast_packets_transmitted_lo; 3146 3147 uint32_t valid_bytes_received_hi; 3148 uint32_t valid_bytes_received_lo; 3149 3150 uint32_t host_func_stats_end; 3151}; 3152 3153/* VIC definitions */ 3154#define VICSTATST_UIF_INDEX 2 3155 3156/* 3157 * stats collected for afex. 3158 * NOTE: structure is exactly as expected to be received by the switch. 3159 * order must remain exactly as is unless protocol changes ! 3160 */ 3161struct afex_stats { 3162 uint32_t tx_unicast_frames_hi; 3163 uint32_t tx_unicast_frames_lo; 3164 uint32_t tx_unicast_bytes_hi; 3165 uint32_t tx_unicast_bytes_lo; 3166 uint32_t tx_multicast_frames_hi; 3167 uint32_t tx_multicast_frames_lo; 3168 uint32_t tx_multicast_bytes_hi; 3169 uint32_t tx_multicast_bytes_lo; 3170 uint32_t tx_broadcast_frames_hi; 3171 uint32_t tx_broadcast_frames_lo; 3172 uint32_t tx_broadcast_bytes_hi; 3173 uint32_t tx_broadcast_bytes_lo; 3174 uint32_t tx_frames_discarded_hi; 3175 uint32_t tx_frames_discarded_lo; 3176 uint32_t tx_frames_dropped_hi; 3177 uint32_t tx_frames_dropped_lo; 3178 3179 uint32_t rx_unicast_frames_hi; 3180 uint32_t rx_unicast_frames_lo; 3181 uint32_t rx_unicast_bytes_hi; 3182 uint32_t rx_unicast_bytes_lo; 3183 uint32_t rx_multicast_frames_hi; 3184 uint32_t rx_multicast_frames_lo; 3185 uint32_t rx_multicast_bytes_hi; 3186 uint32_t rx_multicast_bytes_lo; 3187 uint32_t rx_broadcast_frames_hi; 3188 uint32_t rx_broadcast_frames_lo; 3189 uint32_t rx_broadcast_bytes_hi; 3190 uint32_t rx_broadcast_bytes_lo; 3191 uint32_t rx_frames_discarded_hi; 3192 uint32_t rx_frames_discarded_lo; 3193 uint32_t rx_frames_dropped_hi; 3194 uint32_t rx_frames_dropped_lo; 3195}; 3196 3197/* To maintain backward compatibility between FW and drivers, new elements */ 3198/* should be added to the end of the structure. */ 3199 3200/* Per Port Statistics */ 3201struct port_info { 3202 uint32_t size; /* size of this structure (i.e. sizeof(port_info)) */ 3203 uint32_t enabled; /* 0 =Disabled, 1= Enabled */ 3204 uint32_t link_speed; /* multiplier of 100Mb */ 3205 uint32_t wol_support; /* WoL Support (i.e. Non-Zero if WOL supported ) */ 3206 uint32_t flow_control; /* 802.3X Flow Ctrl. 0=off 1=RX 2=TX 3=RX&TX.*/ 3207 uint32_t flex10; /* Flex10 mode enabled. non zero = yes */ 3208 uint32_t rx_drops; /* RX Discards. Counters roll over, never reset */ 3209 uint32_t rx_errors; /* RX Errors. Physical Port Stats L95, All PFs and NC-SI. 3210 This is flagged by Consumer as an error. */ 3211 uint32_t rx_uncast_lo; /* RX Unicast Packets. Free running counters: */ 3212 uint32_t rx_uncast_hi; /* RX Unicast Packets. Free running counters: */ 3213 uint32_t rx_mcast_lo; /* RX Multicast Packets */ 3214 uint32_t rx_mcast_hi; /* RX Multicast Packets */ 3215 uint32_t rx_bcast_lo; /* RX Broadcast Packets */ 3216 uint32_t rx_bcast_hi; /* RX Broadcast Packets */ 3217 uint32_t tx_uncast_lo; /* TX Unicast Packets */ 3218 uint32_t tx_uncast_hi; /* TX Unicast Packets */ 3219 uint32_t tx_mcast_lo; /* TX Multicast Packets */ 3220 uint32_t tx_mcast_hi; /* TX Multicast Packets */ 3221 uint32_t tx_bcast_lo; /* TX Broadcast Packets */ 3222 uint32_t tx_bcast_hi; /* TX Broadcast Packets */ 3223 uint32_t tx_errors; /* TX Errors */ 3224 uint32_t tx_discards; /* TX Discards */ 3225 uint32_t rx_frames_lo; /* RX Frames received */ 3226 uint32_t rx_frames_hi; /* RX Frames received */ 3227 uint32_t rx_bytes_lo; /* RX Bytes received */ 3228 uint32_t rx_bytes_hi; /* RX Bytes received */ 3229 uint32_t tx_frames_lo; /* TX Frames sent */ 3230 uint32_t tx_frames_hi; /* TX Frames sent */ 3231 uint32_t tx_bytes_lo; /* TX Bytes sent */ 3232 uint32_t tx_bytes_hi; /* TX Bytes sent */ 3233 uint32_t link_status; /* Port P Link Status. 1:0 bit for port enabled. 3234 1:1 bit for link good, 3235 2:1 Set if link changed between last poll. */ 3236 uint32_t tx_pfc_frames_lo; /* PFC Frames sent. */ 3237 uint32_t tx_pfc_frames_hi; /* PFC Frames sent. */ 3238 uint32_t rx_pfc_frames_lo; /* PFC Frames Received. */ 3239 uint32_t rx_pfc_frames_hi; /* PFC Frames Received. */ 3240}; 3241 3242 3243#define BCM_5710_FW_MAJOR_VERSION 7 3244#define BCM_5710_FW_MINOR_VERSION 8 3245#define BCM_5710_FW_REVISION_VERSION 51 3246#define BCM_5710_FW_ENGINEERING_VERSION 0 3247#define BCM_5710_FW_COMPILE_FLAGS 1 3248 3249 3250/* 3251 * attention bits $$KEEP_ENDIANNESS$$ 3252 */ 3253struct atten_sp_status_block 3254{ 3255 uint32_t attn_bits /* 16 bit of attention signal lines */; 3256 uint32_t attn_bits_ack /* 16 bit of attention signal ack */; 3257 uint8_t status_block_id /* status block id */; 3258 uint8_t reserved0 /* resreved for padding */; 3259 uint16_t attn_bits_index /* attention bits running index */; 3260 uint32_t reserved1 /* resreved for padding */; 3261}; 3262 3263 3264/* 3265 * The eth aggregative context of Cstorm 3266 */ 3267struct cstorm_eth_ag_context 3268{ 3269 uint32_t __reserved0[10]; 3270}; 3271 3272 3273/* 3274 * dmae command structure 3275 */ 3276struct dmae_command 3277{ 3278 uint32_t opcode; 3279#define DMAE_COMMAND_SRC (0x1<<0) /* BitField opcode Whether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The source is the GRC. */ 3280#define DMAE_COMMAND_SRC_SHIFT 0 3281#define DMAE_COMMAND_DST (0x3<<1) /* BitField opcode The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */ 3282#define DMAE_COMMAND_DST_SHIFT 1 3283#define DMAE_COMMAND_C_DST (0x1<<3) /* BitField opcode The destination of the completion: 0-PCIe 1-GRC */ 3284#define DMAE_COMMAND_C_DST_SHIFT 3 3285#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) /* BitField opcode Whether to write a completion word to the completion destination: 0-Do not write a completion word 1-Write the completion word */ 3286#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 3287#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) /* BitField opcode Whether to write a CRC word to the completion destination 0-Do not write a CRC word 1-Write a CRC word */ 3288#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 3289#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) /* BitField opcode The CRC word should be taken from the DMAE GRC space from address 9+X, where X is the value in these bits. */ 3290#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 3291#define DMAE_COMMAND_ENDIANITY (0x3<<9) /* BitField opcode swapping mode. */ 3292#define DMAE_COMMAND_ENDIANITY_SHIFT 9 3293#define DMAE_COMMAND_PORT (0x1<<11) /* BitField opcode Which network port ID to present to the PCI request interface */ 3294#define DMAE_COMMAND_PORT_SHIFT 11 3295#define DMAE_COMMAND_CRC_RESET (0x1<<12) /* BitField opcode reset crc result */ 3296#define DMAE_COMMAND_CRC_RESET_SHIFT 12 3297#define DMAE_COMMAND_SRC_RESET (0x1<<13) /* BitField opcode reset source address in next go */ 3298#define DMAE_COMMAND_SRC_RESET_SHIFT 13 3299#define DMAE_COMMAND_DST_RESET (0x1<<14) /* BitField opcode reset dest address in next go */ 3300#define DMAE_COMMAND_DST_RESET_SHIFT 14 3301#define DMAE_COMMAND_E1HVN (0x3<<15) /* BitField opcode vnic number E2 and onwards source vnic */ 3302#define DMAE_COMMAND_E1HVN_SHIFT 15 3303#define DMAE_COMMAND_DST_VN (0x3<<17) /* BitField opcode E2 and onwards dest vnic */ 3304#define DMAE_COMMAND_DST_VN_SHIFT 17 3305#define DMAE_COMMAND_C_FUNC (0x1<<19) /* BitField opcode E2 and onwards which function gets the completion src_vn(e1hvn)-0 dst_vn-1 */ 3306#define DMAE_COMMAND_C_FUNC_SHIFT 19 3307#define DMAE_COMMAND_ERR_POLICY (0x3<<20) /* BitField opcode E2 and onwards what to do when theres a completion and a PCI error regular-0 error indication-1 no completion-2 */ 3308#define DMAE_COMMAND_ERR_POLICY_SHIFT 20 3309#define DMAE_COMMAND_RESERVED0 (0x3FF<<22) /* BitField opcode */ 3310#define DMAE_COMMAND_RESERVED0_SHIFT 22 3311 uint32_t src_addr_lo /* source address low/grc address */; 3312 uint32_t src_addr_hi /* source address hi */; 3313 uint32_t dst_addr_lo /* dest address low/grc address */; 3314 uint32_t dst_addr_hi /* dest address hi */; 3315#if defined(__BIG_ENDIAN) 3316 uint16_t opcode_iov; 3317#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */ 3318#define DMAE_COMMAND_SRC_VFID_SHIFT 0 3319#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */ 3320#define DMAE_COMMAND_SRC_VFPF_SHIFT 6 3321#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3322#define DMAE_COMMAND_RESERVED1_SHIFT 7 3323#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */ 3324#define DMAE_COMMAND_DST_VFID_SHIFT 8 3325#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */ 3326#define DMAE_COMMAND_DST_VFPF_SHIFT 14 3327#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3328#define DMAE_COMMAND_RESERVED2_SHIFT 15 3329 uint16_t len /* copy length */; 3330#elif defined(__LITTLE_ENDIAN) 3331 uint16_t len /* copy length */; 3332 uint16_t opcode_iov; 3333#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */ 3334#define DMAE_COMMAND_SRC_VFID_SHIFT 0 3335#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */ 3336#define DMAE_COMMAND_SRC_VFPF_SHIFT 6 3337#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3338#define DMAE_COMMAND_RESERVED1_SHIFT 7 3339#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */ 3340#define DMAE_COMMAND_DST_VFID_SHIFT 8 3341#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */ 3342#define DMAE_COMMAND_DST_VFPF_SHIFT 14 3343#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3344#define DMAE_COMMAND_RESERVED2_SHIFT 15 3345#endif 3346 uint32_t comp_addr_lo /* completion address low/grc address */; 3347 uint32_t comp_addr_hi /* completion address hi */; 3348 uint32_t comp_val /* value to write to completion address */; 3349 uint32_t crc32 /* crc32 result */; 3350 uint32_t crc32_c /* crc32_c result */; 3351#if defined(__BIG_ENDIAN) 3352 uint16_t crc16_c /* crc16_c result */; 3353 uint16_t crc16 /* crc16 result */; 3354#elif defined(__LITTLE_ENDIAN) 3355 uint16_t crc16 /* crc16 result */; 3356 uint16_t crc16_c /* crc16_c result */; 3357#endif 3358#if defined(__BIG_ENDIAN) 3359 uint16_t reserved3; 3360 uint16_t crc_t10 /* crc_t10 result */; 3361#elif defined(__LITTLE_ENDIAN) 3362 uint16_t crc_t10 /* crc_t10 result */; 3363 uint16_t reserved3; 3364#endif 3365#if defined(__BIG_ENDIAN) 3366 uint16_t xsum8 /* checksum8 result */; 3367 uint16_t xsum16 /* checksum16 result */; 3368#elif defined(__LITTLE_ENDIAN) 3369 uint16_t xsum16 /* checksum16 result */; 3370 uint16_t xsum8 /* checksum8 result */; 3371#endif 3372}; 3373 3374 3375/* 3376 * common data for all protocols 3377 */ 3378struct doorbell_hdr 3379{ 3380 uint8_t header; 3381#define DOORBELL_HDR_RX (0x1<<0) /* BitField header 1 for rx doorbell, 0 for tx doorbell */ 3382#define DOORBELL_HDR_RX_SHIFT 0 3383#define DOORBELL_HDR_DB_TYPE (0x1<<1) /* BitField header 0 for normal doorbell, 1 for advertise wnd doorbell */ 3384#define DOORBELL_HDR_DB_TYPE_SHIFT 1 3385#define DOORBELL_HDR_DPM_SIZE (0x3<<2) /* BitField header rdma tx only: DPM transaction size specifier (64/128/256/512 bytes) */ 3386#define DOORBELL_HDR_DPM_SIZE_SHIFT 2 3387#define DOORBELL_HDR_CONN_TYPE (0xF<<4) /* BitField header connection type */ 3388#define DOORBELL_HDR_CONN_TYPE_SHIFT 4 3389}; 3390 3391/* 3392 * Ethernet doorbell 3393 */ 3394struct eth_tx_doorbell 3395{ 3396#if defined(__BIG_ENDIAN) 3397 uint16_t npackets /* number of data bytes that were added in the doorbell */; 3398 uint8_t params; 3399#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ 3400#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3401#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ 3402#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3403#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */ 3404#define ETH_TX_DOORBELL_SPARE_SHIFT 7 3405 struct doorbell_hdr hdr; 3406#elif defined(__LITTLE_ENDIAN) 3407 struct doorbell_hdr hdr; 3408 uint8_t params; 3409#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ 3410#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3411#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ 3412#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3413#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */ 3414#define ETH_TX_DOORBELL_SPARE_SHIFT 7 3415 uint16_t npackets /* number of data bytes that were added in the doorbell */; 3416#endif 3417}; 3418 3419 3420/* 3421 * 3 lines. status block $$KEEP_ENDIANNESS$$ 3422 */ 3423struct hc_status_block_e1x 3424{ 3425 uint16_t index_values[HC_SB_MAX_INDICES_E1X] /* indices reported by cstorm */; 3426 uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */; 3427 uint32_t rsrv[11]; 3428}; 3429 3430/* 3431 * host status block 3432 */ 3433struct host_hc_status_block_e1x 3434{ 3435 struct hc_status_block_e1x sb /* fast path indices */; 3436}; 3437 3438 3439/* 3440 * 3 lines. status block $$KEEP_ENDIANNESS$$ 3441 */ 3442struct hc_status_block_e2 3443{ 3444 uint16_t index_values[HC_SB_MAX_INDICES_E2] /* indices reported by cstorm */; 3445 uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */; 3446 uint32_t reserved[11]; 3447}; 3448 3449/* 3450 * host status block 3451 */ 3452struct host_hc_status_block_e2 3453{ 3454 struct hc_status_block_e2 sb /* fast path indices */; 3455}; 3456 3457 3458/* 3459 * 5 lines. slow-path status block $$KEEP_ENDIANNESS$$ 3460 */ 3461struct hc_sp_status_block 3462{ 3463 uint16_t index_values[HC_SP_SB_MAX_INDICES] /* indices reported by cstorm */; 3464 uint16_t running_index /* Status Block running index */; 3465 uint16_t rsrv; 3466 uint32_t rsrv1; 3467}; 3468 3469/* 3470 * host status block 3471 */ 3472struct host_sp_status_block 3473{ 3474 struct atten_sp_status_block atten_status_block /* attention bits section */; 3475 struct hc_sp_status_block sp_sb /* slow path indices */; 3476}; 3477 3478 3479/* 3480 * IGU driver acknowledgment register 3481 */ 3482struct igu_ack_register 3483{ 3484#if defined(__BIG_ENDIAN) 3485 uint16_t sb_id_and_flags; 3486#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */ 3487#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3488#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ 3489#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3490#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */ 3491#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3492#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ 3493#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3494#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */ 3495#define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3496 uint16_t status_block_index /* status block index acknowledgement */; 3497#elif defined(__LITTLE_ENDIAN) 3498 uint16_t status_block_index /* status block index acknowledgement */; 3499 uint16_t sb_id_and_flags; 3500#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */ 3501#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3502#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ 3503#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3504#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */ 3505#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3506#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ 3507#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3508#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */ 3509#define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3510#endif 3511}; 3512 3513 3514/* 3515 * IGU driver acknowledgement register 3516 */ 3517struct igu_backward_compatible 3518{ 3519 uint32_t sb_id_and_flags; 3520#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /* BitField sb_id_and_flags */ 3521#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 3522#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /* BitField sb_id_and_flags */ 3523#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 3524#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ 3525#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 3526#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* BitField sb_id_and_flags if set, acknowledges status block index */ 3527#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 3528#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ 3529#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 3530#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /* BitField sb_id_and_flags */ 3531#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 3532 uint32_t reserved_2; 3533}; 3534 3535 3536/* 3537 * IGU driver acknowledgement register 3538 */ 3539struct igu_regular 3540{ 3541 uint32_t sb_id_and_flags; 3542#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) /* BitField sb_id_and_flags */ 3543#define IGU_REGULAR_SB_INDEX_SHIFT 0 3544#define IGU_REGULAR_RESERVED0 (0x1<<20) /* BitField sb_id_and_flags */ 3545#define IGU_REGULAR_RESERVED0_SHIFT 20 3546#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 21-23 (use enum igu_seg_access) */ 3547#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 3548#define IGU_REGULAR_BUPDATE (0x1<<24) /* BitField sb_id_and_flags */ 3549#define IGU_REGULAR_BUPDATE_SHIFT 24 3550#define IGU_REGULAR_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop (use enum igu_int_cmd) */ 3551#define IGU_REGULAR_ENABLE_INT_SHIFT 25 3552#define IGU_REGULAR_RESERVED_1 (0x1<<27) /* BitField sb_id_and_flags */ 3553#define IGU_REGULAR_RESERVED_1_SHIFT 27 3554#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* BitField sb_id_and_flags */ 3555#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 3556#define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags */ 3557#define IGU_REGULAR_CLEANUP_SET_SHIFT 30 3558#define IGU_REGULAR_BCLEANUP (0x1<<31) /* BitField sb_id_and_flags */ 3559#define IGU_REGULAR_BCLEANUP_SHIFT 31 3560 uint32_t reserved_2; 3561}; 3562 3563/* 3564 * IGU driver acknowledgement register 3565 */ 3566union igu_consprod_reg 3567{ 3568 struct igu_regular regular; 3569 struct igu_backward_compatible backward_compatible; 3570}; 3571 3572 3573/* 3574 * Igu control commands 3575 */ 3576enum igu_ctrl_cmd 3577{ 3578 IGU_CTRL_CMD_TYPE_RD, 3579 IGU_CTRL_CMD_TYPE_WR, 3580 MAX_IGU_CTRL_CMD}; 3581 3582 3583/* 3584 * Control register for the IGU command register 3585 */ 3586struct igu_ctrl_reg 3587{ 3588 uint32_t ctrl_data; 3589#define IGU_CTRL_REG_ADDRESS (0xFFF<<0) /* BitField ctrl_data */ 3590#define IGU_CTRL_REG_ADDRESS_SHIFT 0 3591#define IGU_CTRL_REG_FID (0x7F<<12) /* BitField ctrl_data */ 3592#define IGU_CTRL_REG_FID_SHIFT 12 3593#define IGU_CTRL_REG_RESERVED (0x1<<19) /* BitField ctrl_data */ 3594#define IGU_CTRL_REG_RESERVED_SHIFT 19 3595#define IGU_CTRL_REG_TYPE (0x1<<20) /* BitField ctrl_data (use enum igu_ctrl_cmd) */ 3596#define IGU_CTRL_REG_TYPE_SHIFT 20 3597#define IGU_CTRL_REG_UNUSED (0x7FF<<21) /* BitField ctrl_data */ 3598#define IGU_CTRL_REG_UNUSED_SHIFT 21 3599}; 3600 3601 3602/* 3603 * Igu interrupt command 3604 */ 3605enum igu_int_cmd 3606{ 3607 IGU_INT_ENABLE, 3608 IGU_INT_DISABLE, 3609 IGU_INT_NOP, 3610 IGU_INT_NOP2, 3611 MAX_IGU_INT_CMD}; 3612 3613 3614/* 3615 * Igu segments 3616 */ 3617enum igu_seg_access 3618{ 3619 IGU_SEG_ACCESS_NORM, 3620 IGU_SEG_ACCESS_DEF, 3621 IGU_SEG_ACCESS_ATTN, 3622 MAX_IGU_SEG_ACCESS}; 3623 3624 3625/* 3626 * Parser parsing flags field 3627 */ 3628struct parsing_flags 3629{ 3630 uint16_t flags; 3631#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags 0=non-unicast, 1=unicast (use enum prs_flags_eth_addr_type) */ 3632#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 3633#define PARSING_FLAGS_VLAN (0x1<<1) /* BitField flagscontext flags 0 or 1 */ 3634#define PARSING_FLAGS_VLAN_SHIFT 1 3635#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) /* BitField flagscontext flags 0 or 1 */ 3636#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 3637#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags 0=un-known, 1=Ipv4, 2=Ipv6,3=LLC SNAP un-known. LLC SNAP here refers only to LLC/SNAP packets that do not have Ipv4 or Ipv6 above them. Ipv4 and Ipv6 indications are even if they are over LLC/SNAP and not directly over Ethernet (use enum prs_flags_over_eth) */ 3638#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 3639#define PARSING_FLAGS_IP_OPTIONS (0x1<<5) /* BitField flagscontext flags 0=no IP options / extension headers. 1=IP options / extension header exist */ 3640#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 3641#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) /* BitField flagscontext flags 0=non-fragmented, 1=fragmented */ 3642#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 3643#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) /* BitField flagscontext flags 0=un-known, 1=TCP, 2=UDP (use enum prs_flags_over_ip) */ 3644#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 3645#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) /* BitField flagscontext flags 0=packet with data, 1=pure-ACK (use enum prs_flags_ack_type) */ 3646#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 3647#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) /* BitField flagscontext flags 0=no TCP options. 1=TCP options */ 3648#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 3649#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* BitField flagscontext flags According to the TCP header options parsing */ 3650#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 3651#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* BitField flagscontext flags connection match in searcher indication */ 3652#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 3653#define PARSING_FLAGS_LLC_SNAP (0x1<<13) /* BitField flagscontext flags LLC SNAP indication */ 3654#define PARSING_FLAGS_LLC_SNAP_SHIFT 13 3655#define PARSING_FLAGS_RESERVED0 (0x3<<14) /* BitField flagscontext flags */ 3656#define PARSING_FLAGS_RESERVED0_SHIFT 14 3657}; 3658 3659 3660/* 3661 * Parsing flags for TCP ACK type 3662 */ 3663enum prs_flags_ack_type 3664{ 3665 PRS_FLAG_PUREACK_PIGGY, 3666 PRS_FLAG_PUREACK_PURE, 3667 MAX_PRS_FLAGS_ACK_TYPE}; 3668 3669 3670/* 3671 * Parsing flags for Ethernet address type 3672 */ 3673enum prs_flags_eth_addr_type 3674{ 3675 PRS_FLAG_ETHTYPE_NON_UNICAST, 3676 PRS_FLAG_ETHTYPE_UNICAST, 3677 MAX_PRS_FLAGS_ETH_ADDR_TYPE}; 3678 3679 3680/* 3681 * Parsing flags for over-ethernet protocol 3682 */ 3683enum prs_flags_over_eth 3684{ 3685 PRS_FLAG_OVERETH_UNKNOWN, 3686 PRS_FLAG_OVERETH_IPV4, 3687 PRS_FLAG_OVERETH_IPV6, 3688 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 3689 MAX_PRS_FLAGS_OVER_ETH}; 3690 3691 3692/* 3693 * Parsing flags for over-IP protocol 3694 */ 3695enum prs_flags_over_ip 3696{ 3697 PRS_FLAG_OVERIP_UNKNOWN, 3698 PRS_FLAG_OVERIP_TCP, 3699 PRS_FLAG_OVERIP_UDP, 3700 MAX_PRS_FLAGS_OVER_IP}; 3701 3702 3703/* 3704 * SDM operation gen command (generate aggregative interrupt) 3705 */ 3706struct sdm_op_gen 3707{ 3708 uint32_t command; 3709#define SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* BitField commandcomp_param and comp_type thread ID/aggr interrupt number/counter depending on the completion type */ 3710#define SDM_OP_GEN_COMP_PARAM_SHIFT 0 3711#define SDM_OP_GEN_COMP_TYPE (0x7<<5) /* BitField commandcomp_param and comp_type Direct messages to CM / PCI switch are not supported in operation_gen completion */ 3712#define SDM_OP_GEN_COMP_TYPE_SHIFT 5 3713#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* BitField commandcomp_param and comp_type bit index in aggregated interrupt vector */ 3714#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 3715#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* BitField commandcomp_param and comp_type */ 3716#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 3717#define SDM_OP_GEN_RESERVED (0x7FFF<<17) /* BitField commandcomp_param and comp_type */ 3718#define SDM_OP_GEN_RESERVED_SHIFT 17 3719}; 3720 3721 3722/* 3723 * Timers connection context 3724 */ 3725struct timers_block_context 3726{ 3727 uint32_t __reserved_0 /* data of client 0 of the timers block*/; 3728 uint32_t __reserved_1 /* data of client 1 of the timers block*/; 3729 uint32_t __reserved_2 /* data of client 2 of the timers block*/; 3730 uint32_t flags; 3731#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* BitField flagscontext flags number of active timers running */ 3732#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 3733#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* BitField flagscontext flags flag: is connection valid (should be set by driver to 1 in toe/iscsi connections) */ 3734#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 3735#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) /* BitField flagscontext flags */ 3736#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 3737}; 3738 3739 3740/* 3741 * The eth aggregative context of Tstorm 3742 */ 3743struct tstorm_eth_ag_context 3744{ 3745 uint32_t __reserved0[14]; 3746}; 3747 3748 3749/* 3750 * The eth aggregative context of Ustorm 3751 */ 3752struct ustorm_eth_ag_context 3753{ 3754 uint32_t __reserved0; 3755#if defined(__BIG_ENDIAN) 3756 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 3757 uint8_t __reserved2; 3758 uint16_t __reserved1; 3759#elif defined(__LITTLE_ENDIAN) 3760 uint16_t __reserved1; 3761 uint8_t __reserved2; 3762 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 3763#endif 3764 uint32_t __reserved3[6]; 3765}; 3766 3767 3768/* 3769 * The eth aggregative context of Xstorm 3770 */ 3771struct xstorm_eth_ag_context 3772{ 3773 uint32_t reserved0; 3774#if defined(__BIG_ENDIAN) 3775 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 3776 uint8_t reserved2; 3777 uint16_t reserved1; 3778#elif defined(__LITTLE_ENDIAN) 3779 uint16_t reserved1; 3780 uint8_t reserved2; 3781 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 3782#endif 3783 uint32_t reserved3[30]; 3784}; 3785 3786 3787/* 3788 * doorbell message sent to the chip 3789 */ 3790struct doorbell 3791{ 3792#if defined(__BIG_ENDIAN) 3793 uint16_t zero_fill2 /* driver must zero this field! */; 3794 uint8_t zero_fill1 /* driver must zero this field! */; 3795 struct doorbell_hdr header; 3796#elif defined(__LITTLE_ENDIAN) 3797 struct doorbell_hdr header; 3798 uint8_t zero_fill1 /* driver must zero this field! */; 3799 uint16_t zero_fill2 /* driver must zero this field! */; 3800#endif 3801}; 3802 3803 3804/* 3805 * doorbell message sent to the chip 3806 */ 3807struct doorbell_set_prod 3808{ 3809#if defined(__BIG_ENDIAN) 3810 uint16_t prod /* Producer index to be set */; 3811 uint8_t zero_fill1 /* driver must zero this field! */; 3812 struct doorbell_hdr header; 3813#elif defined(__LITTLE_ENDIAN) 3814 struct doorbell_hdr header; 3815 uint8_t zero_fill1 /* driver must zero this field! */; 3816 uint16_t prod /* Producer index to be set */; 3817#endif 3818}; 3819 3820 3821struct regpair 3822{ 3823 uint32_t lo /* low word for reg-pair */; 3824 uint32_t hi /* high word for reg-pair */; 3825}; 3826 3827 3828struct regpair_native 3829{ 3830 uint32_t lo /* low word for reg-pair */; 3831 uint32_t hi /* high word for reg-pair */; 3832}; 3833 3834 3835/* 3836 * Classify rule opcodes in E2/E3 3837 */ 3838enum classify_rule 3839{ 3840 CLASSIFY_RULE_OPCODE_MAC /* Add/remove a MAC address */, 3841 CLASSIFY_RULE_OPCODE_VLAN /* Add/remove a VLAN */, 3842 CLASSIFY_RULE_OPCODE_PAIR /* Add/remove a MAC-VLAN pair */, 3843 MAX_CLASSIFY_RULE}; 3844 3845 3846/* 3847 * Classify rule types in E2/E3 3848 */ 3849enum classify_rule_action_type 3850{ 3851 CLASSIFY_RULE_REMOVE, 3852 CLASSIFY_RULE_ADD, 3853 MAX_CLASSIFY_RULE_ACTION_TYPE}; 3854 3855 3856/* 3857 * client init ramrod data $$KEEP_ENDIANNESS$$ 3858 */ 3859struct client_init_general_data 3860{ 3861 uint8_t client_id /* client_id */; 3862 uint8_t statistics_counter_id /* statistics counter id */; 3863 uint8_t statistics_en_flg /* statistics en flg */; 3864 uint8_t is_fcoe_flg /* is this an fcoe connection. (1 bit is used) */; 3865 uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */; 3866 uint8_t sp_client_id /* the slow path rings client Id. */; 3867 uint16_t mtu /* Host MTU from client config */; 3868 uint8_t statistics_zero_flg /* if set FW will reset the statistic counter of this client */; 3869 uint8_t func_id /* PCI function ID (0-71) */; 3870 uint8_t cos /* The connection cos, if applicable */; 3871 uint8_t traffic_type; 3872 uint32_t reserved0; 3873}; 3874 3875 3876/* 3877 * client init rx data $$KEEP_ENDIANNESS$$ 3878 */ 3879struct client_init_rx_data 3880{ 3881 uint8_t tpa_en; 3882#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* BitField tpa_entpa_enable tpa enable flg ipv4 */ 3883#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 3884#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* BitField tpa_entpa_enable tpa enable flg ipv6 */ 3885#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 3886#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* BitField tpa_entpa_enable tpa mode (LRO or GRO) (use enum tpa_mode) */ 3887#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 3888#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* BitField tpa_entpa_enable */ 3889#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 3890 uint8_t vmqueue_mode_en_flg /* If set, working in VMQueue mode (always consume one sge) */; 3891 uint8_t extra_data_over_sgl_en_flg /* if set, put over sgl data from end of input message */; 3892 uint8_t cache_line_alignment_log_size /* The log size of cache line alignment in bytes. Must be a power of 2. */; 3893 uint8_t enable_dynamic_hc /* If set, dynamic HC is enabled */; 3894 uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */; 3895 uint8_t client_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this client rx producers */; 3896 uint8_t drop_ip_cs_err_flg /* If set, this client drops packets with IP checksum error */; 3897 uint8_t drop_tcp_cs_err_flg /* If set, this client drops packets with TCP checksum error */; 3898 uint8_t drop_ttl0_flg /* If set, this client drops packets with TTL=0 */; 3899 uint8_t drop_udp_cs_err_flg /* If set, this client drops packets with UDP checksum error */; 3900 uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client */; 3901 uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client */; 3902 uint8_t status_block_id /* rx status block id */; 3903 uint8_t rx_sb_index_number /* status block indices */; 3904 uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */; 3905 uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */; 3906 uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */; 3907 uint16_t max_bytes_on_bd /* Maximum bytes that can be placed on a BD. The BD allocated size should include 2 more bytes (ip alignment) and alignment size (in case the address is not aligned) */; 3908 uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */; 3909 uint8_t approx_mcast_engine_id /* In Everest2, if is_approx_mcast is set, this field specified which approximate multicast engine is associate with this client */; 3910 uint8_t rss_engine_id /* In Everest2, if rss_mode is set, this field specified which RSS engine is associate with this client */; 3911 struct regpair bd_page_base /* BD page base address at the host */; 3912 struct regpair sge_page_base /* SGE page base address at the host */; 3913 struct regpair cqe_page_base /* Completion queue base address */; 3914 uint8_t is_leading_rss; 3915 uint8_t is_approx_mcast; 3916 uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */; 3917 uint16_t state; 3918#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* BitField staterx filters state drop all unicast packets */ 3919#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 3920#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* BitField staterx filters state accept all unicast packets (subject to vlan) */ 3921#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 3922#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField staterx filters state accept all unmatched unicast packets (subject to vlan) */ 3923#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3924#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* BitField staterx filters state drop all multicast packets */ 3925#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 3926#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* BitField staterx filters state accept all multicast packets (subject to vlan) */ 3927#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 3928#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* BitField staterx filters state accept all broadcast packets (subject to vlan) */ 3929#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 3930#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* BitField staterx filters state accept packets matched only by MAC (without checking vlan) */ 3931#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 3932#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /* BitField staterx filters state */ 3933#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 3934 uint16_t cqe_pause_thr_low /* number of remaining cqes under which, we send pause message */; 3935 uint16_t cqe_pause_thr_high /* number of remaining cqes above which, we send un-pause message */; 3936 uint16_t bd_pause_thr_low /* number of remaining bds under which, we send pause message */; 3937 uint16_t bd_pause_thr_high /* number of remaining bds above which, we send un-pause message */; 3938 uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */; 3939 uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */; 3940 uint16_t rx_cos_mask /* the bits that will be set on pfc/ safc paket whith will be genratet when this ring is full. for regular flow control set this to 1 */; 3941 uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */; 3942 uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */; 3943 uint32_t reserved6[2]; 3944}; 3945 3946/* 3947 * client init tx data $$KEEP_ENDIANNESS$$ 3948 */ 3949struct client_init_tx_data 3950{ 3951 uint8_t enforce_security_flg /* if set, security checks will be made for this connection */; 3952 uint8_t tx_status_block_id /* the number of status block to update */; 3953 uint8_t tx_sb_index_number /* the index to use inside the status block */; 3954 uint8_t tss_leading_client_id /* client ID of the leading TSS client, for TX classification source knock out */; 3955 uint8_t tx_switching_flg /* if set, tx switching will be done to packets on this connection */; 3956 uint8_t anti_spoofing_flg /* if set, anti spoofing check will be done to packets on this connection */; 3957 uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */; 3958 struct regpair tx_bd_page_base /* BD page base address at the host for TxBdCons */; 3959 uint16_t state; 3960#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* BitField statetx filters state accept all unicast packets (subject to vlan) */ 3961#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 3962#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* BitField statetx filters state accept all multicast packets (subject to vlan) */ 3963#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 3964#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* BitField statetx filters state accept all broadcast packets (subject to vlan) */ 3965#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 3966#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* BitField statetx filters state accept packets matched only by MAC (without checking vlan) */ 3967#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 3968#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /* BitField statetx filters state */ 3969#define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4 3970 uint8_t default_vlan_flg /* is default vlan valid for this client. */; 3971 uint8_t force_default_pri_flg /* if set, force default priority */; 3972 uint8_t tunnel_lso_inc_ip_id /* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header */; 3973 uint8_t refuse_outband_vlan_flg /* if set, the FW will not add outband vlan on packet (even if will exist on BD). */; 3974 uint8_t tunnel_non_lso_pcsum_location /* In case of non-Lso encapsulated packets with L4 checksum offload, the pseudo checksum location - on packet or on BD. */; 3975 uint8_t tunnel_non_lso_outer_ip_csum_location /* In case of non-Lso encapsulated packets with outer L3 ip checksum offload, the pseudo checksum location - on packet or on BD. */; 3976}; 3977 3978/* 3979 * client init ramrod data $$KEEP_ENDIANNESS$$ 3980 */ 3981struct client_init_ramrod_data 3982{ 3983 struct client_init_general_data general /* client init general data */; 3984 struct client_init_rx_data rx /* client init rx data */; 3985 struct client_init_tx_data tx /* client init tx data */; 3986}; 3987 3988 3989/* 3990 * client update ramrod data $$KEEP_ENDIANNESS$$ 3991 */ 3992struct client_update_ramrod_data 3993{ 3994 uint8_t client_id /* the client to update */; 3995 uint8_t func_id /* PCI function ID this client belongs to (0-71) */; 3996 uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client, will be change according to change flag */; 3997 uint8_t inner_vlan_removal_change_flg /* If set, inner VLAN removal flag will be set according to the enable flag */; 3998 uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client, will be change according to change flag */; 3999 uint8_t outer_vlan_removal_change_flg /* If set, outer VLAN removal flag will be set according to the enable flag */; 4000 uint8_t anti_spoofing_enable_flg /* If set, anti spoofing is enabled for this client, will be change according to change flag */; 4001 uint8_t anti_spoofing_change_flg /* If set, anti spoofing flag will be set according to anti spoofing flag */; 4002 uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */; 4003 uint8_t activate_change_flg /* If set, activate_flg will be checked */; 4004 uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */; 4005 uint8_t default_vlan_enable_flg; 4006 uint8_t default_vlan_change_flg; 4007 uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */; 4008 uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */; 4009 uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */; 4010 uint8_t silent_vlan_change_flg; 4011 uint8_t refuse_outband_vlan_flg /* If set, the FW will not add outband vlan on packet (even if will exist on BD). */; 4012 uint8_t refuse_outband_vlan_change_flg /* If set, refuse_outband_vlan_flg will be updated. */; 4013 uint8_t tx_switching_flg /* If set, tx switching will be done to packets on this connection. */; 4014 uint8_t tx_switching_change_flg /* If set, tx_switching_flg will be updated. */; 4015 uint32_t reserved1; 4016 uint32_t echo /* echo value to be sent to driver on event ring */; 4017}; 4018 4019 4020/* 4021 * The eth storm context of Cstorm 4022 */ 4023struct cstorm_eth_st_context 4024{ 4025 uint32_t __reserved0[4]; 4026}; 4027 4028 4029struct double_regpair 4030{ 4031 uint32_t regpair0_lo /* low word for reg-pair0 */; 4032 uint32_t regpair0_hi /* high word for reg-pair0 */; 4033 uint32_t regpair1_lo /* low word for reg-pair1 */; 4034 uint32_t regpair1_hi /* high word for reg-pair1 */; 4035}; 4036 4037 4038/* 4039 * Ethernet address typesm used in ethernet tx BDs 4040 */ 4041enum eth_addr_type 4042{ 4043 UNKNOWN_ADDRESS, 4044 UNICAST_ADDRESS, 4045 MULTICAST_ADDRESS, 4046 BROADCAST_ADDRESS, 4047 MAX_ETH_ADDR_TYPE}; 4048 4049 4050/* 4051 * $$KEEP_ENDIANNESS$$ 4052 */ 4053struct eth_classify_cmd_header 4054{ 4055 uint8_t cmd_general_data; 4056#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ 4057#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 4058#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ 4059#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 4060#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* BitField cmd_general_data command opcode for MAC/VLAN/PAIR (use enum classify_rule) */ 4061#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 4062#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* BitField cmd_general_data (use enum classify_rule_action_type) */ 4063#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 4064#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* BitField cmd_general_data */ 4065#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 4066 uint8_t func_id /* the function id */; 4067 uint8_t client_id; 4068 uint8_t reserved1; 4069}; 4070 4071 4072/* 4073 * header for eth classification config ramrod $$KEEP_ENDIANNESS$$ 4074 */ 4075struct eth_classify_header 4076{ 4077 uint8_t rule_cnt /* number of rules in classification config ramrod */; 4078 uint8_t reserved0; 4079 uint16_t reserved1; 4080 uint32_t echo /* echo value to be sent to driver on event ring */; 4081}; 4082 4083 4084/* 4085 * Command for adding/removing a MAC classification rule $$KEEP_ENDIANNESS$$ 4086 */ 4087struct eth_classify_mac_cmd 4088{ 4089 struct eth_classify_cmd_header header; 4090 uint16_t reserved0; 4091 uint16_t inner_mac; 4092 uint16_t mac_lsb; 4093 uint16_t mac_mid; 4094 uint16_t mac_msb; 4095 uint16_t reserved1; 4096}; 4097 4098 4099/* 4100 * Command for adding/removing a MAC-VLAN pair classification rule $$KEEP_ENDIANNESS$$ 4101 */ 4102struct eth_classify_pair_cmd 4103{ 4104 struct eth_classify_cmd_header header; 4105 uint16_t reserved0; 4106 uint16_t inner_mac; 4107 uint16_t mac_lsb; 4108 uint16_t mac_mid; 4109 uint16_t mac_msb; 4110 uint16_t vlan; 4111}; 4112 4113 4114/* 4115 * Command for adding/removing a VLAN classification rule $$KEEP_ENDIANNESS$$ 4116 */ 4117struct eth_classify_vlan_cmd 4118{ 4119 struct eth_classify_cmd_header header; 4120 uint32_t reserved0; 4121 uint32_t reserved1; 4122 uint16_t reserved2; 4123 uint16_t vlan; 4124}; 4125 4126/* 4127 * union for eth classification rule $$KEEP_ENDIANNESS$$ 4128 */ 4129union eth_classify_rule_cmd 4130{ 4131 struct eth_classify_mac_cmd mac; 4132 struct eth_classify_vlan_cmd vlan; 4133 struct eth_classify_pair_cmd pair; 4134}; 4135 4136/* 4137 * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$ 4138 */ 4139struct eth_classify_rules_ramrod_data 4140{ 4141 struct eth_classify_header header; 4142 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 4143}; 4144 4145 4146/* 4147 * The data contain client ID need to the ramrod $$KEEP_ENDIANNESS$$ 4148 */ 4149struct eth_common_ramrod_data 4150{ 4151 uint32_t client_id /* id of this client. (5 bits are used) */; 4152 uint32_t reserved1; 4153}; 4154 4155 4156/* 4157 * The eth storm context of Ustorm 4158 */ 4159struct ustorm_eth_st_context 4160{ 4161 uint32_t reserved0[52]; 4162}; 4163 4164/* 4165 * The eth storm context of Tstorm 4166 */ 4167struct tstorm_eth_st_context 4168{ 4169 uint32_t __reserved0[28]; 4170}; 4171 4172/* 4173 * The eth storm context of Xstorm 4174 */ 4175struct xstorm_eth_st_context 4176{ 4177 uint32_t reserved0[60]; 4178}; 4179 4180/* 4181 * Ethernet connection context 4182 */ 4183struct eth_context 4184{ 4185 struct ustorm_eth_st_context ustorm_st_context /* Ustorm storm context */; 4186 struct tstorm_eth_st_context tstorm_st_context /* Tstorm storm context */; 4187 struct xstorm_eth_ag_context xstorm_ag_context /* Xstorm aggregative context */; 4188 struct tstorm_eth_ag_context tstorm_ag_context /* Tstorm aggregative context */; 4189 struct cstorm_eth_ag_context cstorm_ag_context /* Cstorm aggregative context */; 4190 struct ustorm_eth_ag_context ustorm_ag_context /* Ustorm aggregative context */; 4191 struct timers_block_context timers_context /* Timers block context */; 4192 struct xstorm_eth_st_context xstorm_st_context /* Xstorm storm context */; 4193 struct cstorm_eth_st_context cstorm_st_context /* Cstorm storm context */; 4194}; 4195 4196 4197/* 4198 * union for sgl and raw data. 4199 */ 4200union eth_sgl_or_raw_data 4201{ 4202 uint16_t sgl[8] /* Scatter-gather list of SGEs used by this packet. This list includes the indices of the SGEs. */; 4203 uint32_t raw_data[4] /* raw data from Tstorm to the driver. */; 4204}; 4205 4206/* 4207 * eth FP end aggregation CQE parameters struct $$KEEP_ENDIANNESS$$ 4208 */ 4209struct eth_end_agg_rx_cqe 4210{ 4211 uint8_t type_error_flags; 4212#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */ 4213#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 4214#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */ 4215#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 4216#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* BitField type_error_flags */ 4217#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 4218 uint8_t reserved1; 4219 uint8_t queue_index /* The aggregation queue index of this packet */; 4220 uint8_t reserved2; 4221 uint32_t timestamp_delta /* timestamp delta between first packet to last packet in aggregation */; 4222 uint16_t num_of_coalesced_segs /* Num of coalesced segments. */; 4223 uint16_t pkt_len /* Packet length */; 4224 uint8_t pure_ack_count /* Number of pure acks coalesced. */; 4225 uint8_t reserved3; 4226 uint16_t reserved4; 4227 union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */; 4228 uint32_t reserved5[8]; 4229}; 4230 4231 4232/* 4233 * regular eth FP CQE parameters struct $$KEEP_ENDIANNESS$$ 4234 */ 4235struct eth_fast_path_rx_cqe 4236{ 4237 uint8_t type_error_flags; 4238#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */ 4239#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 4240#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */ 4241#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 4242#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* BitField type_error_flags Physical layer errors */ 4243#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 4244#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* BitField type_error_flags IP checksum error */ 4245#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 4246#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* BitField type_error_flags TCP/UDP checksum error */ 4247#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 4248#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) /* BitField type_error_flags */ 4249#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 4250 uint8_t status_flags; 4251#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* BitField status_flags (use enum eth_rss_hash_type) */ 4252#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 4253#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* BitField status_flags RSS hashing on/off */ 4254#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 4255#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* BitField status_flags if set to 1, this is a broadcast packet */ 4256#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 4257#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* BitField status_flags if set to 1, the MAC address was matched in the tstorm CAM search */ 4258#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 4259#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* BitField status_flags IP checksum validation was not performed (if packet is not IPv4) */ 4260#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 4261#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* BitField status_flags TCP/UDP checksum validation was not performed (if packet is not TCP/UDP or IPv6 extheaders exist) */ 4262#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 4263 uint8_t queue_index /* The aggregation queue index of this packet */; 4264 uint8_t placement_offset /* Placement offset from the start of the BD, in bytes */; 4265 uint32_t rss_hash_result /* RSS toeplitz hash result */; 4266 uint16_t vlan_tag /* Ethernet VLAN tag field */; 4267 uint16_t pkt_len_or_gro_seg_len /* Packet length (for non-TPA CQE) or GRO Segment Length (for TPA in GRO Mode) otherwise 0 */; 4268 uint16_t len_on_bd /* Number of bytes placed on the BD */; 4269 struct parsing_flags pars_flags; 4270 union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */; 4271 uint32_t reserved1[8]; 4272}; 4273 4274 4275/* 4276 * Command for setting classification flags for a client $$KEEP_ENDIANNESS$$ 4277 */ 4278struct eth_filter_rules_cmd 4279{ 4280 uint8_t cmd_general_data; 4281#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ 4282#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 4283#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ 4284#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 4285#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* BitField cmd_general_data */ 4286#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 4287 uint8_t func_id /* the function id */; 4288 uint8_t client_id /* the client id */; 4289 uint8_t reserved1; 4290 uint16_t state; 4291#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* BitField state drop all unicast packets */ 4292#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 4293#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* BitField state accept all unicast packets (subject to vlan) */ 4294#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 4295#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField state accept all unmatched unicast packets */ 4296#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 4297#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* BitField state drop all multicast packets */ 4298#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 4299#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* BitField state accept all multicast packets (subject to vlan) */ 4300#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 4301#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* BitField state accept all broadcast packets (subject to vlan) */ 4302#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 4303#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* BitField state accept packets matched only by MAC (without checking vlan) */ 4304#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 4305#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /* BitField state */ 4306#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 4307 uint16_t reserved3; 4308 struct regpair reserved4; 4309}; 4310 4311 4312/* 4313 * parameters for eth classification filters ramrod $$KEEP_ENDIANNESS$$ 4314 */ 4315struct eth_filter_rules_ramrod_data 4316{ 4317 struct eth_classify_header header; 4318 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 4319}; 4320 4321 4322/* 4323 * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$ 4324 */ 4325struct eth_general_rules_ramrod_data 4326{ 4327 struct eth_classify_header header; 4328 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 4329}; 4330 4331 4332/* 4333 * The data for Halt ramrod 4334 */ 4335struct eth_halt_ramrod_data 4336{ 4337 uint32_t client_id /* id of this client. (5 bits are used) */; 4338 uint32_t reserved0; 4339}; 4340 4341 4342/* 4343 * destination and source mac address. 4344 */ 4345struct eth_mac_addresses 4346{ 4347#if defined(__BIG_ENDIAN) 4348 uint16_t dst_mid /* destination mac address 16 middle bits */; 4349 uint16_t dst_lo /* destination mac address 16 low bits */; 4350#elif defined(__LITTLE_ENDIAN) 4351 uint16_t dst_lo /* destination mac address 16 low bits */; 4352 uint16_t dst_mid /* destination mac address 16 middle bits */; 4353#endif 4354#if defined(__BIG_ENDIAN) 4355 uint16_t src_lo /* source mac address 16 low bits */; 4356 uint16_t dst_hi /* destination mac address 16 high bits */; 4357#elif defined(__LITTLE_ENDIAN) 4358 uint16_t dst_hi /* destination mac address 16 high bits */; 4359 uint16_t src_lo /* source mac address 16 low bits */; 4360#endif 4361#if defined(__BIG_ENDIAN) 4362 uint16_t src_hi /* source mac address 16 high bits */; 4363 uint16_t src_mid /* source mac address 16 middle bits */; 4364#elif defined(__LITTLE_ENDIAN) 4365 uint16_t src_mid /* source mac address 16 middle bits */; 4366 uint16_t src_hi /* source mac address 16 high bits */; 4367#endif 4368}; 4369 4370 4371/* 4372 * tunneling related data. 4373 */ 4374struct eth_tunnel_data 4375{ 4376#if defined(__BIG_ENDIAN) 4377 uint16_t dst_mid /* destination mac address 16 middle bits */; 4378 uint16_t dst_lo /* destination mac address 16 low bits */; 4379#elif defined(__LITTLE_ENDIAN) 4380 uint16_t dst_lo /* destination mac address 16 low bits */; 4381 uint16_t dst_mid /* destination mac address 16 middle bits */; 4382#endif 4383#if defined(__BIG_ENDIAN) 4384 uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */; 4385 uint16_t dst_hi /* destination mac address 16 high bits */; 4386#elif defined(__LITTLE_ENDIAN) 4387 uint16_t dst_hi /* destination mac address 16 high bits */; 4388 uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */; 4389#endif 4390#if defined(__BIG_ENDIAN) 4391 uint8_t flags; 4392#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */ 4393#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0 4394#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */ 4395#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1 4396 uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */; 4397 uint16_t pseudo_csum /* Pseudo checksum with length field=0 */; 4398#elif defined(__LITTLE_ENDIAN) 4399 uint16_t pseudo_csum /* Pseudo checksum with length field=0 */; 4400 uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */; 4401 uint8_t flags; 4402#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */ 4403#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0 4404#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */ 4405#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1 4406#endif 4407}; 4408 4409/* 4410 * union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). 4411 */ 4412union eth_mac_addr_or_tunnel_data 4413{ 4414 struct eth_mac_addresses mac_addr /* destination and source mac addresses. */; 4415 struct eth_tunnel_data tunnel_data /* tunneling related data. */; 4416}; 4417 4418 4419/* 4420 * Command for setting multicast classification for a client $$KEEP_ENDIANNESS$$ 4421 */ 4422struct eth_multicast_rules_cmd 4423{ 4424 uint8_t cmd_general_data; 4425#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ 4426#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 4427#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ 4428#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 4429#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) /* BitField cmd_general_data 1 for add rule, 0 for remove rule */ 4430#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 4431#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* BitField cmd_general_data */ 4432#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 4433 uint8_t func_id /* the function id */; 4434 uint8_t bin_id /* the bin to add this function to (0-255) */; 4435 uint8_t engine_id /* the approximate multicast engine id */; 4436 uint32_t reserved2; 4437 struct regpair reserved3; 4438}; 4439 4440 4441/* 4442 * parameters for multicast classification ramrod $$KEEP_ENDIANNESS$$ 4443 */ 4444struct eth_multicast_rules_ramrod_data 4445{ 4446 struct eth_classify_header header; 4447 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 4448}; 4449 4450 4451/* 4452 * Place holder for ramrods protocol specific data 4453 */ 4454struct ramrod_data 4455{ 4456 uint32_t data_lo; 4457 uint32_t data_hi; 4458}; 4459 4460/* 4461 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 4462 */ 4463union eth_ramrod_data 4464{ 4465 struct ramrod_data general; 4466}; 4467 4468 4469/* 4470 * RSS toeplitz hash type, as reported in CQE 4471 */ 4472enum eth_rss_hash_type 4473{ 4474 DEFAULT_HASH_TYPE, 4475 IPV4_HASH_TYPE, 4476 TCP_IPV4_HASH_TYPE, 4477 IPV6_HASH_TYPE, 4478 TCP_IPV6_HASH_TYPE, 4479 VLAN_PRI_HASH_TYPE, 4480 E1HOV_PRI_HASH_TYPE, 4481 DSCP_HASH_TYPE, 4482 MAX_ETH_RSS_HASH_TYPE}; 4483 4484 4485/* 4486 * Ethernet RSS mode 4487 */ 4488enum eth_rss_mode 4489{ 4490 ETH_RSS_MODE_DISABLED, 4491 ETH_RSS_MODE_ESX51 /* RSS mode for Vmware ESX 5.1 (Only do RSS if packet is UDP with dst port that matches the UDP 4-tuble Destination Port mask and value) */, 4492 ETH_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */, 4493 ETH_RSS_MODE_VLAN_PRI /* RSS based on inner-vlan priority field */, 4494 ETH_RSS_MODE_E1HOV_PRI /* RSS based on outer-vlan priority field */, 4495 ETH_RSS_MODE_IP_DSCP /* RSS based on IPv4 DSCP field */, 4496 MAX_ETH_RSS_MODE}; 4497 4498 4499/* 4500 * parameters for RSS update ramrod (E2) $$KEEP_ENDIANNESS$$ 4501 */ 4502struct eth_rss_update_ramrod_data 4503{ 4504 uint8_t rss_engine_id; 4505 uint8_t capabilities; 4506#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 2-tupple capability */ 4507#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 4508#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for TCP */ 4509#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 4510#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for UDP */ 4511#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 4512#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 2-tupple capability */ 4513#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 4514#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for TCP */ 4515#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 4516#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for UDP */ 4517#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 4518#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) /* BitField capabilitiesFunction RSS capabilities configuration of the 5-tupple capability */ 4519#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6 4520#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) /* BitField capabilitiesFunction RSS capabilities if set update the rss keys */ 4521#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7 4522 uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */; 4523 uint8_t rss_mode /* The RSS mode for this function */; 4524 uint16_t udp_4tuple_dst_port_mask /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */; 4525 uint16_t udp_4tuple_dst_port_value /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */; 4526 uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE] /* RSS indirection table */; 4527 uint32_t rss_key[T_ETH_RSS_KEY] /* RSS key supplied as by OS */; 4528 uint32_t echo; 4529 uint32_t reserved3; 4530}; 4531 4532 4533/* 4534 * The eth Rx Buffer Descriptor 4535 */ 4536struct eth_rx_bd 4537{ 4538 uint32_t addr_lo /* Single continuous buffer low pointer */; 4539 uint32_t addr_hi /* Single continuous buffer high pointer */; 4540}; 4541 4542 4543/* 4544 * Eth Rx Cqe structure- general structure for ramrods $$KEEP_ENDIANNESS$$ 4545 */ 4546struct common_ramrod_eth_rx_cqe 4547{ 4548 uint8_t ramrod_type; 4549#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* BitField ramrod_type (use enum eth_rx_cqe_type) */ 4550#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 4551#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* BitField ramrod_type */ 4552#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 4553#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* BitField ramrod_type */ 4554#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 4555 uint8_t conn_type /* only 3 bits are used */; 4556 uint16_t reserved1 /* protocol specific data */; 4557 uint32_t conn_and_cmd_data; 4558#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */ 4559#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 4560#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use RamrodCommandIdEnum */ 4561#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 4562 struct ramrod_data protocol_data /* protocol specific data */; 4563 uint32_t echo; 4564 uint32_t reserved2[11]; 4565}; 4566 4567/* 4568 * Rx Last CQE in page (in ETH) 4569 */ 4570struct eth_rx_cqe_next_page 4571{ 4572 uint32_t addr_lo /* Next page low pointer */; 4573 uint32_t addr_hi /* Next page high pointer */; 4574 uint32_t reserved[14]; 4575}; 4576 4577/* 4578 * union for all eth rx cqe types (fix their sizes) 4579 */ 4580union eth_rx_cqe 4581{ 4582 struct eth_fast_path_rx_cqe fast_path_cqe; 4583 struct common_ramrod_eth_rx_cqe ramrod_cqe; 4584 struct eth_rx_cqe_next_page next_page_cqe; 4585 struct eth_end_agg_rx_cqe end_agg_cqe; 4586}; 4587 4588 4589/* 4590 * Values for RX ETH CQE type field 4591 */ 4592enum eth_rx_cqe_type 4593{ 4594 RX_ETH_CQE_TYPE_ETH_FASTPATH /* Fast path CQE */, 4595 RX_ETH_CQE_TYPE_ETH_RAMROD /* Slow path CQE */, 4596 RX_ETH_CQE_TYPE_ETH_START_AGG /* Fast path CQE */, 4597 RX_ETH_CQE_TYPE_ETH_STOP_AGG /* Slow path CQE */, 4598 MAX_ETH_RX_CQE_TYPE}; 4599 4600 4601/* 4602 * Type of SGL/Raw field in ETH RX fast path CQE 4603 */ 4604enum eth_rx_fp_sel 4605{ 4606 ETH_FP_CQE_REGULAR /* Regular CQE- no extra data */, 4607 ETH_FP_CQE_RAW /* Extra data is raw data- iscsi OOO */, 4608 MAX_ETH_RX_FP_SEL}; 4609 4610 4611/* 4612 * The eth Rx SGE Descriptor 4613 */ 4614struct eth_rx_sge 4615{ 4616 uint32_t addr_lo /* Single continuous buffer low pointer */; 4617 uint32_t addr_hi /* Single continuous buffer high pointer */; 4618}; 4619 4620 4621/* 4622 * common data for all protocols $$KEEP_ENDIANNESS$$ 4623 */ 4624struct spe_hdr 4625{ 4626 uint32_t conn_and_cmd_data; 4627#define SPE_HDR_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */ 4628#define SPE_HDR_CID_SHIFT 0 4629#define SPE_HDR_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use enum common_spqe_cmd_id/eth_spqe_cmd_id/toe_spqe_cmd_id */ 4630#define SPE_HDR_CMD_ID_SHIFT 24 4631 uint16_t type; 4632#define SPE_HDR_CONN_TYPE (0xFF<<0) /* BitField type connection type. (3 bits are used) (use enum connection_type) */ 4633#define SPE_HDR_CONN_TYPE_SHIFT 0 4634#define SPE_HDR_FUNCTION_ID (0xFF<<8) /* BitField type */ 4635#define SPE_HDR_FUNCTION_ID_SHIFT 8 4636 uint16_t reserved1; 4637}; 4638 4639/* 4640 * specific data for ethernet slow path element 4641 */ 4642union eth_specific_data 4643{ 4644 uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */; 4645 struct regpair client_update_ramrod_data /* The address of the data for client update ramrod */; 4646 struct regpair client_init_ramrod_init_data /* The data for client setup ramrod */; 4647 struct eth_halt_ramrod_data halt_ramrod_data /* Includes the client id to be deleted */; 4648 struct regpair update_data_addr /* physical address of the eth_rss_update_ramrod_data struct, as allocated by the driver */; 4649 struct eth_common_ramrod_data common_ramrod_data /* The data contain client ID need to the ramrod */; 4650 struct regpair classify_cfg_addr /* physical address of the eth_classify_rules_ramrod_data struct, as allocated by the driver */; 4651 struct regpair filter_cfg_addr /* physical address of the eth_filter_cfg_ramrod_data struct, as allocated by the driver */; 4652 struct regpair mcast_cfg_addr /* physical address of the eth_mcast_cfg_ramrod_data struct, as allocated by the driver */; 4653}; 4654 4655/* 4656 * Ethernet slow path element 4657 */ 4658struct eth_spe 4659{ 4660 struct spe_hdr hdr /* common data for all protocols */; 4661 union eth_specific_data data /* data specific to ethernet protocol */; 4662}; 4663 4664 4665/* 4666 * Ethernet command ID for slow path elements 4667 */ 4668enum eth_spqe_cmd_id 4669{ 4670 RAMROD_CMD_ID_ETH_UNUSED, 4671 RAMROD_CMD_ID_ETH_CLIENT_SETUP /* Setup a new L2 client */, 4672 RAMROD_CMD_ID_ETH_HALT /* Halt an L2 client */, 4673 RAMROD_CMD_ID_ETH_FORWARD_SETUP /* Setup a new FW channel */, 4674 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP /* Setup a new Tx only queue */, 4675 RAMROD_CMD_ID_ETH_CLIENT_UPDATE /* Update an L2 client configuration */, 4676 RAMROD_CMD_ID_ETH_EMPTY /* Empty ramrod - used to synchronize iSCSI OOO */, 4677 RAMROD_CMD_ID_ETH_TERMINATE /* Terminate an L2 client */, 4678 RAMROD_CMD_ID_ETH_TPA_UPDATE /* update the tpa roles in L2 client */, 4679 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, 4680 RAMROD_CMD_ID_ETH_FILTER_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, 4681 RAMROD_CMD_ID_ETH_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */, 4682 RAMROD_CMD_ID_ETH_RSS_UPDATE /* Update RSS configuration */, 4683 RAMROD_CMD_ID_ETH_SET_MAC /* Update RSS configuration */, 4684 MAX_ETH_SPQE_CMD_ID}; 4685 4686 4687/* 4688 * eth tpa update command 4689 */ 4690enum eth_tpa_update_command 4691{ 4692 TPA_UPDATE_NONE_COMMAND /* nop command */, 4693 TPA_UPDATE_ENABLE_COMMAND /* enable command */, 4694 TPA_UPDATE_DISABLE_COMMAND /* disable command */, 4695 MAX_ETH_TPA_UPDATE_COMMAND}; 4696 4697 4698/* 4699 * In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header 4700 */ 4701enum eth_tunnel_lso_inc_ip_id 4702{ 4703 EXT_HEADER /* Increment IP ID of external header (HW works on external, FW works on internal */, 4704 INT_HEADER /* Increment IP ID of internal header (HW works on internal, FW works on external */, 4705 MAX_ETH_TUNNEL_LSO_INC_IP_ID}; 4706 4707 4708/* 4709 * In case tunnel exist and L4 checksum offload (or outer ip header checksum), the pseudo checksum location, on packet or on BD. 4710 */ 4711enum eth_tunnel_non_lso_csum_location 4712{ 4713 CSUM_ON_PKT /* checksum is on the packet. */, 4714 CSUM_ON_BD /* checksum is on the BD. */, 4715 MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION}; 4716 4717 4718/* 4719 * Tx regular BD structure $$KEEP_ENDIANNESS$$ 4720 */ 4721struct eth_tx_bd 4722{ 4723 uint32_t addr_lo /* Single continuous buffer low pointer */; 4724 uint32_t addr_hi /* Single continuous buffer high pointer */; 4725 uint16_t total_pkt_bytes /* Size of the entire packet, valid for non-LSO packets */; 4726 uint16_t nbytes /* Size of the data represented by the BD */; 4727 uint8_t reserved[4] /* keeps same size as other eth tx bd types */; 4728}; 4729 4730 4731/* 4732 * structure for easy accessibility to assembler 4733 */ 4734struct eth_tx_bd_flags 4735{ 4736 uint8_t as_bitfield; 4737#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* BitField as_bitfield IP CKSUM flag,Relevant in START */ 4738#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 4739#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* BitField as_bitfield L4 CKSUM flag,Relevant in START */ 4740#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 4741#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* BitField as_bitfield 00 - no vlan; 01 - inband Vlan; 10 outband Vlan (use enum eth_tx_vlan_type) */ 4742#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 4743#define ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* BitField as_bitfield Start of packet BD */ 4744#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 4745#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* BitField as_bitfield flag that indicates that the current packet is a udp packet */ 4746#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 4747#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* BitField as_bitfield LSO flag, Relevant in START */ 4748#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 4749#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* BitField as_bitfield set in case ipV6 packet, Relevant in START */ 4750#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 4751}; 4752 4753/* 4754 * The eth Tx Buffer Descriptor $$KEEP_ENDIANNESS$$ 4755 */ 4756struct eth_tx_start_bd 4757{ 4758 uint32_t addr_lo /* Single continuous buffer low pointer */; 4759 uint32_t addr_hi /* Single continuous buffer high pointer */; 4760 uint16_t nbd /* Num of BDs in packet: include parsInfoBD, Relevant in START(only in Everest) */; 4761 uint16_t nbytes /* Size of the data represented by the BD */; 4762 uint16_t vlan_or_ethertype /* Vlan structure: vlan_id is in lsb, then cfi and then priority vlan_id 12 bits (lsb), cfi 1 bit, priority 3 bits. In E2, this field should be set with etherType for VFs with no vlan */; 4763 struct eth_tx_bd_flags bd_flags; 4764 uint8_t general_data; 4765#define ETH_TX_START_BD_HDR_NBDS (0xF<<0) /* BitField general_data contains the number of BDs that contain Ethernet/IP/TCP headers, for full/partial LSO modes */ 4766#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 4767#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* BitField general_data force vlan mode according to bds (vlan mode can change accroding to global configuration) */ 4768#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 4769#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* BitField general_data Determines the number of parsing BDs in packet. Number of parsing BDs in packet is (parse_nbds+1). */ 4770#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 4771#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* BitField general_data set in case of tunneling encapsulated packet */ 4772#define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7 4773}; 4774 4775/* 4776 * Tx parsing BD structure for ETH E1/E1h $$KEEP_ENDIANNESS$$ 4777 */ 4778struct eth_tx_parse_bd_e1x 4779{ 4780 uint16_t global_data; 4781#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* BitField global_data IP header Offset in WORDs from start of packet */ 4782#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 4783#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* BitField global_data marks ethernet address type (use enum eth_addr_type) */ 4784#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 4785#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* BitField global_data */ 4786#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 4787#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* BitField global_data */ 4788#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 4789#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */ 4790#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 4791#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) /* BitField global_data reserved bit, should be set with 0 */ 4792#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 4793 uint8_t tcp_flags; 4794#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */ 4795#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 4796#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */ 4797#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 4798#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */ 4799#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 4800#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */ 4801#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 4802#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */ 4803#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 4804#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */ 4805#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 4806#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */ 4807#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 4808#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */ 4809#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 4810 uint8_t ip_hlen_w /* IP header length in WORDs */; 4811 uint16_t total_hlen_w /* IP+TCP+ETH */; 4812 uint16_t tcp_pseudo_csum /* Checksum of pseudo header with length field=0 */; 4813 uint16_t lso_mss /* for LSO mode */; 4814 uint16_t ip_id /* for LSO mode */; 4815 uint32_t tcp_send_seq /* for LSO mode */; 4816}; 4817 4818/* 4819 * Tx parsing BD structure for ETH E2 $$KEEP_ENDIANNESS$$ 4820 */ 4821struct eth_tx_parse_bd_e2 4822{ 4823 union eth_mac_addr_or_tunnel_data data /* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). */; 4824 uint32_t parsing_data; 4825#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /* BitField parsing_data TCP/UDP header Offset in WORDs from start of packet */ 4826#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0 4827#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* BitField parsing_data TCP header size in DOUBLE WORDS */ 4828#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 4829#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* BitField parsing_data a flag to indicate an ipv6 packet with extension headers. If set on LSO packet, pseudo CS should be placed in TCP CS field without length field */ 4830#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 4831#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) /* BitField parsing_data for LSO mode */ 4832#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 4833#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* BitField parsing_data marks ethernet address type (use enum eth_addr_type) */ 4834#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 4835}; 4836 4837/* 4838 * Tx 2nd parsing BD structure for ETH packet $$KEEP_ENDIANNESS$$ 4839 */ 4840struct eth_tx_parse_2nd_bd 4841{ 4842 uint16_t global_data; 4843#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* BitField global_data Outer IP header offset in WORDs (16-bit) from start of packet */ 4844#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 4845#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) /* BitField global_data should be set with 0 */ 4846#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4 4847#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* BitField global_data */ 4848#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 4849#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */ 4850#define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6 4851#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* BitField global_data Set in case UDP header exists in tunnel outer hedears. */ 4852#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 4853#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* BitField global_data Outer IP header length in WORDs (16-bit). Valid only for IpV4. */ 4854#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 4855#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) /* BitField global_data should be set with 0 */ 4856#define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13 4857 uint16_t reserved2; 4858 uint8_t tcp_flags; 4859#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */ 4860#define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 4861#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */ 4862#define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1 4863#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */ 4864#define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2 4865#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */ 4866#define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3 4867#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */ 4868#define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4 4869#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */ 4870#define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5 4871#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */ 4872#define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 4873#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */ 4874#define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 4875 uint8_t reserved3; 4876 uint8_t tunnel_udp_hdr_start_w /* Offset (in WORDs) from start of packet to tunnel UDP header. (if exist) */; 4877 uint8_t fw_ip_hdr_to_payload_w /* In IpV4, the length (in WORDs) from the FW IpV4 header start to the payload start. In IpV6, the length (in WORDs) from the FW IpV6 header end to the payload start. However, if extension headers are included, their length is counted here as well. */; 4878 uint16_t fw_ip_csum_wo_len_flags_frag /* For the IP header which is set by the FW, the IP checksum without length, flags and fragment offset. */; 4879 uint16_t hw_ip_id /* The IP ID to be set by HW for LSO packets in tunnel mode. */; 4880 uint32_t tcp_send_seq /* The TCP sequence number for LSO packets. */; 4881}; 4882 4883/* 4884 * The last BD in the BD memory will hold a pointer to the next BD memory 4885 */ 4886struct eth_tx_next_bd 4887{ 4888 uint32_t addr_lo /* Single continuous buffer low pointer */; 4889 uint32_t addr_hi /* Single continuous buffer high pointer */; 4890 uint8_t reserved[8] /* keeps same size as other eth tx bd types */; 4891}; 4892 4893/* 4894 * union for 4 Bd types 4895 */ 4896union eth_tx_bd_types 4897{ 4898 struct eth_tx_start_bd start_bd /* the first bd in a packets */; 4899 struct eth_tx_bd reg_bd /* the common bd */; 4900 struct eth_tx_parse_bd_e1x parse_bd_e1x /* parsing info BD for e1/e1h */; 4901 struct eth_tx_parse_bd_e2 parse_bd_e2 /* parsing info BD for e2 */; 4902 struct eth_tx_parse_2nd_bd parse_2nd_bd /* 2nd parsing info BD */; 4903 struct eth_tx_next_bd next_bd /* Bd that contains the address of the next page */; 4904}; 4905 4906/* 4907 * array of 13 bds as appears in the eth xstorm context 4908 */ 4909struct eth_tx_bds_array 4910{ 4911 union eth_tx_bd_types bds[13]; 4912}; 4913 4914 4915/* 4916 * VLAN mode on TX BDs 4917 */ 4918enum eth_tx_vlan_type 4919{ 4920 X_ETH_NO_VLAN, 4921 X_ETH_OUTBAND_VLAN, 4922 X_ETH_INBAND_VLAN, 4923 X_ETH_FW_ADDED_VLAN /* Driver should not use this! */, 4924 MAX_ETH_TX_VLAN_TYPE}; 4925 4926 4927/* 4928 * Ethernet VLAN filtering mode in E1x 4929 */ 4930enum eth_vlan_filter_mode 4931{ 4932 ETH_VLAN_FILTER_ANY_VLAN /* Dont filter by vlan */, 4933 ETH_VLAN_FILTER_SPECIFIC_VLAN /* Only the vlan_id is allowed */, 4934 ETH_VLAN_FILTER_CLASSIFY /* Vlan will be added to CAM for classification */, 4935 MAX_ETH_VLAN_FILTER_MODE}; 4936 4937 4938/* 4939 * MAC filtering configuration command header $$KEEP_ENDIANNESS$$ 4940 */ 4941struct mac_configuration_hdr 4942{ 4943 uint8_t length /* number of entries valid in this command (6 bits) */; 4944 uint8_t offset /* offset of the first entry in the list */; 4945 uint16_t client_id /* the client id which this ramrod is sent on. 5b is used. */; 4946 uint32_t echo /* echo value to be sent to driver on event ring */; 4947}; 4948 4949/* 4950 * MAC address in list for ramrod $$KEEP_ENDIANNESS$$ 4951 */ 4952struct mac_configuration_entry 4953{ 4954 uint16_t lsb_mac_addr /* 2 LSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */; 4955 uint16_t middle_mac_addr /* 2 middle bytes of MAC address (should be given in big endien - driver should do hton to this number!!!) */; 4956 uint16_t msb_mac_addr /* 2 MSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */; 4957 uint16_t vlan_id /* The inner vlan id (12b). Used either in vlan_in_cam for mac_valn pair or for vlan filtering */; 4958 uint8_t pf_id /* The pf id, for multi function mode */; 4959 uint8_t flags; 4960#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* BitField flags configures the action to be done in cam (used only is slow path handlers) (use enum set_mac_action_type) */ 4961#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 4962#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* BitField flags If set, this MAC also belongs to RDMA client */ 4963#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 4964#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* BitField flags (use enum eth_vlan_filter_mode) */ 4965#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 4966#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags BitField flags 0 - cant remove vlan 1 - can remove vlan. relevant only to everest1 */ 4967#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 4968#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) /* BitField flags BitField flags 0 - not broadcast 1 - broadcast. relevant only to everest1 */ 4969#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 4970#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* BitField flags */ 4971#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 4972 uint16_t reserved0; 4973 uint32_t clients_bit_vector /* Bit vector for the clients which should receive this MAC. */; 4974}; 4975 4976/* 4977 * MAC filtering configuration command 4978 */ 4979struct mac_configuration_cmd 4980{ 4981 struct mac_configuration_hdr hdr /* header */; 4982 struct mac_configuration_entry config_table[64] /* table of 64 MAC configuration entries: addresses and target table entries */; 4983}; 4984 4985 4986/* 4987 * Set-MAC command type (in E1x) 4988 */ 4989enum set_mac_action_type 4990{ 4991 T_ETH_MAC_COMMAND_INVALIDATE, 4992 T_ETH_MAC_COMMAND_SET, 4993 MAX_SET_MAC_ACTION_TYPE}; 4994 4995 4996/* 4997 * Ethernet TPA Modes 4998 */ 4999enum tpa_mode 5000{ 5001 TPA_LRO /* LRO mode TPA */, 5002 TPA_GRO /* GRO mode TPA */, 5003 MAX_TPA_MODE}; 5004 5005 5006/* 5007 * tpa update ramrod data $$KEEP_ENDIANNESS$$ 5008 */ 5009struct tpa_update_ramrod_data 5010{ 5011 uint8_t update_ipv4 /* none, enable or disable */; 5012 uint8_t update_ipv6 /* none, enable or disable */; 5013 uint8_t client_id /* client init flow control data */; 5014 uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */; 5015 uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */; 5016 uint8_t complete_on_both_clients /* If set and the client has different sp_client, completion will be sent to both rings */; 5017 uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */; 5018 uint8_t tpa_mode /* TPA mode to use (LRO or GRO) */; 5019 uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */; 5020 uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */; 5021 uint32_t sge_page_base_lo /* The address to fetch the next sges from (low) */; 5022 uint32_t sge_page_base_hi /* The address to fetch the next sges from (high) */; 5023 uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */; 5024 uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */; 5025}; 5026 5027 5028/* 5029 * approximate-match multicast filtering for E1H per function in Tstorm 5030 */ 5031struct tstorm_eth_approximate_match_multicast_filtering 5032{ 5033 uint32_t mcast_add_hash_bit_array[8] /* Bit array for multicast hash filtering.Each bit supports a hash function result if to accept this multicast dst address. */; 5034}; 5035 5036 5037/* 5038 * Common configuration parameters per function in Tstorm $$KEEP_ENDIANNESS$$ 5039 */ 5040struct tstorm_eth_function_common_config 5041{ 5042 uint16_t config_flags; 5043#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */ 5044#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 5045#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 4-tupple capability */ 5046#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 5047#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */ 5048#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 5049#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV6 4-tupple capability */ 5050#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 5051#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* BitField config_flagsGeneral configuration flags RSS mode of operation (use enum eth_rss_mode) */ 5052#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 5053#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuration flags 0 - Dont filter by vlan, 1 - Filter according to the vlans specificied in mac_filter_config */ 5054#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 5055#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* BitField config_flagsGeneral configuration flags */ 5056#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 5057 uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */; 5058 uint8_t reserved1; 5059 uint16_t vlan_id[2] /* VLANs of this function. VLAN filtering is determine according to vlan_filtering_enable. */; 5060}; 5061 5062 5063/* 5064 * MAC filtering configuration parameters per port in Tstorm $$KEEP_ENDIANNESS$$ 5065 */ 5066struct tstorm_eth_mac_filter_config 5067{ 5068 uint32_t ucast_drop_all /* bit vector in which the clients which drop all unicast packets are set */; 5069 uint32_t ucast_accept_all /* bit vector in which clients that accept all unicast packets are set */; 5070 uint32_t mcast_drop_all /* bit vector in which the clients which drop all multicast packets are set */; 5071 uint32_t mcast_accept_all /* bit vector in which clients that accept all multicast packets are set */; 5072 uint32_t bcast_accept_all /* bit vector in which clients that accept all broadcast packets are set */; 5073 uint32_t vlan_filter[2] /* bit vector for VLAN filtering. Clients which enforce filtering of vlan[x] should be marked in vlan_filter[x]. In E1 only vlan_filter[1] is checked. The primary vlan is taken from the CAM target table. */; 5074 uint32_t unmatched_unicast /* bit vector in which clients that accept unmatched unicast packets are set */; 5075}; 5076 5077 5078/* 5079 * tx only queue init ramrod data $$KEEP_ENDIANNESS$$ 5080 */ 5081struct tx_queue_init_ramrod_data 5082{ 5083 struct client_init_general_data general /* client init general data */; 5084 struct client_init_tx_data tx /* client init tx data */; 5085}; 5086 5087 5088/* 5089 * Three RX producers for ETH 5090 */ 5091struct ustorm_eth_rx_producers 5092{ 5093#if defined(__BIG_ENDIAN) 5094 uint16_t bd_prod /* Producer of the RX BD ring */; 5095 uint16_t cqe_prod /* Producer of the RX CQE ring */; 5096#elif defined(__LITTLE_ENDIAN) 5097 uint16_t cqe_prod /* Producer of the RX CQE ring */; 5098 uint16_t bd_prod /* Producer of the RX BD ring */; 5099#endif 5100#if defined(__BIG_ENDIAN) 5101 uint16_t reserved; 5102 uint16_t sge_prod /* Producer of the RX SGE ring */; 5103#elif defined(__LITTLE_ENDIAN) 5104 uint16_t sge_prod /* Producer of the RX SGE ring */; 5105 uint16_t reserved; 5106#endif 5107}; 5108 5109 5110/* 5111 * The data afex vif list ramrod need $$KEEP_ENDIANNESS$$ 5112 */ 5113struct afex_vif_list_ramrod_data 5114{ 5115 uint8_t afex_vif_list_command /* set get, clear all a VIF list id defined by enum vif_list_rule_kind */; 5116 uint8_t func_bit_map /* the function bit map to set */; 5117 uint16_t vif_list_index /* the VIF list, in a per pf vector to add this function to */; 5118 uint8_t func_to_clear /* the func id to clear in case of clear func mode */; 5119 uint8_t echo; 5120 uint16_t reserved1; 5121}; 5122 5123 5124/* 5125 * cfc delete event data $$KEEP_ENDIANNESS$$ 5126 */ 5127struct cfc_del_event_data 5128{ 5129 uint32_t cid /* cid of deleted connection */; 5130 uint32_t reserved0; 5131 uint32_t reserved1; 5132}; 5133 5134 5135/* 5136 * per-port SAFC demo variables 5137 */ 5138struct cmng_flags_per_port 5139{ 5140 uint32_t cmng_enables; 5141#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between vnics */ 5142#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 5143#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable rate shaping between vnics */ 5144#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 5145#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between COSes */ 5146#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 5147#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes (use enum fairness_mode) */ 5148#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 5149#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes reserved */ 5150#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 5151 uint32_t __reserved1; 5152}; 5153 5154 5155/* 5156 * per-port rate shaping variables 5157 */ 5158struct rate_shaping_vars_per_port 5159{ 5160 uint32_t rs_periodic_timeout /* timeout of periodic timer */; 5161 uint32_t rs_threshold /* threshold, below which we start to stop queues */; 5162}; 5163 5164/* 5165 * per-port fairness variables 5166 */ 5167struct fairness_vars_per_port 5168{ 5169 uint32_t upper_bound /* Quota for a protocol/vnic */; 5170 uint32_t fair_threshold /* almost-empty threshold */; 5171 uint32_t fairness_timeout /* timeout of fairness timer */; 5172 uint32_t reserved0; 5173}; 5174 5175/* 5176 * per-port SAFC variables 5177 */ 5178struct safc_struct_per_port 5179{ 5180#if defined(__BIG_ENDIAN) 5181 uint16_t __reserved1; 5182 uint8_t __reserved0; 5183 uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */; 5184#elif defined(__LITTLE_ENDIAN) 5185 uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */; 5186 uint8_t __reserved0; 5187 uint16_t __reserved1; 5188#endif 5189 uint8_t cos_to_traffic_types[MAX_COS_NUMBER] /* translate cos to service traffics types */; 5190 uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS] /* QM pause mask for each class of service in the SAFC frame */; 5191}; 5192 5193/* 5194 * Per-port congestion management variables 5195 */ 5196struct cmng_struct_per_port 5197{ 5198 struct rate_shaping_vars_per_port rs_vars; 5199 struct fairness_vars_per_port fair_vars; 5200 struct safc_struct_per_port safc_vars; 5201 struct cmng_flags_per_port flags; 5202}; 5203 5204/* 5205 * a single rate shaping counter. can be used as protocol or vnic counter 5206 */ 5207struct rate_shaping_counter 5208{ 5209 uint32_t quota /* Quota for a protocol/vnic */; 5210#if defined(__BIG_ENDIAN) 5211 uint16_t __reserved0; 5212 uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */; 5213#elif defined(__LITTLE_ENDIAN) 5214 uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */; 5215 uint16_t __reserved0; 5216#endif 5217}; 5218 5219/* 5220 * per-vnic rate shaping variables 5221 */ 5222struct rate_shaping_vars_per_vn 5223{ 5224 struct rate_shaping_counter vn_counter /* per-vnic counter */; 5225}; 5226 5227/* 5228 * per-vnic fairness variables 5229 */ 5230struct fairness_vars_per_vn 5231{ 5232 uint32_t cos_credit_delta[MAX_COS_NUMBER] /* used for incrementing the credit */; 5233 uint32_t vn_credit_delta /* used for incrementing the credit */; 5234 uint32_t __reserved0; 5235}; 5236 5237/* 5238 * cmng port init state 5239 */ 5240struct cmng_vnic 5241{ 5242 struct rate_shaping_vars_per_vn vnic_max_rate[4]; 5243 struct fairness_vars_per_vn vnic_min_rate[4]; 5244}; 5245 5246/* 5247 * cmng port init state 5248 */ 5249struct cmng_init 5250{ 5251 struct cmng_struct_per_port port; 5252 struct cmng_vnic vnic; 5253}; 5254 5255 5256/* 5257 * driver parameters for congestion management init, all rates are in Mbps 5258 */ 5259struct cmng_init_input 5260{ 5261 uint32_t port_rate; 5262 uint16_t vnic_min_rate[4] /* rates are in Mbps */; 5263 uint16_t vnic_max_rate[4] /* rates are in Mbps */; 5264 uint16_t cos_min_rate[MAX_COS_NUMBER] /* rates are in Mbps */; 5265 uint16_t cos_to_pause_mask[MAX_COS_NUMBER]; 5266 struct cmng_flags_per_port flags; 5267}; 5268 5269 5270/* 5271 * Protocol-common command ID for slow path elements 5272 */ 5273enum common_spqe_cmd_id 5274{ 5275 RAMROD_CMD_ID_COMMON_UNUSED, 5276 RAMROD_CMD_ID_COMMON_FUNCTION_START /* Start a function (for PFs only) */, 5277 RAMROD_CMD_ID_COMMON_FUNCTION_STOP /* Stop a function (for PFs only) */, 5278 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE /* niv update function */, 5279 RAMROD_CMD_ID_COMMON_CFC_DEL /* Delete a connection from CFC */, 5280 RAMROD_CMD_ID_COMMON_CFC_DEL_WB /* Delete a connection from CFC (with write back) */, 5281 RAMROD_CMD_ID_COMMON_STAT_QUERY /* Collect statistics counters */, 5282 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */, 5283 RAMROD_CMD_ID_COMMON_START_TRAFFIC /* Start Tx traffic (after DCB updates) */, 5284 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS /* niv vif lists */, 5285 RAMROD_CMD_ID_COMMON_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */, 5286 MAX_COMMON_SPQE_CMD_ID}; 5287 5288 5289/* 5290 * Per-protocol connection types 5291 */ 5292enum connection_type 5293{ 5294 ETH_CONNECTION_TYPE /* Ethernet */, 5295 TOE_CONNECTION_TYPE /* TOE */, 5296 RDMA_CONNECTION_TYPE /* RDMA */, 5297 ISCSI_CONNECTION_TYPE /* iSCSI */, 5298 FCOE_CONNECTION_TYPE /* FCoE */, 5299 RESERVED_CONNECTION_TYPE_0, 5300 RESERVED_CONNECTION_TYPE_1, 5301 RESERVED_CONNECTION_TYPE_2, 5302 NONE_CONNECTION_TYPE /* General- used for common slow path */, 5303 MAX_CONNECTION_TYPE}; 5304 5305 5306/* 5307 * Cos modes 5308 */ 5309enum cos_mode 5310{ 5311 OVERRIDE_COS /* Firmware deduce cos according to DCB */, 5312 STATIC_COS /* Firmware has constant queues per CoS */, 5313 FW_WRR /* Firmware keep fairness between different CoSes */, 5314 MAX_COS_MODE}; 5315 5316 5317/* 5318 * Dynamic HC counters set by the driver 5319 */ 5320struct hc_dynamic_drv_counter 5321{ 5322 uint32_t val[HC_SB_MAX_DYNAMIC_INDICES] /* 4 bytes * 4 indices = 2 lines */; 5323}; 5324 5325/* 5326 * zone A per-queue data 5327 */ 5328struct cstorm_queue_zone_data 5329{ 5330 struct hc_dynamic_drv_counter hc_dyn_drv_cnt /* 4 bytes * 4 indices = 2 lines */; 5331 struct regpair reserved[2]; 5332}; 5333 5334 5335/* 5336 * Vf-PF channel data in cstorm ram (non-triggered zone) 5337 */ 5338struct vf_pf_channel_zone_data 5339{ 5340 uint32_t msg_addr_lo /* the message address on VF memory */; 5341 uint32_t msg_addr_hi /* the message address on VF memory */; 5342}; 5343 5344/* 5345 * zone for VF non-triggered data 5346 */ 5347struct non_trigger_vf_zone 5348{ 5349 struct vf_pf_channel_zone_data vf_pf_channel /* vf-pf channel zone data */; 5350}; 5351 5352/* 5353 * Vf-PF channel trigger zone in cstorm ram 5354 */ 5355struct vf_pf_channel_zone_trigger 5356{ 5357 uint8_t addr_valid /* indicates that a vf-pf message is pending. MUST be set AFTER the message address. */; 5358}; 5359 5360/* 5361 * zone that triggers the in-bound interrupt 5362 */ 5363struct trigger_vf_zone 5364{ 5365#if defined(__BIG_ENDIAN) 5366 uint16_t reserved1; 5367 uint8_t reserved0; 5368 struct vf_pf_channel_zone_trigger vf_pf_channel; 5369#elif defined(__LITTLE_ENDIAN) 5370 struct vf_pf_channel_zone_trigger vf_pf_channel; 5371 uint8_t reserved0; 5372 uint16_t reserved1; 5373#endif 5374 uint32_t reserved2; 5375}; 5376 5377/* 5378 * zone B per-VF data 5379 */ 5380struct cstorm_vf_zone_data 5381{ 5382 struct non_trigger_vf_zone non_trigger /* zone for VF non-triggered data */; 5383 struct trigger_vf_zone trigger /* zone that triggers the in-bound interrupt */; 5384}; 5385 5386 5387/* 5388 * Dynamic host coalescing init parameters, per state machine 5389 */ 5390struct dynamic_hc_sm_config 5391{ 5392 uint32_t threshold[3] /* thresholds of number of outstanding bytes */; 5393 uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES] /* bytes difference of each protocol is shifted right by this value */; 5394 uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 0 for each protocol, in units of usec */; 5395 uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 1 for each protocol, in units of usec */; 5396 uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 2 for each protocol, in units of usec */; 5397 uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 3 for each protocol, in units of usec */; 5398}; 5399 5400/* 5401 * Dynamic host coalescing init parameters 5402 */ 5403struct dynamic_hc_config 5404{ 5405 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM] /* Configuration per state machine */; 5406}; 5407 5408 5409struct e2_integ_data 5410{ 5411#if defined(__BIG_ENDIAN) 5412 uint8_t flags; 5413#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */ 5414#define E2_INTEG_DATA_TESTING_EN_SHIFT 0 5415#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */ 5416#define E2_INTEG_DATA_LB_TX_SHIFT 1 5417#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */ 5418#define E2_INTEG_DATA_COS_TX_SHIFT 2 5419#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */ 5420#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 5421#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */ 5422#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 5423#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */ 5424#define E2_INTEG_DATA_RESERVED_SHIFT 5 5425 uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */; 5426 uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5427 uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5428#elif defined(__LITTLE_ENDIAN) 5429 uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5430 uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5431 uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */; 5432 uint8_t flags; 5433#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */ 5434#define E2_INTEG_DATA_TESTING_EN_SHIFT 0 5435#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */ 5436#define E2_INTEG_DATA_LB_TX_SHIFT 1 5437#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */ 5438#define E2_INTEG_DATA_COS_TX_SHIFT 2 5439#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */ 5440#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 5441#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */ 5442#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 5443#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */ 5444#define E2_INTEG_DATA_RESERVED_SHIFT 5 5445#endif 5446#if defined(__BIG_ENDIAN) 5447 uint16_t reserved3; 5448 uint8_t reserved2; 5449 uint8_t ramEn /* context area reserved for reading enable bit from ram */; 5450#elif defined(__LITTLE_ENDIAN) 5451 uint8_t ramEn /* context area reserved for reading enable bit from ram */; 5452 uint8_t reserved2; 5453 uint16_t reserved3; 5454#endif 5455}; 5456 5457 5458/* 5459 * set mac event data $$KEEP_ENDIANNESS$$ 5460 */ 5461struct eth_event_data 5462{ 5463 uint32_t echo /* set mac echo data to return to driver */; 5464 uint32_t reserved0; 5465 uint32_t reserved1; 5466}; 5467 5468 5469/* 5470 * pf-vf event data $$KEEP_ENDIANNESS$$ 5471 */ 5472struct vf_pf_event_data 5473{ 5474 uint8_t vf_id /* VF ID (0-63) */; 5475 uint8_t reserved0; 5476 uint16_t reserved1; 5477 uint32_t msg_addr_lo /* message address on Vf (low 32 bits) */; 5478 uint32_t msg_addr_hi /* message address on Vf (high 32 bits) */; 5479}; 5480 5481/* 5482 * VF FLR event data $$KEEP_ENDIANNESS$$ 5483 */ 5484struct vf_flr_event_data 5485{ 5486 uint8_t vf_id /* VF ID (0-63) */; 5487 uint8_t reserved0; 5488 uint16_t reserved1; 5489 uint32_t reserved2; 5490 uint32_t reserved3; 5491}; 5492 5493/* 5494 * malicious VF event data $$KEEP_ENDIANNESS$$ 5495 */ 5496struct malicious_vf_event_data 5497{ 5498 uint8_t vf_id /* VF ID (0-63) */; 5499 uint8_t err_id /* reason for malicious notification */; 5500 uint16_t reserved1; 5501 uint32_t reserved2; 5502 uint32_t reserved3; 5503}; 5504 5505/* 5506 * vif list event data $$KEEP_ENDIANNESS$$ 5507 */ 5508struct vif_list_event_data 5509{ 5510 uint8_t func_bit_map /* bit map of pf indice */; 5511 uint8_t echo; 5512 uint16_t reserved0; 5513 uint32_t reserved1; 5514 uint32_t reserved2; 5515}; 5516 5517/* 5518 * function update event data $$KEEP_ENDIANNESS$$ 5519 */ 5520struct function_update_event_data 5521{ 5522 uint8_t echo; 5523 uint8_t reserved; 5524 uint16_t reserved0; 5525 uint32_t reserved1; 5526 uint32_t reserved2; 5527}; 5528 5529/* 5530 * union for all event ring message types 5531 */ 5532union event_data 5533{ 5534 struct vf_pf_event_data vf_pf_event /* vf-pf event data */; 5535 struct eth_event_data eth_event /* set mac event data */; 5536 struct cfc_del_event_data cfc_del_event /* cfc delete event data */; 5537 struct vf_flr_event_data vf_flr_event /* vf flr event data */; 5538 struct malicious_vf_event_data malicious_vf_event /* malicious vf event data */; 5539 struct vif_list_event_data vif_list_event /* vif list event data */; 5540 struct function_update_event_data function_update_event /* function update event data */; 5541}; 5542 5543 5544/* 5545 * per PF event ring data 5546 */ 5547struct event_ring_data 5548{ 5549 struct regpair_native base_addr /* ring base address */; 5550#if defined(__BIG_ENDIAN) 5551 uint8_t index_id /* index ID within the status block */; 5552 uint8_t sb_id /* status block ID */; 5553 uint16_t producer /* event ring producer */; 5554#elif defined(__LITTLE_ENDIAN) 5555 uint16_t producer /* event ring producer */; 5556 uint8_t sb_id /* status block ID */; 5557 uint8_t index_id /* index ID within the status block */; 5558#endif 5559 uint32_t reserved0; 5560}; 5561 5562 5563/* 5564 * event ring message element (each element is 128 bits) $$KEEP_ENDIANNESS$$ 5565 */ 5566struct event_ring_msg 5567{ 5568 uint8_t opcode; 5569 uint8_t error /* error on the mesasage */; 5570 uint16_t reserved1; 5571 union event_data data /* message data (96 bits data) */; 5572}; 5573 5574/* 5575 * event ring next page element (128 bits) 5576 */ 5577struct event_ring_next 5578{ 5579 struct regpair addr /* Address of the next page of the ring */; 5580 uint32_t reserved[2]; 5581}; 5582 5583/* 5584 * union for event ring element types (each element is 128 bits) 5585 */ 5586union event_ring_elem 5587{ 5588 struct event_ring_msg message /* event ring message */; 5589 struct event_ring_next next_page /* event ring next page */; 5590}; 5591 5592 5593/* 5594 * Common event ring opcodes 5595 */ 5596enum event_ring_opcode 5597{ 5598 EVENT_RING_OPCODE_VF_PF_CHANNEL, 5599 EVENT_RING_OPCODE_FUNCTION_START /* Start a function (for PFs only) */, 5600 EVENT_RING_OPCODE_FUNCTION_STOP /* Stop a function (for PFs only) */, 5601 EVENT_RING_OPCODE_CFC_DEL /* Delete a connection from CFC */, 5602 EVENT_RING_OPCODE_CFC_DEL_WB /* Delete a connection from CFC (with write back) */, 5603 EVENT_RING_OPCODE_STAT_QUERY /* Collect statistics counters */, 5604 EVENT_RING_OPCODE_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */, 5605 EVENT_RING_OPCODE_START_TRAFFIC /* Start Tx traffic (after DCB updates) */, 5606 EVENT_RING_OPCODE_VF_FLR /* VF FLR indication for PF */, 5607 EVENT_RING_OPCODE_MALICIOUS_VF /* Malicious VF operation detected */, 5608 EVENT_RING_OPCODE_FORWARD_SETUP /* Initialize forward channel */, 5609 EVENT_RING_OPCODE_RSS_UPDATE_RULES /* Update RSS configuration */, 5610 EVENT_RING_OPCODE_FUNCTION_UPDATE /* function update */, 5611 EVENT_RING_OPCODE_AFEX_VIF_LISTS /* event ring opcode niv vif lists */, 5612 EVENT_RING_OPCODE_SET_MAC /* Add/remove MAC (in E1x only) */, 5613 EVENT_RING_OPCODE_CLASSIFICATION_RULES /* Add/remove MAC or VLAN (in E2/E3 only) */, 5614 EVENT_RING_OPCODE_FILTERS_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, 5615 EVENT_RING_OPCODE_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */, 5616 EVENT_RING_OPCODE_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */, 5617 MAX_EVENT_RING_OPCODE}; 5618 5619 5620/* 5621 * Modes for fairness algorithm 5622 */ 5623enum fairness_mode 5624{ 5625 FAIRNESS_COS_WRR_MODE /* Weighted round robin mode (used in Google) */, 5626 FAIRNESS_COS_ETS_MODE /* ETS mode (used in FCoE) */, 5627 MAX_FAIRNESS_MODE}; 5628 5629 5630/* 5631 * Priority and cos $$KEEP_ENDIANNESS$$ 5632 */ 5633struct priority_cos 5634{ 5635 uint8_t priority /* Priority */; 5636 uint8_t cos /* Cos */; 5637 uint16_t reserved1; 5638}; 5639 5640/* 5641 * The data for flow control configuration $$KEEP_ENDIANNESS$$ 5642 */ 5643struct flow_control_configuration 5644{ 5645 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES] /* traffic_type to priority cos */; 5646 uint8_t dcb_enabled /* If DCB mode is enabled then traffic class to priority array is fully initialized and there must be inner VLAN */; 5647 uint8_t dcb_version /* DCB version Increase by one on each DCB update */; 5648 uint8_t dont_add_pri_0 /* In case, the priority is 0, and the packet has no vlan, the firmware wont add vlan */; 5649 uint8_t reserved1; 5650 uint32_t reserved2; 5651}; 5652 5653 5654/* 5655 * $$KEEP_ENDIANNESS$$ 5656 */ 5657struct function_start_data 5658{ 5659 uint8_t function_mode /* the function mode */; 5660 uint8_t allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independant function mode. (E2/E3 Only) */; 5661 uint16_t sd_vlan_tag /* value of Vlan in case of switch depended multi-function mode */; 5662 uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */; 5663 uint8_t path_id; 5664 uint8_t network_cos_mode /* The cos mode for network traffic. */; 5665 uint8_t dmae_cmd_id /* The DMAE command id to use for FW DMAE transactions */; 5666 uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */; 5667 uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */; 5668 uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */; 5669 uint16_t reserved1[2]; 5670}; 5671 5672 5673/* 5674 * $$KEEP_ENDIANNESS$$ 5675 */ 5676struct function_update_data 5677{ 5678 uint8_t vif_id_change_flg /* If set, vif_id will be checked */; 5679 uint8_t afex_default_vlan_change_flg /* If set, afex_default_vlan will be checked */; 5680 uint8_t allowed_priorities_change_flg /* If set, allowed_priorities will be checked */; 5681 uint8_t network_cos_mode_change_flg /* If set, network_cos_mode will be checked */; 5682 uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */; 5683 uint16_t afex_default_vlan /* value of default Vlan in case of NIV mf */; 5684 uint8_t allowed_priorities /* bit vector of allowed Vlan priorities for this VIF */; 5685 uint8_t network_cos_mode /* The cos mode for network traffic. */; 5686 uint8_t lb_mode_en_change_flg /* If set, lb_mode_en will be checked */; 5687 uint8_t lb_mode_en /* If set, niv loopback mode will be enabled */; 5688 uint8_t tx_switch_suspend_change_flg /* If set, tx_switch_suspend will be checked */; 5689 uint8_t tx_switch_suspend /* If set, TX switching TO this function will be disabled and packets will be dropped */; 5690 uint8_t echo; 5691 uint8_t reserved1; 5692 uint8_t update_gre_cfg_flg /* If set, GRE config for the function will be updated according to the gre_tunnel_rss and nvgre_clss_en fields */; 5693 uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */; 5694 uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */; 5695 uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */; 5696 uint32_t reserved3; 5697}; 5698 5699 5700/* 5701 * FW version stored in the Xstorm RAM 5702 */ 5703struct fw_version 5704{ 5705#if defined(__BIG_ENDIAN) 5706 uint8_t engineering /* firmware current engineering version */; 5707 uint8_t revision /* firmware current revision version */; 5708 uint8_t minor /* firmware current minor version */; 5709 uint8_t major /* firmware current major version */; 5710#elif defined(__LITTLE_ENDIAN) 5711 uint8_t major /* firmware current major version */; 5712 uint8_t minor /* firmware current minor version */; 5713 uint8_t revision /* firmware current revision version */; 5714 uint8_t engineering /* firmware current engineering version */; 5715#endif 5716 uint32_t flags; 5717#define FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */ 5718#define FW_VERSION_OPTIMIZED_SHIFT 0 5719#define FW_VERSION_BIG_ENDIEN (0x1<<1) /* BitField flags if set, this is big-endien ASM */ 5720#define FW_VERSION_BIG_ENDIEN_SHIFT 1 5721#define FW_VERSION_CHIP_VERSION (0x3<<2) /* BitField flags 0 - E1, 1 - E1H */ 5722#define FW_VERSION_CHIP_VERSION_SHIFT 2 5723#define __FW_VERSION_RESERVED (0xFFFFFFF<<4) /* BitField flags */ 5724#define __FW_VERSION_RESERVED_SHIFT 4 5725}; 5726 5727 5728/* 5729 * GRE RSS Mode 5730 */ 5731enum gre_rss_mode 5732{ 5733 GRE_OUTER_HEADERS_RSS /* RSS for GRE Packets is performed on the outer headers */, 5734 GRE_INNER_HEADERS_RSS /* RSS for GRE Packets is performed on the inner headers */, 5735 NVGRE_KEY_ENTROPY_RSS /* RSS for NVGRE Packets is done based on a hash containing the entropy bits from the GRE Key Field (gre_tunnel must be NVGRE_TUNNEL) */, 5736 MAX_GRE_RSS_MODE}; 5737 5738 5739/* 5740 * GRE Tunnel Mode 5741 */ 5742enum gre_tunnel_type 5743{ 5744 NO_GRE_TUNNEL, 5745 NVGRE_TUNNEL /* NV-GRE Tunneling Microsoft L2 over GRE. GRE header contains mandatory Key Field. */, 5746 L2GRE_TUNNEL /* L2-GRE Tunneling General L2 over GRE. GRE can contain Key field with Tenant ID and Sequence Field */, 5747 IPGRE_TUNNEL /* IP-GRE Tunneling IP over GRE. GRE may contain Key field with Tenant ID, Sequence Field and/or Checksum Field */, 5748 MAX_GRE_TUNNEL_TYPE}; 5749 5750 5751/* 5752 * Dynamic Host-Coalescing - Driver(host) counters 5753 */ 5754struct hc_dynamic_sb_drv_counters 5755{ 5756 uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES] /* Dynamic HC counters written by drivers */; 5757}; 5758 5759 5760/* 5761 * 2 bytes. configuration/state parameters for a single protocol index 5762 */ 5763struct hc_index_data 5764{ 5765#if defined(__BIG_ENDIAN) 5766 uint8_t flags; 5767#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */ 5768#define HC_INDEX_DATA_SM_ID_SHIFT 0 5769#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */ 5770#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5771#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */ 5772#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5773#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */ 5774#define HC_INDEX_DATA_RESERVE_SHIFT 3 5775 uint8_t timeout /* the timeout values for this index. Units are 4 usec */; 5776#elif defined(__LITTLE_ENDIAN) 5777 uint8_t timeout /* the timeout values for this index. Units are 4 usec */; 5778 uint8_t flags; 5779#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */ 5780#define HC_INDEX_DATA_SM_ID_SHIFT 0 5781#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */ 5782#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5783#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */ 5784#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5785#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */ 5786#define HC_INDEX_DATA_RESERVE_SHIFT 3 5787#endif 5788}; 5789 5790 5791/* 5792 * HC state-machine 5793 */ 5794struct hc_status_block_sm 5795{ 5796#if defined(__BIG_ENDIAN) 5797 uint8_t igu_seg_id; 5798 uint8_t igu_sb_id /* sb_id within the IGU */; 5799 uint8_t timer_value /* Determines the time_to_expire */; 5800 uint8_t __flags; 5801#elif defined(__LITTLE_ENDIAN) 5802 uint8_t __flags; 5803 uint8_t timer_value /* Determines the time_to_expire */; 5804 uint8_t igu_sb_id /* sb_id within the IGU */; 5805 uint8_t igu_seg_id; 5806#endif 5807 uint32_t time_to_expire /* The time in which it expects to wake up */; 5808}; 5809 5810/* 5811 * hold PCI identification variables- used in various places in firmware 5812 */ 5813struct pci_entity 5814{ 5815#if defined(__BIG_ENDIAN) 5816 uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */; 5817 uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */; 5818 uint8_t vnic_id /* Virtual NIC ID (0-3) */; 5819 uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */; 5820#elif defined(__LITTLE_ENDIAN) 5821 uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */; 5822 uint8_t vnic_id /* Virtual NIC ID (0-3) */; 5823 uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */; 5824 uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */; 5825#endif 5826}; 5827 5828/* 5829 * The fast-path status block meta-data, common to all chips 5830 */ 5831struct hc_sb_data 5832{ 5833 struct regpair_native host_sb_addr /* Host status block address */; 5834 struct hc_status_block_sm state_machine[HC_SB_MAX_SM] /* Holds the state machines of the status block */; 5835 struct pci_entity p_func /* vnic / port of the status block to be set by the driver */; 5836#if defined(__BIG_ENDIAN) 5837 uint8_t rsrv0; 5838 uint8_t state; 5839 uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */; 5840 uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */; 5841#elif defined(__LITTLE_ENDIAN) 5842 uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */; 5843 uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */; 5844 uint8_t state; 5845 uint8_t rsrv0; 5846#endif 5847 struct regpair_native rsrv1[2]; 5848}; 5849 5850 5851/* 5852 * Segment types for host coaslescing 5853 */ 5854enum hc_segment 5855{ 5856 HC_REGULAR_SEGMENT, 5857 HC_DEFAULT_SEGMENT, 5858 MAX_HC_SEGMENT}; 5859 5860 5861/* 5862 * The fast-path status block meta-data 5863 */ 5864struct hc_sp_status_block_data 5865{ 5866 struct regpair_native host_sb_addr /* Host status block address */; 5867#if defined(__BIG_ENDIAN) 5868 uint8_t rsrv1; 5869 uint8_t state; 5870 uint8_t igu_seg_id /* segment id of the IGU */; 5871 uint8_t igu_sb_id /* sb_id within the IGU */; 5872#elif defined(__LITTLE_ENDIAN) 5873 uint8_t igu_sb_id /* sb_id within the IGU */; 5874 uint8_t igu_seg_id /* segment id of the IGU */; 5875 uint8_t state; 5876 uint8_t rsrv1; 5877#endif 5878 struct pci_entity p_func /* vnic / port of the status block to be set by the driver */; 5879}; 5880 5881 5882/* 5883 * The fast-path status block meta-data 5884 */ 5885struct hc_status_block_data_e1x 5886{ 5887 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X] /* configuration/state parameters for a single protocol index */; 5888 struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */; 5889}; 5890 5891 5892/* 5893 * The fast-path status block meta-data 5894 */ 5895struct hc_status_block_data_e2 5896{ 5897 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2] /* configuration/state parameters for a single protocol index */; 5898 struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */; 5899}; 5900 5901 5902/* 5903 * IGU block operartion modes (in Everest2) 5904 */ 5905enum igu_mode 5906{ 5907 HC_IGU_BC_MODE /* Backward compatible mode */, 5908 HC_IGU_NBC_MODE /* Non-backward compatible mode */, 5909 MAX_IGU_MODE}; 5910 5911 5912/* 5913 * IP versions 5914 */ 5915enum ip_ver 5916{ 5917 IP_V4, 5918 IP_V6, 5919 MAX_IP_VER}; 5920 5921 5922/* 5923 * Malicious VF error ID 5924 */ 5925enum malicious_vf_error_id 5926{ 5927 VF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */, 5928 ETH_ILLEGAL_BD_LENGTHS /* TX BD lengths error was detected */, 5929 ETH_PACKET_TOO_SHORT /* TX packet is shorter then reported on BDs */, 5930 ETH_PAYLOAD_TOO_BIG /* TX packet is greater then MTU */, 5931 ETH_ILLEGAL_ETH_TYPE /* TX packet reported without VLAN but eth type is 0x8100 */, 5932 ETH_ILLEGAL_LSO_HDR_LEN /* LSO header length on BDs and on hdr_nbd do not match */, 5933 ETH_TOO_MANY_BDS /* Tx packet has too many BDs */, 5934 ETH_ZERO_HDR_NBDS /* hdr_nbds field is zero */, 5935 ETH_START_BD_NOT_SET /* start_bd should be set on first TX BD in packet */, 5936 ETH_ILLEGAL_PARSE_NBDS /* Tx packet with parse_nbds field which is not legal */, 5937 ETH_IPV6_AND_CHECKSUM /* Tx packet with IP checksum on IPv6 */, 5938 ETH_VLAN_FLG_INCORRECT /* Tx packet with incorrect VLAN flag */, 5939 ETH_ILLEGAL_LSO_MSS /* Tx LSO packet with illegal MSS value */, 5940 ETH_TUNNEL_NOT_SUPPORTED /* Tunneling packets are not supported in current connection */, 5941 MAX_MALICIOUS_VF_ERROR_ID}; 5942 5943 5944/* 5945 * Multi-function modes 5946 */ 5947enum mf_mode 5948{ 5949 SINGLE_FUNCTION, 5950 MULTI_FUNCTION_SD /* Switch dependent (vlan based) */, 5951 MULTI_FUNCTION_SI /* Switch independent (mac based) */, 5952 MULTI_FUNCTION_AFEX /* Switch dependent (niv based) */, 5953 MAX_MF_MODE}; 5954 5955 5956/* 5957 * Protocol-common statistics collected by the Tstorm (per pf) $$KEEP_ENDIANNESS$$ 5958 */ 5959struct tstorm_per_pf_stats 5960{ 5961 struct regpair rcv_error_bytes /* number of bytes received with errors */; 5962}; 5963 5964/* 5965 * $$KEEP_ENDIANNESS$$ 5966 */ 5967struct per_pf_stats 5968{ 5969 struct tstorm_per_pf_stats tstorm_pf_statistics; 5970}; 5971 5972 5973/* 5974 * Protocol-common statistics collected by the Tstorm (per port) $$KEEP_ENDIANNESS$$ 5975 */ 5976struct tstorm_per_port_stats 5977{ 5978 uint32_t mac_discard /* number of packets with mac errors */; 5979 uint32_t mac_filter_discard /* the number of good frames dropped because of no perfect match to MAC/VLAN address */; 5980 uint32_t brb_truncate_discard /* the number of packtes that were dropped because they were truncated in BRB */; 5981 uint32_t mf_tag_discard /* the number of good frames dropped because of no match to the outer vlan/VNtag */; 5982 uint32_t packet_drop /* general packet drop conter- incremented for every packet drop */; 5983 uint32_t reserved; 5984}; 5985 5986/* 5987 * $$KEEP_ENDIANNESS$$ 5988 */ 5989struct per_port_stats 5990{ 5991 struct tstorm_per_port_stats tstorm_port_statistics; 5992}; 5993 5994 5995/* 5996 * Protocol-common statistics collected by the Tstorm (per client) $$KEEP_ENDIANNESS$$ 5997 */ 5998struct tstorm_per_queue_stats 5999{ 6000 struct regpair rcv_ucast_bytes /* number of bytes in unicast packets received without errors and pass the filter */; 6001 uint32_t rcv_ucast_pkts /* number of unicast packets received without errors and pass the filter */; 6002 uint32_t checksum_discard /* number of total packets received with checksum error */; 6003 struct regpair rcv_bcast_bytes /* number of bytes in broadcast packets received without errors and pass the filter */; 6004 uint32_t rcv_bcast_pkts /* number of packets in broadcast packets received without errors and pass the filter */; 6005 uint32_t pkts_too_big_discard /* number of too long packets received */; 6006 struct regpair rcv_mcast_bytes /* number of bytes in multicast packets received without errors and pass the filter */; 6007 uint32_t rcv_mcast_pkts /* number of packets in multicast packets received without errors and pass the filter */; 6008 uint32_t ttl0_discard /* the number of good frames dropped because of TTL=0 */; 6009 uint16_t no_buff_discard; 6010 uint16_t reserved0; 6011 uint32_t reserved1; 6012}; 6013 6014/* 6015 * Protocol-common statistics collected by the Ustorm (per client) $$KEEP_ENDIANNESS$$ 6016 */ 6017struct ustorm_per_queue_stats 6018{ 6019 struct regpair ucast_no_buff_bytes /* the number of unicast bytes received from network dropped because of no buffer at host */; 6020 struct regpair mcast_no_buff_bytes /* the number of multicast bytes received from network dropped because of no buffer at host */; 6021 struct regpair bcast_no_buff_bytes /* the number of broadcast bytes received from network dropped because of no buffer at host */; 6022 uint32_t ucast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; 6023 uint32_t mcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; 6024 uint32_t bcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; 6025 uint32_t coalesced_pkts /* the number of packets coalesced in all aggregations */; 6026 struct regpair coalesced_bytes /* the number of bytes coalesced in all aggregations */; 6027 uint32_t coalesced_events /* the number of aggregations */; 6028 uint32_t coalesced_aborts /* the number of exception which avoid aggregation */; 6029}; 6030 6031/* 6032 * Protocol-common statistics collected by the Xstorm (per client) $$KEEP_ENDIANNESS$$ 6033 */ 6034struct xstorm_per_queue_stats 6035{ 6036 struct regpair ucast_bytes_sent /* number of total bytes sent without errors */; 6037 struct regpair mcast_bytes_sent /* number of total bytes sent without errors */; 6038 struct regpair bcast_bytes_sent /* number of total bytes sent without errors */; 6039 uint32_t ucast_pkts_sent /* number of total packets sent without errors */; 6040 uint32_t mcast_pkts_sent /* number of total packets sent without errors */; 6041 uint32_t bcast_pkts_sent /* number of total packets sent without errors */; 6042 uint32_t error_drop_pkts /* number of total packets drooped due to errors */; 6043}; 6044 6045/* 6046 * $$KEEP_ENDIANNESS$$ 6047 */ 6048struct per_queue_stats 6049{ 6050 struct tstorm_per_queue_stats tstorm_queue_statistics; 6051 struct ustorm_per_queue_stats ustorm_queue_statistics; 6052 struct xstorm_per_queue_stats xstorm_queue_statistics; 6053}; 6054 6055 6056/* 6057 * FW version stored in first line of pram $$KEEP_ENDIANNESS$$ 6058 */ 6059struct pram_fw_version 6060{ 6061 uint8_t major /* firmware current major version */; 6062 uint8_t minor /* firmware current minor version */; 6063 uint8_t revision /* firmware current revision version */; 6064 uint8_t engineering /* firmware current engineering version */; 6065 uint8_t flags; 6066#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */ 6067#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 6068#define PRAM_FW_VERSION_STORM_ID (0x3<<1) /* BitField flags storm_id identification */ 6069#define PRAM_FW_VERSION_STORM_ID_SHIFT 1 6070#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* BitField flags if set, this is big-endien ASM */ 6071#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 6072#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) /* BitField flags 0 - E1, 1 - E1H */ 6073#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 6074#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* BitField flags */ 6075#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 6076}; 6077 6078 6079/* 6080 * Ethernet slow path element 6081 */ 6082union protocol_common_specific_data 6083{ 6084 uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */; 6085 struct regpair phy_address /* SPE physical address */; 6086 struct regpair mac_config_addr /* physical address of the MAC configuration command, as allocated by the driver */; 6087 struct afex_vif_list_ramrod_data afex_vif_list_data /* The data afex vif list ramrod need */; 6088}; 6089 6090/* 6091 * The send queue element 6092 */ 6093struct protocol_common_spe 6094{ 6095 struct spe_hdr hdr /* SPE header */; 6096 union protocol_common_specific_data data /* data specific to common protocol */; 6097}; 6098 6099 6100/* 6101 * The data for the Set Timesync Ramrod $$KEEP_ENDIANNESS$$ 6102 */ 6103struct set_timesync_ramrod_data 6104{ 6105 uint8_t drift_adjust_cmd /* Timesync Drift Adjust Command */; 6106 uint8_t offset_cmd /* Timesync Offset Command */; 6107 uint8_t add_sub_drift_adjust_value /* Whether to add(1)/subtract(0) Drift Adjust Value from the Offset */; 6108 uint8_t drift_adjust_value /* Drift Adjust Value (in ns) */; 6109 uint32_t drift_adjust_period /* Drift Adjust Period (in us) */; 6110 struct regpair offset_delta /* Timesync Offset Delta (in ns) */; 6111}; 6112 6113 6114/* 6115 * The send queue element 6116 */ 6117struct slow_path_element 6118{ 6119 struct spe_hdr hdr /* common data for all protocols */; 6120 struct regpair protocol_data /* additional data specific to the protocol */; 6121}; 6122 6123 6124/* 6125 * Protocol-common statistics counter $$KEEP_ENDIANNESS$$ 6126 */ 6127struct stats_counter 6128{ 6129 uint16_t xstats_counter /* xstorm statistics counter */; 6130 uint16_t reserved0; 6131 uint32_t reserved1; 6132 uint16_t tstats_counter /* tstorm statistics counter */; 6133 uint16_t reserved2; 6134 uint32_t reserved3; 6135 uint16_t ustats_counter /* ustorm statistics counter */; 6136 uint16_t reserved4; 6137 uint32_t reserved5; 6138 uint16_t cstats_counter /* ustorm statistics counter */; 6139 uint16_t reserved6; 6140 uint32_t reserved7; 6141}; 6142 6143 6144/* 6145 * $$KEEP_ENDIANNESS$$ 6146 */ 6147struct stats_query_entry 6148{ 6149 uint8_t kind; 6150 uint8_t index /* queue index */; 6151 uint16_t funcID /* the func the statistic will send to */; 6152 uint32_t reserved; 6153 struct regpair address /* pxp address */; 6154}; 6155 6156/* 6157 * statistic command $$KEEP_ENDIANNESS$$ 6158 */ 6159struct stats_query_cmd_group 6160{ 6161 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 6162}; 6163 6164 6165/* 6166 * statistic command header $$KEEP_ENDIANNESS$$ 6167 */ 6168struct stats_query_header 6169{ 6170 uint8_t cmd_num /* command number */; 6171 uint8_t reserved0; 6172 uint16_t drv_stats_counter; 6173 uint32_t reserved1; 6174 struct regpair stats_counters_addrs /* stats counter */; 6175}; 6176 6177 6178/* 6179 * Types of statistcis query entry 6180 */ 6181enum stats_query_type 6182{ 6183 STATS_TYPE_QUEUE, 6184 STATS_TYPE_PORT, 6185 STATS_TYPE_PF, 6186 STATS_TYPE_TOE, 6187 STATS_TYPE_FCOE, 6188 MAX_STATS_QUERY_TYPE}; 6189 6190 6191/* 6192 * Indicate of the function status block state 6193 */ 6194enum status_block_state 6195{ 6196 SB_DISABLED, 6197 SB_ENABLED, 6198 SB_CLEANED, 6199 MAX_STATUS_BLOCK_STATE}; 6200 6201 6202/* 6203 * Storm IDs (including attentions for IGU related enums) 6204 */ 6205enum storm_id 6206{ 6207 USTORM_ID, 6208 CSTORM_ID, 6209 XSTORM_ID, 6210 TSTORM_ID, 6211 ATTENTION_ID, 6212 MAX_STORM_ID}; 6213 6214 6215/* 6216 * Taffic types used in ETS and flow control algorithms 6217 */ 6218enum traffic_type 6219{ 6220 LLFC_TRAFFIC_TYPE_NW /* Networking */, 6221 LLFC_TRAFFIC_TYPE_FCOE /* FCoE */, 6222 LLFC_TRAFFIC_TYPE_ISCSI /* iSCSI */, 6223 MAX_TRAFFIC_TYPE}; 6224 6225 6226/* 6227 * zone A per-queue data 6228 */ 6229struct tstorm_queue_zone_data 6230{ 6231 struct regpair reserved[4]; 6232}; 6233 6234 6235/* 6236 * zone B per-VF data 6237 */ 6238struct tstorm_vf_zone_data 6239{ 6240 struct regpair reserved; 6241}; 6242 6243 6244/* 6245 * Add or Subtract Value for Set Timesync Ramrod 6246 */ 6247enum ts_add_sub_value 6248{ 6249 TS_SUB_VALUE /* Subtract Value */, 6250 TS_ADD_VALUE /* Add Value */, 6251 MAX_TS_ADD_SUB_VALUE}; 6252 6253 6254/* 6255 * Drift-Adjust Commands for Set Timesync Ramrod 6256 */ 6257enum ts_drift_adjust_cmd 6258{ 6259 TS_DRIFT_ADJUST_KEEP /* Keep Drift-Adjust at current values */, 6260 TS_DRIFT_ADJUST_SET /* Set Drift-Adjust */, 6261 TS_DRIFT_ADJUST_RESET /* Reset Drift-Adjust */, 6262 MAX_TS_DRIFT_ADJUST_CMD}; 6263 6264 6265/* 6266 * Offset Commands for Set Timesync Ramrod 6267 */ 6268enum ts_offset_cmd 6269{ 6270 TS_OFFSET_KEEP /* Keep Offset at current values */, 6271 TS_OFFSET_INC /* Increase Offset by Offset Delta */, 6272 TS_OFFSET_DEC /* Decrease Offset by Offset Delta */, 6273 MAX_TS_OFFSET_CMD}; 6274 6275 6276/* 6277 * zone A per-queue data 6278 */ 6279struct ustorm_queue_zone_data 6280{ 6281 struct ustorm_eth_rx_producers eth_rx_producers /* ETH RX rings producers */; 6282 struct regpair reserved[3]; 6283}; 6284 6285 6286/* 6287 * zone B per-VF data 6288 */ 6289struct ustorm_vf_zone_data 6290{ 6291 struct regpair reserved; 6292}; 6293 6294 6295/* 6296 * data per VF-PF channel 6297 */ 6298struct vf_pf_channel_data 6299{ 6300#if defined(__BIG_ENDIAN) 6301 uint16_t reserved0; 6302 uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */; 6303 uint8_t state /* channel state (ready / waiting for ack) */; 6304#elif defined(__LITTLE_ENDIAN) 6305 uint8_t state /* channel state (ready / waiting for ack) */; 6306 uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */; 6307 uint16_t reserved0; 6308#endif 6309 uint32_t reserved1; 6310}; 6311 6312 6313/* 6314 * State of VF-PF channel 6315 */ 6316enum vf_pf_channel_state 6317{ 6318 VF_PF_CHANNEL_STATE_READY /* Channel is ready to accept a message from VF */, 6319 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK /* Channel waits for an ACK from PF */, 6320 MAX_VF_PF_CHANNEL_STATE}; 6321 6322 6323/* 6324 * vif_list_rule_kind 6325 */ 6326enum vif_list_rule_kind 6327{ 6328 VIF_LIST_RULE_SET, 6329 VIF_LIST_RULE_GET, 6330 VIF_LIST_RULE_CLEAR_ALL, 6331 VIF_LIST_RULE_CLEAR_FUNC, 6332 MAX_VIF_LIST_RULE_KIND}; 6333 6334 6335/* 6336 * zone A per-queue data 6337 */ 6338struct xstorm_queue_zone_data 6339{ 6340 struct regpair reserved[4]; 6341}; 6342 6343 6344/* 6345 * zone B per-VF data 6346 */ 6347struct xstorm_vf_zone_data 6348{ 6349 struct regpair reserved; 6350}; 6351 6352 6353#endif /* ECORE_HSI_H */ 6354 6355