1/*- 2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#ifndef ELINK_H 31#define ELINK_H 32 33#define ELINK_DEBUG 34 35 36 37 38 39 40/***********************************************************/ 41/* CLC Call backs functions */ 42/***********************************************************/ 43/* CLC device structure */ 44struct bxe_softc; 45 46extern uint32_t elink_cb_reg_read(struct bxe_softc *sc, uint32_t reg_addr); 47extern void elink_cb_reg_write(struct bxe_softc *sc, uint32_t reg_addr, uint32_t val); 48/* wb_write - pointer to 2 32 bits vars to be passed to the DMAE*/ 49extern void elink_cb_reg_wb_write(struct bxe_softc *sc, uint32_t offset, 50 uint32_t *wb_write, uint16_t len); 51extern void elink_cb_reg_wb_read(struct bxe_softc *sc, uint32_t offset, 52 uint32_t *wb_write, uint16_t len); 53 54/* mode - 0( LOW ) /1(HIGH)*/ 55extern uint8_t elink_cb_gpio_write(struct bxe_softc *sc, 56 uint16_t gpio_num, 57 uint8_t mode, uint8_t port); 58extern uint8_t elink_cb_gpio_mult_write(struct bxe_softc *sc, 59 uint8_t pins, 60 uint8_t mode); 61 62extern uint32_t elink_cb_gpio_read(struct bxe_softc *sc, uint16_t gpio_num, uint8_t port); 63extern uint8_t elink_cb_gpio_int_write(struct bxe_softc *sc, 64 uint16_t gpio_num, 65 uint8_t mode, uint8_t port); 66 67extern uint32_t elink_cb_fw_command(struct bxe_softc *sc, uint32_t command, uint32_t param); 68 69/* Delay */ 70extern void elink_cb_udelay(struct bxe_softc *sc, uint32_t microsecond); 71 72/* This function is called every 1024 bytes downloading of phy firmware. 73Driver can use it to print to screen indication for download progress */ 74extern void elink_cb_download_progress(struct bxe_softc *sc, uint32_t cur, uint32_t total); 75 76/* Each log type has its own parameters */ 77typedef enum elink_log_id { 78 ELINK_LOG_ID_UNQUAL_IO_MODULE = 0, /* uint8_t port, const char* vendor_name, const char* vendor_pn */ 79 ELINK_LOG_ID_OVER_CURRENT = 1, /* uint8_t port */ 80 ELINK_LOG_ID_PHY_UNINITIALIZED = 2, /* uint8_t port */ 81 ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT= 3, /* No params */ 82 ELINK_LOG_ID_NON_10G_MODULE = 4, /* uint8_t port */ 83}elink_log_id_t; 84 85typedef enum elink_status { 86 ELINK_STATUS_OK = 0, 87 ELINK_STATUS_ERROR, 88 ELINK_STATUS_TIMEOUT, 89 ELINK_STATUS_NO_LINK, 90 ELINK_STATUS_INVALID_IMAGE, 91 ELINK_OP_NOT_SUPPORTED = 122 92} elink_status_t; 93extern void elink_cb_event_log(struct bxe_softc *sc, const elink_log_id_t log_id, ...); 94extern void elink_cb_load_warpcore_microcode(void); 95 96extern uint8_t elink_cb_path_id(struct bxe_softc *sc); 97 98extern void elink_cb_notify_link_changed(struct bxe_softc *sc); 99 100#define ELINK_EVENT_LOG_LEVEL_ERROR 1 101#define ELINK_EVENT_LOG_LEVEL_WARNING 2 102#define ELINK_EVENT_ID_SFP_UNQUALIFIED_MODULE 1 103#define ELINK_EVENT_ID_SFP_POWER_FAULT 2 104 105#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) 106/* Debug prints */ 107#ifdef ELINK_DEBUG 108 109extern void elink_cb_dbg(struct bxe_softc *sc, char *fmt); 110extern void elink_cb_dbg1(struct bxe_softc *sc, char *fmt, uint32_t arg1); 111extern void elink_cb_dbg2(struct bxe_softc *sc, char *fmt, uint32_t arg1, uint32_t arg2); 112extern void elink_cb_dbg3(struct bxe_softc *sc, char *fmt, uint32_t arg1, uint32_t arg2, 113 uint32_t arg3); 114 115#define ELINK_DEBUG_P0(sc, fmt) elink_cb_dbg(sc, fmt) 116#define ELINK_DEBUG_P1(sc, fmt, arg1) elink_cb_dbg1(sc, fmt, arg1) 117#define ELINK_DEBUG_P2(sc, fmt, arg1, arg2) elink_cb_dbg2(sc, fmt, arg1, arg2) 118#define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3) \ 119 elink_cb_dbg3(sc, fmt, arg1, arg2, arg3) 120#else 121#define ELINK_DEBUG_P0(sc, fmt) 122#define ELINK_DEBUG_P1(sc, fmt, arg1) 123#define ELINK_DEBUG_P2(sc, fmt, arg1, arg2) 124#define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3) 125#endif 126 127/***********************************************************/ 128/* Defines */ 129/***********************************************************/ 130#define ELINK_DEFAULT_PHY_DEV_ADDR 3 131#define ELINK_E2_DEFAULT_PHY_DEV_ADDR 5 132 133 134#define DUPLEX_FULL 1 135#define DUPLEX_HALF 2 136 137#define ELINK_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO 138#define ELINK_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX 139#define ELINK_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX 140#define ELINK_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH 141#define ELINK_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE 142 143#define ELINK_NET_SERDES_IF_XFI 1 144#define ELINK_NET_SERDES_IF_SFI 2 145#define ELINK_NET_SERDES_IF_KR 3 146#define ELINK_NET_SERDES_IF_DXGXS 4 147 148#define ELINK_SPEED_AUTO_NEG 0 149#define ELINK_SPEED_10 10 150#define ELINK_SPEED_100 100 151#define ELINK_SPEED_1000 1000 152#define ELINK_SPEED_2500 2500 153#define ELINK_SPEED_10000 10000 154#define ELINK_SPEED_20000 20000 155 156#define ELINK_I2C_DEV_ADDR_A0 0xa0 157#define ELINK_I2C_DEV_ADDR_A2 0xa2 158 159#define ELINK_SFP_EEPROM_PAGE_SIZE 16 160#define ELINK_SFP_EEPROM_VENDOR_NAME_ADDR 0x14 161#define ELINK_SFP_EEPROM_VENDOR_NAME_SIZE 16 162#define ELINK_SFP_EEPROM_VENDOR_OUI_ADDR 0x25 163#define ELINK_SFP_EEPROM_VENDOR_OUI_SIZE 3 164#define ELINK_SFP_EEPROM_PART_NO_ADDR 0x28 165#define ELINK_SFP_EEPROM_PART_NO_SIZE 16 166#define ELINK_SFP_EEPROM_REVISION_ADDR 0x38 167#define ELINK_SFP_EEPROM_REVISION_SIZE 4 168#define ELINK_SFP_EEPROM_SERIAL_ADDR 0x44 169#define ELINK_SFP_EEPROM_SERIAL_SIZE 16 170#define ELINK_SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */ 171#define ELINK_SFP_EEPROM_DATE_SIZE 6 172#define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR 0x5c 173#define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE 1 174#define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2) 175#define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e 176#define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE 1 177 178#define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e 179#define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR 0x5f 180 181#define ELINK_PWR_FLT_ERR_MSG_LEN 250 182 183#define ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config) \ 184 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) 185#define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config) \ 186 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \ 187 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT) 188#define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \ 189 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) 190 191/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */ 192#define ELINK_SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1) 193/* Single Media board contains single external phy */ 194#define ELINK_SINGLE_MEDIA(params) (params->num_phys == 2) 195/* Dual Media board contains two external phy with different media */ 196#define ELINK_DUAL_MEDIA(params) (params->num_phys == 3) 197 198#define ELINK_FW_PARAM_PHY_ADDR_MASK 0x000000FF 199#define ELINK_FW_PARAM_PHY_TYPE_MASK 0x0000FF00 200#define ELINK_FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000 201#define ELINK_FW_PARAM_MDIO_CTRL_OFFSET 16 202#define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \ 203 ELINK_FW_PARAM_PHY_ADDR_MASK) 204#define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \ 205 ELINK_FW_PARAM_PHY_TYPE_MASK) 206#define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \ 207 ELINK_FW_PARAM_MDIO_CTRL_MASK) >> \ 208 ELINK_FW_PARAM_MDIO_CTRL_OFFSET) 209#define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \ 210 (phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET) 211 212 213#define ELINK_PFC_BRB_FULL_LB_XOFF_THRESHOLD 170 214#define ELINK_PFC_BRB_FULL_LB_XON_THRESHOLD 250 215 216#define ELINK_MAXVAL(a, b) (((a) > (b)) ? (a) : (b)) 217 218#define ELINK_BMAC_CONTROL_RX_ENABLE 2 219/***********************************************************/ 220/* Structs */ 221/***********************************************************/ 222#define ELINK_INT_PHY 0 223#define ELINK_EXT_PHY1 1 224#define ELINK_EXT_PHY2 2 225#define ELINK_MAX_PHYS 3 226 227/* Same configuration is shared between the XGXS and the first external phy */ 228#define ELINK_LINK_CONFIG_SIZE (ELINK_MAX_PHYS - 1) 229#define ELINK_LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == ELINK_INT_PHY) ? \ 230 0 : (_phy_idx - 1)) 231/***********************************************************/ 232/* elink_phy struct */ 233/* Defines the required arguments and function per phy */ 234/***********************************************************/ 235struct elink_vars; 236struct elink_params; 237struct elink_phy; 238 239typedef uint8_t (*config_init_t)(struct elink_phy *phy, struct elink_params *params, 240 struct elink_vars *vars); 241typedef uint8_t (*read_status_t)(struct elink_phy *phy, struct elink_params *params, 242 struct elink_vars *vars); 243typedef void (*link_reset_t)(struct elink_phy *phy, 244 struct elink_params *params); 245typedef void (*config_loopback_t)(struct elink_phy *phy, 246 struct elink_params *params); 247typedef uint8_t (*format_fw_ver_t)(uint32_t raw, uint8_t *str, uint16_t *len); 248typedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params); 249typedef void (*set_link_led_t)(struct elink_phy *phy, 250 struct elink_params *params, uint8_t mode); 251typedef void (*phy_specific_func_t)(struct elink_phy *phy, 252 struct elink_params *params, uint32_t action); 253struct elink_reg_set { 254 uint8_t devad; 255 uint16_t reg; 256 uint16_t val; 257}; 258 259struct elink_phy { 260 uint32_t type; 261 262 /* Loaded during init */ 263 uint8_t addr; 264 uint8_t def_md_devad; 265 uint16_t flags; 266 /* No Over-Current detection */ 267#define ELINK_FLAGS_NOC (1<<1) 268 /* Fan failure detection required */ 269#define ELINK_FLAGS_FAN_FAILURE_DET_REQ (1<<2) 270 /* Initialize first the XGXS and only then the phy itself */ 271#define ELINK_FLAGS_INIT_XGXS_FIRST (1<<3) 272#define ELINK_FLAGS_WC_DUAL_MODE (1<<4) 273#define ELINK_FLAGS_4_PORT_MODE (1<<5) 274#define ELINK_FLAGS_REARM_LATCH_SIGNAL (1<<6) 275#define ELINK_FLAGS_SFP_NOT_APPROVED (1<<7) 276#define ELINK_FLAGS_MDC_MDIO_WA (1<<8) 277#define ELINK_FLAGS_DUMMY_READ (1<<9) 278#define ELINK_FLAGS_MDC_MDIO_WA_B0 (1<<10) 279#define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC (1<<11) 280#define ELINK_FLAGS_TX_ERROR_CHECK (1<<12) 281#define ELINK_FLAGS_EEE (1<<13) 282#define ELINK_FLAGS_TEMPERATURE (1<<14) 283#define ELINK_FLAGS_MDC_MDIO_WA_G (1<<15) 284 285 /* preemphasis values for the rx side */ 286 uint16_t rx_preemphasis[4]; 287 288 /* preemphasis values for the tx side */ 289 uint16_t tx_preemphasis[4]; 290 291 /* EMAC address for access MDIO */ 292 uint32_t mdio_ctrl; 293 294 uint32_t supported; 295#define ELINK_SUPPORTED_10baseT_Half (1<<0) 296#define ELINK_SUPPORTED_10baseT_Full (1<<1) 297#define ELINK_SUPPORTED_100baseT_Half (1<<2) 298#define ELINK_SUPPORTED_100baseT_Full (1<<3) 299#define ELINK_SUPPORTED_1000baseT_Full (1<<4) 300#define ELINK_SUPPORTED_2500baseX_Full (1<<5) 301#define ELINK_SUPPORTED_10000baseT_Full (1<<6) 302#define ELINK_SUPPORTED_TP (1<<7) 303#define ELINK_SUPPORTED_FIBRE (1<<8) 304#define ELINK_SUPPORTED_Autoneg (1<<9) 305#define ELINK_SUPPORTED_Pause (1<<10) 306#define ELINK_SUPPORTED_Asym_Pause (1<<11) 307#define ELINK_SUPPORTED_20000baseMLD2_Full (1<<21) 308#define ELINK_SUPPORTED_20000baseKR2_Full (1<<22) 309 310 uint32_t media_type; 311#define ELINK_ETH_PHY_UNSPECIFIED 0x0 312#define ELINK_ETH_PHY_SFPP_10G_FIBER 0x1 313#define ELINK_ETH_PHY_XFP_FIBER 0x2 314#define ELINK_ETH_PHY_DA_TWINAX 0x3 315#define ELINK_ETH_PHY_BASE_T 0x4 316#define ELINK_ETH_PHY_SFP_1G_FIBER 0x5 317#define ELINK_ETH_PHY_KR 0xf0 318#define ELINK_ETH_PHY_CX4 0xf1 319#define ELINK_ETH_PHY_NOT_PRESENT 0xff 320 321 /* The address in which version is located*/ 322 uint32_t ver_addr; 323 324 uint16_t req_flow_ctrl; 325 326 uint16_t req_line_speed; 327 328 uint32_t speed_cap_mask; 329 330 uint16_t req_duplex; 331 uint16_t rsrv; 332 /* Called per phy/port init, and it configures LASI, speed, autoneg, 333 duplex, flow control negotiation, etc. */ 334 config_init_t config_init; 335 336 /* Called due to interrupt. It determines the link, speed */ 337 read_status_t read_status; 338 339 /* Called when driver is unloading. Should reset the phy */ 340 link_reset_t link_reset; 341 342 /* Set the loopback configuration for the phy */ 343 config_loopback_t config_loopback; 344 345 /* Format the given raw number into str up to len */ 346 format_fw_ver_t format_fw_ver; 347 348 /* Reset the phy (both ports) */ 349 hw_reset_t hw_reset; 350 351 /* Set link led mode (on/off/oper)*/ 352 set_link_led_t set_link_led; 353 354 /* PHY Specific tasks */ 355 phy_specific_func_t phy_specific_func; 356#define ELINK_DISABLE_TX 1 357#define ELINK_ENABLE_TX 2 358#define ELINK_PHY_INIT 3 359}; 360 361/* Inputs parameters to the CLC */ 362struct elink_params { 363 364 uint8_t port; 365 366 /* Default / User Configuration */ 367 uint8_t loopback_mode; 368#define ELINK_LOOPBACK_NONE 0 369#define ELINK_LOOPBACK_EMAC 1 370#define ELINK_LOOPBACK_BMAC 2 371#define ELINK_LOOPBACK_XGXS 3 372#define ELINK_LOOPBACK_EXT_PHY 4 373#define ELINK_LOOPBACK_EXT 5 374#define ELINK_LOOPBACK_UMAC 6 375#define ELINK_LOOPBACK_XMAC 7 376 377 /* Device parameters */ 378 uint8_t mac_addr[6]; 379 380 uint16_t req_duplex[ELINK_LINK_CONFIG_SIZE]; 381 uint16_t req_flow_ctrl[ELINK_LINK_CONFIG_SIZE]; 382 383 uint16_t req_line_speed[ELINK_LINK_CONFIG_SIZE]; /* Also determine AutoNeg */ 384 385 /* shmem parameters */ 386 uint32_t shmem_base; 387 uint32_t shmem2_base; 388 uint32_t speed_cap_mask[ELINK_LINK_CONFIG_SIZE]; 389 uint32_t switch_cfg; 390#define ELINK_SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH 391#define ELINK_SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH 392#define ELINK_SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT 393 394 uint32_t lane_config; 395 396 /* Phy register parameter */ 397 uint32_t chip_id; 398 399 /* features */ 400 uint32_t feature_config_flags; 401#define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) 402#define ELINK_FEATURE_CONFIG_PFC_ENABLED (1<<1) 403#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2) 404#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3) 405#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC (1<<4) 406#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC (1<<5) 407#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC (1<<6) 408#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC (1<<7) 409#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8) 410#define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9) 411#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10) 412#define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11) 413#define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST (1<<12) 414#define ELINK_FEATURE_CONFIG_MT_SUPPORT (1<<13) 415#define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN (1<<14) 416 417 /* Will be populated during common init */ 418 struct elink_phy phy[ELINK_MAX_PHYS]; 419 420 /* Will be populated during common init */ 421 uint8_t num_phys; 422 423 uint8_t rsrv; 424 425 /* Used to configure the EEE Tx LPI timer, has several modes of 426 * operation, according to bits 29:28 - 427 * 2'b00: Timer will be configured by nvram, output will be the value 428 * from nvram. 429 * 2'b01: Timer will be configured by nvram, output will be in 430 * microseconds. 431 * 2'b10: bits 1:0 contain an nvram value which will be used instead 432 * of the one located in the nvram. Output will be that value. 433 * 2'b11: bits 19:0 contain the idle timer in microseconds; output 434 * will be in microseconds. 435 * Bits 31:30 should be 2'b11 in order for EEE to be enabled. 436 */ 437 uint32_t eee_mode; 438#define ELINK_EEE_MODE_NVRAM_BALANCED_TIME (0xa00) 439#define ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100) 440#define ELINK_EEE_MODE_NVRAM_LATENCY_TIME (0x6000) 441#define ELINK_EEE_MODE_NVRAM_MASK (0x3) 442#define ELINK_EEE_MODE_TIMER_MASK (0xfffff) 443#define ELINK_EEE_MODE_OUTPUT_TIME (1<<28) 444#define ELINK_EEE_MODE_OVERRIDE_NVRAM (1<<29) 445#define ELINK_EEE_MODE_ENABLE_LPI (1<<30) 446#define ELINK_EEE_MODE_ADV_LPI (1<<31) 447 448 uint16_t hw_led_mode; /* part of the hw_config read from the shmem */ 449 uint32_t multi_phy_config; 450 451 /* Device pointer passed to all callback functions */ 452 struct bxe_softc *sc; 453 uint16_t req_fc_auto_adv; /* Should be set to TX / BOTH when 454 req_flow_ctrl is set to AUTO */ 455 uint16_t link_flags; 456#define ELINK_LINK_FLAGS_INT_DISABLED (1<<0) 457#define ELINK_PHY_INITIALIZED (1<<1) 458 uint32_t lfa_base; 459}; 460 461/* Output parameters */ 462struct elink_vars { 463 uint8_t phy_flags; 464#define PHY_XGXS_FLAG (1<<0) 465#define PHY_SGMII_FLAG (1<<1) 466#define PHY_PHYSICAL_LINK_FLAG (1<<2) 467#define PHY_HALF_OPEN_CONN_FLAG (1<<3) 468#define PHY_OVER_CURRENT_FLAG (1<<4) 469#define PHY_SFP_TX_FAULT_FLAG (1<<5) 470 471 uint8_t mac_type; 472#define ELINK_MAC_TYPE_NONE 0 473#define ELINK_MAC_TYPE_EMAC 1 474#define ELINK_MAC_TYPE_BMAC 2 475#define ELINK_MAC_TYPE_UMAC 3 476#define ELINK_MAC_TYPE_XMAC 4 477 478 uint8_t phy_link_up; /* internal phy link indication */ 479 uint8_t link_up; 480 481 uint16_t line_speed; 482 uint16_t duplex; 483 484 uint16_t flow_ctrl; 485 uint16_t ieee_fc; 486 487 /* The same definitions as the shmem parameter */ 488 uint32_t link_status; 489 uint32_t eee_status; 490 uint8_t fault_detected; 491 uint8_t check_kr2_recovery_cnt; 492#define ELINK_CHECK_KR2_RECOVERY_CNT 5 493 uint16_t periodic_flags; 494#define ELINK_PERIODIC_FLAGS_LINK_EVENT 0x0001 495 496 uint32_t aeu_int_mask; 497 uint8_t rx_tx_asic_rst; 498 uint8_t turn_to_run_wc_rt; 499 uint16_t rsrv2; 500 /* The same definitions as the shmem2 parameter */ 501 uint32_t link_attr_sync; 502}; 503 504/***********************************************************/ 505/* Functions */ 506/***********************************************************/ 507elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars); 508 509/* Reset the link. Should be called when driver or interface goes down 510 Before calling phy firmware upgrade, the reset_ext_phy should be set 511 to 0 */ 512elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars, 513 uint8_t reset_ext_phy); 514elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars); 515/* elink_link_update should be called upon link interrupt */ 516elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars); 517 518/* use the following phy functions to read/write from external_phy 519 In order to use it to read/write internal phy registers, use 520 ELINK_DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as 521 the register */ 522elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr, 523 uint8_t devad, uint16_t reg, uint16_t *ret_val); 524 525elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr, 526 uint8_t devad, uint16_t reg, uint16_t val); 527 528/* Reads the link_status from the shmem, 529 and update the link vars accordingly */ 530void elink_link_status_update(struct elink_params *input, 531 struct elink_vars *output); 532/* returns string representing the fw_version of the external phy */ 533elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, uint8_t *version, 534 uint16_t len); 535 536/* Set/Unset the led 537 Basically, the CLC takes care of the led for the link, but in case one needs 538 to set/unset the led unnaturally, set the "mode" to ELINK_LED_MODE_OPER to 539 blink the led, and ELINK_LED_MODE_OFF to set the led off.*/ 540elink_status_t elink_set_led(struct elink_params *params, 541 struct elink_vars *vars, uint8_t mode, uint32_t speed); 542#define ELINK_LED_MODE_OFF 0 543#define ELINK_LED_MODE_ON 1 544#define ELINK_LED_MODE_OPER 2 545#define ELINK_LED_MODE_FRONT_PANEL_OFF 3 546 547/* elink_handle_module_detect_int should be called upon module detection 548 interrupt */ 549void elink_handle_module_detect_int(struct elink_params *params); 550 551/* Get the actual link status. In case it returns ELINK_STATUS_OK, link is up, 552 otherwise link is down*/ 553elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars, 554 uint8_t is_serdes); 555 556 557/* One-time initialization for external phy after power up */ 558elink_status_t elink_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base_path[], 559 uint32_t shmem2_base_path[], uint32_t chip_id, uint8_t one_port_enabled); 560 561/* Reset the external PHY using GPIO */ 562void elink_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port); 563 564/* Reset the external of SFX7101 */ 565void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy); 566 567/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */ 568elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy, 569 struct elink_params *params, uint8_t dev_addr, 570 uint16_t addr, uint16_t byte_cnt, uint8_t *o_buf); 571 572void elink_hw_reset_phy(struct elink_params *params); 573 574/* Check swap bit and adjust PHY order */ 575uint32_t elink_phy_selection(struct elink_params *params); 576 577/* Probe the phys on board, and populate them in "params" */ 578elink_status_t elink_phy_probe(struct elink_params *params); 579 580/* Checks if fan failure detection is required on one of the phys on board */ 581uint8_t elink_fan_failure_det_req(struct bxe_softc *sc, uint32_t shmem_base, 582 uint32_t shmem2_base, uint8_t port); 583 584/* Open / close the gate between the NIG and the BRB */ 585void elink_set_rx_filter(struct elink_params *params, uint8_t en); 586 587/* DCBX structs */ 588 589/* Number of maximum COS per chip */ 590#define ELINK_DCBX_E2E3_MAX_NUM_COS (2) 591#define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0 (6) 592#define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 (3) 593#define ELINK_DCBX_E3B0_MAX_NUM_COS ( \ 594 ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0, \ 595 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1)) 596 597#define ELINK_DCBX_MAX_NUM_COS ( \ 598 ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS, \ 599 ELINK_DCBX_E2E3_MAX_NUM_COS)) 600 601/* PFC port configuration params */ 602struct elink_nig_brb_pfc_port_params { 603 /* NIG */ 604 uint32_t pause_enable; 605 uint32_t llfc_out_en; 606 uint32_t llfc_enable; 607 uint32_t pkt_priority_to_cos; 608 uint8_t num_of_rx_cos_priority_mask; 609 uint32_t rx_cos_priority_mask[ELINK_DCBX_MAX_NUM_COS]; 610 uint32_t llfc_high_priority_classes; 611 uint32_t llfc_low_priority_classes; 612}; 613 614 615/* ETS port configuration params */ 616struct elink_ets_bw_params { 617 uint8_t bw; 618}; 619 620struct elink_ets_sp_params { 621 /** 622 * valid values are 0 - 5. 0 is highest strict priority. 623 * There can't be two COS's with the same pri. 624 */ 625 uint8_t pri; 626}; 627 628enum elink_cos_state { 629 elink_cos_state_strict = 0, 630 elink_cos_state_bw = 1, 631}; 632 633struct elink_ets_cos_params { 634 enum elink_cos_state state ; 635 union { 636 struct elink_ets_bw_params bw_params; 637 struct elink_ets_sp_params sp_params; 638 } params; 639}; 640 641struct elink_ets_params { 642 uint8_t num_of_cos; /* Number of valid COS entries*/ 643 struct elink_ets_cos_params cos[ELINK_DCBX_MAX_NUM_COS]; 644}; 645 646/* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB 647 * when link is already up 648 */ 649elink_status_t elink_update_pfc(struct elink_params *params, 650 struct elink_vars *vars, 651 struct elink_nig_brb_pfc_port_params *pfc_params); 652 653 654/* Used to configure the ETS to disable */ 655elink_status_t elink_ets_disabled(struct elink_params *params, 656 struct elink_vars *vars); 657 658/* Used to configure the ETS to BW limited */ 659void elink_ets_bw_limit(const struct elink_params *params, const uint32_t cos0_bw, 660 const uint32_t cos1_bw); 661 662/* Used to configure the ETS to strict */ 663elink_status_t elink_ets_strict(const struct elink_params *params, const uint8_t strict_cos); 664 665 666/* Configure the COS to ETS according to BW and SP settings.*/ 667elink_status_t elink_ets_e3b0_config(const struct elink_params *params, 668 const struct elink_vars *vars, 669 struct elink_ets_params *ets_params); 670/* Read pfc statistic*/ 671void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars, 672 uint32_t pfc_frames_sent[2], 673 uint32_t pfc_frames_received[2]); 674void elink_init_mod_abs_int(struct bxe_softc *sc, struct elink_vars *vars, 675 uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base, 676 uint8_t port); 677 678elink_status_t elink_sfp_module_detection(struct elink_phy *phy, 679 struct elink_params *params); 680 681void elink_period_func(struct elink_params *params, struct elink_vars *vars); 682 683elink_status_t elink_check_half_open_conn(struct elink_params *params, 684 struct elink_vars *vars, uint8_t notify); 685 686void elink_enable_pmd_tx(struct elink_params *params); 687 688 689 690#endif /* ELINK_H */ 691 692