1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19#ifndef _ATH_AR5416_DESC_H_ 20#define _ATH_AR5416_DESC_H_ 21 22/* 23 * Hardware-specific descriptor structures. 24 */ 25 26/* XXX Need to replace this with a dynamic 27 * method of determining Owl2 if possible 28 */ 29#define _get_index(_ah) ( IS_5416V1(_ah) ? -4 : 0 ) 30#define AR5416_DS_TXSTATUS(_ah, _ads) \ 31 ((uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)])) 32#define AR5416_DS_TXSTATUS_CONST(_ah, _ads) \ 33 ((const uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)])) 34 35#define AR5416_NUM_TX_STATUS 10 /* Number of TX status words */ 36/* Clear the whole descriptor */ 37#define AR5416_DESC_TX_CTL_SZ sizeof(struct ar5416_tx_desc) 38 39struct ar5416_tx_desc { /* tx desc has 12 control words + 10 status words */ 40 uint32_t ctl2; 41 uint32_t ctl3; 42 uint32_t ctl4; 43 uint32_t ctl5; 44 uint32_t ctl6; 45 uint32_t ctl7; 46 uint32_t ctl8; 47 uint32_t ctl9; 48 uint32_t ctl10; 49 uint32_t ctl11; 50 uint32_t status[AR5416_NUM_TX_STATUS]; 51}; 52 53struct ar5416_rx_desc { /* rx desc has 2 control words + 9 status words */ 54 uint32_t status0; 55 uint32_t status1; 56 uint32_t status2; 57 uint32_t status3; 58 uint32_t status4; 59 uint32_t status5; 60 uint32_t status6; 61 uint32_t status7; 62 uint32_t status8; 63}; 64 65 66struct ar5416_desc { 67 uint32_t ds_link; /* link pointer */ 68 uint32_t ds_data; /* data buffer pointer */ 69 uint32_t ds_ctl0; /* DMA control 0 */ 70 uint32_t ds_ctl1; /* DMA control 1 */ 71 union { 72 struct ar5416_tx_desc tx; 73 struct ar5416_rx_desc rx; 74 } u; 75} __packed; 76#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds)) 77#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds)) 78 79#define ds_ctl2 u.tx.ctl2 80#define ds_ctl3 u.tx.ctl3 81#define ds_ctl4 u.tx.ctl4 82#define ds_ctl5 u.tx.ctl5 83#define ds_ctl6 u.tx.ctl6 84#define ds_ctl7 u.tx.ctl7 85#define ds_ctl8 u.tx.ctl8 86#define ds_ctl9 u.tx.ctl9 87#define ds_ctl10 u.tx.ctl10 88#define ds_ctl11 u.tx.ctl11 89 90#define ds_rxstatus0 u.rx.status0 91#define ds_rxstatus1 u.rx.status1 92#define ds_rxstatus2 u.rx.status2 93#define ds_rxstatus3 u.rx.status3 94#define ds_rxstatus4 u.rx.status4 95#define ds_rxstatus5 u.rx.status5 96#define ds_rxstatus6 u.rx.status6 97#define ds_rxstatus7 u.rx.status7 98#define ds_rxstatus8 u.rx.status8 99 100/*********** 101 * TX Desc * 102 ***********/ 103 104/* ds_ctl0 */ 105#define AR_FrameLen 0x00000fff 106#define AR_VirtMoreFrag 0x00001000 107#define AR_TxCtlRsvd00 0x0000e000 108#define AR_XmitPower 0x003f0000 109#define AR_XmitPower_S 16 110#define AR_RTSEnable 0x00400000 111#define AR_VEOL 0x00800000 112#define AR_ClrDestMask 0x01000000 113#define AR_TxCtlRsvd01 0x1e000000 114#define AR_TxIntrReq 0x20000000 115#define AR_DestIdxValid 0x40000000 116#define AR_CTSEnable 0x80000000 117 118/* ds_ctl1 */ 119#define AR_BufLen 0x00000fff 120#define AR_TxMore 0x00001000 121#define AR_DestIdx 0x000fe000 122#define AR_DestIdx_S 13 123#define AR_FrameType 0x00f00000 124#define AR_FrameType_S 20 125#define AR_NoAck 0x01000000 126#define AR_InsertTS 0x02000000 127#define AR_CorruptFCS 0x04000000 128#define AR_ExtOnly 0x08000000 129#define AR_ExtAndCtl 0x10000000 130#define AR_MoreAggr 0x20000000 131#define AR_IsAggr 0x40000000 132#define AR_MoreRifs 0x80000000 133 134/* ds_ctl2 */ 135#define AR_BurstDur 0x00007fff 136#define AR_BurstDur_S 0 137#define AR_DurUpdateEn 0x00008000 138#define AR_XmitDataTries0 0x000f0000 139#define AR_XmitDataTries0_S 16 140#define AR_XmitDataTries1 0x00f00000 141#define AR_XmitDataTries1_S 20 142#define AR_XmitDataTries2 0x0f000000 143#define AR_XmitDataTries2_S 24 144#define AR_XmitDataTries3 0xf0000000 145#define AR_XmitDataTries3_S 28 146 147/* ds_ctl3 */ 148#define AR_XmitRate0 0x000000ff 149#define AR_XmitRate0_S 0 150#define AR_XmitRate1 0x0000ff00 151#define AR_XmitRate1_S 8 152#define AR_XmitRate2 0x00ff0000 153#define AR_XmitRate2_S 16 154#define AR_XmitRate3 0xff000000 155#define AR_XmitRate3_S 24 156 157/* ds_ctl4 */ 158#define AR_PacketDur0 0x00007fff 159#define AR_PacketDur0_S 0 160#define AR_RTSCTSQual0 0x00008000 161#define AR_PacketDur1 0x7fff0000 162#define AR_PacketDur1_S 16 163#define AR_RTSCTSQual1 0x80000000 164 165/* ds_ctl5 */ 166#define AR_PacketDur2 0x00007fff 167#define AR_PacketDur2_S 0 168#define AR_RTSCTSQual2 0x00008000 169#define AR_PacketDur3 0x7fff0000 170#define AR_PacketDur3_S 16 171#define AR_RTSCTSQual3 0x80000000 172 173/* ds_ctl6 */ 174#define AR_AggrLen 0x0000ffff 175#define AR_AggrLen_S 0 176#define AR_TxCtlRsvd60 0x00030000 177#define AR_PadDelim 0x03fc0000 178#define AR_PadDelim_S 18 179#define AR_EncrType 0x0c000000 180#define AR_EncrType_S 26 181#define AR_TxCtlRsvd61 0xf0000000 182 183/* ds_ctl7 */ 184#define AR_2040_0 0x00000001 185#define AR_GI0 0x00000002 186#define AR_ChainSel0 0x0000001c 187#define AR_ChainSel0_S 2 188#define AR_2040_1 0x00000020 189#define AR_GI1 0x00000040 190#define AR_ChainSel1 0x00000380 191#define AR_ChainSel1_S 7 192#define AR_2040_2 0x00000400 193#define AR_GI2 0x00000800 194#define AR_ChainSel2 0x00007000 195#define AR_ChainSel2_S 12 196#define AR_2040_3 0x00008000 197#define AR_GI3 0x00010000 198#define AR_ChainSel3 0x000e0000 199#define AR_ChainSel3_S 17 200#define AR_RTSCTSRate 0x0ff00000 201#define AR_RTSCTSRate_S 20 202#define AR_STBC0 0x10000000 203#define AR_STBC1 0x20000000 204#define AR_STBC2 0x40000000 205#define AR_STBC3 0x80000000 206 207/* ds_ctl8 */ 208#define AR_AntCtl0 0x00ffffff 209#define AR_AntCtl0_S 0 210/* Xmit 0 TPC is AR_XmitPower in ctl0 */ 211 212/* ds_ctl9 */ 213#define AR_AntCtl1 0x00ffffff 214#define AR_AntCtl1_S 0 215#define AR_XmitPower1 0xff000000 216#define AR_XmitPower1_S 24 217 218/* ds_ctl10 */ 219#define AR_AntCtl2 0x00ffffff 220#define AR_AntCtl2_S 0 221#define AR_XmitPower2 0xff000000 222#define AR_XmitPower2_S 24 223 224/* ds_ctl11 */ 225#define AR_AntCtl3 0x00ffffff 226#define AR_AntCtl3_S 0 227#define AR_XmitPower3 0xff000000 228#define AR_XmitPower3_S 24 229 230/************* 231 * TX Status * 232 *************/ 233 234/* ds_status0 */ 235#define AR_TxRSSIAnt00 0x000000ff 236#define AR_TxRSSIAnt00_S 0 237#define AR_TxRSSIAnt01 0x0000ff00 238#define AR_TxRSSIAnt01_S 8 239#define AR_TxRSSIAnt02 0x00ff0000 240#define AR_TxRSSIAnt02_S 16 241#define AR_TxStatusRsvd00 0x3f000000 242#define AR_TxBaStatus 0x40000000 243#define AR_TxStatusRsvd01 0x80000000 244 245/* ds_status1 */ 246#define AR_FrmXmitOK 0x00000001 247#define AR_ExcessiveRetries 0x00000002 248#define AR_FIFOUnderrun 0x00000004 249#define AR_Filtered 0x00000008 250#define AR_RTSFailCnt 0x000000f0 251#define AR_RTSFailCnt_S 4 252#define AR_DataFailCnt 0x00000f00 253#define AR_DataFailCnt_S 8 254#define AR_VirtRetryCnt 0x0000f000 255#define AR_VirtRetryCnt_S 12 256#define AR_TxDelimUnderrun 0x00010000 257#define AR_TxDelimUnderrun_S 13 258#define AR_TxDataUnderrun 0x00020000 259#define AR_TxDataUnderrun_S 14 260#define AR_DescCfgErr 0x00040000 261#define AR_DescCfgErr_S 15 262#define AR_TxTimerExpired 0x00080000 263#define AR_TxStatusRsvd10 0xfff00000 264 265/* ds_status2 */ 266#define AR_SendTimestamp(_ptr) (_ptr)[2] 267 268/* ds_status3 */ 269#define AR_BaBitmapLow(_ptr) (_ptr)[3] 270 271/* ds_status4 */ 272#define AR_BaBitmapHigh(_ptr) (_ptr)[4] 273 274/* ds_status5 */ 275#define AR_TxRSSIAnt10 0x000000ff 276#define AR_TxRSSIAnt10_S 0 277#define AR_TxRSSIAnt11 0x0000ff00 278#define AR_TxRSSIAnt11_S 8 279#define AR_TxRSSIAnt12 0x00ff0000 280#define AR_TxRSSIAnt12_S 16 281#define AR_TxRSSICombined 0xff000000 282#define AR_TxRSSICombined_S 24 283 284/* ds_status6 */ 285#define AR_TxEVM0(_ptr) (_ptr)[6] 286 287/* ds_status7 */ 288#define AR_TxEVM1(_ptr) (_ptr)[7] 289 290/* ds_status8 */ 291#define AR_TxEVM2(_ptr) (_ptr)[8] 292 293/* ds_status9 */ 294#define AR_TxDone 0x00000001 295#define AR_SeqNum 0x00001ffe 296#define AR_SeqNum_S 1 297#define AR_TxStatusRsvd80 0x0001e000 298#define AR_TxOpExceeded 0x00020000 299#define AR_TxStatusRsvd81 0x001c0000 300#define AR_FinalTxIdx 0x00600000 301#define AR_FinalTxIdx_S 21 302#define AR_TxStatusRsvd82 0x01800000 303#define AR_PowerMgmt 0x02000000 304#define AR_TxStatusRsvd83 0xfc000000 305 306/*********** 307 * RX Desc * 308 ***********/ 309 310/* ds_ctl0 */ 311#define AR_RxCTLRsvd00 0xffffffff 312 313/* ds_ctl1 */ 314#define AR_BufLen 0x00000fff 315#define AR_RxCtlRsvd00 0x00001000 316#define AR_RxIntrReq 0x00002000 317#define AR_RxCtlRsvd01 0xffffc000 318 319/************* 320 * Rx Status * 321 *************/ 322 323/* ds_status0 */ 324#define AR_RxRSSIAnt00 0x000000ff 325#define AR_RxRSSIAnt00_S 0 326#define AR_RxRSSIAnt01 0x0000ff00 327#define AR_RxRSSIAnt01_S 8 328#define AR_RxRSSIAnt02 0x00ff0000 329#define AR_RxRSSIAnt02_S 16 330/* Rev specific */ 331/* Owl 1.x only */ 332#define AR_RxStatusRsvd00 0xff000000 333/* Owl 2.x only */ 334#define AR_RxRate 0xff000000 335#define AR_RxRate_S 24 336 337/* ds_status1 */ 338#define AR_DataLen 0x00000fff 339#define AR_RxMore 0x00001000 340#define AR_NumDelim 0x003fc000 341#define AR_NumDelim_S 14 342#define AR_RxStatusRsvd10 0xff800000 343 344/* ds_status2 */ 345#define AR_RcvTimestamp ds_rxstatus2 346 347/* ds_status3 */ 348#define AR_GI 0x00000001 349#define AR_2040 0x00000002 350/* Rev specific */ 351/* Owl 1.x only */ 352#define AR_RxRateV1 0x000003fc 353#define AR_RxRateV1_S 2 354#define AR_Parallel40 0x00000400 355#define AR_RxStatusRsvd30 0xfffff800 356/* Owl 2.x only */ 357#define AR_DupFrame 0x00000004 358#define AR_RxAntenna 0xffffff00 359#define AR_RxAntenna_S 8 360 361/* ds_status4 */ 362#define AR_RxRSSIAnt10 0x000000ff 363#define AR_RxRSSIAnt10_S 0 364#define AR_RxRSSIAnt11 0x0000ff00 365#define AR_RxRSSIAnt11_S 8 366#define AR_RxRSSIAnt12 0x00ff0000 367#define AR_RxRSSIAnt12_S 16 368#define AR_RxRSSICombined 0xff000000 369#define AR_RxRSSICombined_S 24 370 371/* ds_status5 */ 372#define AR_RxEVM0 ds_rxstatus5 373 374/* ds_status6 */ 375#define AR_RxEVM1 ds_rxstatus6 376 377/* ds_status7 */ 378#define AR_RxEVM2 ds_rxstatus7 379 380/* ds_status8 */ 381#define AR_RxDone 0x00000001 382#define AR_RxFrameOK 0x00000002 383#define AR_CRCErr 0x00000004 384#define AR_DecryptCRCErr 0x00000008 385#define AR_PHYErr 0x00000010 386#define AR_MichaelErr 0x00000020 387#define AR_PreDelimCRCErr 0x00000040 388#define AR_RxStatusRsvd70 0x00000080 389#define AR_RxKeyIdxValid 0x00000100 390#define AR_KeyIdx 0x0000fe00 391#define AR_KeyIdx_S 9 392#define AR_PHYErrCode 0x0000ff00 393#define AR_PHYErrCode_S 8 394#define AR_RxMoreAggr 0x00010000 395#define AR_RxAggr 0x00020000 396#define AR_PostDelimCRCErr 0x00040000 397#define AR_RxStatusRsvd71 0x2ff80000 398#define AR_HiRxChain 0x10000000 399#define AR_DecryptBusyErr 0x40000000 400#define AR_KeyMiss 0x80000000 401 402#define TXCTL_OFFSET(ah) 2 403#define TXCTL_NUMWORDS(ah) (AR_SREV_5416_V20_OR_LATER(ah) ? 12 : 8) 404#define TXSTATUS_OFFSET(ah) (AR_SREV_5416_V20_OR_LATER(ah) ? 14 : 10) 405#define TXSTATUS_NUMWORDS(ah) 10 406 407#define RXCTL_OFFSET(ah) 3 408#define RXCTL_NUMWORDS(ah) 1 409#define RXSTATUS_OFFSET(ah) 4 410#define RXSTATUS_NUMWORDS(ah) 9 411#define RXSTATUS_RATE(ah, ads) \ 412 (AR_SREV_5416_V20_OR_LATER(ah) ? \ 413 MS((ads)->ds_rxstatus0, AR_RxRate) : \ 414 ((ads)->ds_rxstatus3 >> 2) & 0xFF) 415#define RXSTATUS_DUPLICATE(ah, ads) \ 416 (AR_SREV_5416_V20_OR_LATER(ah) ? \ 417 MS((ads)->ds_rxstatus3, AR_Parallel40) : \ 418 ((ads)->ds_rxstatus3 >> 10) & 0x1) 419#endif /* _ATH_AR5416_DESC_H_ */ 420