1/*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2004 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD$
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23
24#include "ar5210/ar5210.h"
25#include "ar5210/ar5210reg.h"
26
27#define	AR_KEYTABLE_SIZE	64
28#define	KEY_XOR			0xaa
29
30/*
31 * Return the size of the hardware key cache.
32 */
33u_int
34ar5210GetKeyCacheSize(struct ath_hal *ah)
35{
36	return AR_KEYTABLE_SIZE;
37}
38
39/*
40 * Return the size of the hardware key cache.
41 */
42HAL_BOOL
43ar5210IsKeyCacheEntryValid(struct ath_hal *ah, uint16_t entry)
44{
45	if (entry < AR_KEYTABLE_SIZE) {
46		uint32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));
47		if (val & AR_KEYTABLE_VALID)
48			return AH_TRUE;
49	}
50	return AH_FALSE;
51}
52
53/*
54 * Clear the specified key cache entry.
55 */
56HAL_BOOL
57ar5210ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry)
58{
59	if (entry < AR_KEYTABLE_SIZE) {
60		OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
61		OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
62		OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
63		OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
64		OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
65		OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), 0);
66		OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
67		OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
68		return AH_TRUE;
69	}
70	return AH_FALSE;
71}
72
73/*
74 * Sets the mac part of the specified key cache entry and mark it valid.
75 */
76HAL_BOOL
77ar5210SetKeyCacheEntryMac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac)
78{
79	uint32_t macHi, macLo;
80
81	if (entry < AR_KEYTABLE_SIZE) {
82		/*
83		 * Set MAC address -- shifted right by 1.  MacLo is
84		 * the 4 MSBs, and MacHi is the 2 LSBs.
85		 */
86		if (mac != AH_NULL) {
87			macHi = (mac[5] << 8) | mac[4];
88			macLo = (mac[3] << 24)| (mac[2] << 16)
89			      | (mac[1] << 8) | mac[0];
90			macLo >>= 1;
91			macLo |= (macHi & 1) << 31;	/* carry */
92			macHi >>= 1;
93		} else {
94			macLo = macHi = 0;
95		}
96
97		OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
98		OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry),
99			macHi | AR_KEYTABLE_VALID);
100		return AH_TRUE;
101	}
102	return AH_FALSE;
103}
104
105/*
106 * Sets the contents of the specified key cache entry.
107 */
108HAL_BOOL
109ar5210SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
110                       const HAL_KEYVAL *k, const uint8_t *mac, int xorKey)
111{
112	uint32_t key0, key1, key2, key3, key4;
113	uint32_t keyType;
114	uint32_t xorMask= xorKey ?
115		(KEY_XOR << 24 | KEY_XOR << 16 | KEY_XOR << 8 | KEY_XOR) : 0;
116
117	if (entry >= AR_KEYTABLE_SIZE)
118		return AH_FALSE;
119	if (k->kv_type != HAL_CIPHER_WEP) {
120		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cipher %u not supported\n",
121		    __func__, k->kv_type);
122		return AH_FALSE;
123	}
124
125	/* NB: only WEP supported */
126	if (k->kv_len < 40 / NBBY)
127		return AH_FALSE;
128	if (k->kv_len <= 40 / NBBY)
129		keyType = AR_KEYTABLE_TYPE_40;
130	else if (k->kv_len <= 104 / NBBY)
131		keyType = AR_KEYTABLE_TYPE_104;
132	else
133		keyType = AR_KEYTABLE_TYPE_128;
134
135	key0 = LE_READ_4(k->kv_val+0) ^ xorMask;
136	key1 = (LE_READ_2(k->kv_val+4) ^ xorMask) & 0xffff;
137	key2 = LE_READ_4(k->kv_val+6) ^ xorMask;
138	key3 = (LE_READ_2(k->kv_val+10) ^ xorMask) & 0xffff;
139	key4 = LE_READ_4(k->kv_val+12) ^ xorMask;
140	if (k->kv_len <= 104 / NBBY)
141		key4 &= 0xff;
142
143	/*
144	 * Note: WEP key cache hardware requires that each double-word
145	 * pair be written in even/odd order (since the destination is
146	 * a 64-bit register).  Don't reorder these writes w/o
147	 * understanding this!
148	 */
149	OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
150	OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
151	OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
152	OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
153	OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
154	OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
155	return ar5210SetKeyCacheEntryMac(ah, entry, mac);
156}
157