1139749Simp/*- 247411Sgibbs ********************************************************************* 347411Sgibbs * FILE NAME : amd.h 447411Sgibbs * BY : C.L. Huang (ching@tekram.com.tw) 547411Sgibbs * Erich Chen (erich@tekram.com.tw) 647411Sgibbs * Description: Device Driver for the amd53c974 PCI Bus Master 747411Sgibbs * SCSI Host adapter found on cards such as 847411Sgibbs * the Tekram DC-390(T). 947411Sgibbs * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. 1047411Sgibbs * 1147411Sgibbs * Redistribution and use in source and binary forms, with or without 1247411Sgibbs * modification, are permitted provided that the following conditions 1347411Sgibbs * are met: 1447411Sgibbs * 1. Redistributions of source code must retain the above copyright 1547411Sgibbs * notice, this list of conditions and the following disclaimer. 1647411Sgibbs * 2. Redistributions in binary form must reproduce the above copyright 1747411Sgibbs * notice, this list of conditions and the following disclaimer in the 1847411Sgibbs * documentation and/or other materials provided with the distribution. 1947411Sgibbs * 3. The name of the author may not be used to endorse or promote products 2047411Sgibbs * derived from this software without specific prior written permission. 2147411Sgibbs * 2247411Sgibbs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 2347411Sgibbs * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2447411Sgibbs * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2547411Sgibbs * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2647411Sgibbs * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2747411Sgibbs * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2847411Sgibbs * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2947411Sgibbs * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3047411Sgibbs * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 3147411Sgibbs * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3247411Sgibbs ********************************************************************* 3359083Snyan * $FreeBSD$ 3447411Sgibbs */ 3547411Sgibbs 3647411Sgibbs#ifndef AMD_H 3747411Sgibbs#define AMD_H 3847411Sgibbs 3947411Sgibbs#define AMD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 4047411Sgibbs#define AMD_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 4147411Sgibbs#define AMD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 4247411Sgibbs#define AMD_TRANS_USER 0x08 /* Modify user negotiation settings */ 4347411Sgibbs 4447411Sgibbs/* 4547411Sgibbs * Per target transfer parameters. 4647411Sgibbs */ 4747411Sgibbsstruct amd_transinfo { 4847411Sgibbs u_int8_t period; 4947411Sgibbs u_int8_t offset; 5047411Sgibbs}; 5147411Sgibbs 5247411Sgibbsstruct amd_target_info { 5347411Sgibbs /* 5447411Sgibbs * Records the currently active and user/default settings for 5547411Sgibbs * tagged queueing and disconnection for each target. 5647411Sgibbs */ 5747411Sgibbs u_int8_t disc_tag; 5847411Sgibbs#define AMD_CUR_DISCENB 0x01 5947411Sgibbs#define AMD_CUR_TAGENB 0x02 6047411Sgibbs#define AMD_USR_DISCENB 0x04 6147411Sgibbs#define AMD_USR_TAGENB 0x08 6247411Sgibbs u_int8_t CtrlR1; 6347411Sgibbs u_int8_t CtrlR3; 6447411Sgibbs u_int8_t CtrlR4; 6547411Sgibbs u_int8_t sync_period_reg; 6647411Sgibbs u_int8_t sync_offset_reg; 6747411Sgibbs 6847411Sgibbs /* 6947411Sgibbs * Currently active transfer settings. 7047411Sgibbs */ 7147411Sgibbs struct amd_transinfo current; 7247411Sgibbs /* 7347411Sgibbs * Transfer settings we wish to achieve 7447411Sgibbs * through negotiation. 7547411Sgibbs */ 7647411Sgibbs struct amd_transinfo goal; 7747411Sgibbs /* 7847411Sgibbs * User defined or default transfer settings. 7947411Sgibbs */ 8047411Sgibbs struct amd_transinfo user; 8147411Sgibbs}; 8247411Sgibbs 8347411Sgibbs/* 8447411Sgibbs * Scatter/Gather Segment entry. 8547411Sgibbs */ 8647411Sgibbsstruct amd_sg { 8747411Sgibbs u_int32_t SGXLen; 8847411Sgibbs u_int32_t SGXPtr; 8947411Sgibbs}; 9047411Sgibbs 9147411Sgibbs/* 9247411Sgibbs * Chipset feature limits 9347411Sgibbs */ 9447411Sgibbs#define MAX_SCSI_ID 8 9547411Sgibbs#define AMD_MAX_SYNC_OFFSET 15 9647411Sgibbs#define AMD_TARGET_MAX 7 9747411Sgibbs#define AMD_LUN_MAX 7 98195534Sscottl#define AMD_MAXPHYS (128 * 1024) /* legacy MAXPHYS */ 99195534Sscottl#define AMD_NSEG (btoc(AMD_MAXPHYS) + 1) 10047411Sgibbs#define AMD_MAXTRANSFER_SIZE 0xFFFFFF /* restricted by 24 bit counter */ 10147411Sgibbs#define MAX_DEVICES 10 10247411Sgibbs#define MAX_TAGS_CMD_QUEUE 256 10347411Sgibbs#define MAX_CMD_PER_LUN 6 10447411Sgibbs#define MAX_SRB_CNT 256 10547411Sgibbs#define MAX_START_JOB 256 10647411Sgibbs 10747411Sgibbs/* 10847411Sgibbs * BIT position to integer mapping. 10947411Sgibbs */ 11047411Sgibbs#define BIT(N) (0x01 << N) 11147411Sgibbs 11247411Sgibbs/* 11347411Sgibbs * EEPROM storage offsets and data structures. 11447411Sgibbs */ 11547411Sgibbstypedef struct _EEprom { 11647411Sgibbs u_int8_t EE_MODE1; 11747411Sgibbs u_int8_t EE_SPEED; 11847411Sgibbs u_int8_t xx1; 11947411Sgibbs u_int8_t xx2; 12047411Sgibbs} EEprom, *PEEprom; 12147411Sgibbs 12247411Sgibbs#define EE_ADAPT_SCSI_ID 64 12347411Sgibbs#define EE_MODE2 65 12447411Sgibbs#define EE_DELAY 66 12547411Sgibbs#define EE_TAG_CMD_NUM 67 12647411Sgibbs#define EE_DATA_SIZE 128 12747411Sgibbs#define EE_CHECKSUM 0x1234 12847411Sgibbs 12947411Sgibbs/* 13047411Sgibbs * EE_MODE1 bits definition 13147411Sgibbs */ 13247411Sgibbs#define PARITY_CHK BIT(0) 13347411Sgibbs#define SYNC_NEGO BIT(1) 13447411Sgibbs#define EN_DISCONNECT BIT(2) 13547411Sgibbs#define SEND_START BIT(3) 13647411Sgibbs#define TAG_QUEUING BIT(4) 13747411Sgibbs 13847411Sgibbs/* 13947411Sgibbs * EE_MODE2 bits definition 14047411Sgibbs */ 14147411Sgibbs#define MORE2_DRV BIT(0) 14247411Sgibbs#define GREATER_1G BIT(1) 14347411Sgibbs#define RST_SCSI_BUS BIT(2) 14447411Sgibbs#define ACTIVE_NEGATION BIT(3) 14547411Sgibbs#define NO_SEEK BIT(4) 14647411Sgibbs#define LUN_CHECK BIT(5) 14747411Sgibbs 14847411Sgibbs#define ENABLE_CE 1 14947411Sgibbs#define DISABLE_CE 0 15047411Sgibbs#define EEPROM_READ 0x80 15147411Sgibbs 15247411Sgibbs#define AMD_TAG_WILDCARD ((u_int)(~0)) 15347411Sgibbs 15447411Sgibbs/* 15547411Sgibbs * SCSI Request Block 15647411Sgibbs */ 15747411Sgibbsstruct amd_srb { 15860938Sjake TAILQ_ENTRY(amd_srb) links; 15947411Sgibbs u_int8_t CmdBlock[12]; 16047411Sgibbs union ccb *pccb; 16147411Sgibbs bus_dmamap_t dmamap; 16247411Sgibbs struct amd_sg *pSGlist; 16347411Sgibbs 16447411Sgibbs u_int32_t TotalXferredLen; 16547411Sgibbs u_int32_t SGPhysAddr; /* a segment starting address */ 16647411Sgibbs u_int32_t SGToBeXferLen; /* to be xfer length */ 16747411Sgibbs u_int32_t Segment0[2]; 16847411Sgibbs u_int32_t Segment1[2]; 16947411Sgibbs 17047411Sgibbs struct amd_sg SGsegment[AMD_NSEG]; 17147411Sgibbs struct amd_sg Segmentx;/* a one entry of S/G list table */ 17247411Sgibbs u_int8_t *pMsgPtr; 17347411Sgibbs u_int16_t SRBState; 17447411Sgibbs 17547411Sgibbs u_int8_t AdaptStatus; 17647411Sgibbs u_int8_t TargetStatus; 17747411Sgibbs u_int8_t MsgCnt; 17847411Sgibbs u_int8_t EndMessage; 17947411Sgibbs u_int8_t TagNumber; 18047411Sgibbs u_int8_t SGcount; 18147411Sgibbs u_int8_t SGIndex; 18247411Sgibbs u_int8_t IORBFlag; /* ;81h-Reset, 2-retry */ 18347411Sgibbs 18447411Sgibbs u_int8_t SRBStatus; 18547411Sgibbs u_int8_t SRBFlag; 18647411Sgibbs /* ; b0-AutoReqSense,b6-Read,b7-write */ 18747411Sgibbs /* ; b4-settimeout,b5-Residual valid */ 18847411Sgibbs u_int8_t ScsiCmdLen; 18947411Sgibbs}; 19047411Sgibbs 19160938SjakeTAILQ_HEAD(srb_queue, amd_srb); 19247411Sgibbs 19347411Sgibbs/* 19447411Sgibbs * Per-adapter, software configuration. 19547411Sgibbs */ 19647411Sgibbsstruct amd_softc { 19759083Snyan device_t dev; 19847411Sgibbs bus_space_tag_t tag; 19947411Sgibbs bus_space_handle_t bsh; 20047411Sgibbs bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 201107876Sscottl bus_dma_tag_t sense_dmat; /* dmat for sense buffer */ 202107876Sscottl bus_dmamap_t sense_dmamap; 203107876Sscottl struct scsi_sense_data *sense_buffers; 204107876Sscottl bus_addr_t sense_busaddr; 20547411Sgibbs int unit; 20647411Sgibbs 20747411Sgibbs int last_phase; 20847411Sgibbs int cur_target; 20947411Sgibbs int cur_lun; 21047411Sgibbs struct amd_srb *active_srb; 21147411Sgibbs struct amd_srb *untagged_srbs[AMD_TARGET_MAX+1][AMD_LUN_MAX+1]; 21247411Sgibbs struct amd_target_info tinfo[AMD_TARGET_MAX+1]; 21347411Sgibbs u_int16_t disc_count[AMD_TARGET_MAX+1][AMD_LUN_MAX+1]; 21447411Sgibbs 21547411Sgibbs struct srb_queue free_srbs; 21647411Sgibbs struct srb_queue waiting_srbs; 21747411Sgibbs struct srb_queue running_srbs; 21847411Sgibbs 21947411Sgibbs struct amd_srb *pTmpSRB; 22047411Sgibbs 22147411Sgibbs u_int16_t SRBCount; 22247411Sgibbs 22347411Sgibbs u_int16_t max_id; 22447411Sgibbs u_int16_t max_lun; 22547411Sgibbs 22647411Sgibbs /* Hooks into the CAM XPT */ 22747411Sgibbs struct cam_sim *psim; 22847411Sgibbs struct cam_path *ppath; 22947411Sgibbs 23047411Sgibbs u_int8_t msgin_buf[6]; 23147411Sgibbs u_int8_t msgout_buf[6]; 23247411Sgibbs u_int msgin_index; 23347411Sgibbs u_int msgout_index; 23447411Sgibbs u_int msgout_len; 23547411Sgibbs 23647411Sgibbs u_int8_t status; 23747411Sgibbs u_int8_t AdaptSCSIID; /* ; Adapter SCSI Target ID */ 23847411Sgibbs u_int8_t AdaptSCSILUN; /* ; Adapter SCSI LUN */ 23947411Sgibbs 24047411Sgibbs u_int8_t ACBFlag; 24147411Sgibbs 24247411Sgibbs u_int8_t Gmode2; 24347411Sgibbs 24447411Sgibbs u_int8_t HostID_Bit; 24547411Sgibbs 24647411Sgibbs u_int8_t InitDCB_flag[8][8]; /* flag of initDCB for device */ 24747411Sgibbs struct amd_srb SRB_array[MAX_SRB_CNT]; /* +45Ch, Len= */ 24847411Sgibbs struct amd_srb TmpSRB; 24947411Sgibbs /* Setup data stored in an 93c46 serial eeprom */ 25047411Sgibbs u_int8_t eepromBuf[EE_DATA_SIZE]; 25147411Sgibbs}; 25247411Sgibbs 25347411Sgibbs/* 25447411Sgibbs * ----SRB State machine definition 25547411Sgibbs */ 25647411Sgibbs#define SRB_FREE 0 25747411Sgibbs#define SRB_READY BIT(1) 25847411Sgibbs#define SRB_MSGOUT BIT(2) /* ;arbitration+msg_out 1st byte */ 25947411Sgibbs#define SRB_MSGIN BIT(3) 26047411Sgibbs#define SRB_MSGIN_MULTI BIT(4) 26147411Sgibbs#define SRB_COMMAND BIT(5) 26247411Sgibbs#define SRB_START BIT(6) /* ;arbitration+msg_out+command_out */ 26347411Sgibbs#define SRB_DISCONNECT BIT(7) 26447411Sgibbs#define SRB_DATA_XFER BIT(8) 26547411Sgibbs#define SRB_XFERPAD BIT(9) 26647411Sgibbs#define SRB_STATUS BIT(10) 26747411Sgibbs#define SRB_COMPLETED BIT(11) 26847411Sgibbs#define SRB_ABORT_SENT BIT(12) 26947411Sgibbs#define DO_SYNC_NEGO BIT(13) 27047411Sgibbs#define SRB_UNEXPECT_RESEL BIT(14) 27147411Sgibbs 27247411Sgibbs/* 27347411Sgibbs * ---ACB Flag 27447411Sgibbs */ 27547411Sgibbs#define RESET_DEV BIT(0) 27647411Sgibbs#define RESET_DETECT BIT(1) 27747411Sgibbs#define RESET_DONE BIT(2) 27847411Sgibbs 27947411Sgibbs/* 28047411Sgibbs * ---DCB Flag 28147411Sgibbs */ 28247411Sgibbs#define ABORT_DEV_ BIT(0) 28347411Sgibbs 28447411Sgibbs/* 28547411Sgibbs * ---SRB status 28647411Sgibbs */ 28747411Sgibbs#define SRB_OK BIT(0) 28847411Sgibbs#define ABORTION BIT(1) 28947411Sgibbs#define OVER_RUN BIT(2) 29047411Sgibbs#define UNDER_RUN BIT(3) 29147411Sgibbs#define PARITY_ERROR BIT(4) 29247411Sgibbs#define SRB_ERROR BIT(5) 29347411Sgibbs 29447411Sgibbs/* 29547411Sgibbs * ---SRB Flags 29647411Sgibbs */ 29747411Sgibbs#define DATAOUT BIT(7) 29847411Sgibbs#define DATAIN BIT(6) 29947411Sgibbs#define RESIDUAL_VALID BIT(5) 30047411Sgibbs#define ENABLE_TIMER BIT(4) 30147411Sgibbs#define RESET_DEV0 BIT(2) 30247411Sgibbs#define ABORT_DEV BIT(1) 30347411Sgibbs#define AUTO_REQSENSE BIT(0) 30447411Sgibbs 30547411Sgibbs/* 30647411Sgibbs * ---Adapter status 30747411Sgibbs */ 30847411Sgibbs#define H_STATUS_GOOD 0 30947411Sgibbs#define H_SEL_TIMEOUT 0x11 31047411Sgibbs#define H_OVER_UNDER_RUN 0x12 31147411Sgibbs#define H_UNEXP_BUS_FREE 0x13 31247411Sgibbs#define H_TARGET_PHASE_F 0x14 31347411Sgibbs#define H_INVALID_CCB_OP 0x16 31447411Sgibbs#define H_LINK_CCB_BAD 0x17 31547411Sgibbs#define H_BAD_TARGET_DIR 0x18 31647411Sgibbs#define H_DUPLICATE_CCB 0x19 31747411Sgibbs#define H_BAD_CCB_OR_SG 0x1A 31847411Sgibbs#define H_ABORT 0x0FF 31947411Sgibbs 32047411Sgibbs/* 32147411Sgibbs * AMD specific "status" codes returned in the SCSI status byte. 32247411Sgibbs */ 32347411Sgibbs#define AMD_SCSI_STAT_UNEXP_BUS_F 0xFD /* ; Unexpect Bus Free */ 32447411Sgibbs#define AMD_SCSI_STAT_BUS_RST_DETECT 0xFE /* ; Scsi Bus Reset detected */ 32547411Sgibbs#define AMD_SCSI_STAT_SEL_TIMEOUT 0xFF /* ; Selection Time out */ 32647411Sgibbs 32747411Sgibbs/* 32847411Sgibbs * ---Sync_Mode 32947411Sgibbs */ 33047411Sgibbs#define SYNC_DISABLE 0 33147411Sgibbs#define SYNC_ENABLE BIT(0) 33247411Sgibbs#define SYNC_NEGO_DONE BIT(1) 33347411Sgibbs#define WIDE_ENABLE BIT(2) 33447411Sgibbs#define WIDE_NEGO_DONE BIT(3) 33547411Sgibbs#define EN_TAG_QUEUING BIT(4) 33647411Sgibbs#define EN_ATN_STOP BIT(5) 33747411Sgibbs 33847411Sgibbs#define SYNC_NEGO_OFFSET 15 33947411Sgibbs 34047411Sgibbs/* 34147411Sgibbs * ---SCSI bus phase 34247411Sgibbs */ 34347411Sgibbs#define SCSI_DATA_OUT 0 34447411Sgibbs#define SCSI_DATA_IN 1 34547411Sgibbs#define SCSI_COMMAND 2 34647411Sgibbs#define SCSI_STATUS 3 34747411Sgibbs#define SCSI_NOP0 4 34847411Sgibbs#define SCSI_ARBITRATING 5 34947411Sgibbs#define SCSI_MSG_OUT 6 35047411Sgibbs#define SCSI_MSG_IN 7 35147411Sgibbs#define SCSI_BUS_FREE 8 35247411Sgibbs 35347411Sgibbs/* 35447411Sgibbs *========================================================== 35547411Sgibbs * AMD 53C974 Registers bit Definition 35647411Sgibbs *========================================================== 35747411Sgibbs */ 35847411Sgibbs 35947411Sgibbs/* 36047411Sgibbs * ------SCSI Register------- 36147411Sgibbs * Command Reg.(+0CH) 36247411Sgibbs */ 36347411Sgibbs#define DMA_COMMAND BIT(7) 36447411Sgibbs#define NOP_CMD 0 36547411Sgibbs#define CLEAR_FIFO_CMD 1 36647411Sgibbs#define RST_DEVICE_CMD 2 36747411Sgibbs#define RST_SCSI_BUS_CMD 3 36847411Sgibbs#define INFO_XFER_CMD 0x10 36947411Sgibbs#define INITIATOR_CMD_CMPLTE 0x11 37047411Sgibbs#define MSG_ACCEPTED_CMD 0x12 37147411Sgibbs#define XFER_PAD_BYTE 0x18 37247411Sgibbs#define SET_ATN_CMD 0x1A 37347411Sgibbs#define RESET_ATN_CMD 0x1B 37447411Sgibbs#define SEL_W_ATN 0x42 37547411Sgibbs#define SEL_W_ATN_STOP 0x43 37647411Sgibbs#define EN_SEL_RESEL 0x44 37747411Sgibbs#define SEL_W_ATN2 0x46 37847411Sgibbs#define DATA_XFER_CMD INFO_XFER_CMD 37947411Sgibbs 38047411Sgibbs 38147411Sgibbs/* 38247411Sgibbs * ------SCSI Register------- 38347411Sgibbs * SCSI Status Reg.(+10H) 38447411Sgibbs */ 38547411Sgibbs#define INTERRUPT BIT(7) 38647411Sgibbs#define ILLEGAL_OP_ERR BIT(6) 38747411Sgibbs#define PARITY_ERR BIT(5) 38847411Sgibbs#define COUNT_2_ZERO BIT(4) 38947411Sgibbs#define GROUP_CODE_VALID BIT(3) 39047411Sgibbs#define SCSI_PHASE_MASK (BIT(2)+BIT(1)+BIT(0)) 39147411Sgibbs 39247411Sgibbs/* 39347411Sgibbs * ------SCSI Register------- 39447411Sgibbs * Interrupt Status Reg.(+14H) 39547411Sgibbs */ 39647411Sgibbs#define SCSI_RESET_ BIT(7) 39747411Sgibbs#define INVALID_CMD BIT(6) 39847411Sgibbs#define DISCONNECTED BIT(5) 39947411Sgibbs#define SERVICE_REQUEST BIT(4) 40047411Sgibbs#define SUCCESSFUL_OP BIT(3) 40147411Sgibbs#define RESELECTED BIT(2) 40247411Sgibbs#define SEL_ATTENTION BIT(1) 40347411Sgibbs#define SELECTED BIT(0) 40447411Sgibbs 40547411Sgibbs/* 40647411Sgibbs * ------SCSI Register------- 40747411Sgibbs * Internal State Reg.(+18H) 40847411Sgibbs */ 40947411Sgibbs#define SYNC_OFFSET_FLAG BIT(3) 41047411Sgibbs#define INTRN_STATE_MASK (BIT(2)+BIT(1)+BIT(0)) 41147411Sgibbs 41247411Sgibbs/* 41347411Sgibbs * ------SCSI Register------- 41447411Sgibbs * Clock Factor Reg.(+24H) 41547411Sgibbs */ 41647411Sgibbs#define CLK_FREQ_40MHZ 0 41747411Sgibbs#define CLK_FREQ_35MHZ (BIT(2)+BIT(1)+BIT(0)) 41847411Sgibbs#define CLK_FREQ_30MHZ (BIT(2)+BIT(1)) 41947411Sgibbs#define CLK_FREQ_25MHZ (BIT(2)+BIT(0)) 42047411Sgibbs#define CLK_FREQ_20MHZ BIT(2) 42147411Sgibbs#define CLK_FREQ_15MHZ (BIT(1)+BIT(0)) 42247411Sgibbs#define CLK_FREQ_10MHZ BIT(1) 42347411Sgibbs 42447411Sgibbs/* 42547411Sgibbs * ------SCSI Register------- 42647411Sgibbs * Control Reg. 1(+20H) 42747411Sgibbs */ 42847411Sgibbs#define EXTENDED_TIMING BIT(7) 42947411Sgibbs#define DIS_INT_ON_SCSI_RST BIT(6) 43047411Sgibbs#define PARITY_ERR_REPO BIT(4) 43147411Sgibbs#define SCSI_ID_ON_BUS (BIT(2)+BIT(1)+BIT(0)) 43247411Sgibbs 43347411Sgibbs/* 43447411Sgibbs * ------SCSI Register------- 43547411Sgibbs * Control Reg. 2(+2CH) 43647411Sgibbs */ 43747411Sgibbs#define EN_FEATURE BIT(6) 43847411Sgibbs#define EN_SCSI2_CMD BIT(3) 43947411Sgibbs 44047411Sgibbs/* 44147411Sgibbs * ------SCSI Register------- 44247411Sgibbs * Control Reg. 3(+30H) 44347411Sgibbs */ 44447411Sgibbs#define ID_MSG_CHECK BIT(7) 44547411Sgibbs#define EN_QTAG_MSG BIT(6) 44647411Sgibbs#define EN_GRP2_CMD BIT(5) 44747411Sgibbs#define FAST_SCSI BIT(4) /* ;10MB/SEC */ 44847411Sgibbs#define FAST_CLK BIT(3) /* ;25 - 40 MHZ */ 44947411Sgibbs 45047411Sgibbs/* 45147411Sgibbs * ------SCSI Register------- 45247411Sgibbs * Control Reg. 4(+34H) 45347411Sgibbs */ 45447411Sgibbs#define EATER_12NS 0 45547411Sgibbs#define EATER_25NS BIT(7) 45647411Sgibbs#define EATER_35NS BIT(6) 45747411Sgibbs#define EATER_0NS (BIT(7)+BIT(6)) 45847411Sgibbs#define NEGATE_REQACKDATA BIT(2) 45947411Sgibbs#define NEGATE_REQACK BIT(3) 46047411Sgibbs 46147411Sgibbs/* 46247411Sgibbs *======================================== 46347411Sgibbs * DMA Register 46447411Sgibbs *======================================== 46547411Sgibbs */ 46647411Sgibbs 46747411Sgibbs/* 46847411Sgibbs * -------DMA Register-------- 46947411Sgibbs * DMA Command Reg.(+40H) 47047411Sgibbs */ 47147411Sgibbs#define READ_DIRECTION BIT(7) 47247411Sgibbs#define WRITE_DIRECTION 0 47347411Sgibbs#define EN_DMA_INT BIT(6) 47447411Sgibbs#define MAP_TO_MDL BIT(5) 47547411Sgibbs#define DMA_DIAGNOSTIC BIT(4) 47647411Sgibbs#define DMA_IDLE_CMD 0 47747411Sgibbs#define DMA_BLAST_CMD BIT(0) 47847411Sgibbs#define DMA_ABORT_CMD BIT(1) 47947411Sgibbs#define DMA_START_CMD (BIT(1)|BIT(0)) 48047411Sgibbs 48147411Sgibbs/* 48247411Sgibbs * -------DMA Register-------- 48347411Sgibbs * DMA Status Reg.(+54H) 48447411Sgibbs */ 48547411Sgibbs#define PCI_MS_ABORT BIT(6) 48647411Sgibbs#define BLAST_COMPLETE BIT(5) 48747411Sgibbs#define SCSI_INTERRUPT BIT(4) 48847411Sgibbs#define DMA_XFER_DONE BIT(3) 48947411Sgibbs#define DMA_XFER_ABORT BIT(2) 49047411Sgibbs#define DMA_XFER_ERROR BIT(1) 49147411Sgibbs#define POWER_DOWN BIT(0) 49247411Sgibbs 49347411Sgibbs/* 49447411Sgibbs * -------DMA Register-------- 49547411Sgibbs * DMA SCSI Bus and Ctrl.(+70H) 49647411Sgibbs * EN_INT_ON_PCI_ABORT 49747411Sgibbs */ 49847411Sgibbs 49947411Sgibbs/* 50047411Sgibbs *========================================================== 50147411Sgibbs * SCSI Chip register address offset 50247411Sgibbs *========================================================== 50347411Sgibbs */ 50447411Sgibbs#define CTCREG_LOW 0x00 /* (R) current transfer count register low */ 50547411Sgibbs#define STCREG_LOW 0x00 /* (W) start transfer count register low */ 50647411Sgibbs 50747411Sgibbs#define CTCREG_MID 0x04 /* (R) current transfer count register 50847411Sgibbs * middle */ 50947411Sgibbs#define STCREG_MID 0x04 /* (W) start transfer count register middle */ 51047411Sgibbs 51147411Sgibbs#define SCSIFIFOREG 0x08 /* (R/W) SCSI FIFO register */ 51247411Sgibbs 51347411Sgibbs#define SCSICMDREG 0x0C /* (R/W) SCSI command register */ 51447411Sgibbs 51547411Sgibbs#define SCSISTATREG 0x10 /* (R) SCSI status register */ 51647411Sgibbs#define SCSIDESTIDREG 0x10 /* (W) SCSI destination ID register */ 51747411Sgibbs 51847411Sgibbs#define INTSTATREG 0x14 /* (R) interrupt status register */ 51947411Sgibbs#define SCSITIMEOUTREG 0x14 /* (W) SCSI timeout register */ 52047411Sgibbs 52147411Sgibbs 52247411Sgibbs#define INTERNSTATREG 0x18 /* (R) internal state register */ 52347411Sgibbs#define SYNCPERIOREG 0x18 /* (W) synchronous transfer period register */ 52447411Sgibbs 52547411Sgibbs#define CURRENTFIFOREG 0x1C /* (R) current FIFO/internal state register */ 52647411Sgibbs#define SYNCOFFREG 0x1C/* (W) synchronous transfer period register */ 52747411Sgibbs 52847411Sgibbs#define CNTLREG1 0x20 /* (R/W) control register 1 */ 52947411Sgibbs#define CLKFACTREG 0x24 /* (W) clock factor register */ 53047411Sgibbs#define CNTLREG2 0x2C /* (R/W) control register 2 */ 53147411Sgibbs#define CNTLREG3 0x30 /* (R/W) control register 3 */ 53247411Sgibbs#define CNTLREG4 0x34 /* (R/W) control register 4 */ 53347411Sgibbs 53447411Sgibbs#define CURTXTCNTREG 0x38 /* (R) current transfer count register 53547411Sgibbs * high/part-unique ID code */ 53647411Sgibbs#define STCREG_HIGH 0x38 /* (W) Start current transfer count register 53747411Sgibbs * high */ 53847411Sgibbs 53947411Sgibbs/* 54047411Sgibbs ********************************************************* 54147411Sgibbs * 54247411Sgibbs * SCSI DMA register 54347411Sgibbs * 54447411Sgibbs ********************************************************* 54547411Sgibbs */ 54647411Sgibbs#define DMA_Cmd 0x40 /* (R/W) command register */ 54747411Sgibbs#define DMA_XferCnt 0x44 /* (R/W) starting transfer count */ 54847411Sgibbs#define DMA_XferAddr 0x48 /* (R/W) starting Physical address */ 54947411Sgibbs#define DMA_Wk_ByteCntr 0x4C /* ( R ) working byte counter */ 55047411Sgibbs#define DMA_Wk_AddrCntr 0x50 /* ( R ) working address counter */ 55147411Sgibbs#define DMA_Status 0x54 /* ( R ) status register */ 55247411Sgibbs#define DMA_MDL_Addr 0x58 /* (R/W) starting memory descriptor list (MDL) 55347411Sgibbs * address */ 55447411Sgibbs#define DMA_Wk_MDL_Cntr 0x5C /* ( R ) working MDL counter */ 55547411Sgibbs#define DMA_ScsiBusCtrl 0x70 /* (bits R/W) SCSI BUS and control */ 55647411Sgibbs 55747411Sgibbs/* ******************************************************* */ 55847411Sgibbs#define am_target SCSISTATREG 55947411Sgibbs#define am_timeout INTSTATREG 56047411Sgibbs#define am_seq_step SYNCPERIOREG 56147411Sgibbs#define am_fifo_count SYNCOFFREG 56247411Sgibbs 56347411Sgibbs 56447411Sgibbs#define amd_read8(amd, port) \ 56547411Sgibbs bus_space_read_1((amd)->tag, (amd)->bsh, port) 56647411Sgibbs 56747411Sgibbs#define amd_read16(amd, port) \ 56847411Sgibbs bus_space_read_2((amd)->tag, (amd)->bsh, port) 56947411Sgibbs 57047411Sgibbs#define amd_read32(amd, port) \ 57147411Sgibbs bus_space_read_4((amd)->tag, (amd)->bsh, port) 57247411Sgibbs 57347411Sgibbs#define amd_write8(amd, port, value) \ 57447411Sgibbs bus_space_write_1((amd)->tag, (amd)->bsh, port, value) 57547411Sgibbs 57647411Sgibbs#define amd_write8_multi(amd, port, ptr, len) \ 57747411Sgibbs bus_space_write_multi_1((amd)->tag, (amd)->bsh, port, ptr, len) 57847411Sgibbs 57947411Sgibbs#define amd_write16(amd, port, value) \ 58047411Sgibbs bus_space_write_2((amd)->tag, (amd)->bsh, port, value) 58147411Sgibbs 58247411Sgibbs#define amd_write32(amd, port, value) \ 58347411Sgibbs bus_space_write_4((amd)->tag, (amd)->bsh, port, value) 58447411Sgibbs 58547411Sgibbs#endif /* AMD_H */ 586