1/*- 2 ********************************************************************* 3 * FILE NAME : amd.h 4 * BY : C.L. Huang (ching@tekram.com.tw) 5 * Erich Chen (erich@tekram.com.tw) 6 * Description: Device Driver for the amd53c974 PCI Bus Master 7 * SCSI Host adapter found on cards such as 8 * the Tekram DC-390(T). 9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 ********************************************************************* 33 * $FreeBSD$ 34 */ 35 36#ifndef AMD_H 37#define AMD_H 38 39#define AMD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 40#define AMD_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 41#define AMD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 42#define AMD_TRANS_USER 0x08 /* Modify user negotiation settings */ 43 44/* 45 * Per target transfer parameters. 46 */ 47struct amd_transinfo { 48 u_int8_t period; 49 u_int8_t offset; 50}; 51 52struct amd_target_info { 53 /* 54 * Records the currently active and user/default settings for 55 * tagged queueing and disconnection for each target. 56 */ 57 u_int8_t disc_tag; 58#define AMD_CUR_DISCENB 0x01 59#define AMD_CUR_TAGENB 0x02 60#define AMD_USR_DISCENB 0x04 61#define AMD_USR_TAGENB 0x08 62 u_int8_t CtrlR1; 63 u_int8_t CtrlR3; 64 u_int8_t CtrlR4; 65 u_int8_t sync_period_reg; 66 u_int8_t sync_offset_reg; 67 68 /* 69 * Currently active transfer settings. 70 */ 71 struct amd_transinfo current; 72 /* 73 * Transfer settings we wish to achieve 74 * through negotiation. 75 */ 76 struct amd_transinfo goal; 77 /* 78 * User defined or default transfer settings. 79 */ 80 struct amd_transinfo user; 81}; 82 83/* 84 * Scatter/Gather Segment entry. 85 */ 86struct amd_sg { 87 u_int32_t SGXLen; 88 u_int32_t SGXPtr; 89}; 90 91/* 92 * Chipset feature limits 93 */ 94#define MAX_SCSI_ID 8 95#define AMD_MAX_SYNC_OFFSET 15 96#define AMD_TARGET_MAX 7 97#define AMD_LUN_MAX 7 98#define AMD_MAXPHYS (128 * 1024) /* legacy MAXPHYS */ 99#define AMD_NSEG (btoc(AMD_MAXPHYS) + 1) 100#define AMD_MAXTRANSFER_SIZE 0xFFFFFF /* restricted by 24 bit counter */ 101#define MAX_DEVICES 10 102#define MAX_TAGS_CMD_QUEUE 256 103#define MAX_CMD_PER_LUN 6 104#define MAX_SRB_CNT 256 105#define MAX_START_JOB 256 106 107/* 108 * BIT position to integer mapping. 109 */ 110#define BIT(N) (0x01 << N) 111 112/* 113 * EEPROM storage offsets and data structures. 114 */ 115typedef struct _EEprom { 116 u_int8_t EE_MODE1; 117 u_int8_t EE_SPEED; 118 u_int8_t xx1; 119 u_int8_t xx2; 120} EEprom, *PEEprom; 121 122#define EE_ADAPT_SCSI_ID 64 123#define EE_MODE2 65 124#define EE_DELAY 66 125#define EE_TAG_CMD_NUM 67 126#define EE_DATA_SIZE 128 127#define EE_CHECKSUM 0x1234 128 129/* 130 * EE_MODE1 bits definition 131 */ 132#define PARITY_CHK BIT(0) 133#define SYNC_NEGO BIT(1) 134#define EN_DISCONNECT BIT(2) 135#define SEND_START BIT(3) 136#define TAG_QUEUING BIT(4) 137 138/* 139 * EE_MODE2 bits definition 140 */ 141#define MORE2_DRV BIT(0) 142#define GREATER_1G BIT(1) 143#define RST_SCSI_BUS BIT(2) 144#define ACTIVE_NEGATION BIT(3) 145#define NO_SEEK BIT(4) 146#define LUN_CHECK BIT(5) 147 148#define ENABLE_CE 1 149#define DISABLE_CE 0 150#define EEPROM_READ 0x80 151 152#define AMD_TAG_WILDCARD ((u_int)(~0)) 153 154/* 155 * SCSI Request Block 156 */ 157struct amd_srb { 158 TAILQ_ENTRY(amd_srb) links; 159 u_int8_t CmdBlock[12]; 160 union ccb *pccb; 161 bus_dmamap_t dmamap; 162 struct amd_sg *pSGlist; 163 164 u_int32_t TotalXferredLen; 165 u_int32_t SGPhysAddr; /* a segment starting address */ 166 u_int32_t SGToBeXferLen; /* to be xfer length */ 167 u_int32_t Segment0[2]; 168 u_int32_t Segment1[2]; 169 170 struct amd_sg SGsegment[AMD_NSEG]; 171 struct amd_sg Segmentx;/* a one entry of S/G list table */ 172 u_int8_t *pMsgPtr; 173 u_int16_t SRBState; 174 175 u_int8_t AdaptStatus; 176 u_int8_t TargetStatus; 177 u_int8_t MsgCnt; 178 u_int8_t EndMessage; 179 u_int8_t TagNumber; 180 u_int8_t SGcount; 181 u_int8_t SGIndex; 182 u_int8_t IORBFlag; /* ;81h-Reset, 2-retry */ 183 184 u_int8_t SRBStatus; 185 u_int8_t SRBFlag; 186 /* ; b0-AutoReqSense,b6-Read,b7-write */ 187 /* ; b4-settimeout,b5-Residual valid */ 188 u_int8_t ScsiCmdLen; 189}; 190 191TAILQ_HEAD(srb_queue, amd_srb); 192 193/* 194 * Per-adapter, software configuration. 195 */ 196struct amd_softc { 197 device_t dev; 198 bus_space_tag_t tag; 199 bus_space_handle_t bsh; 200 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 201 bus_dma_tag_t sense_dmat; /* dmat for sense buffer */ 202 bus_dmamap_t sense_dmamap; 203 struct scsi_sense_data *sense_buffers; 204 bus_addr_t sense_busaddr; 205 int unit; 206 207 int last_phase; 208 int cur_target; 209 int cur_lun; 210 struct amd_srb *active_srb; 211 struct amd_srb *untagged_srbs[AMD_TARGET_MAX+1][AMD_LUN_MAX+1]; 212 struct amd_target_info tinfo[AMD_TARGET_MAX+1]; 213 u_int16_t disc_count[AMD_TARGET_MAX+1][AMD_LUN_MAX+1]; 214 215 struct srb_queue free_srbs; 216 struct srb_queue waiting_srbs; 217 struct srb_queue running_srbs; 218 219 struct amd_srb *pTmpSRB; 220 221 u_int16_t SRBCount; 222 223 u_int16_t max_id; 224 u_int16_t max_lun; 225 226 /* Hooks into the CAM XPT */ 227 struct cam_sim *psim; 228 struct cam_path *ppath; 229 230 u_int8_t msgin_buf[6]; 231 u_int8_t msgout_buf[6]; 232 u_int msgin_index; 233 u_int msgout_index; 234 u_int msgout_len; 235 236 u_int8_t status; 237 u_int8_t AdaptSCSIID; /* ; Adapter SCSI Target ID */ 238 u_int8_t AdaptSCSILUN; /* ; Adapter SCSI LUN */ 239 240 u_int8_t ACBFlag; 241 242 u_int8_t Gmode2; 243 244 u_int8_t HostID_Bit; 245 246 u_int8_t InitDCB_flag[8][8]; /* flag of initDCB for device */ 247 struct amd_srb SRB_array[MAX_SRB_CNT]; /* +45Ch, Len= */ 248 struct amd_srb TmpSRB; 249 /* Setup data stored in an 93c46 serial eeprom */ 250 u_int8_t eepromBuf[EE_DATA_SIZE]; 251}; 252 253/* 254 * ----SRB State machine definition 255 */ 256#define SRB_FREE 0 257#define SRB_READY BIT(1) 258#define SRB_MSGOUT BIT(2) /* ;arbitration+msg_out 1st byte */ 259#define SRB_MSGIN BIT(3) 260#define SRB_MSGIN_MULTI BIT(4) 261#define SRB_COMMAND BIT(5) 262#define SRB_START BIT(6) /* ;arbitration+msg_out+command_out */ 263#define SRB_DISCONNECT BIT(7) 264#define SRB_DATA_XFER BIT(8) 265#define SRB_XFERPAD BIT(9) 266#define SRB_STATUS BIT(10) 267#define SRB_COMPLETED BIT(11) 268#define SRB_ABORT_SENT BIT(12) 269#define DO_SYNC_NEGO BIT(13) 270#define SRB_UNEXPECT_RESEL BIT(14) 271 272/* 273 * ---ACB Flag 274 */ 275#define RESET_DEV BIT(0) 276#define RESET_DETECT BIT(1) 277#define RESET_DONE BIT(2) 278 279/* 280 * ---DCB Flag 281 */ 282#define ABORT_DEV_ BIT(0) 283 284/* 285 * ---SRB status 286 */ 287#define SRB_OK BIT(0) 288#define ABORTION BIT(1) 289#define OVER_RUN BIT(2) 290#define UNDER_RUN BIT(3) 291#define PARITY_ERROR BIT(4) 292#define SRB_ERROR BIT(5) 293 294/* 295 * ---SRB Flags 296 */ 297#define DATAOUT BIT(7) 298#define DATAIN BIT(6) 299#define RESIDUAL_VALID BIT(5) 300#define ENABLE_TIMER BIT(4) 301#define RESET_DEV0 BIT(2) 302#define ABORT_DEV BIT(1) 303#define AUTO_REQSENSE BIT(0) 304 305/* 306 * ---Adapter status 307 */ 308#define H_STATUS_GOOD 0 309#define H_SEL_TIMEOUT 0x11 310#define H_OVER_UNDER_RUN 0x12 311#define H_UNEXP_BUS_FREE 0x13 312#define H_TARGET_PHASE_F 0x14 313#define H_INVALID_CCB_OP 0x16 314#define H_LINK_CCB_BAD 0x17 315#define H_BAD_TARGET_DIR 0x18 316#define H_DUPLICATE_CCB 0x19 317#define H_BAD_CCB_OR_SG 0x1A 318#define H_ABORT 0x0FF 319 320/* 321 * AMD specific "status" codes returned in the SCSI status byte. 322 */ 323#define AMD_SCSI_STAT_UNEXP_BUS_F 0xFD /* ; Unexpect Bus Free */ 324#define AMD_SCSI_STAT_BUS_RST_DETECT 0xFE /* ; Scsi Bus Reset detected */ 325#define AMD_SCSI_STAT_SEL_TIMEOUT 0xFF /* ; Selection Time out */ 326 327/* 328 * ---Sync_Mode 329 */ 330#define SYNC_DISABLE 0 331#define SYNC_ENABLE BIT(0) 332#define SYNC_NEGO_DONE BIT(1) 333#define WIDE_ENABLE BIT(2) 334#define WIDE_NEGO_DONE BIT(3) 335#define EN_TAG_QUEUING BIT(4) 336#define EN_ATN_STOP BIT(5) 337 338#define SYNC_NEGO_OFFSET 15 339 340/* 341 * ---SCSI bus phase 342 */ 343#define SCSI_DATA_OUT 0 344#define SCSI_DATA_IN 1 345#define SCSI_COMMAND 2 346#define SCSI_STATUS 3 347#define SCSI_NOP0 4 348#define SCSI_ARBITRATING 5 349#define SCSI_MSG_OUT 6 350#define SCSI_MSG_IN 7 351#define SCSI_BUS_FREE 8 352 353/* 354 *========================================================== 355 * AMD 53C974 Registers bit Definition 356 *========================================================== 357 */ 358 359/* 360 * ------SCSI Register------- 361 * Command Reg.(+0CH) 362 */ 363#define DMA_COMMAND BIT(7) 364#define NOP_CMD 0 365#define CLEAR_FIFO_CMD 1 366#define RST_DEVICE_CMD 2 367#define RST_SCSI_BUS_CMD 3 368#define INFO_XFER_CMD 0x10 369#define INITIATOR_CMD_CMPLTE 0x11 370#define MSG_ACCEPTED_CMD 0x12 371#define XFER_PAD_BYTE 0x18 372#define SET_ATN_CMD 0x1A 373#define RESET_ATN_CMD 0x1B 374#define SEL_W_ATN 0x42 375#define SEL_W_ATN_STOP 0x43 376#define EN_SEL_RESEL 0x44 377#define SEL_W_ATN2 0x46 378#define DATA_XFER_CMD INFO_XFER_CMD 379 380 381/* 382 * ------SCSI Register------- 383 * SCSI Status Reg.(+10H) 384 */ 385#define INTERRUPT BIT(7) 386#define ILLEGAL_OP_ERR BIT(6) 387#define PARITY_ERR BIT(5) 388#define COUNT_2_ZERO BIT(4) 389#define GROUP_CODE_VALID BIT(3) 390#define SCSI_PHASE_MASK (BIT(2)+BIT(1)+BIT(0)) 391 392/* 393 * ------SCSI Register------- 394 * Interrupt Status Reg.(+14H) 395 */ 396#define SCSI_RESET_ BIT(7) 397#define INVALID_CMD BIT(6) 398#define DISCONNECTED BIT(5) 399#define SERVICE_REQUEST BIT(4) 400#define SUCCESSFUL_OP BIT(3) 401#define RESELECTED BIT(2) 402#define SEL_ATTENTION BIT(1) 403#define SELECTED BIT(0) 404 405/* 406 * ------SCSI Register------- 407 * Internal State Reg.(+18H) 408 */ 409#define SYNC_OFFSET_FLAG BIT(3) 410#define INTRN_STATE_MASK (BIT(2)+BIT(1)+BIT(0)) 411 412/* 413 * ------SCSI Register------- 414 * Clock Factor Reg.(+24H) 415 */ 416#define CLK_FREQ_40MHZ 0 417#define CLK_FREQ_35MHZ (BIT(2)+BIT(1)+BIT(0)) 418#define CLK_FREQ_30MHZ (BIT(2)+BIT(1)) 419#define CLK_FREQ_25MHZ (BIT(2)+BIT(0)) 420#define CLK_FREQ_20MHZ BIT(2) 421#define CLK_FREQ_15MHZ (BIT(1)+BIT(0)) 422#define CLK_FREQ_10MHZ BIT(1) 423 424/* 425 * ------SCSI Register------- 426 * Control Reg. 1(+20H) 427 */ 428#define EXTENDED_TIMING BIT(7) 429#define DIS_INT_ON_SCSI_RST BIT(6) 430#define PARITY_ERR_REPO BIT(4) 431#define SCSI_ID_ON_BUS (BIT(2)+BIT(1)+BIT(0)) 432 433/* 434 * ------SCSI Register------- 435 * Control Reg. 2(+2CH) 436 */ 437#define EN_FEATURE BIT(6) 438#define EN_SCSI2_CMD BIT(3) 439 440/* 441 * ------SCSI Register------- 442 * Control Reg. 3(+30H) 443 */ 444#define ID_MSG_CHECK BIT(7) 445#define EN_QTAG_MSG BIT(6) 446#define EN_GRP2_CMD BIT(5) 447#define FAST_SCSI BIT(4) /* ;10MB/SEC */ 448#define FAST_CLK BIT(3) /* ;25 - 40 MHZ */ 449 450/* 451 * ------SCSI Register------- 452 * Control Reg. 4(+34H) 453 */ 454#define EATER_12NS 0 455#define EATER_25NS BIT(7) 456#define EATER_35NS BIT(6) 457#define EATER_0NS (BIT(7)+BIT(6)) 458#define NEGATE_REQACKDATA BIT(2) 459#define NEGATE_REQACK BIT(3) 460 461/* 462 *======================================== 463 * DMA Register 464 *======================================== 465 */ 466 467/* 468 * -------DMA Register-------- 469 * DMA Command Reg.(+40H) 470 */ 471#define READ_DIRECTION BIT(7) 472#define WRITE_DIRECTION 0 473#define EN_DMA_INT BIT(6) 474#define MAP_TO_MDL BIT(5) 475#define DMA_DIAGNOSTIC BIT(4) 476#define DMA_IDLE_CMD 0 477#define DMA_BLAST_CMD BIT(0) 478#define DMA_ABORT_CMD BIT(1) 479#define DMA_START_CMD (BIT(1)|BIT(0)) 480 481/* 482 * -------DMA Register-------- 483 * DMA Status Reg.(+54H) 484 */ 485#define PCI_MS_ABORT BIT(6) 486#define BLAST_COMPLETE BIT(5) 487#define SCSI_INTERRUPT BIT(4) 488#define DMA_XFER_DONE BIT(3) 489#define DMA_XFER_ABORT BIT(2) 490#define DMA_XFER_ERROR BIT(1) 491#define POWER_DOWN BIT(0) 492 493/* 494 * -------DMA Register-------- 495 * DMA SCSI Bus and Ctrl.(+70H) 496 * EN_INT_ON_PCI_ABORT 497 */ 498 499/* 500 *========================================================== 501 * SCSI Chip register address offset 502 *========================================================== 503 */ 504#define CTCREG_LOW 0x00 /* (R) current transfer count register low */ 505#define STCREG_LOW 0x00 /* (W) start transfer count register low */ 506 507#define CTCREG_MID 0x04 /* (R) current transfer count register 508 * middle */ 509#define STCREG_MID 0x04 /* (W) start transfer count register middle */ 510 511#define SCSIFIFOREG 0x08 /* (R/W) SCSI FIFO register */ 512 513#define SCSICMDREG 0x0C /* (R/W) SCSI command register */ 514 515#define SCSISTATREG 0x10 /* (R) SCSI status register */ 516#define SCSIDESTIDREG 0x10 /* (W) SCSI destination ID register */ 517 518#define INTSTATREG 0x14 /* (R) interrupt status register */ 519#define SCSITIMEOUTREG 0x14 /* (W) SCSI timeout register */ 520 521 522#define INTERNSTATREG 0x18 /* (R) internal state register */ 523#define SYNCPERIOREG 0x18 /* (W) synchronous transfer period register */ 524 525#define CURRENTFIFOREG 0x1C /* (R) current FIFO/internal state register */ 526#define SYNCOFFREG 0x1C/* (W) synchronous transfer period register */ 527 528#define CNTLREG1 0x20 /* (R/W) control register 1 */ 529#define CLKFACTREG 0x24 /* (W) clock factor register */ 530#define CNTLREG2 0x2C /* (R/W) control register 2 */ 531#define CNTLREG3 0x30 /* (R/W) control register 3 */ 532#define CNTLREG4 0x34 /* (R/W) control register 4 */ 533 534#define CURTXTCNTREG 0x38 /* (R) current transfer count register 535 * high/part-unique ID code */ 536#define STCREG_HIGH 0x38 /* (W) Start current transfer count register 537 * high */ 538 539/* 540 ********************************************************* 541 * 542 * SCSI DMA register 543 * 544 ********************************************************* 545 */ 546#define DMA_Cmd 0x40 /* (R/W) command register */ 547#define DMA_XferCnt 0x44 /* (R/W) starting transfer count */ 548#define DMA_XferAddr 0x48 /* (R/W) starting Physical address */ 549#define DMA_Wk_ByteCntr 0x4C /* ( R ) working byte counter */ 550#define DMA_Wk_AddrCntr 0x50 /* ( R ) working address counter */ 551#define DMA_Status 0x54 /* ( R ) status register */ 552#define DMA_MDL_Addr 0x58 /* (R/W) starting memory descriptor list (MDL) 553 * address */ 554#define DMA_Wk_MDL_Cntr 0x5C /* ( R ) working MDL counter */ 555#define DMA_ScsiBusCtrl 0x70 /* (bits R/W) SCSI BUS and control */ 556 557/* ******************************************************* */ 558#define am_target SCSISTATREG 559#define am_timeout INTSTATREG 560#define am_seq_step SYNCPERIOREG 561#define am_fifo_count SYNCOFFREG 562 563 564#define amd_read8(amd, port) \ 565 bus_space_read_1((amd)->tag, (amd)->bsh, port) 566 567#define amd_read16(amd, port) \ 568 bus_space_read_2((amd)->tag, (amd)->bsh, port) 569 570#define amd_read32(amd, port) \ 571 bus_space_read_4((amd)->tag, (amd)->bsh, port) 572 573#define amd_write8(amd, port, value) \ 574 bus_space_write_1((amd)->tag, (amd)->bsh, port, value) 575 576#define amd_write8_multi(amd, port, ptr, len) \ 577 bus_space_write_multi_1((amd)->tag, (amd)->bsh, port, ptr, len) 578 579#define amd_write16(amd, port, value) \ 580 bus_space_write_2((amd)->tag, (amd)->bsh, port, value) 581 582#define amd_write32(amd, port, value) \ 583 bus_space_write_4((amd)->tag, (amd)->bsh, port, value) 584 585#endif /* AMD_H */ 586