1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * Interface to the Thunder specific devices 50 * 51 * <hr>$Revision: 49448 $<hr> 52 * 53 */ 54 55#include "cvmx.h" 56#include "cvmx-sysinfo.h" 57#include "cvmx-thunder.h" 58#include "cvmx-gpio.h" 59#include "cvmx-twsi.h" 60 61 62static const int BYPASS_STATUS = 1<<5; /* GPIO 5 */ 63static const int BYPASS_EN = 1<<6; /* GPIO 6 */ 64static const int WDT_BP_CLR = 1<<7; /* GPIO 7 */ 65 66static const int RTC_CTL_ADDR = 0x7; 67static const int RTC_CTL_BIT_EOSC = 0x80; 68static const int RTC_CTL_BIT_WACE = 0x40; 69static const int RTC_CTL_BIT_WD_ALM = 0x20; 70static const int RTC_CTL_BIT_WDSTR = 0x8; 71static const int RTC_CTL_BIT_AIE = 0x1; 72static const int RTC_WD_ALM_CNT_BYTE0_ADDR = 0x4; 73 74#define CVMX_LAN_BYPASS_MSG(...) do {} while(0) 75 76/* 77 * Board-specifc RTC read 78 * Time is expressed in seconds from epoch (Jan 1 1970 at 00:00:00 UTC) 79 */ 80uint32_t cvmx_rtc_ds1374_read(void) 81{ 82 int retry; 83 uint8_t sec; 84 uint32_t time; 85 86 for(retry=0; retry<2; retry++) 87 { 88 time = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR, 0x0); 89 time |= (cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1374_ADDR) & 0xff) << 8; 90 time |= (cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1374_ADDR) & 0xff) << 16; 91 time |= (cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1374_ADDR) & 0xff) << 24; 92 93 sec = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR, 0x0); 94 if (sec == (time & 0xff)) 95 break; /* Time did not roll-over, value is correct */ 96 } 97 98 return time; 99} 100 101/* 102 * Board-specific RTC write 103 * Time is expressed in seconds from epoch (Jan 1 1970 at 00:00:00 UTC) 104 */ 105int cvmx_rtc_ds1374_write(uint32_t time) 106{ 107 int rc; 108 int retry; 109 uint8_t sec; 110 111 for(retry=0; retry<2; retry++) 112 { 113 rc = cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR, 0x0, time & 0xff); 114 rc |= cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR, 0x1, (time >> 8) & 0xff); 115 rc |= cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR, 0x2, (time >> 16) & 0xff); 116 rc |= cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR, 0x3, (time >> 24) & 0xff); 117 sec = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR, 0x0); 118 if (sec == (time & 0xff)) 119 break; /* Time did not roll-over, value is correct */ 120 } 121 122 return (rc ? -1 : 0); 123} 124 125static int cvmx_rtc_ds1374_alarm_config(int WD, int WDSTR, int AIE) 126{ 127 int val; 128 129 val = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR); 130 val = val & ~RTC_CTL_BIT_EOSC; /* Make sure that oscillator is running */ 131 WD?(val = val | RTC_CTL_BIT_WD_ALM):(val = val & ~RTC_CTL_BIT_WD_ALM); 132 WDSTR?(val = val | RTC_CTL_BIT_WDSTR):(val = val & ~RTC_CTL_BIT_WDSTR); 133 AIE?(val = val | RTC_CTL_BIT_AIE):(val = val & ~RTC_CTL_BIT_AIE); 134 cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR, val); 135 return 0; 136} 137 138static int cvmx_rtc_ds1374_alarm_set(int alarm_on) 139{ 140 uint8_t val; 141 142 if (alarm_on) 143 { 144 val = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR); 145 cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR, val | RTC_CTL_BIT_WACE); 146 } 147 else 148 { 149 val = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR); 150 cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR, val & ~RTC_CTL_BIT_WACE); 151 } 152 return 0; 153} 154 155 156static int cvmx_rtc_ds1374_alarm_counter_set(uint32_t interval) 157{ 158 int i; 159 int rc = 0; 160 161 for(i=0;i<3;i++) 162 { 163 rc |= cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR, RTC_WD_ALM_CNT_BYTE0_ADDR+i, interval & 0xFF); 164 interval >>= 8; 165 } 166 return rc; 167} 168 169#if 0 /* XXX unused */ 170static uint32_t cvmx_rtc_ds1374_alarm_counter_get(void) 171{ 172 int i; 173 uint32_t interval = 0; 174 175 for(i=0;i<3;i++) 176 { 177 interval |= ( cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR,RTC_WD_ALM_CNT_BYTE0_ADDR+i) & 0xff) << (i*8); 178 } 179 return interval; 180} 181#endif 182 183 184#ifdef CVMX_RTC_DEBUG 185 186void cvmx_rtc_ds1374_dump_state(void) 187{ 188 int i = 0; 189 190 cvmx_dprintf("RTC:\n"); 191 cvmx_dprintf("%d : %02X ", i, cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR, 0x0)); 192 for(i=1; i<10; i++) 193 { 194 cvmx_dprintf("%02X ", cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1374_ADDR)); 195 } 196 cvmx_dprintf("\n"); 197} 198 199#endif /* CVMX_RTC_DEBUG */ 200 201 202/* 203 * LAN bypass functionality 204 */ 205 206/* Private initialization function */ 207static int cvmx_lan_bypass_init(void) 208{ 209 const int CLR_PULSE = 100; /* Longer than 100 ns (on CPUs up to 1 GHz) */ 210 211 //Clear GPIO 6 212 cvmx_gpio_clear(BYPASS_EN); 213 214 //Disable WDT 215 cvmx_rtc_ds1374_alarm_set(0); 216 217 //GPIO(7) Send a low pulse 218 cvmx_gpio_clear(WDT_BP_CLR); 219 cvmx_wait(CLR_PULSE); 220 cvmx_gpio_set(WDT_BP_CLR); 221 return 0; 222} 223 224/** 225 * Set LAN bypass mode. 226 * 227 * Supported modes are: 228 * - CVMX_LAN_BYPASS_OFF 229 * <br>LAN ports are connected ( port 0 <--> Octeon <--> port 1 ) 230 * 231 * - CVMX_LAN_BYPASS_GPIO 232 * <br>LAN bypass is controlled by software using cvmx_lan_bypass_force() function. 233 * When transitioning to this mode, default is LAN bypass enabled 234 * ( port 0 <--> port 1, -- Octeon ). 235 * 236 * - CVMX_LAN_BYPASS_WATCHDOG 237 * <br>LAN bypass is inactive as long as a watchdog is kept alive. 238 * The default expiration time is 1 second and the function to 239 * call periodically to prevent watchdog expiration is 240 * cvmx_lan_bypass_keep_alive(). 241 * 242 * @param mode LAN bypass mode 243 * 244 * @return Error code, or 0 in case of success 245 */ 246int cvmx_lan_bypass_mode_set(cvmx_lan_bypass_mode_t mode) 247{ 248 switch(mode) 249 { 250 case CVMX_LAN_BYPASS_GPIO: 251 /* make lan bypass enable */ 252 cvmx_lan_bypass_init(); 253 cvmx_gpio_set(BYPASS_EN); 254 CVMX_LAN_BYPASS_MSG("Enable LAN bypass by GPIO. \n"); 255 break; 256 257 case CVMX_LAN_BYPASS_WATCHDOG: 258 /* make lan bypass enable */ 259 cvmx_lan_bypass_init(); 260 /* Set WDT parameters and turn it on */ 261 cvmx_rtc_ds1374_alarm_counter_set(0x1000); /* 4096 ticks = 1 sec */ 262 cvmx_rtc_ds1374_alarm_config(1,1,1); 263 cvmx_rtc_ds1374_alarm_set(1); 264 CVMX_LAN_BYPASS_MSG("Enable LAN bypass by WDT. \n"); 265 break; 266 267 case CVMX_LAN_BYPASS_OFF: 268 /* make lan bypass disable */ 269 cvmx_lan_bypass_init(); 270 CVMX_LAN_BYPASS_MSG("Disable LAN bypass. \n"); 271 break; 272 273 default: 274 CVMX_LAN_BYPASS_MSG("%s: LAN bypass mode %d not supported\n", __FUNCTION__, mode); 275 break; 276 } 277 return 0; 278} 279 280/** 281 * Refresh watchdog timer. 282 * 283 * Call periodically (less than 1 second) to prevent triggering LAN bypass. 284 * The alternative cvmx_lan_bypass_keep_alive_ms() is provided for cases 285 * where a variable interval is required. 286 */ 287void cvmx_lan_bypass_keep_alive(void) 288{ 289 cvmx_rtc_ds1374_alarm_counter_set(0x1000); /* 4096 ticks = 1 second */ 290} 291 292/** 293 * Refresh watchdog timer, setting a specific expiration interval. 294 * 295 * @param interval_ms Interval, in milliseconds, to next watchdog expiration. 296 */ 297void cvmx_lan_bypass_keep_alive_ms(uint32_t interval_ms) 298{ 299 cvmx_rtc_ds1374_alarm_counter_set((interval_ms * 0x1000) / 1000); 300} 301 302/** 303 * Control LAN bypass via software. 304 * 305 * @param force_bypass Force LAN bypass to active (1) or inactive (0) 306 * 307 * @return Error code, or 0 in case of success 308 */ 309int cvmx_lan_bypass_force(int force_bypass) 310{ 311 if (force_bypass) 312 { 313 //Set GPIO 6 314 cvmx_gpio_set(BYPASS_EN); 315 } 316 else 317 { 318 cvmx_lan_bypass_init(); 319 } 320 return 0; 321} 322 323/** 324 * Return status of LAN bypass circuit. 325 * 326 * @return 1 if ports are in LAN bypass, or 0 if normally connected 327 */ 328int cvmx_lan_bypass_is_active(void) 329{ 330 return !!(cvmx_gpio_read() & BYPASS_STATUS); 331} 332