1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-sriomaintx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon sriomaintx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_SRIOMAINTX_TYPEDEFS_H__ 53#define __CVMX_SRIOMAINTX_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_ID(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 60 cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id); 61 return 0x0000000000000008ull; 62} 63#else 64#define CVMX_SRIOMAINTX_ASMBLY_ID(block_id) (0x0000000000000008ull) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_INFO(unsigned long block_id) 68{ 69 if (!( 70 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 71 cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id); 72 return 0x000000000000000Cull; 73} 74#else 75#define CVMX_SRIOMAINTX_ASMBLY_INFO(block_id) (0x000000000000000Cull) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78static inline uint64_t CVMX_SRIOMAINTX_BAR1_IDXX(unsigned long offset, unsigned long block_id) 79{ 80 if (!( 81 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))))) 82 cvmx_warn("CVMX_SRIOMAINTX_BAR1_IDXX(%lu,%lu) is invalid on this chip\n", offset, block_id); 83 return CVMX_ADD_IO_SEG(0x0000000000200010ull) + (((offset) & 15) + ((block_id) & 1) * 0x0ull) * 4; 84} 85#else 86#define CVMX_SRIOMAINTX_BAR1_IDXX(offset, block_id) (CVMX_ADD_IO_SEG(0x0000000000200010ull) + (((offset) & 15) + ((block_id) & 1) * 0x0ull) * 4) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89static inline uint64_t CVMX_SRIOMAINTX_BELL_STATUS(unsigned long block_id) 90{ 91 if (!( 92 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 93 cvmx_warn("CVMX_SRIOMAINTX_BELL_STATUS(%lu) is invalid on this chip\n", block_id); 94 return 0x0000000000200080ull; 95} 96#else 97#define CVMX_SRIOMAINTX_BELL_STATUS(block_id) (0x0000000000200080ull) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100static inline uint64_t CVMX_SRIOMAINTX_COMP_TAG(unsigned long block_id) 101{ 102 if (!( 103 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 104 cvmx_warn("CVMX_SRIOMAINTX_COMP_TAG(%lu) is invalid on this chip\n", block_id); 105 return 0x000000000000006Cull; 106} 107#else 108#define CVMX_SRIOMAINTX_COMP_TAG(block_id) (0x000000000000006Cull) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111static inline uint64_t CVMX_SRIOMAINTX_CORE_ENABLES(unsigned long block_id) 112{ 113 if (!( 114 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 115 cvmx_warn("CVMX_SRIOMAINTX_CORE_ENABLES(%lu) is invalid on this chip\n", block_id); 116 return 0x0000000000200070ull; 117} 118#else 119#define CVMX_SRIOMAINTX_CORE_ENABLES(block_id) (0x0000000000200070ull) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122static inline uint64_t CVMX_SRIOMAINTX_DEV_ID(unsigned long block_id) 123{ 124 if (!( 125 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 126 cvmx_warn("CVMX_SRIOMAINTX_DEV_ID(%lu) is invalid on this chip\n", block_id); 127 return 0x0000000000000000ull; 128} 129#else 130#define CVMX_SRIOMAINTX_DEV_ID(block_id) (0x0000000000000000ull) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133static inline uint64_t CVMX_SRIOMAINTX_DEV_REV(unsigned long block_id) 134{ 135 if (!( 136 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 137 cvmx_warn("CVMX_SRIOMAINTX_DEV_REV(%lu) is invalid on this chip\n", block_id); 138 return 0x0000000000000004ull; 139} 140#else 141#define CVMX_SRIOMAINTX_DEV_REV(block_id) (0x0000000000000004ull) 142#endif 143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144static inline uint64_t CVMX_SRIOMAINTX_DST_OPS(unsigned long block_id) 145{ 146 if (!( 147 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 148 cvmx_warn("CVMX_SRIOMAINTX_DST_OPS(%lu) is invalid on this chip\n", block_id); 149 return 0x000000000000001Cull; 150} 151#else 152#define CVMX_SRIOMAINTX_DST_OPS(block_id) (0x000000000000001Cull) 153#endif 154#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155static inline uint64_t CVMX_SRIOMAINTX_ERB_ATTR_CAPT(unsigned long block_id) 156{ 157 if (!( 158 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 159 cvmx_warn("CVMX_SRIOMAINTX_ERB_ATTR_CAPT(%lu) is invalid on this chip\n", block_id); 160 return 0x0000000000002048ull; 161} 162#else 163#define CVMX_SRIOMAINTX_ERB_ATTR_CAPT(block_id) (0x0000000000002048ull) 164#endif 165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_DET(unsigned long block_id) 167{ 168 if (!( 169 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 170 cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_DET(%lu) is invalid on this chip\n", block_id); 171 return 0x0000000000002040ull; 172} 173#else 174#define CVMX_SRIOMAINTX_ERB_ERR_DET(block_id) (0x0000000000002040ull) 175#endif 176#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE(unsigned long block_id) 178{ 179 if (!( 180 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 181 cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE(%lu) is invalid on this chip\n", block_id); 182 return 0x0000000000002068ull; 183} 184#else 185#define CVMX_SRIOMAINTX_ERB_ERR_RATE(block_id) (0x0000000000002068ull) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(unsigned long block_id) 189{ 190 if (!( 191 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 192 cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(%lu) is invalid on this chip\n", block_id); 193 return 0x0000000000002044ull; 194} 195#else 196#define CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(block_id) (0x0000000000002044ull) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(unsigned long block_id) 200{ 201 if (!( 202 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 203 cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(%lu) is invalid on this chip\n", block_id); 204 return 0x000000000000206Cull; 205} 206#else 207#define CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(block_id) (0x000000000000206Cull) 208#endif 209#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210static inline uint64_t CVMX_SRIOMAINTX_ERB_HDR(unsigned long block_id) 211{ 212 if (!( 213 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 214 cvmx_warn("CVMX_SRIOMAINTX_ERB_HDR(%lu) is invalid on this chip\n", block_id); 215 return 0x0000000000002000ull; 216} 217#else 218#define CVMX_SRIOMAINTX_ERB_HDR(block_id) (0x0000000000002000ull) 219#endif 220#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(unsigned long block_id) 222{ 223 if (!( 224 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 225 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(%lu) is invalid on this chip\n", block_id); 226 return 0x0000000000002010ull; 227} 228#else 229#define CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(block_id) (0x0000000000002010ull) 230#endif 231#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(unsigned long block_id) 233{ 234 if (!( 235 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 236 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(%lu) is invalid on this chip\n", block_id); 237 return 0x0000000000002014ull; 238} 239#else 240#define CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(block_id) (0x0000000000002014ull) 241#endif 242#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(unsigned long block_id) 244{ 245 if (!( 246 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 247 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(%lu) is invalid on this chip\n", block_id); 248 return 0x000000000000201Cull; 249} 250#else 251#define CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(block_id) (0x000000000000201Cull) 252#endif 253#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID(unsigned long block_id) 255{ 256 if (!( 257 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 258 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID(%lu) is invalid on this chip\n", block_id); 259 return 0x0000000000002028ull; 260} 261#else 262#define CVMX_SRIOMAINTX_ERB_LT_DEV_ID(block_id) (0x0000000000002028ull) 263#endif 264#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(unsigned long block_id) 266{ 267 if (!( 268 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 269 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(%lu) is invalid on this chip\n", block_id); 270 return 0x0000000000002018ull; 271} 272#else 273#define CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(block_id) (0x0000000000002018ull) 274#endif 275#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_DET(unsigned long block_id) 277{ 278 if (!( 279 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 280 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_DET(%lu) is invalid on this chip\n", block_id); 281 return 0x0000000000002008ull; 282} 283#else 284#define CVMX_SRIOMAINTX_ERB_LT_ERR_DET(block_id) (0x0000000000002008ull) 285#endif 286#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_EN(unsigned long block_id) 288{ 289 if (!( 290 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 291 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_EN(%lu) is invalid on this chip\n", block_id); 292 return 0x000000000000200Cull; 293} 294#else 295#define CVMX_SRIOMAINTX_ERB_LT_ERR_EN(block_id) (0x000000000000200Cull) 296#endif 297#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(unsigned long block_id) 299{ 300 if (!( 301 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 302 cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(%lu) is invalid on this chip\n", block_id); 303 return 0x0000000000002050ull; 304} 305#else 306#define CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(block_id) (0x0000000000002050ull) 307#endif 308#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(unsigned long block_id) 310{ 311 if (!( 312 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 313 cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(%lu) is invalid on this chip\n", block_id); 314 return 0x0000000000002054ull; 315} 316#else 317#define CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(block_id) (0x0000000000002054ull) 318#endif 319#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 320static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(unsigned long block_id) 321{ 322 if (!( 323 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 324 cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(%lu) is invalid on this chip\n", block_id); 325 return 0x0000000000002058ull; 326} 327#else 328#define CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(block_id) (0x0000000000002058ull) 329#endif 330#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 331static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(unsigned long block_id) 332{ 333 if (!( 334 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 335 cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(%lu) is invalid on this chip\n", block_id); 336 return 0x000000000000204Cull; 337} 338#else 339#define CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(block_id) (0x000000000000204Cull) 340#endif 341#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342static inline uint64_t CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(unsigned long block_id) 343{ 344 if (!( 345 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 346 cvmx_warn("CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(%lu) is invalid on this chip\n", block_id); 347 return 0x0000000000000068ull; 348} 349#else 350#define CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(block_id) (0x0000000000000068ull) 351#endif 352#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 353static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(unsigned long block_id) 354{ 355 if (!( 356 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 357 cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(%lu) is invalid on this chip\n", block_id); 358 return 0x0000000000102000ull; 359} 360#else 361#define CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(block_id) (0x0000000000102000ull) 362#endif 363#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 364static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(unsigned long block_id) 365{ 366 if (!( 367 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 368 cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(%lu) is invalid on this chip\n", block_id); 369 return 0x0000000000102004ull; 370} 371#else 372#define CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(block_id) (0x0000000000102004ull) 373#endif 374#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 375static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(unsigned long block_id) 376{ 377 if (!( 378 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 379 cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(%lu) is invalid on this chip\n", block_id); 380 return 0x0000000000107028ull; 381} 382#else 383#define CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(block_id) (0x0000000000107028ull) 384#endif 385#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_STAT(unsigned long block_id) 387{ 388 if (!( 389 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 390 cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_STAT(%lu) is invalid on this chip\n", block_id); 391 return 0x000000000010702Cull; 392} 393#else 394#define CVMX_SRIOMAINTX_IR_PD_PHY_STAT(block_id) (0x000000000010702Cull) 395#endif 396#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(unsigned long block_id) 398{ 399 if (!( 400 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 401 cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(%lu) is invalid on this chip\n", block_id); 402 return 0x0000000000107020ull; 403} 404#else 405#define CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(block_id) (0x0000000000107020ull) 406#endif 407#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 408static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_STAT(unsigned long block_id) 409{ 410 if (!( 411 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 412 cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_STAT(%lu) is invalid on this chip\n", block_id); 413 return 0x0000000000107024ull; 414} 415#else 416#define CVMX_SRIOMAINTX_IR_PI_PHY_STAT(block_id) (0x0000000000107024ull) 417#endif 418#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 419static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_CTRL(unsigned long block_id) 420{ 421 if (!( 422 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 423 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_CTRL(%lu) is invalid on this chip\n", block_id); 424 return 0x000000000010700Cull; 425} 426#else 427#define CVMX_SRIOMAINTX_IR_SP_RX_CTRL(block_id) (0x000000000010700Cull) 428#endif 429#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_DATA(unsigned long block_id) 431{ 432 if (!( 433 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 434 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_DATA(%lu) is invalid on this chip\n", block_id); 435 return 0x0000000000107014ull; 436} 437#else 438#define CVMX_SRIOMAINTX_IR_SP_RX_DATA(block_id) (0x0000000000107014ull) 439#endif 440#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 441static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_STAT(unsigned long block_id) 442{ 443 if (!( 444 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 445 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_STAT(%lu) is invalid on this chip\n", block_id); 446 return 0x0000000000107010ull; 447} 448#else 449#define CVMX_SRIOMAINTX_IR_SP_RX_STAT(block_id) (0x0000000000107010ull) 450#endif 451#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_CTRL(unsigned long block_id) 453{ 454 if (!( 455 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 456 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_CTRL(%lu) is invalid on this chip\n", block_id); 457 return 0x0000000000107000ull; 458} 459#else 460#define CVMX_SRIOMAINTX_IR_SP_TX_CTRL(block_id) (0x0000000000107000ull) 461#endif 462#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_DATA(unsigned long block_id) 464{ 465 if (!( 466 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 467 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_DATA(%lu) is invalid on this chip\n", block_id); 468 return 0x0000000000107008ull; 469} 470#else 471#define CVMX_SRIOMAINTX_IR_SP_TX_DATA(block_id) (0x0000000000107008ull) 472#endif 473#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 474static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_STAT(unsigned long block_id) 475{ 476 if (!( 477 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 478 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_STAT(%lu) is invalid on this chip\n", block_id); 479 return 0x0000000000107004ull; 480} 481#else 482#define CVMX_SRIOMAINTX_IR_SP_TX_STAT(block_id) (0x0000000000107004ull) 483#endif 484#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485static inline uint64_t CVMX_SRIOMAINTX_LANE_X_STATUS_0(unsigned long offset, unsigned long block_id) 486{ 487 if (!( 488 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))))) 489 cvmx_warn("CVMX_SRIOMAINTX_LANE_X_STATUS_0(%lu,%lu) is invalid on this chip\n", offset, block_id); 490 return CVMX_ADD_IO_SEG(0x0000000000001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x0ull) * 32; 491} 492#else 493#define CVMX_SRIOMAINTX_LANE_X_STATUS_0(offset, block_id) (CVMX_ADD_IO_SEG(0x0000000000001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x0ull) * 32) 494#endif 495#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496static inline uint64_t CVMX_SRIOMAINTX_LCS_BA0(unsigned long block_id) 497{ 498 if (!( 499 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 500 cvmx_warn("CVMX_SRIOMAINTX_LCS_BA0(%lu) is invalid on this chip\n", block_id); 501 return 0x0000000000000058ull; 502} 503#else 504#define CVMX_SRIOMAINTX_LCS_BA0(block_id) (0x0000000000000058ull) 505#endif 506#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 507static inline uint64_t CVMX_SRIOMAINTX_LCS_BA1(unsigned long block_id) 508{ 509 if (!( 510 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 511 cvmx_warn("CVMX_SRIOMAINTX_LCS_BA1(%lu) is invalid on this chip\n", block_id); 512 return 0x000000000000005Cull; 513} 514#else 515#define CVMX_SRIOMAINTX_LCS_BA1(block_id) (0x000000000000005Cull) 516#endif 517#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 518static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START0(unsigned long block_id) 519{ 520 if (!( 521 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 522 cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START0(%lu) is invalid on this chip\n", block_id); 523 return 0x0000000000200000ull; 524} 525#else 526#define CVMX_SRIOMAINTX_M2S_BAR0_START0(block_id) (0x0000000000200000ull) 527#endif 528#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 529static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START1(unsigned long block_id) 530{ 531 if (!( 532 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 533 cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START1(%lu) is invalid on this chip\n", block_id); 534 return 0x0000000000200004ull; 535} 536#else 537#define CVMX_SRIOMAINTX_M2S_BAR0_START1(block_id) (0x0000000000200004ull) 538#endif 539#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START0(unsigned long block_id) 541{ 542 if (!( 543 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 544 cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START0(%lu) is invalid on this chip\n", block_id); 545 return 0x0000000000200008ull; 546} 547#else 548#define CVMX_SRIOMAINTX_M2S_BAR1_START0(block_id) (0x0000000000200008ull) 549#endif 550#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START1(unsigned long block_id) 552{ 553 if (!( 554 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 555 cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START1(%lu) is invalid on this chip\n", block_id); 556 return 0x000000000020000Cull; 557} 558#else 559#define CVMX_SRIOMAINTX_M2S_BAR1_START1(block_id) (0x000000000020000Cull) 560#endif 561#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 562static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR2_START(unsigned long block_id) 563{ 564 if (!( 565 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 566 cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR2_START(%lu) is invalid on this chip\n", block_id); 567 return 0x0000000000200050ull; 568} 569#else 570#define CVMX_SRIOMAINTX_M2S_BAR2_START(block_id) (0x0000000000200050ull) 571#endif 572#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 573static inline uint64_t CVMX_SRIOMAINTX_MAC_CTRL(unsigned long block_id) 574{ 575 if (!( 576 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 577 cvmx_warn("CVMX_SRIOMAINTX_MAC_CTRL(%lu) is invalid on this chip\n", block_id); 578 return 0x0000000000200068ull; 579} 580#else 581#define CVMX_SRIOMAINTX_MAC_CTRL(block_id) (0x0000000000200068ull) 582#endif 583#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 584static inline uint64_t CVMX_SRIOMAINTX_PE_FEAT(unsigned long block_id) 585{ 586 if (!( 587 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 588 cvmx_warn("CVMX_SRIOMAINTX_PE_FEAT(%lu) is invalid on this chip\n", block_id); 589 return 0x0000000000000010ull; 590} 591#else 592#define CVMX_SRIOMAINTX_PE_FEAT(block_id) (0x0000000000000010ull) 593#endif 594#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 595static inline uint64_t CVMX_SRIOMAINTX_PE_LLC(unsigned long block_id) 596{ 597 if (!( 598 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 599 cvmx_warn("CVMX_SRIOMAINTX_PE_LLC(%lu) is invalid on this chip\n", block_id); 600 return 0x000000000000004Cull; 601} 602#else 603#define CVMX_SRIOMAINTX_PE_LLC(block_id) (0x000000000000004Cull) 604#endif 605#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 606static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL(unsigned long block_id) 607{ 608 if (!( 609 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 610 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL(%lu) is invalid on this chip\n", block_id); 611 return 0x000000000000015Cull; 612} 613#else 614#define CVMX_SRIOMAINTX_PORT_0_CTL(block_id) (0x000000000000015Cull) 615#endif 616#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 617static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL2(unsigned long block_id) 618{ 619 if (!( 620 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 621 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL2(%lu) is invalid on this chip\n", block_id); 622 return 0x0000000000000154ull; 623} 624#else 625#define CVMX_SRIOMAINTX_PORT_0_CTL2(block_id) (0x0000000000000154ull) 626#endif 627#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 628static inline uint64_t CVMX_SRIOMAINTX_PORT_0_ERR_STAT(unsigned long block_id) 629{ 630 if (!( 631 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 632 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_ERR_STAT(%lu) is invalid on this chip\n", block_id); 633 return 0x0000000000000158ull; 634} 635#else 636#define CVMX_SRIOMAINTX_PORT_0_ERR_STAT(block_id) (0x0000000000000158ull) 637#endif 638#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 639static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_REQ(unsigned long block_id) 640{ 641 if (!( 642 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 643 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_REQ(%lu) is invalid on this chip\n", block_id); 644 return 0x0000000000000140ull; 645} 646#else 647#define CVMX_SRIOMAINTX_PORT_0_LINK_REQ(block_id) (0x0000000000000140ull) 648#endif 649#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 650static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_RESP(unsigned long block_id) 651{ 652 if (!( 653 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 654 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_RESP(%lu) is invalid on this chip\n", block_id); 655 return 0x0000000000000144ull; 656} 657#else 658#define CVMX_SRIOMAINTX_PORT_0_LINK_RESP(block_id) (0x0000000000000144ull) 659#endif 660#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 661static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(unsigned long block_id) 662{ 663 if (!( 664 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 665 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(%lu) is invalid on this chip\n", block_id); 666 return 0x0000000000000148ull; 667} 668#else 669#define CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(block_id) (0x0000000000000148ull) 670#endif 671#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 672static inline uint64_t CVMX_SRIOMAINTX_PORT_GEN_CTL(unsigned long block_id) 673{ 674 if (!( 675 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 676 cvmx_warn("CVMX_SRIOMAINTX_PORT_GEN_CTL(%lu) is invalid on this chip\n", block_id); 677 return 0x000000000000013Cull; 678} 679#else 680#define CVMX_SRIOMAINTX_PORT_GEN_CTL(block_id) (0x000000000000013Cull) 681#endif 682#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 683static inline uint64_t CVMX_SRIOMAINTX_PORT_LT_CTL(unsigned long block_id) 684{ 685 if (!( 686 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 687 cvmx_warn("CVMX_SRIOMAINTX_PORT_LT_CTL(%lu) is invalid on this chip\n", block_id); 688 return 0x0000000000000120ull; 689} 690#else 691#define CVMX_SRIOMAINTX_PORT_LT_CTL(block_id) (0x0000000000000120ull) 692#endif 693#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 694static inline uint64_t CVMX_SRIOMAINTX_PORT_MBH0(unsigned long block_id) 695{ 696 if (!( 697 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 698 cvmx_warn("CVMX_SRIOMAINTX_PORT_MBH0(%lu) is invalid on this chip\n", block_id); 699 return 0x0000000000000100ull; 700} 701#else 702#define CVMX_SRIOMAINTX_PORT_MBH0(block_id) (0x0000000000000100ull) 703#endif 704#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 705static inline uint64_t CVMX_SRIOMAINTX_PORT_RT_CTL(unsigned long block_id) 706{ 707 if (!( 708 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 709 cvmx_warn("CVMX_SRIOMAINTX_PORT_RT_CTL(%lu) is invalid on this chip\n", block_id); 710 return 0x0000000000000124ull; 711} 712#else 713#define CVMX_SRIOMAINTX_PORT_RT_CTL(block_id) (0x0000000000000124ull) 714#endif 715#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716static inline uint64_t CVMX_SRIOMAINTX_PORT_TTL_CTL(unsigned long block_id) 717{ 718 if (!( 719 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 720 cvmx_warn("CVMX_SRIOMAINTX_PORT_TTL_CTL(%lu) is invalid on this chip\n", block_id); 721 return 0x000000000000012Cull; 722} 723#else 724#define CVMX_SRIOMAINTX_PORT_TTL_CTL(block_id) (0x000000000000012Cull) 725#endif 726#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 727static inline uint64_t CVMX_SRIOMAINTX_PRI_DEV_ID(unsigned long block_id) 728{ 729 if (!( 730 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 731 cvmx_warn("CVMX_SRIOMAINTX_PRI_DEV_ID(%lu) is invalid on this chip\n", block_id); 732 return 0x0000000000000060ull; 733} 734#else 735#define CVMX_SRIOMAINTX_PRI_DEV_ID(block_id) (0x0000000000000060ull) 736#endif 737#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 738static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_CTRL(unsigned long block_id) 739{ 740 if (!( 741 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 742 cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_CTRL(%lu) is invalid on this chip\n", block_id); 743 return 0x0000000000200064ull; 744} 745#else 746#define CVMX_SRIOMAINTX_SEC_DEV_CTRL(block_id) (0x0000000000200064ull) 747#endif 748#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 749static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_ID(unsigned long block_id) 750{ 751 if (!( 752 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 753 cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_ID(%lu) is invalid on this chip\n", block_id); 754 return 0x0000000000200060ull; 755} 756#else 757#define CVMX_SRIOMAINTX_SEC_DEV_ID(block_id) (0x0000000000200060ull) 758#endif 759#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 760static inline uint64_t CVMX_SRIOMAINTX_SERIAL_LANE_HDR(unsigned long block_id) 761{ 762 if (!( 763 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 764 cvmx_warn("CVMX_SRIOMAINTX_SERIAL_LANE_HDR(%lu) is invalid on this chip\n", block_id); 765 return 0x0000000000001000ull; 766} 767#else 768#define CVMX_SRIOMAINTX_SERIAL_LANE_HDR(block_id) (0x0000000000001000ull) 769#endif 770#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 771static inline uint64_t CVMX_SRIOMAINTX_SRC_OPS(unsigned long block_id) 772{ 773 if (!( 774 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 775 cvmx_warn("CVMX_SRIOMAINTX_SRC_OPS(%lu) is invalid on this chip\n", block_id); 776 return 0x0000000000000018ull; 777} 778#else 779#define CVMX_SRIOMAINTX_SRC_OPS(block_id) (0x0000000000000018ull) 780#endif 781#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 782static inline uint64_t CVMX_SRIOMAINTX_TX_DROP(unsigned long block_id) 783{ 784 if (!( 785 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 786 cvmx_warn("CVMX_SRIOMAINTX_TX_DROP(%lu) is invalid on this chip\n", block_id); 787 return 0x000000000020006Cull; 788} 789#else 790#define CVMX_SRIOMAINTX_TX_DROP(block_id) (0x000000000020006Cull) 791#endif 792 793/** 794 * cvmx_sriomaint#_asmbly_id 795 * 796 * SRIOMAINT_ASMBLY_ID = SRIO Assembly ID 797 * 798 * The Assembly ID register shows the Assembly ID and Vendor 799 * 800 * Notes: 801 * The Assembly ID register shows the Assembly ID and Vendor specified in $SRIO_ASMBLY_ID. 802 * 803 * Clk_Rst: SRIOMAINT(0..1)_ASMBLY_ID hclk hrst_n 804 */ 805union cvmx_sriomaintx_asmbly_id 806{ 807 uint32_t u32; 808 struct cvmx_sriomaintx_asmbly_id_s 809 { 810#if __BYTE_ORDER == __BIG_ENDIAN 811 uint32_t assy_id : 16; /**< Assembly Identifer */ 812 uint32_t assy_ven : 16; /**< Assembly Vendor Identifer */ 813#else 814 uint32_t assy_ven : 16; 815 uint32_t assy_id : 16; 816#endif 817 } s; 818 struct cvmx_sriomaintx_asmbly_id_s cn63xx; 819 struct cvmx_sriomaintx_asmbly_id_s cn63xxp1; 820}; 821typedef union cvmx_sriomaintx_asmbly_id cvmx_sriomaintx_asmbly_id_t; 822 823/** 824 * cvmx_sriomaint#_asmbly_info 825 * 826 * SRIOMAINT_ASMBLY_INFO = SRIO Assembly Information 827 * 828 * The Assembly Info register shows the Assembly Revision specified in $SRIO_ASMBLY_INFO 829 * 830 * Notes: 831 * The Assembly Info register shows the Assembly Revision specified in $SRIO_ASMBLY_INFO and Extended 832 * Feature Pointer. 833 * 834 * Clk_Rst: SRIOMAINT(0..1)_ASMBLY_INFO hclk hrst_n 835 */ 836union cvmx_sriomaintx_asmbly_info 837{ 838 uint32_t u32; 839 struct cvmx_sriomaintx_asmbly_info_s 840 { 841#if __BYTE_ORDER == __BIG_ENDIAN 842 uint32_t assy_rev : 16; /**< Assembly Revision */ 843 uint32_t ext_fptr : 16; /**< Pointer to the first entry in the extended feature 844 list. */ 845#else 846 uint32_t ext_fptr : 16; 847 uint32_t assy_rev : 16; 848#endif 849 } s; 850 struct cvmx_sriomaintx_asmbly_info_s cn63xx; 851 struct cvmx_sriomaintx_asmbly_info_s cn63xxp1; 852}; 853typedef union cvmx_sriomaintx_asmbly_info cvmx_sriomaintx_asmbly_info_t; 854 855/** 856 * cvmx_sriomaint#_bar1_idx# 857 * 858 * SRIOMAINT_BAR1_IDXX = SRIO BAR1 IndexX Register 859 * 860 * Contains address index and control bits for access to memory ranges of BAR1. 861 * 862 * Notes: 863 * This register specifies the Octeon address, endian swap and cache status associated with each of 864 * the 16 BAR1 entries. The local address bits used are based on the BARSIZE field located in the 865 * SRIOMAINT(0..1)_M2S_BAR1_START0 register. This register is only writeable over SRIO if the 866 * SRIO(0..1)_ACC_CTRL.DENY_BAR1 bit is zero. 867 * 868 * Clk_Rst: SRIOMAINT(0..1)_BAR1_IDX[0:15] hclk hrst_n 869 */ 870union cvmx_sriomaintx_bar1_idxx 871{ 872 uint32_t u32; 873 struct cvmx_sriomaintx_bar1_idxx_s 874 { 875#if __BYTE_ORDER == __BIG_ENDIAN 876 uint32_t reserved_30_31 : 2; 877 uint32_t la : 22; /**< L2/DRAM Address bits [37:16] 878 Not all LA[21:0] bits are used by SRIO hardware, 879 depending on SRIOMAINT(0..1)_M2S_BAR1_START1[BARSIZE]. 880 881 Become 882 L2/DRAM 883 Address Entry 884 BARSIZE LA Bits Used Bits Size 885 0 LA[21:0] [37:16] 64KB 886 1 LA[21:1] [37:17] 128KB 887 2 LA[21:2] [37:18] 256KB 888 3 LA[21:3] [37:19] 512KB 889 4 LA[21:4] [37:20] 1MB 890 5 LA[21:5] [37:21] 2MB 891 6 LA[21:6] [37:22] 4MB 892 7 LA[21:7] [37:23] 8MB 893 8 ** not in pass 1 894 9 ** not in pass 1 895 10 ** not in pass 1 896 11 ** not in pass 1 897 12 ** not in pass 1 898 13 ** not in pass 1 */ 899 uint32_t reserved_6_7 : 2; 900 uint32_t es : 2; /**< Endian Swap Mode. 901 0 = No Swap 902 1 = 64-bit Swap Bytes [ABCD_EFGH] -> [HGFE_DCBA] 903 2 = 32-bit Swap Words [ABCD_EFGH] -> [DCBA_HGFE] 904 3 = 32-bit Word Exch [ABCD_EFGH] -> [EFGH_ABCD] */ 905 uint32_t nca : 1; /**< Non-Cacheable Access Mode. When set, transfers 906 through this window are not cacheable. */ 907 uint32_t reserved_1_2 : 2; 908 uint32_t enable : 1; /**< When set the selected index address is valid. */ 909#else 910 uint32_t enable : 1; 911 uint32_t reserved_1_2 : 2; 912 uint32_t nca : 1; 913 uint32_t es : 2; 914 uint32_t reserved_6_7 : 2; 915 uint32_t la : 22; 916 uint32_t reserved_30_31 : 2; 917#endif 918 } s; 919 struct cvmx_sriomaintx_bar1_idxx_s cn63xx; 920 struct cvmx_sriomaintx_bar1_idxx_s cn63xxp1; 921}; 922typedef union cvmx_sriomaintx_bar1_idxx cvmx_sriomaintx_bar1_idxx_t; 923 924/** 925 * cvmx_sriomaint#_bell_status 926 * 927 * SRIOMAINT_BELL_STATUS = SRIO Incoming Doorbell Status 928 * 929 * The SRIO Incoming (RX) Doorbell Status 930 * 931 * Notes: 932 * This register displays the status of the doorbells received. If FULL is set the SRIO device will 933 * retry incoming transactions. 934 * 935 * Clk_Rst: SRIOMAINT(0..1)_BELL_STATUS hclk hrst_n 936 */ 937union cvmx_sriomaintx_bell_status 938{ 939 uint32_t u32; 940 struct cvmx_sriomaintx_bell_status_s 941 { 942#if __BYTE_ORDER == __BIG_ENDIAN 943 uint32_t reserved_1_31 : 31; 944 uint32_t full : 1; /**< Not able to receive Doorbell Transactions */ 945#else 946 uint32_t full : 1; 947 uint32_t reserved_1_31 : 31; 948#endif 949 } s; 950 struct cvmx_sriomaintx_bell_status_s cn63xx; 951 struct cvmx_sriomaintx_bell_status_s cn63xxp1; 952}; 953typedef union cvmx_sriomaintx_bell_status cvmx_sriomaintx_bell_status_t; 954 955/** 956 * cvmx_sriomaint#_comp_tag 957 * 958 * SRIOMAINT_COMP_TAG = SRIO Component Tag 959 * 960 * Component Tag 961 * 962 * Notes: 963 * This register contains a component tag value for the processing element and the value can be 964 * assigned by software when the device is initialized. 965 * 966 * Clk_Rst: SRIOMAINT(0..1)_COMP_TAG hclk hrst_n 967 */ 968union cvmx_sriomaintx_comp_tag 969{ 970 uint32_t u32; 971 struct cvmx_sriomaintx_comp_tag_s 972 { 973#if __BYTE_ORDER == __BIG_ENDIAN 974 uint32_t comp_tag : 32; /**< Component Tag for Firmware Use */ 975#else 976 uint32_t comp_tag : 32; 977#endif 978 } s; 979 struct cvmx_sriomaintx_comp_tag_s cn63xx; 980 struct cvmx_sriomaintx_comp_tag_s cn63xxp1; 981}; 982typedef union cvmx_sriomaintx_comp_tag cvmx_sriomaintx_comp_tag_t; 983 984/** 985 * cvmx_sriomaint#_core_enables 986 * 987 * SRIOMAINT_CORE_ENABLES = SRIO Core Control 988 * 989 * Core Control 990 * 991 * Notes: 992 * This register displays the reset state of the Octeon Core Logic while the SRIO Link is running. 993 * The bit should be set after the software has initialized the chip to allow memory operations. 994 * 995 * Clk_Rst: SRIOMAINT(0..1)_CORE_ENABLES hclk hrst_n, srst_n 996 */ 997union cvmx_sriomaintx_core_enables 998{ 999 uint32_t u32; 1000 struct cvmx_sriomaintx_core_enables_s 1001 { 1002#if __BYTE_ORDER == __BIG_ENDIAN 1003 uint32_t reserved_5_31 : 27; 1004 uint32_t halt : 1; /**< OCTEON currently in Reset 1005 0 = All OCTEON resources are available. 1006 1 = The OCTEON is in reset. When this bit is set, 1007 SRIO maintenance registers can be accessed, 1008 but BAR0, BAR1, and BAR2 cannot be. */ 1009 uint32_t imsg1 : 1; /**< Allow Incoming Message Unit 1 Operations 1010 Note: This bit is cleared when the C63XX is reset 1011 0 = SRIO Incoming Messages to Unit 1 ignored and 1012 return error response 1013 1 = SRIO Incoming Messages to Unit 1 */ 1014 uint32_t imsg0 : 1; /**< Allow Incoming Message Unit 0 Operations 1015 Note: This bit is cleared when the C63XX is reset 1016 0 = SRIO Incoming Messages to Unit 0 ignored and 1017 return error response 1018 1 = SRIO Incoming Messages to Unit 0 */ 1019 uint32_t doorbell : 1; /**< Allow Inbound Doorbell Operations 1020 Note: This bit is cleared when the C63XX is reset 1021 0 = SRIO Doorbell OPs ignored and return error 1022 response 1023 1 = SRIO Doorbell OPs Allowed */ 1024 uint32_t memory : 1; /**< Allow Inbound/Outbound Memory Operations 1025 Note: This bit is cleared when the C63XX is reset 1026 0 = SRIO Incoming Nwrites and Swrites are 1027 dropped. Incoming Nreads, Atomics and 1028 NwriteRs return responses with ERROR status. 1029 SRIO Incoming Maintenance BAR Memory Accesses 1030 are processed normally. 1031 Outgoing Store Operations are Dropped 1032 Outgoing Load Operations are not issued and 1033 return all 1's with an ERROR status. 1034 In Flight Operations started while the bit is 1035 set in both directions will complete normally. 1036 1 = SRIO Memory Read/Write OPs Allowed */ 1037#else 1038 uint32_t memory : 1; 1039 uint32_t doorbell : 1; 1040 uint32_t imsg0 : 1; 1041 uint32_t imsg1 : 1; 1042 uint32_t halt : 1; 1043 uint32_t reserved_5_31 : 27; 1044#endif 1045 } s; 1046 struct cvmx_sriomaintx_core_enables_s cn63xx; 1047 struct cvmx_sriomaintx_core_enables_s cn63xxp1; 1048}; 1049typedef union cvmx_sriomaintx_core_enables cvmx_sriomaintx_core_enables_t; 1050 1051/** 1052 * cvmx_sriomaint#_dev_id 1053 * 1054 * SRIOMAINT_DEV_ID = SRIO Device ID 1055 * 1056 * The DeviceVendor Identity field identifies the vendor that manufactured the device 1057 * 1058 * Notes: 1059 * This register identifies Cavium Networks and the Product ID. 1060 * 1061 * Clk_Rst: SRIOMAINT(0..1)_DEV_ID hclk hrst_n 1062 */ 1063union cvmx_sriomaintx_dev_id 1064{ 1065 uint32_t u32; 1066 struct cvmx_sriomaintx_dev_id_s 1067 { 1068#if __BYTE_ORDER == __BIG_ENDIAN 1069 uint32_t device : 16; /**< Product Identity */ 1070 uint32_t vendor : 16; /**< Cavium Vendor Identity */ 1071#else 1072 uint32_t vendor : 16; 1073 uint32_t device : 16; 1074#endif 1075 } s; 1076 struct cvmx_sriomaintx_dev_id_s cn63xx; 1077 struct cvmx_sriomaintx_dev_id_s cn63xxp1; 1078}; 1079typedef union cvmx_sriomaintx_dev_id cvmx_sriomaintx_dev_id_t; 1080 1081/** 1082 * cvmx_sriomaint#_dev_rev 1083 * 1084 * SRIOMAINT_DEV_REV = SRIO Device Revision 1085 * 1086 * The Device Revision register identifies the chip pass and revision 1087 * 1088 * Notes: 1089 * This register identifies the chip pass and revision derived from the fuses. 1090 * 1091 * Clk_Rst: SRIOMAINT(0..1)_DEV_REV hclk hrst_n 1092 */ 1093union cvmx_sriomaintx_dev_rev 1094{ 1095 uint32_t u32; 1096 struct cvmx_sriomaintx_dev_rev_s 1097 { 1098#if __BYTE_ORDER == __BIG_ENDIAN 1099 uint32_t reserved_8_31 : 24; 1100 uint32_t revision : 8; /**< Chip Pass/Revision */ 1101#else 1102 uint32_t revision : 8; 1103 uint32_t reserved_8_31 : 24; 1104#endif 1105 } s; 1106 struct cvmx_sriomaintx_dev_rev_s cn63xx; 1107 struct cvmx_sriomaintx_dev_rev_s cn63xxp1; 1108}; 1109typedef union cvmx_sriomaintx_dev_rev cvmx_sriomaintx_dev_rev_t; 1110 1111/** 1112 * cvmx_sriomaint#_dst_ops 1113 * 1114 * SRIOMAINT_DST_OPS = SRIO Source Operations 1115 * 1116 * The logical operations supported from external devices. 1117 * 1118 * Notes: 1119 * The logical operations supported from external devices. The Destination OPs register shows the 1120 * operations specified in the SRIO(0..1)_IP_FEATURE.OPS register. 1121 * 1122 * Clk_Rst: SRIOMAINT(0..1)_DST_OPS hclk hrst_n 1123 */ 1124union cvmx_sriomaintx_dst_ops 1125{ 1126 uint32_t u32; 1127 struct cvmx_sriomaintx_dst_ops_s 1128 { 1129#if __BYTE_ORDER == __BIG_ENDIAN 1130 uint32_t gsm_read : 1; /**< PE does not support Read Home operations. 1131 This is a RO copy of SRIO*_IP_FEATURE[OPS<31>] */ 1132 uint32_t i_read : 1; /**< PE does not support Instruction Read. 1133 This is a RO copy of SRIO*_IP_FEATURE[OPS<30>] */ 1134 uint32_t rd_own : 1; /**< PE does not support Read for Ownership. 1135 This is a RO copy of SRIO*_IP_FEATURE[OPS<29>] */ 1136 uint32_t d_invald : 1; /**< PE does not support Data Cache Invalidate. 1137 This is a RO copy of SRIO*_IP_FEATURE[OPS<28>] */ 1138 uint32_t castout : 1; /**< PE does not support Castout Operations. 1139 This is a RO copy of SRIO*_IP_FEATURE[OPS<27>] */ 1140 uint32_t d_flush : 1; /**< PE does not support Data Cache Flush. 1141 This is a RO copy of SRIO*_IP_FEATURE[OPS<26>] */ 1142 uint32_t io_read : 1; /**< PE does not support IO Read. 1143 This is a RO copy of SRIO*_IP_FEATURE[OPS<25>] */ 1144 uint32_t i_invald : 1; /**< PE does not support Instruction Cache Invalidate. 1145 This is a RO copy of SRIO*_IP_FEATURE[OPS<24>] */ 1146 uint32_t tlb_inv : 1; /**< PE does not support TLB Entry Invalidate. 1147 This is a RO copy of SRIO*_IP_FEATURE[OPS<23>] */ 1148 uint32_t tlb_invs : 1; /**< PE does not support TLB Entry Invalidate Sync. 1149 This is a RO copy of SRIO*_IP_FEATURE[OPS<22>] */ 1150 uint32_t reserved_16_21 : 6; 1151 uint32_t read : 1; /**< PE can support Nread operations. 1152 This is a RO copy of SRIO*_IP_FEATURE[OPS<15>] */ 1153 uint32_t write : 1; /**< PE can support Nwrite operations. 1154 This is a RO copy of SRIO*_IP_FEATURE[OPS<14>] */ 1155 uint32_t swrite : 1; /**< PE can support Swrite operations. 1156 This is a RO copy of SRIO*_IP_FEATURE[OPS<13>] */ 1157 uint32_t write_r : 1; /**< PE can support Write with Response operations. 1158 This is a RO copy of SRIO*_IP_FEATURE[OPS<12>] */ 1159 uint32_t msg : 1; /**< PE can support Data Message operations. 1160 This is a RO copy of SRIO*_IP_FEATURE[OPS<11>] */ 1161 uint32_t doorbell : 1; /**< PE can support Doorbell operations. 1162 This is a RO copy of SRIO*_IP_FEATURE[OPS<10>] */ 1163 uint32_t compswap : 1; /**< PE does not support Atomic Compare and Swap. 1164 This is a RO copy of SRIO*_IP_FEATURE[OPS<9>] */ 1165 uint32_t testswap : 1; /**< PE does not support Atomic Test and Swap. 1166 This is a RO copy of SRIO*_IP_FEATURE[OPS<8>] */ 1167 uint32_t atom_inc : 1; /**< PE can support Atomic increment operations. 1168 This is a RO copy of SRIO*_IP_FEATURE[OPS<7>] */ 1169 uint32_t atom_dec : 1; /**< PE can support Atomic decrement operations. 1170 This is a RO copy of SRIO*_IP_FEATURE[OPS<6>] */ 1171 uint32_t atom_set : 1; /**< PE can support Atomic set operations. 1172 This is a RO copy of SRIO*_IP_FEATURE[OPS<5>] */ 1173 uint32_t atom_clr : 1; /**< PE can support Atomic clear operations. 1174 This is a RO copy of SRIO*_IP_FEATURE[OPS<4>] */ 1175 uint32_t atom_swp : 1; /**< PE does not support Atomic Swap. 1176 This is a RO copy of SRIO*_IP_FEATURE[OPS<3>] */ 1177 uint32_t port_wr : 1; /**< PE can Port Write operations. 1178 This is a RO copy of SRIO*_IP_FEATURE[OPS<2>] */ 1179 uint32_t reserved_0_1 : 2; 1180#else 1181 uint32_t reserved_0_1 : 2; 1182 uint32_t port_wr : 1; 1183 uint32_t atom_swp : 1; 1184 uint32_t atom_clr : 1; 1185 uint32_t atom_set : 1; 1186 uint32_t atom_dec : 1; 1187 uint32_t atom_inc : 1; 1188 uint32_t testswap : 1; 1189 uint32_t compswap : 1; 1190 uint32_t doorbell : 1; 1191 uint32_t msg : 1; 1192 uint32_t write_r : 1; 1193 uint32_t swrite : 1; 1194 uint32_t write : 1; 1195 uint32_t read : 1; 1196 uint32_t reserved_16_21 : 6; 1197 uint32_t tlb_invs : 1; 1198 uint32_t tlb_inv : 1; 1199 uint32_t i_invald : 1; 1200 uint32_t io_read : 1; 1201 uint32_t d_flush : 1; 1202 uint32_t castout : 1; 1203 uint32_t d_invald : 1; 1204 uint32_t rd_own : 1; 1205 uint32_t i_read : 1; 1206 uint32_t gsm_read : 1; 1207#endif 1208 } s; 1209 struct cvmx_sriomaintx_dst_ops_s cn63xx; 1210 struct cvmx_sriomaintx_dst_ops_s cn63xxp1; 1211}; 1212typedef union cvmx_sriomaintx_dst_ops cvmx_sriomaintx_dst_ops_t; 1213 1214/** 1215 * cvmx_sriomaint#_erb_attr_capt 1216 * 1217 * SRIOMAINT_ERB_ATTR_CAPT = SRIO Attributes Capture 1218 * 1219 * Attributes Capture 1220 * 1221 * Notes: 1222 * This register contains the information captured during the error. 1223 * The HW will not update this register (i.e. this register is locked) while 1224 * VALID is set in this CSR. 1225 * The HW sets SRIO_INT_REG[PHY_ERB] every time it sets VALID in this CSR. 1226 * To handle the interrupt, the following procedure may be best: 1227 * (1) clear SRIO_INT_REG[PHY_ERB], 1228 * (2) read this CSR, corresponding SRIOMAINT*_ERB_ERR_DET, SRIOMAINT*_ERB_PACK_SYM_CAPT, 1229 * SRIOMAINT*_ERB_PACK_CAPT_1, SRIOMAINT*_ERB_PACK_CAPT_2, and SRIOMAINT*_ERB_PACK_CAPT_3 1230 * (3) Write VALID in this CSR to 0. 1231 * 1232 * Clk_Rst: SRIOMAINT(0..1)_ERB_ATTR_CAPT hclk hrst_n 1233 */ 1234union cvmx_sriomaintx_erb_attr_capt 1235{ 1236 uint32_t u32; 1237 struct cvmx_sriomaintx_erb_attr_capt_s 1238 { 1239#if __BYTE_ORDER == __BIG_ENDIAN 1240 uint32_t inf_type : 3; /**< Type of Information Logged. 1241 000 - Packet 1242 010 - Short Control Symbol 1243 (use only first capture register) 1244 All Others Reserved */ 1245 uint32_t err_type : 5; /**< The encoded value of the 31 minus the bit in 1246 SRIOMAINT(0..1)_ERB_ERR_DET that describes the error 1247 captured in SRIOMAINT(0..1)_ERB_*CAPT Registers. 1248 (For example a value of 5 indicates 31-5 = bit 26) */ 1249 uint32_t err_info : 20; /**< Error Info. (Pass 2) 1250 ERR_TYPE Bits Description 1251 0 23 TX Protocol Error 1252 22 RX Protocol Error 1253 21 TX Link Response Timeout 1254 20 TX ACKID Timeout 1255 - 19:16 Reserved 1256 - 15:12 TX Protocol ID 1257 1 = Rcvd Unexpected Link Response 1258 2 = Rcvd Link Response before Req 1259 3 = Rcvd NACK servicing NACK 1260 4 = Rcvd NACK 1261 5 = Rcvd RETRY servicing RETRY 1262 6 = Rcvd RETRY servicing NACK 1263 7 = Rcvd ACK servicing RETRY 1264 8 = Rcvd ACK servicing NACK 1265 9 = Unexp ACKID on ACK or RETRY 1266 10 = Unexp ACK or RETRY 1267 - 11:8 Reserved 1268 - 7:4 RX Protocol ID 1269 1 = Rcvd EOP w/o Prev SOP 1270 2 = Rcvd STOMP w/o Prev SOP 1271 3 = Unexp RESTART 1272 4 = Redundant Status from LinkReq 1273 9-16 23:20 RX K Bits 1274 - 19:0 Reserved 1275 26 23:20 RX K Bits 1276 - 19:0 Reserved 1277 27 23:12 Type 1278 0x000 TX 1279 0x010 RX 1280 - 11:8 RX or TX Protocol ID (see above) 1281 - 7:4 Reserved 1282 30 23:20 RX K Bits 1283 - 19:0 Reserved 1284 31 23:16 ACKID Timeout 0x2 1285 - 15:14 Reserved 1286 - 13:8 AckID 1287 - 7:4 Reserved 1288 All others ERR_TYPEs are reserved. */ 1289 uint32_t reserved_1_3 : 3; 1290 uint32_t valid : 1; /**< This bit is set by hardware to indicate that the 1291 Packet/control symbol capture registers contain 1292 valid information. For control symbols, only 1293 capture register 0 will contain meaningful 1294 information. This bit must be cleared by software 1295 to allow capture of other errors. */ 1296#else 1297 uint32_t valid : 1; 1298 uint32_t reserved_1_3 : 3; 1299 uint32_t err_info : 20; 1300 uint32_t err_type : 5; 1301 uint32_t inf_type : 3; 1302#endif 1303 } s; 1304 struct cvmx_sriomaintx_erb_attr_capt_s cn63xx; 1305 struct cvmx_sriomaintx_erb_attr_capt_cn63xxp1 1306 { 1307#if __BYTE_ORDER == __BIG_ENDIAN 1308 uint32_t inf_type : 3; /**< Type of Information Logged. 1309 000 - Packet 1310 010 - Short Control Symbol 1311 (use only first capture register) 1312 All Others Reserved */ 1313 uint32_t err_type : 5; /**< The encoded value of the 31 minus the bit in 1314 SRIOMAINT(0..1)_ERB_ERR_DET that describes the error 1315 captured in SRIOMAINT(0..1)_ERB_*CAPT Registers. 1316 (For example a value of 5 indicates 31-5 = bit 26) */ 1317 uint32_t reserved_1_23 : 23; 1318 uint32_t valid : 1; /**< This bit is set by hardware to indicate that the 1319 Packet/control symbol capture registers contain 1320 valid information. For control symbols, only 1321 capture register 0 will contain meaningful 1322 information. This bit must be cleared by software 1323 to allow capture of other errors. */ 1324#else 1325 uint32_t valid : 1; 1326 uint32_t reserved_1_23 : 23; 1327 uint32_t err_type : 5; 1328 uint32_t inf_type : 3; 1329#endif 1330 } cn63xxp1; 1331}; 1332typedef union cvmx_sriomaintx_erb_attr_capt cvmx_sriomaintx_erb_attr_capt_t; 1333 1334/** 1335 * cvmx_sriomaint#_erb_err_det 1336 * 1337 * SRIOMAINT_ERB_ERR_DET = SRIO Error Detect 1338 * 1339 * Error Detect 1340 * 1341 * Notes: 1342 * The Error Detect Register indicates physical layer transmission errors detected by the hardware. 1343 * The HW will not update this register (i.e. this register is locked) while 1344 * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. 1345 * 1346 * Clk_Rst: SRIOMAINT(0..1)_ERB_ERR_DET hclk hrst_n 1347 */ 1348union cvmx_sriomaintx_erb_err_det 1349{ 1350 uint32_t u32; 1351 struct cvmx_sriomaintx_erb_err_det_s 1352 { 1353#if __BYTE_ORDER == __BIG_ENDIAN 1354 uint32_t imp_err : 1; /**< Implementation Specific Error added for Pass 2. */ 1355 uint32_t reserved_23_30 : 8; 1356 uint32_t ctl_crc : 1; /**< Received a control symbol with a bad CRC value 1357 Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1358 uint32_t uns_id : 1; /**< Received an acknowledge control symbol with an 1359 unexpected ackID (packet-accepted or packet_retry) 1360 Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1361 uint32_t nack : 1; /**< Received packet-not-accepted acknowledge control 1362 symbols. 1363 Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1364 uint32_t out_ack : 1; /**< Received packet with unexpected ackID value 1365 Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1366 uint32_t pkt_crc : 1; /**< Received a packet with a bad CRC value 1367 Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1368 uint32_t size : 1; /**< Received packet which exceeds the maximum allowed 1369 size of 276 bytes. 1370 Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1371 uint32_t inv_char : 1; /**< Received illegal, 8B/10B error or undefined 1372 codegroup within a packet. (Pass 2) 1373 Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1374 uint32_t inv_data : 1; /**< Received data codegroup or 8B/10B error within an 1375 IDLE sequence. (Pass 2) 1376 Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1377 uint32_t reserved_6_14 : 9; 1378 uint32_t bad_ack : 1; /**< Link_response received with an ackID that is not 1379 outstanding. 1380 Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1381 uint32_t proterr : 1; /**< An unexpected packet or control symbol was 1382 received. 1383 Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1384 uint32_t f_toggle : 1; /**< Reserved. */ 1385 uint32_t del_err : 1; /**< Received illegal or undefined codegroup. 1386 (either INV_DATA or INV_CHAR) (Pass 2) 1387 Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1388 uint32_t uns_ack : 1; /**< An unexpected acknowledge control symbol was 1389 received. 1390 Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1391 uint32_t lnk_tout : 1; /**< An acknowledge or link-response control symbol is 1392 not received within the specified timeout interval 1393 Partial Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1394#else 1395 uint32_t lnk_tout : 1; 1396 uint32_t uns_ack : 1; 1397 uint32_t del_err : 1; 1398 uint32_t f_toggle : 1; 1399 uint32_t proterr : 1; 1400 uint32_t bad_ack : 1; 1401 uint32_t reserved_6_14 : 9; 1402 uint32_t inv_data : 1; 1403 uint32_t inv_char : 1; 1404 uint32_t size : 1; 1405 uint32_t pkt_crc : 1; 1406 uint32_t out_ack : 1; 1407 uint32_t nack : 1; 1408 uint32_t uns_id : 1; 1409 uint32_t ctl_crc : 1; 1410 uint32_t reserved_23_30 : 8; 1411 uint32_t imp_err : 1; 1412#endif 1413 } s; 1414 struct cvmx_sriomaintx_erb_err_det_s cn63xx; 1415 struct cvmx_sriomaintx_erb_err_det_cn63xxp1 1416 { 1417#if __BYTE_ORDER == __BIG_ENDIAN 1418 uint32_t reserved_23_31 : 9; 1419 uint32_t ctl_crc : 1; /**< Received a control symbol with a bad CRC value 1420 Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1421 uint32_t uns_id : 1; /**< Received an acknowledge control symbol with an 1422 unexpected ackID (packet-accepted or packet_retry) 1423 Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1424 uint32_t nack : 1; /**< Received packet-not-accepted acknowledge control 1425 symbols. 1426 Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1427 uint32_t out_ack : 1; /**< Received packet with unexpected ackID value 1428 Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1429 uint32_t pkt_crc : 1; /**< Received a packet with a bad CRC value 1430 Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1431 uint32_t size : 1; /**< Received packet which exceeds the maximum allowed 1432 size of 276 bytes. 1433 Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1434 uint32_t reserved_6_16 : 11; 1435 uint32_t bad_ack : 1; /**< Link_response received with an ackID that is not 1436 outstanding. 1437 Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1438 uint32_t proterr : 1; /**< An unexpected packet or control symbol was 1439 received. 1440 Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1441 uint32_t f_toggle : 1; /**< Reserved. */ 1442 uint32_t del_err : 1; /**< Received illegal or undefined codegroup. 1443 (either INV_DATA or INV_CHAR) (Pass 2) 1444 Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1445 uint32_t uns_ack : 1; /**< An unexpected acknowledge control symbol was 1446 received. 1447 Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1448 uint32_t lnk_tout : 1; /**< An acknowledge or link-response control symbol is 1449 not received within the specified timeout interval 1450 Partial Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1451#else 1452 uint32_t lnk_tout : 1; 1453 uint32_t uns_ack : 1; 1454 uint32_t del_err : 1; 1455 uint32_t f_toggle : 1; 1456 uint32_t proterr : 1; 1457 uint32_t bad_ack : 1; 1458 uint32_t reserved_6_16 : 11; 1459 uint32_t size : 1; 1460 uint32_t pkt_crc : 1; 1461 uint32_t out_ack : 1; 1462 uint32_t nack : 1; 1463 uint32_t uns_id : 1; 1464 uint32_t ctl_crc : 1; 1465 uint32_t reserved_23_31 : 9; 1466#endif 1467 } cn63xxp1; 1468}; 1469typedef union cvmx_sriomaintx_erb_err_det cvmx_sriomaintx_erb_err_det_t; 1470 1471/** 1472 * cvmx_sriomaint#_erb_err_rate 1473 * 1474 * SRIOMAINT_ERB_ERR_RATE = SRIO Error Rate 1475 * 1476 * Error Rate 1477 * 1478 * Notes: 1479 * The Error Rate register is used with the Error Rate Threshold register to monitor and control the 1480 * reporting of transmission errors. 1481 * 1482 * Clk_Rst: SRIOMAINT(0..1)_ERB_ERR_RATE hclk hrst_n 1483 */ 1484union cvmx_sriomaintx_erb_err_rate 1485{ 1486 uint32_t u32; 1487 struct cvmx_sriomaintx_erb_err_rate_s 1488 { 1489#if __BYTE_ORDER == __BIG_ENDIAN 1490 uint32_t err_bias : 8; /**< These bits provide the error rate bias value. 1491 0x00 - do not decrement the error rate counter 1492 0x01 - decrement every 1ms (+/-34%) 1493 0x02 - decrement every 10ms (+/-34%) 1494 0x04 - decrement every 100ms (+/-34%) 1495 0x08 - decrement every 1s (+/-34%) 1496 0x10 - decrement every 10s (+/-34%) 1497 0x20 - decrement every 100s (+/-34%) 1498 0x40 - decrement every 1000s (+/-34%) 1499 0x80 - decrement every 10000s (+/-34%) 1500 All other values are reserved */ 1501 uint32_t reserved_18_23 : 6; 1502 uint32_t rate_lim : 2; /**< These bits limit the incrementing of the error 1503 rate counter above the failed threshold trigger. 1504 00 - only count 2 errors above 1505 01 - only count 4 errors above 1506 10 - only count 16 error above 1507 11 - do not limit incrementing the error rate ct */ 1508 uint32_t pk_rate : 8; /**< Peak Value attainted by the error rate counter */ 1509 uint32_t rate_cnt : 8; /**< These bits maintain a count of the number of 1510 transmission errors that have been detected by the 1511 port, decremented by the Error Rate Bias 1512 mechanism, to create an indication of the link 1513 error rate. */ 1514#else 1515 uint32_t rate_cnt : 8; 1516 uint32_t pk_rate : 8; 1517 uint32_t rate_lim : 2; 1518 uint32_t reserved_18_23 : 6; 1519 uint32_t err_bias : 8; 1520#endif 1521 } s; 1522 struct cvmx_sriomaintx_erb_err_rate_s cn63xx; 1523 struct cvmx_sriomaintx_erb_err_rate_s cn63xxp1; 1524}; 1525typedef union cvmx_sriomaintx_erb_err_rate cvmx_sriomaintx_erb_err_rate_t; 1526 1527/** 1528 * cvmx_sriomaint#_erb_err_rate_en 1529 * 1530 * SRIOMAINT_ERB_ERR_RATE_EN = SRIO Error Rate Enable 1531 * 1532 * Error Rate Enable 1533 * 1534 * Notes: 1535 * This register contains the bits that control when an error condition is allowed to increment the 1536 * error rate counter in the Error Rate Threshold Register and lock the Error Capture registers. 1537 * 1538 * Clk_Rst: SRIOMAINT(0..1)_ERB_ERR_RATE_EN hclk hrst_n 1539 */ 1540union cvmx_sriomaintx_erb_err_rate_en 1541{ 1542 uint32_t u32; 1543 struct cvmx_sriomaintx_erb_err_rate_en_s 1544 { 1545#if __BYTE_ORDER == __BIG_ENDIAN 1546 uint32_t imp_err : 1; /**< Enable Implementation Specific Error (Pass 2). */ 1547 uint32_t reserved_23_30 : 8; 1548 uint32_t ctl_crc : 1; /**< Enable error rate counting of control symbols with 1549 bad CRC values */ 1550 uint32_t uns_id : 1; /**< Enable error rate counting of acknowledge control 1551 symbol with unexpected ackIDs 1552 (packet-accepted or packet_retry) */ 1553 uint32_t nack : 1; /**< Enable error rate counting of packet-not-accepted 1554 acknowledge control symbols. */ 1555 uint32_t out_ack : 1; /**< Enable error rate counting of received packet with 1556 unexpected ackID value */ 1557 uint32_t pkt_crc : 1; /**< Enable error rate counting of received a packet 1558 with a bad CRC value */ 1559 uint32_t size : 1; /**< Enable error rate counting of received packet 1560 which exceeds the maximum size of 276 bytes. */ 1561 uint32_t inv_char : 1; /**< Enable error rate counting of received illegal 1562 illegal, 8B/10B error or undefined codegroup 1563 within a packet. (Pass 2) */ 1564 uint32_t inv_data : 1; /**< Enable error rate counting of received data 1565 codegroup or 8B/10B error within IDLE sequence. 1566 (Pass 2) */ 1567 uint32_t reserved_6_14 : 9; 1568 uint32_t bad_ack : 1; /**< Enable error rate counting of link_responses with 1569 an ackID that is not outstanding. */ 1570 uint32_t proterr : 1; /**< Enable error rate counting of unexpected packet or 1571 control symbols received. */ 1572 uint32_t f_toggle : 1; /**< Reserved. */ 1573 uint32_t del_err : 1; /**< Enable error rate counting of illegal or undefined 1574 codegroups (either INV_DATA or INV_CHAR). (Pass 2) */ 1575 uint32_t uns_ack : 1; /**< Enable error rate counting of unexpected 1576 acknowledge control symbols received. */ 1577 uint32_t lnk_tout : 1; /**< Enable error rate counting of acknowledge or 1578 link-response control symbols not received within 1579 the specified timeout interval */ 1580#else 1581 uint32_t lnk_tout : 1; 1582 uint32_t uns_ack : 1; 1583 uint32_t del_err : 1; 1584 uint32_t f_toggle : 1; 1585 uint32_t proterr : 1; 1586 uint32_t bad_ack : 1; 1587 uint32_t reserved_6_14 : 9; 1588 uint32_t inv_data : 1; 1589 uint32_t inv_char : 1; 1590 uint32_t size : 1; 1591 uint32_t pkt_crc : 1; 1592 uint32_t out_ack : 1; 1593 uint32_t nack : 1; 1594 uint32_t uns_id : 1; 1595 uint32_t ctl_crc : 1; 1596 uint32_t reserved_23_30 : 8; 1597 uint32_t imp_err : 1; 1598#endif 1599 } s; 1600 struct cvmx_sriomaintx_erb_err_rate_en_s cn63xx; 1601 struct cvmx_sriomaintx_erb_err_rate_en_cn63xxp1 1602 { 1603#if __BYTE_ORDER == __BIG_ENDIAN 1604 uint32_t reserved_23_31 : 9; 1605 uint32_t ctl_crc : 1; /**< Enable error rate counting of control symbols with 1606 bad CRC values */ 1607 uint32_t uns_id : 1; /**< Enable error rate counting of acknowledge control 1608 symbol with unexpected ackIDs 1609 (packet-accepted or packet_retry) */ 1610 uint32_t nack : 1; /**< Enable error rate counting of packet-not-accepted 1611 acknowledge control symbols. */ 1612 uint32_t out_ack : 1; /**< Enable error rate counting of received packet with 1613 unexpected ackID value */ 1614 uint32_t pkt_crc : 1; /**< Enable error rate counting of received a packet 1615 with a bad CRC value */ 1616 uint32_t size : 1; /**< Enable error rate counting of received packet 1617 which exceeds the maximum size of 276 bytes. */ 1618 uint32_t reserved_6_16 : 11; 1619 uint32_t bad_ack : 1; /**< Enable error rate counting of link_responses with 1620 an ackID that is not outstanding. */ 1621 uint32_t proterr : 1; /**< Enable error rate counting of unexpected packet or 1622 control symbols received. */ 1623 uint32_t f_toggle : 1; /**< Reserved. */ 1624 uint32_t del_err : 1; /**< Enable error rate counting of illegal or undefined 1625 codegroups (either INV_DATA or INV_CHAR). (Pass 2) */ 1626 uint32_t uns_ack : 1; /**< Enable error rate counting of unexpected 1627 acknowledge control symbols received. */ 1628 uint32_t lnk_tout : 1; /**< Enable error rate counting of acknowledge or 1629 link-response control symbols not received within 1630 the specified timeout interval */ 1631#else 1632 uint32_t lnk_tout : 1; 1633 uint32_t uns_ack : 1; 1634 uint32_t del_err : 1; 1635 uint32_t f_toggle : 1; 1636 uint32_t proterr : 1; 1637 uint32_t bad_ack : 1; 1638 uint32_t reserved_6_16 : 11; 1639 uint32_t size : 1; 1640 uint32_t pkt_crc : 1; 1641 uint32_t out_ack : 1; 1642 uint32_t nack : 1; 1643 uint32_t uns_id : 1; 1644 uint32_t ctl_crc : 1; 1645 uint32_t reserved_23_31 : 9; 1646#endif 1647 } cn63xxp1; 1648}; 1649typedef union cvmx_sriomaintx_erb_err_rate_en cvmx_sriomaintx_erb_err_rate_en_t; 1650 1651/** 1652 * cvmx_sriomaint#_erb_err_rate_thr 1653 * 1654 * SRIOMAINT_ERB_ERR_RATE_THR = SRIO Error Rate Threshold 1655 * 1656 * Error Rate Threshold 1657 * 1658 * Notes: 1659 * The Error Rate Threshold register is used to control the reporting of errors to the link status. 1660 * Typically the Degraded Threshold is less than the Fail Threshold. 1661 * 1662 * Clk_Rst: SRIOMAINT(0..1)_ERB_ERR_RATE_THR hclk hrst_n 1663 */ 1664union cvmx_sriomaintx_erb_err_rate_thr 1665{ 1666 uint32_t u32; 1667 struct cvmx_sriomaintx_erb_err_rate_thr_s 1668 { 1669#if __BYTE_ORDER == __BIG_ENDIAN 1670 uint32_t fail_th : 8; /**< These bits provide the threshold value for 1671 reporting an error condition due to a possibly 1672 broken link. 1673 0x00 - Disable the Error Rate Failed Threshold 1674 Trigger 1675 0x01 - Set the error reporting threshold to 1 1676 0x02 - Set the error reporting threshold to 2 1677 - ... 1678 0xFF - Set the error reporting threshold to 255 */ 1679 uint32_t dgrad_th : 8; /**< These bits provide the threshold value for 1680 reporting an error condition due to a possibly 1681 degrading link. 1682 0x00 - Disable the Degrade Rate Failed Threshold 1683 Trigger 1684 0x01 - Set the error reporting threshold to 1 1685 0x02 - Set the error reporting threshold to 2 1686 - ... 1687 0xFF - Set the error reporting threshold to 255 */ 1688 uint32_t reserved_0_15 : 16; 1689#else 1690 uint32_t reserved_0_15 : 16; 1691 uint32_t dgrad_th : 8; 1692 uint32_t fail_th : 8; 1693#endif 1694 } s; 1695 struct cvmx_sriomaintx_erb_err_rate_thr_s cn63xx; 1696 struct cvmx_sriomaintx_erb_err_rate_thr_s cn63xxp1; 1697}; 1698typedef union cvmx_sriomaintx_erb_err_rate_thr cvmx_sriomaintx_erb_err_rate_thr_t; 1699 1700/** 1701 * cvmx_sriomaint#_erb_hdr 1702 * 1703 * SRIOMAINT_ERB_HDR = SRIO Error Reporting Block Header 1704 * 1705 * Error Reporting Block Header 1706 * 1707 * Notes: 1708 * The error management extensions block header register contains the EF_PTR to the next EF_BLK and 1709 * the EF_ID that identifies this as the error management extensions block header. In this 1710 * implementation this is the last block and therefore the EF_PTR is a NULL pointer. 1711 * 1712 * Clk_Rst: SRIOMAINT(0..1)_ERB_HDR hclk hrst_n 1713 */ 1714union cvmx_sriomaintx_erb_hdr 1715{ 1716 uint32_t u32; 1717 struct cvmx_sriomaintx_erb_hdr_s 1718 { 1719#if __BYTE_ORDER == __BIG_ENDIAN 1720 uint32_t ef_ptr : 16; /**< Pointer to the next block in the extended features 1721 data structure. */ 1722 uint32_t ef_id : 16; /**< Single Port ID */ 1723#else 1724 uint32_t ef_id : 16; 1725 uint32_t ef_ptr : 16; 1726#endif 1727 } s; 1728 struct cvmx_sriomaintx_erb_hdr_s cn63xx; 1729 struct cvmx_sriomaintx_erb_hdr_s cn63xxp1; 1730}; 1731typedef union cvmx_sriomaintx_erb_hdr cvmx_sriomaintx_erb_hdr_t; 1732 1733/** 1734 * cvmx_sriomaint#_erb_lt_addr_capt_h 1735 * 1736 * SRIOMAINT_ERB_LT_ADDR_CAPT_H = SRIO Logical/Transport Layer High Address Capture 1737 * 1738 * Logical/Transport Layer High Address Capture 1739 * 1740 * Notes: 1741 * This register contains error information. It is locked when a Logical/Transport error is detected 1742 * and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero. This register should be 1743 * written only when error detection is disabled. This register is only required for end point 1744 * transactions of 50 or 66 bits. 1745 * 1746 * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_ADDR_CAPT_H hclk hrst_n 1747 */ 1748union cvmx_sriomaintx_erb_lt_addr_capt_h 1749{ 1750 uint32_t u32; 1751 struct cvmx_sriomaintx_erb_lt_addr_capt_h_s 1752 { 1753#if __BYTE_ORDER == __BIG_ENDIAN 1754 uint32_t addr : 32; /**< Most significant 32 bits of the address associated 1755 with the error. Information supplied for requests 1756 and responses if available. */ 1757#else 1758 uint32_t addr : 32; 1759#endif 1760 } s; 1761 struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn63xx; 1762 struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn63xxp1; 1763}; 1764typedef union cvmx_sriomaintx_erb_lt_addr_capt_h cvmx_sriomaintx_erb_lt_addr_capt_h_t; 1765 1766/** 1767 * cvmx_sriomaint#_erb_lt_addr_capt_l 1768 * 1769 * SRIOMAINT_ERB_LT_ADDR_CAPT_L = SRIO Logical/Transport Layer Low Address Capture 1770 * 1771 * Logical/Transport Layer Low Address Capture 1772 * 1773 * Notes: 1774 * This register contains error information. It is locked when a Logical/Transport error is detected 1775 * and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero. This register should be 1776 * written only when error detection is disabled. 1777 * 1778 * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_ADDR_CAPT_L hclk hrst_n 1779 */ 1780union cvmx_sriomaintx_erb_lt_addr_capt_l 1781{ 1782 uint32_t u32; 1783 struct cvmx_sriomaintx_erb_lt_addr_capt_l_s 1784 { 1785#if __BYTE_ORDER == __BIG_ENDIAN 1786 uint32_t addr : 29; /**< Least significant 29 bits of the address 1787 associated with the error. Bits 31:24 specify the 1788 request HOP count for Maintenance Operations. 1789 Information supplied for requests and responses if 1790 available. */ 1791 uint32_t reserved_2_2 : 1; 1792 uint32_t xaddr : 2; /**< Extended address bits of the address associated 1793 with the error. Information supplied for requests 1794 and responses if available. */ 1795#else 1796 uint32_t xaddr : 2; 1797 uint32_t reserved_2_2 : 1; 1798 uint32_t addr : 29; 1799#endif 1800 } s; 1801 struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn63xx; 1802 struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn63xxp1; 1803}; 1804typedef union cvmx_sriomaintx_erb_lt_addr_capt_l cvmx_sriomaintx_erb_lt_addr_capt_l_t; 1805 1806/** 1807 * cvmx_sriomaint#_erb_lt_ctrl_capt 1808 * 1809 * SRIOMAINT_ERB_LT_CTRL_CAPT = SRIO Logical/Transport Layer Control Capture 1810 * 1811 * Logical/Transport Layer Control Capture 1812 * 1813 * Notes: 1814 * This register contains error information. It is locked when a Logical/Transport error is detected 1815 * and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero. This register should be 1816 * written only when error detection is disabled. 1817 * 1818 * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_CTRL_CAPT hclk hrst_n 1819 */ 1820union cvmx_sriomaintx_erb_lt_ctrl_capt 1821{ 1822 uint32_t u32; 1823 struct cvmx_sriomaintx_erb_lt_ctrl_capt_s 1824 { 1825#if __BYTE_ORDER == __BIG_ENDIAN 1826 uint32_t ftype : 4; /**< Format Type associated with the error */ 1827 uint32_t ttype : 4; /**< Transaction Type associated with the error 1828 (For Messages) 1829 Message Length */ 1830 uint32_t extra : 8; /**< Additional Information 1831 (For Messages) 1832 - 23:22 Letter 1833 - 21:20 Mbox 1834 - 19:16 Msgseg/xmbox 1835 Information for the last message request sent 1836 for the mailbox that had an error 1837 (For Responses) 1838 - 23:20 Response Request FTYPE 1839 - 19:16 Response Request TTYPE 1840 (For all other types) 1841 Reserved. */ 1842 uint32_t status : 4; /**< Response Status. 1843 (For all other Requests) 1844 Reserved. */ 1845 uint32_t size : 4; /**< Size associated with the transaction. */ 1846 uint32_t tt : 1; /**< Transfer Type 0=ID8, 1=ID16. */ 1847 uint32_t wdptr : 1; /**< Word Pointer associated with the error. */ 1848 uint32_t reserved_5_5 : 1; 1849 uint32_t capt_idx : 5; /**< Capture Index. 31 - Bit set in 1850 SRIOMAINT(0..1)_ERB_LT_ERR_DET. */ 1851#else 1852 uint32_t capt_idx : 5; 1853 uint32_t reserved_5_5 : 1; 1854 uint32_t wdptr : 1; 1855 uint32_t tt : 1; 1856 uint32_t size : 4; 1857 uint32_t status : 4; 1858 uint32_t extra : 8; 1859 uint32_t ttype : 4; 1860 uint32_t ftype : 4; 1861#endif 1862 } s; 1863 struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn63xx; 1864 struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn63xxp1; 1865}; 1866typedef union cvmx_sriomaintx_erb_lt_ctrl_capt cvmx_sriomaintx_erb_lt_ctrl_capt_t; 1867 1868/** 1869 * cvmx_sriomaint#_erb_lt_dev_id 1870 * 1871 * SRIOMAINT_ERB_LT_DEV_ID = SRIO Port-write Target deviceID 1872 * 1873 * Port-write Target deviceID 1874 * 1875 * Notes: 1876 * This SRIO interface does not support generating Port-Writes based on ERB Errors. This register is 1877 * currently unused and should be treated as reserved. 1878 * 1879 * Clk_Rst: SRIOMAINT_ERB_LT_DEV_ID hclk hrst_n 1880 */ 1881union cvmx_sriomaintx_erb_lt_dev_id 1882{ 1883 uint32_t u32; 1884 struct cvmx_sriomaintx_erb_lt_dev_id_s 1885 { 1886#if __BYTE_ORDER == __BIG_ENDIAN 1887 uint32_t id16 : 8; /**< This is the most significant byte of the 1888 port-write destination deviceID (large transport 1889 systems only) 1890 destination ID used for Port Write errors */ 1891 uint32_t id8 : 8; /**< This is the port-write destination deviceID */ 1892 uint32_t tt : 1; /**< Transport Type used for Port Write 1893 0 = Small Transport, ID8 Only 1894 1 = Large Transport, ID16 and ID8 */ 1895 uint32_t reserved_0_14 : 15; 1896#else 1897 uint32_t reserved_0_14 : 15; 1898 uint32_t tt : 1; 1899 uint32_t id8 : 8; 1900 uint32_t id16 : 8; 1901#endif 1902 } s; 1903 struct cvmx_sriomaintx_erb_lt_dev_id_s cn63xx; 1904 struct cvmx_sriomaintx_erb_lt_dev_id_s cn63xxp1; 1905}; 1906typedef union cvmx_sriomaintx_erb_lt_dev_id cvmx_sriomaintx_erb_lt_dev_id_t; 1907 1908/** 1909 * cvmx_sriomaint#_erb_lt_dev_id_capt 1910 * 1911 * SRIOMAINT_ERB_LT_DEV_ID_CAPT = SRIO Logical/Transport Layer Device ID Capture 1912 * 1913 * Logical/Transport Layer Device ID Capture 1914 * 1915 * Notes: 1916 * This register contains error information. It is locked when a Logical/Transport error is detected 1917 * and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero. This register should be 1918 * written only when error detection is disabled. 1919 * 1920 * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_DEV_ID_CAPT hclk hrst_n 1921 */ 1922union cvmx_sriomaintx_erb_lt_dev_id_capt 1923{ 1924 uint32_t u32; 1925 struct cvmx_sriomaintx_erb_lt_dev_id_capt_s 1926 { 1927#if __BYTE_ORDER == __BIG_ENDIAN 1928 uint32_t dst_id16 : 8; /**< Most significant byte of the large transport 1929 destination ID associated with the error */ 1930 uint32_t dst_id8 : 8; /**< Least significant byte of the large transport 1931 destination ID or the 8-bit small transport 1932 destination ID associated with the error */ 1933 uint32_t src_id16 : 8; /**< Most significant byte of the large transport 1934 source ID associated with the error */ 1935 uint32_t src_id8 : 8; /**< Least significant byte of the large transport 1936 source ID or the 8-bit small transport source ID 1937 associated with the error */ 1938#else 1939 uint32_t src_id8 : 8; 1940 uint32_t src_id16 : 8; 1941 uint32_t dst_id8 : 8; 1942 uint32_t dst_id16 : 8; 1943#endif 1944 } s; 1945 struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn63xx; 1946 struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn63xxp1; 1947}; 1948typedef union cvmx_sriomaintx_erb_lt_dev_id_capt cvmx_sriomaintx_erb_lt_dev_id_capt_t; 1949 1950/** 1951 * cvmx_sriomaint#_erb_lt_err_det 1952 * 1953 * SRIOMAINT_ERB_LT_ERR_DET = SRIO Logical/Transport Layer Error Detect 1954 * 1955 * SRIO Logical/Transport Layer Error Detect 1956 * 1957 * Notes: 1958 * This register indicates the error that was detected by the Logical or Transport logic layer. 1959 * Once a bit is set in this CSR, HW will lock the register until SW writes a zero to clear all the 1960 * fields. The HW sets SRIO_INT_REG[LOG_ERB] every time it sets one of the bits. 1961 * To handle the interrupt, the following procedure may be best: 1962 * (1) clear SRIO_INT_REG[LOG_ERB], 1963 * (2) read this CSR, corresponding SRIOMAINT*_ERB_LT_ADDR_CAPT_H, SRIOMAINT*_ERB_LT_ADDR_CAPT_L, 1964 * SRIOMAINT*_ERB_LT_DEV_ID_CAPT, and SRIOMAINT*_ERB_LT_CTRL_CAPT 1965 * (3) Write this CSR to 0. 1966 * 1967 * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_ERR_DET hclk hrst_n 1968 */ 1969union cvmx_sriomaintx_erb_lt_err_det 1970{ 1971 uint32_t u32; 1972 struct cvmx_sriomaintx_erb_lt_err_det_s 1973 { 1974#if __BYTE_ORDER == __BIG_ENDIAN 1975 uint32_t io_err : 1; /**< Received a response of ERROR for an IO Logical 1976 Layer Request. This includes all Maintenance and 1977 Memory Responses not destined for the RX Soft 1978 Packet FIFO. When SRIO receives an ERROR response 1979 for a read, the issuing core or DPI DMA engine 1980 receives result bytes with all bits set. In the 1981 case of writes with response, this bit is the only 1982 indication of failure. */ 1983 uint32_t msg_err : 1; /**< Received a response of ERROR for an outgoing 1984 message segment. This bit is the only direct 1985 indication of a MSG_ERR. When a MSG_ERR occurs, 1986 SRIO drops the message segment and will not set 1987 SRIO*_INT_REG[OMSG*] after the message 1988 "transfer". NOTE: SRIO can continue to send or 1989 retry other segments from the same message after 1990 a MSG_ERR. */ 1991 uint32_t gsm_err : 1; /**< Received a response of ERROR for an GSM Logical 1992 Request. SRIO hardware never sets this bit. GSM 1993 operations are not supported (outside of the Soft 1994 Packet FIFO). */ 1995 uint32_t msg_fmt : 1; /**< Received an incoming Message Segment with a 1996 formating error. A MSG_FMT error occurs when SRIO 1997 receives a message segment with a reserved SSIZE, 1998 or a illegal data payload size, or a MSGSEG greater 1999 than MSGLEN, or a MSGSEG that is the duplicate of 2000 one already received by an inflight message. 2001 When a non-duplicate MSG_FMT error occurs, SRIO 2002 drops the segment and sends an ERROR response. 2003 When a duplicate MSG_FMT error occurs, SRIO 2004 (internally) terminates the currently-inflight 2005 message with an error and processes the duplicate, 2006 which may result in a new message being generated 2007 internally for the duplicate. */ 2008 uint32_t ill_tran : 1; /**< Received illegal fields in the request/response 2009 packet for a supported transaction or any packet 2010 with a reserved transaction type. When an ILL_TRAN 2011 error occurs, SRIO ignores the packet. ILL_TRAN 2012 errors are 2nd priority after ILL_TGT and may mask 2013 other problems. Packets with ILL_TRAN errors cannot 2014 enter the RX Soft Packet FIFO. 2015 There are two things that can set ILL_TRAN: 2016 (1) SRIO received a packet with a tt value is not 2017 0 or 1, or (2) SRIO received a response to an 2018 outstanding message segment whose status was not 2019 DONE, RETRY, or ERROR. */ 2020 uint32_t ill_tgt : 1; /**< Received a packet that contained a destination ID 2021 other than SRIOMAINT*_PRI_DEV_ID or 2022 SRIOMAINT*_SEC_DEV_ID. When an ILL_TGT error 2023 occurs, SRIO drops the packet. ILL_TGT errors are 2024 highest priority, so may mask other problems. 2025 Packets with ILL_TGT errors cannot enter the RX 2026 soft packet fifo. */ 2027 uint32_t msg_tout : 1; /**< An expected incoming message request has not been 2028 received within the time-out interval specified in 2029 SRIOMAINT(0..1)_PORT_RT_CTL. When a MSG_TOUT occurs, 2030 SRIO (internally) terminates the inflight message 2031 with an error. */ 2032 uint32_t pkt_tout : 1; /**< A required response has not been received to an 2033 outgoing memory, maintenance or message request 2034 before the time-out interval specified in 2035 SRIOMAINT(0..1)_PORT_RT_CTL. When an IO or maintenance 2036 read request operation has a PKT_TOUT, the issuing 2037 core load or DPI DMA engine receive all ones for 2038 the result. When an IO NWRITE_R has a PKT_TOUT, 2039 this bit is the only indication of failure. When a 2040 message request operation has a PKT_TOUT, SRIO 2041 discards the the outgoing message segment, and 2042 this bit is the only direct indication of failure. 2043 NOTE: SRIO may continue to send or retry other 2044 segments from the same message. When one or more of 2045 the segments in an outgoing message have a 2046 PKT_TOUT, SRIO will not set SRIO*_INT_REG[OMSG*] 2047 after the message "transfer". */ 2048 uint32_t uns_resp : 1; /**< An unsolicited/unexpected memory, maintenance or 2049 message response packet was received that was not 2050 destined for the RX Soft Packet FIFO. When this 2051 condition is detected, the packet is dropped. */ 2052 uint32_t uns_tran : 1; /**< A transaction is received that is not supported. 2053 SRIO HW will never set this bit - SRIO routes all 2054 unsupported transactions to the RX soft packet 2055 FIFO. */ 2056 uint32_t reserved_1_21 : 21; 2057 uint32_t resp_sz : 1; /**< Received an incoming Memory or Maintenance 2058 Read response packet with a DONE status and less 2059 data then expected. This condition causes the 2060 Read to be completed and an error response to be 2061 returned with all the data bits set to the issuing 2062 Core or DMA Engine. */ 2063#else 2064 uint32_t resp_sz : 1; 2065 uint32_t reserved_1_21 : 21; 2066 uint32_t uns_tran : 1; 2067 uint32_t uns_resp : 1; 2068 uint32_t pkt_tout : 1; 2069 uint32_t msg_tout : 1; 2070 uint32_t ill_tgt : 1; 2071 uint32_t ill_tran : 1; 2072 uint32_t msg_fmt : 1; 2073 uint32_t gsm_err : 1; 2074 uint32_t msg_err : 1; 2075 uint32_t io_err : 1; 2076#endif 2077 } s; 2078 struct cvmx_sriomaintx_erb_lt_err_det_s cn63xx; 2079 struct cvmx_sriomaintx_erb_lt_err_det_s cn63xxp1; 2080}; 2081typedef union cvmx_sriomaintx_erb_lt_err_det cvmx_sriomaintx_erb_lt_err_det_t; 2082 2083/** 2084 * cvmx_sriomaint#_erb_lt_err_en 2085 * 2086 * SRIOMAINT_ERB_LT_ERR_EN = SRIO Logical/Transport Layer Error Enable 2087 * 2088 * SRIO Logical/Transport Layer Error Enable 2089 * 2090 * Notes: 2091 * This register contains the bits that control if an error condition locks the Logical/Transport 2092 * Layer Error Detect and Capture registers and is reported to the system host. 2093 * 2094 * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_ERR_EN hclk hrst_n 2095 */ 2096union cvmx_sriomaintx_erb_lt_err_en 2097{ 2098 uint32_t u32; 2099 struct cvmx_sriomaintx_erb_lt_err_en_s 2100 { 2101#if __BYTE_ORDER == __BIG_ENDIAN 2102 uint32_t io_err : 1; /**< Enable reporting of an IO error response. Save and 2103 lock original request transaction information in 2104 all Logical/Transport Layer Capture CSRs. */ 2105 uint32_t msg_err : 1; /**< Enable reporting of a Message error response. Save 2106 and lock original request transaction information 2107 in all Logical/Transport Layer Capture CSRs. */ 2108 uint32_t gsm_err : 1; /**< Enable reporting of a GSM error response. Save and 2109 lock original request transaction capture 2110 information in all Logical/Transport Layer Capture 2111 CSRs. */ 2112 uint32_t msg_fmt : 1; /**< Enable reporting of a message format error. Save 2113 and lock transaction capture information in 2114 Logical/Transport Layer Device ID and Control 2115 Capture CSRs. */ 2116 uint32_t ill_tran : 1; /**< Enable reporting of an illegal transaction decode 2117 error Save and lock transaction capture 2118 information in Logical/Transport Layer Device ID 2119 and Control Capture CSRs. */ 2120 uint32_t ill_tgt : 1; /**< Enable reporting of an illegal transaction target 2121 error. Save and lock transaction capture 2122 information in Logical/Transport Layer Device ID 2123 and Control Capture CSRs. */ 2124 uint32_t msg_tout : 1; /**< Enable reporting of a Message Request time-out 2125 error. Save and lock transaction capture 2126 information in Logical/Transport Layer Device ID 2127 and Control Capture CSRs for the last Message 2128 request segment packet received. */ 2129 uint32_t pkt_tout : 1; /**< Enable reporting of a packet response time-out 2130 error. Save and lock original request address in 2131 Logical/Transport Layer Address Capture CSRs. 2132 Save and lock original request Destination ID in 2133 Logical/Transport Layer Device ID Capture CSR. */ 2134 uint32_t uns_resp : 1; /**< Enable reporting of an unsolicited response error. 2135 Save and lock transaction capture information in 2136 Logical/Transport Layer Device ID and Control 2137 Capture CSRs. */ 2138 uint32_t uns_tran : 1; /**< Enable reporting of an unsupported transaction 2139 error. Save and lock transaction capture 2140 information in Logical/Transport Layer Device ID 2141 and Control Capture CSRs. */ 2142 uint32_t reserved_1_21 : 21; 2143 uint32_t resp_sz : 1; /**< Enable reporting of an incoming response with 2144 unexpected data size */ 2145#else 2146 uint32_t resp_sz : 1; 2147 uint32_t reserved_1_21 : 21; 2148 uint32_t uns_tran : 1; 2149 uint32_t uns_resp : 1; 2150 uint32_t pkt_tout : 1; 2151 uint32_t msg_tout : 1; 2152 uint32_t ill_tgt : 1; 2153 uint32_t ill_tran : 1; 2154 uint32_t msg_fmt : 1; 2155 uint32_t gsm_err : 1; 2156 uint32_t msg_err : 1; 2157 uint32_t io_err : 1; 2158#endif 2159 } s; 2160 struct cvmx_sriomaintx_erb_lt_err_en_s cn63xx; 2161 struct cvmx_sriomaintx_erb_lt_err_en_s cn63xxp1; 2162}; 2163typedef union cvmx_sriomaintx_erb_lt_err_en cvmx_sriomaintx_erb_lt_err_en_t; 2164 2165/** 2166 * cvmx_sriomaint#_erb_pack_capt_1 2167 * 2168 * SRIOMAINT_ERB_PACK_CAPT_1 = SRIO Packet Capture 1 2169 * 2170 * Packet Capture 1 2171 * 2172 * Notes: 2173 * Error capture register 1 contains either long symbol capture information or bytes 4 through 7 of 2174 * the packet header. 2175 * The HW will not update this register (i.e. this register is locked) while 2176 * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. 2177 * 2178 * Clk_Rst: SRIOMAINT(0..1)_ERB_PACK_CAPT_1 hclk hrst_n 2179 */ 2180union cvmx_sriomaintx_erb_pack_capt_1 2181{ 2182 uint32_t u32; 2183 struct cvmx_sriomaintx_erb_pack_capt_1_s 2184 { 2185#if __BYTE_ORDER == __BIG_ENDIAN 2186 uint32_t capture : 32; /**< Bytes 4 thru 7 of the packet header. */ 2187#else 2188 uint32_t capture : 32; 2189#endif 2190 } s; 2191 struct cvmx_sriomaintx_erb_pack_capt_1_s cn63xx; 2192 struct cvmx_sriomaintx_erb_pack_capt_1_s cn63xxp1; 2193}; 2194typedef union cvmx_sriomaintx_erb_pack_capt_1 cvmx_sriomaintx_erb_pack_capt_1_t; 2195 2196/** 2197 * cvmx_sriomaint#_erb_pack_capt_2 2198 * 2199 * SRIOMAINT_ERB_PACK_CAPT_2 = SRIO Packet Capture 2 2200 * 2201 * Packet Capture 2 2202 * 2203 * Notes: 2204 * Error capture register 2 contains bytes 8 through 11 of the packet header. 2205 * The HW will not update this register (i.e. this register is locked) while 2206 * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. 2207 * 2208 * Clk_Rst: SRIOMAINT(0..1)_ERB_PACK_CAPT_2 hclk hrst_n 2209 */ 2210union cvmx_sriomaintx_erb_pack_capt_2 2211{ 2212 uint32_t u32; 2213 struct cvmx_sriomaintx_erb_pack_capt_2_s 2214 { 2215#if __BYTE_ORDER == __BIG_ENDIAN 2216 uint32_t capture : 32; /**< Bytes 8 thru 11 of the packet header. */ 2217#else 2218 uint32_t capture : 32; 2219#endif 2220 } s; 2221 struct cvmx_sriomaintx_erb_pack_capt_2_s cn63xx; 2222 struct cvmx_sriomaintx_erb_pack_capt_2_s cn63xxp1; 2223}; 2224typedef union cvmx_sriomaintx_erb_pack_capt_2 cvmx_sriomaintx_erb_pack_capt_2_t; 2225 2226/** 2227 * cvmx_sriomaint#_erb_pack_capt_3 2228 * 2229 * SRIOMAINT_ERB_PACK_CAPT_3 = SRIO Packet Capture 3 2230 * 2231 * Packet Capture 3 2232 * 2233 * Notes: 2234 * Error capture register 3 contains bytes 12 through 15 of the packet header. 2235 * The HW will not update this register (i.e. this register is locked) while 2236 * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. 2237 * 2238 * Clk_Rst: SRIOMAINT(0..1)_ERB_PACK_CAPT_3 hclk hrst_n 2239 */ 2240union cvmx_sriomaintx_erb_pack_capt_3 2241{ 2242 uint32_t u32; 2243 struct cvmx_sriomaintx_erb_pack_capt_3_s 2244 { 2245#if __BYTE_ORDER == __BIG_ENDIAN 2246 uint32_t capture : 32; /**< Bytes 12 thru 15 of the packet header. */ 2247#else 2248 uint32_t capture : 32; 2249#endif 2250 } s; 2251 struct cvmx_sriomaintx_erb_pack_capt_3_s cn63xx; 2252 struct cvmx_sriomaintx_erb_pack_capt_3_s cn63xxp1; 2253}; 2254typedef union cvmx_sriomaintx_erb_pack_capt_3 cvmx_sriomaintx_erb_pack_capt_3_t; 2255 2256/** 2257 * cvmx_sriomaint#_erb_pack_sym_capt 2258 * 2259 * SRIOMAINT_ERB_PACK_SYM_CAPT = SRIO Packet/Control Symbol Capture 2260 * 2261 * Packet/Control Symbol Capture 2262 * 2263 * Notes: 2264 * This register contains either captured control symbol information or the first 4 bytes of captured 2265 * packet information. The Errors that generate Partial Control Symbols can be found in 2266 * SRIOMAINT*_ERB_ERR_DET. The HW will not update this register (i.e. this register is locked) while 2267 * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. 2268 * 2269 * Clk_Rst: SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT hclk hrst_n 2270 */ 2271union cvmx_sriomaintx_erb_pack_sym_capt 2272{ 2273 uint32_t u32; 2274 struct cvmx_sriomaintx_erb_pack_sym_capt_s 2275 { 2276#if __BYTE_ORDER == __BIG_ENDIAN 2277 uint32_t capture : 32; /**< Control Character and Control Symbol or Bytes 0 to 2278 3 of Packet Header 2279 The Control Symbol consists of 2280 - 31:24 - SC Character (0 in Partial Symbol) 2281 - 23:21 - Stype 0 2282 - 20:16 - Parameter 0 2283 - 15:11 - Parameter 1 2284 - 10: 8 - Stype 1 (0 in Partial Symbol) 2285 - 7: 5 - Command (0 in Partial Symbol) 2286 - 4: 0 - CRC5 (0 in Partial Symbol) */ 2287#else 2288 uint32_t capture : 32; 2289#endif 2290 } s; 2291 struct cvmx_sriomaintx_erb_pack_sym_capt_s cn63xx; 2292 struct cvmx_sriomaintx_erb_pack_sym_capt_s cn63xxp1; 2293}; 2294typedef union cvmx_sriomaintx_erb_pack_sym_capt cvmx_sriomaintx_erb_pack_sym_capt_t; 2295 2296/** 2297 * cvmx_sriomaint#_hb_dev_id_lock 2298 * 2299 * SRIOMAINT_HB_DEV_ID_LOCK = SRIO Host Device ID Lock 2300 * 2301 * The Host Base Device ID 2302 * 2303 * Notes: 2304 * This register contains the Device ID of the Host responsible for initializing this SRIO device. 2305 * The register contains a special write once function that captures the first HOSTID written to it 2306 * after reset. The function allows several potential hosts to write to this register and then read 2307 * it to see if they have responsibility for initialization. The register can be unlocked by 2308 * rewriting the current host value. This will reset the lock and restore the value to 0xFFFF. 2309 * 2310 * Clk_Rst: SRIOMAINT(0..1)_HB_DEV_ID_LOCK hclk hrst_n 2311 */ 2312union cvmx_sriomaintx_hb_dev_id_lock 2313{ 2314 uint32_t u32; 2315 struct cvmx_sriomaintx_hb_dev_id_lock_s 2316 { 2317#if __BYTE_ORDER == __BIG_ENDIAN 2318 uint32_t reserved_16_31 : 16; 2319 uint32_t hostid : 16; /**< Primary 16-bit Device ID */ 2320#else 2321 uint32_t hostid : 16; 2322 uint32_t reserved_16_31 : 16; 2323#endif 2324 } s; 2325 struct cvmx_sriomaintx_hb_dev_id_lock_s cn63xx; 2326 struct cvmx_sriomaintx_hb_dev_id_lock_s cn63xxp1; 2327}; 2328typedef union cvmx_sriomaintx_hb_dev_id_lock cvmx_sriomaintx_hb_dev_id_lock_t; 2329 2330/** 2331 * cvmx_sriomaint#_ir_buffer_config 2332 * 2333 * SRIOMAINT_IR_BUFFER_CONFIG = SRIO Buffer Configuration 2334 * 2335 * Buffer Configuration 2336 * 2337 * Notes: 2338 * This register controls the operation of the SRIO Core buffer mux logic. 2339 * 2340 * Clk_Rst: SRIOMAINT(0..1)_IR_BUFFER_CONFIG hclk hrst_n 2341 */ 2342union cvmx_sriomaintx_ir_buffer_config 2343{ 2344 uint32_t u32; 2345 struct cvmx_sriomaintx_ir_buffer_config_s 2346 { 2347#if __BYTE_ORDER == __BIG_ENDIAN 2348 uint32_t tx_wm0 : 4; /**< Transmitter Flow Control Priority 0 Threshold. 2349 Number of Receive Buffers available before packet 2350 can be scheduled for transmission. 2351 Maximum Value 8. 2352 Generally, TX_WM0 Must be > TX_WM1 to reserve 2353 buffers for priority 1-3 packets when transmitting 2354 in transmitter-controlled flow control mode. 2355 TX_WM0 is not used by the hardware when TX_FLOW=0 2356 or whenever transmitting in 2357 receiver-controlled flow-control mode. */ 2358 uint32_t tx_wm1 : 4; /**< Transmitter Flow Control Priority 1 Threshold. 2359 Number of Receive Buffers available before packet 2360 can be scheduled for transmission. 2361 Maximum Value 8. 2362 Generally, TX_WM1 Must be > TX_WM2 to reserve 2363 buffers for priority 2-3 packets when transmitting 2364 in transmitter-controlled flow control mode. 2365 TX_WM1 is not used by the hardware when TX_FLOW=0 2366 or whenever transmitting in 2367 receiver-controlled flow-control mode. */ 2368 uint32_t tx_wm2 : 4; /**< Transmitter Flow Control Priority 2 Threshold. 2369 Number of Receive Buffers available before packet 2370 can be scheduled for transmission. 2371 Maximum Value 8. 2372 Generally, TX_WM2 Must be > 0 to reserve a 2373 buffer for priority 3 packets when transmitting 2374 in transmitter-controlled flow control mode. 2375 TX_WM2 is not used by the hardware when TX_FLOW=0 2376 or whenever transmitting in 2377 receiver-controlled flow-control mode. */ 2378 uint32_t reserved_3_19 : 17; 2379 uint32_t tx_flow : 1; /**< Controls whether Transmitter Flow Control is 2380 permitted on this device. 2381 0 - Disabled 2382 1 - Permitted 2383 The reset value of this field is 2384 SRIO*_IP_FEATURE[TX_FLOW]. */ 2385 uint32_t tx_sync : 1; /**< Controls whether the synchronizers are enabled 2386 between the SRIO TXCLK and the Internal Clocks. 2387 0 - Synchronizers are enabled 2388 1 - Synchronizers are disabled */ 2389 uint32_t rx_sync : 1; /**< Controls whether the synchronizers are enabled 2390 between the SRIO RXCLK and the Internal Clocks. 2391 0 - Synchronizers are enabled 2392 1 - Synchronizers are disabled */ 2393#else 2394 uint32_t rx_sync : 1; 2395 uint32_t tx_sync : 1; 2396 uint32_t tx_flow : 1; 2397 uint32_t reserved_3_19 : 17; 2398 uint32_t tx_wm2 : 4; 2399 uint32_t tx_wm1 : 4; 2400 uint32_t tx_wm0 : 4; 2401#endif 2402 } s; 2403 struct cvmx_sriomaintx_ir_buffer_config_s cn63xx; 2404 struct cvmx_sriomaintx_ir_buffer_config_s cn63xxp1; 2405}; 2406typedef union cvmx_sriomaintx_ir_buffer_config cvmx_sriomaintx_ir_buffer_config_t; 2407 2408/** 2409 * cvmx_sriomaint#_ir_buffer_config2 2410 * 2411 * SRIOMAINT_IR_BUFFER_CONFIG2 = SRIO Buffer Configuration 2 (Pass 2) 2412 * 2413 * Buffer Configuration 2 2414 * 2415 * Notes: 2416 * This register controls the RX and TX Buffer availablility by priority. The typical values are 2417 * optimized for normal operation. Care must be taken when changing these values to avoid values 2418 * which can result in deadlocks. Disabling a priority is not recommended and can result in system 2419 * level failures. 2420 * 2421 * Clk_Rst: SRIOMAINT(0..1)_IR_BUFFER_CONFIG2 hclk hrst_n 2422 */ 2423union cvmx_sriomaintx_ir_buffer_config2 2424{ 2425 uint32_t u32; 2426 struct cvmx_sriomaintx_ir_buffer_config2_s 2427 { 2428#if __BYTE_ORDER == __BIG_ENDIAN 2429 uint32_t tx_wm3 : 4; /**< Number of buffers free before a priority 3 packet 2430 will be transmitted. A value of 9 will disable 2431 this priority. */ 2432 uint32_t tx_wm2 : 4; /**< Number of buffers free before a priority 2 packet 2433 will be transmitted. A value of 9 will disable 2434 this priority. */ 2435 uint32_t tx_wm1 : 4; /**< Number of buffers free before a priority 1 packet 2436 will be transmitted. A value of 9 will disable 2437 this priority. */ 2438 uint32_t tx_wm0 : 4; /**< Number of buffers free before a priority 0 packet 2439 will be transmitted. A value of 9 will disable 2440 this priority. */ 2441 uint32_t rx_wm3 : 4; /**< Number of buffers free before a priority 3 packet 2442 will be accepted. A value of 9 will disable this 2443 priority and always cause a physical layer RETRY. */ 2444 uint32_t rx_wm2 : 4; /**< Number of buffers free before a priority 2 packet 2445 will be accepted. A value of 9 will disable this 2446 priority and always cause a physical layer RETRY. */ 2447 uint32_t rx_wm1 : 4; /**< Number of buffers free before a priority 1 packet 2448 will be accepted. A value of 9 will disable this 2449 priority and always cause a physical layer RETRY. */ 2450 uint32_t rx_wm0 : 4; /**< Number of buffers free before a priority 0 packet 2451 will be accepted. A value of 9 will disable this 2452 priority and always cause a physical layer RETRY. */ 2453#else 2454 uint32_t rx_wm0 : 4; 2455 uint32_t rx_wm1 : 4; 2456 uint32_t rx_wm2 : 4; 2457 uint32_t rx_wm3 : 4; 2458 uint32_t tx_wm0 : 4; 2459 uint32_t tx_wm1 : 4; 2460 uint32_t tx_wm2 : 4; 2461 uint32_t tx_wm3 : 4; 2462#endif 2463 } s; 2464 struct cvmx_sriomaintx_ir_buffer_config2_s cn63xx; 2465}; 2466typedef union cvmx_sriomaintx_ir_buffer_config2 cvmx_sriomaintx_ir_buffer_config2_t; 2467 2468/** 2469 * cvmx_sriomaint#_ir_pd_phy_ctrl 2470 * 2471 * SRIOMAINT_IR_PD_PHY_CTRL = SRIO Platform Dependent PHY Control 2472 * 2473 * Platform Dependent PHY Control 2474 * 2475 * Notes: 2476 * This register can be used for testing. The register is otherwise unused by the hardware. 2477 * 2478 * Clk_Rst: SRIOMAINT(0..1)_IR_PD_PHY_CTRL hclk hrst_n 2479 */ 2480union cvmx_sriomaintx_ir_pd_phy_ctrl 2481{ 2482 uint32_t u32; 2483 struct cvmx_sriomaintx_ir_pd_phy_ctrl_s 2484 { 2485#if __BYTE_ORDER == __BIG_ENDIAN 2486 uint32_t pd_ctrl : 32; /**< Unused Register available for testing */ 2487#else 2488 uint32_t pd_ctrl : 32; 2489#endif 2490 } s; 2491 struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn63xx; 2492 struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn63xxp1; 2493}; 2494typedef union cvmx_sriomaintx_ir_pd_phy_ctrl cvmx_sriomaintx_ir_pd_phy_ctrl_t; 2495 2496/** 2497 * cvmx_sriomaint#_ir_pd_phy_stat 2498 * 2499 * SRIOMAINT_IR_PD_PHY_STAT = SRIO Platform Dependent PHY Status 2500 * 2501 * Platform Dependent PHY Status 2502 * 2503 * Notes: 2504 * This register is used to monitor PHY status on each lane. They are documented here to assist in 2505 * debugging only. The lane numbers take into account the lane swap pin. 2506 * 2507 * Clk_Rst: SRIOMAINT(0..1)_IR_PD_PHY_STAT hclk hrst_n 2508 */ 2509union cvmx_sriomaintx_ir_pd_phy_stat 2510{ 2511 uint32_t u32; 2512 struct cvmx_sriomaintx_ir_pd_phy_stat_s 2513 { 2514#if __BYTE_ORDER == __BIG_ENDIAN 2515 uint32_t reserved_16_31 : 16; 2516 uint32_t ln3_rx : 3; /**< Phy Lane 3 RX Status 2517 0XX = Normal Operation 2518 100 = 8B/10B Error 2519 101 = Elastic Buffer Overflow (Data Lost) 2520 110 = Elastic Buffer Underflow (Data Corrupted) 2521 111 = Disparity Error */ 2522 uint32_t ln3_dis : 1; /**< Lane 3 Phy Clock Disabled 2523 0 = Phy Clock Valid 2524 1 = Phy Clock InValid */ 2525 uint32_t ln2_rx : 3; /**< Phy Lane 2 RX Status 2526 0XX = Normal Operation 2527 100 = 8B/10B Error 2528 101 = Elastic Buffer Overflow (Data Lost) 2529 110 = Elastic Buffer Underflow (Data Corrupted) 2530 111 = Disparity Error */ 2531 uint32_t ln2_dis : 1; /**< Lane 2 Phy Clock Disabled 2532 0 = Phy Clock Valid 2533 1 = Phy Clock InValid */ 2534 uint32_t ln1_rx : 3; /**< Phy Lane 1 RX Status 2535 0XX = Normal Operation 2536 100 = 8B/10B Error 2537 101 = Elastic Buffer Overflow (Data Lost) 2538 110 = Elastic Buffer Underflow (Data Corrupted) 2539 111 = Disparity Error */ 2540 uint32_t ln1_dis : 1; /**< Lane 1 Phy Clock Disabled 2541 0 = Phy Clock Valid 2542 1 = Phy Clock InValid */ 2543 uint32_t ln0_rx : 3; /**< Phy Lane 0 RX Status 2544 0XX = Normal Operation 2545 100 = 8B/10B Error 2546 101 = Elastic Buffer Overflow (Data Lost) 2547 110 = Elastic Buffer Underflow (Data Corrupted) 2548 111 = Disparity Error */ 2549 uint32_t ln0_dis : 1; /**< Lane 0 Phy Clock Disabled 2550 0 = Phy Clock Valid 2551 1 = Phy Clock InValid */ 2552#else 2553 uint32_t ln0_dis : 1; 2554 uint32_t ln0_rx : 3; 2555 uint32_t ln1_dis : 1; 2556 uint32_t ln1_rx : 3; 2557 uint32_t ln2_dis : 1; 2558 uint32_t ln2_rx : 3; 2559 uint32_t ln3_dis : 1; 2560 uint32_t ln3_rx : 3; 2561 uint32_t reserved_16_31 : 16; 2562#endif 2563 } s; 2564 struct cvmx_sriomaintx_ir_pd_phy_stat_s cn63xx; 2565 struct cvmx_sriomaintx_ir_pd_phy_stat_s cn63xxp1; 2566}; 2567typedef union cvmx_sriomaintx_ir_pd_phy_stat cvmx_sriomaintx_ir_pd_phy_stat_t; 2568 2569/** 2570 * cvmx_sriomaint#_ir_pi_phy_ctrl 2571 * 2572 * SRIOMAINT_IR_PI_PHY_CTRL = SRIO Platform Independent PHY Control 2573 * 2574 * Platform Independent PHY Control 2575 * 2576 * Notes: 2577 * This register is used to control platform independent operating modes of the transceivers. These 2578 * control bits are uniform across all platforms. 2579 * 2580 * Clk_Rst: SRIOMAINT(0..1)_IR_PI_PHY_CTRL hclk hrst_n 2581 */ 2582union cvmx_sriomaintx_ir_pi_phy_ctrl 2583{ 2584 uint32_t u32; 2585 struct cvmx_sriomaintx_ir_pi_phy_ctrl_s 2586 { 2587#if __BYTE_ORDER == __BIG_ENDIAN 2588 uint32_t tx_reset : 1; /**< Outgoing PHY Logic Reset. 0=Reset, 1=Normal Op */ 2589 uint32_t rx_reset : 1; /**< Incoming PHY Logic Reset. 0=Reset, 1=Normal Op */ 2590 uint32_t reserved_29_29 : 1; 2591 uint32_t loopback : 2; /**< These bits control the state of the loopback 2592 control vector on the transceiver interface. The 2593 loopback modes are enumerated as follows: 2594 00 - No Loopback 2595 01 - Near End PCS Loopback 2596 10 - Far End PCS Loopback 2597 11 - Both Near and Far End PCS Loopback */ 2598 uint32_t reserved_0_26 : 27; 2599#else 2600 uint32_t reserved_0_26 : 27; 2601 uint32_t loopback : 2; 2602 uint32_t reserved_29_29 : 1; 2603 uint32_t rx_reset : 1; 2604 uint32_t tx_reset : 1; 2605#endif 2606 } s; 2607 struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn63xx; 2608 struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn63xxp1; 2609}; 2610typedef union cvmx_sriomaintx_ir_pi_phy_ctrl cvmx_sriomaintx_ir_pi_phy_ctrl_t; 2611 2612/** 2613 * cvmx_sriomaint#_ir_pi_phy_stat 2614 * 2615 * SRIOMAINT_IR_PI_PHY_STAT = SRIO Platform Independent PHY Status 2616 * 2617 * Platform Independent PHY Status 2618 * 2619 * Notes: 2620 * This register displays the status of the link initialization state machine. Changes to this state 2621 * cause the SRIO(0..1)_INT_REG.LINK_UP or SRIO(0..1)_INT_REG.LINK_DOWN interrupts. 2622 * 2623 * Clk_Rst: SRIOMAINT(0..1)_IR_PI_PHY_STAT hclk hrst_n 2624 */ 2625union cvmx_sriomaintx_ir_pi_phy_stat 2626{ 2627 uint32_t u32; 2628 struct cvmx_sriomaintx_ir_pi_phy_stat_s 2629 { 2630#if __BYTE_ORDER == __BIG_ENDIAN 2631 uint32_t reserved_12_31 : 20; 2632 uint32_t tx_rdy : 1; /**< Minimum number of Status Transmitted (Pass 2) */ 2633 uint32_t rx_rdy : 1; /**< Minimum number of Good Status Received (Pass 2) */ 2634 uint32_t init_sm : 10; /**< Initialization State Machine 2635 001 - Silent 2636 002 - Seek 2637 004 - Discovery 2638 008 - 1x_Mode_Lane0 2639 010 - 1x_Mode_Lane1 2640 020 - 1x_Mode_Lane2 2641 040 - 1x_Recovery 2642 080 - 2x_Mode 2643 100 - 2x_Recovery 2644 200 - 4x_Mode 2645 All others are reserved */ 2646#else 2647 uint32_t init_sm : 10; 2648 uint32_t rx_rdy : 1; 2649 uint32_t tx_rdy : 1; 2650 uint32_t reserved_12_31 : 20; 2651#endif 2652 } s; 2653 struct cvmx_sriomaintx_ir_pi_phy_stat_s cn63xx; 2654 struct cvmx_sriomaintx_ir_pi_phy_stat_cn63xxp1 2655 { 2656#if __BYTE_ORDER == __BIG_ENDIAN 2657 uint32_t reserved_10_31 : 22; 2658 uint32_t init_sm : 10; /**< Initialization State Machine 2659 001 - Silent 2660 002 - Seek 2661 004 - Discovery 2662 008 - 1x_Mode_Lane0 2663 010 - 1x_Mode_Lane1 2664 020 - 1x_Mode_Lane2 2665 040 - 1x_Recovery 2666 080 - 2x_Mode 2667 100 - 2x_Recovery 2668 200 - 4x_Mode 2669 All others are reserved */ 2670#else 2671 uint32_t init_sm : 10; 2672 uint32_t reserved_10_31 : 22; 2673#endif 2674 } cn63xxp1; 2675}; 2676typedef union cvmx_sriomaintx_ir_pi_phy_stat cvmx_sriomaintx_ir_pi_phy_stat_t; 2677 2678/** 2679 * cvmx_sriomaint#_ir_sp_rx_ctrl 2680 * 2681 * SRIOMAINT_IR_SP_RX_CTRL = SRIO Soft Packet FIFO Receive Control 2682 * 2683 * Soft Packet FIFO Receive Control 2684 * 2685 * Notes: 2686 * This register is used to configure events generated by the reception of packets using the soft 2687 * packet FIFO. 2688 * 2689 * Clk_Rst: SRIOMAINT(0..1)_IR_SP_RX_CTRL hclk hrst_n 2690 */ 2691union cvmx_sriomaintx_ir_sp_rx_ctrl 2692{ 2693 uint32_t u32; 2694 struct cvmx_sriomaintx_ir_sp_rx_ctrl_s 2695 { 2696#if __BYTE_ORDER == __BIG_ENDIAN 2697 uint32_t reserved_1_31 : 31; 2698 uint32_t overwrt : 1; /**< When clear, SRIO drops received packets that should 2699 enter the soft packet FIFO when the FIFO is full. 2700 When set, SRIO 2701 stalls received packets that should enter the soft 2702 packet FIFO when the FIFO is full. SRIO may stop 2703 receiving any packets in this stall case if 2704 software does not drain the receive soft packet 2705 FIFO. */ 2706#else 2707 uint32_t overwrt : 1; 2708 uint32_t reserved_1_31 : 31; 2709#endif 2710 } s; 2711 struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn63xx; 2712 struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn63xxp1; 2713}; 2714typedef union cvmx_sriomaintx_ir_sp_rx_ctrl cvmx_sriomaintx_ir_sp_rx_ctrl_t; 2715 2716/** 2717 * cvmx_sriomaint#_ir_sp_rx_data 2718 * 2719 * SRIOMAINT_IR_SP_RX_DATA = SRIO Soft Packet FIFO Receive Data 2720 * 2721 * Soft Packet FIFO Receive Data 2722 * 2723 * Notes: 2724 * This register is used to read data from the soft packet FIFO. The Soft Packet FIFO contains the 2725 * majority of the packet data received from the SRIO link. The packet does not include the Control 2726 * Symbols or the initial byte containing AckId, 2 Reserved Bits and the CRF. In the case of packets 2727 * with less than 80 bytes (including AckId byte) both the trailing CRC and Pad (if present) are 2728 * included in the FIFO and Octet Count. In the case of a packet with exactly 80 bytes (including 2729 * the AckId byte) the CRC is removed and the Pad is maintained so the Octet Count will read 81 bytes 2730 * instead of the expected 83. In cases over 80 bytes the CRC at 80 bytes is removed but the 2731 * trailing CRC and Pad (if necessary) are present. 2732 * 2733 * Clk_Rst: SRIOMAINT(0..1)_IR_SP_RX_DATA hclk hrst_n 2734 */ 2735union cvmx_sriomaintx_ir_sp_rx_data 2736{ 2737 uint32_t u32; 2738 struct cvmx_sriomaintx_ir_sp_rx_data_s 2739 { 2740#if __BYTE_ORDER == __BIG_ENDIAN 2741 uint32_t pkt_data : 32; /**< This register is used to read packet data from the 2742 RX FIFO. */ 2743#else 2744 uint32_t pkt_data : 32; 2745#endif 2746 } s; 2747 struct cvmx_sriomaintx_ir_sp_rx_data_s cn63xx; 2748 struct cvmx_sriomaintx_ir_sp_rx_data_s cn63xxp1; 2749}; 2750typedef union cvmx_sriomaintx_ir_sp_rx_data cvmx_sriomaintx_ir_sp_rx_data_t; 2751 2752/** 2753 * cvmx_sriomaint#_ir_sp_rx_stat 2754 * 2755 * SRIOMAINT_IR_SP_RX_STAT = SRIO Soft Packet FIFO Receive Status 2756 * 2757 * Soft Packet FIFO Receive Status 2758 * 2759 * Notes: 2760 * This register is used to monitor the reception of packets using the soft packet FIFO. 2761 * The HW sets SRIO_INT_REG[SOFT_RX] every time a packet arrives in the soft packet FIFO. To read 2762 * out (one or more) packets, the following procedure may be best: 2763 * (1) clear SRIO_INT_REG[SOFT_RX], 2764 * (2) read this CSR to determine how many packets there are, 2765 * (3) read the packets out (via SRIOMAINT*_IR_SP_RX_DATA). 2766 * This procedure could lead to situations where SOFT_RX will be set even though there are currently 2767 * no packets - the SW interrupt handler would need to properly handle this case 2768 * 2769 * Clk_Rst: SRIOMAINT(0..1)_IR_SP_RX_STAT hclk hrst_n 2770 */ 2771union cvmx_sriomaintx_ir_sp_rx_stat 2772{ 2773 uint32_t u32; 2774 struct cvmx_sriomaintx_ir_sp_rx_stat_s 2775 { 2776#if __BYTE_ORDER == __BIG_ENDIAN 2777 uint32_t octets : 16; /**< This field shows how many octets are remaining 2778 in the current packet in the RX FIFO. */ 2779 uint32_t buffers : 4; /**< This field indicates how many complete packets are 2780 stored in the Rx FIFO. */ 2781 uint32_t drop_cnt : 7; /**< Number of Packets Received when the RX FIFO was 2782 full and then discarded. 2783 This field always reads zero in Pass 1 */ 2784 uint32_t full : 1; /**< This bit is set when the value of Buffers Filled 2785 equals the number of available reception buffers. 2786 This bit always reads zero in Pass 1 */ 2787 uint32_t fifo_st : 4; /**< These bits display the state of the state machine 2788 that controls loading of packet data into the RX 2789 FIFO. The enumeration of states are as follows: 2790 0000 - Idle 2791 0001 - Armed 2792 0010 - Active 2793 All other states are reserved. */ 2794#else 2795 uint32_t fifo_st : 4; 2796 uint32_t full : 1; 2797 uint32_t drop_cnt : 7; 2798 uint32_t buffers : 4; 2799 uint32_t octets : 16; 2800#endif 2801 } s; 2802 struct cvmx_sriomaintx_ir_sp_rx_stat_s cn63xx; 2803 struct cvmx_sriomaintx_ir_sp_rx_stat_cn63xxp1 2804 { 2805#if __BYTE_ORDER == __BIG_ENDIAN 2806 uint32_t octets : 16; /**< This field shows how many octets are remaining 2807 in the current packet in the RX FIFO. */ 2808 uint32_t buffers : 4; /**< This field indicates how many complete packets are 2809 stored in the Rx FIFO. */ 2810 uint32_t reserved_5_11 : 7; 2811 uint32_t full : 1; /**< This bit is set when the value of Buffers Filled 2812 equals the number of available reception buffers. 2813 This bit always reads zero in Pass 1 */ 2814 uint32_t fifo_st : 4; /**< These bits display the state of the state machine 2815 that controls loading of packet data into the RX 2816 FIFO. The enumeration of states are as follows: 2817 0000 - Idle 2818 0001 - Armed 2819 0010 - Active 2820 All other states are reserved. */ 2821#else 2822 uint32_t fifo_st : 4; 2823 uint32_t full : 1; 2824 uint32_t reserved_5_11 : 7; 2825 uint32_t buffers : 4; 2826 uint32_t octets : 16; 2827#endif 2828 } cn63xxp1; 2829}; 2830typedef union cvmx_sriomaintx_ir_sp_rx_stat cvmx_sriomaintx_ir_sp_rx_stat_t; 2831 2832/** 2833 * cvmx_sriomaint#_ir_sp_tx_ctrl 2834 * 2835 * SRIOMAINT_IR_SP_TX_CTRL = SRIO Soft Packet FIFO Transmit Control 2836 * 2837 * Soft Packet FIFO Transmit Control 2838 * 2839 * Notes: 2840 * This register is used to configure and control the transmission of packets using the soft packet 2841 * FIFO. 2842 * 2843 * Clk_Rst: SRIOMAINT_IR_SP_TX_CTRL hclk hrst_n 2844 */ 2845union cvmx_sriomaintx_ir_sp_tx_ctrl 2846{ 2847 uint32_t u32; 2848 struct cvmx_sriomaintx_ir_sp_tx_ctrl_s 2849 { 2850#if __BYTE_ORDER == __BIG_ENDIAN 2851 uint32_t octets : 16; /**< Writing a non-zero value (N) to this field arms 2852 the packet FIFO for packet transmission. The FIFO 2853 control logic will transmit the next N bytes 2854 written 4-bytes at a time to the 2855 SRIOMAINT(0..1)_IR_SP_TX_DATA Register and create a 2856 single RapidIO packet. */ 2857 uint32_t reserved_0_15 : 16; 2858#else 2859 uint32_t reserved_0_15 : 16; 2860 uint32_t octets : 16; 2861#endif 2862 } s; 2863 struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn63xx; 2864 struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn63xxp1; 2865}; 2866typedef union cvmx_sriomaintx_ir_sp_tx_ctrl cvmx_sriomaintx_ir_sp_tx_ctrl_t; 2867 2868/** 2869 * cvmx_sriomaint#_ir_sp_tx_data 2870 * 2871 * SRIOMAINT_IR_SP_TX_DATA = SRIO Soft Packet FIFO Transmit Data 2872 * 2873 * Soft Packet FIFO Transmit Data 2874 * 2875 * Notes: 2876 * This register is used to write data to the soft packet FIFO. The format of the packet follows the 2877 * Internal Packet Format (add link here). Care must be taken on creating TIDs for the packets which 2878 * generate a response. Bits [7:6] of the 8 bit TID must be set for all Soft Packet FIFO generated 2879 * packets. TID values of 0x00 - 0xBF are reserved for hardware generated Tags. The remainer of the 2880 * TID[5:0] must be unique for each packet in flight and cannot be reused until a response is received 2881 * in the SRIOMAINT(0..1)_IR_SP_RX_DATA register. 2882 * 2883 * Clk_Rst: SRIOMAINT(0..1)_IR_SP_TX_DATA hclk hrst_n 2884 */ 2885union cvmx_sriomaintx_ir_sp_tx_data 2886{ 2887 uint32_t u32; 2888 struct cvmx_sriomaintx_ir_sp_tx_data_s 2889 { 2890#if __BYTE_ORDER == __BIG_ENDIAN 2891 uint32_t pkt_data : 32; /**< This register is used to write packet data to the 2892 Tx FIFO. Reads of this register will return zero. */ 2893#else 2894 uint32_t pkt_data : 32; 2895#endif 2896 } s; 2897 struct cvmx_sriomaintx_ir_sp_tx_data_s cn63xx; 2898 struct cvmx_sriomaintx_ir_sp_tx_data_s cn63xxp1; 2899}; 2900typedef union cvmx_sriomaintx_ir_sp_tx_data cvmx_sriomaintx_ir_sp_tx_data_t; 2901 2902/** 2903 * cvmx_sriomaint#_ir_sp_tx_stat 2904 * 2905 * SRIOMAINT_IR_SP_TX_STAT = SRIO Soft Packet FIFO Transmit Status 2906 * 2907 * Soft Packet FIFO Transmit Status 2908 * 2909 * Notes: 2910 * This register is used to monitor the transmission of packets using the soft packet FIFO. 2911 * 2912 * Clk_Rst: SRIOMAINT(0..1)_IR_SP_TX_STAT hclk hrst_n 2913 */ 2914union cvmx_sriomaintx_ir_sp_tx_stat 2915{ 2916 uint32_t u32; 2917 struct cvmx_sriomaintx_ir_sp_tx_stat_s 2918 { 2919#if __BYTE_ORDER == __BIG_ENDIAN 2920 uint32_t octets : 16; /**< This field shows how many octets are still to be 2921 loaded in the current packet. */ 2922 uint32_t buffers : 4; /**< This field indicates how many complete packets are 2923 stored in the Tx FIFO. The field always reads 2924 zero in the current hardware. */ 2925 uint32_t reserved_5_11 : 7; 2926 uint32_t full : 1; /**< This bit is set when the value of Buffers Filled 2927 equals the number of available transmission 2928 buffers. */ 2929 uint32_t fifo_st : 4; /**< These bits display the state of the state machine 2930 that controls loading of packet data into the TX 2931 FIFO. The enumeration of states are as follows: 2932 0000 - Idle 2933 0001 - Armed 2934 0010 - Active 2935 All other states are reserved. */ 2936#else 2937 uint32_t fifo_st : 4; 2938 uint32_t full : 1; 2939 uint32_t reserved_5_11 : 7; 2940 uint32_t buffers : 4; 2941 uint32_t octets : 16; 2942#endif 2943 } s; 2944 struct cvmx_sriomaintx_ir_sp_tx_stat_s cn63xx; 2945 struct cvmx_sriomaintx_ir_sp_tx_stat_s cn63xxp1; 2946}; 2947typedef union cvmx_sriomaintx_ir_sp_tx_stat cvmx_sriomaintx_ir_sp_tx_stat_t; 2948 2949/** 2950 * cvmx_sriomaint#_lane_#_status_0 2951 * 2952 * SRIOMAINT_LANE_X_STATUS_0 = SRIO Lane X Status 0 2953 * 2954 * SRIO Lane Status 0 2955 * 2956 * Notes: 2957 * This register contains status information about the local lane transceiver. 2958 * 2959 * Clk_Rst: SRIOMAINT(0..1)_LANE_[0:3]_STATUS_0 hclk hrst_n 2960 */ 2961union cvmx_sriomaintx_lane_x_status_0 2962{ 2963 uint32_t u32; 2964 struct cvmx_sriomaintx_lane_x_status_0_s 2965 { 2966#if __BYTE_ORDER == __BIG_ENDIAN 2967 uint32_t port : 8; /**< The number of the port within the device to which 2968 the lane is assigned. */ 2969 uint32_t lane : 4; /**< Lane Number within the port. */ 2970 uint32_t tx_type : 1; /**< Transmitter Type 2971 0 = Short Run 2972 1 = Long Run */ 2973 uint32_t tx_mode : 1; /**< Transmitter Operating Mode 2974 0 = Short Run 2975 1 = Long Run */ 2976 uint32_t rx_type : 2; /**< Receiver Type 2977 0 = Short Run 2978 1 = Medium Run 2979 2 = Long Run 2980 3 = Reserved */ 2981 uint32_t rx_inv : 1; /**< Receiver Input Inverted 2982 0 = No Inversion 2983 1 = Input Inverted */ 2984 uint32_t rx_adapt : 1; /**< Receiver Trained 2985 0 = One or more adaptive equalizers are 2986 controlled by the lane receiver and at least 2987 one is not trained. 2988 1 = The lane receiver controls no adaptive 2989 equalizers or all the equalizers are trained. */ 2990 uint32_t rx_sync : 1; /**< Receiver Lane Sync'd */ 2991 uint32_t rx_train : 1; /**< Receiver Lane Trained */ 2992 uint32_t dec_err : 4; /**< 8Bit/10Bit Decoding Errors 2993 0 = No Errors since last read 2994 1-14 = Number of Errors since last read 2995 15 = Fifteen or more Errors since last read */ 2996 uint32_t xsync : 1; /**< Receiver Lane Sync Change 2997 0 = Lane Sync has not changed since last read 2998 1 = Lane Sync has changed since last read */ 2999 uint32_t xtrain : 1; /**< Receiver Training Change 3000 0 = Training has not changed since last read 3001 1 = Training has changed since last read */ 3002 uint32_t reserved_4_5 : 2; 3003 uint32_t status1 : 1; /**< Status 1 CSR Implemented */ 3004 uint32_t statusn : 3; /**< Status 2-7 Not Implemented */ 3005#else 3006 uint32_t statusn : 3; 3007 uint32_t status1 : 1; 3008 uint32_t reserved_4_5 : 2; 3009 uint32_t xtrain : 1; 3010 uint32_t xsync : 1; 3011 uint32_t dec_err : 4; 3012 uint32_t rx_train : 1; 3013 uint32_t rx_sync : 1; 3014 uint32_t rx_adapt : 1; 3015 uint32_t rx_inv : 1; 3016 uint32_t rx_type : 2; 3017 uint32_t tx_mode : 1; 3018 uint32_t tx_type : 1; 3019 uint32_t lane : 4; 3020 uint32_t port : 8; 3021#endif 3022 } s; 3023 struct cvmx_sriomaintx_lane_x_status_0_s cn63xx; 3024 struct cvmx_sriomaintx_lane_x_status_0_s cn63xxp1; 3025}; 3026typedef union cvmx_sriomaintx_lane_x_status_0 cvmx_sriomaintx_lane_x_status_0_t; 3027 3028/** 3029 * cvmx_sriomaint#_lcs_ba0 3030 * 3031 * SRIOMAINT_LCS_BA0 = SRIO Local Configuration Space MSB Base Address 3032 * 3033 * MSBs of SRIO Address Space mapped to Maintenance BAR. 3034 * 3035 * Notes: 3036 * The double word aligned SRIO address window mapped to the SRIO Maintenance BAR. This window has 3037 * the highest priority and eclipses matches to the BAR0, BAR1 and BAR2 windows. Note: Address bits 3038 * not supplied in the transfer are considered zero. For example, SRIO Address 65:35 must be set to 3039 * zero to match in a 34-bit access. SRIO Address 65:50 must be set to zero to match in a 50-bit 3040 * access. This coding allows the Maintenance Bar window to appear in specific address spaces. The 3041 * remaining bits are located in SRIOMAINT(0..1)_LCS_BA1. This SRIO maintenance BAR is effectively 3042 * disabled when LCSBA[30] is set with 34 or 50-bit addressing. 3043 * 3044 * Clk_Rst: SRIOMAINT(0..1)_LCS_BA0 hclk hrst_n 3045 */ 3046union cvmx_sriomaintx_lcs_ba0 3047{ 3048 uint32_t u32; 3049 struct cvmx_sriomaintx_lcs_ba0_s 3050 { 3051#if __BYTE_ORDER == __BIG_ENDIAN 3052 uint32_t reserved_31_31 : 1; 3053 uint32_t lcsba : 31; /**< SRIO Address 65:35 */ 3054#else 3055 uint32_t lcsba : 31; 3056 uint32_t reserved_31_31 : 1; 3057#endif 3058 } s; 3059 struct cvmx_sriomaintx_lcs_ba0_s cn63xx; 3060 struct cvmx_sriomaintx_lcs_ba0_s cn63xxp1; 3061}; 3062typedef union cvmx_sriomaintx_lcs_ba0 cvmx_sriomaintx_lcs_ba0_t; 3063 3064/** 3065 * cvmx_sriomaint#_lcs_ba1 3066 * 3067 * SRIOMAINT_LCS_BA1 = SRIO Local Configuration Space LSB Base Address 3068 * 3069 * LSBs of SRIO Address Space mapped to Maintenance BAR. 3070 * 3071 * Notes: 3072 * The double word aligned SRIO address window mapped to the SRIO Maintenance BAR. This window has 3073 * the highest priority and eclipses matches to the BAR0, BAR1 and BAR2 windows. Address bits not 3074 * supplied in the transfer are considered zero. For example, SRIO Address 65:35 must be set to zero 3075 * to match in a 34-bit access and SRIO Address 65:50 must be set to zero to match in a 50-bit access. 3076 * This coding allows the Maintenance Bar window to appear in specific address spaces. Accesses 3077 * through this BAR are limited to single word (32-bit) aligned transfers of one to four bytes. 3078 * Accesses which violate this rule will return an error response if possible and be otherwise 3079 * ignored. The remaining bits are located in SRIOMAINT(0..1)_LCS_BA0. 3080 * 3081 * Clk_Rst: SRIOMAINT(0..1)_LCS_BA1 hclk hrst_n 3082 */ 3083union cvmx_sriomaintx_lcs_ba1 3084{ 3085 uint32_t u32; 3086 struct cvmx_sriomaintx_lcs_ba1_s 3087 { 3088#if __BYTE_ORDER == __BIG_ENDIAN 3089 uint32_t lcsba : 11; /**< SRIO Address 34:24 */ 3090 uint32_t reserved_0_20 : 21; 3091#else 3092 uint32_t reserved_0_20 : 21; 3093 uint32_t lcsba : 11; 3094#endif 3095 } s; 3096 struct cvmx_sriomaintx_lcs_ba1_s cn63xx; 3097 struct cvmx_sriomaintx_lcs_ba1_s cn63xxp1; 3098}; 3099typedef union cvmx_sriomaintx_lcs_ba1 cvmx_sriomaintx_lcs_ba1_t; 3100 3101/** 3102 * cvmx_sriomaint#_m2s_bar0_start0 3103 * 3104 * SRIOMAINT_M2S_BAR0_START0 = SRIO Device Access BAR0 MSB Start 3105 * 3106 * The starting SRIO address to forwarded to the NPEI Configuration Space. 3107 * 3108 * Notes: 3109 * This register specifies the 50-bit and 66-bit SRIO Address mapped to the BAR0 Space. See 3110 * SRIOMAINT(0..1)_M2S_BAR0_START1 for more details. This register is only writeable over SRIO if the 3111 * SRIO(0..1)_ACC_CTRL.DENY_BAR0 bit is zero. 3112 * 3113 * Clk_Rst: SRIOMAINT(0..1)_M2S_BAR0_START0 hclk hrst_n 3114 */ 3115union cvmx_sriomaintx_m2s_bar0_start0 3116{ 3117 uint32_t u32; 3118 struct cvmx_sriomaintx_m2s_bar0_start0_s 3119 { 3120#if __BYTE_ORDER == __BIG_ENDIAN 3121 uint32_t addr64 : 16; /**< SRIO Address 63:48 */ 3122 uint32_t addr48 : 16; /**< SRIO Address 47:32 */ 3123#else 3124 uint32_t addr48 : 16; 3125 uint32_t addr64 : 16; 3126#endif 3127 } s; 3128 struct cvmx_sriomaintx_m2s_bar0_start0_s cn63xx; 3129 struct cvmx_sriomaintx_m2s_bar0_start0_s cn63xxp1; 3130}; 3131typedef union cvmx_sriomaintx_m2s_bar0_start0 cvmx_sriomaintx_m2s_bar0_start0_t; 3132 3133/** 3134 * cvmx_sriomaint#_m2s_bar0_start1 3135 * 3136 * SRIOMAINT_M2S_BAR0_START1 = SRIO Device Access BAR0 LSB Start 3137 * 3138 * The starting SRIO address to forwarded to the NPEI Configuration Space. 3139 * 3140 * Notes: 3141 * This register specifies the SRIO Address mapped to the BAR0 RSL Space. If the transaction has not 3142 * already been mapped to SRIO Maintenance Space through the SRIOMAINT_LCS_BA[1:0] registers, if 3143 * ENABLE is set and the address bits match then the SRIO Memory transactions will map to Octeon SLI 3144 * Registers. 34-bit address transactions require a match in SRIO Address 33:14 and require all the 3145 * other bits in ADDR48, ADDR64 and ADDR66 fields to be zero. 50-bit address transactions a match of 3146 * SRIO Address 49:14 and require all the other bits of ADDR64 and ADDR66 to be zero. 66-bit address 3147 * transactions require matches of all valid address field bits. Reads and Writes through Bar0 3148 * have a size limit of 8 bytes and cannot cross a 64-bit boundry. All accesses with sizes greater 3149 * than this limit will be ignored and return an error on any SRIO responses. Note: ADDR48 and 3150 * ADDR64 fields are located in SRIOMAINT(0..1)_M2S_BAR0_START0. This register is only writeable over 3151 * SRIO if the SRIO(0..1)_ACC_CTRL.DENY_BAR0 bit is zero. 3152 * 3153 * Clk_Rst: SRIOMAINT(0..1)_M2S_BAR0_START1 hclk hrst_n 3154 */ 3155union cvmx_sriomaintx_m2s_bar0_start1 3156{ 3157 uint32_t u32; 3158 struct cvmx_sriomaintx_m2s_bar0_start1_s 3159 { 3160#if __BYTE_ORDER == __BIG_ENDIAN 3161 uint32_t addr32 : 18; /**< SRIO Address 31:14 */ 3162 uint32_t reserved_3_13 : 11; 3163 uint32_t addr66 : 2; /**< SRIO Address 65:64 */ 3164 uint32_t enable : 1; /**< Enable BAR0 Access */ 3165#else 3166 uint32_t enable : 1; 3167 uint32_t addr66 : 2; 3168 uint32_t reserved_3_13 : 11; 3169 uint32_t addr32 : 18; 3170#endif 3171 } s; 3172 struct cvmx_sriomaintx_m2s_bar0_start1_s cn63xx; 3173 struct cvmx_sriomaintx_m2s_bar0_start1_s cn63xxp1; 3174}; 3175typedef union cvmx_sriomaintx_m2s_bar0_start1 cvmx_sriomaintx_m2s_bar0_start1_t; 3176 3177/** 3178 * cvmx_sriomaint#_m2s_bar1_start0 3179 * 3180 * SRIOMAINT_M2S_BAR1_START0 = SRIO Device Access BAR1 MSB Start 3181 * 3182 * The starting SRIO address to forwarded to the BAR1 Memory Space. 3183 * 3184 * Notes: 3185 * This register specifies the 50-bit and 66-bit SRIO Address mapped to the BAR1 Space. See 3186 * SRIOMAINT(0..1)_M2S_BAR1_START1 for more details. This register is only writeable over SRIO if the 3187 * SRIO(0..1)_ACC_CTRL.DENY_BAR1 bit is zero. 3188 * 3189 * Clk_Rst: SRIOMAINT(0..1)_M2S_BAR1_START0 hclk hrst_n 3190 */ 3191union cvmx_sriomaintx_m2s_bar1_start0 3192{ 3193 uint32_t u32; 3194 struct cvmx_sriomaintx_m2s_bar1_start0_s 3195 { 3196#if __BYTE_ORDER == __BIG_ENDIAN 3197 uint32_t addr64 : 16; /**< SRIO Address 63:48 */ 3198 uint32_t addr48 : 16; /**< SRIO Address 47:32 */ 3199#else 3200 uint32_t addr48 : 16; 3201 uint32_t addr64 : 16; 3202#endif 3203 } s; 3204 struct cvmx_sriomaintx_m2s_bar1_start0_s cn63xx; 3205 struct cvmx_sriomaintx_m2s_bar1_start0_s cn63xxp1; 3206}; 3207typedef union cvmx_sriomaintx_m2s_bar1_start0 cvmx_sriomaintx_m2s_bar1_start0_t; 3208 3209/** 3210 * cvmx_sriomaint#_m2s_bar1_start1 3211 * 3212 * SRIOMAINT_M2S_BAR1_START1 = SRIO Device to BAR1 Start 3213 * 3214 * The starting SRIO address to forwarded to the BAR1 Memory Space. 3215 * 3216 * Notes: 3217 * This register specifies the SRIO Address mapped to the BAR1 Space. If the transaction has not 3218 * already been mapped to SRIO Maintenance Space through the SRIOMAINT_LCS_BA[1:0] registers and the 3219 * address bits do not match enabled BAR0 addresses and if ENABLE is set and the addresses match the 3220 * BAR1 addresses then SRIO Memory transactions will map to Octeon Memory Space specified by 3221 * SRIOMAINT(0..1)_BAR1_IDX[31:0] registers. The BARSIZE field determines the size of BAR1, the entry 3222 * select bits, and the size of each entry. A 34-bit address matches BAR1 when it matches 3223 * SRIO_Address[33:20+BARSIZE] while all the other bits in ADDR48, ADDR64 and ADDR66 are zero. 3224 * A 50-bit address matches BAR1 when it matches SRIO_Address[49:20+BARSIZE] while all the 3225 * other bits of ADDR64 and ADDR66 are zero. A 66-bit address matches BAR1 when all of 3226 * SRIO_Address[65:20+BARSIZE] match all corresponding address CSR field bits. Note: ADDR48 and 3227 * ADDR64 fields are located in SRIOMAINT(0..1)_M2S_BAR1_START0. This register is only writeable from SRIO 3228 * if the SRIO(0..1)_ACC_CTRL.DENY_BAR1 bit is zero. 3229 * 3230 * Clk_Rst: SRIOMAINT(0..1)_M2S_BAR1_START1 hclk hrst_n 3231 */ 3232union cvmx_sriomaintx_m2s_bar1_start1 3233{ 3234 uint32_t u32; 3235 struct cvmx_sriomaintx_m2s_bar1_start1_s 3236 { 3237#if __BYTE_ORDER == __BIG_ENDIAN 3238 uint32_t addr32 : 12; /**< SRIO Address 31:20 3239 With BARSIZE < 12, the upper 12-BARSIZE 3240 bits of this field are used, and the lower BARSIZE 3241 bits of this field are unused by the SRIO hardware. */ 3242 uint32_t reserved_7_19 : 13; 3243 uint32_t barsize : 4; /**< Bar Size. 3244 SRIO_Address* 3245 --------------------- 3246 / \ 3247 BARSIZE BAR Entry Entry Entry 3248 Value BAR compare Select Offset Size 3249 Size bits bits bits 3250 0 1MB 65:20 19:16 15:0 64KB 3251 1 2MB 65:21 20:17 16:0 128KB 3252 2 4MB 65:22 21:18 17:0 256KB 3253 3 8MB 65:23 22:19 18:0 512KB 3254 4 16MB 65:24 23:20 19:0 1MB 3255 5 32MB 65:25 24:21 20:0 2MB 3256 6 64MB 65:26 25:22 21:0 4MB 3257 7 128MB 65:27 26:23 22:0 8MB 3258 8 256MB ** not in pass 1 3259 9 512MB ** not in pass 1 3260 10 1GB ** not in pass 1 3261 11 2GB ** not in pass 1 3262 12 4GB ** not in pass 1 3263 13 8GB ** not in pass 1 3264 3265 *The SRIO Transaction Address 3266 The entry select bits is the X that select an 3267 SRIOMAINT(0..1)_BAR1_IDXX entry. 3268 3269 In O63 pass 2, BARSIZE is 4 bits (6:3 in this 3270 CSR), and BARSIZE values 8-13 are implemented, 3271 providing a total possible BAR1 size range from 3272 1MB up to 8GB. */ 3273 uint32_t addr66 : 2; /**< SRIO Address 65:64 */ 3274 uint32_t enable : 1; /**< Enable BAR1 Access */ 3275#else 3276 uint32_t enable : 1; 3277 uint32_t addr66 : 2; 3278 uint32_t barsize : 4; 3279 uint32_t reserved_7_19 : 13; 3280 uint32_t addr32 : 12; 3281#endif 3282 } s; 3283 struct cvmx_sriomaintx_m2s_bar1_start1_s cn63xx; 3284 struct cvmx_sriomaintx_m2s_bar1_start1_cn63xxp1 3285 { 3286#if __BYTE_ORDER == __BIG_ENDIAN 3287 uint32_t addr32 : 12; /**< SRIO Address 31:20 3288 With BARSIZE < 12, the upper 12-BARSIZE 3289 bits of this field are used, and the lower BARSIZE 3290 bits of this field are unused by the SRIO hardware. */ 3291 uint32_t reserved_6_19 : 14; 3292 uint32_t barsize : 3; /**< Bar Size. 3293 SRIO_Address* 3294 --------------------- 3295 / \ 3296 BARSIZE BAR Entry Entry Entry 3297 Value BAR compare Select Offset Size 3298 Size bits bits bits 3299 0 1MB 65:20 19:16 15:0 64KB 3300 1 2MB 65:21 20:17 16:0 128KB 3301 2 4MB 65:22 21:18 17:0 256KB 3302 3 8MB 65:23 22:19 18:0 512KB 3303 4 16MB 65:24 23:20 19:0 1MB 3304 5 32MB 65:25 24:21 20:0 2MB 3305 6 64MB 65:26 25:22 21:0 4MB 3306 7 128MB 65:27 26:23 22:0 8MB 3307 8 256MB ** not in pass 1 3308 9 512MB ** not in pass 1 3309 10 1GB ** not in pass 1 3310 11 2GB ** not in pass 1 3311 12 4GB ** not in pass 1 3312 13 8GB ** not in pass 1 3313 3314 *The SRIO Transaction Address 3315 The entry select bits is the X that select an 3316 SRIOMAINT(0..1)_BAR1_IDXX entry. 3317 3318 In O63 pass 2, BARSIZE is 4 bits (6:3 in this 3319 CSR), and BARSIZE values 8-13 are implemented, 3320 providing a total possible BAR1 size range from 3321 1MB up to 8GB. */ 3322 uint32_t addr66 : 2; /**< SRIO Address 65:64 */ 3323 uint32_t enable : 1; /**< Enable BAR1 Access */ 3324#else 3325 uint32_t enable : 1; 3326 uint32_t addr66 : 2; 3327 uint32_t barsize : 3; 3328 uint32_t reserved_6_19 : 14; 3329 uint32_t addr32 : 12; 3330#endif 3331 } cn63xxp1; 3332}; 3333typedef union cvmx_sriomaintx_m2s_bar1_start1 cvmx_sriomaintx_m2s_bar1_start1_t; 3334 3335/** 3336 * cvmx_sriomaint#_m2s_bar2_start 3337 * 3338 * SRIOMAINT_M2S_BAR2_START = SRIO Device to BAR2 Start 3339 * 3340 * The starting SRIO address to forwarded to the BAR2 Memory Space. 3341 * 3342 * Notes: 3343 * This register specifies the SRIO Address mapped to the BAR2 Space. If ENABLE is set and the 3344 * address bits do not match and other enabled BAR address and match the BAR2 addresses then the SRIO 3345 * Memory transactions will map to Octeon BAR2 Memory Space. 34-bit address transactions require 3346 * ADDR66, ADDR64 and ADDR48 fields set to zero and supplies zeros for unused addresses 40:34. 3347 * 50-bit address transactions a match of SRIO Address 49:41 and require all the other bits of ADDR64 3348 * and ADDR66 to be zero. 66-bit address transactions require matches of all valid address field 3349 * bits. This register is only writeable over SRIO if the SRIO(0..1)_ACC_CTRL.DENY_BAR2 bit is zero. 3350 * 3351 * Clk_Rst: SRIOMAINT(0..1)_M2S_BAR2_START hclk hrst_n 3352 */ 3353union cvmx_sriomaintx_m2s_bar2_start 3354{ 3355 uint32_t u32; 3356 struct cvmx_sriomaintx_m2s_bar2_start_s 3357 { 3358#if __BYTE_ORDER == __BIG_ENDIAN 3359 uint32_t addr64 : 16; /**< SRIO Address 63:48 */ 3360 uint32_t addr48 : 7; /**< SRIO Address 47:41 */ 3361 uint32_t reserved_6_8 : 3; 3362 uint32_t esx : 2; /**< Endian Swap Mode used for SRIO 34-bit access. 3363 For 50/66-bit assesses Endian Swap is determine 3364 by ESX XOR'd with SRIO Addr 39:38. 3365 0 = No Swap 3366 1 = 64-bit Swap Bytes [ABCD_EFGH] -> [HGFE_DCBA] 3367 2 = 32-bit Swap Words [ABCD_EFGH] -> [DCBA_HGFE] 3368 3 = 32-bit Word Exch [ABCD_EFGH] -> [EFGH_ABCD] */ 3369 uint32_t cax : 1; /**< Cacheable Access Mode. When set transfer is 3370 cached. This bit is used for SRIO 34-bit access. 3371 For 50/66-bit accessas NCA is determine by CAX 3372 XOR'd with SRIO Addr 40. */ 3373 uint32_t addr66 : 2; /**< SRIO Address 65:64 */ 3374 uint32_t enable : 1; /**< Enable BAR2 Access */ 3375#else 3376 uint32_t enable : 1; 3377 uint32_t addr66 : 2; 3378 uint32_t cax : 1; 3379 uint32_t esx : 2; 3380 uint32_t reserved_6_8 : 3; 3381 uint32_t addr48 : 7; 3382 uint32_t addr64 : 16; 3383#endif 3384 } s; 3385 struct cvmx_sriomaintx_m2s_bar2_start_s cn63xx; 3386 struct cvmx_sriomaintx_m2s_bar2_start_s cn63xxp1; 3387}; 3388typedef union cvmx_sriomaintx_m2s_bar2_start cvmx_sriomaintx_m2s_bar2_start_t; 3389 3390/** 3391 * cvmx_sriomaint#_mac_ctrl 3392 * 3393 * SRIOMAINT_MAC_CTRL = SRIO MAC Control (Pass 2) 3394 * 3395 * Control for MAC Features 3396 * 3397 * Notes: 3398 * This register enables MAC optimizations that may not be supported by all SRIO devices. The 3399 * default values should be supported. This register can be changed at any time while the MAC is 3400 * out of reset. 3401 * 3402 * Clk_Rst: SRIOMAINT(0..1)_MAC_CTRL hclk hrst_n 3403 */ 3404union cvmx_sriomaintx_mac_ctrl 3405{ 3406 uint32_t u32; 3407 struct cvmx_sriomaintx_mac_ctrl_s 3408 { 3409#if __BYTE_ORDER == __BIG_ENDIAN 3410 uint32_t reserved_19_31 : 13; 3411 uint32_t rx_spf : 1; /**< Route all received packets to RX Soft Packet FIFO. 3412 No logical layer ERB Errors will be reported. 3413 Used for Diagnostics Only. */ 3414 uint32_t eop_mrg : 1; /**< Transmitted Packets can eliminate EOP Symbol on 3415 back to back packets. */ 3416 uint32_t type_mrg : 1; /**< Allow STYPE Merging on Transmit. */ 3417 uint32_t lnk_rtry : 16; /**< Number of times MAC will reissue Link Request 3418 after timeout. If retry count is exceeded Fatal 3419 Port Error will occur (see SRIO(0..1)_INT_REG.F_ERROR) */ 3420#else 3421 uint32_t lnk_rtry : 16; 3422 uint32_t type_mrg : 1; 3423 uint32_t eop_mrg : 1; 3424 uint32_t rx_spf : 1; 3425 uint32_t reserved_19_31 : 13; 3426#endif 3427 } s; 3428 struct cvmx_sriomaintx_mac_ctrl_s cn63xx; 3429}; 3430typedef union cvmx_sriomaintx_mac_ctrl cvmx_sriomaintx_mac_ctrl_t; 3431 3432/** 3433 * cvmx_sriomaint#_pe_feat 3434 * 3435 * SRIOMAINT_PE_FEAT = SRIO Processing Element Features 3436 * 3437 * The Supported Processing Element Features. 3438 * 3439 * Notes: 3440 * The Processing Element Feature register describes the major functionality provided by the SRIO 3441 * device. 3442 * 3443 * Clk_Rst: SRIOMAINT(0..1)_PE_FEAT hclk hrst_n 3444 */ 3445union cvmx_sriomaintx_pe_feat 3446{ 3447 uint32_t u32; 3448 struct cvmx_sriomaintx_pe_feat_s 3449 { 3450#if __BYTE_ORDER == __BIG_ENDIAN 3451 uint32_t bridge : 1; /**< Bridge Functions not supported. */ 3452 uint32_t memory : 1; /**< PE contains addressable memory. */ 3453 uint32_t proc : 1; /**< PE contains a local processor. */ 3454 uint32_t switchf : 1; /**< Switch Functions not supported. */ 3455 uint32_t mult_prt : 1; /**< Multiport Functions not supported. */ 3456 uint32_t reserved_7_26 : 20; 3457 uint32_t suppress : 1; /**< Error Recovery Suppression not supported. */ 3458 uint32_t crf : 1; /**< Critical Request Flow not supported. */ 3459 uint32_t lg_tran : 1; /**< Large Transport (16-bit Device IDs) supported. */ 3460 uint32_t ex_feat : 1; /**< Extended Feature Pointer is valid. */ 3461 uint32_t ex_addr : 3; /**< PE supports 66, 50 and 34-bit addresses. 3462 [2:1] are a RO copy of SRIO*_IP_FEATURE[A66,A50]. */ 3463#else 3464 uint32_t ex_addr : 3; 3465 uint32_t ex_feat : 1; 3466 uint32_t lg_tran : 1; 3467 uint32_t crf : 1; 3468 uint32_t suppress : 1; 3469 uint32_t reserved_7_26 : 20; 3470 uint32_t mult_prt : 1; 3471 uint32_t switchf : 1; 3472 uint32_t proc : 1; 3473 uint32_t memory : 1; 3474 uint32_t bridge : 1; 3475#endif 3476 } s; 3477 struct cvmx_sriomaintx_pe_feat_s cn63xx; 3478 struct cvmx_sriomaintx_pe_feat_s cn63xxp1; 3479}; 3480typedef union cvmx_sriomaintx_pe_feat cvmx_sriomaintx_pe_feat_t; 3481 3482/** 3483 * cvmx_sriomaint#_pe_llc 3484 * 3485 * SRIOMAINT_PE_LLC = SRIO Processing Element Logical Layer Control 3486 * 3487 * Addresses supported by the SRIO Device. 3488 * 3489 * Notes: 3490 * The Processing Element Logical Layer is used for general configuration for the logical interface. 3491 * 3492 * Clk_Rst: SRIOMAINT(0..1)_PE_LLC hclk hrst_n 3493 */ 3494union cvmx_sriomaintx_pe_llc 3495{ 3496 uint32_t u32; 3497 struct cvmx_sriomaintx_pe_llc_s 3498 { 3499#if __BYTE_ORDER == __BIG_ENDIAN 3500 uint32_t reserved_3_31 : 29; 3501 uint32_t ex_addr : 3; /**< Controls the number of address bits generated by 3502 PE as a source and processed by the PE as a 3503 target of an operation. 3504 001 = 34-bit Addresses 3505 010 = 50-bit Addresses 3506 100 = 66-bit Addresses 3507 All other encodings are reserved. */ 3508#else 3509 uint32_t ex_addr : 3; 3510 uint32_t reserved_3_31 : 29; 3511#endif 3512 } s; 3513 struct cvmx_sriomaintx_pe_llc_s cn63xx; 3514 struct cvmx_sriomaintx_pe_llc_s cn63xxp1; 3515}; 3516typedef union cvmx_sriomaintx_pe_llc cvmx_sriomaintx_pe_llc_t; 3517 3518/** 3519 * cvmx_sriomaint#_port_0_ctl 3520 * 3521 * SRIOMAINT_PORT_0_CTL = SRIO Port 0 Control 3522 * 3523 * Port 0 Control 3524 * 3525 * Notes: 3526 * This register contains assorted control bits. 3527 * 3528 * Clk_Rst: SRIOMAINT(0..1)_PORT_0_CTL hclk hrst_n 3529 */ 3530union cvmx_sriomaintx_port_0_ctl 3531{ 3532 uint32_t u32; 3533 struct cvmx_sriomaintx_port_0_ctl_s 3534 { 3535#if __BYTE_ORDER == __BIG_ENDIAN 3536 uint32_t pt_width : 2; /**< Hardware Port Width. 3537 00 = One Lane supported. 3538 01 = One/Two Lanes supported. 3539 10 = One/Four Lanes supported. 3540 11 = One/Two/Four Lanes supported. 3541 This is a RO copy of SRIO*_IP_FEATURE[PT_WIDTH]. */ 3542 uint32_t it_width : 3; /**< Initialized Port Width 3543 000 = Single-lane, Lane 0 3544 001 = Single-lane, Lane 1 or 2 3545 010 = Four-lane 3546 011 = Two-lane 3547 Others = Reserved */ 3548 uint32_t ov_width : 3; /**< Override Port Width. Writing this register causes 3549 the port to reinitialize. 3550 000 = No Override all lanes possible 3551 001 = Reserved 3552 010 = Force Single-lane, Lane 0 3553 011 = Force Single-lane, Lane 2 3554 (Lane 1 if only lanes 0,1 are connected) 3555 100 = Reserved 3556 101 = Force Two-lane, Disable Four-Lane 3557 110 = Force Four-lane, Disable Two-Lane 3558 111 = All lanes sizes enabled */ 3559 uint32_t disable : 1; /**< Port Disable. Setting this bit disables both 3560 drivers and receivers. */ 3561 uint32_t o_enable : 1; /**< Port Output Enable. When cleared, port will 3562 generate control symbols and respond to 3563 maintenance transactions only. When set, all 3564 transactions are allowed. */ 3565 uint32_t i_enable : 1; /**< Port Input Enable. When cleared, port will 3566 generate control symbols and respond to 3567 maintenance packets only. All other packets will 3568 not be accepted. */ 3569 uint32_t dis_err : 1; /**< Disable Error Checking. Diagnostic Only. */ 3570 uint32_t mcast : 1; /**< Reserved. */ 3571 uint32_t reserved_18_18 : 1; 3572 uint32_t enumb : 1; /**< Enumeration Boundry. SW can use this bit to 3573 determine port enumeration. */ 3574 uint32_t reserved_16_16 : 1; 3575 uint32_t ex_width : 2; /**< Extended Port Width not supported. */ 3576 uint32_t ex_stat : 2; /**< Extended Port Width Status. 00 = not supported */ 3577 uint32_t suppress : 8; /**< Retransmit Suppression Mask. CRF not Supported. */ 3578 uint32_t stp_port : 1; /**< Stop on Failed Port. This bit is used with the 3579 DROP_PKT bit to force certain behavior when the 3580 Error Rate Failed Threshold has been met or 3581 exceeded. */ 3582 uint32_t drop_pkt : 1; /**< Drop on Failed Port. This bit is used with the 3583 STP_PORT bit to force certain behavior when the 3584 Error Rate Failed Threshold has been met or 3585 exceeded. */ 3586 uint32_t prt_lock : 1; /**< When this bit is cleared, the packets that may be 3587 received and issued are controlled by the state of 3588 the O_ENABLE and I_ENABLE bits. When this bit is 3589 set, this port is stopped and is not enabled to 3590 issue or receive any packets; the input port can 3591 still follow the training procedure and can still 3592 send and respond to link-requests; all received 3593 packets return packet-not-accepted control symbols 3594 to force an error condition to be signaled by the 3595 sending device. */ 3596 uint32_t pt_type : 1; /**< Port Type. 1 = Serial port. */ 3597#else 3598 uint32_t pt_type : 1; 3599 uint32_t prt_lock : 1; 3600 uint32_t drop_pkt : 1; 3601 uint32_t stp_port : 1; 3602 uint32_t suppress : 8; 3603 uint32_t ex_stat : 2; 3604 uint32_t ex_width : 2; 3605 uint32_t reserved_16_16 : 1; 3606 uint32_t enumb : 1; 3607 uint32_t reserved_18_18 : 1; 3608 uint32_t mcast : 1; 3609 uint32_t dis_err : 1; 3610 uint32_t i_enable : 1; 3611 uint32_t o_enable : 1; 3612 uint32_t disable : 1; 3613 uint32_t ov_width : 3; 3614 uint32_t it_width : 3; 3615 uint32_t pt_width : 2; 3616#endif 3617 } s; 3618 struct cvmx_sriomaintx_port_0_ctl_s cn63xx; 3619 struct cvmx_sriomaintx_port_0_ctl_s cn63xxp1; 3620}; 3621typedef union cvmx_sriomaintx_port_0_ctl cvmx_sriomaintx_port_0_ctl_t; 3622 3623/** 3624 * cvmx_sriomaint#_port_0_ctl2 3625 * 3626 * SRIOMAINT_PORT_0_CTL2 = SRIO Port 0 Control 2 3627 * 3628 * Port 0 Control 2 3629 * 3630 * Notes: 3631 * These registers are accessed when a local processor or an external device wishes to examine the 3632 * port baudrate information. WARNING: Writes to this register will reinitialize the SRIO link. 3633 * 3634 * Clk_Rst: SRIOMAINT(0..1)_PORT_0_CTL2 hclk hrst_n 3635 */ 3636union cvmx_sriomaintx_port_0_ctl2 3637{ 3638 uint32_t u32; 3639 struct cvmx_sriomaintx_port_0_ctl2_s 3640 { 3641#if __BYTE_ORDER == __BIG_ENDIAN 3642 uint32_t sel_baud : 4; /**< Link Baud Rate Selected. 3643 0000 - No rate selected 3644 0001 - 1.25 GBaud 3645 0010 - 2.5 GBaud 3646 0011 - 3.125 GBaud 3647 0100 - 5.0 GBaud 3648 0101 - 6.25 GBaud (reserved) 3649 0110 - 0b1111 - Reserved 3650 Indicates the speed of the interface SERDES lanes 3651 (should match the value selected by SUP_* /ENB_* 3652 below). */ 3653 uint32_t baud_sup : 1; /**< Automatic Baud Rate Discovery not supported. */ 3654 uint32_t baud_enb : 1; /**< Auto Baud Rate Discovery Enable. */ 3655 uint32_t sup_125g : 1; /**< 1.25GB Rate Operation supported. 3656 Set when the interface SERDES lanes are operating 3657 at 1.25 Gbaud (as selected by QLM*_SPD straps). */ 3658 uint32_t enb_125g : 1; /**< 1.25GB Rate Operation enable. 3659 Reset to 1 when the interface SERDES lanes are 3660 operating at 1.25 Gbaud (as selected by QLM*_SPD 3661 straps). Reset to 0 otherwise. */ 3662 uint32_t sup_250g : 1; /**< 2.50GB Rate Operation supported. 3663 Set when the interface SERDES lanes are operating 3664 at 2.5 Gbaud (as selected by QLM*_SPD straps). */ 3665 uint32_t enb_250g : 1; /**< 2.50GB Rate Operation enable. 3666 Reset to 1 when the interface SERDES lanes are 3667 operating at 2.5 Gbaud (as selected by QLM*_SPD 3668 straps). Reset to 0 otherwise. */ 3669 uint32_t sup_312g : 1; /**< 3.125GB Rate Operation supported. 3670 Set when the interface SERDES lanes are operating 3671 at 3.125 Gbaud (as selected by QLM*_SPD straps). */ 3672 uint32_t enb_312g : 1; /**< 3.125GB Rate Operation enable. 3673 Reset to 1 when the interface SERDES lanes are 3674 operating at 3.125 Gbaud (as selected by QLM*_SPD 3675 straps). Reset to 0 otherwise. */ 3676 uint32_t sub_500g : 1; /**< 5.0GB Rate Operation supported. 3677 Set when the interface SERDES lanes are operating 3678 at 5.0 Gbaud (as selected by QLM*_SPD straps). */ 3679 uint32_t enb_500g : 1; /**< 5.0GB Rate Operation enable. 3680 Reset to 1 when the interface SERDES lanes are 3681 operating at 5.0 Gbaud (as selected by QLM*_SPD 3682 straps). Reset to 0 otherwise. */ 3683 uint32_t sup_625g : 1; /**< 6.25GB Rate Operation (not supported). */ 3684 uint32_t enb_625g : 1; /**< 6.25GB Rate Operation enable. */ 3685 uint32_t reserved_2_15 : 14; 3686 uint32_t tx_emph : 1; /**< Indicates whether is port is able to transmit 3687 commands to control the transmit emphasis in the 3688 connected port. */ 3689 uint32_t emph_en : 1; /**< Controls whether a port may adjust the 3690 transmit emphasis in the connected port. This bit 3691 should be cleared for normal operation. */ 3692#else 3693 uint32_t emph_en : 1; 3694 uint32_t tx_emph : 1; 3695 uint32_t reserved_2_15 : 14; 3696 uint32_t enb_625g : 1; 3697 uint32_t sup_625g : 1; 3698 uint32_t enb_500g : 1; 3699 uint32_t sub_500g : 1; 3700 uint32_t enb_312g : 1; 3701 uint32_t sup_312g : 1; 3702 uint32_t enb_250g : 1; 3703 uint32_t sup_250g : 1; 3704 uint32_t enb_125g : 1; 3705 uint32_t sup_125g : 1; 3706 uint32_t baud_enb : 1; 3707 uint32_t baud_sup : 1; 3708 uint32_t sel_baud : 4; 3709#endif 3710 } s; 3711 struct cvmx_sriomaintx_port_0_ctl2_s cn63xx; 3712 struct cvmx_sriomaintx_port_0_ctl2_s cn63xxp1; 3713}; 3714typedef union cvmx_sriomaintx_port_0_ctl2 cvmx_sriomaintx_port_0_ctl2_t; 3715 3716/** 3717 * cvmx_sriomaint#_port_0_err_stat 3718 * 3719 * SRIOMAINT_PORT_0_ERR_STAT = SRIO Port 0 Error and Status 3720 * 3721 * Port 0 Error and Status 3722 * 3723 * Notes: 3724 * This register displays port error and status information. Several port error conditions are 3725 * captured here and must be cleared by writing 1's to the individual bits. 3726 * 3727 * Clk_Rst: SRIOMAINT(0..1)_PORT_0_ERR_STAT hclk hrst_n 3728 */ 3729union cvmx_sriomaintx_port_0_err_stat 3730{ 3731 uint32_t u32; 3732 struct cvmx_sriomaintx_port_0_err_stat_s 3733 { 3734#if __BYTE_ORDER == __BIG_ENDIAN 3735 uint32_t reserved_27_31 : 5; 3736 uint32_t pkt_drop : 1; /**< Output Packet Dropped. */ 3737 uint32_t o_fail : 1; /**< Output Port has encountered a failure condition, 3738 meaning the port's failed error threshold has 3739 reached SRIOMAINT(0..1)_ERB_ERR_RATE_THR.ER_FAIL value. */ 3740 uint32_t o_dgrad : 1; /**< Output Port has encountered a degraded condition, 3741 meaning the port's degraded threshold has 3742 reached SRIOMAINT(0..1)_ERB_ERR_RATE_THR.ER_DGRAD 3743 value. */ 3744 uint32_t reserved_21_23 : 3; 3745 uint32_t o_retry : 1; /**< Output Retry Encountered. This bit is set when 3746 bit 18 is set. */ 3747 uint32_t o_rtried : 1; /**< Output Port has received a packet-retry condition 3748 and cannot make forward progress. This bit is set 3749 when bit 18 is set and is cleared when a packet- 3750 accepted or a packet-not-accepted control symbol 3751 is received. */ 3752 uint32_t o_sm_ret : 1; /**< Output Port State Machine has received a 3753 packet-retry control symbol and is retrying the 3754 packet. */ 3755 uint32_t o_error : 1; /**< Output Error Encountered and possibly recovered 3756 from. This sticky bit is set with bit 16. */ 3757 uint32_t o_sm_err : 1; /**< Output Port State Machine has encountered an 3758 error. */ 3759 uint32_t reserved_11_15 : 5; 3760 uint32_t i_sm_ret : 1; /**< Input Port State Machine has received a 3761 packet-retry control symbol and is retrying the 3762 packet. */ 3763 uint32_t i_error : 1; /**< Input Error Encountered and possibly recovered 3764 from. This sticky bit is set with bit 8. */ 3765 uint32_t i_sm_err : 1; /**< Input Port State Machine has encountered an 3766 error. */ 3767 uint32_t reserved_5_7 : 3; 3768 uint32_t pt_write : 1; /**< Port has encountered a condition which required it 3769 initiate a Maintenance Port-Write Operation. */ 3770 uint32_t reserved_3_3 : 1; 3771 uint32_t pt_error : 1; /**< Input or Output Port has encountered an 3772 unrecoverable error condition. */ 3773 uint32_t pt_ok : 1; /**< Input or Output Port are intitialized and the port 3774 is exchanging error free control symbols with 3775 attached device. */ 3776 uint32_t pt_uinit : 1; /**< Port is uninitialized. This bit and bit 1 are 3777 mutually exclusive. */ 3778#else 3779 uint32_t pt_uinit : 1; 3780 uint32_t pt_ok : 1; 3781 uint32_t pt_error : 1; 3782 uint32_t reserved_3_3 : 1; 3783 uint32_t pt_write : 1; 3784 uint32_t reserved_5_7 : 3; 3785 uint32_t i_sm_err : 1; 3786 uint32_t i_error : 1; 3787 uint32_t i_sm_ret : 1; 3788 uint32_t reserved_11_15 : 5; 3789 uint32_t o_sm_err : 1; 3790 uint32_t o_error : 1; 3791 uint32_t o_sm_ret : 1; 3792 uint32_t o_rtried : 1; 3793 uint32_t o_retry : 1; 3794 uint32_t reserved_21_23 : 3; 3795 uint32_t o_dgrad : 1; 3796 uint32_t o_fail : 1; 3797 uint32_t pkt_drop : 1; 3798 uint32_t reserved_27_31 : 5; 3799#endif 3800 } s; 3801 struct cvmx_sriomaintx_port_0_err_stat_s cn63xx; 3802 struct cvmx_sriomaintx_port_0_err_stat_s cn63xxp1; 3803}; 3804typedef union cvmx_sriomaintx_port_0_err_stat cvmx_sriomaintx_port_0_err_stat_t; 3805 3806/** 3807 * cvmx_sriomaint#_port_0_link_req 3808 * 3809 * SRIOMAINT_PORT_0_LINK_REQ = SRIO Port 0 Link Request (Pass 2) 3810 * 3811 * Port 0 Manual Link Request 3812 * 3813 * Notes: 3814 * Writing this register generates the link request symbol or eight device reset symbols. The 3815 * progress of the request can be determined by reading SRIOMAINT(0..1)_PORT_0_LINK_RESP. Only a single 3816 * request should be generated at a time. 3817 * 3818 * Clk_Rst: SRIOMAINT(0..1)_PORT_0_LINK_REQ hclk hrst_n 3819 */ 3820union cvmx_sriomaintx_port_0_link_req 3821{ 3822 uint32_t u32; 3823 struct cvmx_sriomaintx_port_0_link_req_s 3824 { 3825#if __BYTE_ORDER == __BIG_ENDIAN 3826 uint32_t reserved_3_31 : 29; 3827 uint32_t cmd : 3; /**< Link Request Command. 3828 011 - Reset Device 3829 100 - Link Request 3830 All other values reserved. */ 3831#else 3832 uint32_t cmd : 3; 3833 uint32_t reserved_3_31 : 29; 3834#endif 3835 } s; 3836 struct cvmx_sriomaintx_port_0_link_req_s cn63xx; 3837}; 3838typedef union cvmx_sriomaintx_port_0_link_req cvmx_sriomaintx_port_0_link_req_t; 3839 3840/** 3841 * cvmx_sriomaint#_port_0_link_resp 3842 * 3843 * SRIOMAINT_PORT_0_LINK_RESP = SRIO Port 0 Link Response (Pass 2) 3844 * 3845 * Port 0 Manual Link Response 3846 * 3847 * Notes: 3848 * This register only returns responses generated by writes to SRIOMAINT(0..1)_PORT_0_LINK_REQ. 3849 * 3850 * Clk_Rst: SRIOMAINT(0..1)_PORT_0_LINK_RESP hclk hrst_n 3851 */ 3852union cvmx_sriomaintx_port_0_link_resp 3853{ 3854 uint32_t u32; 3855 struct cvmx_sriomaintx_port_0_link_resp_s 3856 { 3857#if __BYTE_ORDER == __BIG_ENDIAN 3858 uint32_t valid : 1; /**< Link Response Valid. 3859 1 = Link Response Received or Reset Device 3860 Symbols Transmitted. Value cleared on read. 3861 0 = No response received. */ 3862 uint32_t reserved_11_30 : 20; 3863 uint32_t ackid : 6; /**< AckID received from link response. 3864 Reset Device symbol response is always zero. 3865 Bit 10 is used for IDLE2 and always reads zero. */ 3866 uint32_t status : 5; /**< Link Response Status. 3867 Status supplied by link response. 3868 Reset Device symbol response is always zero. */ 3869#else 3870 uint32_t status : 5; 3871 uint32_t ackid : 6; 3872 uint32_t reserved_11_30 : 20; 3873 uint32_t valid : 1; 3874#endif 3875 } s; 3876 struct cvmx_sriomaintx_port_0_link_resp_s cn63xx; 3877}; 3878typedef union cvmx_sriomaintx_port_0_link_resp cvmx_sriomaintx_port_0_link_resp_t; 3879 3880/** 3881 * cvmx_sriomaint#_port_0_local_ackid 3882 * 3883 * SRIOMAINT_PORT_0_LOCAL_ACKID = SRIO Port 0 Local AckID (Pass 2) 3884 * 3885 * Port 0 Local AckID Control 3886 * 3887 * Notes: 3888 * This register is typically only written when recovering from a failed link. It may be read at any 3889 * time the MAC is out of reset. Writes to the O_ACKID field will be used for both the O_ACKID and 3890 * E_ACKID. Care must be taken to ensure that no packets are pending at the time of a write. The 3891 * number of pending packets can be read in the TX_INUSE field of SRIO(0..1)_MAC_BUFFERS. 3892 * 3893 * Clk_Rst: SRIOMAINT(0..1)_PORT_0_LOCAL_ACKID hclk hrst_n 3894 */ 3895union cvmx_sriomaintx_port_0_local_ackid 3896{ 3897 uint32_t u32; 3898 struct cvmx_sriomaintx_port_0_local_ackid_s 3899 { 3900#if __BYTE_ORDER == __BIG_ENDIAN 3901 uint32_t reserved_30_31 : 2; 3902 uint32_t i_ackid : 6; /**< Next Expected Inbound AckID. 3903 Bit 29 is used for IDLE2 and should be zero. */ 3904 uint32_t reserved_14_23 : 10; 3905 uint32_t e_ackid : 6; /**< Next Expected Unacknowledged AckID. 3906 Bit 13 is used for IDLE2 and should be zero. */ 3907 uint32_t reserved_6_7 : 2; 3908 uint32_t o_ackid : 6; /**< Next Outgoing Packet AckID. 3909 Bit 5 is used for IDLE2 and should be zero. */ 3910#else 3911 uint32_t o_ackid : 6; 3912 uint32_t reserved_6_7 : 2; 3913 uint32_t e_ackid : 6; 3914 uint32_t reserved_14_23 : 10; 3915 uint32_t i_ackid : 6; 3916 uint32_t reserved_30_31 : 2; 3917#endif 3918 } s; 3919 struct cvmx_sriomaintx_port_0_local_ackid_s cn63xx; 3920}; 3921typedef union cvmx_sriomaintx_port_0_local_ackid cvmx_sriomaintx_port_0_local_ackid_t; 3922 3923/** 3924 * cvmx_sriomaint#_port_gen_ctl 3925 * 3926 * SRIOMAINT_PORT_GEN_CTL = SRIO Port General Control 3927 * 3928 * Port General Control 3929 * 3930 * Notes: 3931 * Clk_Rst: SRIOMAINT(0..1)_PORT_GEN_CTL hclk hrst_n 3932 * 3933 */ 3934union cvmx_sriomaintx_port_gen_ctl 3935{ 3936 uint32_t u32; 3937 struct cvmx_sriomaintx_port_gen_ctl_s 3938 { 3939#if __BYTE_ORDER == __BIG_ENDIAN 3940 uint32_t host : 1; /**< Host Device. 3941 The HOST reset value is based on corresponding 3942 MIO_RST_CTL*[PRTMODE], whose reset value is 3943 selected by the corresponding QLM*_HOST_MODE strap 3944 on a chip cold reset (and can be later modified by 3945 software). HOST resets to 1 when 3946 MIO_RST_CTL*[PRTMODE] selects RC (i.e. host) mode, 3947 else 0. */ 3948 uint32_t menable : 1; /**< Master Enable. Must be set for device to issue 3949 read, write, doorbell, message requests. */ 3950 uint32_t discover : 1; /**< Discovered. The device has been discovered by the 3951 host responsible for initialization. */ 3952 uint32_t reserved_0_28 : 29; 3953#else 3954 uint32_t reserved_0_28 : 29; 3955 uint32_t discover : 1; 3956 uint32_t menable : 1; 3957 uint32_t host : 1; 3958#endif 3959 } s; 3960 struct cvmx_sriomaintx_port_gen_ctl_s cn63xx; 3961 struct cvmx_sriomaintx_port_gen_ctl_s cn63xxp1; 3962}; 3963typedef union cvmx_sriomaintx_port_gen_ctl cvmx_sriomaintx_port_gen_ctl_t; 3964 3965/** 3966 * cvmx_sriomaint#_port_lt_ctl 3967 * 3968 * SRIOMAINT_PORT_LT_CTL = SRIO Link Layer Timeout Control 3969 * 3970 * Link Layer Timeout Control 3971 * 3972 * Notes: 3973 * This register controls the timeout for link layer transactions. It is used as the timeout between 3974 * sending a packet (of any type) or link request to receiving the corresponding link acknowledge or 3975 * link-response. Each count represents 200ns. The minimum timeout period is the TIMEOUT x 200nS 3976 * and the maximum is twice that number. A value less than 32 may not guarantee that all timeout 3977 * errors will be reported correctly. When the timeout period expires the packet or link request is 3978 * dropped and the error is logged in the LNK_TOUT field of the SRIOMAINT(0..1)_ERB_ERR_DET register. A 3979 * value of 0 in this register will allow the packet or link request to be issued but it will timeout 3980 * immediately. This value is not recommended for normal operation. 3981 * 3982 * Clk_Rst: SRIOMAINT(0..1)_PORT_LT_CTL hclk hrst_n 3983 */ 3984union cvmx_sriomaintx_port_lt_ctl 3985{ 3986 uint32_t u32; 3987 struct cvmx_sriomaintx_port_lt_ctl_s 3988 { 3989#if __BYTE_ORDER == __BIG_ENDIAN 3990 uint32_t timeout : 24; /**< Timeout Value */ 3991 uint32_t reserved_0_7 : 8; 3992#else 3993 uint32_t reserved_0_7 : 8; 3994 uint32_t timeout : 24; 3995#endif 3996 } s; 3997 struct cvmx_sriomaintx_port_lt_ctl_s cn63xx; 3998 struct cvmx_sriomaintx_port_lt_ctl_s cn63xxp1; 3999}; 4000typedef union cvmx_sriomaintx_port_lt_ctl cvmx_sriomaintx_port_lt_ctl_t; 4001 4002/** 4003 * cvmx_sriomaint#_port_mbh0 4004 * 4005 * SRIOMAINT_PORT_MBH0 = SRIO Port Maintenance Block Header 0 4006 * 4007 * Port Maintenance Block Header 0 4008 * 4009 * Notes: 4010 * Clk_Rst: SRIOMAINT(0..1)_PORT_MBH0 hclk hrst_n 4011 * 4012 */ 4013union cvmx_sriomaintx_port_mbh0 4014{ 4015 uint32_t u32; 4016 struct cvmx_sriomaintx_port_mbh0_s 4017 { 4018#if __BYTE_ORDER == __BIG_ENDIAN 4019 uint32_t ef_ptr : 16; /**< Pointer to Error Management Block. */ 4020 uint32_t ef_id : 16; /**< Extended Feature ID (Generic Endpoint Device) */ 4021#else 4022 uint32_t ef_id : 16; 4023 uint32_t ef_ptr : 16; 4024#endif 4025 } s; 4026 struct cvmx_sriomaintx_port_mbh0_s cn63xx; 4027 struct cvmx_sriomaintx_port_mbh0_s cn63xxp1; 4028}; 4029typedef union cvmx_sriomaintx_port_mbh0 cvmx_sriomaintx_port_mbh0_t; 4030 4031/** 4032 * cvmx_sriomaint#_port_rt_ctl 4033 * 4034 * SRIOMAINT_PORT_RT_CTL = SRIO Logical Layer Timeout Control 4035 * 4036 * Logical Layer Timeout Control 4037 * 4038 * Notes: 4039 * This register controls the timeout for logical layer transactions. It is used under two 4040 * conditions. First, it is used as the timeout period between sending a packet requiring a packet 4041 * response being sent to receiving the corresponding response. This is used for all outgoing packet 4042 * types including memory, maintenance, doorbells and message operations. When the timeout period 4043 * expires the packet is disgarded and the error is logged in the PKT_TOUT field of the 4044 * SRIOMAINT(0..1)_ERB_LT_ERR_DET register. The second use of this register is as a timeout period 4045 * between incoming message segments of the same message. If a message segment is received then the 4046 * MSG_TOUT field of the SRIOMAINT(0..1)_ERB_LT_ERR_DET register is set if the next segment has not been 4047 * received before the time expires. In both cases, each count represents 200ns. The minimum 4048 * timeout period is the TIMEOUT x 200nS and the maximum is twice that number. A value less than 32 4049 * may not guarantee that all timeout errors will be reported correctly. A value of 0 disables the 4050 * logical layer timeouts and is not recommended for normal operation. 4051 * 4052 * Clk_Rst: SRIOMAINT(0..1)_PORT_RT_CTL hclk hrst_n 4053 */ 4054union cvmx_sriomaintx_port_rt_ctl 4055{ 4056 uint32_t u32; 4057 struct cvmx_sriomaintx_port_rt_ctl_s 4058 { 4059#if __BYTE_ORDER == __BIG_ENDIAN 4060 uint32_t timeout : 24; /**< Timeout Value */ 4061 uint32_t reserved_0_7 : 8; 4062#else 4063 uint32_t reserved_0_7 : 8; 4064 uint32_t timeout : 24; 4065#endif 4066 } s; 4067 struct cvmx_sriomaintx_port_rt_ctl_s cn63xx; 4068 struct cvmx_sriomaintx_port_rt_ctl_s cn63xxp1; 4069}; 4070typedef union cvmx_sriomaintx_port_rt_ctl cvmx_sriomaintx_port_rt_ctl_t; 4071 4072/** 4073 * cvmx_sriomaint#_port_ttl_ctl 4074 * 4075 * SRIOMAINT_PORT_TTL_CTL = SRIO Packet Time to Live Control (Pass 2) 4076 * 4077 * Packet Time to Live 4078 * 4079 * Notes: 4080 * This register controls the timeout for outgoing packets. It is used to make sure packets are 4081 * being transmitted and acknowledged within a reasonable period of time. The timeout value 4082 * corresponds to TIMEOUT x 200ns and a value of 0 disables the timer. The actualy value of the 4083 * should be greater than the physical layer timout specified in SRIOMAINT(0..1)_PORT_LT_CTL and is 4084 * typically a less SRIOMAINT(0..1)_PORT_LT_CTL timeout than the response timeout specified in 4085 * SRIOMAINT(0..1)_PORT_RT_CTL. When the timeout expires the TTL interrupt is asserted, any packets 4086 * currently being transmitted are dropped, the SRIOMAINT(0..1)_TX_DROP.DROP bit is set (causing any 4087 * scheduled packets to be dropped), the SRIOMAINT(0..1)_TX_DROP.DROP_CNT is incremented and the SRIO 4088 * output state is set to IDLE (all errors are cleared). Software must clear the 4089 * SRIOMAINT(0..1)_TX_DROP.DROP bit to resume transmitting packets. 4090 * 4091 * Clk_Rst: SRIOMAINT(0..1)_PORT_RT_CTL hclk hrst_n 4092 */ 4093union cvmx_sriomaintx_port_ttl_ctl 4094{ 4095 uint32_t u32; 4096 struct cvmx_sriomaintx_port_ttl_ctl_s 4097 { 4098#if __BYTE_ORDER == __BIG_ENDIAN 4099 uint32_t timeout : 24; /**< Timeout Value */ 4100 uint32_t reserved_0_7 : 8; 4101#else 4102 uint32_t reserved_0_7 : 8; 4103 uint32_t timeout : 24; 4104#endif 4105 } s; 4106 struct cvmx_sriomaintx_port_ttl_ctl_s cn63xx; 4107}; 4108typedef union cvmx_sriomaintx_port_ttl_ctl cvmx_sriomaintx_port_ttl_ctl_t; 4109 4110/** 4111 * cvmx_sriomaint#_pri_dev_id 4112 * 4113 * SRIOMAINT_PRI_DEV_ID = SRIO Primary Device ID 4114 * 4115 * Primary 8 and 16 bit Device IDs 4116 * 4117 * Notes: 4118 * This register defines the primary 8 and 16 bit device IDs used for large and small transport. An 4119 * optional secondary set of device IDs are located in SRIOMAINT(0..1)_SEC_DEV_ID. 4120 * 4121 * Clk_Rst: SRIOMAINT(0..1)_PRI_DEV_ID hclk hrst_n 4122 */ 4123union cvmx_sriomaintx_pri_dev_id 4124{ 4125 uint32_t u32; 4126 struct cvmx_sriomaintx_pri_dev_id_s 4127 { 4128#if __BYTE_ORDER == __BIG_ENDIAN 4129 uint32_t reserved_24_31 : 8; 4130 uint32_t id8 : 8; /**< Primary 8-bit Device ID */ 4131 uint32_t id16 : 16; /**< Primary 16-bit Device ID */ 4132#else 4133 uint32_t id16 : 16; 4134 uint32_t id8 : 8; 4135 uint32_t reserved_24_31 : 8; 4136#endif 4137 } s; 4138 struct cvmx_sriomaintx_pri_dev_id_s cn63xx; 4139 struct cvmx_sriomaintx_pri_dev_id_s cn63xxp1; 4140}; 4141typedef union cvmx_sriomaintx_pri_dev_id cvmx_sriomaintx_pri_dev_id_t; 4142 4143/** 4144 * cvmx_sriomaint#_sec_dev_ctrl 4145 * 4146 * SRIOMAINT_SEC_DEV_CTRL = SRIO Secondary Device ID Control 4147 * 4148 * Control for Secondary Device IDs 4149 * 4150 * Notes: 4151 * This register enables the secondary 8 and 16 bit device IDs used for large and small transport. 4152 * The corresponding secondary ID must be written before the ID is enabled. The secondary IDs should 4153 * not be enabled if the values of the primary and secondary IDs are identical. 4154 * 4155 * Clk_Rst: SRIOMAINT(0..1)_SEC_DEV_CTRL hclk hrst_n 4156 */ 4157union cvmx_sriomaintx_sec_dev_ctrl 4158{ 4159 uint32_t u32; 4160 struct cvmx_sriomaintx_sec_dev_ctrl_s 4161 { 4162#if __BYTE_ORDER == __BIG_ENDIAN 4163 uint32_t reserved_2_31 : 30; 4164 uint32_t enable8 : 1; /**< Enable matches to secondary 8-bit Device ID */ 4165 uint32_t enable16 : 1; /**< Enable matches to secondary 16-bit Device ID */ 4166#else 4167 uint32_t enable16 : 1; 4168 uint32_t enable8 : 1; 4169 uint32_t reserved_2_31 : 30; 4170#endif 4171 } s; 4172 struct cvmx_sriomaintx_sec_dev_ctrl_s cn63xx; 4173 struct cvmx_sriomaintx_sec_dev_ctrl_s cn63xxp1; 4174}; 4175typedef union cvmx_sriomaintx_sec_dev_ctrl cvmx_sriomaintx_sec_dev_ctrl_t; 4176 4177/** 4178 * cvmx_sriomaint#_sec_dev_id 4179 * 4180 * SRIOMAINT_SEC_DEV_ID = SRIO Secondary Device ID 4181 * 4182 * Secondary 8 and 16 bit Device IDs 4183 * 4184 * Notes: 4185 * This register defines the secondary 8 and 16 bit device IDs used for large and small transport. 4186 * The corresponding secondary ID must be written before the ID is enabled in the 4187 * SRIOMAINT(0..1)_SEC_DEV_CTRL register. The primary set of device IDs are located in 4188 * SRIOMAINT(0..1)_PRI_DEV_ID register. The secondary IDs should not be written to the same values as the 4189 * corresponding primary IDs. 4190 * 4191 * Clk_Rst: SRIOMAINT(0..1)_SEC_DEV_ID hclk hrst_n 4192 */ 4193union cvmx_sriomaintx_sec_dev_id 4194{ 4195 uint32_t u32; 4196 struct cvmx_sriomaintx_sec_dev_id_s 4197 { 4198#if __BYTE_ORDER == __BIG_ENDIAN 4199 uint32_t reserved_24_31 : 8; 4200 uint32_t id8 : 8; /**< Secondary 8-bit Device ID */ 4201 uint32_t id16 : 16; /**< Secondary 16-bit Device ID */ 4202#else 4203 uint32_t id16 : 16; 4204 uint32_t id8 : 8; 4205 uint32_t reserved_24_31 : 8; 4206#endif 4207 } s; 4208 struct cvmx_sriomaintx_sec_dev_id_s cn63xx; 4209 struct cvmx_sriomaintx_sec_dev_id_s cn63xxp1; 4210}; 4211typedef union cvmx_sriomaintx_sec_dev_id cvmx_sriomaintx_sec_dev_id_t; 4212 4213/** 4214 * cvmx_sriomaint#_serial_lane_hdr 4215 * 4216 * SRIOMAINT_SERIAL_LANE_HDR = SRIO Serial Lane Header 4217 * 4218 * SRIO Serial Lane Header 4219 * 4220 * Notes: 4221 * The error management extensions block header register contains the EF_PTR to the next EF_BLK and 4222 * the EF_ID that identifies this as the Serial Lane Status Block. 4223 * 4224 * Clk_Rst: SRIOMAINT(0..1)_SERIAL_LANE_HDR hclk hrst_n 4225 */ 4226union cvmx_sriomaintx_serial_lane_hdr 4227{ 4228 uint32_t u32; 4229 struct cvmx_sriomaintx_serial_lane_hdr_s 4230 { 4231#if __BYTE_ORDER == __BIG_ENDIAN 4232 uint32_t ef_ptr : 16; /**< Pointer to the next block in the extended features 4233 data structure. */ 4234 uint32_t ef_id : 16; 4235#else 4236 uint32_t ef_id : 16; 4237 uint32_t ef_ptr : 16; 4238#endif 4239 } s; 4240 struct cvmx_sriomaintx_serial_lane_hdr_s cn63xx; 4241 struct cvmx_sriomaintx_serial_lane_hdr_s cn63xxp1; 4242}; 4243typedef union cvmx_sriomaintx_serial_lane_hdr cvmx_sriomaintx_serial_lane_hdr_t; 4244 4245/** 4246 * cvmx_sriomaint#_src_ops 4247 * 4248 * SRIOMAINT_SRC_OPS = SRIO Source Operations 4249 * 4250 * The logical operations initiated by the Octeon. 4251 * 4252 * Notes: 4253 * The logical operations initiated by the Cores. The Source OPs register shows the operations 4254 * specified in the SRIO(0..1)_IP_FEATURE.OPS register. 4255 * 4256 * Clk_Rst: SRIOMAINT(0..1)_SRC_OPS hclk hrst_n 4257 */ 4258union cvmx_sriomaintx_src_ops 4259{ 4260 uint32_t u32; 4261 struct cvmx_sriomaintx_src_ops_s 4262 { 4263#if __BYTE_ORDER == __BIG_ENDIAN 4264 uint32_t gsm_read : 1; /**< PE does not support Read Home operations. 4265 This is a RO copy of SRIO*_IP_FEATURE[OPS<31>] */ 4266 uint32_t i_read : 1; /**< PE does not support Instruction Read. 4267 This is a RO copy of SRIO*_IP_FEATURE[OPS<30>] */ 4268 uint32_t rd_own : 1; /**< PE does not support Read for Ownership. 4269 This is a RO copy of SRIO*_IP_FEATURE[OPS<29>] */ 4270 uint32_t d_invald : 1; /**< PE does not support Data Cache Invalidate. 4271 This is a RO copy of SRIO*_IP_FEATURE[OPS<28>] */ 4272 uint32_t castout : 1; /**< PE does not support Castout Operations. 4273 This is a RO copy of SRIO*_IP_FEATURE[OPS<27>] */ 4274 uint32_t d_flush : 1; /**< PE does not support Data Cache Flush. 4275 This is a RO copy of SRIO*_IP_FEATURE[OPS<26>] */ 4276 uint32_t io_read : 1; /**< PE does not support IO Read. 4277 This is a RO copy of SRIO*_IP_FEATURE[OPS<25>] */ 4278 uint32_t i_invald : 1; /**< PE does not support Instruction Cache Invalidate. 4279 This is a RO copy of SRIO*_IP_FEATURE[OPS<24>] */ 4280 uint32_t tlb_inv : 1; /**< PE does not support TLB Entry Invalidate. 4281 This is a RO copy of SRIO*_IP_FEATURE[OPS<23>] */ 4282 uint32_t tlb_invs : 1; /**< PE does not support TLB Entry Invalidate Sync. 4283 This is a RO copy of SRIO*_IP_FEATURE[OPS<22>] */ 4284 uint32_t reserved_16_21 : 6; 4285 uint32_t read : 1; /**< PE can support Nread operations. 4286 This is a RO copy of SRIO*_IP_FEATURE[OPS<15>] */ 4287 uint32_t write : 1; /**< PE can support Nwrite operations. 4288 This is a RO copy of SRIO*_IP_FEATURE[OPS<14>] */ 4289 uint32_t swrite : 1; /**< PE can support Swrite operations. 4290 This is a RO copy of SRIO*_IP_FEATURE[OPS<13>] */ 4291 uint32_t write_r : 1; /**< PE can support Write with Response operations. 4292 This is a RO copy of SRIO*_IP_FEATURE[OPS<12>] */ 4293 uint32_t msg : 1; /**< PE can support Data Message operations. 4294 This is a RO copy of SRIO*_IP_FEATURE[OPS<11>] */ 4295 uint32_t doorbell : 1; /**< PE can support Doorbell operations. 4296 This is a RO copy of SRIO*_IP_FEATURE[OPS<10>] */ 4297 uint32_t compswap : 1; /**< PE does not support Atomic Compare and Swap. 4298 This is a RO copy of SRIO*_IP_FEATURE[OPS<9>] */ 4299 uint32_t testswap : 1; /**< PE does not support Atomic Test and Swap. 4300 This is a RO copy of SRIO*_IP_FEATURE[OPS<8>] */ 4301 uint32_t atom_inc : 1; /**< PE can support Atomic increment operations. 4302 This is a RO copy of SRIO*_IP_FEATURE[OPS<7>] */ 4303 uint32_t atom_dec : 1; /**< PE can support Atomic decrement operations. 4304 This is a RO copy of SRIO*_IP_FEATURE[OPS<6>] */ 4305 uint32_t atom_set : 1; /**< PE can support Atomic set operations. 4306 This is a RO copy of SRIO*_IP_FEATURE[OPS<5>] */ 4307 uint32_t atom_clr : 1; /**< PE can support Atomic clear operations. 4308 This is a RO copy of SRIO*_IP_FEATURE[OPS<4>] */ 4309 uint32_t atom_swp : 1; /**< PE does not support Atomic Swap. 4310 This is a RO copy of SRIO*_IP_FEATURE[OPS<3>] */ 4311 uint32_t port_wr : 1; /**< PE can Port Write operations. 4312 This is a RO copy of SRIO*_IP_FEATURE[OPS<2>] */ 4313 uint32_t reserved_0_1 : 2; 4314#else 4315 uint32_t reserved_0_1 : 2; 4316 uint32_t port_wr : 1; 4317 uint32_t atom_swp : 1; 4318 uint32_t atom_clr : 1; 4319 uint32_t atom_set : 1; 4320 uint32_t atom_dec : 1; 4321 uint32_t atom_inc : 1; 4322 uint32_t testswap : 1; 4323 uint32_t compswap : 1; 4324 uint32_t doorbell : 1; 4325 uint32_t msg : 1; 4326 uint32_t write_r : 1; 4327 uint32_t swrite : 1; 4328 uint32_t write : 1; 4329 uint32_t read : 1; 4330 uint32_t reserved_16_21 : 6; 4331 uint32_t tlb_invs : 1; 4332 uint32_t tlb_inv : 1; 4333 uint32_t i_invald : 1; 4334 uint32_t io_read : 1; 4335 uint32_t d_flush : 1; 4336 uint32_t castout : 1; 4337 uint32_t d_invald : 1; 4338 uint32_t rd_own : 1; 4339 uint32_t i_read : 1; 4340 uint32_t gsm_read : 1; 4341#endif 4342 } s; 4343 struct cvmx_sriomaintx_src_ops_s cn63xx; 4344 struct cvmx_sriomaintx_src_ops_s cn63xxp1; 4345}; 4346typedef union cvmx_sriomaintx_src_ops cvmx_sriomaintx_src_ops_t; 4347 4348/** 4349 * cvmx_sriomaint#_tx_drop 4350 * 4351 * SRIOMAINT_TX_DROP = SRIO MAC Outgoing Packet Drop (Pass 2) 4352 * 4353 * Outging SRIO Packet Drop Control/Status 4354 * 4355 * Notes: 4356 * This register controls and provides status for dropping outgoing SRIO packets. The DROP bit 4357 * should only be cleared when no packets are currently being dropped. This can be guaranteed by 4358 * clearing the SRIOMAINT(0..1)_PORT_0_CTL.O_ENABLE bit before changing the DROP bit and restoring the 4359 * O_ENABLE afterwards. 4360 * 4361 * Clk_Rst: SRIOMAINT(0..1)_MAC_CTRL hclk hrst_n 4362 */ 4363union cvmx_sriomaintx_tx_drop 4364{ 4365 uint32_t u32; 4366 struct cvmx_sriomaintx_tx_drop_s 4367 { 4368#if __BYTE_ORDER == __BIG_ENDIAN 4369 uint32_t reserved_17_31 : 15; 4370 uint32_t drop : 1; /**< All outgoing packets are dropped. Any packets 4371 requiring a response will return 1's after the 4372 SRIOMAINT(0..1)_PORT_RT_CTL Timeout expires. This bit 4373 is set automatically when the TTL Timeout occurs 4374 or can be set by software and must always be 4375 cleared by software. */ 4376 uint32_t drop_cnt : 16; /**< Number of packets dropped by transmit logic. 4377 Packets are dropped whenever a packet is ready to 4378 be transmitted and a TTL Timeouts occur, the DROP 4379 bit is set or the SRIOMAINT(0..1)_ERB_ERR_RATE_THR 4380 FAIL_TH has been reached and the DROP_PKT bit is 4381 set in SRIOMAINT(0..1)_PORT_0_CTL. */ 4382#else 4383 uint32_t drop_cnt : 16; 4384 uint32_t drop : 1; 4385 uint32_t reserved_17_31 : 15; 4386#endif 4387 } s; 4388 struct cvmx_sriomaintx_tx_drop_s cn63xx; 4389}; 4390typedef union cvmx_sriomaintx_tx_drop cvmx_sriomaintx_tx_drop_t; 4391 4392#endif 4393