1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * Interface to RAID block. This is not available on all chips. 50 * 51 * <hr>$Revision: 49448 $<hr> 52 */ 53 54#ifndef __CVMX_RAID_H__ 55#define __CVMX_RAID_H__ 56 57#ifdef __cplusplus 58extern "C" { 59#endif 60 61/** 62 * This structure defines the type of command words the RAID block 63 * will accept. 64 */ 65typedef union 66{ 67 uint64_t u64; 68 struct 69 { 70 uint64_t reserved_37_63 : 27; /**< Must be zero */ 71 uint64_t q_cmp : 1; /**< Indicates whether the Q pipe is in normal mode (CWORD[Q_CMP]=0) or in non-zero 72 byte detect mode (CWORD[Q_CMP]=1). 73 In non-zero byte detect mode, the Q OWORD[PTR] result is the non-zero detect 74 result, which indicates the position of the first non-zero byte in the pipe result bytes. 75 CWORD[Q_CMP] must not be set when CWORD[QOUT]=0, and must not be set 76 when CWORD[Q_XOR] is set. */ 77 uint64_t p_cmp : 1; /**< Indicates whether the P pipe is in normal mode (CWORD[P_CMP]=0) or in non-zero 78 byte detect mode (CWORD[P_CMP]=1). 79 In non-zero byte detect mode, the P OWORD[PTR] result is the non-zero detect 80 result, which indicates the position of the first non-zero byte in the pipe result bytes. 81 CWORD[P_CMP] must not be set when CWORD[POUT]=0, and must not be set 82 when CWORD[P_XOR] is set. */ 83 uint64_t q_xor : 1; /**< Indicates whether the Q output buffer bytes are the normal Q pipe result or the 84 normal Q pipe result exclusive-OR'ed with the P pipe result. 85 When CWORD[Q_XOR]=0 (and CWORD[Q_CMP]=0), the Q output buffer bytes are 86 the normal Q pipe result, which does not include the P pipe result in any way. 87 When CWORD[Q_XOR]=1, the Q output buffer bytes are the normal Q pipe result 88 exclusive-OR'ed with the P pipe result, as if the P pipe result were another Q IWORD 89 for the Q pipe with QMULT=1. 90 CWORD[Q_XOR] must not be set unless both CWORD[POUT,QOUT] are set, and 91 must not be set when CWORD[Q_CMP] is set. */ 92 uint64_t p_xor : 1; /**< Indicates whether the P output buffer bytes are the normal P pipe result or the 93 normal P pipe result exclusive-OR'ed with the Q pipe result. 94 When CWORD[P_XOR]=0 (and CWORD[P_CMP]=0), the P output buffer bytes are 95 the normal P pipe result, which does not include the Q pipe result in any way. 96 When CWORD[P_XOR]=1, the P output buffer bytes are the normal P pipe result 97 exclusive-OR'ed with the Q pipe result, as if the Q pipe result were another P 98 IWORD for the P pipe. 99 CWORD[P_XOR] must not be set unless both CWORD[POUT,QOUT] are set, and 100 must not be set when CWORD[P_CMP] is set. */ 101 uint64_t wqe : 1; /**< Indicates whether RAD submits a work queue entry or writes an L2/DRAM byte to 102 zero after completing the instruction. 103 When CWORD[WQE] is set and RESP[PTR]!=0, RAD adds the work queue entry 104 indicated by RESP[PTR] to the selected POW input queue after completing the 105 instruction. 106 When CWORD[WQE] is clear and RESP[PTR]!=0, RAD writes the L2/DRAM byte 107 indicated by RESP[PTR] to zero after completing the instruction. */ 108 uint64_t qout : 1; /**< Indicates whether the Q pipe is used by this instruction. 109 If CWORD[QOUT] is set, IWORD[QEN] must be set for at least one IWORD. 110 At least one of CWORD[QOUT,POUT] must be set. */ 111 uint64_t pout : 1; /**< Indicates whether the P pipe is used by this instruction. 112 If CWORD[POUT] is set, IWORD[PEN] must be set for at least one IWORD. 113 At least one of CWORD[QOUT,POUT] must be set. */ 114 uint64_t iword : 6; /**< Indicates the number of input buffers used. 115 1 <= CWORD[IWORD] <= 32. */ 116 uint64_t size : 24; /**< Indicates the size in bytes of all input buffers. When CWORD[Q_CMP,P_CMP]=0, 117 also indicates the size of the Q/P output buffers. 118 CWORD[SIZE] must be a multiple of 8B (i.e. <2:0> must be zero). */ 119 } cword; 120 struct 121 { 122 uint64_t reserved_58_63 : 6; /**< Must be zero */ 123 uint64_t fw : 1; /**< When set, indicates that RAD can modify any byte in any (128B) cache line touched 124 by L2/DRAM addresses OWORD[PTR] through OWORD[PTR]+CWORD[SIZE]�1. 125 Setting OWORD[FW] can improve hardware performance, as some DRAM loads can 126 be avoided on L2 cache misses. The Q OWORD[FW] must not be set when 127 CWORD[Q_CMP] is set, and the P OWORD[FW] must not be set when 128 CWORD[P_CMP] is set. */ 129 uint64_t nc : 1; /**< When set, indicates that RAD should not allocate L2 cache space for the P/Q data on 130 L2 cache misses. 131 OWORD[NC] should typically be clear, though setting OWORD[NC] can improve 132 performance in some circumstances, as the L2 cache will not be polluted by P/Q data. 133 The Q OWORD[NC] must not be set when CWORD[Q_CMP] is set, and the P 134 OWORD[NC] must not be set when CWORD[P_CMP] is set. */ 135 uint64_t reserved_40_55 : 16; /**< Must be zero */ 136 uint64_t addr : 40; /**< When CWORD[P_CMP,Q_CMP]=0, OWORD[PTR] indicates the starting address of 137 the L2/DRAM buffer that will receive the P/Q data. In the non-compare mode, the 138 output buffer receives all of the output buffer bytes. 139 When CWORD[P_CMP,Q_CMP]=1, the corresponding P/Q pipe is in compare mode, 140 and the only output of the pipe is the non-zero detect result. In this case, 141 OWORD[PTR] indicates the 8-byte location of the non-zero detect result. */ 142 } oword; 143 struct 144 { 145 uint64_t reserved_57_63 : 7; /**< Must be zero */ 146 uint64_t nc : 1; /**< When set, indicates that RAD should not allocate L2 cache space for this input buffer 147 data on L2 cache misses. 148 Setting IWORD[NC] may improve performance in some circumstances, as the L2 149 cache may not be polluted with input buffer data. */ 150 uint64_t reserved_50_55 : 6; /**< Must be zero */ 151 uint64_t qen : 1; /**< Indicates that this input buffer data should participate in the Q pipe result. 152 The Q pipe hardware multiplies each participating input byte by IWORD[QMULT] 153 before accumulating them by exclusive-OR'ing. 154 IWORD[QEN] must not be set when CWORD[QOUT] is not set. 155 If CWORD[QOUT] is set, IWORD[QEN] must be set for at least one IWORD. */ 156 uint64_t pen : 1; /**< Indicates that this input buffer data should participate in the P pipe result. 157 The P pipe hardware accumulates each participating input byte by bit-wise 158 exclusive-OR'ing it. 159 IWORD[PEN] must not be set when CWORD[POUT] is not set. 160 If CWORD[POUT] is set, IWORD[PEN] must be set for at least one IWORD. */ 161 uint64_t qmult : 8; /**< The Q pipe multiplier for the input buffer. Section 26.1 above describes the GF(28) 162 multiplication algorithm. 163 IWORD[QMULT] must be zero when IWORD[QEN] is not set. 164 IWORD[QMULT] must not be zero when IWORD[QEN] is set. 165 When IWORD[QMULT] is 1, the multiplication simplifies to the identity function, 166 and the Q pipe performs the same XOR function as the P pipe. */ 167 uint64_t addr : 40; /**< The starting address of the input buffer in L2/DRAM. 168 IWORD[PTR] must be naturally-aligned on an 8 byte boundary (i.e. <2:0> must be 169 zero). */ 170 } iword; 171} cvmx_raid_word_t; 172 173/** 174 * Initialize the RAID block 175 * 176 * @param polynomial Coefficients for the RAID polynomial 177 * 178 * @return Zero on success, negative on failure 179 */ 180int cvmx_raid_initialize(cvmx_rad_reg_polynomial_t polynomial); 181 182/** 183 * Shutdown the RAID block. RAID must be idle when 184 * this function is called. 185 * 186 * @return Zero on success, negative on failure 187 */ 188int cvmx_raid_shutdown(void); 189 190/** 191 * Submit a command to the RAID block 192 * 193 * @param num_words Number of command words to submit 194 * @param words Command words 195 * 196 * @return Zero on success, negative on failure 197 */ 198int cvmx_raid_submit(int num_words, cvmx_raid_word_t words[]); 199 200#ifdef __cplusplus 201} 202#endif 203 204#endif // __CVMX_CMD_QUEUE_H__ 205