1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pciercx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pciercx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_PCIERCX_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_PCIERCX_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG000(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 61215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 62215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG000(%lu) is invalid on this chip\n", block_id); 63215976Sjmallett return 0x0000000000000000ull; 64215976Sjmallett} 65215976Sjmallett#else 66215976Sjmallett#define CVMX_PCIERCX_CFG000(block_id) (0x0000000000000000ull) 67215976Sjmallett#endif 68215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG001(unsigned long block_id) 70215976Sjmallett{ 71215976Sjmallett if (!( 72215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 73215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 74215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 75215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG001(%lu) is invalid on this chip\n", block_id); 76215976Sjmallett return 0x0000000000000004ull; 77215976Sjmallett} 78215976Sjmallett#else 79215976Sjmallett#define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull) 80215976Sjmallett#endif 81215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG002(unsigned long block_id) 83215976Sjmallett{ 84215976Sjmallett if (!( 85215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 86215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 87215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 88215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG002(%lu) is invalid on this chip\n", block_id); 89215976Sjmallett return 0x0000000000000008ull; 90215976Sjmallett} 91215976Sjmallett#else 92215976Sjmallett#define CVMX_PCIERCX_CFG002(block_id) (0x0000000000000008ull) 93215976Sjmallett#endif 94215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 95215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG003(unsigned long block_id) 96215976Sjmallett{ 97215976Sjmallett if (!( 98215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 99215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 100215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 101215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG003(%lu) is invalid on this chip\n", block_id); 102215976Sjmallett return 0x000000000000000Cull; 103215976Sjmallett} 104215976Sjmallett#else 105215976Sjmallett#define CVMX_PCIERCX_CFG003(block_id) (0x000000000000000Cull) 106215976Sjmallett#endif 107215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 108215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG004(unsigned long block_id) 109215976Sjmallett{ 110215976Sjmallett if (!( 111215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 112215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 113215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 114215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG004(%lu) is invalid on this chip\n", block_id); 115215976Sjmallett return 0x0000000000000010ull; 116215976Sjmallett} 117215976Sjmallett#else 118215976Sjmallett#define CVMX_PCIERCX_CFG004(block_id) (0x0000000000000010ull) 119215976Sjmallett#endif 120215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 121215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG005(unsigned long block_id) 122215976Sjmallett{ 123215976Sjmallett if (!( 124215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 125215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 126215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 127215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG005(%lu) is invalid on this chip\n", block_id); 128215976Sjmallett return 0x0000000000000014ull; 129215976Sjmallett} 130215976Sjmallett#else 131215976Sjmallett#define CVMX_PCIERCX_CFG005(block_id) (0x0000000000000014ull) 132215976Sjmallett#endif 133215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 134215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG006(unsigned long block_id) 135215976Sjmallett{ 136215976Sjmallett if (!( 137215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 138215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 139215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 140215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG006(%lu) is invalid on this chip\n", block_id); 141215976Sjmallett return 0x0000000000000018ull; 142215976Sjmallett} 143215976Sjmallett#else 144215976Sjmallett#define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull) 145215976Sjmallett#endif 146215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 147215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG007(unsigned long block_id) 148215976Sjmallett{ 149215976Sjmallett if (!( 150215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 151215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 152215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 153215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG007(%lu) is invalid on this chip\n", block_id); 154215976Sjmallett return 0x000000000000001Cull; 155215976Sjmallett} 156215976Sjmallett#else 157215976Sjmallett#define CVMX_PCIERCX_CFG007(block_id) (0x000000000000001Cull) 158215976Sjmallett#endif 159215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 160215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG008(unsigned long block_id) 161215976Sjmallett{ 162215976Sjmallett if (!( 163215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 164215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 165215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 166215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG008(%lu) is invalid on this chip\n", block_id); 167215976Sjmallett return 0x0000000000000020ull; 168215976Sjmallett} 169215976Sjmallett#else 170215976Sjmallett#define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull) 171215976Sjmallett#endif 172215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 173215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG009(unsigned long block_id) 174215976Sjmallett{ 175215976Sjmallett if (!( 176215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 177215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 178215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 179215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG009(%lu) is invalid on this chip\n", block_id); 180215976Sjmallett return 0x0000000000000024ull; 181215976Sjmallett} 182215976Sjmallett#else 183215976Sjmallett#define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull) 184215976Sjmallett#endif 185215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 186215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG010(unsigned long block_id) 187215976Sjmallett{ 188215976Sjmallett if (!( 189215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 190215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 191215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 192215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG010(%lu) is invalid on this chip\n", block_id); 193215976Sjmallett return 0x0000000000000028ull; 194215976Sjmallett} 195215976Sjmallett#else 196215976Sjmallett#define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull) 197215976Sjmallett#endif 198215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG011(unsigned long block_id) 200215976Sjmallett{ 201215976Sjmallett if (!( 202215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 203215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 204215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 205215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG011(%lu) is invalid on this chip\n", block_id); 206215976Sjmallett return 0x000000000000002Cull; 207215976Sjmallett} 208215976Sjmallett#else 209215976Sjmallett#define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull) 210215976Sjmallett#endif 211215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG012(unsigned long block_id) 213215976Sjmallett{ 214215976Sjmallett if (!( 215215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 216215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 217215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 218215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG012(%lu) is invalid on this chip\n", block_id); 219215976Sjmallett return 0x0000000000000030ull; 220215976Sjmallett} 221215976Sjmallett#else 222215976Sjmallett#define CVMX_PCIERCX_CFG012(block_id) (0x0000000000000030ull) 223215976Sjmallett#endif 224215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 225215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG013(unsigned long block_id) 226215976Sjmallett{ 227215976Sjmallett if (!( 228215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 229215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 230215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 231215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG013(%lu) is invalid on this chip\n", block_id); 232215976Sjmallett return 0x0000000000000034ull; 233215976Sjmallett} 234215976Sjmallett#else 235215976Sjmallett#define CVMX_PCIERCX_CFG013(block_id) (0x0000000000000034ull) 236215976Sjmallett#endif 237215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 238215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG014(unsigned long block_id) 239215976Sjmallett{ 240215976Sjmallett if (!( 241215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 242215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 243215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 244215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG014(%lu) is invalid on this chip\n", block_id); 245215976Sjmallett return 0x0000000000000038ull; 246215976Sjmallett} 247215976Sjmallett#else 248215976Sjmallett#define CVMX_PCIERCX_CFG014(block_id) (0x0000000000000038ull) 249215976Sjmallett#endif 250215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG015(unsigned long block_id) 252215976Sjmallett{ 253215976Sjmallett if (!( 254215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 255215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 256215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 257215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG015(%lu) is invalid on this chip\n", block_id); 258215976Sjmallett return 0x000000000000003Cull; 259215976Sjmallett} 260215976Sjmallett#else 261215976Sjmallett#define CVMX_PCIERCX_CFG015(block_id) (0x000000000000003Cull) 262215976Sjmallett#endif 263215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 264215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG016(unsigned long block_id) 265215976Sjmallett{ 266215976Sjmallett if (!( 267215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 268215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 269215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 270215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG016(%lu) is invalid on this chip\n", block_id); 271215976Sjmallett return 0x0000000000000040ull; 272215976Sjmallett} 273215976Sjmallett#else 274215976Sjmallett#define CVMX_PCIERCX_CFG016(block_id) (0x0000000000000040ull) 275215976Sjmallett#endif 276215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 277215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG017(unsigned long block_id) 278215976Sjmallett{ 279215976Sjmallett if (!( 280215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 281215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 282215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 283215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG017(%lu) is invalid on this chip\n", block_id); 284215976Sjmallett return 0x0000000000000044ull; 285215976Sjmallett} 286215976Sjmallett#else 287215976Sjmallett#define CVMX_PCIERCX_CFG017(block_id) (0x0000000000000044ull) 288215976Sjmallett#endif 289215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 290215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG020(unsigned long block_id) 291215976Sjmallett{ 292215976Sjmallett if (!( 293215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 294215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 295215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 296215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG020(%lu) is invalid on this chip\n", block_id); 297215976Sjmallett return 0x0000000000000050ull; 298215976Sjmallett} 299215976Sjmallett#else 300215976Sjmallett#define CVMX_PCIERCX_CFG020(block_id) (0x0000000000000050ull) 301215976Sjmallett#endif 302215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 303215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG021(unsigned long block_id) 304215976Sjmallett{ 305215976Sjmallett if (!( 306215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 307215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 308215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 309215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG021(%lu) is invalid on this chip\n", block_id); 310215976Sjmallett return 0x0000000000000054ull; 311215976Sjmallett} 312215976Sjmallett#else 313215976Sjmallett#define CVMX_PCIERCX_CFG021(block_id) (0x0000000000000054ull) 314215976Sjmallett#endif 315215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 316215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG022(unsigned long block_id) 317215976Sjmallett{ 318215976Sjmallett if (!( 319215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 320215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 321215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 322215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG022(%lu) is invalid on this chip\n", block_id); 323215976Sjmallett return 0x0000000000000058ull; 324215976Sjmallett} 325215976Sjmallett#else 326215976Sjmallett#define CVMX_PCIERCX_CFG022(block_id) (0x0000000000000058ull) 327215976Sjmallett#endif 328215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 329215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG023(unsigned long block_id) 330215976Sjmallett{ 331215976Sjmallett if (!( 332215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 333215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 334215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 335215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG023(%lu) is invalid on this chip\n", block_id); 336215976Sjmallett return 0x000000000000005Cull; 337215976Sjmallett} 338215976Sjmallett#else 339215976Sjmallett#define CVMX_PCIERCX_CFG023(block_id) (0x000000000000005Cull) 340215976Sjmallett#endif 341215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG028(unsigned long block_id) 343215976Sjmallett{ 344215976Sjmallett if (!( 345215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 346215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 347215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 348215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG028(%lu) is invalid on this chip\n", block_id); 349215976Sjmallett return 0x0000000000000070ull; 350215976Sjmallett} 351215976Sjmallett#else 352215976Sjmallett#define CVMX_PCIERCX_CFG028(block_id) (0x0000000000000070ull) 353215976Sjmallett#endif 354215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 355215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG029(unsigned long block_id) 356215976Sjmallett{ 357215976Sjmallett if (!( 358215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 359215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 360215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 361215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG029(%lu) is invalid on this chip\n", block_id); 362215976Sjmallett return 0x0000000000000074ull; 363215976Sjmallett} 364215976Sjmallett#else 365215976Sjmallett#define CVMX_PCIERCX_CFG029(block_id) (0x0000000000000074ull) 366215976Sjmallett#endif 367215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 368215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG030(unsigned long block_id) 369215976Sjmallett{ 370215976Sjmallett if (!( 371215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 372215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 373215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 374215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG030(%lu) is invalid on this chip\n", block_id); 375215976Sjmallett return 0x0000000000000078ull; 376215976Sjmallett} 377215976Sjmallett#else 378215976Sjmallett#define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull) 379215976Sjmallett#endif 380215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 381215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG031(unsigned long block_id) 382215976Sjmallett{ 383215976Sjmallett if (!( 384215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 385215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 386215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 387215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG031(%lu) is invalid on this chip\n", block_id); 388215976Sjmallett return 0x000000000000007Cull; 389215976Sjmallett} 390215976Sjmallett#else 391215976Sjmallett#define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull) 392215976Sjmallett#endif 393215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 394215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG032(unsigned long block_id) 395215976Sjmallett{ 396215976Sjmallett if (!( 397215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 398215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 399215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 400215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG032(%lu) is invalid on this chip\n", block_id); 401215976Sjmallett return 0x0000000000000080ull; 402215976Sjmallett} 403215976Sjmallett#else 404215976Sjmallett#define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull) 405215976Sjmallett#endif 406215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 407215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG033(unsigned long block_id) 408215976Sjmallett{ 409215976Sjmallett if (!( 410215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 411215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 412215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 413215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG033(%lu) is invalid on this chip\n", block_id); 414215976Sjmallett return 0x0000000000000084ull; 415215976Sjmallett} 416215976Sjmallett#else 417215976Sjmallett#define CVMX_PCIERCX_CFG033(block_id) (0x0000000000000084ull) 418215976Sjmallett#endif 419215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 420215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG034(unsigned long block_id) 421215976Sjmallett{ 422215976Sjmallett if (!( 423215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 424215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 425215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 426215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG034(%lu) is invalid on this chip\n", block_id); 427215976Sjmallett return 0x0000000000000088ull; 428215976Sjmallett} 429215976Sjmallett#else 430215976Sjmallett#define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull) 431215976Sjmallett#endif 432215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 433215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG035(unsigned long block_id) 434215976Sjmallett{ 435215976Sjmallett if (!( 436215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 437215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 438215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 439215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG035(%lu) is invalid on this chip\n", block_id); 440215976Sjmallett return 0x000000000000008Cull; 441215976Sjmallett} 442215976Sjmallett#else 443215976Sjmallett#define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull) 444215976Sjmallett#endif 445215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 446215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG036(unsigned long block_id) 447215976Sjmallett{ 448215976Sjmallett if (!( 449215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 450215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 451215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 452215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG036(%lu) is invalid on this chip\n", block_id); 453215976Sjmallett return 0x0000000000000090ull; 454215976Sjmallett} 455215976Sjmallett#else 456215976Sjmallett#define CVMX_PCIERCX_CFG036(block_id) (0x0000000000000090ull) 457215976Sjmallett#endif 458215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 459215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG037(unsigned long block_id) 460215976Sjmallett{ 461215976Sjmallett if (!( 462215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 463215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 464215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 465215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG037(%lu) is invalid on this chip\n", block_id); 466215976Sjmallett return 0x0000000000000094ull; 467215976Sjmallett} 468215976Sjmallett#else 469215976Sjmallett#define CVMX_PCIERCX_CFG037(block_id) (0x0000000000000094ull) 470215976Sjmallett#endif 471215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 472215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG038(unsigned long block_id) 473215976Sjmallett{ 474215976Sjmallett if (!( 475215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 476215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 477215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 478215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG038(%lu) is invalid on this chip\n", block_id); 479215976Sjmallett return 0x0000000000000098ull; 480215976Sjmallett} 481215976Sjmallett#else 482215976Sjmallett#define CVMX_PCIERCX_CFG038(block_id) (0x0000000000000098ull) 483215976Sjmallett#endif 484215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG039(unsigned long block_id) 486215976Sjmallett{ 487215976Sjmallett if (!( 488215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 489215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 490215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 491215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG039(%lu) is invalid on this chip\n", block_id); 492215976Sjmallett return 0x000000000000009Cull; 493215976Sjmallett} 494215976Sjmallett#else 495215976Sjmallett#define CVMX_PCIERCX_CFG039(block_id) (0x000000000000009Cull) 496215976Sjmallett#endif 497215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 498215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG040(unsigned long block_id) 499215976Sjmallett{ 500215976Sjmallett if (!( 501215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 502215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 503215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 504215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG040(%lu) is invalid on this chip\n", block_id); 505215976Sjmallett return 0x00000000000000A0ull; 506215976Sjmallett} 507215976Sjmallett#else 508215976Sjmallett#define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull) 509215976Sjmallett#endif 510215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 511215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG041(unsigned long block_id) 512215976Sjmallett{ 513215976Sjmallett if (!( 514215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 515215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 516215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 517215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG041(%lu) is invalid on this chip\n", block_id); 518215976Sjmallett return 0x00000000000000A4ull; 519215976Sjmallett} 520215976Sjmallett#else 521215976Sjmallett#define CVMX_PCIERCX_CFG041(block_id) (0x00000000000000A4ull) 522215976Sjmallett#endif 523215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 524215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG042(unsigned long block_id) 525215976Sjmallett{ 526215976Sjmallett if (!( 527215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 528215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 529215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 530215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG042(%lu) is invalid on this chip\n", block_id); 531215976Sjmallett return 0x00000000000000A8ull; 532215976Sjmallett} 533215976Sjmallett#else 534215976Sjmallett#define CVMX_PCIERCX_CFG042(block_id) (0x00000000000000A8ull) 535215976Sjmallett#endif 536215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 537215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG064(unsigned long block_id) 538215976Sjmallett{ 539215976Sjmallett if (!( 540215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 541215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 542215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 543215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG064(%lu) is invalid on this chip\n", block_id); 544215976Sjmallett return 0x0000000000000100ull; 545215976Sjmallett} 546215976Sjmallett#else 547215976Sjmallett#define CVMX_PCIERCX_CFG064(block_id) (0x0000000000000100ull) 548215976Sjmallett#endif 549215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 550215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG065(unsigned long block_id) 551215976Sjmallett{ 552215976Sjmallett if (!( 553215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 554215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 555215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 556215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG065(%lu) is invalid on this chip\n", block_id); 557215976Sjmallett return 0x0000000000000104ull; 558215976Sjmallett} 559215976Sjmallett#else 560215976Sjmallett#define CVMX_PCIERCX_CFG065(block_id) (0x0000000000000104ull) 561215976Sjmallett#endif 562215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 563215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG066(unsigned long block_id) 564215976Sjmallett{ 565215976Sjmallett if (!( 566215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 567215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 568215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 569215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG066(%lu) is invalid on this chip\n", block_id); 570215976Sjmallett return 0x0000000000000108ull; 571215976Sjmallett} 572215976Sjmallett#else 573215976Sjmallett#define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull) 574215976Sjmallett#endif 575215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 576215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG067(unsigned long block_id) 577215976Sjmallett{ 578215976Sjmallett if (!( 579215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 580215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 581215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 582215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG067(%lu) is invalid on this chip\n", block_id); 583215976Sjmallett return 0x000000000000010Cull; 584215976Sjmallett} 585215976Sjmallett#else 586215976Sjmallett#define CVMX_PCIERCX_CFG067(block_id) (0x000000000000010Cull) 587215976Sjmallett#endif 588215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 589215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG068(unsigned long block_id) 590215976Sjmallett{ 591215976Sjmallett if (!( 592215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 593215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 594215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 595215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG068(%lu) is invalid on this chip\n", block_id); 596215976Sjmallett return 0x0000000000000110ull; 597215976Sjmallett} 598215976Sjmallett#else 599215976Sjmallett#define CVMX_PCIERCX_CFG068(block_id) (0x0000000000000110ull) 600215976Sjmallett#endif 601215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 602215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG069(unsigned long block_id) 603215976Sjmallett{ 604215976Sjmallett if (!( 605215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 606215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 607215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 608215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG069(%lu) is invalid on this chip\n", block_id); 609215976Sjmallett return 0x0000000000000114ull; 610215976Sjmallett} 611215976Sjmallett#else 612215976Sjmallett#define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull) 613215976Sjmallett#endif 614215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 615215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG070(unsigned long block_id) 616215976Sjmallett{ 617215976Sjmallett if (!( 618215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 619215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 620215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 621215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG070(%lu) is invalid on this chip\n", block_id); 622215976Sjmallett return 0x0000000000000118ull; 623215976Sjmallett} 624215976Sjmallett#else 625215976Sjmallett#define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull) 626215976Sjmallett#endif 627215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 628215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG071(unsigned long block_id) 629215976Sjmallett{ 630215976Sjmallett if (!( 631215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 632215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 633215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 634215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG071(%lu) is invalid on this chip\n", block_id); 635215976Sjmallett return 0x000000000000011Cull; 636215976Sjmallett} 637215976Sjmallett#else 638215976Sjmallett#define CVMX_PCIERCX_CFG071(block_id) (0x000000000000011Cull) 639215976Sjmallett#endif 640215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 641215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG072(unsigned long block_id) 642215976Sjmallett{ 643215976Sjmallett if (!( 644215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 645215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 646215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 647215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG072(%lu) is invalid on this chip\n", block_id); 648215976Sjmallett return 0x0000000000000120ull; 649215976Sjmallett} 650215976Sjmallett#else 651215976Sjmallett#define CVMX_PCIERCX_CFG072(block_id) (0x0000000000000120ull) 652215976Sjmallett#endif 653215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 654215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG073(unsigned long block_id) 655215976Sjmallett{ 656215976Sjmallett if (!( 657215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 658215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 659215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 660215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG073(%lu) is invalid on this chip\n", block_id); 661215976Sjmallett return 0x0000000000000124ull; 662215976Sjmallett} 663215976Sjmallett#else 664215976Sjmallett#define CVMX_PCIERCX_CFG073(block_id) (0x0000000000000124ull) 665215976Sjmallett#endif 666215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 667215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG074(unsigned long block_id) 668215976Sjmallett{ 669215976Sjmallett if (!( 670215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 671215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 672215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 673215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG074(%lu) is invalid on this chip\n", block_id); 674215976Sjmallett return 0x0000000000000128ull; 675215976Sjmallett} 676215976Sjmallett#else 677215976Sjmallett#define CVMX_PCIERCX_CFG074(block_id) (0x0000000000000128ull) 678215976Sjmallett#endif 679215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 680215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG075(unsigned long block_id) 681215976Sjmallett{ 682215976Sjmallett if (!( 683215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 684215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 685215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 686215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG075(%lu) is invalid on this chip\n", block_id); 687215976Sjmallett return 0x000000000000012Cull; 688215976Sjmallett} 689215976Sjmallett#else 690215976Sjmallett#define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull) 691215976Sjmallett#endif 692215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 693215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG076(unsigned long block_id) 694215976Sjmallett{ 695215976Sjmallett if (!( 696215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 697215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 698215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 699215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG076(%lu) is invalid on this chip\n", block_id); 700215976Sjmallett return 0x0000000000000130ull; 701215976Sjmallett} 702215976Sjmallett#else 703215976Sjmallett#define CVMX_PCIERCX_CFG076(block_id) (0x0000000000000130ull) 704215976Sjmallett#endif 705215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 706215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG077(unsigned long block_id) 707215976Sjmallett{ 708215976Sjmallett if (!( 709215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 710215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 711215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 712215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG077(%lu) is invalid on this chip\n", block_id); 713215976Sjmallett return 0x0000000000000134ull; 714215976Sjmallett} 715215976Sjmallett#else 716215976Sjmallett#define CVMX_PCIERCX_CFG077(block_id) (0x0000000000000134ull) 717215976Sjmallett#endif 718215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 719215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG448(unsigned long block_id) 720215976Sjmallett{ 721215976Sjmallett if (!( 722215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 723215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 724215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 725215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG448(%lu) is invalid on this chip\n", block_id); 726215976Sjmallett return 0x0000000000000700ull; 727215976Sjmallett} 728215976Sjmallett#else 729215976Sjmallett#define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull) 730215976Sjmallett#endif 731215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 732215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG449(unsigned long block_id) 733215976Sjmallett{ 734215976Sjmallett if (!( 735215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 736215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 737215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 738215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG449(%lu) is invalid on this chip\n", block_id); 739215976Sjmallett return 0x0000000000000704ull; 740215976Sjmallett} 741215976Sjmallett#else 742215976Sjmallett#define CVMX_PCIERCX_CFG449(block_id) (0x0000000000000704ull) 743215976Sjmallett#endif 744215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 745215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG450(unsigned long block_id) 746215976Sjmallett{ 747215976Sjmallett if (!( 748215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 749215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 750215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 751215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG450(%lu) is invalid on this chip\n", block_id); 752215976Sjmallett return 0x0000000000000708ull; 753215976Sjmallett} 754215976Sjmallett#else 755215976Sjmallett#define CVMX_PCIERCX_CFG450(block_id) (0x0000000000000708ull) 756215976Sjmallett#endif 757215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 758215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG451(unsigned long block_id) 759215976Sjmallett{ 760215976Sjmallett if (!( 761215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 762215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 763215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 764215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG451(%lu) is invalid on this chip\n", block_id); 765215976Sjmallett return 0x000000000000070Cull; 766215976Sjmallett} 767215976Sjmallett#else 768215976Sjmallett#define CVMX_PCIERCX_CFG451(block_id) (0x000000000000070Cull) 769215976Sjmallett#endif 770215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 771215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG452(unsigned long block_id) 772215976Sjmallett{ 773215976Sjmallett if (!( 774215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 775215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 776215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 777215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG452(%lu) is invalid on this chip\n", block_id); 778215976Sjmallett return 0x0000000000000710ull; 779215976Sjmallett} 780215976Sjmallett#else 781215976Sjmallett#define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull) 782215976Sjmallett#endif 783215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 784215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG453(unsigned long block_id) 785215976Sjmallett{ 786215976Sjmallett if (!( 787215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 788215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 789215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 790215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG453(%lu) is invalid on this chip\n", block_id); 791215976Sjmallett return 0x0000000000000714ull; 792215976Sjmallett} 793215976Sjmallett#else 794215976Sjmallett#define CVMX_PCIERCX_CFG453(block_id) (0x0000000000000714ull) 795215976Sjmallett#endif 796215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 797215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG454(unsigned long block_id) 798215976Sjmallett{ 799215976Sjmallett if (!( 800215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 801215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 802215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 803215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG454(%lu) is invalid on this chip\n", block_id); 804215976Sjmallett return 0x0000000000000718ull; 805215976Sjmallett} 806215976Sjmallett#else 807215976Sjmallett#define CVMX_PCIERCX_CFG454(block_id) (0x0000000000000718ull) 808215976Sjmallett#endif 809215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 810215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG455(unsigned long block_id) 811215976Sjmallett{ 812215976Sjmallett if (!( 813215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 814215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 815215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 816215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG455(%lu) is invalid on this chip\n", block_id); 817215976Sjmallett return 0x000000000000071Cull; 818215976Sjmallett} 819215976Sjmallett#else 820215976Sjmallett#define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull) 821215976Sjmallett#endif 822215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 823215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG456(unsigned long block_id) 824215976Sjmallett{ 825215976Sjmallett if (!( 826215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 827215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 828215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 829215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG456(%lu) is invalid on this chip\n", block_id); 830215976Sjmallett return 0x0000000000000720ull; 831215976Sjmallett} 832215976Sjmallett#else 833215976Sjmallett#define CVMX_PCIERCX_CFG456(block_id) (0x0000000000000720ull) 834215976Sjmallett#endif 835215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 836215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG458(unsigned long block_id) 837215976Sjmallett{ 838215976Sjmallett if (!( 839215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 840215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 841215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 842215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG458(%lu) is invalid on this chip\n", block_id); 843215976Sjmallett return 0x0000000000000728ull; 844215976Sjmallett} 845215976Sjmallett#else 846215976Sjmallett#define CVMX_PCIERCX_CFG458(block_id) (0x0000000000000728ull) 847215976Sjmallett#endif 848215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 849215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG459(unsigned long block_id) 850215976Sjmallett{ 851215976Sjmallett if (!( 852215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 853215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 854215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 855215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG459(%lu) is invalid on this chip\n", block_id); 856215976Sjmallett return 0x000000000000072Cull; 857215976Sjmallett} 858215976Sjmallett#else 859215976Sjmallett#define CVMX_PCIERCX_CFG459(block_id) (0x000000000000072Cull) 860215976Sjmallett#endif 861215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 862215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG460(unsigned long block_id) 863215976Sjmallett{ 864215976Sjmallett if (!( 865215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 866215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 867215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 868215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG460(%lu) is invalid on this chip\n", block_id); 869215976Sjmallett return 0x0000000000000730ull; 870215976Sjmallett} 871215976Sjmallett#else 872215976Sjmallett#define CVMX_PCIERCX_CFG460(block_id) (0x0000000000000730ull) 873215976Sjmallett#endif 874215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 875215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG461(unsigned long block_id) 876215976Sjmallett{ 877215976Sjmallett if (!( 878215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 879215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 880215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 881215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG461(%lu) is invalid on this chip\n", block_id); 882215976Sjmallett return 0x0000000000000734ull; 883215976Sjmallett} 884215976Sjmallett#else 885215976Sjmallett#define CVMX_PCIERCX_CFG461(block_id) (0x0000000000000734ull) 886215976Sjmallett#endif 887215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 888215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG462(unsigned long block_id) 889215976Sjmallett{ 890215976Sjmallett if (!( 891215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 892215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 893215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 894215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG462(%lu) is invalid on this chip\n", block_id); 895215976Sjmallett return 0x0000000000000738ull; 896215976Sjmallett} 897215976Sjmallett#else 898215976Sjmallett#define CVMX_PCIERCX_CFG462(block_id) (0x0000000000000738ull) 899215976Sjmallett#endif 900215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 901215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG463(unsigned long block_id) 902215976Sjmallett{ 903215976Sjmallett if (!( 904215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 905215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 906215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 907215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG463(%lu) is invalid on this chip\n", block_id); 908215976Sjmallett return 0x000000000000073Cull; 909215976Sjmallett} 910215976Sjmallett#else 911215976Sjmallett#define CVMX_PCIERCX_CFG463(block_id) (0x000000000000073Cull) 912215976Sjmallett#endif 913215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 914215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG464(unsigned long block_id) 915215976Sjmallett{ 916215976Sjmallett if (!( 917215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 918215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 919215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 920215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG464(%lu) is invalid on this chip\n", block_id); 921215976Sjmallett return 0x0000000000000740ull; 922215976Sjmallett} 923215976Sjmallett#else 924215976Sjmallett#define CVMX_PCIERCX_CFG464(block_id) (0x0000000000000740ull) 925215976Sjmallett#endif 926215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 927215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG465(unsigned long block_id) 928215976Sjmallett{ 929215976Sjmallett if (!( 930215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 931215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 932215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 933215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG465(%lu) is invalid on this chip\n", block_id); 934215976Sjmallett return 0x0000000000000744ull; 935215976Sjmallett} 936215976Sjmallett#else 937215976Sjmallett#define CVMX_PCIERCX_CFG465(block_id) (0x0000000000000744ull) 938215976Sjmallett#endif 939215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 940215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG466(unsigned long block_id) 941215976Sjmallett{ 942215976Sjmallett if (!( 943215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 944215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 945215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 946215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG466(%lu) is invalid on this chip\n", block_id); 947215976Sjmallett return 0x0000000000000748ull; 948215976Sjmallett} 949215976Sjmallett#else 950215976Sjmallett#define CVMX_PCIERCX_CFG466(block_id) (0x0000000000000748ull) 951215976Sjmallett#endif 952215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 953215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG467(unsigned long block_id) 954215976Sjmallett{ 955215976Sjmallett if (!( 956215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 957215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 958215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 959215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG467(%lu) is invalid on this chip\n", block_id); 960215976Sjmallett return 0x000000000000074Cull; 961215976Sjmallett} 962215976Sjmallett#else 963215976Sjmallett#define CVMX_PCIERCX_CFG467(block_id) (0x000000000000074Cull) 964215976Sjmallett#endif 965215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 966215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG468(unsigned long block_id) 967215976Sjmallett{ 968215976Sjmallett if (!( 969215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 970215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 971215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 972215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG468(%lu) is invalid on this chip\n", block_id); 973215976Sjmallett return 0x0000000000000750ull; 974215976Sjmallett} 975215976Sjmallett#else 976215976Sjmallett#define CVMX_PCIERCX_CFG468(block_id) (0x0000000000000750ull) 977215976Sjmallett#endif 978215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 979215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG490(unsigned long block_id) 980215976Sjmallett{ 981215976Sjmallett if (!( 982215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 983215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 984215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 985215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG490(%lu) is invalid on this chip\n", block_id); 986215976Sjmallett return 0x00000000000007A8ull; 987215976Sjmallett} 988215976Sjmallett#else 989215976Sjmallett#define CVMX_PCIERCX_CFG490(block_id) (0x00000000000007A8ull) 990215976Sjmallett#endif 991215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 992215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG491(unsigned long block_id) 993215976Sjmallett{ 994215976Sjmallett if (!( 995215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 996215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 997215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 998215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG491(%lu) is invalid on this chip\n", block_id); 999215976Sjmallett return 0x00000000000007ACull; 1000215976Sjmallett} 1001215976Sjmallett#else 1002215976Sjmallett#define CVMX_PCIERCX_CFG491(block_id) (0x00000000000007ACull) 1003215976Sjmallett#endif 1004215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1005215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG492(unsigned long block_id) 1006215976Sjmallett{ 1007215976Sjmallett if (!( 1008215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1009215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1010215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 1011215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG492(%lu) is invalid on this chip\n", block_id); 1012215976Sjmallett return 0x00000000000007B0ull; 1013215976Sjmallett} 1014215976Sjmallett#else 1015215976Sjmallett#define CVMX_PCIERCX_CFG492(block_id) (0x00000000000007B0ull) 1016215976Sjmallett#endif 1017215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1018215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG515(unsigned long block_id) 1019215976Sjmallett{ 1020215976Sjmallett if (!( 1021215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 1022215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG515(%lu) is invalid on this chip\n", block_id); 1023215976Sjmallett return 0x000000000000080Cull; 1024215976Sjmallett} 1025215976Sjmallett#else 1026215976Sjmallett#define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull) 1027215976Sjmallett#endif 1028215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1029215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG516(unsigned long block_id) 1030215976Sjmallett{ 1031215976Sjmallett if (!( 1032215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1033215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1034215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 1035215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG516(%lu) is invalid on this chip\n", block_id); 1036215976Sjmallett return 0x0000000000000810ull; 1037215976Sjmallett} 1038215976Sjmallett#else 1039215976Sjmallett#define CVMX_PCIERCX_CFG516(block_id) (0x0000000000000810ull) 1040215976Sjmallett#endif 1041215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1042215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG517(unsigned long block_id) 1043215976Sjmallett{ 1044215976Sjmallett if (!( 1045215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1046215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1047215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 1048215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG517(%lu) is invalid on this chip\n", block_id); 1049215976Sjmallett return 0x0000000000000814ull; 1050215976Sjmallett} 1051215976Sjmallett#else 1052215976Sjmallett#define CVMX_PCIERCX_CFG517(block_id) (0x0000000000000814ull) 1053215976Sjmallett#endif 1054215976Sjmallett 1055215976Sjmallett/** 1056215976Sjmallett * cvmx_pcierc#_cfg000 1057215976Sjmallett * 1058215976Sjmallett * PCIE_CFG000 = First 32-bits of PCIE type 1 config space (Device ID and Vendor ID Register) 1059215976Sjmallett * 1060215976Sjmallett */ 1061215976Sjmallettunion cvmx_pciercx_cfg000 1062215976Sjmallett{ 1063215976Sjmallett uint32_t u32; 1064215976Sjmallett struct cvmx_pciercx_cfg000_s 1065215976Sjmallett { 1066215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1067215976Sjmallett uint32_t devid : 16; /**< Device ID, writable through PEM(0..1)_CFG_WR 1068215976Sjmallett However, the application must not change this field. */ 1069215976Sjmallett uint32_t vendid : 16; /**< Vendor ID, writable through PEM(0..1)_CFG_WR 1070215976Sjmallett However, the application must not change this field. */ 1071215976Sjmallett#else 1072215976Sjmallett uint32_t vendid : 16; 1073215976Sjmallett uint32_t devid : 16; 1074215976Sjmallett#endif 1075215976Sjmallett } s; 1076215976Sjmallett struct cvmx_pciercx_cfg000_s cn52xx; 1077215976Sjmallett struct cvmx_pciercx_cfg000_s cn52xxp1; 1078215976Sjmallett struct cvmx_pciercx_cfg000_s cn56xx; 1079215976Sjmallett struct cvmx_pciercx_cfg000_s cn56xxp1; 1080215976Sjmallett struct cvmx_pciercx_cfg000_s cn63xx; 1081215976Sjmallett struct cvmx_pciercx_cfg000_s cn63xxp1; 1082215976Sjmallett}; 1083215976Sjmalletttypedef union cvmx_pciercx_cfg000 cvmx_pciercx_cfg000_t; 1084215976Sjmallett 1085215976Sjmallett/** 1086215976Sjmallett * cvmx_pcierc#_cfg001 1087215976Sjmallett * 1088215976Sjmallett * PCIE_CFG001 = Second 32-bits of PCIE type 1 config space (Command/Status Register) 1089215976Sjmallett * 1090215976Sjmallett */ 1091215976Sjmallettunion cvmx_pciercx_cfg001 1092215976Sjmallett{ 1093215976Sjmallett uint32_t u32; 1094215976Sjmallett struct cvmx_pciercx_cfg001_s 1095215976Sjmallett { 1096215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1097215976Sjmallett uint32_t dpe : 1; /**< Detected Parity Error */ 1098215976Sjmallett uint32_t sse : 1; /**< Signaled System Error */ 1099215976Sjmallett uint32_t rma : 1; /**< Received Master Abort */ 1100215976Sjmallett uint32_t rta : 1; /**< Received Target Abort */ 1101215976Sjmallett uint32_t sta : 1; /**< Signaled Target Abort */ 1102215976Sjmallett uint32_t devt : 2; /**< DEVSEL Timing 1103215976Sjmallett Not applicable for PCI Express. Hardwired to 0. */ 1104215976Sjmallett uint32_t mdpe : 1; /**< Master Data Parity Error */ 1105215976Sjmallett uint32_t fbb : 1; /**< Fast Back-to-Back Capable 1106215976Sjmallett Not applicable for PCI Express. Hardwired to 0. */ 1107215976Sjmallett uint32_t reserved_22_22 : 1; 1108215976Sjmallett uint32_t m66 : 1; /**< 66 MHz Capable 1109215976Sjmallett Not applicable for PCI Express. Hardwired to 0. */ 1110215976Sjmallett uint32_t cl : 1; /**< Capabilities List 1111215976Sjmallett Indicates presence of an extended capability item. 1112215976Sjmallett Hardwired to 1. */ 1113215976Sjmallett uint32_t i_stat : 1; /**< INTx Status */ 1114215976Sjmallett uint32_t reserved_11_18 : 8; 1115215976Sjmallett uint32_t i_dis : 1; /**< INTx Assertion Disable */ 1116215976Sjmallett uint32_t fbbe : 1; /**< Fast Back-to-Back Enable 1117215976Sjmallett Not applicable for PCI Express. Must be hardwired to 0. */ 1118215976Sjmallett uint32_t see : 1; /**< SERR# Enable */ 1119215976Sjmallett uint32_t ids_wcc : 1; /**< IDSEL Stepping/Wait Cycle Control 1120215976Sjmallett Not applicable for PCI Express. Must be hardwired to 0 */ 1121215976Sjmallett uint32_t per : 1; /**< Parity Error Response */ 1122215976Sjmallett uint32_t vps : 1; /**< VGA Palette Snoop 1123215976Sjmallett Not applicable for PCI Express. Must be hardwired to 0. */ 1124215976Sjmallett uint32_t mwice : 1; /**< Memory Write and Invalidate 1125215976Sjmallett Not applicable for PCI Express. Must be hardwired to 0. */ 1126215976Sjmallett uint32_t scse : 1; /**< Special Cycle Enable 1127215976Sjmallett Not applicable for PCI Express. Must be hardwired to 0. */ 1128215976Sjmallett uint32_t me : 1; /**< Bus Master Enable */ 1129215976Sjmallett uint32_t msae : 1; /**< Memory Space Enable */ 1130215976Sjmallett uint32_t isae : 1; /**< I/O Space Enable */ 1131215976Sjmallett#else 1132215976Sjmallett uint32_t isae : 1; 1133215976Sjmallett uint32_t msae : 1; 1134215976Sjmallett uint32_t me : 1; 1135215976Sjmallett uint32_t scse : 1; 1136215976Sjmallett uint32_t mwice : 1; 1137215976Sjmallett uint32_t vps : 1; 1138215976Sjmallett uint32_t per : 1; 1139215976Sjmallett uint32_t ids_wcc : 1; 1140215976Sjmallett uint32_t see : 1; 1141215976Sjmallett uint32_t fbbe : 1; 1142215976Sjmallett uint32_t i_dis : 1; 1143215976Sjmallett uint32_t reserved_11_18 : 8; 1144215976Sjmallett uint32_t i_stat : 1; 1145215976Sjmallett uint32_t cl : 1; 1146215976Sjmallett uint32_t m66 : 1; 1147215976Sjmallett uint32_t reserved_22_22 : 1; 1148215976Sjmallett uint32_t fbb : 1; 1149215976Sjmallett uint32_t mdpe : 1; 1150215976Sjmallett uint32_t devt : 2; 1151215976Sjmallett uint32_t sta : 1; 1152215976Sjmallett uint32_t rta : 1; 1153215976Sjmallett uint32_t rma : 1; 1154215976Sjmallett uint32_t sse : 1; 1155215976Sjmallett uint32_t dpe : 1; 1156215976Sjmallett#endif 1157215976Sjmallett } s; 1158215976Sjmallett struct cvmx_pciercx_cfg001_s cn52xx; 1159215976Sjmallett struct cvmx_pciercx_cfg001_s cn52xxp1; 1160215976Sjmallett struct cvmx_pciercx_cfg001_s cn56xx; 1161215976Sjmallett struct cvmx_pciercx_cfg001_s cn56xxp1; 1162215976Sjmallett struct cvmx_pciercx_cfg001_s cn63xx; 1163215976Sjmallett struct cvmx_pciercx_cfg001_s cn63xxp1; 1164215976Sjmallett}; 1165215976Sjmalletttypedef union cvmx_pciercx_cfg001 cvmx_pciercx_cfg001_t; 1166215976Sjmallett 1167215976Sjmallett/** 1168215976Sjmallett * cvmx_pcierc#_cfg002 1169215976Sjmallett * 1170215976Sjmallett * PCIE_CFG002 = Third 32-bits of PCIE type 1 config space (Revision ID/Class Code Register) 1171215976Sjmallett * 1172215976Sjmallett */ 1173215976Sjmallettunion cvmx_pciercx_cfg002 1174215976Sjmallett{ 1175215976Sjmallett uint32_t u32; 1176215976Sjmallett struct cvmx_pciercx_cfg002_s 1177215976Sjmallett { 1178215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1179215976Sjmallett uint32_t bcc : 8; /**< Base Class Code, writable through PEM(0..1)_CFG_WR 1180215976Sjmallett However, the application must not change this field. */ 1181215976Sjmallett uint32_t sc : 8; /**< Subclass Code, writable through PEM(0..1)_CFG_WR 1182215976Sjmallett However, the application must not change this field. */ 1183215976Sjmallett uint32_t pi : 8; /**< Programming Interface, writable through PEM(0..1)_CFG_WR 1184215976Sjmallett However, the application must not change this field. */ 1185215976Sjmallett uint32_t rid : 8; /**< Revision ID, writable through PEM(0..1)_CFG_WR 1186215976Sjmallett However, the application must not change this field. */ 1187215976Sjmallett#else 1188215976Sjmallett uint32_t rid : 8; 1189215976Sjmallett uint32_t pi : 8; 1190215976Sjmallett uint32_t sc : 8; 1191215976Sjmallett uint32_t bcc : 8; 1192215976Sjmallett#endif 1193215976Sjmallett } s; 1194215976Sjmallett struct cvmx_pciercx_cfg002_s cn52xx; 1195215976Sjmallett struct cvmx_pciercx_cfg002_s cn52xxp1; 1196215976Sjmallett struct cvmx_pciercx_cfg002_s cn56xx; 1197215976Sjmallett struct cvmx_pciercx_cfg002_s cn56xxp1; 1198215976Sjmallett struct cvmx_pciercx_cfg002_s cn63xx; 1199215976Sjmallett struct cvmx_pciercx_cfg002_s cn63xxp1; 1200215976Sjmallett}; 1201215976Sjmalletttypedef union cvmx_pciercx_cfg002 cvmx_pciercx_cfg002_t; 1202215976Sjmallett 1203215976Sjmallett/** 1204215976Sjmallett * cvmx_pcierc#_cfg003 1205215976Sjmallett * 1206215976Sjmallett * PCIE_CFG003 = Fourth 32-bits of PCIE type 1 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register) 1207215976Sjmallett * 1208215976Sjmallett */ 1209215976Sjmallettunion cvmx_pciercx_cfg003 1210215976Sjmallett{ 1211215976Sjmallett uint32_t u32; 1212215976Sjmallett struct cvmx_pciercx_cfg003_s 1213215976Sjmallett { 1214215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1215215976Sjmallett uint32_t bist : 8; /**< The BIST register functions are not supported. 1216215976Sjmallett All 8 bits of the BIST register are hardwired to 0. */ 1217215976Sjmallett uint32_t mfd : 1; /**< Multi Function Device 1218215976Sjmallett The Multi Function Device bit is writable through PEM(0..1)_CFG_WR. 1219215976Sjmallett However, this is a single function device. Therefore, the 1220215976Sjmallett application must not write a 1 to this bit. */ 1221215976Sjmallett uint32_t chf : 7; /**< Configuration Header Format 1222215976Sjmallett Hardwired to 1. */ 1223215976Sjmallett uint32_t lt : 8; /**< Master Latency Timer 1224215976Sjmallett Not applicable for PCI Express, hardwired to 0. */ 1225215976Sjmallett uint32_t cls : 8; /**< Cache Line Size 1226215976Sjmallett The Cache Line Size register is RW for legacy compatibility 1227215976Sjmallett purposes and is not applicable to PCI Express device 1228215976Sjmallett functionality. */ 1229215976Sjmallett#else 1230215976Sjmallett uint32_t cls : 8; 1231215976Sjmallett uint32_t lt : 8; 1232215976Sjmallett uint32_t chf : 7; 1233215976Sjmallett uint32_t mfd : 1; 1234215976Sjmallett uint32_t bist : 8; 1235215976Sjmallett#endif 1236215976Sjmallett } s; 1237215976Sjmallett struct cvmx_pciercx_cfg003_s cn52xx; 1238215976Sjmallett struct cvmx_pciercx_cfg003_s cn52xxp1; 1239215976Sjmallett struct cvmx_pciercx_cfg003_s cn56xx; 1240215976Sjmallett struct cvmx_pciercx_cfg003_s cn56xxp1; 1241215976Sjmallett struct cvmx_pciercx_cfg003_s cn63xx; 1242215976Sjmallett struct cvmx_pciercx_cfg003_s cn63xxp1; 1243215976Sjmallett}; 1244215976Sjmalletttypedef union cvmx_pciercx_cfg003 cvmx_pciercx_cfg003_t; 1245215976Sjmallett 1246215976Sjmallett/** 1247215976Sjmallett * cvmx_pcierc#_cfg004 1248215976Sjmallett * 1249215976Sjmallett * PCIE_CFG004 = Fifth 32-bits of PCIE type 1 config space (Base Address Register 0 - Low) 1250215976Sjmallett * 1251215976Sjmallett */ 1252215976Sjmallettunion cvmx_pciercx_cfg004 1253215976Sjmallett{ 1254215976Sjmallett uint32_t u32; 1255215976Sjmallett struct cvmx_pciercx_cfg004_s 1256215976Sjmallett { 1257215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1258215976Sjmallett uint32_t reserved_0_31 : 32; 1259215976Sjmallett#else 1260215976Sjmallett uint32_t reserved_0_31 : 32; 1261215976Sjmallett#endif 1262215976Sjmallett } s; 1263215976Sjmallett struct cvmx_pciercx_cfg004_s cn52xx; 1264215976Sjmallett struct cvmx_pciercx_cfg004_s cn52xxp1; 1265215976Sjmallett struct cvmx_pciercx_cfg004_s cn56xx; 1266215976Sjmallett struct cvmx_pciercx_cfg004_s cn56xxp1; 1267215976Sjmallett struct cvmx_pciercx_cfg004_s cn63xx; 1268215976Sjmallett struct cvmx_pciercx_cfg004_s cn63xxp1; 1269215976Sjmallett}; 1270215976Sjmalletttypedef union cvmx_pciercx_cfg004 cvmx_pciercx_cfg004_t; 1271215976Sjmallett 1272215976Sjmallett/** 1273215976Sjmallett * cvmx_pcierc#_cfg005 1274215976Sjmallett * 1275215976Sjmallett * PCIE_CFG005 = Sixth 32-bits of PCIE type 1 config space (Base Address Register 0 - High) 1276215976Sjmallett * 1277215976Sjmallett */ 1278215976Sjmallettunion cvmx_pciercx_cfg005 1279215976Sjmallett{ 1280215976Sjmallett uint32_t u32; 1281215976Sjmallett struct cvmx_pciercx_cfg005_s 1282215976Sjmallett { 1283215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1284215976Sjmallett uint32_t reserved_0_31 : 32; 1285215976Sjmallett#else 1286215976Sjmallett uint32_t reserved_0_31 : 32; 1287215976Sjmallett#endif 1288215976Sjmallett } s; 1289215976Sjmallett struct cvmx_pciercx_cfg005_s cn52xx; 1290215976Sjmallett struct cvmx_pciercx_cfg005_s cn52xxp1; 1291215976Sjmallett struct cvmx_pciercx_cfg005_s cn56xx; 1292215976Sjmallett struct cvmx_pciercx_cfg005_s cn56xxp1; 1293215976Sjmallett struct cvmx_pciercx_cfg005_s cn63xx; 1294215976Sjmallett struct cvmx_pciercx_cfg005_s cn63xxp1; 1295215976Sjmallett}; 1296215976Sjmalletttypedef union cvmx_pciercx_cfg005 cvmx_pciercx_cfg005_t; 1297215976Sjmallett 1298215976Sjmallett/** 1299215976Sjmallett * cvmx_pcierc#_cfg006 1300215976Sjmallett * 1301215976Sjmallett * PCIE_CFG006 = Seventh 32-bits of PCIE type 1 config space (Bus Number Registers) 1302215976Sjmallett * 1303215976Sjmallett */ 1304215976Sjmallettunion cvmx_pciercx_cfg006 1305215976Sjmallett{ 1306215976Sjmallett uint32_t u32; 1307215976Sjmallett struct cvmx_pciercx_cfg006_s 1308215976Sjmallett { 1309215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1310215976Sjmallett uint32_t slt : 8; /**< Secondary Latency Timer 1311215976Sjmallett Not applicable to PCI Express, hardwired to 0x00. */ 1312215976Sjmallett uint32_t subbnum : 8; /**< Subordinate Bus Number */ 1313215976Sjmallett uint32_t sbnum : 8; /**< Secondary Bus Number */ 1314215976Sjmallett uint32_t pbnum : 8; /**< Primary Bus Number */ 1315215976Sjmallett#else 1316215976Sjmallett uint32_t pbnum : 8; 1317215976Sjmallett uint32_t sbnum : 8; 1318215976Sjmallett uint32_t subbnum : 8; 1319215976Sjmallett uint32_t slt : 8; 1320215976Sjmallett#endif 1321215976Sjmallett } s; 1322215976Sjmallett struct cvmx_pciercx_cfg006_s cn52xx; 1323215976Sjmallett struct cvmx_pciercx_cfg006_s cn52xxp1; 1324215976Sjmallett struct cvmx_pciercx_cfg006_s cn56xx; 1325215976Sjmallett struct cvmx_pciercx_cfg006_s cn56xxp1; 1326215976Sjmallett struct cvmx_pciercx_cfg006_s cn63xx; 1327215976Sjmallett struct cvmx_pciercx_cfg006_s cn63xxp1; 1328215976Sjmallett}; 1329215976Sjmalletttypedef union cvmx_pciercx_cfg006 cvmx_pciercx_cfg006_t; 1330215976Sjmallett 1331215976Sjmallett/** 1332215976Sjmallett * cvmx_pcierc#_cfg007 1333215976Sjmallett * 1334215976Sjmallett * PCIE_CFG007 = Eighth 32-bits of PCIE type 1 config space (IO Base and IO Limit/Secondary Status Register) 1335215976Sjmallett * 1336215976Sjmallett */ 1337215976Sjmallettunion cvmx_pciercx_cfg007 1338215976Sjmallett{ 1339215976Sjmallett uint32_t u32; 1340215976Sjmallett struct cvmx_pciercx_cfg007_s 1341215976Sjmallett { 1342215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1343215976Sjmallett uint32_t dpe : 1; /**< Detected Parity Error */ 1344215976Sjmallett uint32_t sse : 1; /**< Signaled System Error */ 1345215976Sjmallett uint32_t rma : 1; /**< Received Master Abort */ 1346215976Sjmallett uint32_t rta : 1; /**< Received Target Abort */ 1347215976Sjmallett uint32_t sta : 1; /**< Signaled Target Abort */ 1348215976Sjmallett uint32_t devt : 2; /**< DEVSEL Timing 1349215976Sjmallett Not applicable for PCI Express. Hardwired to 0. */ 1350215976Sjmallett uint32_t mdpe : 1; /**< Master Data Parity Error */ 1351215976Sjmallett uint32_t fbb : 1; /**< Fast Back-to-Back Capable 1352215976Sjmallett Not applicable for PCI Express. Hardwired to 0. */ 1353215976Sjmallett uint32_t reserved_22_22 : 1; 1354215976Sjmallett uint32_t m66 : 1; /**< 66 MHz Capable 1355215976Sjmallett Not applicable for PCI Express. Hardwired to 0. */ 1356215976Sjmallett uint32_t reserved_16_20 : 5; 1357215976Sjmallett uint32_t lio_limi : 4; /**< I/O Space Limit */ 1358215976Sjmallett uint32_t reserved_9_11 : 3; 1359215976Sjmallett uint32_t io32b : 1; /**< 32-Bit I/O Space */ 1360215976Sjmallett uint32_t lio_base : 4; /**< I/O Space Base */ 1361215976Sjmallett uint32_t reserved_1_3 : 3; 1362215976Sjmallett uint32_t io32a : 1; /**< 32-Bit I/O Space 1363215976Sjmallett o 0 = 16-bit I/O addressing 1364215976Sjmallett o 1 = 32-bit I/O addressing 1365215976Sjmallett This bit is writable through PEM(0..1)_CFG_WR. 1366215976Sjmallett When the application 1367215976Sjmallett writes to this bit through PEM(0..1)_CFG_WR, 1368215976Sjmallett the same value is written 1369215976Sjmallett to bit 8 of this register. */ 1370215976Sjmallett#else 1371215976Sjmallett uint32_t io32a : 1; 1372215976Sjmallett uint32_t reserved_1_3 : 3; 1373215976Sjmallett uint32_t lio_base : 4; 1374215976Sjmallett uint32_t io32b : 1; 1375215976Sjmallett uint32_t reserved_9_11 : 3; 1376215976Sjmallett uint32_t lio_limi : 4; 1377215976Sjmallett uint32_t reserved_16_20 : 5; 1378215976Sjmallett uint32_t m66 : 1; 1379215976Sjmallett uint32_t reserved_22_22 : 1; 1380215976Sjmallett uint32_t fbb : 1; 1381215976Sjmallett uint32_t mdpe : 1; 1382215976Sjmallett uint32_t devt : 2; 1383215976Sjmallett uint32_t sta : 1; 1384215976Sjmallett uint32_t rta : 1; 1385215976Sjmallett uint32_t rma : 1; 1386215976Sjmallett uint32_t sse : 1; 1387215976Sjmallett uint32_t dpe : 1; 1388215976Sjmallett#endif 1389215976Sjmallett } s; 1390215976Sjmallett struct cvmx_pciercx_cfg007_s cn52xx; 1391215976Sjmallett struct cvmx_pciercx_cfg007_s cn52xxp1; 1392215976Sjmallett struct cvmx_pciercx_cfg007_s cn56xx; 1393215976Sjmallett struct cvmx_pciercx_cfg007_s cn56xxp1; 1394215976Sjmallett struct cvmx_pciercx_cfg007_s cn63xx; 1395215976Sjmallett struct cvmx_pciercx_cfg007_s cn63xxp1; 1396215976Sjmallett}; 1397215976Sjmalletttypedef union cvmx_pciercx_cfg007 cvmx_pciercx_cfg007_t; 1398215976Sjmallett 1399215976Sjmallett/** 1400215976Sjmallett * cvmx_pcierc#_cfg008 1401215976Sjmallett * 1402215976Sjmallett * PCIE_CFG008 = Ninth 32-bits of PCIE type 1 config space (Memory Base and Memory Limit Register) 1403215976Sjmallett * 1404215976Sjmallett */ 1405215976Sjmallettunion cvmx_pciercx_cfg008 1406215976Sjmallett{ 1407215976Sjmallett uint32_t u32; 1408215976Sjmallett struct cvmx_pciercx_cfg008_s 1409215976Sjmallett { 1410215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1411215976Sjmallett uint32_t ml_addr : 12; /**< Memory Limit Address */ 1412215976Sjmallett uint32_t reserved_16_19 : 4; 1413215976Sjmallett uint32_t mb_addr : 12; /**< Memory Base Address */ 1414215976Sjmallett uint32_t reserved_0_3 : 4; 1415215976Sjmallett#else 1416215976Sjmallett uint32_t reserved_0_3 : 4; 1417215976Sjmallett uint32_t mb_addr : 12; 1418215976Sjmallett uint32_t reserved_16_19 : 4; 1419215976Sjmallett uint32_t ml_addr : 12; 1420215976Sjmallett#endif 1421215976Sjmallett } s; 1422215976Sjmallett struct cvmx_pciercx_cfg008_s cn52xx; 1423215976Sjmallett struct cvmx_pciercx_cfg008_s cn52xxp1; 1424215976Sjmallett struct cvmx_pciercx_cfg008_s cn56xx; 1425215976Sjmallett struct cvmx_pciercx_cfg008_s cn56xxp1; 1426215976Sjmallett struct cvmx_pciercx_cfg008_s cn63xx; 1427215976Sjmallett struct cvmx_pciercx_cfg008_s cn63xxp1; 1428215976Sjmallett}; 1429215976Sjmalletttypedef union cvmx_pciercx_cfg008 cvmx_pciercx_cfg008_t; 1430215976Sjmallett 1431215976Sjmallett/** 1432215976Sjmallett * cvmx_pcierc#_cfg009 1433215976Sjmallett * 1434215976Sjmallett * PCIE_CFG009 = Tenth 32-bits of PCIE type 1 config space (Prefetchable Memory Base and Limit Register) 1435215976Sjmallett * 1436215976Sjmallett */ 1437215976Sjmallettunion cvmx_pciercx_cfg009 1438215976Sjmallett{ 1439215976Sjmallett uint32_t u32; 1440215976Sjmallett struct cvmx_pciercx_cfg009_s 1441215976Sjmallett { 1442215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1443215976Sjmallett uint32_t lmem_limit : 12; /**< Upper 12 bits of 32-bit Prefetchable Memory End Address */ 1444215976Sjmallett uint32_t reserved_17_19 : 3; 1445215976Sjmallett uint32_t mem64b : 1; /**< 64-Bit Memory Addressing 1446215976Sjmallett o 0 = 32-bit memory addressing 1447215976Sjmallett o 1 = 64-bit memory addressing */ 1448215976Sjmallett uint32_t lmem_base : 12; /**< Upper 12 bits of 32-bit Prefetchable Memory Start Address */ 1449215976Sjmallett uint32_t reserved_1_3 : 3; 1450215976Sjmallett uint32_t mem64a : 1; /**< 64-Bit Memory Addressing 1451215976Sjmallett o 0 = 32-bit memory addressing 1452215976Sjmallett o 1 = 64-bit memory addressing 1453215976Sjmallett This bit is writable through PEM(0..1)_CFG_WR. 1454215976Sjmallett When the application 1455215976Sjmallett writes to this bit through PEM(0..1)_CFG_WR, 1456215976Sjmallett the same value is written 1457215976Sjmallett to bit 16 of this register. */ 1458215976Sjmallett#else 1459215976Sjmallett uint32_t mem64a : 1; 1460215976Sjmallett uint32_t reserved_1_3 : 3; 1461215976Sjmallett uint32_t lmem_base : 12; 1462215976Sjmallett uint32_t mem64b : 1; 1463215976Sjmallett uint32_t reserved_17_19 : 3; 1464215976Sjmallett uint32_t lmem_limit : 12; 1465215976Sjmallett#endif 1466215976Sjmallett } s; 1467215976Sjmallett struct cvmx_pciercx_cfg009_s cn52xx; 1468215976Sjmallett struct cvmx_pciercx_cfg009_s cn52xxp1; 1469215976Sjmallett struct cvmx_pciercx_cfg009_s cn56xx; 1470215976Sjmallett struct cvmx_pciercx_cfg009_s cn56xxp1; 1471215976Sjmallett struct cvmx_pciercx_cfg009_s cn63xx; 1472215976Sjmallett struct cvmx_pciercx_cfg009_s cn63xxp1; 1473215976Sjmallett}; 1474215976Sjmalletttypedef union cvmx_pciercx_cfg009 cvmx_pciercx_cfg009_t; 1475215976Sjmallett 1476215976Sjmallett/** 1477215976Sjmallett * cvmx_pcierc#_cfg010 1478215976Sjmallett * 1479215976Sjmallett * PCIE_CFG010 = Eleventh 32-bits of PCIE type 1 config space (Prefetchable Base Upper 32 Bits Register) 1480215976Sjmallett * 1481215976Sjmallett */ 1482215976Sjmallettunion cvmx_pciercx_cfg010 1483215976Sjmallett{ 1484215976Sjmallett uint32_t u32; 1485215976Sjmallett struct cvmx_pciercx_cfg010_s 1486215976Sjmallett { 1487215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1488215976Sjmallett uint32_t umem_base : 32; /**< Upper 32 Bits of Base Address of Prefetchable Memory Space 1489215976Sjmallett Used only when 64-bit prefetchable memory addressing is 1490215976Sjmallett enabled. */ 1491215976Sjmallett#else 1492215976Sjmallett uint32_t umem_base : 32; 1493215976Sjmallett#endif 1494215976Sjmallett } s; 1495215976Sjmallett struct cvmx_pciercx_cfg010_s cn52xx; 1496215976Sjmallett struct cvmx_pciercx_cfg010_s cn52xxp1; 1497215976Sjmallett struct cvmx_pciercx_cfg010_s cn56xx; 1498215976Sjmallett struct cvmx_pciercx_cfg010_s cn56xxp1; 1499215976Sjmallett struct cvmx_pciercx_cfg010_s cn63xx; 1500215976Sjmallett struct cvmx_pciercx_cfg010_s cn63xxp1; 1501215976Sjmallett}; 1502215976Sjmalletttypedef union cvmx_pciercx_cfg010 cvmx_pciercx_cfg010_t; 1503215976Sjmallett 1504215976Sjmallett/** 1505215976Sjmallett * cvmx_pcierc#_cfg011 1506215976Sjmallett * 1507215976Sjmallett * PCIE_CFG011 = Twelfth 32-bits of PCIE type 1 config space (Prefetchable Limit Upper 32 Bits Register) 1508215976Sjmallett * 1509215976Sjmallett */ 1510215976Sjmallettunion cvmx_pciercx_cfg011 1511215976Sjmallett{ 1512215976Sjmallett uint32_t u32; 1513215976Sjmallett struct cvmx_pciercx_cfg011_s 1514215976Sjmallett { 1515215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1516215976Sjmallett uint32_t umem_limit : 32; /**< Upper 32 Bits of Limit Address of Prefetchable Memory Space 1517215976Sjmallett Used only when 64-bit prefetchable memory addressing is 1518215976Sjmallett enabled. */ 1519215976Sjmallett#else 1520215976Sjmallett uint32_t umem_limit : 32; 1521215976Sjmallett#endif 1522215976Sjmallett } s; 1523215976Sjmallett struct cvmx_pciercx_cfg011_s cn52xx; 1524215976Sjmallett struct cvmx_pciercx_cfg011_s cn52xxp1; 1525215976Sjmallett struct cvmx_pciercx_cfg011_s cn56xx; 1526215976Sjmallett struct cvmx_pciercx_cfg011_s cn56xxp1; 1527215976Sjmallett struct cvmx_pciercx_cfg011_s cn63xx; 1528215976Sjmallett struct cvmx_pciercx_cfg011_s cn63xxp1; 1529215976Sjmallett}; 1530215976Sjmalletttypedef union cvmx_pciercx_cfg011 cvmx_pciercx_cfg011_t; 1531215976Sjmallett 1532215976Sjmallett/** 1533215976Sjmallett * cvmx_pcierc#_cfg012 1534215976Sjmallett * 1535215976Sjmallett * PCIE_CFG012 = Thirteenth 32-bits of PCIE type 1 config space (IO Base and Limit Upper 16 Bits Register) 1536215976Sjmallett * 1537215976Sjmallett */ 1538215976Sjmallettunion cvmx_pciercx_cfg012 1539215976Sjmallett{ 1540215976Sjmallett uint32_t u32; 1541215976Sjmallett struct cvmx_pciercx_cfg012_s 1542215976Sjmallett { 1543215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1544215976Sjmallett uint32_t uio_limit : 16; /**< Upper 16 Bits of I/O Limit (if 32-bit I/O decoding is supported 1545215976Sjmallett for devices on the secondary side) */ 1546215976Sjmallett uint32_t uio_base : 16; /**< Upper 16 Bits of I/O Base (if 32-bit I/O decoding is supported 1547215976Sjmallett for devices on the secondary side) */ 1548215976Sjmallett#else 1549215976Sjmallett uint32_t uio_base : 16; 1550215976Sjmallett uint32_t uio_limit : 16; 1551215976Sjmallett#endif 1552215976Sjmallett } s; 1553215976Sjmallett struct cvmx_pciercx_cfg012_s cn52xx; 1554215976Sjmallett struct cvmx_pciercx_cfg012_s cn52xxp1; 1555215976Sjmallett struct cvmx_pciercx_cfg012_s cn56xx; 1556215976Sjmallett struct cvmx_pciercx_cfg012_s cn56xxp1; 1557215976Sjmallett struct cvmx_pciercx_cfg012_s cn63xx; 1558215976Sjmallett struct cvmx_pciercx_cfg012_s cn63xxp1; 1559215976Sjmallett}; 1560215976Sjmalletttypedef union cvmx_pciercx_cfg012 cvmx_pciercx_cfg012_t; 1561215976Sjmallett 1562215976Sjmallett/** 1563215976Sjmallett * cvmx_pcierc#_cfg013 1564215976Sjmallett * 1565215976Sjmallett * PCIE_CFG013 = Fourteenth 32-bits of PCIE type 1 config space (Capability Pointer Register) 1566215976Sjmallett * 1567215976Sjmallett */ 1568215976Sjmallettunion cvmx_pciercx_cfg013 1569215976Sjmallett{ 1570215976Sjmallett uint32_t u32; 1571215976Sjmallett struct cvmx_pciercx_cfg013_s 1572215976Sjmallett { 1573215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1574215976Sjmallett uint32_t reserved_8_31 : 24; 1575215976Sjmallett uint32_t cp : 8; /**< First Capability Pointer. 1576215976Sjmallett Points to Power Management Capability structure by 1577215976Sjmallett default, writable through PEM(0..1)_CFG_WR 1578215976Sjmallett However, the application must not change this field. */ 1579215976Sjmallett#else 1580215976Sjmallett uint32_t cp : 8; 1581215976Sjmallett uint32_t reserved_8_31 : 24; 1582215976Sjmallett#endif 1583215976Sjmallett } s; 1584215976Sjmallett struct cvmx_pciercx_cfg013_s cn52xx; 1585215976Sjmallett struct cvmx_pciercx_cfg013_s cn52xxp1; 1586215976Sjmallett struct cvmx_pciercx_cfg013_s cn56xx; 1587215976Sjmallett struct cvmx_pciercx_cfg013_s cn56xxp1; 1588215976Sjmallett struct cvmx_pciercx_cfg013_s cn63xx; 1589215976Sjmallett struct cvmx_pciercx_cfg013_s cn63xxp1; 1590215976Sjmallett}; 1591215976Sjmalletttypedef union cvmx_pciercx_cfg013 cvmx_pciercx_cfg013_t; 1592215976Sjmallett 1593215976Sjmallett/** 1594215976Sjmallett * cvmx_pcierc#_cfg014 1595215976Sjmallett * 1596215976Sjmallett * PCIE_CFG014 = Fifteenth 32-bits of PCIE type 1 config space (Expansion ROM Base Address Register) 1597215976Sjmallett * 1598215976Sjmallett */ 1599215976Sjmallettunion cvmx_pciercx_cfg014 1600215976Sjmallett{ 1601215976Sjmallett uint32_t u32; 1602215976Sjmallett struct cvmx_pciercx_cfg014_s 1603215976Sjmallett { 1604215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1605215976Sjmallett uint32_t reserved_0_31 : 32; 1606215976Sjmallett#else 1607215976Sjmallett uint32_t reserved_0_31 : 32; 1608215976Sjmallett#endif 1609215976Sjmallett } s; 1610215976Sjmallett struct cvmx_pciercx_cfg014_s cn52xx; 1611215976Sjmallett struct cvmx_pciercx_cfg014_s cn52xxp1; 1612215976Sjmallett struct cvmx_pciercx_cfg014_s cn56xx; 1613215976Sjmallett struct cvmx_pciercx_cfg014_s cn56xxp1; 1614215976Sjmallett struct cvmx_pciercx_cfg014_s cn63xx; 1615215976Sjmallett struct cvmx_pciercx_cfg014_s cn63xxp1; 1616215976Sjmallett}; 1617215976Sjmalletttypedef union cvmx_pciercx_cfg014 cvmx_pciercx_cfg014_t; 1618215976Sjmallett 1619215976Sjmallett/** 1620215976Sjmallett * cvmx_pcierc#_cfg015 1621215976Sjmallett * 1622215976Sjmallett * PCIE_CFG015 = Sixteenth 32-bits of PCIE type 1 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register) 1623215976Sjmallett * 1624215976Sjmallett */ 1625215976Sjmallettunion cvmx_pciercx_cfg015 1626215976Sjmallett{ 1627215976Sjmallett uint32_t u32; 1628215976Sjmallett struct cvmx_pciercx_cfg015_s 1629215976Sjmallett { 1630215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1631215976Sjmallett uint32_t reserved_28_31 : 4; 1632215976Sjmallett uint32_t dtsees : 1; /**< Discard Timer SERR Enable Status 1633215976Sjmallett Not applicable to PCI Express, hardwired to 0. */ 1634215976Sjmallett uint32_t dts : 1; /**< Discard Timer Status 1635215976Sjmallett Not applicable to PCI Express, hardwired to 0. */ 1636215976Sjmallett uint32_t sdt : 1; /**< Secondary Discard Timer 1637215976Sjmallett Not applicable to PCI Express, hardwired to 0. */ 1638215976Sjmallett uint32_t pdt : 1; /**< Primary Discard Timer 1639215976Sjmallett Not applicable to PCI Express, hardwired to 0. */ 1640215976Sjmallett uint32_t fbbe : 1; /**< Fast Back-to-Back Transactions Enable 1641215976Sjmallett Not applicable to PCI Express, hardwired to 0. */ 1642215976Sjmallett uint32_t sbrst : 1; /**< Secondary Bus Reset 1643215976Sjmallett Hot reset. Causes TS1s with the hot reset bit to be sent to 1644215976Sjmallett the link partner. When set, SW should wait 2ms before 1645215976Sjmallett clearing. The link partner normally responds by sending TS1s 1646215976Sjmallett with the hot reset bit set, which will cause a link 1647215976Sjmallett down event - refer to "PCIe Link-Down Reset in RC Mode" 1648215976Sjmallett section. */ 1649215976Sjmallett uint32_t mam : 1; /**< Master Abort Mode 1650215976Sjmallett Not applicable to PCI Express, hardwired to 0. */ 1651215976Sjmallett uint32_t vga16d : 1; /**< VGA 16-Bit Decode */ 1652215976Sjmallett uint32_t vgae : 1; /**< VGA Enable */ 1653215976Sjmallett uint32_t isae : 1; /**< ISA Enable */ 1654215976Sjmallett uint32_t see : 1; /**< SERR Enable */ 1655215976Sjmallett uint32_t pere : 1; /**< Parity Error Response Enable */ 1656215976Sjmallett uint32_t inta : 8; /**< Interrupt Pin 1657215976Sjmallett Identifies the legacy interrupt Message that the device 1658215976Sjmallett (or device function) uses. 1659215976Sjmallett The Interrupt Pin register is writable through PEM(0..1)_CFG_WR. 1660215976Sjmallett In a single-function configuration, only INTA is used. 1661215976Sjmallett Therefore, the application must not change this field. */ 1662215976Sjmallett uint32_t il : 8; /**< Interrupt Line */ 1663215976Sjmallett#else 1664215976Sjmallett uint32_t il : 8; 1665215976Sjmallett uint32_t inta : 8; 1666215976Sjmallett uint32_t pere : 1; 1667215976Sjmallett uint32_t see : 1; 1668215976Sjmallett uint32_t isae : 1; 1669215976Sjmallett uint32_t vgae : 1; 1670215976Sjmallett uint32_t vga16d : 1; 1671215976Sjmallett uint32_t mam : 1; 1672215976Sjmallett uint32_t sbrst : 1; 1673215976Sjmallett uint32_t fbbe : 1; 1674215976Sjmallett uint32_t pdt : 1; 1675215976Sjmallett uint32_t sdt : 1; 1676215976Sjmallett uint32_t dts : 1; 1677215976Sjmallett uint32_t dtsees : 1; 1678215976Sjmallett uint32_t reserved_28_31 : 4; 1679215976Sjmallett#endif 1680215976Sjmallett } s; 1681215976Sjmallett struct cvmx_pciercx_cfg015_s cn52xx; 1682215976Sjmallett struct cvmx_pciercx_cfg015_s cn52xxp1; 1683215976Sjmallett struct cvmx_pciercx_cfg015_s cn56xx; 1684215976Sjmallett struct cvmx_pciercx_cfg015_s cn56xxp1; 1685215976Sjmallett struct cvmx_pciercx_cfg015_s cn63xx; 1686215976Sjmallett struct cvmx_pciercx_cfg015_s cn63xxp1; 1687215976Sjmallett}; 1688215976Sjmalletttypedef union cvmx_pciercx_cfg015 cvmx_pciercx_cfg015_t; 1689215976Sjmallett 1690215976Sjmallett/** 1691215976Sjmallett * cvmx_pcierc#_cfg016 1692215976Sjmallett * 1693215976Sjmallett * PCIE_CFG016 = Seventeenth 32-bits of PCIE type 1 config space 1694215976Sjmallett * (Power Management Capability ID/ 1695215976Sjmallett * Power Management Next Item Pointer/ 1696215976Sjmallett * Power Management Capabilities Register) 1697215976Sjmallett */ 1698215976Sjmallettunion cvmx_pciercx_cfg016 1699215976Sjmallett{ 1700215976Sjmallett uint32_t u32; 1701215976Sjmallett struct cvmx_pciercx_cfg016_s 1702215976Sjmallett { 1703215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1704215976Sjmallett uint32_t pmes : 5; /**< PME_Support 1705215976Sjmallett A value of 0 for any bit indicates that the 1706215976Sjmallett device (or function) is not capable of generating PME Messages 1707215976Sjmallett while in that power state: 1708215976Sjmallett o Bit 11: If set, PME Messages can be generated from D0 1709215976Sjmallett o Bit 12: If set, PME Messages can be generated from D1 1710215976Sjmallett o Bit 13: If set, PME Messages can be generated from D2 1711215976Sjmallett o Bit 14: If set, PME Messages can be generated from D3hot 1712215976Sjmallett o Bit 15: If set, PME Messages can be generated from D3cold 1713215976Sjmallett The PME_Support field is writable through PEM(0..1)_CFG_WR. 1714215976Sjmallett However, the application must not change this field. */ 1715215976Sjmallett uint32_t d2s : 1; /**< D2 Support, writable through PEM(0..1)_CFG_WR 1716215976Sjmallett However, the application must not change this field. */ 1717215976Sjmallett uint32_t d1s : 1; /**< D1 Support, writable through PEM(0..1)_CFG_WR 1718215976Sjmallett However, the application must not change this field. */ 1719215976Sjmallett uint32_t auxc : 3; /**< AUX Current, writable through PEM(0..1)_CFG_WR 1720215976Sjmallett However, the application must not change this field. */ 1721215976Sjmallett uint32_t dsi : 1; /**< Device Specific Initialization (DSI), writable through PEM(0..1)_CFG_WR 1722215976Sjmallett However, the application must not change this field. */ 1723215976Sjmallett uint32_t reserved_20_20 : 1; 1724215976Sjmallett uint32_t pme_clock : 1; /**< PME Clock, hardwired to 0 */ 1725215976Sjmallett uint32_t pmsv : 3; /**< Power Management Specification Version, writable through PEM(0..1)_CFG_WR 1726215976Sjmallett However, the application must not change this field. */ 1727215976Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer 1728215976Sjmallett Points to the MSI capabilities by default, writable 1729215976Sjmallett through PEM(0..1)_CFG_WR. */ 1730215976Sjmallett uint32_t pmcid : 8; /**< Power Management Capability ID */ 1731215976Sjmallett#else 1732215976Sjmallett uint32_t pmcid : 8; 1733215976Sjmallett uint32_t ncp : 8; 1734215976Sjmallett uint32_t pmsv : 3; 1735215976Sjmallett uint32_t pme_clock : 1; 1736215976Sjmallett uint32_t reserved_20_20 : 1; 1737215976Sjmallett uint32_t dsi : 1; 1738215976Sjmallett uint32_t auxc : 3; 1739215976Sjmallett uint32_t d1s : 1; 1740215976Sjmallett uint32_t d2s : 1; 1741215976Sjmallett uint32_t pmes : 5; 1742215976Sjmallett#endif 1743215976Sjmallett } s; 1744215976Sjmallett struct cvmx_pciercx_cfg016_s cn52xx; 1745215976Sjmallett struct cvmx_pciercx_cfg016_s cn52xxp1; 1746215976Sjmallett struct cvmx_pciercx_cfg016_s cn56xx; 1747215976Sjmallett struct cvmx_pciercx_cfg016_s cn56xxp1; 1748215976Sjmallett struct cvmx_pciercx_cfg016_s cn63xx; 1749215976Sjmallett struct cvmx_pciercx_cfg016_s cn63xxp1; 1750215976Sjmallett}; 1751215976Sjmalletttypedef union cvmx_pciercx_cfg016 cvmx_pciercx_cfg016_t; 1752215976Sjmallett 1753215976Sjmallett/** 1754215976Sjmallett * cvmx_pcierc#_cfg017 1755215976Sjmallett * 1756215976Sjmallett * PCIE_CFG017 = Eighteenth 32-bits of PCIE type 1 config space (Power Management Control and Status Register) 1757215976Sjmallett * 1758215976Sjmallett */ 1759215976Sjmallettunion cvmx_pciercx_cfg017 1760215976Sjmallett{ 1761215976Sjmallett uint32_t u32; 1762215976Sjmallett struct cvmx_pciercx_cfg017_s 1763215976Sjmallett { 1764215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1765215976Sjmallett uint32_t pmdia : 8; /**< Data register for additional information (not supported) */ 1766215976Sjmallett uint32_t bpccee : 1; /**< Bus Power/Clock Control Enable, hardwired to 0 */ 1767215976Sjmallett uint32_t bd3h : 1; /**< B2/B3 Support, hardwired to 0 */ 1768215976Sjmallett uint32_t reserved_16_21 : 6; 1769215976Sjmallett uint32_t pmess : 1; /**< PME Status 1770215976Sjmallett Indicates if a previously enabled PME event occurred or not. */ 1771215976Sjmallett uint32_t pmedsia : 2; /**< Data Scale (not supported) */ 1772215976Sjmallett uint32_t pmds : 4; /**< Data Select (not supported) */ 1773215976Sjmallett uint32_t pmeens : 1; /**< PME Enable 1774215976Sjmallett A value of 1 indicates that the device is enabled to 1775215976Sjmallett generate PME. */ 1776215976Sjmallett uint32_t reserved_4_7 : 4; 1777215976Sjmallett uint32_t nsr : 1; /**< No Soft Reset, writable through PEM(0..1)_CFG_WR 1778215976Sjmallett However, the application must not change this field. */ 1779215976Sjmallett uint32_t reserved_2_2 : 1; 1780215976Sjmallett uint32_t ps : 2; /**< Power State 1781215976Sjmallett Controls the device power state: 1782215976Sjmallett o 00b: D0 1783215976Sjmallett o 01b: D1 1784215976Sjmallett o 10b: D2 1785215976Sjmallett o 11b: D3 1786215976Sjmallett The written value is ignored if the specific state is 1787215976Sjmallett not supported. */ 1788215976Sjmallett#else 1789215976Sjmallett uint32_t ps : 2; 1790215976Sjmallett uint32_t reserved_2_2 : 1; 1791215976Sjmallett uint32_t nsr : 1; 1792215976Sjmallett uint32_t reserved_4_7 : 4; 1793215976Sjmallett uint32_t pmeens : 1; 1794215976Sjmallett uint32_t pmds : 4; 1795215976Sjmallett uint32_t pmedsia : 2; 1796215976Sjmallett uint32_t pmess : 1; 1797215976Sjmallett uint32_t reserved_16_21 : 6; 1798215976Sjmallett uint32_t bd3h : 1; 1799215976Sjmallett uint32_t bpccee : 1; 1800215976Sjmallett uint32_t pmdia : 8; 1801215976Sjmallett#endif 1802215976Sjmallett } s; 1803215976Sjmallett struct cvmx_pciercx_cfg017_s cn52xx; 1804215976Sjmallett struct cvmx_pciercx_cfg017_s cn52xxp1; 1805215976Sjmallett struct cvmx_pciercx_cfg017_s cn56xx; 1806215976Sjmallett struct cvmx_pciercx_cfg017_s cn56xxp1; 1807215976Sjmallett struct cvmx_pciercx_cfg017_s cn63xx; 1808215976Sjmallett struct cvmx_pciercx_cfg017_s cn63xxp1; 1809215976Sjmallett}; 1810215976Sjmalletttypedef union cvmx_pciercx_cfg017 cvmx_pciercx_cfg017_t; 1811215976Sjmallett 1812215976Sjmallett/** 1813215976Sjmallett * cvmx_pcierc#_cfg020 1814215976Sjmallett * 1815215976Sjmallett * PCIE_CFG020 = Twenty-first 32-bits of PCIE type 1 config space 1816215976Sjmallett * (MSI Capability ID/ 1817215976Sjmallett * MSI Next Item Pointer/ 1818215976Sjmallett * MSI Control Register) 1819215976Sjmallett */ 1820215976Sjmallettunion cvmx_pciercx_cfg020 1821215976Sjmallett{ 1822215976Sjmallett uint32_t u32; 1823215976Sjmallett struct cvmx_pciercx_cfg020_s 1824215976Sjmallett { 1825215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1826215976Sjmallett uint32_t reserved_24_31 : 8; 1827215976Sjmallett uint32_t m64 : 1; /**< 64-bit Address Capable, writable through PEM(0..1)_CFG_WR 1828215976Sjmallett However, the application must not change this field. */ 1829215976Sjmallett uint32_t mme : 3; /**< Multiple Message Enabled 1830215976Sjmallett Indicates that multiple Message mode is enabled by system 1831215976Sjmallett software. The number of Messages enabled must be less than 1832215976Sjmallett or equal to the Multiple Message Capable value. */ 1833215976Sjmallett uint32_t mmc : 3; /**< Multiple Message Capable, writable through PEM(0..1)_CFG_WR 1834215976Sjmallett However, the application must not change this field. */ 1835215976Sjmallett uint32_t msien : 1; /**< MSI Enabled 1836215976Sjmallett When set, INTx must be disabled. 1837215976Sjmallett This bit must never be set, as internal-MSI is not supported in 1838215976Sjmallett RC mode. (Note that this has no effect on external MSI, which 1839215976Sjmallett will be commonly used in RC mode.) */ 1840215976Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer 1841215976Sjmallett Points to PCI Express Capabilities by default, 1842215976Sjmallett writable through PEM(0..1)_CFG_WR. 1843215976Sjmallett However, the application must not change this field. */ 1844215976Sjmallett uint32_t msicid : 8; /**< MSI Capability ID */ 1845215976Sjmallett#else 1846215976Sjmallett uint32_t msicid : 8; 1847215976Sjmallett uint32_t ncp : 8; 1848215976Sjmallett uint32_t msien : 1; 1849215976Sjmallett uint32_t mmc : 3; 1850215976Sjmallett uint32_t mme : 3; 1851215976Sjmallett uint32_t m64 : 1; 1852215976Sjmallett uint32_t reserved_24_31 : 8; 1853215976Sjmallett#endif 1854215976Sjmallett } s; 1855215976Sjmallett struct cvmx_pciercx_cfg020_s cn52xx; 1856215976Sjmallett struct cvmx_pciercx_cfg020_s cn52xxp1; 1857215976Sjmallett struct cvmx_pciercx_cfg020_s cn56xx; 1858215976Sjmallett struct cvmx_pciercx_cfg020_s cn56xxp1; 1859215976Sjmallett struct cvmx_pciercx_cfg020_s cn63xx; 1860215976Sjmallett struct cvmx_pciercx_cfg020_s cn63xxp1; 1861215976Sjmallett}; 1862215976Sjmalletttypedef union cvmx_pciercx_cfg020 cvmx_pciercx_cfg020_t; 1863215976Sjmallett 1864215976Sjmallett/** 1865215976Sjmallett * cvmx_pcierc#_cfg021 1866215976Sjmallett * 1867215976Sjmallett * PCIE_CFG021 = Twenty-second 32-bits of PCIE type 1 config space (MSI Lower 32 Bits Address Register) 1868215976Sjmallett * 1869215976Sjmallett */ 1870215976Sjmallettunion cvmx_pciercx_cfg021 1871215976Sjmallett{ 1872215976Sjmallett uint32_t u32; 1873215976Sjmallett struct cvmx_pciercx_cfg021_s 1874215976Sjmallett { 1875215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1876215976Sjmallett uint32_t lmsi : 30; /**< Lower 32-bit Address */ 1877215976Sjmallett uint32_t reserved_0_1 : 2; 1878215976Sjmallett#else 1879215976Sjmallett uint32_t reserved_0_1 : 2; 1880215976Sjmallett uint32_t lmsi : 30; 1881215976Sjmallett#endif 1882215976Sjmallett } s; 1883215976Sjmallett struct cvmx_pciercx_cfg021_s cn52xx; 1884215976Sjmallett struct cvmx_pciercx_cfg021_s cn52xxp1; 1885215976Sjmallett struct cvmx_pciercx_cfg021_s cn56xx; 1886215976Sjmallett struct cvmx_pciercx_cfg021_s cn56xxp1; 1887215976Sjmallett struct cvmx_pciercx_cfg021_s cn63xx; 1888215976Sjmallett struct cvmx_pciercx_cfg021_s cn63xxp1; 1889215976Sjmallett}; 1890215976Sjmalletttypedef union cvmx_pciercx_cfg021 cvmx_pciercx_cfg021_t; 1891215976Sjmallett 1892215976Sjmallett/** 1893215976Sjmallett * cvmx_pcierc#_cfg022 1894215976Sjmallett * 1895215976Sjmallett * PCIE_CFG022 = Twenty-third 32-bits of PCIE type 1 config space (MSI Upper 32 bits Address Register) 1896215976Sjmallett * 1897215976Sjmallett */ 1898215976Sjmallettunion cvmx_pciercx_cfg022 1899215976Sjmallett{ 1900215976Sjmallett uint32_t u32; 1901215976Sjmallett struct cvmx_pciercx_cfg022_s 1902215976Sjmallett { 1903215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1904215976Sjmallett uint32_t umsi : 32; /**< Upper 32-bit Address */ 1905215976Sjmallett#else 1906215976Sjmallett uint32_t umsi : 32; 1907215976Sjmallett#endif 1908215976Sjmallett } s; 1909215976Sjmallett struct cvmx_pciercx_cfg022_s cn52xx; 1910215976Sjmallett struct cvmx_pciercx_cfg022_s cn52xxp1; 1911215976Sjmallett struct cvmx_pciercx_cfg022_s cn56xx; 1912215976Sjmallett struct cvmx_pciercx_cfg022_s cn56xxp1; 1913215976Sjmallett struct cvmx_pciercx_cfg022_s cn63xx; 1914215976Sjmallett struct cvmx_pciercx_cfg022_s cn63xxp1; 1915215976Sjmallett}; 1916215976Sjmalletttypedef union cvmx_pciercx_cfg022 cvmx_pciercx_cfg022_t; 1917215976Sjmallett 1918215976Sjmallett/** 1919215976Sjmallett * cvmx_pcierc#_cfg023 1920215976Sjmallett * 1921215976Sjmallett * PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 1 config space (MSI Data Register) 1922215976Sjmallett * 1923215976Sjmallett */ 1924215976Sjmallettunion cvmx_pciercx_cfg023 1925215976Sjmallett{ 1926215976Sjmallett uint32_t u32; 1927215976Sjmallett struct cvmx_pciercx_cfg023_s 1928215976Sjmallett { 1929215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1930215976Sjmallett uint32_t reserved_16_31 : 16; 1931215976Sjmallett uint32_t msimd : 16; /**< MSI Data 1932215976Sjmallett Pattern assigned by system software, bits [4:0] are Or-ed with 1933215976Sjmallett MSI_VECTOR to generate 32 MSI Messages per function. */ 1934215976Sjmallett#else 1935215976Sjmallett uint32_t msimd : 16; 1936215976Sjmallett uint32_t reserved_16_31 : 16; 1937215976Sjmallett#endif 1938215976Sjmallett } s; 1939215976Sjmallett struct cvmx_pciercx_cfg023_s cn52xx; 1940215976Sjmallett struct cvmx_pciercx_cfg023_s cn52xxp1; 1941215976Sjmallett struct cvmx_pciercx_cfg023_s cn56xx; 1942215976Sjmallett struct cvmx_pciercx_cfg023_s cn56xxp1; 1943215976Sjmallett struct cvmx_pciercx_cfg023_s cn63xx; 1944215976Sjmallett struct cvmx_pciercx_cfg023_s cn63xxp1; 1945215976Sjmallett}; 1946215976Sjmalletttypedef union cvmx_pciercx_cfg023 cvmx_pciercx_cfg023_t; 1947215976Sjmallett 1948215976Sjmallett/** 1949215976Sjmallett * cvmx_pcierc#_cfg028 1950215976Sjmallett * 1951215976Sjmallett * PCIE_CFG028 = Twenty-ninth 32-bits of PCIE type 1 config space 1952215976Sjmallett * (PCI Express Capabilities List Register/ 1953215976Sjmallett * PCI Express Capabilities Register) 1954215976Sjmallett */ 1955215976Sjmallettunion cvmx_pciercx_cfg028 1956215976Sjmallett{ 1957215976Sjmallett uint32_t u32; 1958215976Sjmallett struct cvmx_pciercx_cfg028_s 1959215976Sjmallett { 1960215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1961215976Sjmallett uint32_t reserved_30_31 : 2; 1962215976Sjmallett uint32_t imn : 5; /**< Interrupt Message Number 1963215976Sjmallett Updated by hardware, writable through PEM(0..1)_CFG_WR. 1964215976Sjmallett However, the application must not change this field. */ 1965215976Sjmallett uint32_t si : 1; /**< Slot Implemented 1966215976Sjmallett This bit is writable through PEM(0..1)_CFG_WR. 1967215976Sjmallett However, it must 0 for an 1968215976Sjmallett Endpoint device. Therefore, the application must not write a 1969215976Sjmallett 1 to this bit. */ 1970215976Sjmallett uint32_t dpt : 4; /**< Device Port Type */ 1971215976Sjmallett uint32_t pciecv : 4; /**< PCI Express Capability Version */ 1972215976Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer 1973215976Sjmallett writable through PEM(0..1)_CFG_WR. 1974215976Sjmallett However, the application must not change this field. */ 1975215976Sjmallett uint32_t pcieid : 8; /**< PCIE Capability ID */ 1976215976Sjmallett#else 1977215976Sjmallett uint32_t pcieid : 8; 1978215976Sjmallett uint32_t ncp : 8; 1979215976Sjmallett uint32_t pciecv : 4; 1980215976Sjmallett uint32_t dpt : 4; 1981215976Sjmallett uint32_t si : 1; 1982215976Sjmallett uint32_t imn : 5; 1983215976Sjmallett uint32_t reserved_30_31 : 2; 1984215976Sjmallett#endif 1985215976Sjmallett } s; 1986215976Sjmallett struct cvmx_pciercx_cfg028_s cn52xx; 1987215976Sjmallett struct cvmx_pciercx_cfg028_s cn52xxp1; 1988215976Sjmallett struct cvmx_pciercx_cfg028_s cn56xx; 1989215976Sjmallett struct cvmx_pciercx_cfg028_s cn56xxp1; 1990215976Sjmallett struct cvmx_pciercx_cfg028_s cn63xx; 1991215976Sjmallett struct cvmx_pciercx_cfg028_s cn63xxp1; 1992215976Sjmallett}; 1993215976Sjmalletttypedef union cvmx_pciercx_cfg028 cvmx_pciercx_cfg028_t; 1994215976Sjmallett 1995215976Sjmallett/** 1996215976Sjmallett * cvmx_pcierc#_cfg029 1997215976Sjmallett * 1998215976Sjmallett * PCIE_CFG029 = Thirtieth 32-bits of PCIE type 1 config space (Device Capabilities Register) 1999215976Sjmallett * 2000215976Sjmallett */ 2001215976Sjmallettunion cvmx_pciercx_cfg029 2002215976Sjmallett{ 2003215976Sjmallett uint32_t u32; 2004215976Sjmallett struct cvmx_pciercx_cfg029_s 2005215976Sjmallett { 2006215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2007215976Sjmallett uint32_t reserved_28_31 : 4; 2008215976Sjmallett uint32_t cspls : 2; /**< Captured Slot Power Limit Scale 2009215976Sjmallett Not applicable for RC port, upstream port only. */ 2010215976Sjmallett uint32_t csplv : 8; /**< Captured Slot Power Limit Value 2011215976Sjmallett Not applicable for RC port, upstream port only. */ 2012215976Sjmallett uint32_t reserved_16_17 : 2; 2013215976Sjmallett uint32_t rber : 1; /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR 2014215976Sjmallett However, the application must not change this field. */ 2015215976Sjmallett uint32_t reserved_12_14 : 3; 2016215976Sjmallett uint32_t el1al : 3; /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR 2017215976Sjmallett Must be 0x0 for non-endpoint devices. */ 2018215976Sjmallett uint32_t el0al : 3; /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR 2019215976Sjmallett Must be 0x0 for non-endpoint devices. */ 2020215976Sjmallett uint32_t etfs : 1; /**< Extended Tag Field Supported 2021215976Sjmallett This bit is writable through PEM(0..1)_CFG_WR. 2022215976Sjmallett However, the application 2023215976Sjmallett must not write a 1 to this bit. */ 2024215976Sjmallett uint32_t pfs : 2; /**< Phantom Function Supported 2025215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 2026215976Sjmallett However, Phantom 2027215976Sjmallett Function is not supported. Therefore, the application must not 2028215976Sjmallett write any value other than 0x0 to this field. */ 2029215976Sjmallett uint32_t mpss : 3; /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR 2030215976Sjmallett However, the application must not change this field. */ 2031215976Sjmallett#else 2032215976Sjmallett uint32_t mpss : 3; 2033215976Sjmallett uint32_t pfs : 2; 2034215976Sjmallett uint32_t etfs : 1; 2035215976Sjmallett uint32_t el0al : 3; 2036215976Sjmallett uint32_t el1al : 3; 2037215976Sjmallett uint32_t reserved_12_14 : 3; 2038215976Sjmallett uint32_t rber : 1; 2039215976Sjmallett uint32_t reserved_16_17 : 2; 2040215976Sjmallett uint32_t csplv : 8; 2041215976Sjmallett uint32_t cspls : 2; 2042215976Sjmallett uint32_t reserved_28_31 : 4; 2043215976Sjmallett#endif 2044215976Sjmallett } s; 2045215976Sjmallett struct cvmx_pciercx_cfg029_s cn52xx; 2046215976Sjmallett struct cvmx_pciercx_cfg029_s cn52xxp1; 2047215976Sjmallett struct cvmx_pciercx_cfg029_s cn56xx; 2048215976Sjmallett struct cvmx_pciercx_cfg029_s cn56xxp1; 2049215976Sjmallett struct cvmx_pciercx_cfg029_s cn63xx; 2050215976Sjmallett struct cvmx_pciercx_cfg029_s cn63xxp1; 2051215976Sjmallett}; 2052215976Sjmalletttypedef union cvmx_pciercx_cfg029 cvmx_pciercx_cfg029_t; 2053215976Sjmallett 2054215976Sjmallett/** 2055215976Sjmallett * cvmx_pcierc#_cfg030 2056215976Sjmallett * 2057215976Sjmallett * PCIE_CFG030 = Thirty-first 32-bits of PCIE type 1 config space 2058215976Sjmallett * (Device Control Register/Device Status Register) 2059215976Sjmallett */ 2060215976Sjmallettunion cvmx_pciercx_cfg030 2061215976Sjmallett{ 2062215976Sjmallett uint32_t u32; 2063215976Sjmallett struct cvmx_pciercx_cfg030_s 2064215976Sjmallett { 2065215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2066215976Sjmallett uint32_t reserved_22_31 : 10; 2067215976Sjmallett uint32_t tp : 1; /**< Transaction Pending 2068215976Sjmallett Set to 1 when Non-Posted Requests are not yet completed 2069215976Sjmallett and clear when they are completed. */ 2070215976Sjmallett uint32_t ap_d : 1; /**< Aux Power Detected 2071215976Sjmallett Set to 1 if Aux power detected. */ 2072215976Sjmallett uint32_t ur_d : 1; /**< Unsupported Request Detected 2073215976Sjmallett Errors are logged in this register regardless of whether 2074215976Sjmallett error reporting is enabled in the Device Control register. 2075215976Sjmallett UR_D occurs when we receive something we don't support. 2076215976Sjmallett Unsupported requests are Nonfatal errors, so UR_D should 2077215976Sjmallett cause NFE_D. Receiving a vendor defined message should 2078215976Sjmallett cause an unsupported request. */ 2079215976Sjmallett uint32_t fe_d : 1; /**< Fatal Error Detected 2080215976Sjmallett Errors are logged in this register regardless of whether 2081215976Sjmallett error reporting is enabled in the Device Control register. 2082215976Sjmallett FE_D is set if receive any of the errors in PCIE_CFG066 that 2083215976Sjmallett has a severity set to Fatal. Malformed TLP's generally fit 2084215976Sjmallett into this category. */ 2085215976Sjmallett uint32_t nfe_d : 1; /**< Non-Fatal Error detected 2086215976Sjmallett Errors are logged in this register regardless of whether 2087215976Sjmallett error reporting is enabled in the Device Control register. 2088215976Sjmallett NFE_D is set if we receive any of the errors in PCIE_CFG066 2089215976Sjmallett that has a severity set to Nonfatal and does NOT meet Advisory 2090215976Sjmallett Nonfatal criteria , which 2091215976Sjmallett most poisoned TLP's should be. */ 2092215976Sjmallett uint32_t ce_d : 1; /**< Correctable Error Detected 2093215976Sjmallett Errors are logged in this register regardless of whether 2094215976Sjmallett error reporting is enabled in the Device Control register. 2095215976Sjmallett CE_D is set if we receive any of the errors in PCIE_CFG068 2096215976Sjmallett for example a Replay Timer Timeout. Also, it can be set if 2097215976Sjmallett we get any of the errors in PCIE_CFG066 that has a severity 2098215976Sjmallett set to Nonfatal and meets the Advisory Nonfatal criteria, 2099215976Sjmallett which most ECRC errors should be. */ 2100215976Sjmallett uint32_t reserved_15_15 : 1; 2101215976Sjmallett uint32_t mrrs : 3; /**< Max Read Request Size 2102215976Sjmallett 0 = 128B 2103215976Sjmallett 1 = 256B 2104215976Sjmallett 2 = 512B 2105215976Sjmallett 3 = 1024B 2106215976Sjmallett 4 = 2048B 2107215976Sjmallett 5 = 4096B 2108215976Sjmallett Note: SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] and 2109215976Sjmallett also must be set properly. 2110215976Sjmallett SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] must 2111215976Sjmallett not exceed the desired max read request size. */ 2112215976Sjmallett uint32_t ns_en : 1; /**< Enable No Snoop */ 2113215976Sjmallett uint32_t ap_en : 1; /**< AUX Power PM Enable */ 2114215976Sjmallett uint32_t pf_en : 1; /**< Phantom Function Enable 2115215976Sjmallett This bit should never be set - OCTEON requests never use 2116215976Sjmallett phantom functions. */ 2117215976Sjmallett uint32_t etf_en : 1; /**< Extended Tag Field Enable 2118215976Sjmallett This bit should never be set - OCTEON requests never use 2119215976Sjmallett extended tags. */ 2120215976Sjmallett uint32_t mps : 3; /**< Max Payload Size 2121215976Sjmallett Legal values: 2122215976Sjmallett 0 = 128B 2123215976Sjmallett 1 = 256B 2124215976Sjmallett Larger sizes not supported. 2125215976Sjmallett Note: Both PCI Express Ports must be set to the same value 2126215976Sjmallett for Peer-to-Peer to function properly. 2127215976Sjmallett Note: DPI_SLI_PRT#_CFG[MPS] must also be set to the same 2128215976Sjmallett value for proper functionality. */ 2129215976Sjmallett uint32_t ro_en : 1; /**< Enable Relaxed Ordering */ 2130215976Sjmallett uint32_t ur_en : 1; /**< Unsupported Request Reporting Enable */ 2131215976Sjmallett uint32_t fe_en : 1; /**< Fatal Error Reporting Enable */ 2132215976Sjmallett uint32_t nfe_en : 1; /**< Non-Fatal Error Reporting Enable */ 2133215976Sjmallett uint32_t ce_en : 1; /**< Correctable Error Reporting Enable */ 2134215976Sjmallett#else 2135215976Sjmallett uint32_t ce_en : 1; 2136215976Sjmallett uint32_t nfe_en : 1; 2137215976Sjmallett uint32_t fe_en : 1; 2138215976Sjmallett uint32_t ur_en : 1; 2139215976Sjmallett uint32_t ro_en : 1; 2140215976Sjmallett uint32_t mps : 3; 2141215976Sjmallett uint32_t etf_en : 1; 2142215976Sjmallett uint32_t pf_en : 1; 2143215976Sjmallett uint32_t ap_en : 1; 2144215976Sjmallett uint32_t ns_en : 1; 2145215976Sjmallett uint32_t mrrs : 3; 2146215976Sjmallett uint32_t reserved_15_15 : 1; 2147215976Sjmallett uint32_t ce_d : 1; 2148215976Sjmallett uint32_t nfe_d : 1; 2149215976Sjmallett uint32_t fe_d : 1; 2150215976Sjmallett uint32_t ur_d : 1; 2151215976Sjmallett uint32_t ap_d : 1; 2152215976Sjmallett uint32_t tp : 1; 2153215976Sjmallett uint32_t reserved_22_31 : 10; 2154215976Sjmallett#endif 2155215976Sjmallett } s; 2156215976Sjmallett struct cvmx_pciercx_cfg030_s cn52xx; 2157215976Sjmallett struct cvmx_pciercx_cfg030_s cn52xxp1; 2158215976Sjmallett struct cvmx_pciercx_cfg030_s cn56xx; 2159215976Sjmallett struct cvmx_pciercx_cfg030_s cn56xxp1; 2160215976Sjmallett struct cvmx_pciercx_cfg030_s cn63xx; 2161215976Sjmallett struct cvmx_pciercx_cfg030_s cn63xxp1; 2162215976Sjmallett}; 2163215976Sjmalletttypedef union cvmx_pciercx_cfg030 cvmx_pciercx_cfg030_t; 2164215976Sjmallett 2165215976Sjmallett/** 2166215976Sjmallett * cvmx_pcierc#_cfg031 2167215976Sjmallett * 2168215976Sjmallett * PCIE_CFG031 = Thirty-second 32-bits of PCIE type 1 config space 2169215976Sjmallett * (Link Capabilities Register) 2170215976Sjmallett */ 2171215976Sjmallettunion cvmx_pciercx_cfg031 2172215976Sjmallett{ 2173215976Sjmallett uint32_t u32; 2174215976Sjmallett struct cvmx_pciercx_cfg031_s 2175215976Sjmallett { 2176215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2177215976Sjmallett uint32_t pnum : 8; /**< Port Number, writable through PEM(0..1)_CFG_WR 2178215976Sjmallett However, the application must not change this field. */ 2179215976Sjmallett uint32_t reserved_22_23 : 2; 2180215976Sjmallett uint32_t lbnc : 1; /**< Link Bandwith Notification Capability */ 2181215976Sjmallett uint32_t dllarc : 1; /**< Data Link Layer Active Reporting Capable 2182215976Sjmallett Set to 1 for Root Complex devices and 0 for Endpoint devices. */ 2183215976Sjmallett uint32_t sderc : 1; /**< Surprise Down Error Reporting Capable 2184215976Sjmallett Not supported, hardwired to 0x0. */ 2185215976Sjmallett uint32_t cpm : 1; /**< Clock Power Management 2186215976Sjmallett The default value is the value you specify during hardware 2187215976Sjmallett configuration, writable through PEM(0..1)_CFG_WR. 2188215976Sjmallett However, the application must not change this field. */ 2189215976Sjmallett uint32_t l1el : 3; /**< L1 Exit Latency 2190215976Sjmallett The default value is the value you specify during hardware 2191215976Sjmallett configuration, writable through PEM(0..1)_CFG_WR. 2192215976Sjmallett However, the application must not change this field. */ 2193215976Sjmallett uint32_t l0el : 3; /**< L0s Exit Latency 2194215976Sjmallett The default value is the value you specify during hardware 2195215976Sjmallett configuration, writable through PEM(0..1)_CFG_WR. 2196215976Sjmallett However, the application must not change this field. */ 2197215976Sjmallett uint32_t aslpms : 2; /**< Active State Link PM Support 2198215976Sjmallett The default value is the value you specify during hardware 2199215976Sjmallett configuration, writable through PEM(0..1)_CFG_WR. 2200215976Sjmallett However, the application must not change this field. */ 2201215976Sjmallett uint32_t mlw : 6; /**< Maximum Link Width 2202215976Sjmallett The default value is the value you specify during hardware 2203215976Sjmallett configuration (x1, x4, x8, or x16), writable through PEM(0..1)_CFG_WR. */ 2204215976Sjmallett uint32_t mls : 4; /**< Maximum Link Speed 2205215976Sjmallett The following values are accepted: 2206215976Sjmallett 0001b: 2.5 GHz supported 2207215976Sjmallett 0010b: 5.0 GHz and 2.5 GHz supported 2208215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 2209215976Sjmallett However, the application must not change this field. */ 2210215976Sjmallett#else 2211215976Sjmallett uint32_t mls : 4; 2212215976Sjmallett uint32_t mlw : 6; 2213215976Sjmallett uint32_t aslpms : 2; 2214215976Sjmallett uint32_t l0el : 3; 2215215976Sjmallett uint32_t l1el : 3; 2216215976Sjmallett uint32_t cpm : 1; 2217215976Sjmallett uint32_t sderc : 1; 2218215976Sjmallett uint32_t dllarc : 1; 2219215976Sjmallett uint32_t lbnc : 1; 2220215976Sjmallett uint32_t reserved_22_23 : 2; 2221215976Sjmallett uint32_t pnum : 8; 2222215976Sjmallett#endif 2223215976Sjmallett } s; 2224215976Sjmallett struct cvmx_pciercx_cfg031_s cn52xx; 2225215976Sjmallett struct cvmx_pciercx_cfg031_s cn52xxp1; 2226215976Sjmallett struct cvmx_pciercx_cfg031_s cn56xx; 2227215976Sjmallett struct cvmx_pciercx_cfg031_s cn56xxp1; 2228215976Sjmallett struct cvmx_pciercx_cfg031_s cn63xx; 2229215976Sjmallett struct cvmx_pciercx_cfg031_s cn63xxp1; 2230215976Sjmallett}; 2231215976Sjmalletttypedef union cvmx_pciercx_cfg031 cvmx_pciercx_cfg031_t; 2232215976Sjmallett 2233215976Sjmallett/** 2234215976Sjmallett * cvmx_pcierc#_cfg032 2235215976Sjmallett * 2236215976Sjmallett * PCIE_CFG032 = Thirty-third 32-bits of PCIE type 1 config space 2237215976Sjmallett * (Link Control Register/Link Status Register) 2238215976Sjmallett */ 2239215976Sjmallettunion cvmx_pciercx_cfg032 2240215976Sjmallett{ 2241215976Sjmallett uint32_t u32; 2242215976Sjmallett struct cvmx_pciercx_cfg032_s 2243215976Sjmallett { 2244215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2245215976Sjmallett uint32_t lab : 1; /**< Link Autonomous Bandwidth Status */ 2246215976Sjmallett uint32_t lbm : 1; /**< Link Bandwidth Management Status */ 2247215976Sjmallett uint32_t dlla : 1; /**< Data Link Layer Active */ 2248215976Sjmallett uint32_t scc : 1; /**< Slot Clock Configuration 2249215976Sjmallett Indicates that the component uses the same physical reference 2250215976Sjmallett clock that the platform provides on the connector. The default 2251215976Sjmallett value is the value you select during hardware configuration, 2252215976Sjmallett writable through PEM(0..1)_CFG_WR. 2253215976Sjmallett However, the application must not change this field. */ 2254215976Sjmallett uint32_t lt : 1; /**< Link Training */ 2255215976Sjmallett uint32_t reserved_26_26 : 1; 2256215976Sjmallett uint32_t nlw : 6; /**< Negotiated Link Width 2257215976Sjmallett Set automatically by hardware after Link initialization. */ 2258215976Sjmallett uint32_t ls : 4; /**< Link Speed 2259215976Sjmallett The negotiated Link speed: 2.5 Gbps */ 2260215976Sjmallett uint32_t reserved_12_15 : 4; 2261215976Sjmallett uint32_t lab_int_enb : 1; /**< Link Autonomous Bandwidth Interrupt Enable 2262215976Sjmallett This interrupt is for Gen2 and is not supported. This bit should 2263215976Sjmallett always be written to zero. */ 2264215976Sjmallett uint32_t lbm_int_enb : 1; /**< Link Bandwidth Management Interrupt Enable 2265215976Sjmallett This interrupt is for Gen2 and is not supported. This bit should 2266215976Sjmallett always be written to zero. */ 2267215976Sjmallett uint32_t hawd : 1; /**< Hardware Autonomous Width Disable 2268215976Sjmallett (Not Supported) */ 2269215976Sjmallett uint32_t ecpm : 1; /**< Enable Clock Power Management 2270215976Sjmallett Hardwired to 0 if Clock Power Management is disabled in 2271215976Sjmallett the Link Capabilities register. */ 2272215976Sjmallett uint32_t es : 1; /**< Extended Synch */ 2273215976Sjmallett uint32_t ccc : 1; /**< Common Clock Configuration */ 2274215976Sjmallett uint32_t rl : 1; /**< Retrain Link */ 2275215976Sjmallett uint32_t ld : 1; /**< Link Disable */ 2276215976Sjmallett uint32_t rcb : 1; /**< Read Completion Boundary (RCB), writable through PEM(0..1)_CFG_WR 2277215976Sjmallett However, the application must not change this field 2278215976Sjmallett because an RCB of 64 bytes is not supported. */ 2279215976Sjmallett uint32_t reserved_2_2 : 1; 2280215976Sjmallett uint32_t aslpc : 2; /**< Active State Link PM Control */ 2281215976Sjmallett#else 2282215976Sjmallett uint32_t aslpc : 2; 2283215976Sjmallett uint32_t reserved_2_2 : 1; 2284215976Sjmallett uint32_t rcb : 1; 2285215976Sjmallett uint32_t ld : 1; 2286215976Sjmallett uint32_t rl : 1; 2287215976Sjmallett uint32_t ccc : 1; 2288215976Sjmallett uint32_t es : 1; 2289215976Sjmallett uint32_t ecpm : 1; 2290215976Sjmallett uint32_t hawd : 1; 2291215976Sjmallett uint32_t lbm_int_enb : 1; 2292215976Sjmallett uint32_t lab_int_enb : 1; 2293215976Sjmallett uint32_t reserved_12_15 : 4; 2294215976Sjmallett uint32_t ls : 4; 2295215976Sjmallett uint32_t nlw : 6; 2296215976Sjmallett uint32_t reserved_26_26 : 1; 2297215976Sjmallett uint32_t lt : 1; 2298215976Sjmallett uint32_t scc : 1; 2299215976Sjmallett uint32_t dlla : 1; 2300215976Sjmallett uint32_t lbm : 1; 2301215976Sjmallett uint32_t lab : 1; 2302215976Sjmallett#endif 2303215976Sjmallett } s; 2304215976Sjmallett struct cvmx_pciercx_cfg032_s cn52xx; 2305215976Sjmallett struct cvmx_pciercx_cfg032_s cn52xxp1; 2306215976Sjmallett struct cvmx_pciercx_cfg032_s cn56xx; 2307215976Sjmallett struct cvmx_pciercx_cfg032_s cn56xxp1; 2308215976Sjmallett struct cvmx_pciercx_cfg032_s cn63xx; 2309215976Sjmallett struct cvmx_pciercx_cfg032_s cn63xxp1; 2310215976Sjmallett}; 2311215976Sjmalletttypedef union cvmx_pciercx_cfg032 cvmx_pciercx_cfg032_t; 2312215976Sjmallett 2313215976Sjmallett/** 2314215976Sjmallett * cvmx_pcierc#_cfg033 2315215976Sjmallett * 2316215976Sjmallett * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 1 config space 2317215976Sjmallett * (Slot Capabilities Register) 2318215976Sjmallett */ 2319215976Sjmallettunion cvmx_pciercx_cfg033 2320215976Sjmallett{ 2321215976Sjmallett uint32_t u32; 2322215976Sjmallett struct cvmx_pciercx_cfg033_s 2323215976Sjmallett { 2324215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2325215976Sjmallett uint32_t ps_num : 13; /**< Physical Slot Number, writable through PEM(0..1)_CFG_WR 2326215976Sjmallett However, the application must not change this field. */ 2327215976Sjmallett uint32_t nccs : 1; /**< No Command Complete Support, writable through PEM(0..1)_CFG_WR 2328215976Sjmallett However, the application must not change this field. */ 2329215976Sjmallett uint32_t emip : 1; /**< Electromechanical Interlock Present, writable through PEM(0..1)_CFG_WR 2330215976Sjmallett However, the application must not change this field. */ 2331215976Sjmallett uint32_t sp_ls : 2; /**< Slot Power Limit Scale, writable through PEM(0..1)_CFG_WR. */ 2332215976Sjmallett uint32_t sp_lv : 8; /**< Slot Power Limit Value, writable through PEM(0..1)_CFG_WR. */ 2333215976Sjmallett uint32_t hp_c : 1; /**< Hot-Plug Capable, writable through PEM(0..1)_CFG_WR 2334215976Sjmallett However, the application must not change this field. */ 2335215976Sjmallett uint32_t hp_s : 1; /**< Hot-Plug Surprise, writable through PEM(0..1)_CFG_WR 2336215976Sjmallett However, the application must not change this field. */ 2337215976Sjmallett uint32_t pip : 1; /**< Power Indicator Present, writable through PEM(0..1)_CFG_WR 2338215976Sjmallett However, the application must not change this field. */ 2339215976Sjmallett uint32_t aip : 1; /**< Attention Indicator Present, writable through PEM(0..1)_CFG_WR 2340215976Sjmallett However, the application must not change this field. */ 2341215976Sjmallett uint32_t mrlsp : 1; /**< MRL Sensor Present, writable through PEM(0..1)_CFG_WR 2342215976Sjmallett However, the application must not change this field. */ 2343215976Sjmallett uint32_t pcp : 1; /**< Power Controller Present, writable through PEM(0..1)_CFG_WR 2344215976Sjmallett However, the application must not change this field. */ 2345215976Sjmallett uint32_t abp : 1; /**< Attention Button Present, writable through PEM(0..1)_CFG_WR 2346215976Sjmallett However, the application must not change this field. */ 2347215976Sjmallett#else 2348215976Sjmallett uint32_t abp : 1; 2349215976Sjmallett uint32_t pcp : 1; 2350215976Sjmallett uint32_t mrlsp : 1; 2351215976Sjmallett uint32_t aip : 1; 2352215976Sjmallett uint32_t pip : 1; 2353215976Sjmallett uint32_t hp_s : 1; 2354215976Sjmallett uint32_t hp_c : 1; 2355215976Sjmallett uint32_t sp_lv : 8; 2356215976Sjmallett uint32_t sp_ls : 2; 2357215976Sjmallett uint32_t emip : 1; 2358215976Sjmallett uint32_t nccs : 1; 2359215976Sjmallett uint32_t ps_num : 13; 2360215976Sjmallett#endif 2361215976Sjmallett } s; 2362215976Sjmallett struct cvmx_pciercx_cfg033_s cn52xx; 2363215976Sjmallett struct cvmx_pciercx_cfg033_s cn52xxp1; 2364215976Sjmallett struct cvmx_pciercx_cfg033_s cn56xx; 2365215976Sjmallett struct cvmx_pciercx_cfg033_s cn56xxp1; 2366215976Sjmallett struct cvmx_pciercx_cfg033_s cn63xx; 2367215976Sjmallett struct cvmx_pciercx_cfg033_s cn63xxp1; 2368215976Sjmallett}; 2369215976Sjmalletttypedef union cvmx_pciercx_cfg033 cvmx_pciercx_cfg033_t; 2370215976Sjmallett 2371215976Sjmallett/** 2372215976Sjmallett * cvmx_pcierc#_cfg034 2373215976Sjmallett * 2374215976Sjmallett * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 1 config space 2375215976Sjmallett * (Slot Control Register/Slot Status Register) 2376215976Sjmallett */ 2377215976Sjmallettunion cvmx_pciercx_cfg034 2378215976Sjmallett{ 2379215976Sjmallett uint32_t u32; 2380215976Sjmallett struct cvmx_pciercx_cfg034_s 2381215976Sjmallett { 2382215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2383215976Sjmallett uint32_t reserved_25_31 : 7; 2384215976Sjmallett uint32_t dlls_c : 1; /**< Data Link Layer State Changed */ 2385215976Sjmallett uint32_t emis : 1; /**< Electromechanical Interlock Status */ 2386215976Sjmallett uint32_t pds : 1; /**< Presence Detect State */ 2387215976Sjmallett uint32_t mrlss : 1; /**< MRL Sensor State */ 2388215976Sjmallett uint32_t ccint_d : 1; /**< Command Completed */ 2389215976Sjmallett uint32_t pd_c : 1; /**< Presence Detect Changed */ 2390215976Sjmallett uint32_t mrls_c : 1; /**< MRL Sensor Changed */ 2391215976Sjmallett uint32_t pf_d : 1; /**< Power Fault Detected */ 2392215976Sjmallett uint32_t abp_d : 1; /**< Attention Button Pressed */ 2393215976Sjmallett uint32_t reserved_13_15 : 3; 2394215976Sjmallett uint32_t dlls_en : 1; /**< Data Link Layer State Changed Enable */ 2395215976Sjmallett uint32_t emic : 1; /**< Electromechanical Interlock Control */ 2396215976Sjmallett uint32_t pcc : 1; /**< Power Controller Control */ 2397215976Sjmallett uint32_t pic : 2; /**< Power Indicator Control */ 2398215976Sjmallett uint32_t aic : 2; /**< Attention Indicator Control */ 2399215976Sjmallett uint32_t hpint_en : 1; /**< Hot-Plug Interrupt Enable */ 2400215976Sjmallett uint32_t ccint_en : 1; /**< Command Completed Interrupt Enable */ 2401215976Sjmallett uint32_t pd_en : 1; /**< Presence Detect Changed Enable */ 2402215976Sjmallett uint32_t mrls_en : 1; /**< MRL Sensor Changed Enable */ 2403215976Sjmallett uint32_t pf_en : 1; /**< Power Fault Detected Enable */ 2404215976Sjmallett uint32_t abp_en : 1; /**< Attention Button Pressed Enable */ 2405215976Sjmallett#else 2406215976Sjmallett uint32_t abp_en : 1; 2407215976Sjmallett uint32_t pf_en : 1; 2408215976Sjmallett uint32_t mrls_en : 1; 2409215976Sjmallett uint32_t pd_en : 1; 2410215976Sjmallett uint32_t ccint_en : 1; 2411215976Sjmallett uint32_t hpint_en : 1; 2412215976Sjmallett uint32_t aic : 2; 2413215976Sjmallett uint32_t pic : 2; 2414215976Sjmallett uint32_t pcc : 1; 2415215976Sjmallett uint32_t emic : 1; 2416215976Sjmallett uint32_t dlls_en : 1; 2417215976Sjmallett uint32_t reserved_13_15 : 3; 2418215976Sjmallett uint32_t abp_d : 1; 2419215976Sjmallett uint32_t pf_d : 1; 2420215976Sjmallett uint32_t mrls_c : 1; 2421215976Sjmallett uint32_t pd_c : 1; 2422215976Sjmallett uint32_t ccint_d : 1; 2423215976Sjmallett uint32_t mrlss : 1; 2424215976Sjmallett uint32_t pds : 1; 2425215976Sjmallett uint32_t emis : 1; 2426215976Sjmallett uint32_t dlls_c : 1; 2427215976Sjmallett uint32_t reserved_25_31 : 7; 2428215976Sjmallett#endif 2429215976Sjmallett } s; 2430215976Sjmallett struct cvmx_pciercx_cfg034_s cn52xx; 2431215976Sjmallett struct cvmx_pciercx_cfg034_s cn52xxp1; 2432215976Sjmallett struct cvmx_pciercx_cfg034_s cn56xx; 2433215976Sjmallett struct cvmx_pciercx_cfg034_s cn56xxp1; 2434215976Sjmallett struct cvmx_pciercx_cfg034_s cn63xx; 2435215976Sjmallett struct cvmx_pciercx_cfg034_s cn63xxp1; 2436215976Sjmallett}; 2437215976Sjmalletttypedef union cvmx_pciercx_cfg034 cvmx_pciercx_cfg034_t; 2438215976Sjmallett 2439215976Sjmallett/** 2440215976Sjmallett * cvmx_pcierc#_cfg035 2441215976Sjmallett * 2442215976Sjmallett * PCIE_CFG035 = Thirty-sixth 32-bits of PCIE type 1 config space 2443215976Sjmallett * (Root Control Register/Root Capabilities Register) 2444215976Sjmallett */ 2445215976Sjmallettunion cvmx_pciercx_cfg035 2446215976Sjmallett{ 2447215976Sjmallett uint32_t u32; 2448215976Sjmallett struct cvmx_pciercx_cfg035_s 2449215976Sjmallett { 2450215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2451215976Sjmallett uint32_t reserved_17_31 : 15; 2452215976Sjmallett uint32_t crssv : 1; /**< CRS Software Visibility 2453215976Sjmallett Not supported, hardwired to 0x0. */ 2454215976Sjmallett uint32_t reserved_5_15 : 11; 2455215976Sjmallett uint32_t crssve : 1; /**< CRS Software Visibility Enable 2456215976Sjmallett Not supported, hardwired to 0x0. */ 2457215976Sjmallett uint32_t pmeie : 1; /**< PME Interrupt Enable */ 2458215976Sjmallett uint32_t sefee : 1; /**< System Error on Fatal Error Enable */ 2459215976Sjmallett uint32_t senfee : 1; /**< System Error on Non-fatal Error Enable */ 2460215976Sjmallett uint32_t secee : 1; /**< System Error on Correctable Error Enable */ 2461215976Sjmallett#else 2462215976Sjmallett uint32_t secee : 1; 2463215976Sjmallett uint32_t senfee : 1; 2464215976Sjmallett uint32_t sefee : 1; 2465215976Sjmallett uint32_t pmeie : 1; 2466215976Sjmallett uint32_t crssve : 1; 2467215976Sjmallett uint32_t reserved_5_15 : 11; 2468215976Sjmallett uint32_t crssv : 1; 2469215976Sjmallett uint32_t reserved_17_31 : 15; 2470215976Sjmallett#endif 2471215976Sjmallett } s; 2472215976Sjmallett struct cvmx_pciercx_cfg035_s cn52xx; 2473215976Sjmallett struct cvmx_pciercx_cfg035_s cn52xxp1; 2474215976Sjmallett struct cvmx_pciercx_cfg035_s cn56xx; 2475215976Sjmallett struct cvmx_pciercx_cfg035_s cn56xxp1; 2476215976Sjmallett struct cvmx_pciercx_cfg035_s cn63xx; 2477215976Sjmallett struct cvmx_pciercx_cfg035_s cn63xxp1; 2478215976Sjmallett}; 2479215976Sjmalletttypedef union cvmx_pciercx_cfg035 cvmx_pciercx_cfg035_t; 2480215976Sjmallett 2481215976Sjmallett/** 2482215976Sjmallett * cvmx_pcierc#_cfg036 2483215976Sjmallett * 2484215976Sjmallett * PCIE_CFG036 = Thirty-seventh 32-bits of PCIE type 1 config space 2485215976Sjmallett * (Root Status Register) 2486215976Sjmallett */ 2487215976Sjmallettunion cvmx_pciercx_cfg036 2488215976Sjmallett{ 2489215976Sjmallett uint32_t u32; 2490215976Sjmallett struct cvmx_pciercx_cfg036_s 2491215976Sjmallett { 2492215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2493215976Sjmallett uint32_t reserved_18_31 : 14; 2494215976Sjmallett uint32_t pme_pend : 1; /**< PME Pending */ 2495215976Sjmallett uint32_t pme_stat : 1; /**< PME Status */ 2496215976Sjmallett uint32_t pme_rid : 16; /**< PME Requester ID */ 2497215976Sjmallett#else 2498215976Sjmallett uint32_t pme_rid : 16; 2499215976Sjmallett uint32_t pme_stat : 1; 2500215976Sjmallett uint32_t pme_pend : 1; 2501215976Sjmallett uint32_t reserved_18_31 : 14; 2502215976Sjmallett#endif 2503215976Sjmallett } s; 2504215976Sjmallett struct cvmx_pciercx_cfg036_s cn52xx; 2505215976Sjmallett struct cvmx_pciercx_cfg036_s cn52xxp1; 2506215976Sjmallett struct cvmx_pciercx_cfg036_s cn56xx; 2507215976Sjmallett struct cvmx_pciercx_cfg036_s cn56xxp1; 2508215976Sjmallett struct cvmx_pciercx_cfg036_s cn63xx; 2509215976Sjmallett struct cvmx_pciercx_cfg036_s cn63xxp1; 2510215976Sjmallett}; 2511215976Sjmalletttypedef union cvmx_pciercx_cfg036 cvmx_pciercx_cfg036_t; 2512215976Sjmallett 2513215976Sjmallett/** 2514215976Sjmallett * cvmx_pcierc#_cfg037 2515215976Sjmallett * 2516215976Sjmallett * PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 1 config space 2517215976Sjmallett * (Device Capabilities 2 Register) 2518215976Sjmallett */ 2519215976Sjmallettunion cvmx_pciercx_cfg037 2520215976Sjmallett{ 2521215976Sjmallett uint32_t u32; 2522215976Sjmallett struct cvmx_pciercx_cfg037_s 2523215976Sjmallett { 2524215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2525215976Sjmallett uint32_t reserved_5_31 : 27; 2526215976Sjmallett uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 2527215976Sjmallett uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported 2528215976Sjmallett Value of 0 indicates that Completion Timeout Programming 2529215976Sjmallett is not supported 2530215976Sjmallett Completion timeout is 16.7ms. */ 2531215976Sjmallett#else 2532215976Sjmallett uint32_t ctrs : 4; 2533215976Sjmallett uint32_t ctds : 1; 2534215976Sjmallett uint32_t reserved_5_31 : 27; 2535215976Sjmallett#endif 2536215976Sjmallett } s; 2537215976Sjmallett struct cvmx_pciercx_cfg037_s cn52xx; 2538215976Sjmallett struct cvmx_pciercx_cfg037_s cn52xxp1; 2539215976Sjmallett struct cvmx_pciercx_cfg037_s cn56xx; 2540215976Sjmallett struct cvmx_pciercx_cfg037_s cn56xxp1; 2541215976Sjmallett struct cvmx_pciercx_cfg037_s cn63xx; 2542215976Sjmallett struct cvmx_pciercx_cfg037_s cn63xxp1; 2543215976Sjmallett}; 2544215976Sjmalletttypedef union cvmx_pciercx_cfg037 cvmx_pciercx_cfg037_t; 2545215976Sjmallett 2546215976Sjmallett/** 2547215976Sjmallett * cvmx_pcierc#_cfg038 2548215976Sjmallett * 2549215976Sjmallett * PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 1 config space 2550215976Sjmallett * (Device Control 2 Register) 2551215976Sjmallett */ 2552215976Sjmallettunion cvmx_pciercx_cfg038 2553215976Sjmallett{ 2554215976Sjmallett uint32_t u32; 2555215976Sjmallett struct cvmx_pciercx_cfg038_s 2556215976Sjmallett { 2557215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2558215976Sjmallett uint32_t reserved_5_31 : 27; 2559215976Sjmallett uint32_t ctd : 1; /**< Completion Timeout Disable */ 2560215976Sjmallett uint32_t ctv : 4; /**< Completion Timeout Value 2561215976Sjmallett Completion Timeout Programming is not supported 2562215976Sjmallett Completion timeout is 16.7ms. */ 2563215976Sjmallett#else 2564215976Sjmallett uint32_t ctv : 4; 2565215976Sjmallett uint32_t ctd : 1; 2566215976Sjmallett uint32_t reserved_5_31 : 27; 2567215976Sjmallett#endif 2568215976Sjmallett } s; 2569215976Sjmallett struct cvmx_pciercx_cfg038_s cn52xx; 2570215976Sjmallett struct cvmx_pciercx_cfg038_s cn52xxp1; 2571215976Sjmallett struct cvmx_pciercx_cfg038_s cn56xx; 2572215976Sjmallett struct cvmx_pciercx_cfg038_s cn56xxp1; 2573215976Sjmallett struct cvmx_pciercx_cfg038_s cn63xx; 2574215976Sjmallett struct cvmx_pciercx_cfg038_s cn63xxp1; 2575215976Sjmallett}; 2576215976Sjmalletttypedef union cvmx_pciercx_cfg038 cvmx_pciercx_cfg038_t; 2577215976Sjmallett 2578215976Sjmallett/** 2579215976Sjmallett * cvmx_pcierc#_cfg039 2580215976Sjmallett * 2581215976Sjmallett * PCIE_CFG039 = Fourtieth 32-bits of PCIE type 1 config space 2582215976Sjmallett * (Link Capabilities 2 Register) 2583215976Sjmallett */ 2584215976Sjmallettunion cvmx_pciercx_cfg039 2585215976Sjmallett{ 2586215976Sjmallett uint32_t u32; 2587215976Sjmallett struct cvmx_pciercx_cfg039_s 2588215976Sjmallett { 2589215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2590215976Sjmallett uint32_t reserved_0_31 : 32; 2591215976Sjmallett#else 2592215976Sjmallett uint32_t reserved_0_31 : 32; 2593215976Sjmallett#endif 2594215976Sjmallett } s; 2595215976Sjmallett struct cvmx_pciercx_cfg039_s cn52xx; 2596215976Sjmallett struct cvmx_pciercx_cfg039_s cn52xxp1; 2597215976Sjmallett struct cvmx_pciercx_cfg039_s cn56xx; 2598215976Sjmallett struct cvmx_pciercx_cfg039_s cn56xxp1; 2599215976Sjmallett struct cvmx_pciercx_cfg039_s cn63xx; 2600215976Sjmallett struct cvmx_pciercx_cfg039_s cn63xxp1; 2601215976Sjmallett}; 2602215976Sjmalletttypedef union cvmx_pciercx_cfg039 cvmx_pciercx_cfg039_t; 2603215976Sjmallett 2604215976Sjmallett/** 2605215976Sjmallett * cvmx_pcierc#_cfg040 2606215976Sjmallett * 2607215976Sjmallett * PCIE_CFG040 = Fourty-first 32-bits of PCIE type 1 config space 2608215976Sjmallett * (Link Control 2 Register/Link Status 2 Register) 2609215976Sjmallett */ 2610215976Sjmallettunion cvmx_pciercx_cfg040 2611215976Sjmallett{ 2612215976Sjmallett uint32_t u32; 2613215976Sjmallett struct cvmx_pciercx_cfg040_s 2614215976Sjmallett { 2615215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2616215976Sjmallett uint32_t reserved_17_31 : 15; 2617215976Sjmallett uint32_t cdl : 1; /**< Current De-emphasis Level 2618215976Sjmallett When the Link is operating at 5 GT/s speed, this bit 2619215976Sjmallett reflects the level of de-emphasis. Encodings: 2620215976Sjmallett 1b: -3.5 dB 2621215976Sjmallett 0b: -6 dB 2622215976Sjmallett Note: The value in this bit is undefined when the Link is 2623215976Sjmallett operating at 2.5 GT/s speed */ 2624215976Sjmallett uint32_t reserved_13_15 : 3; 2625215976Sjmallett uint32_t cde : 1; /**< Compliance De-emphasis 2626215976Sjmallett This bit sets the de-emphasis level in Polling. Compliance 2627215976Sjmallett state if the entry occurred due to the Tx Compliance 2628215976Sjmallett Receive bit being 1b. Encodings: 2629215976Sjmallett 1b: -3.5 dB 2630215976Sjmallett 0b: -6 dB 2631215976Sjmallett Note: When the Link is operating at 2.5 GT/s, the setting 2632215976Sjmallett of this bit has no effect. */ 2633215976Sjmallett uint32_t csos : 1; /**< Compliance SOS 2634215976Sjmallett When set to 1b, the LTSSM is required to send SKP 2635215976Sjmallett Ordered Sets periodically in between the (modified) 2636215976Sjmallett compliance patterns. 2637215976Sjmallett Note: When the Link is operating at 2.5 GT/s, the setting 2638215976Sjmallett of this bit has no effect. */ 2639215976Sjmallett uint32_t emc : 1; /**< Enter Modified Compliance 2640215976Sjmallett When this bit is set to 1b, the device transmits a modified 2641215976Sjmallett compliance pattern if the LTSSM enters Polling. 2642215976Sjmallett Compliance state. */ 2643215976Sjmallett uint32_t tm : 3; /**< Transmit Margin 2644215976Sjmallett This field controls the value of the non-de-emphasized 2645215976Sjmallett voltage level at the Transmitter pins: 2646215976Sjmallett - 000: 800-1200 mV for full swing 400-600 mV for half-swing 2647215976Sjmallett - 001-010: values must be monotonic with a non-zero slope 2648215976Sjmallett - 011: 200-400 mV for full-swing and 100-200 mV for halfswing 2649215976Sjmallett - 100-111: reserved 2650215976Sjmallett This field is reset to 000b on entry to the LTSSM Polling. 2651215976Sjmallett Compliance substate. 2652215976Sjmallett When operating in 5.0 GT/s mode with full swing, the 2653215976Sjmallett de-emphasis ratio must be maintained within +/- 1 dB 2654215976Sjmallett from the specification-defined operational value 2655215976Sjmallett either -3.5 or -6 dB). */ 2656215976Sjmallett uint32_t sde : 1; /**< Selectable De-emphasis 2657215976Sjmallett When the Link is operating at 5.0 GT/s speed, selects the 2658215976Sjmallett level of de-emphasis: 2659215976Sjmallett - 1: -3.5 dB 2660215976Sjmallett - 0: -6 dB 2661215976Sjmallett When the Link is operating at 2.5 GT/s speed, the setting 2662215976Sjmallett of this bit has no effect. */ 2663215976Sjmallett uint32_t hasd : 1; /**< Hardware Autonomous Speed Disable 2664215976Sjmallett When asserted, the 2665215976Sjmallett application must disable hardware from changing the Link 2666215976Sjmallett speed for device-specific reasons other than attempting to 2667215976Sjmallett correct unreliable Link operation by reducing Link speed. 2668215976Sjmallett Initial transition to the highest supported common link 2669215976Sjmallett speed is not blocked by this signal. */ 2670215976Sjmallett uint32_t ec : 1; /**< Enter Compliance 2671215976Sjmallett Software is permitted to force a link to enter Compliance 2672215976Sjmallett mode at the speed indicated in the Target Link Speed 2673215976Sjmallett field by setting this bit to 1b in both components on a link 2674215976Sjmallett and then initiating a hot reset on the link. */ 2675215976Sjmallett uint32_t tls : 4; /**< Target Link Speed 2676215976Sjmallett For Downstream ports, this field sets an upper limit on link 2677215976Sjmallett operational speed by restricting the values advertised by 2678215976Sjmallett the upstream component in its training sequences: 2679215976Sjmallett - 0001: 2.5Gb/s Target Link Speed 2680215976Sjmallett - 0010: 5Gb/s Target Link Speed 2681215976Sjmallett All other encodings are reserved. 2682215976Sjmallett If a value is written to this field that does not correspond to 2683215976Sjmallett a speed included in the Supported Link Speeds field, the 2684215976Sjmallett result is undefined. 2685215976Sjmallett For both Upstream and Downstream ports, this field is 2686215976Sjmallett used to set the target compliance mode speed when 2687215976Sjmallett software is using the Enter Compliance bit to force a link 2688215976Sjmallett into compliance mode. 2689215976Sjmallett Out of reset this will have a value of 1 or 2 which is 2690215976Sjmallett selected by qlmCfgx[1]. */ 2691215976Sjmallett#else 2692215976Sjmallett uint32_t tls : 4; 2693215976Sjmallett uint32_t ec : 1; 2694215976Sjmallett uint32_t hasd : 1; 2695215976Sjmallett uint32_t sde : 1; 2696215976Sjmallett uint32_t tm : 3; 2697215976Sjmallett uint32_t emc : 1; 2698215976Sjmallett uint32_t csos : 1; 2699215976Sjmallett uint32_t cde : 1; 2700215976Sjmallett uint32_t reserved_13_15 : 3; 2701215976Sjmallett uint32_t cdl : 1; 2702215976Sjmallett uint32_t reserved_17_31 : 15; 2703215976Sjmallett#endif 2704215976Sjmallett } s; 2705215976Sjmallett struct cvmx_pciercx_cfg040_cn52xx 2706215976Sjmallett { 2707215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2708215976Sjmallett uint32_t reserved_0_31 : 32; 2709215976Sjmallett#else 2710215976Sjmallett uint32_t reserved_0_31 : 32; 2711215976Sjmallett#endif 2712215976Sjmallett } cn52xx; 2713215976Sjmallett struct cvmx_pciercx_cfg040_cn52xx cn52xxp1; 2714215976Sjmallett struct cvmx_pciercx_cfg040_cn52xx cn56xx; 2715215976Sjmallett struct cvmx_pciercx_cfg040_cn52xx cn56xxp1; 2716215976Sjmallett struct cvmx_pciercx_cfg040_s cn63xx; 2717215976Sjmallett struct cvmx_pciercx_cfg040_s cn63xxp1; 2718215976Sjmallett}; 2719215976Sjmalletttypedef union cvmx_pciercx_cfg040 cvmx_pciercx_cfg040_t; 2720215976Sjmallett 2721215976Sjmallett/** 2722215976Sjmallett * cvmx_pcierc#_cfg041 2723215976Sjmallett * 2724215976Sjmallett * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 1 config space 2725215976Sjmallett * (Slot Capabilities 2 Register) 2726215976Sjmallett */ 2727215976Sjmallettunion cvmx_pciercx_cfg041 2728215976Sjmallett{ 2729215976Sjmallett uint32_t u32; 2730215976Sjmallett struct cvmx_pciercx_cfg041_s 2731215976Sjmallett { 2732215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2733215976Sjmallett uint32_t reserved_0_31 : 32; 2734215976Sjmallett#else 2735215976Sjmallett uint32_t reserved_0_31 : 32; 2736215976Sjmallett#endif 2737215976Sjmallett } s; 2738215976Sjmallett struct cvmx_pciercx_cfg041_s cn52xx; 2739215976Sjmallett struct cvmx_pciercx_cfg041_s cn52xxp1; 2740215976Sjmallett struct cvmx_pciercx_cfg041_s cn56xx; 2741215976Sjmallett struct cvmx_pciercx_cfg041_s cn56xxp1; 2742215976Sjmallett struct cvmx_pciercx_cfg041_s cn63xx; 2743215976Sjmallett struct cvmx_pciercx_cfg041_s cn63xxp1; 2744215976Sjmallett}; 2745215976Sjmalletttypedef union cvmx_pciercx_cfg041 cvmx_pciercx_cfg041_t; 2746215976Sjmallett 2747215976Sjmallett/** 2748215976Sjmallett * cvmx_pcierc#_cfg042 2749215976Sjmallett * 2750215976Sjmallett * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 1 config space 2751215976Sjmallett * (Slot Control 2 Register/Slot Status 2 Register) 2752215976Sjmallett */ 2753215976Sjmallettunion cvmx_pciercx_cfg042 2754215976Sjmallett{ 2755215976Sjmallett uint32_t u32; 2756215976Sjmallett struct cvmx_pciercx_cfg042_s 2757215976Sjmallett { 2758215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2759215976Sjmallett uint32_t reserved_0_31 : 32; 2760215976Sjmallett#else 2761215976Sjmallett uint32_t reserved_0_31 : 32; 2762215976Sjmallett#endif 2763215976Sjmallett } s; 2764215976Sjmallett struct cvmx_pciercx_cfg042_s cn52xx; 2765215976Sjmallett struct cvmx_pciercx_cfg042_s cn52xxp1; 2766215976Sjmallett struct cvmx_pciercx_cfg042_s cn56xx; 2767215976Sjmallett struct cvmx_pciercx_cfg042_s cn56xxp1; 2768215976Sjmallett struct cvmx_pciercx_cfg042_s cn63xx; 2769215976Sjmallett struct cvmx_pciercx_cfg042_s cn63xxp1; 2770215976Sjmallett}; 2771215976Sjmalletttypedef union cvmx_pciercx_cfg042 cvmx_pciercx_cfg042_t; 2772215976Sjmallett 2773215976Sjmallett/** 2774215976Sjmallett * cvmx_pcierc#_cfg064 2775215976Sjmallett * 2776215976Sjmallett * PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 1 config space 2777215976Sjmallett * (PCI Express Enhanced Capability Header) 2778215976Sjmallett */ 2779215976Sjmallettunion cvmx_pciercx_cfg064 2780215976Sjmallett{ 2781215976Sjmallett uint32_t u32; 2782215976Sjmallett struct cvmx_pciercx_cfg064_s 2783215976Sjmallett { 2784215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2785215976Sjmallett uint32_t nco : 12; /**< Next Capability Offset */ 2786215976Sjmallett uint32_t cv : 4; /**< Capability Version */ 2787215976Sjmallett uint32_t pcieec : 16; /**< PCIE Express Extended Capability */ 2788215976Sjmallett#else 2789215976Sjmallett uint32_t pcieec : 16; 2790215976Sjmallett uint32_t cv : 4; 2791215976Sjmallett uint32_t nco : 12; 2792215976Sjmallett#endif 2793215976Sjmallett } s; 2794215976Sjmallett struct cvmx_pciercx_cfg064_s cn52xx; 2795215976Sjmallett struct cvmx_pciercx_cfg064_s cn52xxp1; 2796215976Sjmallett struct cvmx_pciercx_cfg064_s cn56xx; 2797215976Sjmallett struct cvmx_pciercx_cfg064_s cn56xxp1; 2798215976Sjmallett struct cvmx_pciercx_cfg064_s cn63xx; 2799215976Sjmallett struct cvmx_pciercx_cfg064_s cn63xxp1; 2800215976Sjmallett}; 2801215976Sjmalletttypedef union cvmx_pciercx_cfg064 cvmx_pciercx_cfg064_t; 2802215976Sjmallett 2803215976Sjmallett/** 2804215976Sjmallett * cvmx_pcierc#_cfg065 2805215976Sjmallett * 2806215976Sjmallett * PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 1 config space 2807215976Sjmallett * (Uncorrectable Error Status Register) 2808215976Sjmallett */ 2809215976Sjmallettunion cvmx_pciercx_cfg065 2810215976Sjmallett{ 2811215976Sjmallett uint32_t u32; 2812215976Sjmallett struct cvmx_pciercx_cfg065_s 2813215976Sjmallett { 2814215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2815215976Sjmallett uint32_t reserved_21_31 : 11; 2816215976Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Status */ 2817215976Sjmallett uint32_t ecrces : 1; /**< ECRC Error Status */ 2818215976Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Status */ 2819215976Sjmallett uint32_t ros : 1; /**< Receiver Overflow Status */ 2820215976Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Status */ 2821215976Sjmallett uint32_t cas : 1; /**< Completer Abort Status */ 2822215976Sjmallett uint32_t cts : 1; /**< Completion Timeout Status */ 2823215976Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 2824215976Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Status */ 2825215976Sjmallett uint32_t reserved_6_11 : 6; 2826215976Sjmallett uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */ 2827215976Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 2828215976Sjmallett uint32_t reserved_0_3 : 4; 2829215976Sjmallett#else 2830215976Sjmallett uint32_t reserved_0_3 : 4; 2831215976Sjmallett uint32_t dlpes : 1; 2832215976Sjmallett uint32_t sdes : 1; 2833215976Sjmallett uint32_t reserved_6_11 : 6; 2834215976Sjmallett uint32_t ptlps : 1; 2835215976Sjmallett uint32_t fcpes : 1; 2836215976Sjmallett uint32_t cts : 1; 2837215976Sjmallett uint32_t cas : 1; 2838215976Sjmallett uint32_t ucs : 1; 2839215976Sjmallett uint32_t ros : 1; 2840215976Sjmallett uint32_t mtlps : 1; 2841215976Sjmallett uint32_t ecrces : 1; 2842215976Sjmallett uint32_t ures : 1; 2843215976Sjmallett uint32_t reserved_21_31 : 11; 2844215976Sjmallett#endif 2845215976Sjmallett } s; 2846215976Sjmallett struct cvmx_pciercx_cfg065_s cn52xx; 2847215976Sjmallett struct cvmx_pciercx_cfg065_s cn52xxp1; 2848215976Sjmallett struct cvmx_pciercx_cfg065_s cn56xx; 2849215976Sjmallett struct cvmx_pciercx_cfg065_s cn56xxp1; 2850215976Sjmallett struct cvmx_pciercx_cfg065_s cn63xx; 2851215976Sjmallett struct cvmx_pciercx_cfg065_s cn63xxp1; 2852215976Sjmallett}; 2853215976Sjmalletttypedef union cvmx_pciercx_cfg065 cvmx_pciercx_cfg065_t; 2854215976Sjmallett 2855215976Sjmallett/** 2856215976Sjmallett * cvmx_pcierc#_cfg066 2857215976Sjmallett * 2858215976Sjmallett * PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 1 config space 2859215976Sjmallett * (Uncorrectable Error Mask Register) 2860215976Sjmallett */ 2861215976Sjmallettunion cvmx_pciercx_cfg066 2862215976Sjmallett{ 2863215976Sjmallett uint32_t u32; 2864215976Sjmallett struct cvmx_pciercx_cfg066_s 2865215976Sjmallett { 2866215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2867215976Sjmallett uint32_t reserved_21_31 : 11; 2868215976Sjmallett uint32_t urem : 1; /**< Unsupported Request Error Mask */ 2869215976Sjmallett uint32_t ecrcem : 1; /**< ECRC Error Mask */ 2870215976Sjmallett uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 2871215976Sjmallett uint32_t rom : 1; /**< Receiver Overflow Mask */ 2872215976Sjmallett uint32_t ucm : 1; /**< Unexpected Completion Mask */ 2873215976Sjmallett uint32_t cam : 1; /**< Completer Abort Mask */ 2874215976Sjmallett uint32_t ctm : 1; /**< Completion Timeout Mask */ 2875215976Sjmallett uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 2876215976Sjmallett uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 2877215976Sjmallett uint32_t reserved_6_11 : 6; 2878215976Sjmallett uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */ 2879215976Sjmallett uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 2880215976Sjmallett uint32_t reserved_0_3 : 4; 2881215976Sjmallett#else 2882215976Sjmallett uint32_t reserved_0_3 : 4; 2883215976Sjmallett uint32_t dlpem : 1; 2884215976Sjmallett uint32_t sdem : 1; 2885215976Sjmallett uint32_t reserved_6_11 : 6; 2886215976Sjmallett uint32_t ptlpm : 1; 2887215976Sjmallett uint32_t fcpem : 1; 2888215976Sjmallett uint32_t ctm : 1; 2889215976Sjmallett uint32_t cam : 1; 2890215976Sjmallett uint32_t ucm : 1; 2891215976Sjmallett uint32_t rom : 1; 2892215976Sjmallett uint32_t mtlpm : 1; 2893215976Sjmallett uint32_t ecrcem : 1; 2894215976Sjmallett uint32_t urem : 1; 2895215976Sjmallett uint32_t reserved_21_31 : 11; 2896215976Sjmallett#endif 2897215976Sjmallett } s; 2898215976Sjmallett struct cvmx_pciercx_cfg066_s cn52xx; 2899215976Sjmallett struct cvmx_pciercx_cfg066_s cn52xxp1; 2900215976Sjmallett struct cvmx_pciercx_cfg066_s cn56xx; 2901215976Sjmallett struct cvmx_pciercx_cfg066_s cn56xxp1; 2902215976Sjmallett struct cvmx_pciercx_cfg066_s cn63xx; 2903215976Sjmallett struct cvmx_pciercx_cfg066_s cn63xxp1; 2904215976Sjmallett}; 2905215976Sjmalletttypedef union cvmx_pciercx_cfg066 cvmx_pciercx_cfg066_t; 2906215976Sjmallett 2907215976Sjmallett/** 2908215976Sjmallett * cvmx_pcierc#_cfg067 2909215976Sjmallett * 2910215976Sjmallett * PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 1 config space 2911215976Sjmallett * (Uncorrectable Error Severity Register) 2912215976Sjmallett */ 2913215976Sjmallettunion cvmx_pciercx_cfg067 2914215976Sjmallett{ 2915215976Sjmallett uint32_t u32; 2916215976Sjmallett struct cvmx_pciercx_cfg067_s 2917215976Sjmallett { 2918215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2919215976Sjmallett uint32_t reserved_21_31 : 11; 2920215976Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Severity */ 2921215976Sjmallett uint32_t ecrces : 1; /**< ECRC Error Severity */ 2922215976Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Severity */ 2923215976Sjmallett uint32_t ros : 1; /**< Receiver Overflow Severity */ 2924215976Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Severity */ 2925215976Sjmallett uint32_t cas : 1; /**< Completer Abort Severity */ 2926215976Sjmallett uint32_t cts : 1; /**< Completion Timeout Severity */ 2927215976Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 2928215976Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 2929215976Sjmallett uint32_t reserved_6_11 : 6; 2930215976Sjmallett uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */ 2931215976Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 2932215976Sjmallett uint32_t reserved_0_3 : 4; 2933215976Sjmallett#else 2934215976Sjmallett uint32_t reserved_0_3 : 4; 2935215976Sjmallett uint32_t dlpes : 1; 2936215976Sjmallett uint32_t sdes : 1; 2937215976Sjmallett uint32_t reserved_6_11 : 6; 2938215976Sjmallett uint32_t ptlps : 1; 2939215976Sjmallett uint32_t fcpes : 1; 2940215976Sjmallett uint32_t cts : 1; 2941215976Sjmallett uint32_t cas : 1; 2942215976Sjmallett uint32_t ucs : 1; 2943215976Sjmallett uint32_t ros : 1; 2944215976Sjmallett uint32_t mtlps : 1; 2945215976Sjmallett uint32_t ecrces : 1; 2946215976Sjmallett uint32_t ures : 1; 2947215976Sjmallett uint32_t reserved_21_31 : 11; 2948215976Sjmallett#endif 2949215976Sjmallett } s; 2950215976Sjmallett struct cvmx_pciercx_cfg067_s cn52xx; 2951215976Sjmallett struct cvmx_pciercx_cfg067_s cn52xxp1; 2952215976Sjmallett struct cvmx_pciercx_cfg067_s cn56xx; 2953215976Sjmallett struct cvmx_pciercx_cfg067_s cn56xxp1; 2954215976Sjmallett struct cvmx_pciercx_cfg067_s cn63xx; 2955215976Sjmallett struct cvmx_pciercx_cfg067_s cn63xxp1; 2956215976Sjmallett}; 2957215976Sjmalletttypedef union cvmx_pciercx_cfg067 cvmx_pciercx_cfg067_t; 2958215976Sjmallett 2959215976Sjmallett/** 2960215976Sjmallett * cvmx_pcierc#_cfg068 2961215976Sjmallett * 2962215976Sjmallett * PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 1 config space 2963215976Sjmallett * (Correctable Error Status Register) 2964215976Sjmallett */ 2965215976Sjmallettunion cvmx_pciercx_cfg068 2966215976Sjmallett{ 2967215976Sjmallett uint32_t u32; 2968215976Sjmallett struct cvmx_pciercx_cfg068_s 2969215976Sjmallett { 2970215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2971215976Sjmallett uint32_t reserved_14_31 : 18; 2972215976Sjmallett uint32_t anfes : 1; /**< Advisory Non-Fatal Error Status */ 2973215976Sjmallett uint32_t rtts : 1; /**< Replay Timer Timeout Status */ 2974215976Sjmallett uint32_t reserved_9_11 : 3; 2975215976Sjmallett uint32_t rnrs : 1; /**< REPLAY_NUM Rollover Status */ 2976215976Sjmallett uint32_t bdllps : 1; /**< Bad DLLP Status */ 2977215976Sjmallett uint32_t btlps : 1; /**< Bad TLP Status */ 2978215976Sjmallett uint32_t reserved_1_5 : 5; 2979215976Sjmallett uint32_t res : 1; /**< Receiver Error Status */ 2980215976Sjmallett#else 2981215976Sjmallett uint32_t res : 1; 2982215976Sjmallett uint32_t reserved_1_5 : 5; 2983215976Sjmallett uint32_t btlps : 1; 2984215976Sjmallett uint32_t bdllps : 1; 2985215976Sjmallett uint32_t rnrs : 1; 2986215976Sjmallett uint32_t reserved_9_11 : 3; 2987215976Sjmallett uint32_t rtts : 1; 2988215976Sjmallett uint32_t anfes : 1; 2989215976Sjmallett uint32_t reserved_14_31 : 18; 2990215976Sjmallett#endif 2991215976Sjmallett } s; 2992215976Sjmallett struct cvmx_pciercx_cfg068_s cn52xx; 2993215976Sjmallett struct cvmx_pciercx_cfg068_s cn52xxp1; 2994215976Sjmallett struct cvmx_pciercx_cfg068_s cn56xx; 2995215976Sjmallett struct cvmx_pciercx_cfg068_s cn56xxp1; 2996215976Sjmallett struct cvmx_pciercx_cfg068_s cn63xx; 2997215976Sjmallett struct cvmx_pciercx_cfg068_s cn63xxp1; 2998215976Sjmallett}; 2999215976Sjmalletttypedef union cvmx_pciercx_cfg068 cvmx_pciercx_cfg068_t; 3000215976Sjmallett 3001215976Sjmallett/** 3002215976Sjmallett * cvmx_pcierc#_cfg069 3003215976Sjmallett * 3004215976Sjmallett * PCIE_CFG069 = Seventieth 32-bits of PCIE type 1 config space 3005215976Sjmallett * (Correctable Error Mask Register) 3006215976Sjmallett */ 3007215976Sjmallettunion cvmx_pciercx_cfg069 3008215976Sjmallett{ 3009215976Sjmallett uint32_t u32; 3010215976Sjmallett struct cvmx_pciercx_cfg069_s 3011215976Sjmallett { 3012215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3013215976Sjmallett uint32_t reserved_14_31 : 18; 3014215976Sjmallett uint32_t anfem : 1; /**< Advisory Non-Fatal Error Mask */ 3015215976Sjmallett uint32_t rttm : 1; /**< Replay Timer Timeout Mask */ 3016215976Sjmallett uint32_t reserved_9_11 : 3; 3017215976Sjmallett uint32_t rnrm : 1; /**< REPLAY_NUM Rollover Mask */ 3018215976Sjmallett uint32_t bdllpm : 1; /**< Bad DLLP Mask */ 3019215976Sjmallett uint32_t btlpm : 1; /**< Bad TLP Mask */ 3020215976Sjmallett uint32_t reserved_1_5 : 5; 3021215976Sjmallett uint32_t rem : 1; /**< Receiver Error Mask */ 3022215976Sjmallett#else 3023215976Sjmallett uint32_t rem : 1; 3024215976Sjmallett uint32_t reserved_1_5 : 5; 3025215976Sjmallett uint32_t btlpm : 1; 3026215976Sjmallett uint32_t bdllpm : 1; 3027215976Sjmallett uint32_t rnrm : 1; 3028215976Sjmallett uint32_t reserved_9_11 : 3; 3029215976Sjmallett uint32_t rttm : 1; 3030215976Sjmallett uint32_t anfem : 1; 3031215976Sjmallett uint32_t reserved_14_31 : 18; 3032215976Sjmallett#endif 3033215976Sjmallett } s; 3034215976Sjmallett struct cvmx_pciercx_cfg069_s cn52xx; 3035215976Sjmallett struct cvmx_pciercx_cfg069_s cn52xxp1; 3036215976Sjmallett struct cvmx_pciercx_cfg069_s cn56xx; 3037215976Sjmallett struct cvmx_pciercx_cfg069_s cn56xxp1; 3038215976Sjmallett struct cvmx_pciercx_cfg069_s cn63xx; 3039215976Sjmallett struct cvmx_pciercx_cfg069_s cn63xxp1; 3040215976Sjmallett}; 3041215976Sjmalletttypedef union cvmx_pciercx_cfg069 cvmx_pciercx_cfg069_t; 3042215976Sjmallett 3043215976Sjmallett/** 3044215976Sjmallett * cvmx_pcierc#_cfg070 3045215976Sjmallett * 3046215976Sjmallett * PCIE_CFG070 = Seventy-first 32-bits of PCIE type 1 config space 3047215976Sjmallett * (Advanced Capabilities and Control Register) 3048215976Sjmallett */ 3049215976Sjmallettunion cvmx_pciercx_cfg070 3050215976Sjmallett{ 3051215976Sjmallett uint32_t u32; 3052215976Sjmallett struct cvmx_pciercx_cfg070_s 3053215976Sjmallett { 3054215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3055215976Sjmallett uint32_t reserved_9_31 : 23; 3056215976Sjmallett uint32_t ce : 1; /**< ECRC Check Enable */ 3057215976Sjmallett uint32_t cc : 1; /**< ECRC Check Capable */ 3058215976Sjmallett uint32_t ge : 1; /**< ECRC Generation Enable */ 3059215976Sjmallett uint32_t gc : 1; /**< ECRC Generation Capability */ 3060215976Sjmallett uint32_t fep : 5; /**< First Error Pointer */ 3061215976Sjmallett#else 3062215976Sjmallett uint32_t fep : 5; 3063215976Sjmallett uint32_t gc : 1; 3064215976Sjmallett uint32_t ge : 1; 3065215976Sjmallett uint32_t cc : 1; 3066215976Sjmallett uint32_t ce : 1; 3067215976Sjmallett uint32_t reserved_9_31 : 23; 3068215976Sjmallett#endif 3069215976Sjmallett } s; 3070215976Sjmallett struct cvmx_pciercx_cfg070_s cn52xx; 3071215976Sjmallett struct cvmx_pciercx_cfg070_s cn52xxp1; 3072215976Sjmallett struct cvmx_pciercx_cfg070_s cn56xx; 3073215976Sjmallett struct cvmx_pciercx_cfg070_s cn56xxp1; 3074215976Sjmallett struct cvmx_pciercx_cfg070_s cn63xx; 3075215976Sjmallett struct cvmx_pciercx_cfg070_s cn63xxp1; 3076215976Sjmallett}; 3077215976Sjmalletttypedef union cvmx_pciercx_cfg070 cvmx_pciercx_cfg070_t; 3078215976Sjmallett 3079215976Sjmallett/** 3080215976Sjmallett * cvmx_pcierc#_cfg071 3081215976Sjmallett * 3082215976Sjmallett * PCIE_CFG071 = Seventy-second 32-bits of PCIE type 1 config space 3083215976Sjmallett * (Header Log Register 1) 3084215976Sjmallett * 3085215976Sjmallett * The Header Log registers collect the header for the TLP corresponding to a detected error. 3086215976Sjmallett */ 3087215976Sjmallettunion cvmx_pciercx_cfg071 3088215976Sjmallett{ 3089215976Sjmallett uint32_t u32; 3090215976Sjmallett struct cvmx_pciercx_cfg071_s 3091215976Sjmallett { 3092215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3093215976Sjmallett uint32_t dword1 : 32; /**< Header Log Register (first DWORD) */ 3094215976Sjmallett#else 3095215976Sjmallett uint32_t dword1 : 32; 3096215976Sjmallett#endif 3097215976Sjmallett } s; 3098215976Sjmallett struct cvmx_pciercx_cfg071_s cn52xx; 3099215976Sjmallett struct cvmx_pciercx_cfg071_s cn52xxp1; 3100215976Sjmallett struct cvmx_pciercx_cfg071_s cn56xx; 3101215976Sjmallett struct cvmx_pciercx_cfg071_s cn56xxp1; 3102215976Sjmallett struct cvmx_pciercx_cfg071_s cn63xx; 3103215976Sjmallett struct cvmx_pciercx_cfg071_s cn63xxp1; 3104215976Sjmallett}; 3105215976Sjmalletttypedef union cvmx_pciercx_cfg071 cvmx_pciercx_cfg071_t; 3106215976Sjmallett 3107215976Sjmallett/** 3108215976Sjmallett * cvmx_pcierc#_cfg072 3109215976Sjmallett * 3110215976Sjmallett * PCIE_CFG072 = Seventy-third 32-bits of PCIE type 1 config space 3111215976Sjmallett * (Header Log Register 2) 3112215976Sjmallett * 3113215976Sjmallett * The Header Log registers collect the header for the TLP corresponding to a detected error. 3114215976Sjmallett */ 3115215976Sjmallettunion cvmx_pciercx_cfg072 3116215976Sjmallett{ 3117215976Sjmallett uint32_t u32; 3118215976Sjmallett struct cvmx_pciercx_cfg072_s 3119215976Sjmallett { 3120215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3121215976Sjmallett uint32_t dword2 : 32; /**< Header Log Register (second DWORD) */ 3122215976Sjmallett#else 3123215976Sjmallett uint32_t dword2 : 32; 3124215976Sjmallett#endif 3125215976Sjmallett } s; 3126215976Sjmallett struct cvmx_pciercx_cfg072_s cn52xx; 3127215976Sjmallett struct cvmx_pciercx_cfg072_s cn52xxp1; 3128215976Sjmallett struct cvmx_pciercx_cfg072_s cn56xx; 3129215976Sjmallett struct cvmx_pciercx_cfg072_s cn56xxp1; 3130215976Sjmallett struct cvmx_pciercx_cfg072_s cn63xx; 3131215976Sjmallett struct cvmx_pciercx_cfg072_s cn63xxp1; 3132215976Sjmallett}; 3133215976Sjmalletttypedef union cvmx_pciercx_cfg072 cvmx_pciercx_cfg072_t; 3134215976Sjmallett 3135215976Sjmallett/** 3136215976Sjmallett * cvmx_pcierc#_cfg073 3137215976Sjmallett * 3138215976Sjmallett * PCIE_CFG073 = Seventy-fourth 32-bits of PCIE type 1 config space 3139215976Sjmallett * (Header Log Register 3) 3140215976Sjmallett * 3141215976Sjmallett * The Header Log registers collect the header for the TLP corresponding to a detected error. 3142215976Sjmallett */ 3143215976Sjmallettunion cvmx_pciercx_cfg073 3144215976Sjmallett{ 3145215976Sjmallett uint32_t u32; 3146215976Sjmallett struct cvmx_pciercx_cfg073_s 3147215976Sjmallett { 3148215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3149215976Sjmallett uint32_t dword3 : 32; /**< Header Log Register (third DWORD) */ 3150215976Sjmallett#else 3151215976Sjmallett uint32_t dword3 : 32; 3152215976Sjmallett#endif 3153215976Sjmallett } s; 3154215976Sjmallett struct cvmx_pciercx_cfg073_s cn52xx; 3155215976Sjmallett struct cvmx_pciercx_cfg073_s cn52xxp1; 3156215976Sjmallett struct cvmx_pciercx_cfg073_s cn56xx; 3157215976Sjmallett struct cvmx_pciercx_cfg073_s cn56xxp1; 3158215976Sjmallett struct cvmx_pciercx_cfg073_s cn63xx; 3159215976Sjmallett struct cvmx_pciercx_cfg073_s cn63xxp1; 3160215976Sjmallett}; 3161215976Sjmalletttypedef union cvmx_pciercx_cfg073 cvmx_pciercx_cfg073_t; 3162215976Sjmallett 3163215976Sjmallett/** 3164215976Sjmallett * cvmx_pcierc#_cfg074 3165215976Sjmallett * 3166215976Sjmallett * PCIE_CFG074 = Seventy-fifth 32-bits of PCIE type 1 config space 3167215976Sjmallett * (Header Log Register 4) 3168215976Sjmallett * 3169215976Sjmallett * The Header Log registers collect the header for the TLP corresponding to a detected error. 3170215976Sjmallett */ 3171215976Sjmallettunion cvmx_pciercx_cfg074 3172215976Sjmallett{ 3173215976Sjmallett uint32_t u32; 3174215976Sjmallett struct cvmx_pciercx_cfg074_s 3175215976Sjmallett { 3176215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3177215976Sjmallett uint32_t dword4 : 32; /**< Header Log Register (fourth DWORD) */ 3178215976Sjmallett#else 3179215976Sjmallett uint32_t dword4 : 32; 3180215976Sjmallett#endif 3181215976Sjmallett } s; 3182215976Sjmallett struct cvmx_pciercx_cfg074_s cn52xx; 3183215976Sjmallett struct cvmx_pciercx_cfg074_s cn52xxp1; 3184215976Sjmallett struct cvmx_pciercx_cfg074_s cn56xx; 3185215976Sjmallett struct cvmx_pciercx_cfg074_s cn56xxp1; 3186215976Sjmallett struct cvmx_pciercx_cfg074_s cn63xx; 3187215976Sjmallett struct cvmx_pciercx_cfg074_s cn63xxp1; 3188215976Sjmallett}; 3189215976Sjmalletttypedef union cvmx_pciercx_cfg074 cvmx_pciercx_cfg074_t; 3190215976Sjmallett 3191215976Sjmallett/** 3192215976Sjmallett * cvmx_pcierc#_cfg075 3193215976Sjmallett * 3194215976Sjmallett * PCIE_CFG075 = Seventy-sixth 32-bits of PCIE type 1 config space 3195215976Sjmallett * (Root Error Command Register) 3196215976Sjmallett */ 3197215976Sjmallettunion cvmx_pciercx_cfg075 3198215976Sjmallett{ 3199215976Sjmallett uint32_t u32; 3200215976Sjmallett struct cvmx_pciercx_cfg075_s 3201215976Sjmallett { 3202215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3203215976Sjmallett uint32_t reserved_3_31 : 29; 3204215976Sjmallett uint32_t fere : 1; /**< Fatal Error Reporting Enable */ 3205215976Sjmallett uint32_t nfere : 1; /**< Non-Fatal Error Reporting Enable */ 3206215976Sjmallett uint32_t cere : 1; /**< Correctable Error Reporting Enable */ 3207215976Sjmallett#else 3208215976Sjmallett uint32_t cere : 1; 3209215976Sjmallett uint32_t nfere : 1; 3210215976Sjmallett uint32_t fere : 1; 3211215976Sjmallett uint32_t reserved_3_31 : 29; 3212215976Sjmallett#endif 3213215976Sjmallett } s; 3214215976Sjmallett struct cvmx_pciercx_cfg075_s cn52xx; 3215215976Sjmallett struct cvmx_pciercx_cfg075_s cn52xxp1; 3216215976Sjmallett struct cvmx_pciercx_cfg075_s cn56xx; 3217215976Sjmallett struct cvmx_pciercx_cfg075_s cn56xxp1; 3218215976Sjmallett struct cvmx_pciercx_cfg075_s cn63xx; 3219215976Sjmallett struct cvmx_pciercx_cfg075_s cn63xxp1; 3220215976Sjmallett}; 3221215976Sjmalletttypedef union cvmx_pciercx_cfg075 cvmx_pciercx_cfg075_t; 3222215976Sjmallett 3223215976Sjmallett/** 3224215976Sjmallett * cvmx_pcierc#_cfg076 3225215976Sjmallett * 3226215976Sjmallett * PCIE_CFG076 = Seventy-seventh 32-bits of PCIE type 1 config space 3227215976Sjmallett * (Root Error Status Register) 3228215976Sjmallett */ 3229215976Sjmallettunion cvmx_pciercx_cfg076 3230215976Sjmallett{ 3231215976Sjmallett uint32_t u32; 3232215976Sjmallett struct cvmx_pciercx_cfg076_s 3233215976Sjmallett { 3234215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3235215976Sjmallett uint32_t aeimn : 5; /**< Advanced Error Interrupt Message Number, 3236215976Sjmallett writable through PEM(0..1)_CFG_WR */ 3237215976Sjmallett uint32_t reserved_7_26 : 20; 3238215976Sjmallett uint32_t femr : 1; /**< Fatal Error Messages Received */ 3239215976Sjmallett uint32_t nfemr : 1; /**< Non-Fatal Error Messages Received */ 3240215976Sjmallett uint32_t fuf : 1; /**< First Uncorrectable Fatal */ 3241215976Sjmallett uint32_t multi_efnfr : 1; /**< Multiple ERR_FATAL/NONFATAL Received */ 3242215976Sjmallett uint32_t efnfr : 1; /**< ERR_FATAL/NONFATAL Received */ 3243215976Sjmallett uint32_t multi_ecr : 1; /**< Multiple ERR_COR Received */ 3244215976Sjmallett uint32_t ecr : 1; /**< ERR_COR Received */ 3245215976Sjmallett#else 3246215976Sjmallett uint32_t ecr : 1; 3247215976Sjmallett uint32_t multi_ecr : 1; 3248215976Sjmallett uint32_t efnfr : 1; 3249215976Sjmallett uint32_t multi_efnfr : 1; 3250215976Sjmallett uint32_t fuf : 1; 3251215976Sjmallett uint32_t nfemr : 1; 3252215976Sjmallett uint32_t femr : 1; 3253215976Sjmallett uint32_t reserved_7_26 : 20; 3254215976Sjmallett uint32_t aeimn : 5; 3255215976Sjmallett#endif 3256215976Sjmallett } s; 3257215976Sjmallett struct cvmx_pciercx_cfg076_s cn52xx; 3258215976Sjmallett struct cvmx_pciercx_cfg076_s cn52xxp1; 3259215976Sjmallett struct cvmx_pciercx_cfg076_s cn56xx; 3260215976Sjmallett struct cvmx_pciercx_cfg076_s cn56xxp1; 3261215976Sjmallett struct cvmx_pciercx_cfg076_s cn63xx; 3262215976Sjmallett struct cvmx_pciercx_cfg076_s cn63xxp1; 3263215976Sjmallett}; 3264215976Sjmalletttypedef union cvmx_pciercx_cfg076 cvmx_pciercx_cfg076_t; 3265215976Sjmallett 3266215976Sjmallett/** 3267215976Sjmallett * cvmx_pcierc#_cfg077 3268215976Sjmallett * 3269215976Sjmallett * PCIE_CFG077 = Seventy-eighth 32-bits of PCIE type 1 config space 3270215976Sjmallett * (Error Source Identification Register) 3271215976Sjmallett */ 3272215976Sjmallettunion cvmx_pciercx_cfg077 3273215976Sjmallett{ 3274215976Sjmallett uint32_t u32; 3275215976Sjmallett struct cvmx_pciercx_cfg077_s 3276215976Sjmallett { 3277215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3278215976Sjmallett uint32_t efnfsi : 16; /**< ERR_FATAL/NONFATAL Source Identification */ 3279215976Sjmallett uint32_t ecsi : 16; /**< ERR_COR Source Identification */ 3280215976Sjmallett#else 3281215976Sjmallett uint32_t ecsi : 16; 3282215976Sjmallett uint32_t efnfsi : 16; 3283215976Sjmallett#endif 3284215976Sjmallett } s; 3285215976Sjmallett struct cvmx_pciercx_cfg077_s cn52xx; 3286215976Sjmallett struct cvmx_pciercx_cfg077_s cn52xxp1; 3287215976Sjmallett struct cvmx_pciercx_cfg077_s cn56xx; 3288215976Sjmallett struct cvmx_pciercx_cfg077_s cn56xxp1; 3289215976Sjmallett struct cvmx_pciercx_cfg077_s cn63xx; 3290215976Sjmallett struct cvmx_pciercx_cfg077_s cn63xxp1; 3291215976Sjmallett}; 3292215976Sjmalletttypedef union cvmx_pciercx_cfg077 cvmx_pciercx_cfg077_t; 3293215976Sjmallett 3294215976Sjmallett/** 3295215976Sjmallett * cvmx_pcierc#_cfg448 3296215976Sjmallett * 3297215976Sjmallett * PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 1 config space 3298215976Sjmallett * (Ack Latency Timer and Replay Timer Register) 3299215976Sjmallett */ 3300215976Sjmallettunion cvmx_pciercx_cfg448 3301215976Sjmallett{ 3302215976Sjmallett uint32_t u32; 3303215976Sjmallett struct cvmx_pciercx_cfg448_s 3304215976Sjmallett { 3305215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3306215976Sjmallett uint32_t rtl : 16; /**< Replay Time Limit 3307215976Sjmallett The replay timer expires when it reaches this limit. The PCI 3308215976Sjmallett Express bus initiates a replay upon reception of a Nak or when 3309215976Sjmallett the replay timer expires. 3310215976Sjmallett The default is then updated based on the Negotiated Link Width 3311215976Sjmallett and Max_Payload_Size. */ 3312215976Sjmallett uint32_t rtltl : 16; /**< Round Trip Latency Time Limit 3313215976Sjmallett The Ack/Nak latency timer expires when it reaches this limit. 3314215976Sjmallett The default is then updated based on the Negotiated Link Width 3315215976Sjmallett and Max_Payload_Size. */ 3316215976Sjmallett#else 3317215976Sjmallett uint32_t rtltl : 16; 3318215976Sjmallett uint32_t rtl : 16; 3319215976Sjmallett#endif 3320215976Sjmallett } s; 3321215976Sjmallett struct cvmx_pciercx_cfg448_s cn52xx; 3322215976Sjmallett struct cvmx_pciercx_cfg448_s cn52xxp1; 3323215976Sjmallett struct cvmx_pciercx_cfg448_s cn56xx; 3324215976Sjmallett struct cvmx_pciercx_cfg448_s cn56xxp1; 3325215976Sjmallett struct cvmx_pciercx_cfg448_s cn63xx; 3326215976Sjmallett struct cvmx_pciercx_cfg448_s cn63xxp1; 3327215976Sjmallett}; 3328215976Sjmalletttypedef union cvmx_pciercx_cfg448 cvmx_pciercx_cfg448_t; 3329215976Sjmallett 3330215976Sjmallett/** 3331215976Sjmallett * cvmx_pcierc#_cfg449 3332215976Sjmallett * 3333215976Sjmallett * PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 1 config space 3334215976Sjmallett * (Other Message Register) 3335215976Sjmallett */ 3336215976Sjmallettunion cvmx_pciercx_cfg449 3337215976Sjmallett{ 3338215976Sjmallett uint32_t u32; 3339215976Sjmallett struct cvmx_pciercx_cfg449_s 3340215976Sjmallett { 3341215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3342215976Sjmallett uint32_t omr : 32; /**< Other Message Register 3343215976Sjmallett This register can be used for either of the following purposes: 3344215976Sjmallett o To send a specific PCI Express Message, the application 3345215976Sjmallett writes the payload of the Message into this register, then 3346215976Sjmallett sets bit 0 of the Port Link Control Register to send the 3347215976Sjmallett Message. 3348215976Sjmallett o To store a corruption pattern for corrupting the LCRC on all 3349215976Sjmallett TLPs, the application places a 32-bit corruption pattern into 3350215976Sjmallett this register and enables this function by setting bit 25 of 3351215976Sjmallett the Port Link Control Register. When enabled, the transmit 3352215976Sjmallett LCRC result is XOR'd with this pattern before inserting 3353215976Sjmallett it into the packet. */ 3354215976Sjmallett#else 3355215976Sjmallett uint32_t omr : 32; 3356215976Sjmallett#endif 3357215976Sjmallett } s; 3358215976Sjmallett struct cvmx_pciercx_cfg449_s cn52xx; 3359215976Sjmallett struct cvmx_pciercx_cfg449_s cn52xxp1; 3360215976Sjmallett struct cvmx_pciercx_cfg449_s cn56xx; 3361215976Sjmallett struct cvmx_pciercx_cfg449_s cn56xxp1; 3362215976Sjmallett struct cvmx_pciercx_cfg449_s cn63xx; 3363215976Sjmallett struct cvmx_pciercx_cfg449_s cn63xxp1; 3364215976Sjmallett}; 3365215976Sjmalletttypedef union cvmx_pciercx_cfg449 cvmx_pciercx_cfg449_t; 3366215976Sjmallett 3367215976Sjmallett/** 3368215976Sjmallett * cvmx_pcierc#_cfg450 3369215976Sjmallett * 3370215976Sjmallett * PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 1 config space 3371215976Sjmallett * (Port Force Link Register) 3372215976Sjmallett */ 3373215976Sjmallettunion cvmx_pciercx_cfg450 3374215976Sjmallett{ 3375215976Sjmallett uint32_t u32; 3376215976Sjmallett struct cvmx_pciercx_cfg450_s 3377215976Sjmallett { 3378215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3379215976Sjmallett uint32_t lpec : 8; /**< Low Power Entrance Count 3380215976Sjmallett The Power Management state will wait for this many clock cycles 3381215976Sjmallett for the associated completion of a CfgWr to PCIE_CFG017 register 3382215976Sjmallett Power State (PS) field register to go low-power. This register 3383215976Sjmallett is intended for applications that do not let the PCI Express 3384215976Sjmallett bus handle a completion for configuration request to the 3385215976Sjmallett Power Management Control and Status (PCIE_CFG017) register. */ 3386215976Sjmallett uint32_t reserved_22_23 : 2; 3387215976Sjmallett uint32_t link_state : 6; /**< Link State 3388215976Sjmallett The Link state that the PCI Express Bus will be forced to 3389215976Sjmallett when bit 15 (Force Link) is set. 3390215976Sjmallett State encoding: 3391215976Sjmallett o DETECT_QUIET 00h 3392215976Sjmallett o DETECT_ACT 01h 3393215976Sjmallett o POLL_ACTIVE 02h 3394215976Sjmallett o POLL_COMPLIANCE 03h 3395215976Sjmallett o POLL_CONFIG 04h 3396215976Sjmallett o PRE_DETECT_QUIET 05h 3397215976Sjmallett o DETECT_WAIT 06h 3398215976Sjmallett o CFG_LINKWD_START 07h 3399215976Sjmallett o CFG_LINKWD_ACEPT 08h 3400215976Sjmallett o CFG_LANENUM_WAIT 09h 3401215976Sjmallett o CFG_LANENUM_ACEPT 0Ah 3402215976Sjmallett o CFG_COMPLETE 0Bh 3403215976Sjmallett o CFG_IDLE 0Ch 3404215976Sjmallett o RCVRY_LOCK 0Dh 3405215976Sjmallett o RCVRY_SPEED 0Eh 3406215976Sjmallett o RCVRY_RCVRCFG 0Fh 3407215976Sjmallett o RCVRY_IDLE 10h 3408215976Sjmallett o L0 11h 3409215976Sjmallett o L0S 12h 3410215976Sjmallett o L123_SEND_EIDLE 13h 3411215976Sjmallett o L1_IDLE 14h 3412215976Sjmallett o L2_IDLE 15h 3413215976Sjmallett o L2_WAKE 16h 3414215976Sjmallett o DISABLED_ENTRY 17h 3415215976Sjmallett o DISABLED_IDLE 18h 3416215976Sjmallett o DISABLED 19h 3417215976Sjmallett o LPBK_ENTRY 1Ah 3418215976Sjmallett o LPBK_ACTIVE 1Bh 3419215976Sjmallett o LPBK_EXIT 1Ch 3420215976Sjmallett o LPBK_EXIT_TIMEOUT 1Dh 3421215976Sjmallett o HOT_RESET_ENTRY 1Eh 3422215976Sjmallett o HOT_RESET 1Fh */ 3423215976Sjmallett uint32_t force_link : 1; /**< Force Link 3424215976Sjmallett Forces the Link to the state specified by the Link State field. 3425215976Sjmallett The Force Link pulse will trigger Link re-negotiation. 3426215976Sjmallett * As the The Force Link is a pulse, writing a 1 to it does 3427215976Sjmallett trigger the forced link state event, even thought reading it 3428215976Sjmallett always returns a 0. */ 3429215976Sjmallett uint32_t reserved_8_14 : 7; 3430215976Sjmallett uint32_t link_num : 8; /**< Link Number */ 3431215976Sjmallett#else 3432215976Sjmallett uint32_t link_num : 8; 3433215976Sjmallett uint32_t reserved_8_14 : 7; 3434215976Sjmallett uint32_t force_link : 1; 3435215976Sjmallett uint32_t link_state : 6; 3436215976Sjmallett uint32_t reserved_22_23 : 2; 3437215976Sjmallett uint32_t lpec : 8; 3438215976Sjmallett#endif 3439215976Sjmallett } s; 3440215976Sjmallett struct cvmx_pciercx_cfg450_s cn52xx; 3441215976Sjmallett struct cvmx_pciercx_cfg450_s cn52xxp1; 3442215976Sjmallett struct cvmx_pciercx_cfg450_s cn56xx; 3443215976Sjmallett struct cvmx_pciercx_cfg450_s cn56xxp1; 3444215976Sjmallett struct cvmx_pciercx_cfg450_s cn63xx; 3445215976Sjmallett struct cvmx_pciercx_cfg450_s cn63xxp1; 3446215976Sjmallett}; 3447215976Sjmalletttypedef union cvmx_pciercx_cfg450 cvmx_pciercx_cfg450_t; 3448215976Sjmallett 3449215976Sjmallett/** 3450215976Sjmallett * cvmx_pcierc#_cfg451 3451215976Sjmallett * 3452215976Sjmallett * PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 1 config space 3453215976Sjmallett * (Ack Frequency Register) 3454215976Sjmallett */ 3455215976Sjmallettunion cvmx_pciercx_cfg451 3456215976Sjmallett{ 3457215976Sjmallett uint32_t u32; 3458215976Sjmallett struct cvmx_pciercx_cfg451_s 3459215976Sjmallett { 3460215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3461215976Sjmallett uint32_t reserved_30_31 : 2; 3462215976Sjmallett uint32_t l1el : 3; /**< L1 Entrance Latency 3463215976Sjmallett Values correspond to: 3464215976Sjmallett o 000: 1 ms 3465215976Sjmallett o 001: 2 ms 3466215976Sjmallett o 010: 4 ms 3467215976Sjmallett o 011: 8 ms 3468215976Sjmallett o 100: 16 ms 3469215976Sjmallett o 101: 32 ms 3470215976Sjmallett o 110 or 111: 64 ms */ 3471215976Sjmallett uint32_t l0el : 3; /**< L0s Entrance Latency 3472215976Sjmallett Values correspond to: 3473215976Sjmallett o 000: 1 ms 3474215976Sjmallett o 001: 2 ms 3475215976Sjmallett o 010: 3 ms 3476215976Sjmallett o 011: 4 ms 3477215976Sjmallett o 100: 5 ms 3478215976Sjmallett o 101: 6 ms 3479215976Sjmallett o 110 or 111: 7 ms */ 3480215976Sjmallett uint32_t n_fts_cc : 8; /**< N_FTS when common clock is used. 3481215976Sjmallett The number of Fast Training Sequence ordered sets to be 3482215976Sjmallett transmitted when transitioning from L0s to L0. The maximum 3483215976Sjmallett number of FTS ordered-sets that a component can request is 255. 3484215976Sjmallett Note: The core does not support a value of zero; a value of 3485215976Sjmallett zero can cause the LTSSM to go into the recovery state 3486215976Sjmallett when exiting from L0s. */ 3487215976Sjmallett uint32_t n_fts : 8; /**< N_FTS 3488215976Sjmallett The number of Fast Training Sequence ordered sets to be 3489215976Sjmallett transmitted when transitioning from L0s to L0. The maximum 3490215976Sjmallett number of FTS ordered-sets that a component can request is 255. 3491215976Sjmallett Note: The core does not support a value of zero; a value of 3492215976Sjmallett zero can cause the LTSSM to go into the recovery state 3493215976Sjmallett when exiting from L0s. */ 3494215976Sjmallett uint32_t ack_freq : 8; /**< Ack Frequency 3495215976Sjmallett The number of pending Ack's specified here (up to 255) before 3496215976Sjmallett sending an Ack. */ 3497215976Sjmallett#else 3498215976Sjmallett uint32_t ack_freq : 8; 3499215976Sjmallett uint32_t n_fts : 8; 3500215976Sjmallett uint32_t n_fts_cc : 8; 3501215976Sjmallett uint32_t l0el : 3; 3502215976Sjmallett uint32_t l1el : 3; 3503215976Sjmallett uint32_t reserved_30_31 : 2; 3504215976Sjmallett#endif 3505215976Sjmallett } s; 3506215976Sjmallett struct cvmx_pciercx_cfg451_s cn52xx; 3507215976Sjmallett struct cvmx_pciercx_cfg451_s cn52xxp1; 3508215976Sjmallett struct cvmx_pciercx_cfg451_s cn56xx; 3509215976Sjmallett struct cvmx_pciercx_cfg451_s cn56xxp1; 3510215976Sjmallett struct cvmx_pciercx_cfg451_s cn63xx; 3511215976Sjmallett struct cvmx_pciercx_cfg451_s cn63xxp1; 3512215976Sjmallett}; 3513215976Sjmalletttypedef union cvmx_pciercx_cfg451 cvmx_pciercx_cfg451_t; 3514215976Sjmallett 3515215976Sjmallett/** 3516215976Sjmallett * cvmx_pcierc#_cfg452 3517215976Sjmallett * 3518215976Sjmallett * PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 1 config space 3519215976Sjmallett * (Port Link Control Register) 3520215976Sjmallett */ 3521215976Sjmallettunion cvmx_pciercx_cfg452 3522215976Sjmallett{ 3523215976Sjmallett uint32_t u32; 3524215976Sjmallett struct cvmx_pciercx_cfg452_s 3525215976Sjmallett { 3526215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3527215976Sjmallett uint32_t reserved_26_31 : 6; 3528215976Sjmallett uint32_t eccrc : 1; /**< Enable Corrupted CRC 3529215976Sjmallett Causes corrupt LCRC for TLPs when set, 3530215976Sjmallett using the pattern contained in the Other Message register. 3531215976Sjmallett This is a test feature, not to be used in normal operation. */ 3532215976Sjmallett uint32_t reserved_22_24 : 3; 3533215976Sjmallett uint32_t lme : 6; /**< Link Mode Enable 3534215976Sjmallett o 000001: x1 3535215976Sjmallett o 000011: x2 3536215976Sjmallett o 000111: x4 3537215976Sjmallett o 001111: x8 (not supported) 3538215976Sjmallett o 011111: x16 (not supported) 3539215976Sjmallett o 111111: x32 (not supported) 3540215976Sjmallett This field indicates the MAXIMUM number of lanes supported 3541215976Sjmallett by the PCIe port. The value can be set less than 0x7 3542215976Sjmallett to limit the number of lanes the PCIe will attempt to use. 3543215976Sjmallett The programming of this field needs to be done by SW BEFORE 3544215976Sjmallett enabling the link. See also MLW. 3545215976Sjmallett (Note: The value of this field does NOT indicate the number 3546215976Sjmallett of lanes in use by the PCIe. LME sets the max number of lanes 3547215976Sjmallett in the PCIe core that COULD be used. As per the PCIe specs, 3548215976Sjmallett the PCIe core can negotiate a smaller link width, so all 3549215976Sjmallett of x4, x2, and x1 are supported when LME=0x7, 3550215976Sjmallett for example.) */ 3551215976Sjmallett uint32_t reserved_8_15 : 8; 3552215976Sjmallett uint32_t flm : 1; /**< Fast Link Mode 3553215976Sjmallett Sets all internal timers to fast mode for simulation purposes. */ 3554215976Sjmallett uint32_t reserved_6_6 : 1; 3555215976Sjmallett uint32_t dllle : 1; /**< DLL Link Enable 3556215976Sjmallett Enables Link initialization. If DLL Link Enable = 0, the PCI 3557215976Sjmallett Express bus does not transmit InitFC DLLPs and does not 3558215976Sjmallett establish a Link. */ 3559215976Sjmallett uint32_t reserved_4_4 : 1; 3560215976Sjmallett uint32_t ra : 1; /**< Reset Assert 3561215976Sjmallett Triggers a recovery and forces the LTSSM to the Hot Reset 3562215976Sjmallett state (downstream port only). */ 3563215976Sjmallett uint32_t le : 1; /**< Loopback Enable 3564215976Sjmallett Initiate loopback mode as a master. On a 0->1 transition, 3565215976Sjmallett the PCIe core sends TS ordered sets with the loopback bit set 3566215976Sjmallett to cause the link partner to enter into loopback mode as a 3567215976Sjmallett slave. Normal transmission is not possible when LE=1. To exit 3568215976Sjmallett loopback mode, take the link through a reset sequence. */ 3569215976Sjmallett uint32_t sd : 1; /**< Scramble Disable 3570215976Sjmallett Turns off data scrambling. */ 3571215976Sjmallett uint32_t omr : 1; /**< Other Message Request 3572215976Sjmallett When software writes a `1' to this bit, the PCI Express bus 3573215976Sjmallett transmits the Message contained in the Other Message register. */ 3574215976Sjmallett#else 3575215976Sjmallett uint32_t omr : 1; 3576215976Sjmallett uint32_t sd : 1; 3577215976Sjmallett uint32_t le : 1; 3578215976Sjmallett uint32_t ra : 1; 3579215976Sjmallett uint32_t reserved_4_4 : 1; 3580215976Sjmallett uint32_t dllle : 1; 3581215976Sjmallett uint32_t reserved_6_6 : 1; 3582215976Sjmallett uint32_t flm : 1; 3583215976Sjmallett uint32_t reserved_8_15 : 8; 3584215976Sjmallett uint32_t lme : 6; 3585215976Sjmallett uint32_t reserved_22_24 : 3; 3586215976Sjmallett uint32_t eccrc : 1; 3587215976Sjmallett uint32_t reserved_26_31 : 6; 3588215976Sjmallett#endif 3589215976Sjmallett } s; 3590215976Sjmallett struct cvmx_pciercx_cfg452_s cn52xx; 3591215976Sjmallett struct cvmx_pciercx_cfg452_s cn52xxp1; 3592215976Sjmallett struct cvmx_pciercx_cfg452_s cn56xx; 3593215976Sjmallett struct cvmx_pciercx_cfg452_s cn56xxp1; 3594215976Sjmallett struct cvmx_pciercx_cfg452_s cn63xx; 3595215976Sjmallett struct cvmx_pciercx_cfg452_s cn63xxp1; 3596215976Sjmallett}; 3597215976Sjmalletttypedef union cvmx_pciercx_cfg452 cvmx_pciercx_cfg452_t; 3598215976Sjmallett 3599215976Sjmallett/** 3600215976Sjmallett * cvmx_pcierc#_cfg453 3601215976Sjmallett * 3602215976Sjmallett * PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 1 config space 3603215976Sjmallett * (Lane Skew Register) 3604215976Sjmallett */ 3605215976Sjmallettunion cvmx_pciercx_cfg453 3606215976Sjmallett{ 3607215976Sjmallett uint32_t u32; 3608215976Sjmallett struct cvmx_pciercx_cfg453_s 3609215976Sjmallett { 3610215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3611215976Sjmallett uint32_t dlld : 1; /**< Disable Lane-to-Lane Deskew 3612215976Sjmallett Disables the internal Lane-to-Lane deskew logic. */ 3613215976Sjmallett uint32_t reserved_26_30 : 5; 3614215976Sjmallett uint32_t ack_nak : 1; /**< Ack/Nak Disable 3615215976Sjmallett Prevents the PCI Express bus from sending Ack and Nak DLLPs. */ 3616215976Sjmallett uint32_t fcd : 1; /**< Flow Control Disable 3617215976Sjmallett Prevents the PCI Express bus from sending FC DLLPs. */ 3618215976Sjmallett uint32_t ilst : 24; /**< Insert Lane Skew for Transmit (not supported for x16) 3619215976Sjmallett Causes skew between lanes for test purposes. There are three 3620215976Sjmallett bits per Lane. The value is in units of one symbol time. For 3621215976Sjmallett example, the value 010b for a Lane forces a skew of two symbol 3622215976Sjmallett times for that Lane. The maximum skew value for any Lane is 5 3623215976Sjmallett symbol times. */ 3624215976Sjmallett#else 3625215976Sjmallett uint32_t ilst : 24; 3626215976Sjmallett uint32_t fcd : 1; 3627215976Sjmallett uint32_t ack_nak : 1; 3628215976Sjmallett uint32_t reserved_26_30 : 5; 3629215976Sjmallett uint32_t dlld : 1; 3630215976Sjmallett#endif 3631215976Sjmallett } s; 3632215976Sjmallett struct cvmx_pciercx_cfg453_s cn52xx; 3633215976Sjmallett struct cvmx_pciercx_cfg453_s cn52xxp1; 3634215976Sjmallett struct cvmx_pciercx_cfg453_s cn56xx; 3635215976Sjmallett struct cvmx_pciercx_cfg453_s cn56xxp1; 3636215976Sjmallett struct cvmx_pciercx_cfg453_s cn63xx; 3637215976Sjmallett struct cvmx_pciercx_cfg453_s cn63xxp1; 3638215976Sjmallett}; 3639215976Sjmalletttypedef union cvmx_pciercx_cfg453 cvmx_pciercx_cfg453_t; 3640215976Sjmallett 3641215976Sjmallett/** 3642215976Sjmallett * cvmx_pcierc#_cfg454 3643215976Sjmallett * 3644215976Sjmallett * PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 1 config space 3645215976Sjmallett * (Symbol Number Register) 3646215976Sjmallett */ 3647215976Sjmallettunion cvmx_pciercx_cfg454 3648215976Sjmallett{ 3649215976Sjmallett uint32_t u32; 3650215976Sjmallett struct cvmx_pciercx_cfg454_s 3651215976Sjmallett { 3652215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3653215976Sjmallett uint32_t reserved_29_31 : 3; 3654215976Sjmallett uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer 3655215976Sjmallett Increases the timer value for the Flow Control watchdog timer, 3656215976Sjmallett in increments of 16 clock cycles. */ 3657215976Sjmallett uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer 3658215976Sjmallett Increases the timer value for the Ack/Nak latency timer, in 3659215976Sjmallett increments of 64 clock cycles. */ 3660215976Sjmallett uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer 3661215976Sjmallett Increases the timer value for the replay timer, in increments 3662215976Sjmallett of 64 clock cycles. */ 3663215976Sjmallett uint32_t reserved_11_13 : 3; 3664215976Sjmallett uint32_t nskps : 3; /**< Number of SKP Symbols */ 3665215976Sjmallett uint32_t reserved_4_7 : 4; 3666215976Sjmallett uint32_t ntss : 4; /**< Number of TS Symbols 3667215976Sjmallett Sets the number of TS identifier symbols that are sent in TS1 3668215976Sjmallett and TS2 ordered sets. */ 3669215976Sjmallett#else 3670215976Sjmallett uint32_t ntss : 4; 3671215976Sjmallett uint32_t reserved_4_7 : 4; 3672215976Sjmallett uint32_t nskps : 3; 3673215976Sjmallett uint32_t reserved_11_13 : 3; 3674215976Sjmallett uint32_t tmrt : 5; 3675215976Sjmallett uint32_t tmanlt : 5; 3676215976Sjmallett uint32_t tmfcwt : 5; 3677215976Sjmallett uint32_t reserved_29_31 : 3; 3678215976Sjmallett#endif 3679215976Sjmallett } s; 3680215976Sjmallett struct cvmx_pciercx_cfg454_s cn52xx; 3681215976Sjmallett struct cvmx_pciercx_cfg454_s cn52xxp1; 3682215976Sjmallett struct cvmx_pciercx_cfg454_s cn56xx; 3683215976Sjmallett struct cvmx_pciercx_cfg454_s cn56xxp1; 3684215976Sjmallett struct cvmx_pciercx_cfg454_s cn63xx; 3685215976Sjmallett struct cvmx_pciercx_cfg454_s cn63xxp1; 3686215976Sjmallett}; 3687215976Sjmalletttypedef union cvmx_pciercx_cfg454 cvmx_pciercx_cfg454_t; 3688215976Sjmallett 3689215976Sjmallett/** 3690215976Sjmallett * cvmx_pcierc#_cfg455 3691215976Sjmallett * 3692215976Sjmallett * PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 1 config space 3693215976Sjmallett * (Symbol Timer Register/Filter Mask Register 1) 3694215976Sjmallett */ 3695215976Sjmallettunion cvmx_pciercx_cfg455 3696215976Sjmallett{ 3697215976Sjmallett uint32_t u32; 3698215976Sjmallett struct cvmx_pciercx_cfg455_s 3699215976Sjmallett { 3700215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3701215976Sjmallett uint32_t m_cfg0_filt : 1; /**< Mask filtering of received Configuration Requests (RC mode only) */ 3702215976Sjmallett uint32_t m_io_filt : 1; /**< Mask filtering of received I/O Requests (RC mode only) */ 3703215976Sjmallett uint32_t msg_ctrl : 1; /**< Message Control 3704215976Sjmallett The application must not change this field. */ 3705215976Sjmallett uint32_t m_cpl_ecrc_filt : 1; /**< Mask ECRC error filtering for Completions */ 3706215976Sjmallett uint32_t m_ecrc_filt : 1; /**< Mask ECRC error filtering */ 3707215976Sjmallett uint32_t m_cpl_len_err : 1; /**< Mask Length mismatch error for received Completions */ 3708215976Sjmallett uint32_t m_cpl_attr_err : 1; /**< Mask Attributes mismatch error for received Completions */ 3709215976Sjmallett uint32_t m_cpl_tc_err : 1; /**< Mask Traffic Class mismatch error for received Completions */ 3710215976Sjmallett uint32_t m_cpl_fun_err : 1; /**< Mask function mismatch error for received Completions */ 3711215976Sjmallett uint32_t m_cpl_rid_err : 1; /**< Mask Requester ID mismatch error for received Completions */ 3712215976Sjmallett uint32_t m_cpl_tag_err : 1; /**< Mask Tag error rules for received Completions */ 3713215976Sjmallett uint32_t m_lk_filt : 1; /**< Mask Locked Request filtering */ 3714215976Sjmallett uint32_t m_cfg1_filt : 1; /**< Mask Type 1 Configuration Request filtering */ 3715215976Sjmallett uint32_t m_bar_match : 1; /**< Mask BAR match filtering */ 3716215976Sjmallett uint32_t m_pois_filt : 1; /**< Mask poisoned TLP filtering */ 3717215976Sjmallett uint32_t m_fun : 1; /**< Mask function */ 3718215976Sjmallett uint32_t dfcwt : 1; /**< Disable FC Watchdog Timer */ 3719215976Sjmallett uint32_t reserved_11_14 : 4; 3720215976Sjmallett uint32_t skpiv : 11; /**< SKP Interval Value */ 3721215976Sjmallett#else 3722215976Sjmallett uint32_t skpiv : 11; 3723215976Sjmallett uint32_t reserved_11_14 : 4; 3724215976Sjmallett uint32_t dfcwt : 1; 3725215976Sjmallett uint32_t m_fun : 1; 3726215976Sjmallett uint32_t m_pois_filt : 1; 3727215976Sjmallett uint32_t m_bar_match : 1; 3728215976Sjmallett uint32_t m_cfg1_filt : 1; 3729215976Sjmallett uint32_t m_lk_filt : 1; 3730215976Sjmallett uint32_t m_cpl_tag_err : 1; 3731215976Sjmallett uint32_t m_cpl_rid_err : 1; 3732215976Sjmallett uint32_t m_cpl_fun_err : 1; 3733215976Sjmallett uint32_t m_cpl_tc_err : 1; 3734215976Sjmallett uint32_t m_cpl_attr_err : 1; 3735215976Sjmallett uint32_t m_cpl_len_err : 1; 3736215976Sjmallett uint32_t m_ecrc_filt : 1; 3737215976Sjmallett uint32_t m_cpl_ecrc_filt : 1; 3738215976Sjmallett uint32_t msg_ctrl : 1; 3739215976Sjmallett uint32_t m_io_filt : 1; 3740215976Sjmallett uint32_t m_cfg0_filt : 1; 3741215976Sjmallett#endif 3742215976Sjmallett } s; 3743215976Sjmallett struct cvmx_pciercx_cfg455_s cn52xx; 3744215976Sjmallett struct cvmx_pciercx_cfg455_s cn52xxp1; 3745215976Sjmallett struct cvmx_pciercx_cfg455_s cn56xx; 3746215976Sjmallett struct cvmx_pciercx_cfg455_s cn56xxp1; 3747215976Sjmallett struct cvmx_pciercx_cfg455_s cn63xx; 3748215976Sjmallett struct cvmx_pciercx_cfg455_s cn63xxp1; 3749215976Sjmallett}; 3750215976Sjmalletttypedef union cvmx_pciercx_cfg455 cvmx_pciercx_cfg455_t; 3751215976Sjmallett 3752215976Sjmallett/** 3753215976Sjmallett * cvmx_pcierc#_cfg456 3754215976Sjmallett * 3755215976Sjmallett * PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 1 config space 3756215976Sjmallett * (Filter Mask Register 2) 3757215976Sjmallett */ 3758215976Sjmallettunion cvmx_pciercx_cfg456 3759215976Sjmallett{ 3760215976Sjmallett uint32_t u32; 3761215976Sjmallett struct cvmx_pciercx_cfg456_s 3762215976Sjmallett { 3763215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3764215976Sjmallett uint32_t reserved_2_31 : 30; 3765215976Sjmallett uint32_t m_vend1_drp : 1; /**< Mask Vendor MSG Type 1 dropped silently */ 3766215976Sjmallett uint32_t m_vend0_drp : 1; /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */ 3767215976Sjmallett#else 3768215976Sjmallett uint32_t m_vend0_drp : 1; 3769215976Sjmallett uint32_t m_vend1_drp : 1; 3770215976Sjmallett uint32_t reserved_2_31 : 30; 3771215976Sjmallett#endif 3772215976Sjmallett } s; 3773215976Sjmallett struct cvmx_pciercx_cfg456_s cn52xx; 3774215976Sjmallett struct cvmx_pciercx_cfg456_s cn52xxp1; 3775215976Sjmallett struct cvmx_pciercx_cfg456_s cn56xx; 3776215976Sjmallett struct cvmx_pciercx_cfg456_s cn56xxp1; 3777215976Sjmallett struct cvmx_pciercx_cfg456_s cn63xx; 3778215976Sjmallett struct cvmx_pciercx_cfg456_s cn63xxp1; 3779215976Sjmallett}; 3780215976Sjmalletttypedef union cvmx_pciercx_cfg456 cvmx_pciercx_cfg456_t; 3781215976Sjmallett 3782215976Sjmallett/** 3783215976Sjmallett * cvmx_pcierc#_cfg458 3784215976Sjmallett * 3785215976Sjmallett * PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 1 config space 3786215976Sjmallett * (Debug Register 0) 3787215976Sjmallett */ 3788215976Sjmallettunion cvmx_pciercx_cfg458 3789215976Sjmallett{ 3790215976Sjmallett uint32_t u32; 3791215976Sjmallett struct cvmx_pciercx_cfg458_s 3792215976Sjmallett { 3793215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3794215976Sjmallett uint32_t dbg_info_l32 : 32; /**< The value on cxpl_debug_info[31:0]. */ 3795215976Sjmallett#else 3796215976Sjmallett uint32_t dbg_info_l32 : 32; 3797215976Sjmallett#endif 3798215976Sjmallett } s; 3799215976Sjmallett struct cvmx_pciercx_cfg458_s cn52xx; 3800215976Sjmallett struct cvmx_pciercx_cfg458_s cn52xxp1; 3801215976Sjmallett struct cvmx_pciercx_cfg458_s cn56xx; 3802215976Sjmallett struct cvmx_pciercx_cfg458_s cn56xxp1; 3803215976Sjmallett struct cvmx_pciercx_cfg458_s cn63xx; 3804215976Sjmallett struct cvmx_pciercx_cfg458_s cn63xxp1; 3805215976Sjmallett}; 3806215976Sjmalletttypedef union cvmx_pciercx_cfg458 cvmx_pciercx_cfg458_t; 3807215976Sjmallett 3808215976Sjmallett/** 3809215976Sjmallett * cvmx_pcierc#_cfg459 3810215976Sjmallett * 3811215976Sjmallett * PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 1 config space 3812215976Sjmallett * (Debug Register 1) 3813215976Sjmallett */ 3814215976Sjmallettunion cvmx_pciercx_cfg459 3815215976Sjmallett{ 3816215976Sjmallett uint32_t u32; 3817215976Sjmallett struct cvmx_pciercx_cfg459_s 3818215976Sjmallett { 3819215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3820215976Sjmallett uint32_t dbg_info_u32 : 32; /**< The value on cxpl_debug_info[63:32]. */ 3821215976Sjmallett#else 3822215976Sjmallett uint32_t dbg_info_u32 : 32; 3823215976Sjmallett#endif 3824215976Sjmallett } s; 3825215976Sjmallett struct cvmx_pciercx_cfg459_s cn52xx; 3826215976Sjmallett struct cvmx_pciercx_cfg459_s cn52xxp1; 3827215976Sjmallett struct cvmx_pciercx_cfg459_s cn56xx; 3828215976Sjmallett struct cvmx_pciercx_cfg459_s cn56xxp1; 3829215976Sjmallett struct cvmx_pciercx_cfg459_s cn63xx; 3830215976Sjmallett struct cvmx_pciercx_cfg459_s cn63xxp1; 3831215976Sjmallett}; 3832215976Sjmalletttypedef union cvmx_pciercx_cfg459 cvmx_pciercx_cfg459_t; 3833215976Sjmallett 3834215976Sjmallett/** 3835215976Sjmallett * cvmx_pcierc#_cfg460 3836215976Sjmallett * 3837215976Sjmallett * PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 1 config space 3838215976Sjmallett * (Transmit Posted FC Credit Status) 3839215976Sjmallett */ 3840215976Sjmallettunion cvmx_pciercx_cfg460 3841215976Sjmallett{ 3842215976Sjmallett uint32_t u32; 3843215976Sjmallett struct cvmx_pciercx_cfg460_s 3844215976Sjmallett { 3845215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3846215976Sjmallett uint32_t reserved_20_31 : 12; 3847215976Sjmallett uint32_t tphfcc : 8; /**< Transmit Posted Header FC Credits 3848215976Sjmallett The Posted Header credits advertised by the receiver at the 3849215976Sjmallett other end of the Link, updated with each UpdateFC DLLP. */ 3850215976Sjmallett uint32_t tpdfcc : 12; /**< Transmit Posted Data FC Credits 3851215976Sjmallett The Posted Data credits advertised by the receiver at the other 3852215976Sjmallett end of the Link, updated with each UpdateFC DLLP. */ 3853215976Sjmallett#else 3854215976Sjmallett uint32_t tpdfcc : 12; 3855215976Sjmallett uint32_t tphfcc : 8; 3856215976Sjmallett uint32_t reserved_20_31 : 12; 3857215976Sjmallett#endif 3858215976Sjmallett } s; 3859215976Sjmallett struct cvmx_pciercx_cfg460_s cn52xx; 3860215976Sjmallett struct cvmx_pciercx_cfg460_s cn52xxp1; 3861215976Sjmallett struct cvmx_pciercx_cfg460_s cn56xx; 3862215976Sjmallett struct cvmx_pciercx_cfg460_s cn56xxp1; 3863215976Sjmallett struct cvmx_pciercx_cfg460_s cn63xx; 3864215976Sjmallett struct cvmx_pciercx_cfg460_s cn63xxp1; 3865215976Sjmallett}; 3866215976Sjmalletttypedef union cvmx_pciercx_cfg460 cvmx_pciercx_cfg460_t; 3867215976Sjmallett 3868215976Sjmallett/** 3869215976Sjmallett * cvmx_pcierc#_cfg461 3870215976Sjmallett * 3871215976Sjmallett * PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 1 config space 3872215976Sjmallett * (Transmit Non-Posted FC Credit Status) 3873215976Sjmallett */ 3874215976Sjmallettunion cvmx_pciercx_cfg461 3875215976Sjmallett{ 3876215976Sjmallett uint32_t u32; 3877215976Sjmallett struct cvmx_pciercx_cfg461_s 3878215976Sjmallett { 3879215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3880215976Sjmallett uint32_t reserved_20_31 : 12; 3881215976Sjmallett uint32_t tchfcc : 8; /**< Transmit Non-Posted Header FC Credits 3882215976Sjmallett The Non-Posted Header credits advertised by the receiver at the 3883215976Sjmallett other end of the Link, updated with each UpdateFC DLLP. */ 3884215976Sjmallett uint32_t tcdfcc : 12; /**< Transmit Non-Posted Data FC Credits 3885215976Sjmallett The Non-Posted Data credits advertised by the receiver at the 3886215976Sjmallett other end of the Link, updated with each UpdateFC DLLP. */ 3887215976Sjmallett#else 3888215976Sjmallett uint32_t tcdfcc : 12; 3889215976Sjmallett uint32_t tchfcc : 8; 3890215976Sjmallett uint32_t reserved_20_31 : 12; 3891215976Sjmallett#endif 3892215976Sjmallett } s; 3893215976Sjmallett struct cvmx_pciercx_cfg461_s cn52xx; 3894215976Sjmallett struct cvmx_pciercx_cfg461_s cn52xxp1; 3895215976Sjmallett struct cvmx_pciercx_cfg461_s cn56xx; 3896215976Sjmallett struct cvmx_pciercx_cfg461_s cn56xxp1; 3897215976Sjmallett struct cvmx_pciercx_cfg461_s cn63xx; 3898215976Sjmallett struct cvmx_pciercx_cfg461_s cn63xxp1; 3899215976Sjmallett}; 3900215976Sjmalletttypedef union cvmx_pciercx_cfg461 cvmx_pciercx_cfg461_t; 3901215976Sjmallett 3902215976Sjmallett/** 3903215976Sjmallett * cvmx_pcierc#_cfg462 3904215976Sjmallett * 3905215976Sjmallett * PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 1 config space 3906215976Sjmallett * (Transmit Completion FC Credit Status ) 3907215976Sjmallett */ 3908215976Sjmallettunion cvmx_pciercx_cfg462 3909215976Sjmallett{ 3910215976Sjmallett uint32_t u32; 3911215976Sjmallett struct cvmx_pciercx_cfg462_s 3912215976Sjmallett { 3913215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3914215976Sjmallett uint32_t reserved_20_31 : 12; 3915215976Sjmallett uint32_t tchfcc : 8; /**< Transmit Completion Header FC Credits 3916215976Sjmallett The Completion Header credits advertised by the receiver at the 3917215976Sjmallett other end of the Link, updated with each UpdateFC DLLP. */ 3918215976Sjmallett uint32_t tcdfcc : 12; /**< Transmit Completion Data FC Credits 3919215976Sjmallett The Completion Data credits advertised by the receiver at the 3920215976Sjmallett other end of the Link, updated with each UpdateFC DLLP. */ 3921215976Sjmallett#else 3922215976Sjmallett uint32_t tcdfcc : 12; 3923215976Sjmallett uint32_t tchfcc : 8; 3924215976Sjmallett uint32_t reserved_20_31 : 12; 3925215976Sjmallett#endif 3926215976Sjmallett } s; 3927215976Sjmallett struct cvmx_pciercx_cfg462_s cn52xx; 3928215976Sjmallett struct cvmx_pciercx_cfg462_s cn52xxp1; 3929215976Sjmallett struct cvmx_pciercx_cfg462_s cn56xx; 3930215976Sjmallett struct cvmx_pciercx_cfg462_s cn56xxp1; 3931215976Sjmallett struct cvmx_pciercx_cfg462_s cn63xx; 3932215976Sjmallett struct cvmx_pciercx_cfg462_s cn63xxp1; 3933215976Sjmallett}; 3934215976Sjmalletttypedef union cvmx_pciercx_cfg462 cvmx_pciercx_cfg462_t; 3935215976Sjmallett 3936215976Sjmallett/** 3937215976Sjmallett * cvmx_pcierc#_cfg463 3938215976Sjmallett * 3939215976Sjmallett * PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 1 config space 3940215976Sjmallett * (Queue Status) 3941215976Sjmallett */ 3942215976Sjmallettunion cvmx_pciercx_cfg463 3943215976Sjmallett{ 3944215976Sjmallett uint32_t u32; 3945215976Sjmallett struct cvmx_pciercx_cfg463_s 3946215976Sjmallett { 3947215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3948215976Sjmallett uint32_t reserved_3_31 : 29; 3949215976Sjmallett uint32_t rqne : 1; /**< Received Queue Not Empty 3950215976Sjmallett Indicates there is data in one or more of the receive buffers. */ 3951215976Sjmallett uint32_t trbne : 1; /**< Transmit Retry Buffer Not Empty 3952215976Sjmallett Indicates that there is data in the transmit retry buffer. */ 3953215976Sjmallett uint32_t rtlpfccnr : 1; /**< Received TLP FC Credits Not Returned 3954215976Sjmallett Indicates that the PCI Express bus has sent a TLP but has not 3955215976Sjmallett yet received an UpdateFC DLLP indicating that the credits for 3956215976Sjmallett that TLP have been restored by the receiver at the other end of 3957215976Sjmallett the Link. */ 3958215976Sjmallett#else 3959215976Sjmallett uint32_t rtlpfccnr : 1; 3960215976Sjmallett uint32_t trbne : 1; 3961215976Sjmallett uint32_t rqne : 1; 3962215976Sjmallett uint32_t reserved_3_31 : 29; 3963215976Sjmallett#endif 3964215976Sjmallett } s; 3965215976Sjmallett struct cvmx_pciercx_cfg463_s cn52xx; 3966215976Sjmallett struct cvmx_pciercx_cfg463_s cn52xxp1; 3967215976Sjmallett struct cvmx_pciercx_cfg463_s cn56xx; 3968215976Sjmallett struct cvmx_pciercx_cfg463_s cn56xxp1; 3969215976Sjmallett struct cvmx_pciercx_cfg463_s cn63xx; 3970215976Sjmallett struct cvmx_pciercx_cfg463_s cn63xxp1; 3971215976Sjmallett}; 3972215976Sjmalletttypedef union cvmx_pciercx_cfg463 cvmx_pciercx_cfg463_t; 3973215976Sjmallett 3974215976Sjmallett/** 3975215976Sjmallett * cvmx_pcierc#_cfg464 3976215976Sjmallett * 3977215976Sjmallett * PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 1 config space 3978215976Sjmallett * (VC Transmit Arbitration Register 1) 3979215976Sjmallett */ 3980215976Sjmallettunion cvmx_pciercx_cfg464 3981215976Sjmallett{ 3982215976Sjmallett uint32_t u32; 3983215976Sjmallett struct cvmx_pciercx_cfg464_s 3984215976Sjmallett { 3985215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3986215976Sjmallett uint32_t wrr_vc3 : 8; /**< WRR Weight for VC3 */ 3987215976Sjmallett uint32_t wrr_vc2 : 8; /**< WRR Weight for VC2 */ 3988215976Sjmallett uint32_t wrr_vc1 : 8; /**< WRR Weight for VC1 */ 3989215976Sjmallett uint32_t wrr_vc0 : 8; /**< WRR Weight for VC0 */ 3990215976Sjmallett#else 3991215976Sjmallett uint32_t wrr_vc0 : 8; 3992215976Sjmallett uint32_t wrr_vc1 : 8; 3993215976Sjmallett uint32_t wrr_vc2 : 8; 3994215976Sjmallett uint32_t wrr_vc3 : 8; 3995215976Sjmallett#endif 3996215976Sjmallett } s; 3997215976Sjmallett struct cvmx_pciercx_cfg464_s cn52xx; 3998215976Sjmallett struct cvmx_pciercx_cfg464_s cn52xxp1; 3999215976Sjmallett struct cvmx_pciercx_cfg464_s cn56xx; 4000215976Sjmallett struct cvmx_pciercx_cfg464_s cn56xxp1; 4001215976Sjmallett struct cvmx_pciercx_cfg464_s cn63xx; 4002215976Sjmallett struct cvmx_pciercx_cfg464_s cn63xxp1; 4003215976Sjmallett}; 4004215976Sjmalletttypedef union cvmx_pciercx_cfg464 cvmx_pciercx_cfg464_t; 4005215976Sjmallett 4006215976Sjmallett/** 4007215976Sjmallett * cvmx_pcierc#_cfg465 4008215976Sjmallett * 4009215976Sjmallett * PCIE_CFG465 = Four hundred sixty-sixth 32-bits of config space 4010215976Sjmallett * (VC Transmit Arbitration Register 2) 4011215976Sjmallett */ 4012215976Sjmallettunion cvmx_pciercx_cfg465 4013215976Sjmallett{ 4014215976Sjmallett uint32_t u32; 4015215976Sjmallett struct cvmx_pciercx_cfg465_s 4016215976Sjmallett { 4017215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4018215976Sjmallett uint32_t wrr_vc7 : 8; /**< WRR Weight for VC7 */ 4019215976Sjmallett uint32_t wrr_vc6 : 8; /**< WRR Weight for VC6 */ 4020215976Sjmallett uint32_t wrr_vc5 : 8; /**< WRR Weight for VC5 */ 4021215976Sjmallett uint32_t wrr_vc4 : 8; /**< WRR Weight for VC4 */ 4022215976Sjmallett#else 4023215976Sjmallett uint32_t wrr_vc4 : 8; 4024215976Sjmallett uint32_t wrr_vc5 : 8; 4025215976Sjmallett uint32_t wrr_vc6 : 8; 4026215976Sjmallett uint32_t wrr_vc7 : 8; 4027215976Sjmallett#endif 4028215976Sjmallett } s; 4029215976Sjmallett struct cvmx_pciercx_cfg465_s cn52xx; 4030215976Sjmallett struct cvmx_pciercx_cfg465_s cn52xxp1; 4031215976Sjmallett struct cvmx_pciercx_cfg465_s cn56xx; 4032215976Sjmallett struct cvmx_pciercx_cfg465_s cn56xxp1; 4033215976Sjmallett struct cvmx_pciercx_cfg465_s cn63xx; 4034215976Sjmallett struct cvmx_pciercx_cfg465_s cn63xxp1; 4035215976Sjmallett}; 4036215976Sjmalletttypedef union cvmx_pciercx_cfg465 cvmx_pciercx_cfg465_t; 4037215976Sjmallett 4038215976Sjmallett/** 4039215976Sjmallett * cvmx_pcierc#_cfg466 4040215976Sjmallett * 4041215976Sjmallett * PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 1 config space 4042215976Sjmallett * (VC0 Posted Receive Queue Control) 4043215976Sjmallett */ 4044215976Sjmallettunion cvmx_pciercx_cfg466 4045215976Sjmallett{ 4046215976Sjmallett uint32_t u32; 4047215976Sjmallett struct cvmx_pciercx_cfg466_s 4048215976Sjmallett { 4049215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4050215976Sjmallett uint32_t rx_queue_order : 1; /**< VC Ordering for Receive Queues 4051215976Sjmallett Determines the VC ordering rule for the receive queues, used 4052215976Sjmallett only in the segmented-buffer configuration, 4053215976Sjmallett writable through PEM(0..1)_CFG_WR: 4054215976Sjmallett o 1: Strict ordering, higher numbered VCs have higher priority 4055215976Sjmallett o 0: Round robin 4056215976Sjmallett However, the application must not change this field. */ 4057215976Sjmallett uint32_t type_ordering : 1; /**< TLP Type Ordering for VC0 4058215976Sjmallett Determines the TLP type ordering rule for VC0 receive queues, 4059215976Sjmallett used only in the segmented-buffer configuration, writable 4060215976Sjmallett through PEM(0..1)_CFG_WR: 4061215976Sjmallett o 1: Ordering of received TLPs follows the rules in 4062215976Sjmallett PCI Express Base Specification 4063215976Sjmallett o 0: Strict ordering for received TLPs: Posted, then 4064215976Sjmallett Completion, then Non-Posted 4065215976Sjmallett However, the application must not change this field. */ 4066215976Sjmallett uint32_t reserved_24_29 : 6; 4067215976Sjmallett uint32_t queue_mode : 3; /**< VC0 Posted TLP Queue Mode 4068215976Sjmallett The operating mode of the Posted receive queue for VC0, used 4069215976Sjmallett only in the segmented-buffer configuration, writable through 4070215976Sjmallett PEM(0..1)_CFG_WR. 4071215976Sjmallett However, the application must not change this field. 4072215976Sjmallett Only one bit can be set at a time: 4073215976Sjmallett o Bit 23: Bypass 4074215976Sjmallett o Bit 22: Cut-through 4075215976Sjmallett o Bit 21: Store-and-forward */ 4076215976Sjmallett uint32_t reserved_20_20 : 1; 4077215976Sjmallett uint32_t header_credits : 8; /**< VC0 Posted Header Credits 4078215976Sjmallett The number of initial Posted header credits for VC0, used for 4079215976Sjmallett all receive queue buffer configurations. 4080215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 4081215976Sjmallett However, the application must not change this field. */ 4082215976Sjmallett uint32_t data_credits : 12; /**< VC0 Posted Data Credits 4083215976Sjmallett The number of initial Posted data credits for VC0, used for all 4084215976Sjmallett receive queue buffer configurations. 4085215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 4086215976Sjmallett However, the application must not change this field. */ 4087215976Sjmallett#else 4088215976Sjmallett uint32_t data_credits : 12; 4089215976Sjmallett uint32_t header_credits : 8; 4090215976Sjmallett uint32_t reserved_20_20 : 1; 4091215976Sjmallett uint32_t queue_mode : 3; 4092215976Sjmallett uint32_t reserved_24_29 : 6; 4093215976Sjmallett uint32_t type_ordering : 1; 4094215976Sjmallett uint32_t rx_queue_order : 1; 4095215976Sjmallett#endif 4096215976Sjmallett } s; 4097215976Sjmallett struct cvmx_pciercx_cfg466_s cn52xx; 4098215976Sjmallett struct cvmx_pciercx_cfg466_s cn52xxp1; 4099215976Sjmallett struct cvmx_pciercx_cfg466_s cn56xx; 4100215976Sjmallett struct cvmx_pciercx_cfg466_s cn56xxp1; 4101215976Sjmallett struct cvmx_pciercx_cfg466_s cn63xx; 4102215976Sjmallett struct cvmx_pciercx_cfg466_s cn63xxp1; 4103215976Sjmallett}; 4104215976Sjmalletttypedef union cvmx_pciercx_cfg466 cvmx_pciercx_cfg466_t; 4105215976Sjmallett 4106215976Sjmallett/** 4107215976Sjmallett * cvmx_pcierc#_cfg467 4108215976Sjmallett * 4109215976Sjmallett * PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 1 config space 4110215976Sjmallett * (VC0 Non-Posted Receive Queue Control) 4111215976Sjmallett */ 4112215976Sjmallettunion cvmx_pciercx_cfg467 4113215976Sjmallett{ 4114215976Sjmallett uint32_t u32; 4115215976Sjmallett struct cvmx_pciercx_cfg467_s 4116215976Sjmallett { 4117215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4118215976Sjmallett uint32_t reserved_24_31 : 8; 4119215976Sjmallett uint32_t queue_mode : 3; /**< VC0 Non-Posted TLP Queue Mode 4120215976Sjmallett The operating mode of the Non-Posted receive queue for VC0, 4121215976Sjmallett used only in the segmented-buffer configuration, writable 4122215976Sjmallett through PEM(0..1)_CFG_WR. 4123215976Sjmallett Only one bit can be set at a time: 4124215976Sjmallett o Bit 23: Bypass 4125215976Sjmallett o Bit 22: Cut-through 4126215976Sjmallett o Bit 21: Store-and-forward 4127215976Sjmallett However, the application must not change this field. */ 4128215976Sjmallett uint32_t reserved_20_20 : 1; 4129215976Sjmallett uint32_t header_credits : 8; /**< VC0 Non-Posted Header Credits 4130215976Sjmallett The number of initial Non-Posted header credits for VC0, used 4131215976Sjmallett for all receive queue buffer configurations. 4132215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 4133215976Sjmallett However, the application must not change this field. */ 4134215976Sjmallett uint32_t data_credits : 12; /**< VC0 Non-Posted Data Credits 4135215976Sjmallett The number of initial Non-Posted data credits for VC0, used for 4136215976Sjmallett all receive queue buffer configurations. 4137215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 4138215976Sjmallett However, the application must not change this field. */ 4139215976Sjmallett#else 4140215976Sjmallett uint32_t data_credits : 12; 4141215976Sjmallett uint32_t header_credits : 8; 4142215976Sjmallett uint32_t reserved_20_20 : 1; 4143215976Sjmallett uint32_t queue_mode : 3; 4144215976Sjmallett uint32_t reserved_24_31 : 8; 4145215976Sjmallett#endif 4146215976Sjmallett } s; 4147215976Sjmallett struct cvmx_pciercx_cfg467_s cn52xx; 4148215976Sjmallett struct cvmx_pciercx_cfg467_s cn52xxp1; 4149215976Sjmallett struct cvmx_pciercx_cfg467_s cn56xx; 4150215976Sjmallett struct cvmx_pciercx_cfg467_s cn56xxp1; 4151215976Sjmallett struct cvmx_pciercx_cfg467_s cn63xx; 4152215976Sjmallett struct cvmx_pciercx_cfg467_s cn63xxp1; 4153215976Sjmallett}; 4154215976Sjmalletttypedef union cvmx_pciercx_cfg467 cvmx_pciercx_cfg467_t; 4155215976Sjmallett 4156215976Sjmallett/** 4157215976Sjmallett * cvmx_pcierc#_cfg468 4158215976Sjmallett * 4159215976Sjmallett * PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 1 config space 4160215976Sjmallett * (VC0 Completion Receive Queue Control) 4161215976Sjmallett */ 4162215976Sjmallettunion cvmx_pciercx_cfg468 4163215976Sjmallett{ 4164215976Sjmallett uint32_t u32; 4165215976Sjmallett struct cvmx_pciercx_cfg468_s 4166215976Sjmallett { 4167215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4168215976Sjmallett uint32_t reserved_24_31 : 8; 4169215976Sjmallett uint32_t queue_mode : 3; /**< VC0 Completion TLP Queue Mode 4170215976Sjmallett The operating mode of the Completion receive queue for VC0, 4171215976Sjmallett used only in the segmented-buffer configuration, writable 4172215976Sjmallett through PEM(0..1)_CFG_WR. 4173215976Sjmallett Only one bit can be set at a time: 4174215976Sjmallett o Bit 23: Bypass 4175215976Sjmallett o Bit 22: Cut-through 4176215976Sjmallett o Bit 21: Store-and-forward 4177215976Sjmallett However, the application must not change this field. */ 4178215976Sjmallett uint32_t reserved_20_20 : 1; 4179215976Sjmallett uint32_t header_credits : 8; /**< VC0 Completion Header Credits 4180215976Sjmallett The number of initial Completion header credits for VC0, used 4181215976Sjmallett for all receive queue buffer configurations. 4182215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 4183215976Sjmallett However, the application must not change this field. */ 4184215976Sjmallett uint32_t data_credits : 12; /**< VC0 Completion Data Credits 4185215976Sjmallett The number of initial Completion data credits for VC0, used for 4186215976Sjmallett all receive queue buffer configurations. 4187215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 4188215976Sjmallett However, the application must not change this field. */ 4189215976Sjmallett#else 4190215976Sjmallett uint32_t data_credits : 12; 4191215976Sjmallett uint32_t header_credits : 8; 4192215976Sjmallett uint32_t reserved_20_20 : 1; 4193215976Sjmallett uint32_t queue_mode : 3; 4194215976Sjmallett uint32_t reserved_24_31 : 8; 4195215976Sjmallett#endif 4196215976Sjmallett } s; 4197215976Sjmallett struct cvmx_pciercx_cfg468_s cn52xx; 4198215976Sjmallett struct cvmx_pciercx_cfg468_s cn52xxp1; 4199215976Sjmallett struct cvmx_pciercx_cfg468_s cn56xx; 4200215976Sjmallett struct cvmx_pciercx_cfg468_s cn56xxp1; 4201215976Sjmallett struct cvmx_pciercx_cfg468_s cn63xx; 4202215976Sjmallett struct cvmx_pciercx_cfg468_s cn63xxp1; 4203215976Sjmallett}; 4204215976Sjmalletttypedef union cvmx_pciercx_cfg468 cvmx_pciercx_cfg468_t; 4205215976Sjmallett 4206215976Sjmallett/** 4207215976Sjmallett * cvmx_pcierc#_cfg490 4208215976Sjmallett * 4209215976Sjmallett * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 1 config space 4210215976Sjmallett * (VC0 Posted Buffer Depth) 4211215976Sjmallett */ 4212215976Sjmallettunion cvmx_pciercx_cfg490 4213215976Sjmallett{ 4214215976Sjmallett uint32_t u32; 4215215976Sjmallett struct cvmx_pciercx_cfg490_s 4216215976Sjmallett { 4217215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4218215976Sjmallett uint32_t reserved_26_31 : 6; 4219215976Sjmallett uint32_t header_depth : 10; /**< VC0 Posted Header Queue Depth 4220215976Sjmallett Sets the number of entries in the Posted header queue for VC0 4221215976Sjmallett when using the segmented-buffer configuration, writable through 4222215976Sjmallett PEM(0..1)_CFG_WR. 4223215976Sjmallett However, the application must not change this field. */ 4224215976Sjmallett uint32_t reserved_14_15 : 2; 4225215976Sjmallett uint32_t data_depth : 14; /**< VC0 Posted Data Queue Depth 4226215976Sjmallett Sets the number of entries in the Posted data queue for VC0 4227215976Sjmallett when using the segmented-buffer configuration, writable 4228215976Sjmallett through PEM(0..1)_CFG_WR. 4229215976Sjmallett However, the application must not change this field. */ 4230215976Sjmallett#else 4231215976Sjmallett uint32_t data_depth : 14; 4232215976Sjmallett uint32_t reserved_14_15 : 2; 4233215976Sjmallett uint32_t header_depth : 10; 4234215976Sjmallett uint32_t reserved_26_31 : 6; 4235215976Sjmallett#endif 4236215976Sjmallett } s; 4237215976Sjmallett struct cvmx_pciercx_cfg490_s cn52xx; 4238215976Sjmallett struct cvmx_pciercx_cfg490_s cn52xxp1; 4239215976Sjmallett struct cvmx_pciercx_cfg490_s cn56xx; 4240215976Sjmallett struct cvmx_pciercx_cfg490_s cn56xxp1; 4241215976Sjmallett struct cvmx_pciercx_cfg490_s cn63xx; 4242215976Sjmallett struct cvmx_pciercx_cfg490_s cn63xxp1; 4243215976Sjmallett}; 4244215976Sjmalletttypedef union cvmx_pciercx_cfg490 cvmx_pciercx_cfg490_t; 4245215976Sjmallett 4246215976Sjmallett/** 4247215976Sjmallett * cvmx_pcierc#_cfg491 4248215976Sjmallett * 4249215976Sjmallett * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 1 config space 4250215976Sjmallett * (VC0 Non-Posted Buffer Depth) 4251215976Sjmallett */ 4252215976Sjmallettunion cvmx_pciercx_cfg491 4253215976Sjmallett{ 4254215976Sjmallett uint32_t u32; 4255215976Sjmallett struct cvmx_pciercx_cfg491_s 4256215976Sjmallett { 4257215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4258215976Sjmallett uint32_t reserved_26_31 : 6; 4259215976Sjmallett uint32_t header_depth : 10; /**< VC0 Non-Posted Header Queue Depth 4260215976Sjmallett Sets the number of entries in the Non-Posted header queue for 4261215976Sjmallett VC0 when using the segmented-buffer configuration, writable 4262215976Sjmallett through PEM(0..1)_CFG_WR. 4263215976Sjmallett However, the application must not change this field. */ 4264215976Sjmallett uint32_t reserved_14_15 : 2; 4265215976Sjmallett uint32_t data_depth : 14; /**< VC0 Non-Posted Data Queue Depth 4266215976Sjmallett Sets the number of entries in the Non-Posted data queue for VC0 4267215976Sjmallett when using the segmented-buffer configuration, writable 4268215976Sjmallett through PEM(0..1)_CFG_WR. 4269215976Sjmallett However, the application must not change this field. */ 4270215976Sjmallett#else 4271215976Sjmallett uint32_t data_depth : 14; 4272215976Sjmallett uint32_t reserved_14_15 : 2; 4273215976Sjmallett uint32_t header_depth : 10; 4274215976Sjmallett uint32_t reserved_26_31 : 6; 4275215976Sjmallett#endif 4276215976Sjmallett } s; 4277215976Sjmallett struct cvmx_pciercx_cfg491_s cn52xx; 4278215976Sjmallett struct cvmx_pciercx_cfg491_s cn52xxp1; 4279215976Sjmallett struct cvmx_pciercx_cfg491_s cn56xx; 4280215976Sjmallett struct cvmx_pciercx_cfg491_s cn56xxp1; 4281215976Sjmallett struct cvmx_pciercx_cfg491_s cn63xx; 4282215976Sjmallett struct cvmx_pciercx_cfg491_s cn63xxp1; 4283215976Sjmallett}; 4284215976Sjmalletttypedef union cvmx_pciercx_cfg491 cvmx_pciercx_cfg491_t; 4285215976Sjmallett 4286215976Sjmallett/** 4287215976Sjmallett * cvmx_pcierc#_cfg492 4288215976Sjmallett * 4289215976Sjmallett * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 1 config space 4290215976Sjmallett * (VC0 Completion Buffer Depth) 4291215976Sjmallett */ 4292215976Sjmallettunion cvmx_pciercx_cfg492 4293215976Sjmallett{ 4294215976Sjmallett uint32_t u32; 4295215976Sjmallett struct cvmx_pciercx_cfg492_s 4296215976Sjmallett { 4297215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4298215976Sjmallett uint32_t reserved_26_31 : 6; 4299215976Sjmallett uint32_t header_depth : 10; /**< VC0 Completion Header Queue Depth 4300215976Sjmallett Sets the number of entries in the Completion header queue for 4301215976Sjmallett VC0 when using the segmented-buffer configuration, writable 4302215976Sjmallett through PEM(0..1)_CFG_WR. 4303215976Sjmallett However, the application must not change this field. */ 4304215976Sjmallett uint32_t reserved_14_15 : 2; 4305215976Sjmallett uint32_t data_depth : 14; /**< VC0 Completion Data Queue Depth 4306215976Sjmallett Sets the number of entries in the Completion data queue for VC0 4307215976Sjmallett when using the segmented-buffer configuration, writable 4308215976Sjmallett through PEM(0..1)_CFG_WR. 4309215976Sjmallett However, the application must not change this field. */ 4310215976Sjmallett#else 4311215976Sjmallett uint32_t data_depth : 14; 4312215976Sjmallett uint32_t reserved_14_15 : 2; 4313215976Sjmallett uint32_t header_depth : 10; 4314215976Sjmallett uint32_t reserved_26_31 : 6; 4315215976Sjmallett#endif 4316215976Sjmallett } s; 4317215976Sjmallett struct cvmx_pciercx_cfg492_s cn52xx; 4318215976Sjmallett struct cvmx_pciercx_cfg492_s cn52xxp1; 4319215976Sjmallett struct cvmx_pciercx_cfg492_s cn56xx; 4320215976Sjmallett struct cvmx_pciercx_cfg492_s cn56xxp1; 4321215976Sjmallett struct cvmx_pciercx_cfg492_s cn63xx; 4322215976Sjmallett struct cvmx_pciercx_cfg492_s cn63xxp1; 4323215976Sjmallett}; 4324215976Sjmalletttypedef union cvmx_pciercx_cfg492 cvmx_pciercx_cfg492_t; 4325215976Sjmallett 4326215976Sjmallett/** 4327215976Sjmallett * cvmx_pcierc#_cfg515 4328215976Sjmallett * 4329215976Sjmallett * PCIE_CFG515 = Five hundred sixteenth 32-bits of PCIE type 1 config space 4330215976Sjmallett * (Port Logic Register (Gen2)) 4331215976Sjmallett */ 4332215976Sjmallettunion cvmx_pciercx_cfg515 4333215976Sjmallett{ 4334215976Sjmallett uint32_t u32; 4335215976Sjmallett struct cvmx_pciercx_cfg515_s 4336215976Sjmallett { 4337215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4338215976Sjmallett uint32_t reserved_21_31 : 11; 4339215976Sjmallett uint32_t s_d_e : 1; /**< SEL_DE_EMPHASIS 4340215976Sjmallett Used to set the de-emphasis level for upstream ports. */ 4341215976Sjmallett uint32_t ctcrb : 1; /**< Config Tx Compliance Receive Bit 4342215976Sjmallett When set to 1, signals LTSSM to transmit TS ordered sets 4343215976Sjmallett with the compliance receive bit assert (equal to 1). */ 4344215976Sjmallett uint32_t cpyts : 1; /**< Config PHY Tx Swing 4345215976Sjmallett Indicates the voltage level the PHY should drive. When set to 4346215976Sjmallett 1, indicates Full Swing. When set to 0, indicates Low Swing */ 4347215976Sjmallett uint32_t dsc : 1; /**< Directed Speed Change 4348215976Sjmallett Indicates to the LTSSM whether or not to initiate a speed 4349215976Sjmallett change. */ 4350215976Sjmallett uint32_t le : 9; /**< Lane Enable 4351215976Sjmallett Indicates the number of lanes to check for exit from electrical 4352215976Sjmallett idle in Polling.Active and Polling.Compliance. 1 = x1, 2 = x2, 4353215976Sjmallett etc. Used to limit the maximum link width to ignore broken 4354215976Sjmallett lanes that detect a receiver, but will not exit electrical 4355215976Sjmallett idle and 4356215976Sjmallett would otherwise prevent a valid link from being configured. */ 4357215976Sjmallett uint32_t n_fts : 8; /**< N_FTS 4358215976Sjmallett Sets the Number of Fast Training Sequences (N_FTS) that 4359215976Sjmallett the core advertises as its N_FTS during GEN2 Link training. 4360215976Sjmallett This value is used to inform the Link partner about the PHYs 4361215976Sjmallett ability to recover synchronization after a low power state. 4362215976Sjmallett Note: Do not set N_FTS to zero; doing so can cause the 4363215976Sjmallett LTSSM to go into the recovery state when exiting from 4364215976Sjmallett L0s. */ 4365215976Sjmallett#else 4366215976Sjmallett uint32_t n_fts : 8; 4367215976Sjmallett uint32_t le : 9; 4368215976Sjmallett uint32_t dsc : 1; 4369215976Sjmallett uint32_t cpyts : 1; 4370215976Sjmallett uint32_t ctcrb : 1; 4371215976Sjmallett uint32_t s_d_e : 1; 4372215976Sjmallett uint32_t reserved_21_31 : 11; 4373215976Sjmallett#endif 4374215976Sjmallett } s; 4375215976Sjmallett struct cvmx_pciercx_cfg515_s cn63xx; 4376215976Sjmallett struct cvmx_pciercx_cfg515_s cn63xxp1; 4377215976Sjmallett}; 4378215976Sjmalletttypedef union cvmx_pciercx_cfg515 cvmx_pciercx_cfg515_t; 4379215976Sjmallett 4380215976Sjmallett/** 4381215976Sjmallett * cvmx_pcierc#_cfg516 4382215976Sjmallett * 4383215976Sjmallett * PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 1 config space 4384215976Sjmallett * (PHY Status Register) 4385215976Sjmallett */ 4386215976Sjmallettunion cvmx_pciercx_cfg516 4387215976Sjmallett{ 4388215976Sjmallett uint32_t u32; 4389215976Sjmallett struct cvmx_pciercx_cfg516_s 4390215976Sjmallett { 4391215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4392215976Sjmallett uint32_t phy_stat : 32; /**< PHY Status */ 4393215976Sjmallett#else 4394215976Sjmallett uint32_t phy_stat : 32; 4395215976Sjmallett#endif 4396215976Sjmallett } s; 4397215976Sjmallett struct cvmx_pciercx_cfg516_s cn52xx; 4398215976Sjmallett struct cvmx_pciercx_cfg516_s cn52xxp1; 4399215976Sjmallett struct cvmx_pciercx_cfg516_s cn56xx; 4400215976Sjmallett struct cvmx_pciercx_cfg516_s cn56xxp1; 4401215976Sjmallett struct cvmx_pciercx_cfg516_s cn63xx; 4402215976Sjmallett struct cvmx_pciercx_cfg516_s cn63xxp1; 4403215976Sjmallett}; 4404215976Sjmalletttypedef union cvmx_pciercx_cfg516 cvmx_pciercx_cfg516_t; 4405215976Sjmallett 4406215976Sjmallett/** 4407215976Sjmallett * cvmx_pcierc#_cfg517 4408215976Sjmallett * 4409215976Sjmallett * PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 1 config space 4410215976Sjmallett * (PHY Control Register) 4411215976Sjmallett */ 4412215976Sjmallettunion cvmx_pciercx_cfg517 4413215976Sjmallett{ 4414215976Sjmallett uint32_t u32; 4415215976Sjmallett struct cvmx_pciercx_cfg517_s 4416215976Sjmallett { 4417215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4418215976Sjmallett uint32_t phy_ctrl : 32; /**< PHY Control */ 4419215976Sjmallett#else 4420215976Sjmallett uint32_t phy_ctrl : 32; 4421215976Sjmallett#endif 4422215976Sjmallett } s; 4423215976Sjmallett struct cvmx_pciercx_cfg517_s cn52xx; 4424215976Sjmallett struct cvmx_pciercx_cfg517_s cn52xxp1; 4425215976Sjmallett struct cvmx_pciercx_cfg517_s cn56xx; 4426215976Sjmallett struct cvmx_pciercx_cfg517_s cn56xxp1; 4427215976Sjmallett struct cvmx_pciercx_cfg517_s cn63xx; 4428215976Sjmallett struct cvmx_pciercx_cfg517_s cn63xxp1; 4429215976Sjmallett}; 4430215976Sjmalletttypedef union cvmx_pciercx_cfg517 cvmx_pciercx_cfg517_t; 4431215976Sjmallett 4432215976Sjmallett#endif 4433