1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-pciercx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon pciercx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_PCIERCX_TYPEDEFS_H__ 53#define __CVMX_PCIERCX_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_PCIERCX_CFG000(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 60 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 61 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 62 cvmx_warn("CVMX_PCIERCX_CFG000(%lu) is invalid on this chip\n", block_id); 63 return 0x0000000000000000ull; 64} 65#else 66#define CVMX_PCIERCX_CFG000(block_id) (0x0000000000000000ull) 67#endif 68#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69static inline uint64_t CVMX_PCIERCX_CFG001(unsigned long block_id) 70{ 71 if (!( 72 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 73 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 74 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 75 cvmx_warn("CVMX_PCIERCX_CFG001(%lu) is invalid on this chip\n", block_id); 76 return 0x0000000000000004ull; 77} 78#else 79#define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull) 80#endif 81#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82static inline uint64_t CVMX_PCIERCX_CFG002(unsigned long block_id) 83{ 84 if (!( 85 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 86 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 87 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 88 cvmx_warn("CVMX_PCIERCX_CFG002(%lu) is invalid on this chip\n", block_id); 89 return 0x0000000000000008ull; 90} 91#else 92#define CVMX_PCIERCX_CFG002(block_id) (0x0000000000000008ull) 93#endif 94#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 95static inline uint64_t CVMX_PCIERCX_CFG003(unsigned long block_id) 96{ 97 if (!( 98 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 99 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 100 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 101 cvmx_warn("CVMX_PCIERCX_CFG003(%lu) is invalid on this chip\n", block_id); 102 return 0x000000000000000Cull; 103} 104#else 105#define CVMX_PCIERCX_CFG003(block_id) (0x000000000000000Cull) 106#endif 107#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 108static inline uint64_t CVMX_PCIERCX_CFG004(unsigned long block_id) 109{ 110 if (!( 111 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 112 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 113 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 114 cvmx_warn("CVMX_PCIERCX_CFG004(%lu) is invalid on this chip\n", block_id); 115 return 0x0000000000000010ull; 116} 117#else 118#define CVMX_PCIERCX_CFG004(block_id) (0x0000000000000010ull) 119#endif 120#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 121static inline uint64_t CVMX_PCIERCX_CFG005(unsigned long block_id) 122{ 123 if (!( 124 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 125 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 126 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 127 cvmx_warn("CVMX_PCIERCX_CFG005(%lu) is invalid on this chip\n", block_id); 128 return 0x0000000000000014ull; 129} 130#else 131#define CVMX_PCIERCX_CFG005(block_id) (0x0000000000000014ull) 132#endif 133#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 134static inline uint64_t CVMX_PCIERCX_CFG006(unsigned long block_id) 135{ 136 if (!( 137 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 138 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 139 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 140 cvmx_warn("CVMX_PCIERCX_CFG006(%lu) is invalid on this chip\n", block_id); 141 return 0x0000000000000018ull; 142} 143#else 144#define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull) 145#endif 146#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 147static inline uint64_t CVMX_PCIERCX_CFG007(unsigned long block_id) 148{ 149 if (!( 150 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 151 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 152 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 153 cvmx_warn("CVMX_PCIERCX_CFG007(%lu) is invalid on this chip\n", block_id); 154 return 0x000000000000001Cull; 155} 156#else 157#define CVMX_PCIERCX_CFG007(block_id) (0x000000000000001Cull) 158#endif 159#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 160static inline uint64_t CVMX_PCIERCX_CFG008(unsigned long block_id) 161{ 162 if (!( 163 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 164 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 165 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 166 cvmx_warn("CVMX_PCIERCX_CFG008(%lu) is invalid on this chip\n", block_id); 167 return 0x0000000000000020ull; 168} 169#else 170#define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull) 171#endif 172#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 173static inline uint64_t CVMX_PCIERCX_CFG009(unsigned long block_id) 174{ 175 if (!( 176 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 177 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 178 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 179 cvmx_warn("CVMX_PCIERCX_CFG009(%lu) is invalid on this chip\n", block_id); 180 return 0x0000000000000024ull; 181} 182#else 183#define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull) 184#endif 185#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 186static inline uint64_t CVMX_PCIERCX_CFG010(unsigned long block_id) 187{ 188 if (!( 189 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 190 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 191 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 192 cvmx_warn("CVMX_PCIERCX_CFG010(%lu) is invalid on this chip\n", block_id); 193 return 0x0000000000000028ull; 194} 195#else 196#define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199static inline uint64_t CVMX_PCIERCX_CFG011(unsigned long block_id) 200{ 201 if (!( 202 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 203 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 204 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 205 cvmx_warn("CVMX_PCIERCX_CFG011(%lu) is invalid on this chip\n", block_id); 206 return 0x000000000000002Cull; 207} 208#else 209#define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull) 210#endif 211#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212static inline uint64_t CVMX_PCIERCX_CFG012(unsigned long block_id) 213{ 214 if (!( 215 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 216 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 217 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 218 cvmx_warn("CVMX_PCIERCX_CFG012(%lu) is invalid on this chip\n", block_id); 219 return 0x0000000000000030ull; 220} 221#else 222#define CVMX_PCIERCX_CFG012(block_id) (0x0000000000000030ull) 223#endif 224#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 225static inline uint64_t CVMX_PCIERCX_CFG013(unsigned long block_id) 226{ 227 if (!( 228 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 229 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 230 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 231 cvmx_warn("CVMX_PCIERCX_CFG013(%lu) is invalid on this chip\n", block_id); 232 return 0x0000000000000034ull; 233} 234#else 235#define CVMX_PCIERCX_CFG013(block_id) (0x0000000000000034ull) 236#endif 237#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 238static inline uint64_t CVMX_PCIERCX_CFG014(unsigned long block_id) 239{ 240 if (!( 241 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 242 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 243 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 244 cvmx_warn("CVMX_PCIERCX_CFG014(%lu) is invalid on this chip\n", block_id); 245 return 0x0000000000000038ull; 246} 247#else 248#define CVMX_PCIERCX_CFG014(block_id) (0x0000000000000038ull) 249#endif 250#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251static inline uint64_t CVMX_PCIERCX_CFG015(unsigned long block_id) 252{ 253 if (!( 254 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 255 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 256 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 257 cvmx_warn("CVMX_PCIERCX_CFG015(%lu) is invalid on this chip\n", block_id); 258 return 0x000000000000003Cull; 259} 260#else 261#define CVMX_PCIERCX_CFG015(block_id) (0x000000000000003Cull) 262#endif 263#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 264static inline uint64_t CVMX_PCIERCX_CFG016(unsigned long block_id) 265{ 266 if (!( 267 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 268 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 269 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 270 cvmx_warn("CVMX_PCIERCX_CFG016(%lu) is invalid on this chip\n", block_id); 271 return 0x0000000000000040ull; 272} 273#else 274#define CVMX_PCIERCX_CFG016(block_id) (0x0000000000000040ull) 275#endif 276#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 277static inline uint64_t CVMX_PCIERCX_CFG017(unsigned long block_id) 278{ 279 if (!( 280 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 281 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 282 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 283 cvmx_warn("CVMX_PCIERCX_CFG017(%lu) is invalid on this chip\n", block_id); 284 return 0x0000000000000044ull; 285} 286#else 287#define CVMX_PCIERCX_CFG017(block_id) (0x0000000000000044ull) 288#endif 289#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 290static inline uint64_t CVMX_PCIERCX_CFG020(unsigned long block_id) 291{ 292 if (!( 293 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 294 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 295 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 296 cvmx_warn("CVMX_PCIERCX_CFG020(%lu) is invalid on this chip\n", block_id); 297 return 0x0000000000000050ull; 298} 299#else 300#define CVMX_PCIERCX_CFG020(block_id) (0x0000000000000050ull) 301#endif 302#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 303static inline uint64_t CVMX_PCIERCX_CFG021(unsigned long block_id) 304{ 305 if (!( 306 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 307 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 308 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 309 cvmx_warn("CVMX_PCIERCX_CFG021(%lu) is invalid on this chip\n", block_id); 310 return 0x0000000000000054ull; 311} 312#else 313#define CVMX_PCIERCX_CFG021(block_id) (0x0000000000000054ull) 314#endif 315#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 316static inline uint64_t CVMX_PCIERCX_CFG022(unsigned long block_id) 317{ 318 if (!( 319 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 320 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 321 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 322 cvmx_warn("CVMX_PCIERCX_CFG022(%lu) is invalid on this chip\n", block_id); 323 return 0x0000000000000058ull; 324} 325#else 326#define CVMX_PCIERCX_CFG022(block_id) (0x0000000000000058ull) 327#endif 328#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 329static inline uint64_t CVMX_PCIERCX_CFG023(unsigned long block_id) 330{ 331 if (!( 332 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 333 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 334 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 335 cvmx_warn("CVMX_PCIERCX_CFG023(%lu) is invalid on this chip\n", block_id); 336 return 0x000000000000005Cull; 337} 338#else 339#define CVMX_PCIERCX_CFG023(block_id) (0x000000000000005Cull) 340#endif 341#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342static inline uint64_t CVMX_PCIERCX_CFG028(unsigned long block_id) 343{ 344 if (!( 345 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 346 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 347 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 348 cvmx_warn("CVMX_PCIERCX_CFG028(%lu) is invalid on this chip\n", block_id); 349 return 0x0000000000000070ull; 350} 351#else 352#define CVMX_PCIERCX_CFG028(block_id) (0x0000000000000070ull) 353#endif 354#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 355static inline uint64_t CVMX_PCIERCX_CFG029(unsigned long block_id) 356{ 357 if (!( 358 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 359 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 360 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 361 cvmx_warn("CVMX_PCIERCX_CFG029(%lu) is invalid on this chip\n", block_id); 362 return 0x0000000000000074ull; 363} 364#else 365#define CVMX_PCIERCX_CFG029(block_id) (0x0000000000000074ull) 366#endif 367#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 368static inline uint64_t CVMX_PCIERCX_CFG030(unsigned long block_id) 369{ 370 if (!( 371 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 372 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 373 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 374 cvmx_warn("CVMX_PCIERCX_CFG030(%lu) is invalid on this chip\n", block_id); 375 return 0x0000000000000078ull; 376} 377#else 378#define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull) 379#endif 380#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 381static inline uint64_t CVMX_PCIERCX_CFG031(unsigned long block_id) 382{ 383 if (!( 384 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 385 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 386 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 387 cvmx_warn("CVMX_PCIERCX_CFG031(%lu) is invalid on this chip\n", block_id); 388 return 0x000000000000007Cull; 389} 390#else 391#define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull) 392#endif 393#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 394static inline uint64_t CVMX_PCIERCX_CFG032(unsigned long block_id) 395{ 396 if (!( 397 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 398 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 399 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 400 cvmx_warn("CVMX_PCIERCX_CFG032(%lu) is invalid on this chip\n", block_id); 401 return 0x0000000000000080ull; 402} 403#else 404#define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull) 405#endif 406#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 407static inline uint64_t CVMX_PCIERCX_CFG033(unsigned long block_id) 408{ 409 if (!( 410 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 411 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 412 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 413 cvmx_warn("CVMX_PCIERCX_CFG033(%lu) is invalid on this chip\n", block_id); 414 return 0x0000000000000084ull; 415} 416#else 417#define CVMX_PCIERCX_CFG033(block_id) (0x0000000000000084ull) 418#endif 419#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 420static inline uint64_t CVMX_PCIERCX_CFG034(unsigned long block_id) 421{ 422 if (!( 423 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 424 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 425 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 426 cvmx_warn("CVMX_PCIERCX_CFG034(%lu) is invalid on this chip\n", block_id); 427 return 0x0000000000000088ull; 428} 429#else 430#define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull) 431#endif 432#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 433static inline uint64_t CVMX_PCIERCX_CFG035(unsigned long block_id) 434{ 435 if (!( 436 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 437 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 438 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 439 cvmx_warn("CVMX_PCIERCX_CFG035(%lu) is invalid on this chip\n", block_id); 440 return 0x000000000000008Cull; 441} 442#else 443#define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull) 444#endif 445#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 446static inline uint64_t CVMX_PCIERCX_CFG036(unsigned long block_id) 447{ 448 if (!( 449 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 450 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 451 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 452 cvmx_warn("CVMX_PCIERCX_CFG036(%lu) is invalid on this chip\n", block_id); 453 return 0x0000000000000090ull; 454} 455#else 456#define CVMX_PCIERCX_CFG036(block_id) (0x0000000000000090ull) 457#endif 458#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 459static inline uint64_t CVMX_PCIERCX_CFG037(unsigned long block_id) 460{ 461 if (!( 462 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 463 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 464 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 465 cvmx_warn("CVMX_PCIERCX_CFG037(%lu) is invalid on this chip\n", block_id); 466 return 0x0000000000000094ull; 467} 468#else 469#define CVMX_PCIERCX_CFG037(block_id) (0x0000000000000094ull) 470#endif 471#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 472static inline uint64_t CVMX_PCIERCX_CFG038(unsigned long block_id) 473{ 474 if (!( 475 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 476 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 477 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 478 cvmx_warn("CVMX_PCIERCX_CFG038(%lu) is invalid on this chip\n", block_id); 479 return 0x0000000000000098ull; 480} 481#else 482#define CVMX_PCIERCX_CFG038(block_id) (0x0000000000000098ull) 483#endif 484#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485static inline uint64_t CVMX_PCIERCX_CFG039(unsigned long block_id) 486{ 487 if (!( 488 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 489 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 490 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 491 cvmx_warn("CVMX_PCIERCX_CFG039(%lu) is invalid on this chip\n", block_id); 492 return 0x000000000000009Cull; 493} 494#else 495#define CVMX_PCIERCX_CFG039(block_id) (0x000000000000009Cull) 496#endif 497#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 498static inline uint64_t CVMX_PCIERCX_CFG040(unsigned long block_id) 499{ 500 if (!( 501 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 502 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 503 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 504 cvmx_warn("CVMX_PCIERCX_CFG040(%lu) is invalid on this chip\n", block_id); 505 return 0x00000000000000A0ull; 506} 507#else 508#define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull) 509#endif 510#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 511static inline uint64_t CVMX_PCIERCX_CFG041(unsigned long block_id) 512{ 513 if (!( 514 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 515 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 516 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 517 cvmx_warn("CVMX_PCIERCX_CFG041(%lu) is invalid on this chip\n", block_id); 518 return 0x00000000000000A4ull; 519} 520#else 521#define CVMX_PCIERCX_CFG041(block_id) (0x00000000000000A4ull) 522#endif 523#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 524static inline uint64_t CVMX_PCIERCX_CFG042(unsigned long block_id) 525{ 526 if (!( 527 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 528 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 529 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 530 cvmx_warn("CVMX_PCIERCX_CFG042(%lu) is invalid on this chip\n", block_id); 531 return 0x00000000000000A8ull; 532} 533#else 534#define CVMX_PCIERCX_CFG042(block_id) (0x00000000000000A8ull) 535#endif 536#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 537static inline uint64_t CVMX_PCIERCX_CFG064(unsigned long block_id) 538{ 539 if (!( 540 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 541 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 542 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 543 cvmx_warn("CVMX_PCIERCX_CFG064(%lu) is invalid on this chip\n", block_id); 544 return 0x0000000000000100ull; 545} 546#else 547#define CVMX_PCIERCX_CFG064(block_id) (0x0000000000000100ull) 548#endif 549#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 550static inline uint64_t CVMX_PCIERCX_CFG065(unsigned long block_id) 551{ 552 if (!( 553 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 554 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 555 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 556 cvmx_warn("CVMX_PCIERCX_CFG065(%lu) is invalid on this chip\n", block_id); 557 return 0x0000000000000104ull; 558} 559#else 560#define CVMX_PCIERCX_CFG065(block_id) (0x0000000000000104ull) 561#endif 562#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 563static inline uint64_t CVMX_PCIERCX_CFG066(unsigned long block_id) 564{ 565 if (!( 566 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 567 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 568 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 569 cvmx_warn("CVMX_PCIERCX_CFG066(%lu) is invalid on this chip\n", block_id); 570 return 0x0000000000000108ull; 571} 572#else 573#define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull) 574#endif 575#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 576static inline uint64_t CVMX_PCIERCX_CFG067(unsigned long block_id) 577{ 578 if (!( 579 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 580 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 581 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 582 cvmx_warn("CVMX_PCIERCX_CFG067(%lu) is invalid on this chip\n", block_id); 583 return 0x000000000000010Cull; 584} 585#else 586#define CVMX_PCIERCX_CFG067(block_id) (0x000000000000010Cull) 587#endif 588#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 589static inline uint64_t CVMX_PCIERCX_CFG068(unsigned long block_id) 590{ 591 if (!( 592 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 593 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 594 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 595 cvmx_warn("CVMX_PCIERCX_CFG068(%lu) is invalid on this chip\n", block_id); 596 return 0x0000000000000110ull; 597} 598#else 599#define CVMX_PCIERCX_CFG068(block_id) (0x0000000000000110ull) 600#endif 601#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 602static inline uint64_t CVMX_PCIERCX_CFG069(unsigned long block_id) 603{ 604 if (!( 605 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 606 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 607 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 608 cvmx_warn("CVMX_PCIERCX_CFG069(%lu) is invalid on this chip\n", block_id); 609 return 0x0000000000000114ull; 610} 611#else 612#define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull) 613#endif 614#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 615static inline uint64_t CVMX_PCIERCX_CFG070(unsigned long block_id) 616{ 617 if (!( 618 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 619 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 620 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 621 cvmx_warn("CVMX_PCIERCX_CFG070(%lu) is invalid on this chip\n", block_id); 622 return 0x0000000000000118ull; 623} 624#else 625#define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull) 626#endif 627#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 628static inline uint64_t CVMX_PCIERCX_CFG071(unsigned long block_id) 629{ 630 if (!( 631 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 632 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 633 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 634 cvmx_warn("CVMX_PCIERCX_CFG071(%lu) is invalid on this chip\n", block_id); 635 return 0x000000000000011Cull; 636} 637#else 638#define CVMX_PCIERCX_CFG071(block_id) (0x000000000000011Cull) 639#endif 640#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 641static inline uint64_t CVMX_PCIERCX_CFG072(unsigned long block_id) 642{ 643 if (!( 644 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 645 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 646 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 647 cvmx_warn("CVMX_PCIERCX_CFG072(%lu) is invalid on this chip\n", block_id); 648 return 0x0000000000000120ull; 649} 650#else 651#define CVMX_PCIERCX_CFG072(block_id) (0x0000000000000120ull) 652#endif 653#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 654static inline uint64_t CVMX_PCIERCX_CFG073(unsigned long block_id) 655{ 656 if (!( 657 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 658 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 659 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 660 cvmx_warn("CVMX_PCIERCX_CFG073(%lu) is invalid on this chip\n", block_id); 661 return 0x0000000000000124ull; 662} 663#else 664#define CVMX_PCIERCX_CFG073(block_id) (0x0000000000000124ull) 665#endif 666#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 667static inline uint64_t CVMX_PCIERCX_CFG074(unsigned long block_id) 668{ 669 if (!( 670 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 671 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 672 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 673 cvmx_warn("CVMX_PCIERCX_CFG074(%lu) is invalid on this chip\n", block_id); 674 return 0x0000000000000128ull; 675} 676#else 677#define CVMX_PCIERCX_CFG074(block_id) (0x0000000000000128ull) 678#endif 679#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 680static inline uint64_t CVMX_PCIERCX_CFG075(unsigned long block_id) 681{ 682 if (!( 683 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 684 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 685 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 686 cvmx_warn("CVMX_PCIERCX_CFG075(%lu) is invalid on this chip\n", block_id); 687 return 0x000000000000012Cull; 688} 689#else 690#define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull) 691#endif 692#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 693static inline uint64_t CVMX_PCIERCX_CFG076(unsigned long block_id) 694{ 695 if (!( 696 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 697 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 698 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 699 cvmx_warn("CVMX_PCIERCX_CFG076(%lu) is invalid on this chip\n", block_id); 700 return 0x0000000000000130ull; 701} 702#else 703#define CVMX_PCIERCX_CFG076(block_id) (0x0000000000000130ull) 704#endif 705#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 706static inline uint64_t CVMX_PCIERCX_CFG077(unsigned long block_id) 707{ 708 if (!( 709 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 710 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 711 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 712 cvmx_warn("CVMX_PCIERCX_CFG077(%lu) is invalid on this chip\n", block_id); 713 return 0x0000000000000134ull; 714} 715#else 716#define CVMX_PCIERCX_CFG077(block_id) (0x0000000000000134ull) 717#endif 718#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 719static inline uint64_t CVMX_PCIERCX_CFG448(unsigned long block_id) 720{ 721 if (!( 722 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 723 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 724 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 725 cvmx_warn("CVMX_PCIERCX_CFG448(%lu) is invalid on this chip\n", block_id); 726 return 0x0000000000000700ull; 727} 728#else 729#define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull) 730#endif 731#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 732static inline uint64_t CVMX_PCIERCX_CFG449(unsigned long block_id) 733{ 734 if (!( 735 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 736 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 737 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 738 cvmx_warn("CVMX_PCIERCX_CFG449(%lu) is invalid on this chip\n", block_id); 739 return 0x0000000000000704ull; 740} 741#else 742#define CVMX_PCIERCX_CFG449(block_id) (0x0000000000000704ull) 743#endif 744#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 745static inline uint64_t CVMX_PCIERCX_CFG450(unsigned long block_id) 746{ 747 if (!( 748 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 749 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 750 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 751 cvmx_warn("CVMX_PCIERCX_CFG450(%lu) is invalid on this chip\n", block_id); 752 return 0x0000000000000708ull; 753} 754#else 755#define CVMX_PCIERCX_CFG450(block_id) (0x0000000000000708ull) 756#endif 757#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 758static inline uint64_t CVMX_PCIERCX_CFG451(unsigned long block_id) 759{ 760 if (!( 761 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 762 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 763 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 764 cvmx_warn("CVMX_PCIERCX_CFG451(%lu) is invalid on this chip\n", block_id); 765 return 0x000000000000070Cull; 766} 767#else 768#define CVMX_PCIERCX_CFG451(block_id) (0x000000000000070Cull) 769#endif 770#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 771static inline uint64_t CVMX_PCIERCX_CFG452(unsigned long block_id) 772{ 773 if (!( 774 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 775 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 776 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 777 cvmx_warn("CVMX_PCIERCX_CFG452(%lu) is invalid on this chip\n", block_id); 778 return 0x0000000000000710ull; 779} 780#else 781#define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull) 782#endif 783#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 784static inline uint64_t CVMX_PCIERCX_CFG453(unsigned long block_id) 785{ 786 if (!( 787 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 788 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 789 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 790 cvmx_warn("CVMX_PCIERCX_CFG453(%lu) is invalid on this chip\n", block_id); 791 return 0x0000000000000714ull; 792} 793#else 794#define CVMX_PCIERCX_CFG453(block_id) (0x0000000000000714ull) 795#endif 796#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 797static inline uint64_t CVMX_PCIERCX_CFG454(unsigned long block_id) 798{ 799 if (!( 800 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 801 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 802 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 803 cvmx_warn("CVMX_PCIERCX_CFG454(%lu) is invalid on this chip\n", block_id); 804 return 0x0000000000000718ull; 805} 806#else 807#define CVMX_PCIERCX_CFG454(block_id) (0x0000000000000718ull) 808#endif 809#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 810static inline uint64_t CVMX_PCIERCX_CFG455(unsigned long block_id) 811{ 812 if (!( 813 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 814 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 815 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 816 cvmx_warn("CVMX_PCIERCX_CFG455(%lu) is invalid on this chip\n", block_id); 817 return 0x000000000000071Cull; 818} 819#else 820#define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull) 821#endif 822#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 823static inline uint64_t CVMX_PCIERCX_CFG456(unsigned long block_id) 824{ 825 if (!( 826 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 827 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 828 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 829 cvmx_warn("CVMX_PCIERCX_CFG456(%lu) is invalid on this chip\n", block_id); 830 return 0x0000000000000720ull; 831} 832#else 833#define CVMX_PCIERCX_CFG456(block_id) (0x0000000000000720ull) 834#endif 835#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 836static inline uint64_t CVMX_PCIERCX_CFG458(unsigned long block_id) 837{ 838 if (!( 839 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 840 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 841 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 842 cvmx_warn("CVMX_PCIERCX_CFG458(%lu) is invalid on this chip\n", block_id); 843 return 0x0000000000000728ull; 844} 845#else 846#define CVMX_PCIERCX_CFG458(block_id) (0x0000000000000728ull) 847#endif 848#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 849static inline uint64_t CVMX_PCIERCX_CFG459(unsigned long block_id) 850{ 851 if (!( 852 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 853 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 854 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 855 cvmx_warn("CVMX_PCIERCX_CFG459(%lu) is invalid on this chip\n", block_id); 856 return 0x000000000000072Cull; 857} 858#else 859#define CVMX_PCIERCX_CFG459(block_id) (0x000000000000072Cull) 860#endif 861#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 862static inline uint64_t CVMX_PCIERCX_CFG460(unsigned long block_id) 863{ 864 if (!( 865 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 866 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 867 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 868 cvmx_warn("CVMX_PCIERCX_CFG460(%lu) is invalid on this chip\n", block_id); 869 return 0x0000000000000730ull; 870} 871#else 872#define CVMX_PCIERCX_CFG460(block_id) (0x0000000000000730ull) 873#endif 874#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 875static inline uint64_t CVMX_PCIERCX_CFG461(unsigned long block_id) 876{ 877 if (!( 878 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 879 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 880 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 881 cvmx_warn("CVMX_PCIERCX_CFG461(%lu) is invalid on this chip\n", block_id); 882 return 0x0000000000000734ull; 883} 884#else 885#define CVMX_PCIERCX_CFG461(block_id) (0x0000000000000734ull) 886#endif 887#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 888static inline uint64_t CVMX_PCIERCX_CFG462(unsigned long block_id) 889{ 890 if (!( 891 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 892 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 893 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 894 cvmx_warn("CVMX_PCIERCX_CFG462(%lu) is invalid on this chip\n", block_id); 895 return 0x0000000000000738ull; 896} 897#else 898#define CVMX_PCIERCX_CFG462(block_id) (0x0000000000000738ull) 899#endif 900#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 901static inline uint64_t CVMX_PCIERCX_CFG463(unsigned long block_id) 902{ 903 if (!( 904 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 905 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 906 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 907 cvmx_warn("CVMX_PCIERCX_CFG463(%lu) is invalid on this chip\n", block_id); 908 return 0x000000000000073Cull; 909} 910#else 911#define CVMX_PCIERCX_CFG463(block_id) (0x000000000000073Cull) 912#endif 913#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 914static inline uint64_t CVMX_PCIERCX_CFG464(unsigned long block_id) 915{ 916 if (!( 917 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 918 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 919 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 920 cvmx_warn("CVMX_PCIERCX_CFG464(%lu) is invalid on this chip\n", block_id); 921 return 0x0000000000000740ull; 922} 923#else 924#define CVMX_PCIERCX_CFG464(block_id) (0x0000000000000740ull) 925#endif 926#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 927static inline uint64_t CVMX_PCIERCX_CFG465(unsigned long block_id) 928{ 929 if (!( 930 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 931 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 932 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 933 cvmx_warn("CVMX_PCIERCX_CFG465(%lu) is invalid on this chip\n", block_id); 934 return 0x0000000000000744ull; 935} 936#else 937#define CVMX_PCIERCX_CFG465(block_id) (0x0000000000000744ull) 938#endif 939#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 940static inline uint64_t CVMX_PCIERCX_CFG466(unsigned long block_id) 941{ 942 if (!( 943 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 944 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 945 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 946 cvmx_warn("CVMX_PCIERCX_CFG466(%lu) is invalid on this chip\n", block_id); 947 return 0x0000000000000748ull; 948} 949#else 950#define CVMX_PCIERCX_CFG466(block_id) (0x0000000000000748ull) 951#endif 952#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 953static inline uint64_t CVMX_PCIERCX_CFG467(unsigned long block_id) 954{ 955 if (!( 956 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 957 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 958 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 959 cvmx_warn("CVMX_PCIERCX_CFG467(%lu) is invalid on this chip\n", block_id); 960 return 0x000000000000074Cull; 961} 962#else 963#define CVMX_PCIERCX_CFG467(block_id) (0x000000000000074Cull) 964#endif 965#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 966static inline uint64_t CVMX_PCIERCX_CFG468(unsigned long block_id) 967{ 968 if (!( 969 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 970 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 971 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 972 cvmx_warn("CVMX_PCIERCX_CFG468(%lu) is invalid on this chip\n", block_id); 973 return 0x0000000000000750ull; 974} 975#else 976#define CVMX_PCIERCX_CFG468(block_id) (0x0000000000000750ull) 977#endif 978#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 979static inline uint64_t CVMX_PCIERCX_CFG490(unsigned long block_id) 980{ 981 if (!( 982 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 983 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 984 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 985 cvmx_warn("CVMX_PCIERCX_CFG490(%lu) is invalid on this chip\n", block_id); 986 return 0x00000000000007A8ull; 987} 988#else 989#define CVMX_PCIERCX_CFG490(block_id) (0x00000000000007A8ull) 990#endif 991#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 992static inline uint64_t CVMX_PCIERCX_CFG491(unsigned long block_id) 993{ 994 if (!( 995 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 996 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 997 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 998 cvmx_warn("CVMX_PCIERCX_CFG491(%lu) is invalid on this chip\n", block_id); 999 return 0x00000000000007ACull; 1000} 1001#else 1002#define CVMX_PCIERCX_CFG491(block_id) (0x00000000000007ACull) 1003#endif 1004#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1005static inline uint64_t CVMX_PCIERCX_CFG492(unsigned long block_id) 1006{ 1007 if (!( 1008 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1009 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1010 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 1011 cvmx_warn("CVMX_PCIERCX_CFG492(%lu) is invalid on this chip\n", block_id); 1012 return 0x00000000000007B0ull; 1013} 1014#else 1015#define CVMX_PCIERCX_CFG492(block_id) (0x00000000000007B0ull) 1016#endif 1017#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1018static inline uint64_t CVMX_PCIERCX_CFG515(unsigned long block_id) 1019{ 1020 if (!( 1021 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 1022 cvmx_warn("CVMX_PCIERCX_CFG515(%lu) is invalid on this chip\n", block_id); 1023 return 0x000000000000080Cull; 1024} 1025#else 1026#define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull) 1027#endif 1028#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1029static inline uint64_t CVMX_PCIERCX_CFG516(unsigned long block_id) 1030{ 1031 if (!( 1032 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1033 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1034 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 1035 cvmx_warn("CVMX_PCIERCX_CFG516(%lu) is invalid on this chip\n", block_id); 1036 return 0x0000000000000810ull; 1037} 1038#else 1039#define CVMX_PCIERCX_CFG516(block_id) (0x0000000000000810ull) 1040#endif 1041#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1042static inline uint64_t CVMX_PCIERCX_CFG517(unsigned long block_id) 1043{ 1044 if (!( 1045 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1046 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1047 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 1048 cvmx_warn("CVMX_PCIERCX_CFG517(%lu) is invalid on this chip\n", block_id); 1049 return 0x0000000000000814ull; 1050} 1051#else 1052#define CVMX_PCIERCX_CFG517(block_id) (0x0000000000000814ull) 1053#endif 1054 1055/** 1056 * cvmx_pcierc#_cfg000 1057 * 1058 * PCIE_CFG000 = First 32-bits of PCIE type 1 config space (Device ID and Vendor ID Register) 1059 * 1060 */ 1061union cvmx_pciercx_cfg000 1062{ 1063 uint32_t u32; 1064 struct cvmx_pciercx_cfg000_s 1065 { 1066#if __BYTE_ORDER == __BIG_ENDIAN 1067 uint32_t devid : 16; /**< Device ID, writable through PEM(0..1)_CFG_WR 1068 However, the application must not change this field. */ 1069 uint32_t vendid : 16; /**< Vendor ID, writable through PEM(0..1)_CFG_WR 1070 However, the application must not change this field. */ 1071#else 1072 uint32_t vendid : 16; 1073 uint32_t devid : 16; 1074#endif 1075 } s; 1076 struct cvmx_pciercx_cfg000_s cn52xx; 1077 struct cvmx_pciercx_cfg000_s cn52xxp1; 1078 struct cvmx_pciercx_cfg000_s cn56xx; 1079 struct cvmx_pciercx_cfg000_s cn56xxp1; 1080 struct cvmx_pciercx_cfg000_s cn63xx; 1081 struct cvmx_pciercx_cfg000_s cn63xxp1; 1082}; 1083typedef union cvmx_pciercx_cfg000 cvmx_pciercx_cfg000_t; 1084 1085/** 1086 * cvmx_pcierc#_cfg001 1087 * 1088 * PCIE_CFG001 = Second 32-bits of PCIE type 1 config space (Command/Status Register) 1089 * 1090 */ 1091union cvmx_pciercx_cfg001 1092{ 1093 uint32_t u32; 1094 struct cvmx_pciercx_cfg001_s 1095 { 1096#if __BYTE_ORDER == __BIG_ENDIAN 1097 uint32_t dpe : 1; /**< Detected Parity Error */ 1098 uint32_t sse : 1; /**< Signaled System Error */ 1099 uint32_t rma : 1; /**< Received Master Abort */ 1100 uint32_t rta : 1; /**< Received Target Abort */ 1101 uint32_t sta : 1; /**< Signaled Target Abort */ 1102 uint32_t devt : 2; /**< DEVSEL Timing 1103 Not applicable for PCI Express. Hardwired to 0. */ 1104 uint32_t mdpe : 1; /**< Master Data Parity Error */ 1105 uint32_t fbb : 1; /**< Fast Back-to-Back Capable 1106 Not applicable for PCI Express. Hardwired to 0. */ 1107 uint32_t reserved_22_22 : 1; 1108 uint32_t m66 : 1; /**< 66 MHz Capable 1109 Not applicable for PCI Express. Hardwired to 0. */ 1110 uint32_t cl : 1; /**< Capabilities List 1111 Indicates presence of an extended capability item. 1112 Hardwired to 1. */ 1113 uint32_t i_stat : 1; /**< INTx Status */ 1114 uint32_t reserved_11_18 : 8; 1115 uint32_t i_dis : 1; /**< INTx Assertion Disable */ 1116 uint32_t fbbe : 1; /**< Fast Back-to-Back Enable 1117 Not applicable for PCI Express. Must be hardwired to 0. */ 1118 uint32_t see : 1; /**< SERR# Enable */ 1119 uint32_t ids_wcc : 1; /**< IDSEL Stepping/Wait Cycle Control 1120 Not applicable for PCI Express. Must be hardwired to 0 */ 1121 uint32_t per : 1; /**< Parity Error Response */ 1122 uint32_t vps : 1; /**< VGA Palette Snoop 1123 Not applicable for PCI Express. Must be hardwired to 0. */ 1124 uint32_t mwice : 1; /**< Memory Write and Invalidate 1125 Not applicable for PCI Express. Must be hardwired to 0. */ 1126 uint32_t scse : 1; /**< Special Cycle Enable 1127 Not applicable for PCI Express. Must be hardwired to 0. */ 1128 uint32_t me : 1; /**< Bus Master Enable */ 1129 uint32_t msae : 1; /**< Memory Space Enable */ 1130 uint32_t isae : 1; /**< I/O Space Enable */ 1131#else 1132 uint32_t isae : 1; 1133 uint32_t msae : 1; 1134 uint32_t me : 1; 1135 uint32_t scse : 1; 1136 uint32_t mwice : 1; 1137 uint32_t vps : 1; 1138 uint32_t per : 1; 1139 uint32_t ids_wcc : 1; 1140 uint32_t see : 1; 1141 uint32_t fbbe : 1; 1142 uint32_t i_dis : 1; 1143 uint32_t reserved_11_18 : 8; 1144 uint32_t i_stat : 1; 1145 uint32_t cl : 1; 1146 uint32_t m66 : 1; 1147 uint32_t reserved_22_22 : 1; 1148 uint32_t fbb : 1; 1149 uint32_t mdpe : 1; 1150 uint32_t devt : 2; 1151 uint32_t sta : 1; 1152 uint32_t rta : 1; 1153 uint32_t rma : 1; 1154 uint32_t sse : 1; 1155 uint32_t dpe : 1; 1156#endif 1157 } s; 1158 struct cvmx_pciercx_cfg001_s cn52xx; 1159 struct cvmx_pciercx_cfg001_s cn52xxp1; 1160 struct cvmx_pciercx_cfg001_s cn56xx; 1161 struct cvmx_pciercx_cfg001_s cn56xxp1; 1162 struct cvmx_pciercx_cfg001_s cn63xx; 1163 struct cvmx_pciercx_cfg001_s cn63xxp1; 1164}; 1165typedef union cvmx_pciercx_cfg001 cvmx_pciercx_cfg001_t; 1166 1167/** 1168 * cvmx_pcierc#_cfg002 1169 * 1170 * PCIE_CFG002 = Third 32-bits of PCIE type 1 config space (Revision ID/Class Code Register) 1171 * 1172 */ 1173union cvmx_pciercx_cfg002 1174{ 1175 uint32_t u32; 1176 struct cvmx_pciercx_cfg002_s 1177 { 1178#if __BYTE_ORDER == __BIG_ENDIAN 1179 uint32_t bcc : 8; /**< Base Class Code, writable through PEM(0..1)_CFG_WR 1180 However, the application must not change this field. */ 1181 uint32_t sc : 8; /**< Subclass Code, writable through PEM(0..1)_CFG_WR 1182 However, the application must not change this field. */ 1183 uint32_t pi : 8; /**< Programming Interface, writable through PEM(0..1)_CFG_WR 1184 However, the application must not change this field. */ 1185 uint32_t rid : 8; /**< Revision ID, writable through PEM(0..1)_CFG_WR 1186 However, the application must not change this field. */ 1187#else 1188 uint32_t rid : 8; 1189 uint32_t pi : 8; 1190 uint32_t sc : 8; 1191 uint32_t bcc : 8; 1192#endif 1193 } s; 1194 struct cvmx_pciercx_cfg002_s cn52xx; 1195 struct cvmx_pciercx_cfg002_s cn52xxp1; 1196 struct cvmx_pciercx_cfg002_s cn56xx; 1197 struct cvmx_pciercx_cfg002_s cn56xxp1; 1198 struct cvmx_pciercx_cfg002_s cn63xx; 1199 struct cvmx_pciercx_cfg002_s cn63xxp1; 1200}; 1201typedef union cvmx_pciercx_cfg002 cvmx_pciercx_cfg002_t; 1202 1203/** 1204 * cvmx_pcierc#_cfg003 1205 * 1206 * PCIE_CFG003 = Fourth 32-bits of PCIE type 1 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register) 1207 * 1208 */ 1209union cvmx_pciercx_cfg003 1210{ 1211 uint32_t u32; 1212 struct cvmx_pciercx_cfg003_s 1213 { 1214#if __BYTE_ORDER == __BIG_ENDIAN 1215 uint32_t bist : 8; /**< The BIST register functions are not supported. 1216 All 8 bits of the BIST register are hardwired to 0. */ 1217 uint32_t mfd : 1; /**< Multi Function Device 1218 The Multi Function Device bit is writable through PEM(0..1)_CFG_WR. 1219 However, this is a single function device. Therefore, the 1220 application must not write a 1 to this bit. */ 1221 uint32_t chf : 7; /**< Configuration Header Format 1222 Hardwired to 1. */ 1223 uint32_t lt : 8; /**< Master Latency Timer 1224 Not applicable for PCI Express, hardwired to 0. */ 1225 uint32_t cls : 8; /**< Cache Line Size 1226 The Cache Line Size register is RW for legacy compatibility 1227 purposes and is not applicable to PCI Express device 1228 functionality. */ 1229#else 1230 uint32_t cls : 8; 1231 uint32_t lt : 8; 1232 uint32_t chf : 7; 1233 uint32_t mfd : 1; 1234 uint32_t bist : 8; 1235#endif 1236 } s; 1237 struct cvmx_pciercx_cfg003_s cn52xx; 1238 struct cvmx_pciercx_cfg003_s cn52xxp1; 1239 struct cvmx_pciercx_cfg003_s cn56xx; 1240 struct cvmx_pciercx_cfg003_s cn56xxp1; 1241 struct cvmx_pciercx_cfg003_s cn63xx; 1242 struct cvmx_pciercx_cfg003_s cn63xxp1; 1243}; 1244typedef union cvmx_pciercx_cfg003 cvmx_pciercx_cfg003_t; 1245 1246/** 1247 * cvmx_pcierc#_cfg004 1248 * 1249 * PCIE_CFG004 = Fifth 32-bits of PCIE type 1 config space (Base Address Register 0 - Low) 1250 * 1251 */ 1252union cvmx_pciercx_cfg004 1253{ 1254 uint32_t u32; 1255 struct cvmx_pciercx_cfg004_s 1256 { 1257#if __BYTE_ORDER == __BIG_ENDIAN 1258 uint32_t reserved_0_31 : 32; 1259#else 1260 uint32_t reserved_0_31 : 32; 1261#endif 1262 } s; 1263 struct cvmx_pciercx_cfg004_s cn52xx; 1264 struct cvmx_pciercx_cfg004_s cn52xxp1; 1265 struct cvmx_pciercx_cfg004_s cn56xx; 1266 struct cvmx_pciercx_cfg004_s cn56xxp1; 1267 struct cvmx_pciercx_cfg004_s cn63xx; 1268 struct cvmx_pciercx_cfg004_s cn63xxp1; 1269}; 1270typedef union cvmx_pciercx_cfg004 cvmx_pciercx_cfg004_t; 1271 1272/** 1273 * cvmx_pcierc#_cfg005 1274 * 1275 * PCIE_CFG005 = Sixth 32-bits of PCIE type 1 config space (Base Address Register 0 - High) 1276 * 1277 */ 1278union cvmx_pciercx_cfg005 1279{ 1280 uint32_t u32; 1281 struct cvmx_pciercx_cfg005_s 1282 { 1283#if __BYTE_ORDER == __BIG_ENDIAN 1284 uint32_t reserved_0_31 : 32; 1285#else 1286 uint32_t reserved_0_31 : 32; 1287#endif 1288 } s; 1289 struct cvmx_pciercx_cfg005_s cn52xx; 1290 struct cvmx_pciercx_cfg005_s cn52xxp1; 1291 struct cvmx_pciercx_cfg005_s cn56xx; 1292 struct cvmx_pciercx_cfg005_s cn56xxp1; 1293 struct cvmx_pciercx_cfg005_s cn63xx; 1294 struct cvmx_pciercx_cfg005_s cn63xxp1; 1295}; 1296typedef union cvmx_pciercx_cfg005 cvmx_pciercx_cfg005_t; 1297 1298/** 1299 * cvmx_pcierc#_cfg006 1300 * 1301 * PCIE_CFG006 = Seventh 32-bits of PCIE type 1 config space (Bus Number Registers) 1302 * 1303 */ 1304union cvmx_pciercx_cfg006 1305{ 1306 uint32_t u32; 1307 struct cvmx_pciercx_cfg006_s 1308 { 1309#if __BYTE_ORDER == __BIG_ENDIAN 1310 uint32_t slt : 8; /**< Secondary Latency Timer 1311 Not applicable to PCI Express, hardwired to 0x00. */ 1312 uint32_t subbnum : 8; /**< Subordinate Bus Number */ 1313 uint32_t sbnum : 8; /**< Secondary Bus Number */ 1314 uint32_t pbnum : 8; /**< Primary Bus Number */ 1315#else 1316 uint32_t pbnum : 8; 1317 uint32_t sbnum : 8; 1318 uint32_t subbnum : 8; 1319 uint32_t slt : 8; 1320#endif 1321 } s; 1322 struct cvmx_pciercx_cfg006_s cn52xx; 1323 struct cvmx_pciercx_cfg006_s cn52xxp1; 1324 struct cvmx_pciercx_cfg006_s cn56xx; 1325 struct cvmx_pciercx_cfg006_s cn56xxp1; 1326 struct cvmx_pciercx_cfg006_s cn63xx; 1327 struct cvmx_pciercx_cfg006_s cn63xxp1; 1328}; 1329typedef union cvmx_pciercx_cfg006 cvmx_pciercx_cfg006_t; 1330 1331/** 1332 * cvmx_pcierc#_cfg007 1333 * 1334 * PCIE_CFG007 = Eighth 32-bits of PCIE type 1 config space (IO Base and IO Limit/Secondary Status Register) 1335 * 1336 */ 1337union cvmx_pciercx_cfg007 1338{ 1339 uint32_t u32; 1340 struct cvmx_pciercx_cfg007_s 1341 { 1342#if __BYTE_ORDER == __BIG_ENDIAN 1343 uint32_t dpe : 1; /**< Detected Parity Error */ 1344 uint32_t sse : 1; /**< Signaled System Error */ 1345 uint32_t rma : 1; /**< Received Master Abort */ 1346 uint32_t rta : 1; /**< Received Target Abort */ 1347 uint32_t sta : 1; /**< Signaled Target Abort */ 1348 uint32_t devt : 2; /**< DEVSEL Timing 1349 Not applicable for PCI Express. Hardwired to 0. */ 1350 uint32_t mdpe : 1; /**< Master Data Parity Error */ 1351 uint32_t fbb : 1; /**< Fast Back-to-Back Capable 1352 Not applicable for PCI Express. Hardwired to 0. */ 1353 uint32_t reserved_22_22 : 1; 1354 uint32_t m66 : 1; /**< 66 MHz Capable 1355 Not applicable for PCI Express. Hardwired to 0. */ 1356 uint32_t reserved_16_20 : 5; 1357 uint32_t lio_limi : 4; /**< I/O Space Limit */ 1358 uint32_t reserved_9_11 : 3; 1359 uint32_t io32b : 1; /**< 32-Bit I/O Space */ 1360 uint32_t lio_base : 4; /**< I/O Space Base */ 1361 uint32_t reserved_1_3 : 3; 1362 uint32_t io32a : 1; /**< 32-Bit I/O Space 1363 o 0 = 16-bit I/O addressing 1364 o 1 = 32-bit I/O addressing 1365 This bit is writable through PEM(0..1)_CFG_WR. 1366 When the application 1367 writes to this bit through PEM(0..1)_CFG_WR, 1368 the same value is written 1369 to bit 8 of this register. */ 1370#else 1371 uint32_t io32a : 1; 1372 uint32_t reserved_1_3 : 3; 1373 uint32_t lio_base : 4; 1374 uint32_t io32b : 1; 1375 uint32_t reserved_9_11 : 3; 1376 uint32_t lio_limi : 4; 1377 uint32_t reserved_16_20 : 5; 1378 uint32_t m66 : 1; 1379 uint32_t reserved_22_22 : 1; 1380 uint32_t fbb : 1; 1381 uint32_t mdpe : 1; 1382 uint32_t devt : 2; 1383 uint32_t sta : 1; 1384 uint32_t rta : 1; 1385 uint32_t rma : 1; 1386 uint32_t sse : 1; 1387 uint32_t dpe : 1; 1388#endif 1389 } s; 1390 struct cvmx_pciercx_cfg007_s cn52xx; 1391 struct cvmx_pciercx_cfg007_s cn52xxp1; 1392 struct cvmx_pciercx_cfg007_s cn56xx; 1393 struct cvmx_pciercx_cfg007_s cn56xxp1; 1394 struct cvmx_pciercx_cfg007_s cn63xx; 1395 struct cvmx_pciercx_cfg007_s cn63xxp1; 1396}; 1397typedef union cvmx_pciercx_cfg007 cvmx_pciercx_cfg007_t; 1398 1399/** 1400 * cvmx_pcierc#_cfg008 1401 * 1402 * PCIE_CFG008 = Ninth 32-bits of PCIE type 1 config space (Memory Base and Memory Limit Register) 1403 * 1404 */ 1405union cvmx_pciercx_cfg008 1406{ 1407 uint32_t u32; 1408 struct cvmx_pciercx_cfg008_s 1409 { 1410#if __BYTE_ORDER == __BIG_ENDIAN 1411 uint32_t ml_addr : 12; /**< Memory Limit Address */ 1412 uint32_t reserved_16_19 : 4; 1413 uint32_t mb_addr : 12; /**< Memory Base Address */ 1414 uint32_t reserved_0_3 : 4; 1415#else 1416 uint32_t reserved_0_3 : 4; 1417 uint32_t mb_addr : 12; 1418 uint32_t reserved_16_19 : 4; 1419 uint32_t ml_addr : 12; 1420#endif 1421 } s; 1422 struct cvmx_pciercx_cfg008_s cn52xx; 1423 struct cvmx_pciercx_cfg008_s cn52xxp1; 1424 struct cvmx_pciercx_cfg008_s cn56xx; 1425 struct cvmx_pciercx_cfg008_s cn56xxp1; 1426 struct cvmx_pciercx_cfg008_s cn63xx; 1427 struct cvmx_pciercx_cfg008_s cn63xxp1; 1428}; 1429typedef union cvmx_pciercx_cfg008 cvmx_pciercx_cfg008_t; 1430 1431/** 1432 * cvmx_pcierc#_cfg009 1433 * 1434 * PCIE_CFG009 = Tenth 32-bits of PCIE type 1 config space (Prefetchable Memory Base and Limit Register) 1435 * 1436 */ 1437union cvmx_pciercx_cfg009 1438{ 1439 uint32_t u32; 1440 struct cvmx_pciercx_cfg009_s 1441 { 1442#if __BYTE_ORDER == __BIG_ENDIAN 1443 uint32_t lmem_limit : 12; /**< Upper 12 bits of 32-bit Prefetchable Memory End Address */ 1444 uint32_t reserved_17_19 : 3; 1445 uint32_t mem64b : 1; /**< 64-Bit Memory Addressing 1446 o 0 = 32-bit memory addressing 1447 o 1 = 64-bit memory addressing */ 1448 uint32_t lmem_base : 12; /**< Upper 12 bits of 32-bit Prefetchable Memory Start Address */ 1449 uint32_t reserved_1_3 : 3; 1450 uint32_t mem64a : 1; /**< 64-Bit Memory Addressing 1451 o 0 = 32-bit memory addressing 1452 o 1 = 64-bit memory addressing 1453 This bit is writable through PEM(0..1)_CFG_WR. 1454 When the application 1455 writes to this bit through PEM(0..1)_CFG_WR, 1456 the same value is written 1457 to bit 16 of this register. */ 1458#else 1459 uint32_t mem64a : 1; 1460 uint32_t reserved_1_3 : 3; 1461 uint32_t lmem_base : 12; 1462 uint32_t mem64b : 1; 1463 uint32_t reserved_17_19 : 3; 1464 uint32_t lmem_limit : 12; 1465#endif 1466 } s; 1467 struct cvmx_pciercx_cfg009_s cn52xx; 1468 struct cvmx_pciercx_cfg009_s cn52xxp1; 1469 struct cvmx_pciercx_cfg009_s cn56xx; 1470 struct cvmx_pciercx_cfg009_s cn56xxp1; 1471 struct cvmx_pciercx_cfg009_s cn63xx; 1472 struct cvmx_pciercx_cfg009_s cn63xxp1; 1473}; 1474typedef union cvmx_pciercx_cfg009 cvmx_pciercx_cfg009_t; 1475 1476/** 1477 * cvmx_pcierc#_cfg010 1478 * 1479 * PCIE_CFG010 = Eleventh 32-bits of PCIE type 1 config space (Prefetchable Base Upper 32 Bits Register) 1480 * 1481 */ 1482union cvmx_pciercx_cfg010 1483{ 1484 uint32_t u32; 1485 struct cvmx_pciercx_cfg010_s 1486 { 1487#if __BYTE_ORDER == __BIG_ENDIAN 1488 uint32_t umem_base : 32; /**< Upper 32 Bits of Base Address of Prefetchable Memory Space 1489 Used only when 64-bit prefetchable memory addressing is 1490 enabled. */ 1491#else 1492 uint32_t umem_base : 32; 1493#endif 1494 } s; 1495 struct cvmx_pciercx_cfg010_s cn52xx; 1496 struct cvmx_pciercx_cfg010_s cn52xxp1; 1497 struct cvmx_pciercx_cfg010_s cn56xx; 1498 struct cvmx_pciercx_cfg010_s cn56xxp1; 1499 struct cvmx_pciercx_cfg010_s cn63xx; 1500 struct cvmx_pciercx_cfg010_s cn63xxp1; 1501}; 1502typedef union cvmx_pciercx_cfg010 cvmx_pciercx_cfg010_t; 1503 1504/** 1505 * cvmx_pcierc#_cfg011 1506 * 1507 * PCIE_CFG011 = Twelfth 32-bits of PCIE type 1 config space (Prefetchable Limit Upper 32 Bits Register) 1508 * 1509 */ 1510union cvmx_pciercx_cfg011 1511{ 1512 uint32_t u32; 1513 struct cvmx_pciercx_cfg011_s 1514 { 1515#if __BYTE_ORDER == __BIG_ENDIAN 1516 uint32_t umem_limit : 32; /**< Upper 32 Bits of Limit Address of Prefetchable Memory Space 1517 Used only when 64-bit prefetchable memory addressing is 1518 enabled. */ 1519#else 1520 uint32_t umem_limit : 32; 1521#endif 1522 } s; 1523 struct cvmx_pciercx_cfg011_s cn52xx; 1524 struct cvmx_pciercx_cfg011_s cn52xxp1; 1525 struct cvmx_pciercx_cfg011_s cn56xx; 1526 struct cvmx_pciercx_cfg011_s cn56xxp1; 1527 struct cvmx_pciercx_cfg011_s cn63xx; 1528 struct cvmx_pciercx_cfg011_s cn63xxp1; 1529}; 1530typedef union cvmx_pciercx_cfg011 cvmx_pciercx_cfg011_t; 1531 1532/** 1533 * cvmx_pcierc#_cfg012 1534 * 1535 * PCIE_CFG012 = Thirteenth 32-bits of PCIE type 1 config space (IO Base and Limit Upper 16 Bits Register) 1536 * 1537 */ 1538union cvmx_pciercx_cfg012 1539{ 1540 uint32_t u32; 1541 struct cvmx_pciercx_cfg012_s 1542 { 1543#if __BYTE_ORDER == __BIG_ENDIAN 1544 uint32_t uio_limit : 16; /**< Upper 16 Bits of I/O Limit (if 32-bit I/O decoding is supported 1545 for devices on the secondary side) */ 1546 uint32_t uio_base : 16; /**< Upper 16 Bits of I/O Base (if 32-bit I/O decoding is supported 1547 for devices on the secondary side) */ 1548#else 1549 uint32_t uio_base : 16; 1550 uint32_t uio_limit : 16; 1551#endif 1552 } s; 1553 struct cvmx_pciercx_cfg012_s cn52xx; 1554 struct cvmx_pciercx_cfg012_s cn52xxp1; 1555 struct cvmx_pciercx_cfg012_s cn56xx; 1556 struct cvmx_pciercx_cfg012_s cn56xxp1; 1557 struct cvmx_pciercx_cfg012_s cn63xx; 1558 struct cvmx_pciercx_cfg012_s cn63xxp1; 1559}; 1560typedef union cvmx_pciercx_cfg012 cvmx_pciercx_cfg012_t; 1561 1562/** 1563 * cvmx_pcierc#_cfg013 1564 * 1565 * PCIE_CFG013 = Fourteenth 32-bits of PCIE type 1 config space (Capability Pointer Register) 1566 * 1567 */ 1568union cvmx_pciercx_cfg013 1569{ 1570 uint32_t u32; 1571 struct cvmx_pciercx_cfg013_s 1572 { 1573#if __BYTE_ORDER == __BIG_ENDIAN 1574 uint32_t reserved_8_31 : 24; 1575 uint32_t cp : 8; /**< First Capability Pointer. 1576 Points to Power Management Capability structure by 1577 default, writable through PEM(0..1)_CFG_WR 1578 However, the application must not change this field. */ 1579#else 1580 uint32_t cp : 8; 1581 uint32_t reserved_8_31 : 24; 1582#endif 1583 } s; 1584 struct cvmx_pciercx_cfg013_s cn52xx; 1585 struct cvmx_pciercx_cfg013_s cn52xxp1; 1586 struct cvmx_pciercx_cfg013_s cn56xx; 1587 struct cvmx_pciercx_cfg013_s cn56xxp1; 1588 struct cvmx_pciercx_cfg013_s cn63xx; 1589 struct cvmx_pciercx_cfg013_s cn63xxp1; 1590}; 1591typedef union cvmx_pciercx_cfg013 cvmx_pciercx_cfg013_t; 1592 1593/** 1594 * cvmx_pcierc#_cfg014 1595 * 1596 * PCIE_CFG014 = Fifteenth 32-bits of PCIE type 1 config space (Expansion ROM Base Address Register) 1597 * 1598 */ 1599union cvmx_pciercx_cfg014 1600{ 1601 uint32_t u32; 1602 struct cvmx_pciercx_cfg014_s 1603 { 1604#if __BYTE_ORDER == __BIG_ENDIAN 1605 uint32_t reserved_0_31 : 32; 1606#else 1607 uint32_t reserved_0_31 : 32; 1608#endif 1609 } s; 1610 struct cvmx_pciercx_cfg014_s cn52xx; 1611 struct cvmx_pciercx_cfg014_s cn52xxp1; 1612 struct cvmx_pciercx_cfg014_s cn56xx; 1613 struct cvmx_pciercx_cfg014_s cn56xxp1; 1614 struct cvmx_pciercx_cfg014_s cn63xx; 1615 struct cvmx_pciercx_cfg014_s cn63xxp1; 1616}; 1617typedef union cvmx_pciercx_cfg014 cvmx_pciercx_cfg014_t; 1618 1619/** 1620 * cvmx_pcierc#_cfg015 1621 * 1622 * PCIE_CFG015 = Sixteenth 32-bits of PCIE type 1 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register) 1623 * 1624 */ 1625union cvmx_pciercx_cfg015 1626{ 1627 uint32_t u32; 1628 struct cvmx_pciercx_cfg015_s 1629 { 1630#if __BYTE_ORDER == __BIG_ENDIAN 1631 uint32_t reserved_28_31 : 4; 1632 uint32_t dtsees : 1; /**< Discard Timer SERR Enable Status 1633 Not applicable to PCI Express, hardwired to 0. */ 1634 uint32_t dts : 1; /**< Discard Timer Status 1635 Not applicable to PCI Express, hardwired to 0. */ 1636 uint32_t sdt : 1; /**< Secondary Discard Timer 1637 Not applicable to PCI Express, hardwired to 0. */ 1638 uint32_t pdt : 1; /**< Primary Discard Timer 1639 Not applicable to PCI Express, hardwired to 0. */ 1640 uint32_t fbbe : 1; /**< Fast Back-to-Back Transactions Enable 1641 Not applicable to PCI Express, hardwired to 0. */ 1642 uint32_t sbrst : 1; /**< Secondary Bus Reset 1643 Hot reset. Causes TS1s with the hot reset bit to be sent to 1644 the link partner. When set, SW should wait 2ms before 1645 clearing. The link partner normally responds by sending TS1s 1646 with the hot reset bit set, which will cause a link 1647 down event - refer to "PCIe Link-Down Reset in RC Mode" 1648 section. */ 1649 uint32_t mam : 1; /**< Master Abort Mode 1650 Not applicable to PCI Express, hardwired to 0. */ 1651 uint32_t vga16d : 1; /**< VGA 16-Bit Decode */ 1652 uint32_t vgae : 1; /**< VGA Enable */ 1653 uint32_t isae : 1; /**< ISA Enable */ 1654 uint32_t see : 1; /**< SERR Enable */ 1655 uint32_t pere : 1; /**< Parity Error Response Enable */ 1656 uint32_t inta : 8; /**< Interrupt Pin 1657 Identifies the legacy interrupt Message that the device 1658 (or device function) uses. 1659 The Interrupt Pin register is writable through PEM(0..1)_CFG_WR. 1660 In a single-function configuration, only INTA is used. 1661 Therefore, the application must not change this field. */ 1662 uint32_t il : 8; /**< Interrupt Line */ 1663#else 1664 uint32_t il : 8; 1665 uint32_t inta : 8; 1666 uint32_t pere : 1; 1667 uint32_t see : 1; 1668 uint32_t isae : 1; 1669 uint32_t vgae : 1; 1670 uint32_t vga16d : 1; 1671 uint32_t mam : 1; 1672 uint32_t sbrst : 1; 1673 uint32_t fbbe : 1; 1674 uint32_t pdt : 1; 1675 uint32_t sdt : 1; 1676 uint32_t dts : 1; 1677 uint32_t dtsees : 1; 1678 uint32_t reserved_28_31 : 4; 1679#endif 1680 } s; 1681 struct cvmx_pciercx_cfg015_s cn52xx; 1682 struct cvmx_pciercx_cfg015_s cn52xxp1; 1683 struct cvmx_pciercx_cfg015_s cn56xx; 1684 struct cvmx_pciercx_cfg015_s cn56xxp1; 1685 struct cvmx_pciercx_cfg015_s cn63xx; 1686 struct cvmx_pciercx_cfg015_s cn63xxp1; 1687}; 1688typedef union cvmx_pciercx_cfg015 cvmx_pciercx_cfg015_t; 1689 1690/** 1691 * cvmx_pcierc#_cfg016 1692 * 1693 * PCIE_CFG016 = Seventeenth 32-bits of PCIE type 1 config space 1694 * (Power Management Capability ID/ 1695 * Power Management Next Item Pointer/ 1696 * Power Management Capabilities Register) 1697 */ 1698union cvmx_pciercx_cfg016 1699{ 1700 uint32_t u32; 1701 struct cvmx_pciercx_cfg016_s 1702 { 1703#if __BYTE_ORDER == __BIG_ENDIAN 1704 uint32_t pmes : 5; /**< PME_Support 1705 A value of 0 for any bit indicates that the 1706 device (or function) is not capable of generating PME Messages 1707 while in that power state: 1708 o Bit 11: If set, PME Messages can be generated from D0 1709 o Bit 12: If set, PME Messages can be generated from D1 1710 o Bit 13: If set, PME Messages can be generated from D2 1711 o Bit 14: If set, PME Messages can be generated from D3hot 1712 o Bit 15: If set, PME Messages can be generated from D3cold 1713 The PME_Support field is writable through PEM(0..1)_CFG_WR. 1714 However, the application must not change this field. */ 1715 uint32_t d2s : 1; /**< D2 Support, writable through PEM(0..1)_CFG_WR 1716 However, the application must not change this field. */ 1717 uint32_t d1s : 1; /**< D1 Support, writable through PEM(0..1)_CFG_WR 1718 However, the application must not change this field. */ 1719 uint32_t auxc : 3; /**< AUX Current, writable through PEM(0..1)_CFG_WR 1720 However, the application must not change this field. */ 1721 uint32_t dsi : 1; /**< Device Specific Initialization (DSI), writable through PEM(0..1)_CFG_WR 1722 However, the application must not change this field. */ 1723 uint32_t reserved_20_20 : 1; 1724 uint32_t pme_clock : 1; /**< PME Clock, hardwired to 0 */ 1725 uint32_t pmsv : 3; /**< Power Management Specification Version, writable through PEM(0..1)_CFG_WR 1726 However, the application must not change this field. */ 1727 uint32_t ncp : 8; /**< Next Capability Pointer 1728 Points to the MSI capabilities by default, writable 1729 through PEM(0..1)_CFG_WR. */ 1730 uint32_t pmcid : 8; /**< Power Management Capability ID */ 1731#else 1732 uint32_t pmcid : 8; 1733 uint32_t ncp : 8; 1734 uint32_t pmsv : 3; 1735 uint32_t pme_clock : 1; 1736 uint32_t reserved_20_20 : 1; 1737 uint32_t dsi : 1; 1738 uint32_t auxc : 3; 1739 uint32_t d1s : 1; 1740 uint32_t d2s : 1; 1741 uint32_t pmes : 5; 1742#endif 1743 } s; 1744 struct cvmx_pciercx_cfg016_s cn52xx; 1745 struct cvmx_pciercx_cfg016_s cn52xxp1; 1746 struct cvmx_pciercx_cfg016_s cn56xx; 1747 struct cvmx_pciercx_cfg016_s cn56xxp1; 1748 struct cvmx_pciercx_cfg016_s cn63xx; 1749 struct cvmx_pciercx_cfg016_s cn63xxp1; 1750}; 1751typedef union cvmx_pciercx_cfg016 cvmx_pciercx_cfg016_t; 1752 1753/** 1754 * cvmx_pcierc#_cfg017 1755 * 1756 * PCIE_CFG017 = Eighteenth 32-bits of PCIE type 1 config space (Power Management Control and Status Register) 1757 * 1758 */ 1759union cvmx_pciercx_cfg017 1760{ 1761 uint32_t u32; 1762 struct cvmx_pciercx_cfg017_s 1763 { 1764#if __BYTE_ORDER == __BIG_ENDIAN 1765 uint32_t pmdia : 8; /**< Data register for additional information (not supported) */ 1766 uint32_t bpccee : 1; /**< Bus Power/Clock Control Enable, hardwired to 0 */ 1767 uint32_t bd3h : 1; /**< B2/B3 Support, hardwired to 0 */ 1768 uint32_t reserved_16_21 : 6; 1769 uint32_t pmess : 1; /**< PME Status 1770 Indicates if a previously enabled PME event occurred or not. */ 1771 uint32_t pmedsia : 2; /**< Data Scale (not supported) */ 1772 uint32_t pmds : 4; /**< Data Select (not supported) */ 1773 uint32_t pmeens : 1; /**< PME Enable 1774 A value of 1 indicates that the device is enabled to 1775 generate PME. */ 1776 uint32_t reserved_4_7 : 4; 1777 uint32_t nsr : 1; /**< No Soft Reset, writable through PEM(0..1)_CFG_WR 1778 However, the application must not change this field. */ 1779 uint32_t reserved_2_2 : 1; 1780 uint32_t ps : 2; /**< Power State 1781 Controls the device power state: 1782 o 00b: D0 1783 o 01b: D1 1784 o 10b: D2 1785 o 11b: D3 1786 The written value is ignored if the specific state is 1787 not supported. */ 1788#else 1789 uint32_t ps : 2; 1790 uint32_t reserved_2_2 : 1; 1791 uint32_t nsr : 1; 1792 uint32_t reserved_4_7 : 4; 1793 uint32_t pmeens : 1; 1794 uint32_t pmds : 4; 1795 uint32_t pmedsia : 2; 1796 uint32_t pmess : 1; 1797 uint32_t reserved_16_21 : 6; 1798 uint32_t bd3h : 1; 1799 uint32_t bpccee : 1; 1800 uint32_t pmdia : 8; 1801#endif 1802 } s; 1803 struct cvmx_pciercx_cfg017_s cn52xx; 1804 struct cvmx_pciercx_cfg017_s cn52xxp1; 1805 struct cvmx_pciercx_cfg017_s cn56xx; 1806 struct cvmx_pciercx_cfg017_s cn56xxp1; 1807 struct cvmx_pciercx_cfg017_s cn63xx; 1808 struct cvmx_pciercx_cfg017_s cn63xxp1; 1809}; 1810typedef union cvmx_pciercx_cfg017 cvmx_pciercx_cfg017_t; 1811 1812/** 1813 * cvmx_pcierc#_cfg020 1814 * 1815 * PCIE_CFG020 = Twenty-first 32-bits of PCIE type 1 config space 1816 * (MSI Capability ID/ 1817 * MSI Next Item Pointer/ 1818 * MSI Control Register) 1819 */ 1820union cvmx_pciercx_cfg020 1821{ 1822 uint32_t u32; 1823 struct cvmx_pciercx_cfg020_s 1824 { 1825#if __BYTE_ORDER == __BIG_ENDIAN 1826 uint32_t reserved_24_31 : 8; 1827 uint32_t m64 : 1; /**< 64-bit Address Capable, writable through PEM(0..1)_CFG_WR 1828 However, the application must not change this field. */ 1829 uint32_t mme : 3; /**< Multiple Message Enabled 1830 Indicates that multiple Message mode is enabled by system 1831 software. The number of Messages enabled must be less than 1832 or equal to the Multiple Message Capable value. */ 1833 uint32_t mmc : 3; /**< Multiple Message Capable, writable through PEM(0..1)_CFG_WR 1834 However, the application must not change this field. */ 1835 uint32_t msien : 1; /**< MSI Enabled 1836 When set, INTx must be disabled. 1837 This bit must never be set, as internal-MSI is not supported in 1838 RC mode. (Note that this has no effect on external MSI, which 1839 will be commonly used in RC mode.) */ 1840 uint32_t ncp : 8; /**< Next Capability Pointer 1841 Points to PCI Express Capabilities by default, 1842 writable through PEM(0..1)_CFG_WR. 1843 However, the application must not change this field. */ 1844 uint32_t msicid : 8; /**< MSI Capability ID */ 1845#else 1846 uint32_t msicid : 8; 1847 uint32_t ncp : 8; 1848 uint32_t msien : 1; 1849 uint32_t mmc : 3; 1850 uint32_t mme : 3; 1851 uint32_t m64 : 1; 1852 uint32_t reserved_24_31 : 8; 1853#endif 1854 } s; 1855 struct cvmx_pciercx_cfg020_s cn52xx; 1856 struct cvmx_pciercx_cfg020_s cn52xxp1; 1857 struct cvmx_pciercx_cfg020_s cn56xx; 1858 struct cvmx_pciercx_cfg020_s cn56xxp1; 1859 struct cvmx_pciercx_cfg020_s cn63xx; 1860 struct cvmx_pciercx_cfg020_s cn63xxp1; 1861}; 1862typedef union cvmx_pciercx_cfg020 cvmx_pciercx_cfg020_t; 1863 1864/** 1865 * cvmx_pcierc#_cfg021 1866 * 1867 * PCIE_CFG021 = Twenty-second 32-bits of PCIE type 1 config space (MSI Lower 32 Bits Address Register) 1868 * 1869 */ 1870union cvmx_pciercx_cfg021 1871{ 1872 uint32_t u32; 1873 struct cvmx_pciercx_cfg021_s 1874 { 1875#if __BYTE_ORDER == __BIG_ENDIAN 1876 uint32_t lmsi : 30; /**< Lower 32-bit Address */ 1877 uint32_t reserved_0_1 : 2; 1878#else 1879 uint32_t reserved_0_1 : 2; 1880 uint32_t lmsi : 30; 1881#endif 1882 } s; 1883 struct cvmx_pciercx_cfg021_s cn52xx; 1884 struct cvmx_pciercx_cfg021_s cn52xxp1; 1885 struct cvmx_pciercx_cfg021_s cn56xx; 1886 struct cvmx_pciercx_cfg021_s cn56xxp1; 1887 struct cvmx_pciercx_cfg021_s cn63xx; 1888 struct cvmx_pciercx_cfg021_s cn63xxp1; 1889}; 1890typedef union cvmx_pciercx_cfg021 cvmx_pciercx_cfg021_t; 1891 1892/** 1893 * cvmx_pcierc#_cfg022 1894 * 1895 * PCIE_CFG022 = Twenty-third 32-bits of PCIE type 1 config space (MSI Upper 32 bits Address Register) 1896 * 1897 */ 1898union cvmx_pciercx_cfg022 1899{ 1900 uint32_t u32; 1901 struct cvmx_pciercx_cfg022_s 1902 { 1903#if __BYTE_ORDER == __BIG_ENDIAN 1904 uint32_t umsi : 32; /**< Upper 32-bit Address */ 1905#else 1906 uint32_t umsi : 32; 1907#endif 1908 } s; 1909 struct cvmx_pciercx_cfg022_s cn52xx; 1910 struct cvmx_pciercx_cfg022_s cn52xxp1; 1911 struct cvmx_pciercx_cfg022_s cn56xx; 1912 struct cvmx_pciercx_cfg022_s cn56xxp1; 1913 struct cvmx_pciercx_cfg022_s cn63xx; 1914 struct cvmx_pciercx_cfg022_s cn63xxp1; 1915}; 1916typedef union cvmx_pciercx_cfg022 cvmx_pciercx_cfg022_t; 1917 1918/** 1919 * cvmx_pcierc#_cfg023 1920 * 1921 * PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 1 config space (MSI Data Register) 1922 * 1923 */ 1924union cvmx_pciercx_cfg023 1925{ 1926 uint32_t u32; 1927 struct cvmx_pciercx_cfg023_s 1928 { 1929#if __BYTE_ORDER == __BIG_ENDIAN 1930 uint32_t reserved_16_31 : 16; 1931 uint32_t msimd : 16; /**< MSI Data 1932 Pattern assigned by system software, bits [4:0] are Or-ed with 1933 MSI_VECTOR to generate 32 MSI Messages per function. */ 1934#else 1935 uint32_t msimd : 16; 1936 uint32_t reserved_16_31 : 16; 1937#endif 1938 } s; 1939 struct cvmx_pciercx_cfg023_s cn52xx; 1940 struct cvmx_pciercx_cfg023_s cn52xxp1; 1941 struct cvmx_pciercx_cfg023_s cn56xx; 1942 struct cvmx_pciercx_cfg023_s cn56xxp1; 1943 struct cvmx_pciercx_cfg023_s cn63xx; 1944 struct cvmx_pciercx_cfg023_s cn63xxp1; 1945}; 1946typedef union cvmx_pciercx_cfg023 cvmx_pciercx_cfg023_t; 1947 1948/** 1949 * cvmx_pcierc#_cfg028 1950 * 1951 * PCIE_CFG028 = Twenty-ninth 32-bits of PCIE type 1 config space 1952 * (PCI Express Capabilities List Register/ 1953 * PCI Express Capabilities Register) 1954 */ 1955union cvmx_pciercx_cfg028 1956{ 1957 uint32_t u32; 1958 struct cvmx_pciercx_cfg028_s 1959 { 1960#if __BYTE_ORDER == __BIG_ENDIAN 1961 uint32_t reserved_30_31 : 2; 1962 uint32_t imn : 5; /**< Interrupt Message Number 1963 Updated by hardware, writable through PEM(0..1)_CFG_WR. 1964 However, the application must not change this field. */ 1965 uint32_t si : 1; /**< Slot Implemented 1966 This bit is writable through PEM(0..1)_CFG_WR. 1967 However, it must 0 for an 1968 Endpoint device. Therefore, the application must not write a 1969 1 to this bit. */ 1970 uint32_t dpt : 4; /**< Device Port Type */ 1971 uint32_t pciecv : 4; /**< PCI Express Capability Version */ 1972 uint32_t ncp : 8; /**< Next Capability Pointer 1973 writable through PEM(0..1)_CFG_WR. 1974 However, the application must not change this field. */ 1975 uint32_t pcieid : 8; /**< PCIE Capability ID */ 1976#else 1977 uint32_t pcieid : 8; 1978 uint32_t ncp : 8; 1979 uint32_t pciecv : 4; 1980 uint32_t dpt : 4; 1981 uint32_t si : 1; 1982 uint32_t imn : 5; 1983 uint32_t reserved_30_31 : 2; 1984#endif 1985 } s; 1986 struct cvmx_pciercx_cfg028_s cn52xx; 1987 struct cvmx_pciercx_cfg028_s cn52xxp1; 1988 struct cvmx_pciercx_cfg028_s cn56xx; 1989 struct cvmx_pciercx_cfg028_s cn56xxp1; 1990 struct cvmx_pciercx_cfg028_s cn63xx; 1991 struct cvmx_pciercx_cfg028_s cn63xxp1; 1992}; 1993typedef union cvmx_pciercx_cfg028 cvmx_pciercx_cfg028_t; 1994 1995/** 1996 * cvmx_pcierc#_cfg029 1997 * 1998 * PCIE_CFG029 = Thirtieth 32-bits of PCIE type 1 config space (Device Capabilities Register) 1999 * 2000 */ 2001union cvmx_pciercx_cfg029 2002{ 2003 uint32_t u32; 2004 struct cvmx_pciercx_cfg029_s 2005 { 2006#if __BYTE_ORDER == __BIG_ENDIAN 2007 uint32_t reserved_28_31 : 4; 2008 uint32_t cspls : 2; /**< Captured Slot Power Limit Scale 2009 Not applicable for RC port, upstream port only. */ 2010 uint32_t csplv : 8; /**< Captured Slot Power Limit Value 2011 Not applicable for RC port, upstream port only. */ 2012 uint32_t reserved_16_17 : 2; 2013 uint32_t rber : 1; /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR 2014 However, the application must not change this field. */ 2015 uint32_t reserved_12_14 : 3; 2016 uint32_t el1al : 3; /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR 2017 Must be 0x0 for non-endpoint devices. */ 2018 uint32_t el0al : 3; /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR 2019 Must be 0x0 for non-endpoint devices. */ 2020 uint32_t etfs : 1; /**< Extended Tag Field Supported 2021 This bit is writable through PEM(0..1)_CFG_WR. 2022 However, the application 2023 must not write a 1 to this bit. */ 2024 uint32_t pfs : 2; /**< Phantom Function Supported 2025 This field is writable through PEM(0..1)_CFG_WR. 2026 However, Phantom 2027 Function is not supported. Therefore, the application must not 2028 write any value other than 0x0 to this field. */ 2029 uint32_t mpss : 3; /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR 2030 However, the application must not change this field. */ 2031#else 2032 uint32_t mpss : 3; 2033 uint32_t pfs : 2; 2034 uint32_t etfs : 1; 2035 uint32_t el0al : 3; 2036 uint32_t el1al : 3; 2037 uint32_t reserved_12_14 : 3; 2038 uint32_t rber : 1; 2039 uint32_t reserved_16_17 : 2; 2040 uint32_t csplv : 8; 2041 uint32_t cspls : 2; 2042 uint32_t reserved_28_31 : 4; 2043#endif 2044 } s; 2045 struct cvmx_pciercx_cfg029_s cn52xx; 2046 struct cvmx_pciercx_cfg029_s cn52xxp1; 2047 struct cvmx_pciercx_cfg029_s cn56xx; 2048 struct cvmx_pciercx_cfg029_s cn56xxp1; 2049 struct cvmx_pciercx_cfg029_s cn63xx; 2050 struct cvmx_pciercx_cfg029_s cn63xxp1; 2051}; 2052typedef union cvmx_pciercx_cfg029 cvmx_pciercx_cfg029_t; 2053 2054/** 2055 * cvmx_pcierc#_cfg030 2056 * 2057 * PCIE_CFG030 = Thirty-first 32-bits of PCIE type 1 config space 2058 * (Device Control Register/Device Status Register) 2059 */ 2060union cvmx_pciercx_cfg030 2061{ 2062 uint32_t u32; 2063 struct cvmx_pciercx_cfg030_s 2064 { 2065#if __BYTE_ORDER == __BIG_ENDIAN 2066 uint32_t reserved_22_31 : 10; 2067 uint32_t tp : 1; /**< Transaction Pending 2068 Set to 1 when Non-Posted Requests are not yet completed 2069 and clear when they are completed. */ 2070 uint32_t ap_d : 1; /**< Aux Power Detected 2071 Set to 1 if Aux power detected. */ 2072 uint32_t ur_d : 1; /**< Unsupported Request Detected 2073 Errors are logged in this register regardless of whether 2074 error reporting is enabled in the Device Control register. 2075 UR_D occurs when we receive something we don't support. 2076 Unsupported requests are Nonfatal errors, so UR_D should 2077 cause NFE_D. Receiving a vendor defined message should 2078 cause an unsupported request. */ 2079 uint32_t fe_d : 1; /**< Fatal Error Detected 2080 Errors are logged in this register regardless of whether 2081 error reporting is enabled in the Device Control register. 2082 FE_D is set if receive any of the errors in PCIE_CFG066 that 2083 has a severity set to Fatal. Malformed TLP's generally fit 2084 into this category. */ 2085 uint32_t nfe_d : 1; /**< Non-Fatal Error detected 2086 Errors are logged in this register regardless of whether 2087 error reporting is enabled in the Device Control register. 2088 NFE_D is set if we receive any of the errors in PCIE_CFG066 2089 that has a severity set to Nonfatal and does NOT meet Advisory 2090 Nonfatal criteria , which 2091 most poisoned TLP's should be. */ 2092 uint32_t ce_d : 1; /**< Correctable Error Detected 2093 Errors are logged in this register regardless of whether 2094 error reporting is enabled in the Device Control register. 2095 CE_D is set if we receive any of the errors in PCIE_CFG068 2096 for example a Replay Timer Timeout. Also, it can be set if 2097 we get any of the errors in PCIE_CFG066 that has a severity 2098 set to Nonfatal and meets the Advisory Nonfatal criteria, 2099 which most ECRC errors should be. */ 2100 uint32_t reserved_15_15 : 1; 2101 uint32_t mrrs : 3; /**< Max Read Request Size 2102 0 = 128B 2103 1 = 256B 2104 2 = 512B 2105 3 = 1024B 2106 4 = 2048B 2107 5 = 4096B 2108 Note: SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] and 2109 also must be set properly. 2110 SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] must 2111 not exceed the desired max read request size. */ 2112 uint32_t ns_en : 1; /**< Enable No Snoop */ 2113 uint32_t ap_en : 1; /**< AUX Power PM Enable */ 2114 uint32_t pf_en : 1; /**< Phantom Function Enable 2115 This bit should never be set - OCTEON requests never use 2116 phantom functions. */ 2117 uint32_t etf_en : 1; /**< Extended Tag Field Enable 2118 This bit should never be set - OCTEON requests never use 2119 extended tags. */ 2120 uint32_t mps : 3; /**< Max Payload Size 2121 Legal values: 2122 0 = 128B 2123 1 = 256B 2124 Larger sizes not supported. 2125 Note: Both PCI Express Ports must be set to the same value 2126 for Peer-to-Peer to function properly. 2127 Note: DPI_SLI_PRT#_CFG[MPS] must also be set to the same 2128 value for proper functionality. */ 2129 uint32_t ro_en : 1; /**< Enable Relaxed Ordering */ 2130 uint32_t ur_en : 1; /**< Unsupported Request Reporting Enable */ 2131 uint32_t fe_en : 1; /**< Fatal Error Reporting Enable */ 2132 uint32_t nfe_en : 1; /**< Non-Fatal Error Reporting Enable */ 2133 uint32_t ce_en : 1; /**< Correctable Error Reporting Enable */ 2134#else 2135 uint32_t ce_en : 1; 2136 uint32_t nfe_en : 1; 2137 uint32_t fe_en : 1; 2138 uint32_t ur_en : 1; 2139 uint32_t ro_en : 1; 2140 uint32_t mps : 3; 2141 uint32_t etf_en : 1; 2142 uint32_t pf_en : 1; 2143 uint32_t ap_en : 1; 2144 uint32_t ns_en : 1; 2145 uint32_t mrrs : 3; 2146 uint32_t reserved_15_15 : 1; 2147 uint32_t ce_d : 1; 2148 uint32_t nfe_d : 1; 2149 uint32_t fe_d : 1; 2150 uint32_t ur_d : 1; 2151 uint32_t ap_d : 1; 2152 uint32_t tp : 1; 2153 uint32_t reserved_22_31 : 10; 2154#endif 2155 } s; 2156 struct cvmx_pciercx_cfg030_s cn52xx; 2157 struct cvmx_pciercx_cfg030_s cn52xxp1; 2158 struct cvmx_pciercx_cfg030_s cn56xx; 2159 struct cvmx_pciercx_cfg030_s cn56xxp1; 2160 struct cvmx_pciercx_cfg030_s cn63xx; 2161 struct cvmx_pciercx_cfg030_s cn63xxp1; 2162}; 2163typedef union cvmx_pciercx_cfg030 cvmx_pciercx_cfg030_t; 2164 2165/** 2166 * cvmx_pcierc#_cfg031 2167 * 2168 * PCIE_CFG031 = Thirty-second 32-bits of PCIE type 1 config space 2169 * (Link Capabilities Register) 2170 */ 2171union cvmx_pciercx_cfg031 2172{ 2173 uint32_t u32; 2174 struct cvmx_pciercx_cfg031_s 2175 { 2176#if __BYTE_ORDER == __BIG_ENDIAN 2177 uint32_t pnum : 8; /**< Port Number, writable through PEM(0..1)_CFG_WR 2178 However, the application must not change this field. */ 2179 uint32_t reserved_22_23 : 2; 2180 uint32_t lbnc : 1; /**< Link Bandwith Notification Capability */ 2181 uint32_t dllarc : 1; /**< Data Link Layer Active Reporting Capable 2182 Set to 1 for Root Complex devices and 0 for Endpoint devices. */ 2183 uint32_t sderc : 1; /**< Surprise Down Error Reporting Capable 2184 Not supported, hardwired to 0x0. */ 2185 uint32_t cpm : 1; /**< Clock Power Management 2186 The default value is the value you specify during hardware 2187 configuration, writable through PEM(0..1)_CFG_WR. 2188 However, the application must not change this field. */ 2189 uint32_t l1el : 3; /**< L1 Exit Latency 2190 The default value is the value you specify during hardware 2191 configuration, writable through PEM(0..1)_CFG_WR. 2192 However, the application must not change this field. */ 2193 uint32_t l0el : 3; /**< L0s Exit Latency 2194 The default value is the value you specify during hardware 2195 configuration, writable through PEM(0..1)_CFG_WR. 2196 However, the application must not change this field. */ 2197 uint32_t aslpms : 2; /**< Active State Link PM Support 2198 The default value is the value you specify during hardware 2199 configuration, writable through PEM(0..1)_CFG_WR. 2200 However, the application must not change this field. */ 2201 uint32_t mlw : 6; /**< Maximum Link Width 2202 The default value is the value you specify during hardware 2203 configuration (x1, x4, x8, or x16), writable through PEM(0..1)_CFG_WR. */ 2204 uint32_t mls : 4; /**< Maximum Link Speed 2205 The following values are accepted: 2206 0001b: 2.5 GHz supported 2207 0010b: 5.0 GHz and 2.5 GHz supported 2208 This field is writable through PEM(0..1)_CFG_WR. 2209 However, the application must not change this field. */ 2210#else 2211 uint32_t mls : 4; 2212 uint32_t mlw : 6; 2213 uint32_t aslpms : 2; 2214 uint32_t l0el : 3; 2215 uint32_t l1el : 3; 2216 uint32_t cpm : 1; 2217 uint32_t sderc : 1; 2218 uint32_t dllarc : 1; 2219 uint32_t lbnc : 1; 2220 uint32_t reserved_22_23 : 2; 2221 uint32_t pnum : 8; 2222#endif 2223 } s; 2224 struct cvmx_pciercx_cfg031_s cn52xx; 2225 struct cvmx_pciercx_cfg031_s cn52xxp1; 2226 struct cvmx_pciercx_cfg031_s cn56xx; 2227 struct cvmx_pciercx_cfg031_s cn56xxp1; 2228 struct cvmx_pciercx_cfg031_s cn63xx; 2229 struct cvmx_pciercx_cfg031_s cn63xxp1; 2230}; 2231typedef union cvmx_pciercx_cfg031 cvmx_pciercx_cfg031_t; 2232 2233/** 2234 * cvmx_pcierc#_cfg032 2235 * 2236 * PCIE_CFG032 = Thirty-third 32-bits of PCIE type 1 config space 2237 * (Link Control Register/Link Status Register) 2238 */ 2239union cvmx_pciercx_cfg032 2240{ 2241 uint32_t u32; 2242 struct cvmx_pciercx_cfg032_s 2243 { 2244#if __BYTE_ORDER == __BIG_ENDIAN 2245 uint32_t lab : 1; /**< Link Autonomous Bandwidth Status */ 2246 uint32_t lbm : 1; /**< Link Bandwidth Management Status */ 2247 uint32_t dlla : 1; /**< Data Link Layer Active */ 2248 uint32_t scc : 1; /**< Slot Clock Configuration 2249 Indicates that the component uses the same physical reference 2250 clock that the platform provides on the connector. The default 2251 value is the value you select during hardware configuration, 2252 writable through PEM(0..1)_CFG_WR. 2253 However, the application must not change this field. */ 2254 uint32_t lt : 1; /**< Link Training */ 2255 uint32_t reserved_26_26 : 1; 2256 uint32_t nlw : 6; /**< Negotiated Link Width 2257 Set automatically by hardware after Link initialization. */ 2258 uint32_t ls : 4; /**< Link Speed 2259 The negotiated Link speed: 2.5 Gbps */ 2260 uint32_t reserved_12_15 : 4; 2261 uint32_t lab_int_enb : 1; /**< Link Autonomous Bandwidth Interrupt Enable 2262 This interrupt is for Gen2 and is not supported. This bit should 2263 always be written to zero. */ 2264 uint32_t lbm_int_enb : 1; /**< Link Bandwidth Management Interrupt Enable 2265 This interrupt is for Gen2 and is not supported. This bit should 2266 always be written to zero. */ 2267 uint32_t hawd : 1; /**< Hardware Autonomous Width Disable 2268 (Not Supported) */ 2269 uint32_t ecpm : 1; /**< Enable Clock Power Management 2270 Hardwired to 0 if Clock Power Management is disabled in 2271 the Link Capabilities register. */ 2272 uint32_t es : 1; /**< Extended Synch */ 2273 uint32_t ccc : 1; /**< Common Clock Configuration */ 2274 uint32_t rl : 1; /**< Retrain Link */ 2275 uint32_t ld : 1; /**< Link Disable */ 2276 uint32_t rcb : 1; /**< Read Completion Boundary (RCB), writable through PEM(0..1)_CFG_WR 2277 However, the application must not change this field 2278 because an RCB of 64 bytes is not supported. */ 2279 uint32_t reserved_2_2 : 1; 2280 uint32_t aslpc : 2; /**< Active State Link PM Control */ 2281#else 2282 uint32_t aslpc : 2; 2283 uint32_t reserved_2_2 : 1; 2284 uint32_t rcb : 1; 2285 uint32_t ld : 1; 2286 uint32_t rl : 1; 2287 uint32_t ccc : 1; 2288 uint32_t es : 1; 2289 uint32_t ecpm : 1; 2290 uint32_t hawd : 1; 2291 uint32_t lbm_int_enb : 1; 2292 uint32_t lab_int_enb : 1; 2293 uint32_t reserved_12_15 : 4; 2294 uint32_t ls : 4; 2295 uint32_t nlw : 6; 2296 uint32_t reserved_26_26 : 1; 2297 uint32_t lt : 1; 2298 uint32_t scc : 1; 2299 uint32_t dlla : 1; 2300 uint32_t lbm : 1; 2301 uint32_t lab : 1; 2302#endif 2303 } s; 2304 struct cvmx_pciercx_cfg032_s cn52xx; 2305 struct cvmx_pciercx_cfg032_s cn52xxp1; 2306 struct cvmx_pciercx_cfg032_s cn56xx; 2307 struct cvmx_pciercx_cfg032_s cn56xxp1; 2308 struct cvmx_pciercx_cfg032_s cn63xx; 2309 struct cvmx_pciercx_cfg032_s cn63xxp1; 2310}; 2311typedef union cvmx_pciercx_cfg032 cvmx_pciercx_cfg032_t; 2312 2313/** 2314 * cvmx_pcierc#_cfg033 2315 * 2316 * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 1 config space 2317 * (Slot Capabilities Register) 2318 */ 2319union cvmx_pciercx_cfg033 2320{ 2321 uint32_t u32; 2322 struct cvmx_pciercx_cfg033_s 2323 { 2324#if __BYTE_ORDER == __BIG_ENDIAN 2325 uint32_t ps_num : 13; /**< Physical Slot Number, writable through PEM(0..1)_CFG_WR 2326 However, the application must not change this field. */ 2327 uint32_t nccs : 1; /**< No Command Complete Support, writable through PEM(0..1)_CFG_WR 2328 However, the application must not change this field. */ 2329 uint32_t emip : 1; /**< Electromechanical Interlock Present, writable through PEM(0..1)_CFG_WR 2330 However, the application must not change this field. */ 2331 uint32_t sp_ls : 2; /**< Slot Power Limit Scale, writable through PEM(0..1)_CFG_WR. */ 2332 uint32_t sp_lv : 8; /**< Slot Power Limit Value, writable through PEM(0..1)_CFG_WR. */ 2333 uint32_t hp_c : 1; /**< Hot-Plug Capable, writable through PEM(0..1)_CFG_WR 2334 However, the application must not change this field. */ 2335 uint32_t hp_s : 1; /**< Hot-Plug Surprise, writable through PEM(0..1)_CFG_WR 2336 However, the application must not change this field. */ 2337 uint32_t pip : 1; /**< Power Indicator Present, writable through PEM(0..1)_CFG_WR 2338 However, the application must not change this field. */ 2339 uint32_t aip : 1; /**< Attention Indicator Present, writable through PEM(0..1)_CFG_WR 2340 However, the application must not change this field. */ 2341 uint32_t mrlsp : 1; /**< MRL Sensor Present, writable through PEM(0..1)_CFG_WR 2342 However, the application must not change this field. */ 2343 uint32_t pcp : 1; /**< Power Controller Present, writable through PEM(0..1)_CFG_WR 2344 However, the application must not change this field. */ 2345 uint32_t abp : 1; /**< Attention Button Present, writable through PEM(0..1)_CFG_WR 2346 However, the application must not change this field. */ 2347#else 2348 uint32_t abp : 1; 2349 uint32_t pcp : 1; 2350 uint32_t mrlsp : 1; 2351 uint32_t aip : 1; 2352 uint32_t pip : 1; 2353 uint32_t hp_s : 1; 2354 uint32_t hp_c : 1; 2355 uint32_t sp_lv : 8; 2356 uint32_t sp_ls : 2; 2357 uint32_t emip : 1; 2358 uint32_t nccs : 1; 2359 uint32_t ps_num : 13; 2360#endif 2361 } s; 2362 struct cvmx_pciercx_cfg033_s cn52xx; 2363 struct cvmx_pciercx_cfg033_s cn52xxp1; 2364 struct cvmx_pciercx_cfg033_s cn56xx; 2365 struct cvmx_pciercx_cfg033_s cn56xxp1; 2366 struct cvmx_pciercx_cfg033_s cn63xx; 2367 struct cvmx_pciercx_cfg033_s cn63xxp1; 2368}; 2369typedef union cvmx_pciercx_cfg033 cvmx_pciercx_cfg033_t; 2370 2371/** 2372 * cvmx_pcierc#_cfg034 2373 * 2374 * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 1 config space 2375 * (Slot Control Register/Slot Status Register) 2376 */ 2377union cvmx_pciercx_cfg034 2378{ 2379 uint32_t u32; 2380 struct cvmx_pciercx_cfg034_s 2381 { 2382#if __BYTE_ORDER == __BIG_ENDIAN 2383 uint32_t reserved_25_31 : 7; 2384 uint32_t dlls_c : 1; /**< Data Link Layer State Changed */ 2385 uint32_t emis : 1; /**< Electromechanical Interlock Status */ 2386 uint32_t pds : 1; /**< Presence Detect State */ 2387 uint32_t mrlss : 1; /**< MRL Sensor State */ 2388 uint32_t ccint_d : 1; /**< Command Completed */ 2389 uint32_t pd_c : 1; /**< Presence Detect Changed */ 2390 uint32_t mrls_c : 1; /**< MRL Sensor Changed */ 2391 uint32_t pf_d : 1; /**< Power Fault Detected */ 2392 uint32_t abp_d : 1; /**< Attention Button Pressed */ 2393 uint32_t reserved_13_15 : 3; 2394 uint32_t dlls_en : 1; /**< Data Link Layer State Changed Enable */ 2395 uint32_t emic : 1; /**< Electromechanical Interlock Control */ 2396 uint32_t pcc : 1; /**< Power Controller Control */ 2397 uint32_t pic : 2; /**< Power Indicator Control */ 2398 uint32_t aic : 2; /**< Attention Indicator Control */ 2399 uint32_t hpint_en : 1; /**< Hot-Plug Interrupt Enable */ 2400 uint32_t ccint_en : 1; /**< Command Completed Interrupt Enable */ 2401 uint32_t pd_en : 1; /**< Presence Detect Changed Enable */ 2402 uint32_t mrls_en : 1; /**< MRL Sensor Changed Enable */ 2403 uint32_t pf_en : 1; /**< Power Fault Detected Enable */ 2404 uint32_t abp_en : 1; /**< Attention Button Pressed Enable */ 2405#else 2406 uint32_t abp_en : 1; 2407 uint32_t pf_en : 1; 2408 uint32_t mrls_en : 1; 2409 uint32_t pd_en : 1; 2410 uint32_t ccint_en : 1; 2411 uint32_t hpint_en : 1; 2412 uint32_t aic : 2; 2413 uint32_t pic : 2; 2414 uint32_t pcc : 1; 2415 uint32_t emic : 1; 2416 uint32_t dlls_en : 1; 2417 uint32_t reserved_13_15 : 3; 2418 uint32_t abp_d : 1; 2419 uint32_t pf_d : 1; 2420 uint32_t mrls_c : 1; 2421 uint32_t pd_c : 1; 2422 uint32_t ccint_d : 1; 2423 uint32_t mrlss : 1; 2424 uint32_t pds : 1; 2425 uint32_t emis : 1; 2426 uint32_t dlls_c : 1; 2427 uint32_t reserved_25_31 : 7; 2428#endif 2429 } s; 2430 struct cvmx_pciercx_cfg034_s cn52xx; 2431 struct cvmx_pciercx_cfg034_s cn52xxp1; 2432 struct cvmx_pciercx_cfg034_s cn56xx; 2433 struct cvmx_pciercx_cfg034_s cn56xxp1; 2434 struct cvmx_pciercx_cfg034_s cn63xx; 2435 struct cvmx_pciercx_cfg034_s cn63xxp1; 2436}; 2437typedef union cvmx_pciercx_cfg034 cvmx_pciercx_cfg034_t; 2438 2439/** 2440 * cvmx_pcierc#_cfg035 2441 * 2442 * PCIE_CFG035 = Thirty-sixth 32-bits of PCIE type 1 config space 2443 * (Root Control Register/Root Capabilities Register) 2444 */ 2445union cvmx_pciercx_cfg035 2446{ 2447 uint32_t u32; 2448 struct cvmx_pciercx_cfg035_s 2449 { 2450#if __BYTE_ORDER == __BIG_ENDIAN 2451 uint32_t reserved_17_31 : 15; 2452 uint32_t crssv : 1; /**< CRS Software Visibility 2453 Not supported, hardwired to 0x0. */ 2454 uint32_t reserved_5_15 : 11; 2455 uint32_t crssve : 1; /**< CRS Software Visibility Enable 2456 Not supported, hardwired to 0x0. */ 2457 uint32_t pmeie : 1; /**< PME Interrupt Enable */ 2458 uint32_t sefee : 1; /**< System Error on Fatal Error Enable */ 2459 uint32_t senfee : 1; /**< System Error on Non-fatal Error Enable */ 2460 uint32_t secee : 1; /**< System Error on Correctable Error Enable */ 2461#else 2462 uint32_t secee : 1; 2463 uint32_t senfee : 1; 2464 uint32_t sefee : 1; 2465 uint32_t pmeie : 1; 2466 uint32_t crssve : 1; 2467 uint32_t reserved_5_15 : 11; 2468 uint32_t crssv : 1; 2469 uint32_t reserved_17_31 : 15; 2470#endif 2471 } s; 2472 struct cvmx_pciercx_cfg035_s cn52xx; 2473 struct cvmx_pciercx_cfg035_s cn52xxp1; 2474 struct cvmx_pciercx_cfg035_s cn56xx; 2475 struct cvmx_pciercx_cfg035_s cn56xxp1; 2476 struct cvmx_pciercx_cfg035_s cn63xx; 2477 struct cvmx_pciercx_cfg035_s cn63xxp1; 2478}; 2479typedef union cvmx_pciercx_cfg035 cvmx_pciercx_cfg035_t; 2480 2481/** 2482 * cvmx_pcierc#_cfg036 2483 * 2484 * PCIE_CFG036 = Thirty-seventh 32-bits of PCIE type 1 config space 2485 * (Root Status Register) 2486 */ 2487union cvmx_pciercx_cfg036 2488{ 2489 uint32_t u32; 2490 struct cvmx_pciercx_cfg036_s 2491 { 2492#if __BYTE_ORDER == __BIG_ENDIAN 2493 uint32_t reserved_18_31 : 14; 2494 uint32_t pme_pend : 1; /**< PME Pending */ 2495 uint32_t pme_stat : 1; /**< PME Status */ 2496 uint32_t pme_rid : 16; /**< PME Requester ID */ 2497#else 2498 uint32_t pme_rid : 16; 2499 uint32_t pme_stat : 1; 2500 uint32_t pme_pend : 1; 2501 uint32_t reserved_18_31 : 14; 2502#endif 2503 } s; 2504 struct cvmx_pciercx_cfg036_s cn52xx; 2505 struct cvmx_pciercx_cfg036_s cn52xxp1; 2506 struct cvmx_pciercx_cfg036_s cn56xx; 2507 struct cvmx_pciercx_cfg036_s cn56xxp1; 2508 struct cvmx_pciercx_cfg036_s cn63xx; 2509 struct cvmx_pciercx_cfg036_s cn63xxp1; 2510}; 2511typedef union cvmx_pciercx_cfg036 cvmx_pciercx_cfg036_t; 2512 2513/** 2514 * cvmx_pcierc#_cfg037 2515 * 2516 * PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 1 config space 2517 * (Device Capabilities 2 Register) 2518 */ 2519union cvmx_pciercx_cfg037 2520{ 2521 uint32_t u32; 2522 struct cvmx_pciercx_cfg037_s 2523 { 2524#if __BYTE_ORDER == __BIG_ENDIAN 2525 uint32_t reserved_5_31 : 27; 2526 uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 2527 uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported 2528 Value of 0 indicates that Completion Timeout Programming 2529 is not supported 2530 Completion timeout is 16.7ms. */ 2531#else 2532 uint32_t ctrs : 4; 2533 uint32_t ctds : 1; 2534 uint32_t reserved_5_31 : 27; 2535#endif 2536 } s; 2537 struct cvmx_pciercx_cfg037_s cn52xx; 2538 struct cvmx_pciercx_cfg037_s cn52xxp1; 2539 struct cvmx_pciercx_cfg037_s cn56xx; 2540 struct cvmx_pciercx_cfg037_s cn56xxp1; 2541 struct cvmx_pciercx_cfg037_s cn63xx; 2542 struct cvmx_pciercx_cfg037_s cn63xxp1; 2543}; 2544typedef union cvmx_pciercx_cfg037 cvmx_pciercx_cfg037_t; 2545 2546/** 2547 * cvmx_pcierc#_cfg038 2548 * 2549 * PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 1 config space 2550 * (Device Control 2 Register) 2551 */ 2552union cvmx_pciercx_cfg038 2553{ 2554 uint32_t u32; 2555 struct cvmx_pciercx_cfg038_s 2556 { 2557#if __BYTE_ORDER == __BIG_ENDIAN 2558 uint32_t reserved_5_31 : 27; 2559 uint32_t ctd : 1; /**< Completion Timeout Disable */ 2560 uint32_t ctv : 4; /**< Completion Timeout Value 2561 Completion Timeout Programming is not supported 2562 Completion timeout is 16.7ms. */ 2563#else 2564 uint32_t ctv : 4; 2565 uint32_t ctd : 1; 2566 uint32_t reserved_5_31 : 27; 2567#endif 2568 } s; 2569 struct cvmx_pciercx_cfg038_s cn52xx; 2570 struct cvmx_pciercx_cfg038_s cn52xxp1; 2571 struct cvmx_pciercx_cfg038_s cn56xx; 2572 struct cvmx_pciercx_cfg038_s cn56xxp1; 2573 struct cvmx_pciercx_cfg038_s cn63xx; 2574 struct cvmx_pciercx_cfg038_s cn63xxp1; 2575}; 2576typedef union cvmx_pciercx_cfg038 cvmx_pciercx_cfg038_t; 2577 2578/** 2579 * cvmx_pcierc#_cfg039 2580 * 2581 * PCIE_CFG039 = Fourtieth 32-bits of PCIE type 1 config space 2582 * (Link Capabilities 2 Register) 2583 */ 2584union cvmx_pciercx_cfg039 2585{ 2586 uint32_t u32; 2587 struct cvmx_pciercx_cfg039_s 2588 { 2589#if __BYTE_ORDER == __BIG_ENDIAN 2590 uint32_t reserved_0_31 : 32; 2591#else 2592 uint32_t reserved_0_31 : 32; 2593#endif 2594 } s; 2595 struct cvmx_pciercx_cfg039_s cn52xx; 2596 struct cvmx_pciercx_cfg039_s cn52xxp1; 2597 struct cvmx_pciercx_cfg039_s cn56xx; 2598 struct cvmx_pciercx_cfg039_s cn56xxp1; 2599 struct cvmx_pciercx_cfg039_s cn63xx; 2600 struct cvmx_pciercx_cfg039_s cn63xxp1; 2601}; 2602typedef union cvmx_pciercx_cfg039 cvmx_pciercx_cfg039_t; 2603 2604/** 2605 * cvmx_pcierc#_cfg040 2606 * 2607 * PCIE_CFG040 = Fourty-first 32-bits of PCIE type 1 config space 2608 * (Link Control 2 Register/Link Status 2 Register) 2609 */ 2610union cvmx_pciercx_cfg040 2611{ 2612 uint32_t u32; 2613 struct cvmx_pciercx_cfg040_s 2614 { 2615#if __BYTE_ORDER == __BIG_ENDIAN 2616 uint32_t reserved_17_31 : 15; 2617 uint32_t cdl : 1; /**< Current De-emphasis Level 2618 When the Link is operating at 5 GT/s speed, this bit 2619 reflects the level of de-emphasis. Encodings: 2620 1b: -3.5 dB 2621 0b: -6 dB 2622 Note: The value in this bit is undefined when the Link is 2623 operating at 2.5 GT/s speed */ 2624 uint32_t reserved_13_15 : 3; 2625 uint32_t cde : 1; /**< Compliance De-emphasis 2626 This bit sets the de-emphasis level in Polling. Compliance 2627 state if the entry occurred due to the Tx Compliance 2628 Receive bit being 1b. Encodings: 2629 1b: -3.5 dB 2630 0b: -6 dB 2631 Note: When the Link is operating at 2.5 GT/s, the setting 2632 of this bit has no effect. */ 2633 uint32_t csos : 1; /**< Compliance SOS 2634 When set to 1b, the LTSSM is required to send SKP 2635 Ordered Sets periodically in between the (modified) 2636 compliance patterns. 2637 Note: When the Link is operating at 2.5 GT/s, the setting 2638 of this bit has no effect. */ 2639 uint32_t emc : 1; /**< Enter Modified Compliance 2640 When this bit is set to 1b, the device transmits a modified 2641 compliance pattern if the LTSSM enters Polling. 2642 Compliance state. */ 2643 uint32_t tm : 3; /**< Transmit Margin 2644 This field controls the value of the non-de-emphasized 2645 voltage level at the Transmitter pins: 2646 - 000: 800-1200 mV for full swing 400-600 mV for half-swing 2647 - 001-010: values must be monotonic with a non-zero slope 2648 - 011: 200-400 mV for full-swing and 100-200 mV for halfswing 2649 - 100-111: reserved 2650 This field is reset to 000b on entry to the LTSSM Polling. 2651 Compliance substate. 2652 When operating in 5.0 GT/s mode with full swing, the 2653 de-emphasis ratio must be maintained within +/- 1 dB 2654 from the specification-defined operational value 2655 either -3.5 or -6 dB). */ 2656 uint32_t sde : 1; /**< Selectable De-emphasis 2657 When the Link is operating at 5.0 GT/s speed, selects the 2658 level of de-emphasis: 2659 - 1: -3.5 dB 2660 - 0: -6 dB 2661 When the Link is operating at 2.5 GT/s speed, the setting 2662 of this bit has no effect. */ 2663 uint32_t hasd : 1; /**< Hardware Autonomous Speed Disable 2664 When asserted, the 2665 application must disable hardware from changing the Link 2666 speed for device-specific reasons other than attempting to 2667 correct unreliable Link operation by reducing Link speed. 2668 Initial transition to the highest supported common link 2669 speed is not blocked by this signal. */ 2670 uint32_t ec : 1; /**< Enter Compliance 2671 Software is permitted to force a link to enter Compliance 2672 mode at the speed indicated in the Target Link Speed 2673 field by setting this bit to 1b in both components on a link 2674 and then initiating a hot reset on the link. */ 2675 uint32_t tls : 4; /**< Target Link Speed 2676 For Downstream ports, this field sets an upper limit on link 2677 operational speed by restricting the values advertised by 2678 the upstream component in its training sequences: 2679 - 0001: 2.5Gb/s Target Link Speed 2680 - 0010: 5Gb/s Target Link Speed 2681 All other encodings are reserved. 2682 If a value is written to this field that does not correspond to 2683 a speed included in the Supported Link Speeds field, the 2684 result is undefined. 2685 For both Upstream and Downstream ports, this field is 2686 used to set the target compliance mode speed when 2687 software is using the Enter Compliance bit to force a link 2688 into compliance mode. 2689 Out of reset this will have a value of 1 or 2 which is 2690 selected by qlmCfgx[1]. */ 2691#else 2692 uint32_t tls : 4; 2693 uint32_t ec : 1; 2694 uint32_t hasd : 1; 2695 uint32_t sde : 1; 2696 uint32_t tm : 3; 2697 uint32_t emc : 1; 2698 uint32_t csos : 1; 2699 uint32_t cde : 1; 2700 uint32_t reserved_13_15 : 3; 2701 uint32_t cdl : 1; 2702 uint32_t reserved_17_31 : 15; 2703#endif 2704 } s; 2705 struct cvmx_pciercx_cfg040_cn52xx 2706 { 2707#if __BYTE_ORDER == __BIG_ENDIAN 2708 uint32_t reserved_0_31 : 32; 2709#else 2710 uint32_t reserved_0_31 : 32; 2711#endif 2712 } cn52xx; 2713 struct cvmx_pciercx_cfg040_cn52xx cn52xxp1; 2714 struct cvmx_pciercx_cfg040_cn52xx cn56xx; 2715 struct cvmx_pciercx_cfg040_cn52xx cn56xxp1; 2716 struct cvmx_pciercx_cfg040_s cn63xx; 2717 struct cvmx_pciercx_cfg040_s cn63xxp1; 2718}; 2719typedef union cvmx_pciercx_cfg040 cvmx_pciercx_cfg040_t; 2720 2721/** 2722 * cvmx_pcierc#_cfg041 2723 * 2724 * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 1 config space 2725 * (Slot Capabilities 2 Register) 2726 */ 2727union cvmx_pciercx_cfg041 2728{ 2729 uint32_t u32; 2730 struct cvmx_pciercx_cfg041_s 2731 { 2732#if __BYTE_ORDER == __BIG_ENDIAN 2733 uint32_t reserved_0_31 : 32; 2734#else 2735 uint32_t reserved_0_31 : 32; 2736#endif 2737 } s; 2738 struct cvmx_pciercx_cfg041_s cn52xx; 2739 struct cvmx_pciercx_cfg041_s cn52xxp1; 2740 struct cvmx_pciercx_cfg041_s cn56xx; 2741 struct cvmx_pciercx_cfg041_s cn56xxp1; 2742 struct cvmx_pciercx_cfg041_s cn63xx; 2743 struct cvmx_pciercx_cfg041_s cn63xxp1; 2744}; 2745typedef union cvmx_pciercx_cfg041 cvmx_pciercx_cfg041_t; 2746 2747/** 2748 * cvmx_pcierc#_cfg042 2749 * 2750 * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 1 config space 2751 * (Slot Control 2 Register/Slot Status 2 Register) 2752 */ 2753union cvmx_pciercx_cfg042 2754{ 2755 uint32_t u32; 2756 struct cvmx_pciercx_cfg042_s 2757 { 2758#if __BYTE_ORDER == __BIG_ENDIAN 2759 uint32_t reserved_0_31 : 32; 2760#else 2761 uint32_t reserved_0_31 : 32; 2762#endif 2763 } s; 2764 struct cvmx_pciercx_cfg042_s cn52xx; 2765 struct cvmx_pciercx_cfg042_s cn52xxp1; 2766 struct cvmx_pciercx_cfg042_s cn56xx; 2767 struct cvmx_pciercx_cfg042_s cn56xxp1; 2768 struct cvmx_pciercx_cfg042_s cn63xx; 2769 struct cvmx_pciercx_cfg042_s cn63xxp1; 2770}; 2771typedef union cvmx_pciercx_cfg042 cvmx_pciercx_cfg042_t; 2772 2773/** 2774 * cvmx_pcierc#_cfg064 2775 * 2776 * PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 1 config space 2777 * (PCI Express Enhanced Capability Header) 2778 */ 2779union cvmx_pciercx_cfg064 2780{ 2781 uint32_t u32; 2782 struct cvmx_pciercx_cfg064_s 2783 { 2784#if __BYTE_ORDER == __BIG_ENDIAN 2785 uint32_t nco : 12; /**< Next Capability Offset */ 2786 uint32_t cv : 4; /**< Capability Version */ 2787 uint32_t pcieec : 16; /**< PCIE Express Extended Capability */ 2788#else 2789 uint32_t pcieec : 16; 2790 uint32_t cv : 4; 2791 uint32_t nco : 12; 2792#endif 2793 } s; 2794 struct cvmx_pciercx_cfg064_s cn52xx; 2795 struct cvmx_pciercx_cfg064_s cn52xxp1; 2796 struct cvmx_pciercx_cfg064_s cn56xx; 2797 struct cvmx_pciercx_cfg064_s cn56xxp1; 2798 struct cvmx_pciercx_cfg064_s cn63xx; 2799 struct cvmx_pciercx_cfg064_s cn63xxp1; 2800}; 2801typedef union cvmx_pciercx_cfg064 cvmx_pciercx_cfg064_t; 2802 2803/** 2804 * cvmx_pcierc#_cfg065 2805 * 2806 * PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 1 config space 2807 * (Uncorrectable Error Status Register) 2808 */ 2809union cvmx_pciercx_cfg065 2810{ 2811 uint32_t u32; 2812 struct cvmx_pciercx_cfg065_s 2813 { 2814#if __BYTE_ORDER == __BIG_ENDIAN 2815 uint32_t reserved_21_31 : 11; 2816 uint32_t ures : 1; /**< Unsupported Request Error Status */ 2817 uint32_t ecrces : 1; /**< ECRC Error Status */ 2818 uint32_t mtlps : 1; /**< Malformed TLP Status */ 2819 uint32_t ros : 1; /**< Receiver Overflow Status */ 2820 uint32_t ucs : 1; /**< Unexpected Completion Status */ 2821 uint32_t cas : 1; /**< Completer Abort Status */ 2822 uint32_t cts : 1; /**< Completion Timeout Status */ 2823 uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 2824 uint32_t ptlps : 1; /**< Poisoned TLP Status */ 2825 uint32_t reserved_6_11 : 6; 2826 uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */ 2827 uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 2828 uint32_t reserved_0_3 : 4; 2829#else 2830 uint32_t reserved_0_3 : 4; 2831 uint32_t dlpes : 1; 2832 uint32_t sdes : 1; 2833 uint32_t reserved_6_11 : 6; 2834 uint32_t ptlps : 1; 2835 uint32_t fcpes : 1; 2836 uint32_t cts : 1; 2837 uint32_t cas : 1; 2838 uint32_t ucs : 1; 2839 uint32_t ros : 1; 2840 uint32_t mtlps : 1; 2841 uint32_t ecrces : 1; 2842 uint32_t ures : 1; 2843 uint32_t reserved_21_31 : 11; 2844#endif 2845 } s; 2846 struct cvmx_pciercx_cfg065_s cn52xx; 2847 struct cvmx_pciercx_cfg065_s cn52xxp1; 2848 struct cvmx_pciercx_cfg065_s cn56xx; 2849 struct cvmx_pciercx_cfg065_s cn56xxp1; 2850 struct cvmx_pciercx_cfg065_s cn63xx; 2851 struct cvmx_pciercx_cfg065_s cn63xxp1; 2852}; 2853typedef union cvmx_pciercx_cfg065 cvmx_pciercx_cfg065_t; 2854 2855/** 2856 * cvmx_pcierc#_cfg066 2857 * 2858 * PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 1 config space 2859 * (Uncorrectable Error Mask Register) 2860 */ 2861union cvmx_pciercx_cfg066 2862{ 2863 uint32_t u32; 2864 struct cvmx_pciercx_cfg066_s 2865 { 2866#if __BYTE_ORDER == __BIG_ENDIAN 2867 uint32_t reserved_21_31 : 11; 2868 uint32_t urem : 1; /**< Unsupported Request Error Mask */ 2869 uint32_t ecrcem : 1; /**< ECRC Error Mask */ 2870 uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 2871 uint32_t rom : 1; /**< Receiver Overflow Mask */ 2872 uint32_t ucm : 1; /**< Unexpected Completion Mask */ 2873 uint32_t cam : 1; /**< Completer Abort Mask */ 2874 uint32_t ctm : 1; /**< Completion Timeout Mask */ 2875 uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 2876 uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 2877 uint32_t reserved_6_11 : 6; 2878 uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */ 2879 uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 2880 uint32_t reserved_0_3 : 4; 2881#else 2882 uint32_t reserved_0_3 : 4; 2883 uint32_t dlpem : 1; 2884 uint32_t sdem : 1; 2885 uint32_t reserved_6_11 : 6; 2886 uint32_t ptlpm : 1; 2887 uint32_t fcpem : 1; 2888 uint32_t ctm : 1; 2889 uint32_t cam : 1; 2890 uint32_t ucm : 1; 2891 uint32_t rom : 1; 2892 uint32_t mtlpm : 1; 2893 uint32_t ecrcem : 1; 2894 uint32_t urem : 1; 2895 uint32_t reserved_21_31 : 11; 2896#endif 2897 } s; 2898 struct cvmx_pciercx_cfg066_s cn52xx; 2899 struct cvmx_pciercx_cfg066_s cn52xxp1; 2900 struct cvmx_pciercx_cfg066_s cn56xx; 2901 struct cvmx_pciercx_cfg066_s cn56xxp1; 2902 struct cvmx_pciercx_cfg066_s cn63xx; 2903 struct cvmx_pciercx_cfg066_s cn63xxp1; 2904}; 2905typedef union cvmx_pciercx_cfg066 cvmx_pciercx_cfg066_t; 2906 2907/** 2908 * cvmx_pcierc#_cfg067 2909 * 2910 * PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 1 config space 2911 * (Uncorrectable Error Severity Register) 2912 */ 2913union cvmx_pciercx_cfg067 2914{ 2915 uint32_t u32; 2916 struct cvmx_pciercx_cfg067_s 2917 { 2918#if __BYTE_ORDER == __BIG_ENDIAN 2919 uint32_t reserved_21_31 : 11; 2920 uint32_t ures : 1; /**< Unsupported Request Error Severity */ 2921 uint32_t ecrces : 1; /**< ECRC Error Severity */ 2922 uint32_t mtlps : 1; /**< Malformed TLP Severity */ 2923 uint32_t ros : 1; /**< Receiver Overflow Severity */ 2924 uint32_t ucs : 1; /**< Unexpected Completion Severity */ 2925 uint32_t cas : 1; /**< Completer Abort Severity */ 2926 uint32_t cts : 1; /**< Completion Timeout Severity */ 2927 uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 2928 uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 2929 uint32_t reserved_6_11 : 6; 2930 uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */ 2931 uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 2932 uint32_t reserved_0_3 : 4; 2933#else 2934 uint32_t reserved_0_3 : 4; 2935 uint32_t dlpes : 1; 2936 uint32_t sdes : 1; 2937 uint32_t reserved_6_11 : 6; 2938 uint32_t ptlps : 1; 2939 uint32_t fcpes : 1; 2940 uint32_t cts : 1; 2941 uint32_t cas : 1; 2942 uint32_t ucs : 1; 2943 uint32_t ros : 1; 2944 uint32_t mtlps : 1; 2945 uint32_t ecrces : 1; 2946 uint32_t ures : 1; 2947 uint32_t reserved_21_31 : 11; 2948#endif 2949 } s; 2950 struct cvmx_pciercx_cfg067_s cn52xx; 2951 struct cvmx_pciercx_cfg067_s cn52xxp1; 2952 struct cvmx_pciercx_cfg067_s cn56xx; 2953 struct cvmx_pciercx_cfg067_s cn56xxp1; 2954 struct cvmx_pciercx_cfg067_s cn63xx; 2955 struct cvmx_pciercx_cfg067_s cn63xxp1; 2956}; 2957typedef union cvmx_pciercx_cfg067 cvmx_pciercx_cfg067_t; 2958 2959/** 2960 * cvmx_pcierc#_cfg068 2961 * 2962 * PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 1 config space 2963 * (Correctable Error Status Register) 2964 */ 2965union cvmx_pciercx_cfg068 2966{ 2967 uint32_t u32; 2968 struct cvmx_pciercx_cfg068_s 2969 { 2970#if __BYTE_ORDER == __BIG_ENDIAN 2971 uint32_t reserved_14_31 : 18; 2972 uint32_t anfes : 1; /**< Advisory Non-Fatal Error Status */ 2973 uint32_t rtts : 1; /**< Replay Timer Timeout Status */ 2974 uint32_t reserved_9_11 : 3; 2975 uint32_t rnrs : 1; /**< REPLAY_NUM Rollover Status */ 2976 uint32_t bdllps : 1; /**< Bad DLLP Status */ 2977 uint32_t btlps : 1; /**< Bad TLP Status */ 2978 uint32_t reserved_1_5 : 5; 2979 uint32_t res : 1; /**< Receiver Error Status */ 2980#else 2981 uint32_t res : 1; 2982 uint32_t reserved_1_5 : 5; 2983 uint32_t btlps : 1; 2984 uint32_t bdllps : 1; 2985 uint32_t rnrs : 1; 2986 uint32_t reserved_9_11 : 3; 2987 uint32_t rtts : 1; 2988 uint32_t anfes : 1; 2989 uint32_t reserved_14_31 : 18; 2990#endif 2991 } s; 2992 struct cvmx_pciercx_cfg068_s cn52xx; 2993 struct cvmx_pciercx_cfg068_s cn52xxp1; 2994 struct cvmx_pciercx_cfg068_s cn56xx; 2995 struct cvmx_pciercx_cfg068_s cn56xxp1; 2996 struct cvmx_pciercx_cfg068_s cn63xx; 2997 struct cvmx_pciercx_cfg068_s cn63xxp1; 2998}; 2999typedef union cvmx_pciercx_cfg068 cvmx_pciercx_cfg068_t; 3000 3001/** 3002 * cvmx_pcierc#_cfg069 3003 * 3004 * PCIE_CFG069 = Seventieth 32-bits of PCIE type 1 config space 3005 * (Correctable Error Mask Register) 3006 */ 3007union cvmx_pciercx_cfg069 3008{ 3009 uint32_t u32; 3010 struct cvmx_pciercx_cfg069_s 3011 { 3012#if __BYTE_ORDER == __BIG_ENDIAN 3013 uint32_t reserved_14_31 : 18; 3014 uint32_t anfem : 1; /**< Advisory Non-Fatal Error Mask */ 3015 uint32_t rttm : 1; /**< Replay Timer Timeout Mask */ 3016 uint32_t reserved_9_11 : 3; 3017 uint32_t rnrm : 1; /**< REPLAY_NUM Rollover Mask */ 3018 uint32_t bdllpm : 1; /**< Bad DLLP Mask */ 3019 uint32_t btlpm : 1; /**< Bad TLP Mask */ 3020 uint32_t reserved_1_5 : 5; 3021 uint32_t rem : 1; /**< Receiver Error Mask */ 3022#else 3023 uint32_t rem : 1; 3024 uint32_t reserved_1_5 : 5; 3025 uint32_t btlpm : 1; 3026 uint32_t bdllpm : 1; 3027 uint32_t rnrm : 1; 3028 uint32_t reserved_9_11 : 3; 3029 uint32_t rttm : 1; 3030 uint32_t anfem : 1; 3031 uint32_t reserved_14_31 : 18; 3032#endif 3033 } s; 3034 struct cvmx_pciercx_cfg069_s cn52xx; 3035 struct cvmx_pciercx_cfg069_s cn52xxp1; 3036 struct cvmx_pciercx_cfg069_s cn56xx; 3037 struct cvmx_pciercx_cfg069_s cn56xxp1; 3038 struct cvmx_pciercx_cfg069_s cn63xx; 3039 struct cvmx_pciercx_cfg069_s cn63xxp1; 3040}; 3041typedef union cvmx_pciercx_cfg069 cvmx_pciercx_cfg069_t; 3042 3043/** 3044 * cvmx_pcierc#_cfg070 3045 * 3046 * PCIE_CFG070 = Seventy-first 32-bits of PCIE type 1 config space 3047 * (Advanced Capabilities and Control Register) 3048 */ 3049union cvmx_pciercx_cfg070 3050{ 3051 uint32_t u32; 3052 struct cvmx_pciercx_cfg070_s 3053 { 3054#if __BYTE_ORDER == __BIG_ENDIAN 3055 uint32_t reserved_9_31 : 23; 3056 uint32_t ce : 1; /**< ECRC Check Enable */ 3057 uint32_t cc : 1; /**< ECRC Check Capable */ 3058 uint32_t ge : 1; /**< ECRC Generation Enable */ 3059 uint32_t gc : 1; /**< ECRC Generation Capability */ 3060 uint32_t fep : 5; /**< First Error Pointer */ 3061#else 3062 uint32_t fep : 5; 3063 uint32_t gc : 1; 3064 uint32_t ge : 1; 3065 uint32_t cc : 1; 3066 uint32_t ce : 1; 3067 uint32_t reserved_9_31 : 23; 3068#endif 3069 } s; 3070 struct cvmx_pciercx_cfg070_s cn52xx; 3071 struct cvmx_pciercx_cfg070_s cn52xxp1; 3072 struct cvmx_pciercx_cfg070_s cn56xx; 3073 struct cvmx_pciercx_cfg070_s cn56xxp1; 3074 struct cvmx_pciercx_cfg070_s cn63xx; 3075 struct cvmx_pciercx_cfg070_s cn63xxp1; 3076}; 3077typedef union cvmx_pciercx_cfg070 cvmx_pciercx_cfg070_t; 3078 3079/** 3080 * cvmx_pcierc#_cfg071 3081 * 3082 * PCIE_CFG071 = Seventy-second 32-bits of PCIE type 1 config space 3083 * (Header Log Register 1) 3084 * 3085 * The Header Log registers collect the header for the TLP corresponding to a detected error. 3086 */ 3087union cvmx_pciercx_cfg071 3088{ 3089 uint32_t u32; 3090 struct cvmx_pciercx_cfg071_s 3091 { 3092#if __BYTE_ORDER == __BIG_ENDIAN 3093 uint32_t dword1 : 32; /**< Header Log Register (first DWORD) */ 3094#else 3095 uint32_t dword1 : 32; 3096#endif 3097 } s; 3098 struct cvmx_pciercx_cfg071_s cn52xx; 3099 struct cvmx_pciercx_cfg071_s cn52xxp1; 3100 struct cvmx_pciercx_cfg071_s cn56xx; 3101 struct cvmx_pciercx_cfg071_s cn56xxp1; 3102 struct cvmx_pciercx_cfg071_s cn63xx; 3103 struct cvmx_pciercx_cfg071_s cn63xxp1; 3104}; 3105typedef union cvmx_pciercx_cfg071 cvmx_pciercx_cfg071_t; 3106 3107/** 3108 * cvmx_pcierc#_cfg072 3109 * 3110 * PCIE_CFG072 = Seventy-third 32-bits of PCIE type 1 config space 3111 * (Header Log Register 2) 3112 * 3113 * The Header Log registers collect the header for the TLP corresponding to a detected error. 3114 */ 3115union cvmx_pciercx_cfg072 3116{ 3117 uint32_t u32; 3118 struct cvmx_pciercx_cfg072_s 3119 { 3120#if __BYTE_ORDER == __BIG_ENDIAN 3121 uint32_t dword2 : 32; /**< Header Log Register (second DWORD) */ 3122#else 3123 uint32_t dword2 : 32; 3124#endif 3125 } s; 3126 struct cvmx_pciercx_cfg072_s cn52xx; 3127 struct cvmx_pciercx_cfg072_s cn52xxp1; 3128 struct cvmx_pciercx_cfg072_s cn56xx; 3129 struct cvmx_pciercx_cfg072_s cn56xxp1; 3130 struct cvmx_pciercx_cfg072_s cn63xx; 3131 struct cvmx_pciercx_cfg072_s cn63xxp1; 3132}; 3133typedef union cvmx_pciercx_cfg072 cvmx_pciercx_cfg072_t; 3134 3135/** 3136 * cvmx_pcierc#_cfg073 3137 * 3138 * PCIE_CFG073 = Seventy-fourth 32-bits of PCIE type 1 config space 3139 * (Header Log Register 3) 3140 * 3141 * The Header Log registers collect the header for the TLP corresponding to a detected error. 3142 */ 3143union cvmx_pciercx_cfg073 3144{ 3145 uint32_t u32; 3146 struct cvmx_pciercx_cfg073_s 3147 { 3148#if __BYTE_ORDER == __BIG_ENDIAN 3149 uint32_t dword3 : 32; /**< Header Log Register (third DWORD) */ 3150#else 3151 uint32_t dword3 : 32; 3152#endif 3153 } s; 3154 struct cvmx_pciercx_cfg073_s cn52xx; 3155 struct cvmx_pciercx_cfg073_s cn52xxp1; 3156 struct cvmx_pciercx_cfg073_s cn56xx; 3157 struct cvmx_pciercx_cfg073_s cn56xxp1; 3158 struct cvmx_pciercx_cfg073_s cn63xx; 3159 struct cvmx_pciercx_cfg073_s cn63xxp1; 3160}; 3161typedef union cvmx_pciercx_cfg073 cvmx_pciercx_cfg073_t; 3162 3163/** 3164 * cvmx_pcierc#_cfg074 3165 * 3166 * PCIE_CFG074 = Seventy-fifth 32-bits of PCIE type 1 config space 3167 * (Header Log Register 4) 3168 * 3169 * The Header Log registers collect the header for the TLP corresponding to a detected error. 3170 */ 3171union cvmx_pciercx_cfg074 3172{ 3173 uint32_t u32; 3174 struct cvmx_pciercx_cfg074_s 3175 { 3176#if __BYTE_ORDER == __BIG_ENDIAN 3177 uint32_t dword4 : 32; /**< Header Log Register (fourth DWORD) */ 3178#else 3179 uint32_t dword4 : 32; 3180#endif 3181 } s; 3182 struct cvmx_pciercx_cfg074_s cn52xx; 3183 struct cvmx_pciercx_cfg074_s cn52xxp1; 3184 struct cvmx_pciercx_cfg074_s cn56xx; 3185 struct cvmx_pciercx_cfg074_s cn56xxp1; 3186 struct cvmx_pciercx_cfg074_s cn63xx; 3187 struct cvmx_pciercx_cfg074_s cn63xxp1; 3188}; 3189typedef union cvmx_pciercx_cfg074 cvmx_pciercx_cfg074_t; 3190 3191/** 3192 * cvmx_pcierc#_cfg075 3193 * 3194 * PCIE_CFG075 = Seventy-sixth 32-bits of PCIE type 1 config space 3195 * (Root Error Command Register) 3196 */ 3197union cvmx_pciercx_cfg075 3198{ 3199 uint32_t u32; 3200 struct cvmx_pciercx_cfg075_s 3201 { 3202#if __BYTE_ORDER == __BIG_ENDIAN 3203 uint32_t reserved_3_31 : 29; 3204 uint32_t fere : 1; /**< Fatal Error Reporting Enable */ 3205 uint32_t nfere : 1; /**< Non-Fatal Error Reporting Enable */ 3206 uint32_t cere : 1; /**< Correctable Error Reporting Enable */ 3207#else 3208 uint32_t cere : 1; 3209 uint32_t nfere : 1; 3210 uint32_t fere : 1; 3211 uint32_t reserved_3_31 : 29; 3212#endif 3213 } s; 3214 struct cvmx_pciercx_cfg075_s cn52xx; 3215 struct cvmx_pciercx_cfg075_s cn52xxp1; 3216 struct cvmx_pciercx_cfg075_s cn56xx; 3217 struct cvmx_pciercx_cfg075_s cn56xxp1; 3218 struct cvmx_pciercx_cfg075_s cn63xx; 3219 struct cvmx_pciercx_cfg075_s cn63xxp1; 3220}; 3221typedef union cvmx_pciercx_cfg075 cvmx_pciercx_cfg075_t; 3222 3223/** 3224 * cvmx_pcierc#_cfg076 3225 * 3226 * PCIE_CFG076 = Seventy-seventh 32-bits of PCIE type 1 config space 3227 * (Root Error Status Register) 3228 */ 3229union cvmx_pciercx_cfg076 3230{ 3231 uint32_t u32; 3232 struct cvmx_pciercx_cfg076_s 3233 { 3234#if __BYTE_ORDER == __BIG_ENDIAN 3235 uint32_t aeimn : 5; /**< Advanced Error Interrupt Message Number, 3236 writable through PEM(0..1)_CFG_WR */ 3237 uint32_t reserved_7_26 : 20; 3238 uint32_t femr : 1; /**< Fatal Error Messages Received */ 3239 uint32_t nfemr : 1; /**< Non-Fatal Error Messages Received */ 3240 uint32_t fuf : 1; /**< First Uncorrectable Fatal */ 3241 uint32_t multi_efnfr : 1; /**< Multiple ERR_FATAL/NONFATAL Received */ 3242 uint32_t efnfr : 1; /**< ERR_FATAL/NONFATAL Received */ 3243 uint32_t multi_ecr : 1; /**< Multiple ERR_COR Received */ 3244 uint32_t ecr : 1; /**< ERR_COR Received */ 3245#else 3246 uint32_t ecr : 1; 3247 uint32_t multi_ecr : 1; 3248 uint32_t efnfr : 1; 3249 uint32_t multi_efnfr : 1; 3250 uint32_t fuf : 1; 3251 uint32_t nfemr : 1; 3252 uint32_t femr : 1; 3253 uint32_t reserved_7_26 : 20; 3254 uint32_t aeimn : 5; 3255#endif 3256 } s; 3257 struct cvmx_pciercx_cfg076_s cn52xx; 3258 struct cvmx_pciercx_cfg076_s cn52xxp1; 3259 struct cvmx_pciercx_cfg076_s cn56xx; 3260 struct cvmx_pciercx_cfg076_s cn56xxp1; 3261 struct cvmx_pciercx_cfg076_s cn63xx; 3262 struct cvmx_pciercx_cfg076_s cn63xxp1; 3263}; 3264typedef union cvmx_pciercx_cfg076 cvmx_pciercx_cfg076_t; 3265 3266/** 3267 * cvmx_pcierc#_cfg077 3268 * 3269 * PCIE_CFG077 = Seventy-eighth 32-bits of PCIE type 1 config space 3270 * (Error Source Identification Register) 3271 */ 3272union cvmx_pciercx_cfg077 3273{ 3274 uint32_t u32; 3275 struct cvmx_pciercx_cfg077_s 3276 { 3277#if __BYTE_ORDER == __BIG_ENDIAN 3278 uint32_t efnfsi : 16; /**< ERR_FATAL/NONFATAL Source Identification */ 3279 uint32_t ecsi : 16; /**< ERR_COR Source Identification */ 3280#else 3281 uint32_t ecsi : 16; 3282 uint32_t efnfsi : 16; 3283#endif 3284 } s; 3285 struct cvmx_pciercx_cfg077_s cn52xx; 3286 struct cvmx_pciercx_cfg077_s cn52xxp1; 3287 struct cvmx_pciercx_cfg077_s cn56xx; 3288 struct cvmx_pciercx_cfg077_s cn56xxp1; 3289 struct cvmx_pciercx_cfg077_s cn63xx; 3290 struct cvmx_pciercx_cfg077_s cn63xxp1; 3291}; 3292typedef union cvmx_pciercx_cfg077 cvmx_pciercx_cfg077_t; 3293 3294/** 3295 * cvmx_pcierc#_cfg448 3296 * 3297 * PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 1 config space 3298 * (Ack Latency Timer and Replay Timer Register) 3299 */ 3300union cvmx_pciercx_cfg448 3301{ 3302 uint32_t u32; 3303 struct cvmx_pciercx_cfg448_s 3304 { 3305#if __BYTE_ORDER == __BIG_ENDIAN 3306 uint32_t rtl : 16; /**< Replay Time Limit 3307 The replay timer expires when it reaches this limit. The PCI 3308 Express bus initiates a replay upon reception of a Nak or when 3309 the replay timer expires. 3310 The default is then updated based on the Negotiated Link Width 3311 and Max_Payload_Size. */ 3312 uint32_t rtltl : 16; /**< Round Trip Latency Time Limit 3313 The Ack/Nak latency timer expires when it reaches this limit. 3314 The default is then updated based on the Negotiated Link Width 3315 and Max_Payload_Size. */ 3316#else 3317 uint32_t rtltl : 16; 3318 uint32_t rtl : 16; 3319#endif 3320 } s; 3321 struct cvmx_pciercx_cfg448_s cn52xx; 3322 struct cvmx_pciercx_cfg448_s cn52xxp1; 3323 struct cvmx_pciercx_cfg448_s cn56xx; 3324 struct cvmx_pciercx_cfg448_s cn56xxp1; 3325 struct cvmx_pciercx_cfg448_s cn63xx; 3326 struct cvmx_pciercx_cfg448_s cn63xxp1; 3327}; 3328typedef union cvmx_pciercx_cfg448 cvmx_pciercx_cfg448_t; 3329 3330/** 3331 * cvmx_pcierc#_cfg449 3332 * 3333 * PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 1 config space 3334 * (Other Message Register) 3335 */ 3336union cvmx_pciercx_cfg449 3337{ 3338 uint32_t u32; 3339 struct cvmx_pciercx_cfg449_s 3340 { 3341#if __BYTE_ORDER == __BIG_ENDIAN 3342 uint32_t omr : 32; /**< Other Message Register 3343 This register can be used for either of the following purposes: 3344 o To send a specific PCI Express Message, the application 3345 writes the payload of the Message into this register, then 3346 sets bit 0 of the Port Link Control Register to send the 3347 Message. 3348 o To store a corruption pattern for corrupting the LCRC on all 3349 TLPs, the application places a 32-bit corruption pattern into 3350 this register and enables this function by setting bit 25 of 3351 the Port Link Control Register. When enabled, the transmit 3352 LCRC result is XOR'd with this pattern before inserting 3353 it into the packet. */ 3354#else 3355 uint32_t omr : 32; 3356#endif 3357 } s; 3358 struct cvmx_pciercx_cfg449_s cn52xx; 3359 struct cvmx_pciercx_cfg449_s cn52xxp1; 3360 struct cvmx_pciercx_cfg449_s cn56xx; 3361 struct cvmx_pciercx_cfg449_s cn56xxp1; 3362 struct cvmx_pciercx_cfg449_s cn63xx; 3363 struct cvmx_pciercx_cfg449_s cn63xxp1; 3364}; 3365typedef union cvmx_pciercx_cfg449 cvmx_pciercx_cfg449_t; 3366 3367/** 3368 * cvmx_pcierc#_cfg450 3369 * 3370 * PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 1 config space 3371 * (Port Force Link Register) 3372 */ 3373union cvmx_pciercx_cfg450 3374{ 3375 uint32_t u32; 3376 struct cvmx_pciercx_cfg450_s 3377 { 3378#if __BYTE_ORDER == __BIG_ENDIAN 3379 uint32_t lpec : 8; /**< Low Power Entrance Count 3380 The Power Management state will wait for this many clock cycles 3381 for the associated completion of a CfgWr to PCIE_CFG017 register 3382 Power State (PS) field register to go low-power. This register 3383 is intended for applications that do not let the PCI Express 3384 bus handle a completion for configuration request to the 3385 Power Management Control and Status (PCIE_CFG017) register. */ 3386 uint32_t reserved_22_23 : 2; 3387 uint32_t link_state : 6; /**< Link State 3388 The Link state that the PCI Express Bus will be forced to 3389 when bit 15 (Force Link) is set. 3390 State encoding: 3391 o DETECT_QUIET 00h 3392 o DETECT_ACT 01h 3393 o POLL_ACTIVE 02h 3394 o POLL_COMPLIANCE 03h 3395 o POLL_CONFIG 04h 3396 o PRE_DETECT_QUIET 05h 3397 o DETECT_WAIT 06h 3398 o CFG_LINKWD_START 07h 3399 o CFG_LINKWD_ACEPT 08h 3400 o CFG_LANENUM_WAIT 09h 3401 o CFG_LANENUM_ACEPT 0Ah 3402 o CFG_COMPLETE 0Bh 3403 o CFG_IDLE 0Ch 3404 o RCVRY_LOCK 0Dh 3405 o RCVRY_SPEED 0Eh 3406 o RCVRY_RCVRCFG 0Fh 3407 o RCVRY_IDLE 10h 3408 o L0 11h 3409 o L0S 12h 3410 o L123_SEND_EIDLE 13h 3411 o L1_IDLE 14h 3412 o L2_IDLE 15h 3413 o L2_WAKE 16h 3414 o DISABLED_ENTRY 17h 3415 o DISABLED_IDLE 18h 3416 o DISABLED 19h 3417 o LPBK_ENTRY 1Ah 3418 o LPBK_ACTIVE 1Bh 3419 o LPBK_EXIT 1Ch 3420 o LPBK_EXIT_TIMEOUT 1Dh 3421 o HOT_RESET_ENTRY 1Eh 3422 o HOT_RESET 1Fh */ 3423 uint32_t force_link : 1; /**< Force Link 3424 Forces the Link to the state specified by the Link State field. 3425 The Force Link pulse will trigger Link re-negotiation. 3426 * As the The Force Link is a pulse, writing a 1 to it does 3427 trigger the forced link state event, even thought reading it 3428 always returns a 0. */ 3429 uint32_t reserved_8_14 : 7; 3430 uint32_t link_num : 8; /**< Link Number */ 3431#else 3432 uint32_t link_num : 8; 3433 uint32_t reserved_8_14 : 7; 3434 uint32_t force_link : 1; 3435 uint32_t link_state : 6; 3436 uint32_t reserved_22_23 : 2; 3437 uint32_t lpec : 8; 3438#endif 3439 } s; 3440 struct cvmx_pciercx_cfg450_s cn52xx; 3441 struct cvmx_pciercx_cfg450_s cn52xxp1; 3442 struct cvmx_pciercx_cfg450_s cn56xx; 3443 struct cvmx_pciercx_cfg450_s cn56xxp1; 3444 struct cvmx_pciercx_cfg450_s cn63xx; 3445 struct cvmx_pciercx_cfg450_s cn63xxp1; 3446}; 3447typedef union cvmx_pciercx_cfg450 cvmx_pciercx_cfg450_t; 3448 3449/** 3450 * cvmx_pcierc#_cfg451 3451 * 3452 * PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 1 config space 3453 * (Ack Frequency Register) 3454 */ 3455union cvmx_pciercx_cfg451 3456{ 3457 uint32_t u32; 3458 struct cvmx_pciercx_cfg451_s 3459 { 3460#if __BYTE_ORDER == __BIG_ENDIAN 3461 uint32_t reserved_30_31 : 2; 3462 uint32_t l1el : 3; /**< L1 Entrance Latency 3463 Values correspond to: 3464 o 000: 1 ms 3465 o 001: 2 ms 3466 o 010: 4 ms 3467 o 011: 8 ms 3468 o 100: 16 ms 3469 o 101: 32 ms 3470 o 110 or 111: 64 ms */ 3471 uint32_t l0el : 3; /**< L0s Entrance Latency 3472 Values correspond to: 3473 o 000: 1 ms 3474 o 001: 2 ms 3475 o 010: 3 ms 3476 o 011: 4 ms 3477 o 100: 5 ms 3478 o 101: 6 ms 3479 o 110 or 111: 7 ms */ 3480 uint32_t n_fts_cc : 8; /**< N_FTS when common clock is used. 3481 The number of Fast Training Sequence ordered sets to be 3482 transmitted when transitioning from L0s to L0. The maximum 3483 number of FTS ordered-sets that a component can request is 255. 3484 Note: The core does not support a value of zero; a value of 3485 zero can cause the LTSSM to go into the recovery state 3486 when exiting from L0s. */ 3487 uint32_t n_fts : 8; /**< N_FTS 3488 The number of Fast Training Sequence ordered sets to be 3489 transmitted when transitioning from L0s to L0. The maximum 3490 number of FTS ordered-sets that a component can request is 255. 3491 Note: The core does not support a value of zero; a value of 3492 zero can cause the LTSSM to go into the recovery state 3493 when exiting from L0s. */ 3494 uint32_t ack_freq : 8; /**< Ack Frequency 3495 The number of pending Ack's specified here (up to 255) before 3496 sending an Ack. */ 3497#else 3498 uint32_t ack_freq : 8; 3499 uint32_t n_fts : 8; 3500 uint32_t n_fts_cc : 8; 3501 uint32_t l0el : 3; 3502 uint32_t l1el : 3; 3503 uint32_t reserved_30_31 : 2; 3504#endif 3505 } s; 3506 struct cvmx_pciercx_cfg451_s cn52xx; 3507 struct cvmx_pciercx_cfg451_s cn52xxp1; 3508 struct cvmx_pciercx_cfg451_s cn56xx; 3509 struct cvmx_pciercx_cfg451_s cn56xxp1; 3510 struct cvmx_pciercx_cfg451_s cn63xx; 3511 struct cvmx_pciercx_cfg451_s cn63xxp1; 3512}; 3513typedef union cvmx_pciercx_cfg451 cvmx_pciercx_cfg451_t; 3514 3515/** 3516 * cvmx_pcierc#_cfg452 3517 * 3518 * PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 1 config space 3519 * (Port Link Control Register) 3520 */ 3521union cvmx_pciercx_cfg452 3522{ 3523 uint32_t u32; 3524 struct cvmx_pciercx_cfg452_s 3525 { 3526#if __BYTE_ORDER == __BIG_ENDIAN 3527 uint32_t reserved_26_31 : 6; 3528 uint32_t eccrc : 1; /**< Enable Corrupted CRC 3529 Causes corrupt LCRC for TLPs when set, 3530 using the pattern contained in the Other Message register. 3531 This is a test feature, not to be used in normal operation. */ 3532 uint32_t reserved_22_24 : 3; 3533 uint32_t lme : 6; /**< Link Mode Enable 3534 o 000001: x1 3535 o 000011: x2 3536 o 000111: x4 3537 o 001111: x8 (not supported) 3538 o 011111: x16 (not supported) 3539 o 111111: x32 (not supported) 3540 This field indicates the MAXIMUM number of lanes supported 3541 by the PCIe port. The value can be set less than 0x7 3542 to limit the number of lanes the PCIe will attempt to use. 3543 The programming of this field needs to be done by SW BEFORE 3544 enabling the link. See also MLW. 3545 (Note: The value of this field does NOT indicate the number 3546 of lanes in use by the PCIe. LME sets the max number of lanes 3547 in the PCIe core that COULD be used. As per the PCIe specs, 3548 the PCIe core can negotiate a smaller link width, so all 3549 of x4, x2, and x1 are supported when LME=0x7, 3550 for example.) */ 3551 uint32_t reserved_8_15 : 8; 3552 uint32_t flm : 1; /**< Fast Link Mode 3553 Sets all internal timers to fast mode for simulation purposes. */ 3554 uint32_t reserved_6_6 : 1; 3555 uint32_t dllle : 1; /**< DLL Link Enable 3556 Enables Link initialization. If DLL Link Enable = 0, the PCI 3557 Express bus does not transmit InitFC DLLPs and does not 3558 establish a Link. */ 3559 uint32_t reserved_4_4 : 1; 3560 uint32_t ra : 1; /**< Reset Assert 3561 Triggers a recovery and forces the LTSSM to the Hot Reset 3562 state (downstream port only). */ 3563 uint32_t le : 1; /**< Loopback Enable 3564 Initiate loopback mode as a master. On a 0->1 transition, 3565 the PCIe core sends TS ordered sets with the loopback bit set 3566 to cause the link partner to enter into loopback mode as a 3567 slave. Normal transmission is not possible when LE=1. To exit 3568 loopback mode, take the link through a reset sequence. */ 3569 uint32_t sd : 1; /**< Scramble Disable 3570 Turns off data scrambling. */ 3571 uint32_t omr : 1; /**< Other Message Request 3572 When software writes a `1' to this bit, the PCI Express bus 3573 transmits the Message contained in the Other Message register. */ 3574#else 3575 uint32_t omr : 1; 3576 uint32_t sd : 1; 3577 uint32_t le : 1; 3578 uint32_t ra : 1; 3579 uint32_t reserved_4_4 : 1; 3580 uint32_t dllle : 1; 3581 uint32_t reserved_6_6 : 1; 3582 uint32_t flm : 1; 3583 uint32_t reserved_8_15 : 8; 3584 uint32_t lme : 6; 3585 uint32_t reserved_22_24 : 3; 3586 uint32_t eccrc : 1; 3587 uint32_t reserved_26_31 : 6; 3588#endif 3589 } s; 3590 struct cvmx_pciercx_cfg452_s cn52xx; 3591 struct cvmx_pciercx_cfg452_s cn52xxp1; 3592 struct cvmx_pciercx_cfg452_s cn56xx; 3593 struct cvmx_pciercx_cfg452_s cn56xxp1; 3594 struct cvmx_pciercx_cfg452_s cn63xx; 3595 struct cvmx_pciercx_cfg452_s cn63xxp1; 3596}; 3597typedef union cvmx_pciercx_cfg452 cvmx_pciercx_cfg452_t; 3598 3599/** 3600 * cvmx_pcierc#_cfg453 3601 * 3602 * PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 1 config space 3603 * (Lane Skew Register) 3604 */ 3605union cvmx_pciercx_cfg453 3606{ 3607 uint32_t u32; 3608 struct cvmx_pciercx_cfg453_s 3609 { 3610#if __BYTE_ORDER == __BIG_ENDIAN 3611 uint32_t dlld : 1; /**< Disable Lane-to-Lane Deskew 3612 Disables the internal Lane-to-Lane deskew logic. */ 3613 uint32_t reserved_26_30 : 5; 3614 uint32_t ack_nak : 1; /**< Ack/Nak Disable 3615 Prevents the PCI Express bus from sending Ack and Nak DLLPs. */ 3616 uint32_t fcd : 1; /**< Flow Control Disable 3617 Prevents the PCI Express bus from sending FC DLLPs. */ 3618 uint32_t ilst : 24; /**< Insert Lane Skew for Transmit (not supported for x16) 3619 Causes skew between lanes for test purposes. There are three 3620 bits per Lane. The value is in units of one symbol time. For 3621 example, the value 010b for a Lane forces a skew of two symbol 3622 times for that Lane. The maximum skew value for any Lane is 5 3623 symbol times. */ 3624#else 3625 uint32_t ilst : 24; 3626 uint32_t fcd : 1; 3627 uint32_t ack_nak : 1; 3628 uint32_t reserved_26_30 : 5; 3629 uint32_t dlld : 1; 3630#endif 3631 } s; 3632 struct cvmx_pciercx_cfg453_s cn52xx; 3633 struct cvmx_pciercx_cfg453_s cn52xxp1; 3634 struct cvmx_pciercx_cfg453_s cn56xx; 3635 struct cvmx_pciercx_cfg453_s cn56xxp1; 3636 struct cvmx_pciercx_cfg453_s cn63xx; 3637 struct cvmx_pciercx_cfg453_s cn63xxp1; 3638}; 3639typedef union cvmx_pciercx_cfg453 cvmx_pciercx_cfg453_t; 3640 3641/** 3642 * cvmx_pcierc#_cfg454 3643 * 3644 * PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 1 config space 3645 * (Symbol Number Register) 3646 */ 3647union cvmx_pciercx_cfg454 3648{ 3649 uint32_t u32; 3650 struct cvmx_pciercx_cfg454_s 3651 { 3652#if __BYTE_ORDER == __BIG_ENDIAN 3653 uint32_t reserved_29_31 : 3; 3654 uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer 3655 Increases the timer value for the Flow Control watchdog timer, 3656 in increments of 16 clock cycles. */ 3657 uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer 3658 Increases the timer value for the Ack/Nak latency timer, in 3659 increments of 64 clock cycles. */ 3660 uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer 3661 Increases the timer value for the replay timer, in increments 3662 of 64 clock cycles. */ 3663 uint32_t reserved_11_13 : 3; 3664 uint32_t nskps : 3; /**< Number of SKP Symbols */ 3665 uint32_t reserved_4_7 : 4; 3666 uint32_t ntss : 4; /**< Number of TS Symbols 3667 Sets the number of TS identifier symbols that are sent in TS1 3668 and TS2 ordered sets. */ 3669#else 3670 uint32_t ntss : 4; 3671 uint32_t reserved_4_7 : 4; 3672 uint32_t nskps : 3; 3673 uint32_t reserved_11_13 : 3; 3674 uint32_t tmrt : 5; 3675 uint32_t tmanlt : 5; 3676 uint32_t tmfcwt : 5; 3677 uint32_t reserved_29_31 : 3; 3678#endif 3679 } s; 3680 struct cvmx_pciercx_cfg454_s cn52xx; 3681 struct cvmx_pciercx_cfg454_s cn52xxp1; 3682 struct cvmx_pciercx_cfg454_s cn56xx; 3683 struct cvmx_pciercx_cfg454_s cn56xxp1; 3684 struct cvmx_pciercx_cfg454_s cn63xx; 3685 struct cvmx_pciercx_cfg454_s cn63xxp1; 3686}; 3687typedef union cvmx_pciercx_cfg454 cvmx_pciercx_cfg454_t; 3688 3689/** 3690 * cvmx_pcierc#_cfg455 3691 * 3692 * PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 1 config space 3693 * (Symbol Timer Register/Filter Mask Register 1) 3694 */ 3695union cvmx_pciercx_cfg455 3696{ 3697 uint32_t u32; 3698 struct cvmx_pciercx_cfg455_s 3699 { 3700#if __BYTE_ORDER == __BIG_ENDIAN 3701 uint32_t m_cfg0_filt : 1; /**< Mask filtering of received Configuration Requests (RC mode only) */ 3702 uint32_t m_io_filt : 1; /**< Mask filtering of received I/O Requests (RC mode only) */ 3703 uint32_t msg_ctrl : 1; /**< Message Control 3704 The application must not change this field. */ 3705 uint32_t m_cpl_ecrc_filt : 1; /**< Mask ECRC error filtering for Completions */ 3706 uint32_t m_ecrc_filt : 1; /**< Mask ECRC error filtering */ 3707 uint32_t m_cpl_len_err : 1; /**< Mask Length mismatch error for received Completions */ 3708 uint32_t m_cpl_attr_err : 1; /**< Mask Attributes mismatch error for received Completions */ 3709 uint32_t m_cpl_tc_err : 1; /**< Mask Traffic Class mismatch error for received Completions */ 3710 uint32_t m_cpl_fun_err : 1; /**< Mask function mismatch error for received Completions */ 3711 uint32_t m_cpl_rid_err : 1; /**< Mask Requester ID mismatch error for received Completions */ 3712 uint32_t m_cpl_tag_err : 1; /**< Mask Tag error rules for received Completions */ 3713 uint32_t m_lk_filt : 1; /**< Mask Locked Request filtering */ 3714 uint32_t m_cfg1_filt : 1; /**< Mask Type 1 Configuration Request filtering */ 3715 uint32_t m_bar_match : 1; /**< Mask BAR match filtering */ 3716 uint32_t m_pois_filt : 1; /**< Mask poisoned TLP filtering */ 3717 uint32_t m_fun : 1; /**< Mask function */ 3718 uint32_t dfcwt : 1; /**< Disable FC Watchdog Timer */ 3719 uint32_t reserved_11_14 : 4; 3720 uint32_t skpiv : 11; /**< SKP Interval Value */ 3721#else 3722 uint32_t skpiv : 11; 3723 uint32_t reserved_11_14 : 4; 3724 uint32_t dfcwt : 1; 3725 uint32_t m_fun : 1; 3726 uint32_t m_pois_filt : 1; 3727 uint32_t m_bar_match : 1; 3728 uint32_t m_cfg1_filt : 1; 3729 uint32_t m_lk_filt : 1; 3730 uint32_t m_cpl_tag_err : 1; 3731 uint32_t m_cpl_rid_err : 1; 3732 uint32_t m_cpl_fun_err : 1; 3733 uint32_t m_cpl_tc_err : 1; 3734 uint32_t m_cpl_attr_err : 1; 3735 uint32_t m_cpl_len_err : 1; 3736 uint32_t m_ecrc_filt : 1; 3737 uint32_t m_cpl_ecrc_filt : 1; 3738 uint32_t msg_ctrl : 1; 3739 uint32_t m_io_filt : 1; 3740 uint32_t m_cfg0_filt : 1; 3741#endif 3742 } s; 3743 struct cvmx_pciercx_cfg455_s cn52xx; 3744 struct cvmx_pciercx_cfg455_s cn52xxp1; 3745 struct cvmx_pciercx_cfg455_s cn56xx; 3746 struct cvmx_pciercx_cfg455_s cn56xxp1; 3747 struct cvmx_pciercx_cfg455_s cn63xx; 3748 struct cvmx_pciercx_cfg455_s cn63xxp1; 3749}; 3750typedef union cvmx_pciercx_cfg455 cvmx_pciercx_cfg455_t; 3751 3752/** 3753 * cvmx_pcierc#_cfg456 3754 * 3755 * PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 1 config space 3756 * (Filter Mask Register 2) 3757 */ 3758union cvmx_pciercx_cfg456 3759{ 3760 uint32_t u32; 3761 struct cvmx_pciercx_cfg456_s 3762 { 3763#if __BYTE_ORDER == __BIG_ENDIAN 3764 uint32_t reserved_2_31 : 30; 3765 uint32_t m_vend1_drp : 1; /**< Mask Vendor MSG Type 1 dropped silently */ 3766 uint32_t m_vend0_drp : 1; /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */ 3767#else 3768 uint32_t m_vend0_drp : 1; 3769 uint32_t m_vend1_drp : 1; 3770 uint32_t reserved_2_31 : 30; 3771#endif 3772 } s; 3773 struct cvmx_pciercx_cfg456_s cn52xx; 3774 struct cvmx_pciercx_cfg456_s cn52xxp1; 3775 struct cvmx_pciercx_cfg456_s cn56xx; 3776 struct cvmx_pciercx_cfg456_s cn56xxp1; 3777 struct cvmx_pciercx_cfg456_s cn63xx; 3778 struct cvmx_pciercx_cfg456_s cn63xxp1; 3779}; 3780typedef union cvmx_pciercx_cfg456 cvmx_pciercx_cfg456_t; 3781 3782/** 3783 * cvmx_pcierc#_cfg458 3784 * 3785 * PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 1 config space 3786 * (Debug Register 0) 3787 */ 3788union cvmx_pciercx_cfg458 3789{ 3790 uint32_t u32; 3791 struct cvmx_pciercx_cfg458_s 3792 { 3793#if __BYTE_ORDER == __BIG_ENDIAN 3794 uint32_t dbg_info_l32 : 32; /**< The value on cxpl_debug_info[31:0]. */ 3795#else 3796 uint32_t dbg_info_l32 : 32; 3797#endif 3798 } s; 3799 struct cvmx_pciercx_cfg458_s cn52xx; 3800 struct cvmx_pciercx_cfg458_s cn52xxp1; 3801 struct cvmx_pciercx_cfg458_s cn56xx; 3802 struct cvmx_pciercx_cfg458_s cn56xxp1; 3803 struct cvmx_pciercx_cfg458_s cn63xx; 3804 struct cvmx_pciercx_cfg458_s cn63xxp1; 3805}; 3806typedef union cvmx_pciercx_cfg458 cvmx_pciercx_cfg458_t; 3807 3808/** 3809 * cvmx_pcierc#_cfg459 3810 * 3811 * PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 1 config space 3812 * (Debug Register 1) 3813 */ 3814union cvmx_pciercx_cfg459 3815{ 3816 uint32_t u32; 3817 struct cvmx_pciercx_cfg459_s 3818 { 3819#if __BYTE_ORDER == __BIG_ENDIAN 3820 uint32_t dbg_info_u32 : 32; /**< The value on cxpl_debug_info[63:32]. */ 3821#else 3822 uint32_t dbg_info_u32 : 32; 3823#endif 3824 } s; 3825 struct cvmx_pciercx_cfg459_s cn52xx; 3826 struct cvmx_pciercx_cfg459_s cn52xxp1; 3827 struct cvmx_pciercx_cfg459_s cn56xx; 3828 struct cvmx_pciercx_cfg459_s cn56xxp1; 3829 struct cvmx_pciercx_cfg459_s cn63xx; 3830 struct cvmx_pciercx_cfg459_s cn63xxp1; 3831}; 3832typedef union cvmx_pciercx_cfg459 cvmx_pciercx_cfg459_t; 3833 3834/** 3835 * cvmx_pcierc#_cfg460 3836 * 3837 * PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 1 config space 3838 * (Transmit Posted FC Credit Status) 3839 */ 3840union cvmx_pciercx_cfg460 3841{ 3842 uint32_t u32; 3843 struct cvmx_pciercx_cfg460_s 3844 { 3845#if __BYTE_ORDER == __BIG_ENDIAN 3846 uint32_t reserved_20_31 : 12; 3847 uint32_t tphfcc : 8; /**< Transmit Posted Header FC Credits 3848 The Posted Header credits advertised by the receiver at the 3849 other end of the Link, updated with each UpdateFC DLLP. */ 3850 uint32_t tpdfcc : 12; /**< Transmit Posted Data FC Credits 3851 The Posted Data credits advertised by the receiver at the other 3852 end of the Link, updated with each UpdateFC DLLP. */ 3853#else 3854 uint32_t tpdfcc : 12; 3855 uint32_t tphfcc : 8; 3856 uint32_t reserved_20_31 : 12; 3857#endif 3858 } s; 3859 struct cvmx_pciercx_cfg460_s cn52xx; 3860 struct cvmx_pciercx_cfg460_s cn52xxp1; 3861 struct cvmx_pciercx_cfg460_s cn56xx; 3862 struct cvmx_pciercx_cfg460_s cn56xxp1; 3863 struct cvmx_pciercx_cfg460_s cn63xx; 3864 struct cvmx_pciercx_cfg460_s cn63xxp1; 3865}; 3866typedef union cvmx_pciercx_cfg460 cvmx_pciercx_cfg460_t; 3867 3868/** 3869 * cvmx_pcierc#_cfg461 3870 * 3871 * PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 1 config space 3872 * (Transmit Non-Posted FC Credit Status) 3873 */ 3874union cvmx_pciercx_cfg461 3875{ 3876 uint32_t u32; 3877 struct cvmx_pciercx_cfg461_s 3878 { 3879#if __BYTE_ORDER == __BIG_ENDIAN 3880 uint32_t reserved_20_31 : 12; 3881 uint32_t tchfcc : 8; /**< Transmit Non-Posted Header FC Credits 3882 The Non-Posted Header credits advertised by the receiver at the 3883 other end of the Link, updated with each UpdateFC DLLP. */ 3884 uint32_t tcdfcc : 12; /**< Transmit Non-Posted Data FC Credits 3885 The Non-Posted Data credits advertised by the receiver at the 3886 other end of the Link, updated with each UpdateFC DLLP. */ 3887#else 3888 uint32_t tcdfcc : 12; 3889 uint32_t tchfcc : 8; 3890 uint32_t reserved_20_31 : 12; 3891#endif 3892 } s; 3893 struct cvmx_pciercx_cfg461_s cn52xx; 3894 struct cvmx_pciercx_cfg461_s cn52xxp1; 3895 struct cvmx_pciercx_cfg461_s cn56xx; 3896 struct cvmx_pciercx_cfg461_s cn56xxp1; 3897 struct cvmx_pciercx_cfg461_s cn63xx; 3898 struct cvmx_pciercx_cfg461_s cn63xxp1; 3899}; 3900typedef union cvmx_pciercx_cfg461 cvmx_pciercx_cfg461_t; 3901 3902/** 3903 * cvmx_pcierc#_cfg462 3904 * 3905 * PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 1 config space 3906 * (Transmit Completion FC Credit Status ) 3907 */ 3908union cvmx_pciercx_cfg462 3909{ 3910 uint32_t u32; 3911 struct cvmx_pciercx_cfg462_s 3912 { 3913#if __BYTE_ORDER == __BIG_ENDIAN 3914 uint32_t reserved_20_31 : 12; 3915 uint32_t tchfcc : 8; /**< Transmit Completion Header FC Credits 3916 The Completion Header credits advertised by the receiver at the 3917 other end of the Link, updated with each UpdateFC DLLP. */ 3918 uint32_t tcdfcc : 12; /**< Transmit Completion Data FC Credits 3919 The Completion Data credits advertised by the receiver at the 3920 other end of the Link, updated with each UpdateFC DLLP. */ 3921#else 3922 uint32_t tcdfcc : 12; 3923 uint32_t tchfcc : 8; 3924 uint32_t reserved_20_31 : 12; 3925#endif 3926 } s; 3927 struct cvmx_pciercx_cfg462_s cn52xx; 3928 struct cvmx_pciercx_cfg462_s cn52xxp1; 3929 struct cvmx_pciercx_cfg462_s cn56xx; 3930 struct cvmx_pciercx_cfg462_s cn56xxp1; 3931 struct cvmx_pciercx_cfg462_s cn63xx; 3932 struct cvmx_pciercx_cfg462_s cn63xxp1; 3933}; 3934typedef union cvmx_pciercx_cfg462 cvmx_pciercx_cfg462_t; 3935 3936/** 3937 * cvmx_pcierc#_cfg463 3938 * 3939 * PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 1 config space 3940 * (Queue Status) 3941 */ 3942union cvmx_pciercx_cfg463 3943{ 3944 uint32_t u32; 3945 struct cvmx_pciercx_cfg463_s 3946 { 3947#if __BYTE_ORDER == __BIG_ENDIAN 3948 uint32_t reserved_3_31 : 29; 3949 uint32_t rqne : 1; /**< Received Queue Not Empty 3950 Indicates there is data in one or more of the receive buffers. */ 3951 uint32_t trbne : 1; /**< Transmit Retry Buffer Not Empty 3952 Indicates that there is data in the transmit retry buffer. */ 3953 uint32_t rtlpfccnr : 1; /**< Received TLP FC Credits Not Returned 3954 Indicates that the PCI Express bus has sent a TLP but has not 3955 yet received an UpdateFC DLLP indicating that the credits for 3956 that TLP have been restored by the receiver at the other end of 3957 the Link. */ 3958#else 3959 uint32_t rtlpfccnr : 1; 3960 uint32_t trbne : 1; 3961 uint32_t rqne : 1; 3962 uint32_t reserved_3_31 : 29; 3963#endif 3964 } s; 3965 struct cvmx_pciercx_cfg463_s cn52xx; 3966 struct cvmx_pciercx_cfg463_s cn52xxp1; 3967 struct cvmx_pciercx_cfg463_s cn56xx; 3968 struct cvmx_pciercx_cfg463_s cn56xxp1; 3969 struct cvmx_pciercx_cfg463_s cn63xx; 3970 struct cvmx_pciercx_cfg463_s cn63xxp1; 3971}; 3972typedef union cvmx_pciercx_cfg463 cvmx_pciercx_cfg463_t; 3973 3974/** 3975 * cvmx_pcierc#_cfg464 3976 * 3977 * PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 1 config space 3978 * (VC Transmit Arbitration Register 1) 3979 */ 3980union cvmx_pciercx_cfg464 3981{ 3982 uint32_t u32; 3983 struct cvmx_pciercx_cfg464_s 3984 { 3985#if __BYTE_ORDER == __BIG_ENDIAN 3986 uint32_t wrr_vc3 : 8; /**< WRR Weight for VC3 */ 3987 uint32_t wrr_vc2 : 8; /**< WRR Weight for VC2 */ 3988 uint32_t wrr_vc1 : 8; /**< WRR Weight for VC1 */ 3989 uint32_t wrr_vc0 : 8; /**< WRR Weight for VC0 */ 3990#else 3991 uint32_t wrr_vc0 : 8; 3992 uint32_t wrr_vc1 : 8; 3993 uint32_t wrr_vc2 : 8; 3994 uint32_t wrr_vc3 : 8; 3995#endif 3996 } s; 3997 struct cvmx_pciercx_cfg464_s cn52xx; 3998 struct cvmx_pciercx_cfg464_s cn52xxp1; 3999 struct cvmx_pciercx_cfg464_s cn56xx; 4000 struct cvmx_pciercx_cfg464_s cn56xxp1; 4001 struct cvmx_pciercx_cfg464_s cn63xx; 4002 struct cvmx_pciercx_cfg464_s cn63xxp1; 4003}; 4004typedef union cvmx_pciercx_cfg464 cvmx_pciercx_cfg464_t; 4005 4006/** 4007 * cvmx_pcierc#_cfg465 4008 * 4009 * PCIE_CFG465 = Four hundred sixty-sixth 32-bits of config space 4010 * (VC Transmit Arbitration Register 2) 4011 */ 4012union cvmx_pciercx_cfg465 4013{ 4014 uint32_t u32; 4015 struct cvmx_pciercx_cfg465_s 4016 { 4017#if __BYTE_ORDER == __BIG_ENDIAN 4018 uint32_t wrr_vc7 : 8; /**< WRR Weight for VC7 */ 4019 uint32_t wrr_vc6 : 8; /**< WRR Weight for VC6 */ 4020 uint32_t wrr_vc5 : 8; /**< WRR Weight for VC5 */ 4021 uint32_t wrr_vc4 : 8; /**< WRR Weight for VC4 */ 4022#else 4023 uint32_t wrr_vc4 : 8; 4024 uint32_t wrr_vc5 : 8; 4025 uint32_t wrr_vc6 : 8; 4026 uint32_t wrr_vc7 : 8; 4027#endif 4028 } s; 4029 struct cvmx_pciercx_cfg465_s cn52xx; 4030 struct cvmx_pciercx_cfg465_s cn52xxp1; 4031 struct cvmx_pciercx_cfg465_s cn56xx; 4032 struct cvmx_pciercx_cfg465_s cn56xxp1; 4033 struct cvmx_pciercx_cfg465_s cn63xx; 4034 struct cvmx_pciercx_cfg465_s cn63xxp1; 4035}; 4036typedef union cvmx_pciercx_cfg465 cvmx_pciercx_cfg465_t; 4037 4038/** 4039 * cvmx_pcierc#_cfg466 4040 * 4041 * PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 1 config space 4042 * (VC0 Posted Receive Queue Control) 4043 */ 4044union cvmx_pciercx_cfg466 4045{ 4046 uint32_t u32; 4047 struct cvmx_pciercx_cfg466_s 4048 { 4049#if __BYTE_ORDER == __BIG_ENDIAN 4050 uint32_t rx_queue_order : 1; /**< VC Ordering for Receive Queues 4051 Determines the VC ordering rule for the receive queues, used 4052 only in the segmented-buffer configuration, 4053 writable through PEM(0..1)_CFG_WR: 4054 o 1: Strict ordering, higher numbered VCs have higher priority 4055 o 0: Round robin 4056 However, the application must not change this field. */ 4057 uint32_t type_ordering : 1; /**< TLP Type Ordering for VC0 4058 Determines the TLP type ordering rule for VC0 receive queues, 4059 used only in the segmented-buffer configuration, writable 4060 through PEM(0..1)_CFG_WR: 4061 o 1: Ordering of received TLPs follows the rules in 4062 PCI Express Base Specification 4063 o 0: Strict ordering for received TLPs: Posted, then 4064 Completion, then Non-Posted 4065 However, the application must not change this field. */ 4066 uint32_t reserved_24_29 : 6; 4067 uint32_t queue_mode : 3; /**< VC0 Posted TLP Queue Mode 4068 The operating mode of the Posted receive queue for VC0, used 4069 only in the segmented-buffer configuration, writable through 4070 PEM(0..1)_CFG_WR. 4071 However, the application must not change this field. 4072 Only one bit can be set at a time: 4073 o Bit 23: Bypass 4074 o Bit 22: Cut-through 4075 o Bit 21: Store-and-forward */ 4076 uint32_t reserved_20_20 : 1; 4077 uint32_t header_credits : 8; /**< VC0 Posted Header Credits 4078 The number of initial Posted header credits for VC0, used for 4079 all receive queue buffer configurations. 4080 This field is writable through PEM(0..1)_CFG_WR. 4081 However, the application must not change this field. */ 4082 uint32_t data_credits : 12; /**< VC0 Posted Data Credits 4083 The number of initial Posted data credits for VC0, used for all 4084 receive queue buffer configurations. 4085 This field is writable through PEM(0..1)_CFG_WR. 4086 However, the application must not change this field. */ 4087#else 4088 uint32_t data_credits : 12; 4089 uint32_t header_credits : 8; 4090 uint32_t reserved_20_20 : 1; 4091 uint32_t queue_mode : 3; 4092 uint32_t reserved_24_29 : 6; 4093 uint32_t type_ordering : 1; 4094 uint32_t rx_queue_order : 1; 4095#endif 4096 } s; 4097 struct cvmx_pciercx_cfg466_s cn52xx; 4098 struct cvmx_pciercx_cfg466_s cn52xxp1; 4099 struct cvmx_pciercx_cfg466_s cn56xx; 4100 struct cvmx_pciercx_cfg466_s cn56xxp1; 4101 struct cvmx_pciercx_cfg466_s cn63xx; 4102 struct cvmx_pciercx_cfg466_s cn63xxp1; 4103}; 4104typedef union cvmx_pciercx_cfg466 cvmx_pciercx_cfg466_t; 4105 4106/** 4107 * cvmx_pcierc#_cfg467 4108 * 4109 * PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 1 config space 4110 * (VC0 Non-Posted Receive Queue Control) 4111 */ 4112union cvmx_pciercx_cfg467 4113{ 4114 uint32_t u32; 4115 struct cvmx_pciercx_cfg467_s 4116 { 4117#if __BYTE_ORDER == __BIG_ENDIAN 4118 uint32_t reserved_24_31 : 8; 4119 uint32_t queue_mode : 3; /**< VC0 Non-Posted TLP Queue Mode 4120 The operating mode of the Non-Posted receive queue for VC0, 4121 used only in the segmented-buffer configuration, writable 4122 through PEM(0..1)_CFG_WR. 4123 Only one bit can be set at a time: 4124 o Bit 23: Bypass 4125 o Bit 22: Cut-through 4126 o Bit 21: Store-and-forward 4127 However, the application must not change this field. */ 4128 uint32_t reserved_20_20 : 1; 4129 uint32_t header_credits : 8; /**< VC0 Non-Posted Header Credits 4130 The number of initial Non-Posted header credits for VC0, used 4131 for all receive queue buffer configurations. 4132 This field is writable through PEM(0..1)_CFG_WR. 4133 However, the application must not change this field. */ 4134 uint32_t data_credits : 12; /**< VC0 Non-Posted Data Credits 4135 The number of initial Non-Posted data credits for VC0, used for 4136 all receive queue buffer configurations. 4137 This field is writable through PEM(0..1)_CFG_WR. 4138 However, the application must not change this field. */ 4139#else 4140 uint32_t data_credits : 12; 4141 uint32_t header_credits : 8; 4142 uint32_t reserved_20_20 : 1; 4143 uint32_t queue_mode : 3; 4144 uint32_t reserved_24_31 : 8; 4145#endif 4146 } s; 4147 struct cvmx_pciercx_cfg467_s cn52xx; 4148 struct cvmx_pciercx_cfg467_s cn52xxp1; 4149 struct cvmx_pciercx_cfg467_s cn56xx; 4150 struct cvmx_pciercx_cfg467_s cn56xxp1; 4151 struct cvmx_pciercx_cfg467_s cn63xx; 4152 struct cvmx_pciercx_cfg467_s cn63xxp1; 4153}; 4154typedef union cvmx_pciercx_cfg467 cvmx_pciercx_cfg467_t; 4155 4156/** 4157 * cvmx_pcierc#_cfg468 4158 * 4159 * PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 1 config space 4160 * (VC0 Completion Receive Queue Control) 4161 */ 4162union cvmx_pciercx_cfg468 4163{ 4164 uint32_t u32; 4165 struct cvmx_pciercx_cfg468_s 4166 { 4167#if __BYTE_ORDER == __BIG_ENDIAN 4168 uint32_t reserved_24_31 : 8; 4169 uint32_t queue_mode : 3; /**< VC0 Completion TLP Queue Mode 4170 The operating mode of the Completion receive queue for VC0, 4171 used only in the segmented-buffer configuration, writable 4172 through PEM(0..1)_CFG_WR. 4173 Only one bit can be set at a time: 4174 o Bit 23: Bypass 4175 o Bit 22: Cut-through 4176 o Bit 21: Store-and-forward 4177 However, the application must not change this field. */ 4178 uint32_t reserved_20_20 : 1; 4179 uint32_t header_credits : 8; /**< VC0 Completion Header Credits 4180 The number of initial Completion header credits for VC0, used 4181 for all receive queue buffer configurations. 4182 This field is writable through PEM(0..1)_CFG_WR. 4183 However, the application must not change this field. */ 4184 uint32_t data_credits : 12; /**< VC0 Completion Data Credits 4185 The number of initial Completion data credits for VC0, used for 4186 all receive queue buffer configurations. 4187 This field is writable through PEM(0..1)_CFG_WR. 4188 However, the application must not change this field. */ 4189#else 4190 uint32_t data_credits : 12; 4191 uint32_t header_credits : 8; 4192 uint32_t reserved_20_20 : 1; 4193 uint32_t queue_mode : 3; 4194 uint32_t reserved_24_31 : 8; 4195#endif 4196 } s; 4197 struct cvmx_pciercx_cfg468_s cn52xx; 4198 struct cvmx_pciercx_cfg468_s cn52xxp1; 4199 struct cvmx_pciercx_cfg468_s cn56xx; 4200 struct cvmx_pciercx_cfg468_s cn56xxp1; 4201 struct cvmx_pciercx_cfg468_s cn63xx; 4202 struct cvmx_pciercx_cfg468_s cn63xxp1; 4203}; 4204typedef union cvmx_pciercx_cfg468 cvmx_pciercx_cfg468_t; 4205 4206/** 4207 * cvmx_pcierc#_cfg490 4208 * 4209 * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 1 config space 4210 * (VC0 Posted Buffer Depth) 4211 */ 4212union cvmx_pciercx_cfg490 4213{ 4214 uint32_t u32; 4215 struct cvmx_pciercx_cfg490_s 4216 { 4217#if __BYTE_ORDER == __BIG_ENDIAN 4218 uint32_t reserved_26_31 : 6; 4219 uint32_t header_depth : 10; /**< VC0 Posted Header Queue Depth 4220 Sets the number of entries in the Posted header queue for VC0 4221 when using the segmented-buffer configuration, writable through 4222 PEM(0..1)_CFG_WR. 4223 However, the application must not change this field. */ 4224 uint32_t reserved_14_15 : 2; 4225 uint32_t data_depth : 14; /**< VC0 Posted Data Queue Depth 4226 Sets the number of entries in the Posted data queue for VC0 4227 when using the segmented-buffer configuration, writable 4228 through PEM(0..1)_CFG_WR. 4229 However, the application must not change this field. */ 4230#else 4231 uint32_t data_depth : 14; 4232 uint32_t reserved_14_15 : 2; 4233 uint32_t header_depth : 10; 4234 uint32_t reserved_26_31 : 6; 4235#endif 4236 } s; 4237 struct cvmx_pciercx_cfg490_s cn52xx; 4238 struct cvmx_pciercx_cfg490_s cn52xxp1; 4239 struct cvmx_pciercx_cfg490_s cn56xx; 4240 struct cvmx_pciercx_cfg490_s cn56xxp1; 4241 struct cvmx_pciercx_cfg490_s cn63xx; 4242 struct cvmx_pciercx_cfg490_s cn63xxp1; 4243}; 4244typedef union cvmx_pciercx_cfg490 cvmx_pciercx_cfg490_t; 4245 4246/** 4247 * cvmx_pcierc#_cfg491 4248 * 4249 * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 1 config space 4250 * (VC0 Non-Posted Buffer Depth) 4251 */ 4252union cvmx_pciercx_cfg491 4253{ 4254 uint32_t u32; 4255 struct cvmx_pciercx_cfg491_s 4256 { 4257#if __BYTE_ORDER == __BIG_ENDIAN 4258 uint32_t reserved_26_31 : 6; 4259 uint32_t header_depth : 10; /**< VC0 Non-Posted Header Queue Depth 4260 Sets the number of entries in the Non-Posted header queue for 4261 VC0 when using the segmented-buffer configuration, writable 4262 through PEM(0..1)_CFG_WR. 4263 However, the application must not change this field. */ 4264 uint32_t reserved_14_15 : 2; 4265 uint32_t data_depth : 14; /**< VC0 Non-Posted Data Queue Depth 4266 Sets the number of entries in the Non-Posted data queue for VC0 4267 when using the segmented-buffer configuration, writable 4268 through PEM(0..1)_CFG_WR. 4269 However, the application must not change this field. */ 4270#else 4271 uint32_t data_depth : 14; 4272 uint32_t reserved_14_15 : 2; 4273 uint32_t header_depth : 10; 4274 uint32_t reserved_26_31 : 6; 4275#endif 4276 } s; 4277 struct cvmx_pciercx_cfg491_s cn52xx; 4278 struct cvmx_pciercx_cfg491_s cn52xxp1; 4279 struct cvmx_pciercx_cfg491_s cn56xx; 4280 struct cvmx_pciercx_cfg491_s cn56xxp1; 4281 struct cvmx_pciercx_cfg491_s cn63xx; 4282 struct cvmx_pciercx_cfg491_s cn63xxp1; 4283}; 4284typedef union cvmx_pciercx_cfg491 cvmx_pciercx_cfg491_t; 4285 4286/** 4287 * cvmx_pcierc#_cfg492 4288 * 4289 * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 1 config space 4290 * (VC0 Completion Buffer Depth) 4291 */ 4292union cvmx_pciercx_cfg492 4293{ 4294 uint32_t u32; 4295 struct cvmx_pciercx_cfg492_s 4296 { 4297#if __BYTE_ORDER == __BIG_ENDIAN 4298 uint32_t reserved_26_31 : 6; 4299 uint32_t header_depth : 10; /**< VC0 Completion Header Queue Depth 4300 Sets the number of entries in the Completion header queue for 4301 VC0 when using the segmented-buffer configuration, writable 4302 through PEM(0..1)_CFG_WR. 4303 However, the application must not change this field. */ 4304 uint32_t reserved_14_15 : 2; 4305 uint32_t data_depth : 14; /**< VC0 Completion Data Queue Depth 4306 Sets the number of entries in the Completion data queue for VC0 4307 when using the segmented-buffer configuration, writable 4308 through PEM(0..1)_CFG_WR. 4309 However, the application must not change this field. */ 4310#else 4311 uint32_t data_depth : 14; 4312 uint32_t reserved_14_15 : 2; 4313 uint32_t header_depth : 10; 4314 uint32_t reserved_26_31 : 6; 4315#endif 4316 } s; 4317 struct cvmx_pciercx_cfg492_s cn52xx; 4318 struct cvmx_pciercx_cfg492_s cn52xxp1; 4319 struct cvmx_pciercx_cfg492_s cn56xx; 4320 struct cvmx_pciercx_cfg492_s cn56xxp1; 4321 struct cvmx_pciercx_cfg492_s cn63xx; 4322 struct cvmx_pciercx_cfg492_s cn63xxp1; 4323}; 4324typedef union cvmx_pciercx_cfg492 cvmx_pciercx_cfg492_t; 4325 4326/** 4327 * cvmx_pcierc#_cfg515 4328 * 4329 * PCIE_CFG515 = Five hundred sixteenth 32-bits of PCIE type 1 config space 4330 * (Port Logic Register (Gen2)) 4331 */ 4332union cvmx_pciercx_cfg515 4333{ 4334 uint32_t u32; 4335 struct cvmx_pciercx_cfg515_s 4336 { 4337#if __BYTE_ORDER == __BIG_ENDIAN 4338 uint32_t reserved_21_31 : 11; 4339 uint32_t s_d_e : 1; /**< SEL_DE_EMPHASIS 4340 Used to set the de-emphasis level for upstream ports. */ 4341 uint32_t ctcrb : 1; /**< Config Tx Compliance Receive Bit 4342 When set to 1, signals LTSSM to transmit TS ordered sets 4343 with the compliance receive bit assert (equal to 1). */ 4344 uint32_t cpyts : 1; /**< Config PHY Tx Swing 4345 Indicates the voltage level the PHY should drive. When set to 4346 1, indicates Full Swing. When set to 0, indicates Low Swing */ 4347 uint32_t dsc : 1; /**< Directed Speed Change 4348 Indicates to the LTSSM whether or not to initiate a speed 4349 change. */ 4350 uint32_t le : 9; /**< Lane Enable 4351 Indicates the number of lanes to check for exit from electrical 4352 idle in Polling.Active and Polling.Compliance. 1 = x1, 2 = x2, 4353 etc. Used to limit the maximum link width to ignore broken 4354 lanes that detect a receiver, but will not exit electrical 4355 idle and 4356 would otherwise prevent a valid link from being configured. */ 4357 uint32_t n_fts : 8; /**< N_FTS 4358 Sets the Number of Fast Training Sequences (N_FTS) that 4359 the core advertises as its N_FTS during GEN2 Link training. 4360 This value is used to inform the Link partner about the PHYs 4361 ability to recover synchronization after a low power state. 4362 Note: Do not set N_FTS to zero; doing so can cause the 4363 LTSSM to go into the recovery state when exiting from 4364 L0s. */ 4365#else 4366 uint32_t n_fts : 8; 4367 uint32_t le : 9; 4368 uint32_t dsc : 1; 4369 uint32_t cpyts : 1; 4370 uint32_t ctcrb : 1; 4371 uint32_t s_d_e : 1; 4372 uint32_t reserved_21_31 : 11; 4373#endif 4374 } s; 4375 struct cvmx_pciercx_cfg515_s cn63xx; 4376 struct cvmx_pciercx_cfg515_s cn63xxp1; 4377}; 4378typedef union cvmx_pciercx_cfg515 cvmx_pciercx_cfg515_t; 4379 4380/** 4381 * cvmx_pcierc#_cfg516 4382 * 4383 * PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 1 config space 4384 * (PHY Status Register) 4385 */ 4386union cvmx_pciercx_cfg516 4387{ 4388 uint32_t u32; 4389 struct cvmx_pciercx_cfg516_s 4390 { 4391#if __BYTE_ORDER == __BIG_ENDIAN 4392 uint32_t phy_stat : 32; /**< PHY Status */ 4393#else 4394 uint32_t phy_stat : 32; 4395#endif 4396 } s; 4397 struct cvmx_pciercx_cfg516_s cn52xx; 4398 struct cvmx_pciercx_cfg516_s cn52xxp1; 4399 struct cvmx_pciercx_cfg516_s cn56xx; 4400 struct cvmx_pciercx_cfg516_s cn56xxp1; 4401 struct cvmx_pciercx_cfg516_s cn63xx; 4402 struct cvmx_pciercx_cfg516_s cn63xxp1; 4403}; 4404typedef union cvmx_pciercx_cfg516 cvmx_pciercx_cfg516_t; 4405 4406/** 4407 * cvmx_pcierc#_cfg517 4408 * 4409 * PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 1 config space 4410 * (PHY Control Register) 4411 */ 4412union cvmx_pciercx_cfg517 4413{ 4414 uint32_t u32; 4415 struct cvmx_pciercx_cfg517_s 4416 { 4417#if __BYTE_ORDER == __BIG_ENDIAN 4418 uint32_t phy_ctrl : 32; /**< PHY Control */ 4419#else 4420 uint32_t phy_ctrl : 32; 4421#endif 4422 } s; 4423 struct cvmx_pciercx_cfg517_s cn52xx; 4424 struct cvmx_pciercx_cfg517_s cn52xxp1; 4425 struct cvmx_pciercx_cfg517_s cn56xx; 4426 struct cvmx_pciercx_cfg517_s cn56xxp1; 4427 struct cvmx_pciercx_cfg517_s cn63xx; 4428 struct cvmx_pciercx_cfg517_s cn63xxp1; 4429}; 4430typedef union cvmx_pciercx_cfg517 cvmx_pciercx_cfg517_t; 4431 4432#endif 4433