1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-pci-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon pci. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_PCI_TYPEDEFS_H__ 53#define __CVMX_PCI_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_PCI_BAR1_INDEXX(unsigned long offset) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) || 60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) || 61 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) || 62 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) || 63 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31))))) 64 cvmx_warn("CVMX_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset); 65 return 0x0000000000000100ull + ((offset) & 31) * 4; 66} 67#else 68#define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4) 69#endif 70#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71#define CVMX_PCI_BIST_REG CVMX_PCI_BIST_REG_FUNC() 72static inline uint64_t CVMX_PCI_BIST_REG_FUNC(void) 73{ 74 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX))) 75 cvmx_warn("CVMX_PCI_BIST_REG not supported on this chip\n"); 76 return 0x00000000000001C0ull; 77} 78#else 79#define CVMX_PCI_BIST_REG (0x00000000000001C0ull) 80#endif 81#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82#define CVMX_PCI_CFG00 CVMX_PCI_CFG00_FUNC() 83static inline uint64_t CVMX_PCI_CFG00_FUNC(void) 84{ 85 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 86 cvmx_warn("CVMX_PCI_CFG00 not supported on this chip\n"); 87 return 0x0000000000000000ull; 88} 89#else 90#define CVMX_PCI_CFG00 (0x0000000000000000ull) 91#endif 92#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 93#define CVMX_PCI_CFG01 CVMX_PCI_CFG01_FUNC() 94static inline uint64_t CVMX_PCI_CFG01_FUNC(void) 95{ 96 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 97 cvmx_warn("CVMX_PCI_CFG01 not supported on this chip\n"); 98 return 0x0000000000000004ull; 99} 100#else 101#define CVMX_PCI_CFG01 (0x0000000000000004ull) 102#endif 103#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104#define CVMX_PCI_CFG02 CVMX_PCI_CFG02_FUNC() 105static inline uint64_t CVMX_PCI_CFG02_FUNC(void) 106{ 107 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 108 cvmx_warn("CVMX_PCI_CFG02 not supported on this chip\n"); 109 return 0x0000000000000008ull; 110} 111#else 112#define CVMX_PCI_CFG02 (0x0000000000000008ull) 113#endif 114#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 115#define CVMX_PCI_CFG03 CVMX_PCI_CFG03_FUNC() 116static inline uint64_t CVMX_PCI_CFG03_FUNC(void) 117{ 118 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 119 cvmx_warn("CVMX_PCI_CFG03 not supported on this chip\n"); 120 return 0x000000000000000Cull; 121} 122#else 123#define CVMX_PCI_CFG03 (0x000000000000000Cull) 124#endif 125#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 126#define CVMX_PCI_CFG04 CVMX_PCI_CFG04_FUNC() 127static inline uint64_t CVMX_PCI_CFG04_FUNC(void) 128{ 129 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 130 cvmx_warn("CVMX_PCI_CFG04 not supported on this chip\n"); 131 return 0x0000000000000010ull; 132} 133#else 134#define CVMX_PCI_CFG04 (0x0000000000000010ull) 135#endif 136#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 137#define CVMX_PCI_CFG05 CVMX_PCI_CFG05_FUNC() 138static inline uint64_t CVMX_PCI_CFG05_FUNC(void) 139{ 140 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 141 cvmx_warn("CVMX_PCI_CFG05 not supported on this chip\n"); 142 return 0x0000000000000014ull; 143} 144#else 145#define CVMX_PCI_CFG05 (0x0000000000000014ull) 146#endif 147#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 148#define CVMX_PCI_CFG06 CVMX_PCI_CFG06_FUNC() 149static inline uint64_t CVMX_PCI_CFG06_FUNC(void) 150{ 151 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 152 cvmx_warn("CVMX_PCI_CFG06 not supported on this chip\n"); 153 return 0x0000000000000018ull; 154} 155#else 156#define CVMX_PCI_CFG06 (0x0000000000000018ull) 157#endif 158#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 159#define CVMX_PCI_CFG07 CVMX_PCI_CFG07_FUNC() 160static inline uint64_t CVMX_PCI_CFG07_FUNC(void) 161{ 162 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 163 cvmx_warn("CVMX_PCI_CFG07 not supported on this chip\n"); 164 return 0x000000000000001Cull; 165} 166#else 167#define CVMX_PCI_CFG07 (0x000000000000001Cull) 168#endif 169#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 170#define CVMX_PCI_CFG08 CVMX_PCI_CFG08_FUNC() 171static inline uint64_t CVMX_PCI_CFG08_FUNC(void) 172{ 173 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 174 cvmx_warn("CVMX_PCI_CFG08 not supported on this chip\n"); 175 return 0x0000000000000020ull; 176} 177#else 178#define CVMX_PCI_CFG08 (0x0000000000000020ull) 179#endif 180#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 181#define CVMX_PCI_CFG09 CVMX_PCI_CFG09_FUNC() 182static inline uint64_t CVMX_PCI_CFG09_FUNC(void) 183{ 184 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 185 cvmx_warn("CVMX_PCI_CFG09 not supported on this chip\n"); 186 return 0x0000000000000024ull; 187} 188#else 189#define CVMX_PCI_CFG09 (0x0000000000000024ull) 190#endif 191#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 192#define CVMX_PCI_CFG10 CVMX_PCI_CFG10_FUNC() 193static inline uint64_t CVMX_PCI_CFG10_FUNC(void) 194{ 195 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 196 cvmx_warn("CVMX_PCI_CFG10 not supported on this chip\n"); 197 return 0x0000000000000028ull; 198} 199#else 200#define CVMX_PCI_CFG10 (0x0000000000000028ull) 201#endif 202#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 203#define CVMX_PCI_CFG11 CVMX_PCI_CFG11_FUNC() 204static inline uint64_t CVMX_PCI_CFG11_FUNC(void) 205{ 206 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 207 cvmx_warn("CVMX_PCI_CFG11 not supported on this chip\n"); 208 return 0x000000000000002Cull; 209} 210#else 211#define CVMX_PCI_CFG11 (0x000000000000002Cull) 212#endif 213#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 214#define CVMX_PCI_CFG12 CVMX_PCI_CFG12_FUNC() 215static inline uint64_t CVMX_PCI_CFG12_FUNC(void) 216{ 217 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 218 cvmx_warn("CVMX_PCI_CFG12 not supported on this chip\n"); 219 return 0x0000000000000030ull; 220} 221#else 222#define CVMX_PCI_CFG12 (0x0000000000000030ull) 223#endif 224#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 225#define CVMX_PCI_CFG13 CVMX_PCI_CFG13_FUNC() 226static inline uint64_t CVMX_PCI_CFG13_FUNC(void) 227{ 228 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 229 cvmx_warn("CVMX_PCI_CFG13 not supported on this chip\n"); 230 return 0x0000000000000034ull; 231} 232#else 233#define CVMX_PCI_CFG13 (0x0000000000000034ull) 234#endif 235#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236#define CVMX_PCI_CFG15 CVMX_PCI_CFG15_FUNC() 237static inline uint64_t CVMX_PCI_CFG15_FUNC(void) 238{ 239 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 240 cvmx_warn("CVMX_PCI_CFG15 not supported on this chip\n"); 241 return 0x000000000000003Cull; 242} 243#else 244#define CVMX_PCI_CFG15 (0x000000000000003Cull) 245#endif 246#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 247#define CVMX_PCI_CFG16 CVMX_PCI_CFG16_FUNC() 248static inline uint64_t CVMX_PCI_CFG16_FUNC(void) 249{ 250 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 251 cvmx_warn("CVMX_PCI_CFG16 not supported on this chip\n"); 252 return 0x0000000000000040ull; 253} 254#else 255#define CVMX_PCI_CFG16 (0x0000000000000040ull) 256#endif 257#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 258#define CVMX_PCI_CFG17 CVMX_PCI_CFG17_FUNC() 259static inline uint64_t CVMX_PCI_CFG17_FUNC(void) 260{ 261 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 262 cvmx_warn("CVMX_PCI_CFG17 not supported on this chip\n"); 263 return 0x0000000000000044ull; 264} 265#else 266#define CVMX_PCI_CFG17 (0x0000000000000044ull) 267#endif 268#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 269#define CVMX_PCI_CFG18 CVMX_PCI_CFG18_FUNC() 270static inline uint64_t CVMX_PCI_CFG18_FUNC(void) 271{ 272 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 273 cvmx_warn("CVMX_PCI_CFG18 not supported on this chip\n"); 274 return 0x0000000000000048ull; 275} 276#else 277#define CVMX_PCI_CFG18 (0x0000000000000048ull) 278#endif 279#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 280#define CVMX_PCI_CFG19 CVMX_PCI_CFG19_FUNC() 281static inline uint64_t CVMX_PCI_CFG19_FUNC(void) 282{ 283 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 284 cvmx_warn("CVMX_PCI_CFG19 not supported on this chip\n"); 285 return 0x000000000000004Cull; 286} 287#else 288#define CVMX_PCI_CFG19 (0x000000000000004Cull) 289#endif 290#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 291#define CVMX_PCI_CFG20 CVMX_PCI_CFG20_FUNC() 292static inline uint64_t CVMX_PCI_CFG20_FUNC(void) 293{ 294 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 295 cvmx_warn("CVMX_PCI_CFG20 not supported on this chip\n"); 296 return 0x0000000000000050ull; 297} 298#else 299#define CVMX_PCI_CFG20 (0x0000000000000050ull) 300#endif 301#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 302#define CVMX_PCI_CFG21 CVMX_PCI_CFG21_FUNC() 303static inline uint64_t CVMX_PCI_CFG21_FUNC(void) 304{ 305 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 306 cvmx_warn("CVMX_PCI_CFG21 not supported on this chip\n"); 307 return 0x0000000000000054ull; 308} 309#else 310#define CVMX_PCI_CFG21 (0x0000000000000054ull) 311#endif 312#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 313#define CVMX_PCI_CFG22 CVMX_PCI_CFG22_FUNC() 314static inline uint64_t CVMX_PCI_CFG22_FUNC(void) 315{ 316 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 317 cvmx_warn("CVMX_PCI_CFG22 not supported on this chip\n"); 318 return 0x0000000000000058ull; 319} 320#else 321#define CVMX_PCI_CFG22 (0x0000000000000058ull) 322#endif 323#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 324#define CVMX_PCI_CFG56 CVMX_PCI_CFG56_FUNC() 325static inline uint64_t CVMX_PCI_CFG56_FUNC(void) 326{ 327 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 328 cvmx_warn("CVMX_PCI_CFG56 not supported on this chip\n"); 329 return 0x00000000000000E0ull; 330} 331#else 332#define CVMX_PCI_CFG56 (0x00000000000000E0ull) 333#endif 334#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 335#define CVMX_PCI_CFG57 CVMX_PCI_CFG57_FUNC() 336static inline uint64_t CVMX_PCI_CFG57_FUNC(void) 337{ 338 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 339 cvmx_warn("CVMX_PCI_CFG57 not supported on this chip\n"); 340 return 0x00000000000000E4ull; 341} 342#else 343#define CVMX_PCI_CFG57 (0x00000000000000E4ull) 344#endif 345#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 346#define CVMX_PCI_CFG58 CVMX_PCI_CFG58_FUNC() 347static inline uint64_t CVMX_PCI_CFG58_FUNC(void) 348{ 349 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 350 cvmx_warn("CVMX_PCI_CFG58 not supported on this chip\n"); 351 return 0x00000000000000E8ull; 352} 353#else 354#define CVMX_PCI_CFG58 (0x00000000000000E8ull) 355#endif 356#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 357#define CVMX_PCI_CFG59 CVMX_PCI_CFG59_FUNC() 358static inline uint64_t CVMX_PCI_CFG59_FUNC(void) 359{ 360 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 361 cvmx_warn("CVMX_PCI_CFG59 not supported on this chip\n"); 362 return 0x00000000000000ECull; 363} 364#else 365#define CVMX_PCI_CFG59 (0x00000000000000ECull) 366#endif 367#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 368#define CVMX_PCI_CFG60 CVMX_PCI_CFG60_FUNC() 369static inline uint64_t CVMX_PCI_CFG60_FUNC(void) 370{ 371 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 372 cvmx_warn("CVMX_PCI_CFG60 not supported on this chip\n"); 373 return 0x00000000000000F0ull; 374} 375#else 376#define CVMX_PCI_CFG60 (0x00000000000000F0ull) 377#endif 378#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 379#define CVMX_PCI_CFG61 CVMX_PCI_CFG61_FUNC() 380static inline uint64_t CVMX_PCI_CFG61_FUNC(void) 381{ 382 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 383 cvmx_warn("CVMX_PCI_CFG61 not supported on this chip\n"); 384 return 0x00000000000000F4ull; 385} 386#else 387#define CVMX_PCI_CFG61 (0x00000000000000F4ull) 388#endif 389#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 390#define CVMX_PCI_CFG62 CVMX_PCI_CFG62_FUNC() 391static inline uint64_t CVMX_PCI_CFG62_FUNC(void) 392{ 393 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 394 cvmx_warn("CVMX_PCI_CFG62 not supported on this chip\n"); 395 return 0x00000000000000F8ull; 396} 397#else 398#define CVMX_PCI_CFG62 (0x00000000000000F8ull) 399#endif 400#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 401#define CVMX_PCI_CFG63 CVMX_PCI_CFG63_FUNC() 402static inline uint64_t CVMX_PCI_CFG63_FUNC(void) 403{ 404 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 405 cvmx_warn("CVMX_PCI_CFG63 not supported on this chip\n"); 406 return 0x00000000000000FCull; 407} 408#else 409#define CVMX_PCI_CFG63 (0x00000000000000FCull) 410#endif 411#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 412#define CVMX_PCI_CNT_REG CVMX_PCI_CNT_REG_FUNC() 413static inline uint64_t CVMX_PCI_CNT_REG_FUNC(void) 414{ 415 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 416 cvmx_warn("CVMX_PCI_CNT_REG not supported on this chip\n"); 417 return 0x00000000000001B8ull; 418} 419#else 420#define CVMX_PCI_CNT_REG (0x00000000000001B8ull) 421#endif 422#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 423#define CVMX_PCI_CTL_STATUS_2 CVMX_PCI_CTL_STATUS_2_FUNC() 424static inline uint64_t CVMX_PCI_CTL_STATUS_2_FUNC(void) 425{ 426 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 427 cvmx_warn("CVMX_PCI_CTL_STATUS_2 not supported on this chip\n"); 428 return 0x000000000000018Cull; 429} 430#else 431#define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull) 432#endif 433#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 434static inline uint64_t CVMX_PCI_DBELL_X(unsigned long offset) 435{ 436 if (!( 437 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 438 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 439 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 440 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 441 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 442 cvmx_warn("CVMX_PCI_DBELL_X(%lu) is invalid on this chip\n", offset); 443 return 0x0000000000000080ull + ((offset) & 3) * 8; 444} 445#else 446#define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8) 447#endif 448#define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0) 449#define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1) 450#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 451static inline uint64_t CVMX_PCI_DMA_CNTX(unsigned long offset) 452{ 453 if (!( 454 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 455 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 456 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 457 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 458 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 459 cvmx_warn("CVMX_PCI_DMA_CNTX(%lu) is invalid on this chip\n", offset); 460 return 0x00000000000000A0ull + ((offset) & 1) * 8; 461} 462#else 463#define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8) 464#endif 465#define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0) 466#define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1) 467#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 468static inline uint64_t CVMX_PCI_DMA_INT_LEVX(unsigned long offset) 469{ 470 if (!( 471 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 472 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 473 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 474 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 475 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 476 cvmx_warn("CVMX_PCI_DMA_INT_LEVX(%lu) is invalid on this chip\n", offset); 477 return 0x00000000000000A4ull + ((offset) & 1) * 8; 478} 479#else 480#define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8) 481#endif 482#define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0) 483#define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1) 484#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485static inline uint64_t CVMX_PCI_DMA_TIMEX(unsigned long offset) 486{ 487 if (!( 488 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 489 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 490 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 491 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 492 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 493 cvmx_warn("CVMX_PCI_DMA_TIMEX(%lu) is invalid on this chip\n", offset); 494 return 0x00000000000000B0ull + ((offset) & 1) * 4; 495} 496#else 497#define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4) 498#endif 499#define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0) 500#define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1) 501#define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2) 502#define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3) 503#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 504static inline uint64_t CVMX_PCI_INSTR_COUNTX(unsigned long offset) 505{ 506 if (!( 507 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 508 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 509 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 510 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 511 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 512 cvmx_warn("CVMX_PCI_INSTR_COUNTX(%lu) is invalid on this chip\n", offset); 513 return 0x0000000000000084ull + ((offset) & 3) * 8; 514} 515#else 516#define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8) 517#endif 518#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 519#define CVMX_PCI_INT_ENB CVMX_PCI_INT_ENB_FUNC() 520static inline uint64_t CVMX_PCI_INT_ENB_FUNC(void) 521{ 522 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 523 cvmx_warn("CVMX_PCI_INT_ENB not supported on this chip\n"); 524 return 0x0000000000000038ull; 525} 526#else 527#define CVMX_PCI_INT_ENB (0x0000000000000038ull) 528#endif 529#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 530#define CVMX_PCI_INT_ENB2 CVMX_PCI_INT_ENB2_FUNC() 531static inline uint64_t CVMX_PCI_INT_ENB2_FUNC(void) 532{ 533 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 534 cvmx_warn("CVMX_PCI_INT_ENB2 not supported on this chip\n"); 535 return 0x00000000000001A0ull; 536} 537#else 538#define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull) 539#endif 540#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 541#define CVMX_PCI_INT_SUM CVMX_PCI_INT_SUM_FUNC() 542static inline uint64_t CVMX_PCI_INT_SUM_FUNC(void) 543{ 544 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 545 cvmx_warn("CVMX_PCI_INT_SUM not supported on this chip\n"); 546 return 0x0000000000000030ull; 547} 548#else 549#define CVMX_PCI_INT_SUM (0x0000000000000030ull) 550#endif 551#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 552#define CVMX_PCI_INT_SUM2 CVMX_PCI_INT_SUM2_FUNC() 553static inline uint64_t CVMX_PCI_INT_SUM2_FUNC(void) 554{ 555 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 556 cvmx_warn("CVMX_PCI_INT_SUM2 not supported on this chip\n"); 557 return 0x0000000000000198ull; 558} 559#else 560#define CVMX_PCI_INT_SUM2 (0x0000000000000198ull) 561#endif 562#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 563#define CVMX_PCI_MSI_RCV CVMX_PCI_MSI_RCV_FUNC() 564static inline uint64_t CVMX_PCI_MSI_RCV_FUNC(void) 565{ 566 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 567 cvmx_warn("CVMX_PCI_MSI_RCV not supported on this chip\n"); 568 return 0x00000000000000F0ull; 569} 570#else 571#define CVMX_PCI_MSI_RCV (0x00000000000000F0ull) 572#endif 573#define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0) 574#define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1) 575#define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2) 576#define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3) 577#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 578static inline uint64_t CVMX_PCI_PKTS_SENTX(unsigned long offset) 579{ 580 if (!( 581 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 582 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 583 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 584 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 585 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 586 cvmx_warn("CVMX_PCI_PKTS_SENTX(%lu) is invalid on this chip\n", offset); 587 return 0x0000000000000040ull + ((offset) & 3) * 16; 588} 589#else 590#define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16) 591#endif 592#define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0) 593#define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1) 594#define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2) 595#define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3) 596#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 597static inline uint64_t CVMX_PCI_PKTS_SENT_INT_LEVX(unsigned long offset) 598{ 599 if (!( 600 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 601 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 602 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 603 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 604 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 605 cvmx_warn("CVMX_PCI_PKTS_SENT_INT_LEVX(%lu) is invalid on this chip\n", offset); 606 return 0x0000000000000048ull + ((offset) & 3) * 16; 607} 608#else 609#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16) 610#endif 611#define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0) 612#define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1) 613#define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2) 614#define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3) 615#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 616static inline uint64_t CVMX_PCI_PKTS_SENT_TIMEX(unsigned long offset) 617{ 618 if (!( 619 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 620 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 621 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 622 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 623 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 624 cvmx_warn("CVMX_PCI_PKTS_SENT_TIMEX(%lu) is invalid on this chip\n", offset); 625 return 0x000000000000004Cull + ((offset) & 3) * 16; 626} 627#else 628#define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16) 629#endif 630#define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0) 631#define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1) 632#define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2) 633#define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3) 634#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 635static inline uint64_t CVMX_PCI_PKT_CREDITSX(unsigned long offset) 636{ 637 if (!( 638 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 639 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 640 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 641 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 642 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 643 cvmx_warn("CVMX_PCI_PKT_CREDITSX(%lu) is invalid on this chip\n", offset); 644 return 0x0000000000000044ull + ((offset) & 3) * 16; 645} 646#else 647#define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16) 648#endif 649#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 650#define CVMX_PCI_READ_CMD_6 CVMX_PCI_READ_CMD_6_FUNC() 651static inline uint64_t CVMX_PCI_READ_CMD_6_FUNC(void) 652{ 653 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 654 cvmx_warn("CVMX_PCI_READ_CMD_6 not supported on this chip\n"); 655 return 0x0000000000000180ull; 656} 657#else 658#define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull) 659#endif 660#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 661#define CVMX_PCI_READ_CMD_C CVMX_PCI_READ_CMD_C_FUNC() 662static inline uint64_t CVMX_PCI_READ_CMD_C_FUNC(void) 663{ 664 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 665 cvmx_warn("CVMX_PCI_READ_CMD_C not supported on this chip\n"); 666 return 0x0000000000000184ull; 667} 668#else 669#define CVMX_PCI_READ_CMD_C (0x0000000000000184ull) 670#endif 671#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 672#define CVMX_PCI_READ_CMD_E CVMX_PCI_READ_CMD_E_FUNC() 673static inline uint64_t CVMX_PCI_READ_CMD_E_FUNC(void) 674{ 675 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 676 cvmx_warn("CVMX_PCI_READ_CMD_E not supported on this chip\n"); 677 return 0x0000000000000188ull; 678} 679#else 680#define CVMX_PCI_READ_CMD_E (0x0000000000000188ull) 681#endif 682#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 683#define CVMX_PCI_READ_TIMEOUT CVMX_PCI_READ_TIMEOUT_FUNC() 684static inline uint64_t CVMX_PCI_READ_TIMEOUT_FUNC(void) 685{ 686 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 687 cvmx_warn("CVMX_PCI_READ_TIMEOUT not supported on this chip\n"); 688 return CVMX_ADD_IO_SEG(0x00011F00000000B0ull); 689} 690#else 691#define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull)) 692#endif 693#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 694#define CVMX_PCI_SCM_REG CVMX_PCI_SCM_REG_FUNC() 695static inline uint64_t CVMX_PCI_SCM_REG_FUNC(void) 696{ 697 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 698 cvmx_warn("CVMX_PCI_SCM_REG not supported on this chip\n"); 699 return 0x00000000000001A8ull; 700} 701#else 702#define CVMX_PCI_SCM_REG (0x00000000000001A8ull) 703#endif 704#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 705#define CVMX_PCI_TSR_REG CVMX_PCI_TSR_REG_FUNC() 706static inline uint64_t CVMX_PCI_TSR_REG_FUNC(void) 707{ 708 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 709 cvmx_warn("CVMX_PCI_TSR_REG not supported on this chip\n"); 710 return 0x00000000000001B0ull; 711} 712#else 713#define CVMX_PCI_TSR_REG (0x00000000000001B0ull) 714#endif 715#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716#define CVMX_PCI_WIN_RD_ADDR CVMX_PCI_WIN_RD_ADDR_FUNC() 717static inline uint64_t CVMX_PCI_WIN_RD_ADDR_FUNC(void) 718{ 719 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 720 cvmx_warn("CVMX_PCI_WIN_RD_ADDR not supported on this chip\n"); 721 return 0x0000000000000008ull; 722} 723#else 724#define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull) 725#endif 726#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 727#define CVMX_PCI_WIN_RD_DATA CVMX_PCI_WIN_RD_DATA_FUNC() 728static inline uint64_t CVMX_PCI_WIN_RD_DATA_FUNC(void) 729{ 730 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 731 cvmx_warn("CVMX_PCI_WIN_RD_DATA not supported on this chip\n"); 732 return 0x0000000000000020ull; 733} 734#else 735#define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull) 736#endif 737#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 738#define CVMX_PCI_WIN_WR_ADDR CVMX_PCI_WIN_WR_ADDR_FUNC() 739static inline uint64_t CVMX_PCI_WIN_WR_ADDR_FUNC(void) 740{ 741 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 742 cvmx_warn("CVMX_PCI_WIN_WR_ADDR not supported on this chip\n"); 743 return 0x0000000000000000ull; 744} 745#else 746#define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull) 747#endif 748#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 749#define CVMX_PCI_WIN_WR_DATA CVMX_PCI_WIN_WR_DATA_FUNC() 750static inline uint64_t CVMX_PCI_WIN_WR_DATA_FUNC(void) 751{ 752 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 753 cvmx_warn("CVMX_PCI_WIN_WR_DATA not supported on this chip\n"); 754 return 0x0000000000000010ull; 755} 756#else 757#define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull) 758#endif 759#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 760#define CVMX_PCI_WIN_WR_MASK CVMX_PCI_WIN_WR_MASK_FUNC() 761static inline uint64_t CVMX_PCI_WIN_WR_MASK_FUNC(void) 762{ 763 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 764 cvmx_warn("CVMX_PCI_WIN_WR_MASK not supported on this chip\n"); 765 return 0x0000000000000018ull; 766} 767#else 768#define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull) 769#endif 770 771/** 772 * cvmx_pci_bar1_index# 773 * 774 * PCI_BAR1_INDEXX = PCI IndexX Register 775 * 776 * Contains address index and control bits for access to memory ranges of Bar-1, 777 * when PCI supplied address-bits [26:22] == X. 778 */ 779union cvmx_pci_bar1_indexx 780{ 781 uint32_t u32; 782 struct cvmx_pci_bar1_indexx_s 783 { 784#if __BYTE_ORDER == __BIG_ENDIAN 785 uint32_t reserved_18_31 : 14; 786 uint32_t addr_idx : 14; /**< Address bits [35:22] sent to L2C */ 787 uint32_t ca : 1; /**< Set '1' when access is not to be cached in L2. */ 788 uint32_t end_swp : 2; /**< Endian Swap Mode */ 789 uint32_t addr_v : 1; /**< Set '1' when the selected address range is valid. */ 790#else 791 uint32_t addr_v : 1; 792 uint32_t end_swp : 2; 793 uint32_t ca : 1; 794 uint32_t addr_idx : 14; 795 uint32_t reserved_18_31 : 14; 796#endif 797 } s; 798 struct cvmx_pci_bar1_indexx_s cn30xx; 799 struct cvmx_pci_bar1_indexx_s cn31xx; 800 struct cvmx_pci_bar1_indexx_s cn38xx; 801 struct cvmx_pci_bar1_indexx_s cn38xxp2; 802 struct cvmx_pci_bar1_indexx_s cn50xx; 803 struct cvmx_pci_bar1_indexx_s cn58xx; 804 struct cvmx_pci_bar1_indexx_s cn58xxp1; 805}; 806typedef union cvmx_pci_bar1_indexx cvmx_pci_bar1_indexx_t; 807 808/** 809 * cvmx_pci_bist_reg 810 * 811 * PCI_BIST_REG = PCI PNI BIST Status Register 812 * 813 * Contains the bist results for the PNI memories. 814 */ 815union cvmx_pci_bist_reg 816{ 817 uint64_t u64; 818 struct cvmx_pci_bist_reg_s 819 { 820#if __BYTE_ORDER == __BIG_ENDIAN 821 uint64_t reserved_10_63 : 54; 822 uint64_t rsp_bs : 1; /**< Bist Status For b12_rsp_fifo_bist 823 The value of this register is available 100,000 824 core clocks + 21,000 pclks after: 825 Host Mode - deassertion of pci_rst_n 826 Non Host Mode - deassertion of pci_rst_n */ 827 uint64_t dma0_bs : 1; /**< Bist Status For dmao_count 828 The value of this register is available 100,000 829 core clocks + 21,000 pclks after: 830 Host Mode - deassertion of pci_rst_n 831 Non Host Mode - deassertion of pci_rst_n */ 832 uint64_t cmd0_bs : 1; /**< Bist Status For npi_cmd0_pni_am0 833 The value of this register is available 100,000 834 core clocks + 21,000 pclks after: 835 Host Mode - deassertion of pci_rst_n 836 Non Host Mode - deassertion of pci_rst_n */ 837 uint64_t cmd_bs : 1; /**< Bist Status For npi_cmd_pni_am1 838 The value of this register is available 100,000 839 core clocks + 21,000 pclks after: 840 Host Mode - deassertion of pci_rst_n 841 Non Host Mode - deassertion of pci_rst_n */ 842 uint64_t csr2p_bs : 1; /**< Bist Status For npi_csr_2_pni_am 843 The value of this register is available 100,000 844 core clocks + 21,000 pclks after: 845 Host Mode - deassertion of pci_rst_n 846 Non Host Mode - deassertion of pci_rst_n */ 847 uint64_t csrr_bs : 1; /**< Bist Status For npi_csr_rsp_2_pni_am 848 The value of this register is available 100,000 849 core clocks + 21,000 pclks after: 850 Host Mode - deassertion of pci_rst_n 851 Non Host Mode - deassertion of pci_rst_n */ 852 uint64_t rsp2p_bs : 1; /**< Bist Status For npi_rsp_2_pni_am 853 The value of this register is available 100,000 854 core clocks + 21,000 pclks after: 855 Host Mode - deassertion of pci_rst_n 856 Non Host Mode - deassertion of pci_rst_n */ 857 uint64_t csr2n_bs : 1; /**< Bist Status For pni_csr_2_npi_am 858 The value of this register is available 100,000 859 core clocks + 21,000 pclks after: 860 Host Mode - deassertion of pci_rst_n 861 Non Host Mode - deassertion of pci_rst_n */ 862 uint64_t dat2n_bs : 1; /**< Bist Status For pni_data_2_npi_am 863 The value of this register is available 100,000 864 core clocks + 21,000 pclks after: 865 Host Mode - deassertion of pci_rst_n 866 Non Host Mode - deassertion of pci_rst_n */ 867 uint64_t dbg2n_bs : 1; /**< Bist Status For pni_dbg_data_2_npi_am 868 The value of this register is available 100,000 869 core clocks + 21,000 pclks after: 870 Host Mode - deassertion of pci_rst_n 871 Non Host Mode - deassertion of pci_rst_n */ 872#else 873 uint64_t dbg2n_bs : 1; 874 uint64_t dat2n_bs : 1; 875 uint64_t csr2n_bs : 1; 876 uint64_t rsp2p_bs : 1; 877 uint64_t csrr_bs : 1; 878 uint64_t csr2p_bs : 1; 879 uint64_t cmd_bs : 1; 880 uint64_t cmd0_bs : 1; 881 uint64_t dma0_bs : 1; 882 uint64_t rsp_bs : 1; 883 uint64_t reserved_10_63 : 54; 884#endif 885 } s; 886 struct cvmx_pci_bist_reg_s cn50xx; 887}; 888typedef union cvmx_pci_bist_reg cvmx_pci_bist_reg_t; 889 890/** 891 * cvmx_pci_cfg00 892 * 893 * Registers at address 0x1000 -> 0x17FF are PNI 894 * Start at 0x100 into range 895 * these are shifted by 2 to the left to make address 896 * Registers at address 0x1800 -> 0x18FF are CFG 897 * these are shifted by 2 to the left to make address 898 * 899 * PCI_CFG00 = First 32-bits of PCI config space (PCI Vendor + Device) 900 * 901 * This register contains the first 32-bits of the PCI config space registers 902 */ 903union cvmx_pci_cfg00 904{ 905 uint32_t u32; 906 struct cvmx_pci_cfg00_s 907 { 908#if __BYTE_ORDER == __BIG_ENDIAN 909 uint32_t devid : 16; /**< This is the device ID for OCTEON (90nm shhrink) */ 910 uint32_t vendid : 16; /**< This is the Cavium's vendor ID */ 911#else 912 uint32_t vendid : 16; 913 uint32_t devid : 16; 914#endif 915 } s; 916 struct cvmx_pci_cfg00_s cn30xx; 917 struct cvmx_pci_cfg00_s cn31xx; 918 struct cvmx_pci_cfg00_s cn38xx; 919 struct cvmx_pci_cfg00_s cn38xxp2; 920 struct cvmx_pci_cfg00_s cn50xx; 921 struct cvmx_pci_cfg00_s cn58xx; 922 struct cvmx_pci_cfg00_s cn58xxp1; 923}; 924typedef union cvmx_pci_cfg00 cvmx_pci_cfg00_t; 925 926/** 927 * cvmx_pci_cfg01 928 * 929 * PCI_CFG01 = Second 32-bits of PCI config space (Command/Status Register) 930 * 931 */ 932union cvmx_pci_cfg01 933{ 934 uint32_t u32; 935 struct cvmx_pci_cfg01_s 936 { 937#if __BYTE_ORDER == __BIG_ENDIAN 938 uint32_t dpe : 1; /**< Detected Parity Error */ 939 uint32_t sse : 1; /**< Signaled System Error */ 940 uint32_t rma : 1; /**< Received Master Abort */ 941 uint32_t rta : 1; /**< Received Target Abort */ 942 uint32_t sta : 1; /**< Signaled Target Abort */ 943 uint32_t devt : 2; /**< DEVSEL# timing (for PCI only/for PCIX = don't care) */ 944 uint32_t mdpe : 1; /**< Master Data Parity Error */ 945 uint32_t fbb : 1; /**< Fast Back-to-Back Transactions Capable 946 Mode Dependent (1 = PCI Mode / 0 = PCIX Mode) */ 947 uint32_t reserved_22_22 : 1; 948 uint32_t m66 : 1; /**< 66MHz Capable */ 949 uint32_t cle : 1; /**< Capabilities List Enable */ 950 uint32_t i_stat : 1; /**< When INTx# is asserted by OCTEON this bit will be set. 951 When deasserted by OCTEON this bit will be cleared. */ 952 uint32_t reserved_11_18 : 8; 953 uint32_t i_dis : 1; /**< When asserted '1' disables the generation of INTx# 954 by OCTEON. When disabled '0' allows assertion of INTx# 955 by OCTEON. */ 956 uint32_t fbbe : 1; /**< Fast Back to Back Transaction Enable */ 957 uint32_t see : 1; /**< System Error Enable */ 958 uint32_t ads : 1; /**< Address/Data Stepping 959 NOTE: Octeon does NOT support address/data stepping. */ 960 uint32_t pee : 1; /**< PERR# Enable */ 961 uint32_t vps : 1; /**< VGA Palette Snooping */ 962 uint32_t mwice : 1; /**< Memory Write & Invalidate Command Enable */ 963 uint32_t scse : 1; /**< Special Cycle Snooping Enable */ 964 uint32_t me : 1; /**< Master Enable 965 Must be set for OCTEON to master a PCI/PCI-X 966 transaction. This should always be set any time 967 that OCTEON is connected to a PCI/PCI-X bus. */ 968 uint32_t msae : 1; /**< Memory Space Access Enable 969 Must be set to recieve a PCI/PCI-X memory space 970 transaction. This must always be set any time that 971 OCTEON is connected to a PCI/PCI-X bus. */ 972 uint32_t isae : 1; /**< I/O Space Access Enable 973 NOTE: For OCTEON, this bit MUST NEVER be set 974 (it is read-only and OCTEON does not respond to I/O 975 Space accesses). */ 976#else 977 uint32_t isae : 1; 978 uint32_t msae : 1; 979 uint32_t me : 1; 980 uint32_t scse : 1; 981 uint32_t mwice : 1; 982 uint32_t vps : 1; 983 uint32_t pee : 1; 984 uint32_t ads : 1; 985 uint32_t see : 1; 986 uint32_t fbbe : 1; 987 uint32_t i_dis : 1; 988 uint32_t reserved_11_18 : 8; 989 uint32_t i_stat : 1; 990 uint32_t cle : 1; 991 uint32_t m66 : 1; 992 uint32_t reserved_22_22 : 1; 993 uint32_t fbb : 1; 994 uint32_t mdpe : 1; 995 uint32_t devt : 2; 996 uint32_t sta : 1; 997 uint32_t rta : 1; 998 uint32_t rma : 1; 999 uint32_t sse : 1; 1000 uint32_t dpe : 1; 1001#endif 1002 } s; 1003 struct cvmx_pci_cfg01_s cn30xx; 1004 struct cvmx_pci_cfg01_s cn31xx; 1005 struct cvmx_pci_cfg01_s cn38xx; 1006 struct cvmx_pci_cfg01_s cn38xxp2; 1007 struct cvmx_pci_cfg01_s cn50xx; 1008 struct cvmx_pci_cfg01_s cn58xx; 1009 struct cvmx_pci_cfg01_s cn58xxp1; 1010}; 1011typedef union cvmx_pci_cfg01 cvmx_pci_cfg01_t; 1012 1013/** 1014 * cvmx_pci_cfg02 1015 * 1016 * PCI_CFG02 = Third 32-bits of PCI config space (Class Code / Revision ID) 1017 * 1018 */ 1019union cvmx_pci_cfg02 1020{ 1021 uint32_t u32; 1022 struct cvmx_pci_cfg02_s 1023 { 1024#if __BYTE_ORDER == __BIG_ENDIAN 1025 uint32_t cc : 24; /**< Class Code (Processor/MIPS) 1026 (was 0x100000 in pass 1 and pass 2) */ 1027 uint32_t rid : 8; /**< Revision ID 1028 (0 in pass 1, 1 in pass 1.1, 8 in pass 2.0) */ 1029#else 1030 uint32_t rid : 8; 1031 uint32_t cc : 24; 1032#endif 1033 } s; 1034 struct cvmx_pci_cfg02_s cn30xx; 1035 struct cvmx_pci_cfg02_s cn31xx; 1036 struct cvmx_pci_cfg02_s cn38xx; 1037 struct cvmx_pci_cfg02_s cn38xxp2; 1038 struct cvmx_pci_cfg02_s cn50xx; 1039 struct cvmx_pci_cfg02_s cn58xx; 1040 struct cvmx_pci_cfg02_s cn58xxp1; 1041}; 1042typedef union cvmx_pci_cfg02 cvmx_pci_cfg02_t; 1043 1044/** 1045 * cvmx_pci_cfg03 1046 * 1047 * PCI_CFG03 = Fourth 32-bits of PCI config space (BIST, HEADER Type, Latency timer, line size) 1048 * 1049 */ 1050union cvmx_pci_cfg03 1051{ 1052 uint32_t u32; 1053 struct cvmx_pci_cfg03_s 1054 { 1055#if __BYTE_ORDER == __BIG_ENDIAN 1056 uint32_t bcap : 1; /**< BIST Capable */ 1057 uint32_t brb : 1; /**< BIST Request/busy bit 1058 Note: OCTEON does not support PCI BIST, therefore 1059 this bit should remain zero. */ 1060 uint32_t reserved_28_29 : 2; 1061 uint32_t bcod : 4; /**< BIST Code */ 1062 uint32_t ht : 8; /**< Header Type (Type 0) */ 1063 uint32_t lt : 8; /**< Latency Timer 1064 (0=PCI) (0=PCI) 1065 (0x40=PCIX) (0x40=PCIX) */ 1066 uint32_t cls : 8; /**< Cache Line Size */ 1067#else 1068 uint32_t cls : 8; 1069 uint32_t lt : 8; 1070 uint32_t ht : 8; 1071 uint32_t bcod : 4; 1072 uint32_t reserved_28_29 : 2; 1073 uint32_t brb : 1; 1074 uint32_t bcap : 1; 1075#endif 1076 } s; 1077 struct cvmx_pci_cfg03_s cn30xx; 1078 struct cvmx_pci_cfg03_s cn31xx; 1079 struct cvmx_pci_cfg03_s cn38xx; 1080 struct cvmx_pci_cfg03_s cn38xxp2; 1081 struct cvmx_pci_cfg03_s cn50xx; 1082 struct cvmx_pci_cfg03_s cn58xx; 1083 struct cvmx_pci_cfg03_s cn58xxp1; 1084}; 1085typedef union cvmx_pci_cfg03 cvmx_pci_cfg03_t; 1086 1087/** 1088 * cvmx_pci_cfg04 1089 * 1090 * PCI_CFG04 = Fifth 32-bits of PCI config space (Base Address Register 0 - Low) 1091 * 1092 * Description: BAR0: 4KB 64-bit Prefetchable Memory Space 1093 * [0]: 0 (Memory Space) 1094 * [2:1]: 2 (64bit memory decoder) 1095 * [3]: 1 (Prefetchable) 1096 * [11:4]: RAZ (to imply 4KB space) 1097 * [31:12]: RW (User may define base address) 1098 */ 1099union cvmx_pci_cfg04 1100{ 1101 uint32_t u32; 1102 struct cvmx_pci_cfg04_s 1103 { 1104#if __BYTE_ORDER == __BIG_ENDIAN 1105 uint32_t lbase : 20; /**< Base Address[31:12] 1106 Base Address[30:12] read as zero if 1107 PCI_CTL_STATUS_2[BB0] is set (in pass 3+) */ 1108 uint32_t lbasez : 8; /**< Base Address[11:4] (Read as Zero) */ 1109 uint32_t pf : 1; /**< Prefetchable Space */ 1110 uint32_t typ : 2; /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */ 1111 uint32_t mspc : 1; /**< Memory Space Indicator */ 1112#else 1113 uint32_t mspc : 1; 1114 uint32_t typ : 2; 1115 uint32_t pf : 1; 1116 uint32_t lbasez : 8; 1117 uint32_t lbase : 20; 1118#endif 1119 } s; 1120 struct cvmx_pci_cfg04_s cn30xx; 1121 struct cvmx_pci_cfg04_s cn31xx; 1122 struct cvmx_pci_cfg04_s cn38xx; 1123 struct cvmx_pci_cfg04_s cn38xxp2; 1124 struct cvmx_pci_cfg04_s cn50xx; 1125 struct cvmx_pci_cfg04_s cn58xx; 1126 struct cvmx_pci_cfg04_s cn58xxp1; 1127}; 1128typedef union cvmx_pci_cfg04 cvmx_pci_cfg04_t; 1129 1130/** 1131 * cvmx_pci_cfg05 1132 * 1133 * PCI_CFG05 = Sixth 32-bits of PCI config space (Base Address Register 0 - High) 1134 * 1135 */ 1136union cvmx_pci_cfg05 1137{ 1138 uint32_t u32; 1139 struct cvmx_pci_cfg05_s 1140 { 1141#if __BYTE_ORDER == __BIG_ENDIAN 1142 uint32_t hbase : 32; /**< Base Address[63:32] */ 1143#else 1144 uint32_t hbase : 32; 1145#endif 1146 } s; 1147 struct cvmx_pci_cfg05_s cn30xx; 1148 struct cvmx_pci_cfg05_s cn31xx; 1149 struct cvmx_pci_cfg05_s cn38xx; 1150 struct cvmx_pci_cfg05_s cn38xxp2; 1151 struct cvmx_pci_cfg05_s cn50xx; 1152 struct cvmx_pci_cfg05_s cn58xx; 1153 struct cvmx_pci_cfg05_s cn58xxp1; 1154}; 1155typedef union cvmx_pci_cfg05 cvmx_pci_cfg05_t; 1156 1157/** 1158 * cvmx_pci_cfg06 1159 * 1160 * PCI_CFG06 = Seventh 32-bits of PCI config space (Base Address Register 1 - Low) 1161 * 1162 * Description: BAR1: 128MB 64-bit Prefetchable Memory Space 1163 * [0]: 0 (Memory Space) 1164 * [2:1]: 2 (64bit memory decoder) 1165 * [3]: 1 (Prefetchable) 1166 * [26:4]: RAZ (to imply 128MB space) 1167 * [31:27]: RW (User may define base address) 1168 */ 1169union cvmx_pci_cfg06 1170{ 1171 uint32_t u32; 1172 struct cvmx_pci_cfg06_s 1173 { 1174#if __BYTE_ORDER == __BIG_ENDIAN 1175 uint32_t lbase : 5; /**< Base Address[31:27] 1176 In pass 3+: 1177 Base Address[29:27] read as zero if 1178 PCI_CTL_STATUS_2[BB1] is set 1179 Base Address[30] reads as zero if 1180 PCI_CTL_STATUS_2[BB1] is set and 1181 PCI_CTL_STATUS_2[BB1_SIZE] is set */ 1182 uint32_t lbasez : 23; /**< Base Address[26:4] (Read as Zero) */ 1183 uint32_t pf : 1; /**< Prefetchable Space */ 1184 uint32_t typ : 2; /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */ 1185 uint32_t mspc : 1; /**< Memory Space Indicator */ 1186#else 1187 uint32_t mspc : 1; 1188 uint32_t typ : 2; 1189 uint32_t pf : 1; 1190 uint32_t lbasez : 23; 1191 uint32_t lbase : 5; 1192#endif 1193 } s; 1194 struct cvmx_pci_cfg06_s cn30xx; 1195 struct cvmx_pci_cfg06_s cn31xx; 1196 struct cvmx_pci_cfg06_s cn38xx; 1197 struct cvmx_pci_cfg06_s cn38xxp2; 1198 struct cvmx_pci_cfg06_s cn50xx; 1199 struct cvmx_pci_cfg06_s cn58xx; 1200 struct cvmx_pci_cfg06_s cn58xxp1; 1201}; 1202typedef union cvmx_pci_cfg06 cvmx_pci_cfg06_t; 1203 1204/** 1205 * cvmx_pci_cfg07 1206 * 1207 * PCI_CFG07 = Eighth 32-bits of PCI config space (Base Address Register 1 - High) 1208 * 1209 */ 1210union cvmx_pci_cfg07 1211{ 1212 uint32_t u32; 1213 struct cvmx_pci_cfg07_s 1214 { 1215#if __BYTE_ORDER == __BIG_ENDIAN 1216 uint32_t hbase : 32; /**< Base Address[63:32] */ 1217#else 1218 uint32_t hbase : 32; 1219#endif 1220 } s; 1221 struct cvmx_pci_cfg07_s cn30xx; 1222 struct cvmx_pci_cfg07_s cn31xx; 1223 struct cvmx_pci_cfg07_s cn38xx; 1224 struct cvmx_pci_cfg07_s cn38xxp2; 1225 struct cvmx_pci_cfg07_s cn50xx; 1226 struct cvmx_pci_cfg07_s cn58xx; 1227 struct cvmx_pci_cfg07_s cn58xxp1; 1228}; 1229typedef union cvmx_pci_cfg07 cvmx_pci_cfg07_t; 1230 1231/** 1232 * cvmx_pci_cfg08 1233 * 1234 * PCI_CFG08 = Ninth 32-bits of PCI config space (Base Address Register 2 - Low) 1235 * 1236 * Description: BAR1: 2^39 (512GB) 64-bit Prefetchable Memory Space 1237 * [0]: 0 (Memory Space) 1238 * [2:1]: 2 (64bit memory decoder) 1239 * [3]: 1 (Prefetchable) 1240 * [31:4]: RAZ 1241 */ 1242union cvmx_pci_cfg08 1243{ 1244 uint32_t u32; 1245 struct cvmx_pci_cfg08_s 1246 { 1247#if __BYTE_ORDER == __BIG_ENDIAN 1248 uint32_t lbasez : 28; /**< Base Address[31:4] (Read as Zero) */ 1249 uint32_t pf : 1; /**< Prefetchable Space */ 1250 uint32_t typ : 2; /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */ 1251 uint32_t mspc : 1; /**< Memory Space Indicator */ 1252#else 1253 uint32_t mspc : 1; 1254 uint32_t typ : 2; 1255 uint32_t pf : 1; 1256 uint32_t lbasez : 28; 1257#endif 1258 } s; 1259 struct cvmx_pci_cfg08_s cn30xx; 1260 struct cvmx_pci_cfg08_s cn31xx; 1261 struct cvmx_pci_cfg08_s cn38xx; 1262 struct cvmx_pci_cfg08_s cn38xxp2; 1263 struct cvmx_pci_cfg08_s cn50xx; 1264 struct cvmx_pci_cfg08_s cn58xx; 1265 struct cvmx_pci_cfg08_s cn58xxp1; 1266}; 1267typedef union cvmx_pci_cfg08 cvmx_pci_cfg08_t; 1268 1269/** 1270 * cvmx_pci_cfg09 1271 * 1272 * PCI_CFG09 = Tenth 32-bits of PCI config space (Base Address Register 2 - High) 1273 * 1274 */ 1275union cvmx_pci_cfg09 1276{ 1277 uint32_t u32; 1278 struct cvmx_pci_cfg09_s 1279 { 1280#if __BYTE_ORDER == __BIG_ENDIAN 1281 uint32_t hbase : 25; /**< Base Address[63:39] */ 1282 uint32_t hbasez : 7; /**< Base Address[38:31] (Read as Zero) */ 1283#else 1284 uint32_t hbasez : 7; 1285 uint32_t hbase : 25; 1286#endif 1287 } s; 1288 struct cvmx_pci_cfg09_s cn30xx; 1289 struct cvmx_pci_cfg09_s cn31xx; 1290 struct cvmx_pci_cfg09_s cn38xx; 1291 struct cvmx_pci_cfg09_s cn38xxp2; 1292 struct cvmx_pci_cfg09_s cn50xx; 1293 struct cvmx_pci_cfg09_s cn58xx; 1294 struct cvmx_pci_cfg09_s cn58xxp1; 1295}; 1296typedef union cvmx_pci_cfg09 cvmx_pci_cfg09_t; 1297 1298/** 1299 * cvmx_pci_cfg10 1300 * 1301 * PCI_CFG10 = Eleventh 32-bits of PCI config space (Card Bus CIS Pointer) 1302 * 1303 */ 1304union cvmx_pci_cfg10 1305{ 1306 uint32_t u32; 1307 struct cvmx_pci_cfg10_s 1308 { 1309#if __BYTE_ORDER == __BIG_ENDIAN 1310 uint32_t cisp : 32; /**< CardBus CIS Pointer (UNUSED) */ 1311#else 1312 uint32_t cisp : 32; 1313#endif 1314 } s; 1315 struct cvmx_pci_cfg10_s cn30xx; 1316 struct cvmx_pci_cfg10_s cn31xx; 1317 struct cvmx_pci_cfg10_s cn38xx; 1318 struct cvmx_pci_cfg10_s cn38xxp2; 1319 struct cvmx_pci_cfg10_s cn50xx; 1320 struct cvmx_pci_cfg10_s cn58xx; 1321 struct cvmx_pci_cfg10_s cn58xxp1; 1322}; 1323typedef union cvmx_pci_cfg10 cvmx_pci_cfg10_t; 1324 1325/** 1326 * cvmx_pci_cfg11 1327 * 1328 * PCI_CFG11 = Twelfth 32-bits of PCI config space (SubSystem ID/Subsystem Vendor ID Register) 1329 * 1330 */ 1331union cvmx_pci_cfg11 1332{ 1333 uint32_t u32; 1334 struct cvmx_pci_cfg11_s 1335 { 1336#if __BYTE_ORDER == __BIG_ENDIAN 1337 uint32_t ssid : 16; /**< SubSystem ID */ 1338 uint32_t ssvid : 16; /**< Subsystem Vendor ID */ 1339#else 1340 uint32_t ssvid : 16; 1341 uint32_t ssid : 16; 1342#endif 1343 } s; 1344 struct cvmx_pci_cfg11_s cn30xx; 1345 struct cvmx_pci_cfg11_s cn31xx; 1346 struct cvmx_pci_cfg11_s cn38xx; 1347 struct cvmx_pci_cfg11_s cn38xxp2; 1348 struct cvmx_pci_cfg11_s cn50xx; 1349 struct cvmx_pci_cfg11_s cn58xx; 1350 struct cvmx_pci_cfg11_s cn58xxp1; 1351}; 1352typedef union cvmx_pci_cfg11 cvmx_pci_cfg11_t; 1353 1354/** 1355 * cvmx_pci_cfg12 1356 * 1357 * PCI_CFG12 = Thirteenth 32-bits of PCI config space (Expansion ROM Base Address Register) 1358 * 1359 */ 1360union cvmx_pci_cfg12 1361{ 1362 uint32_t u32; 1363 struct cvmx_pci_cfg12_s 1364 { 1365#if __BYTE_ORDER == __BIG_ENDIAN 1366 uint32_t erbar : 16; /**< Expansion ROM Base Address[31:16] 64KB in size */ 1367 uint32_t erbarz : 5; /**< Expansion ROM Base Base Address (Read as Zero) */ 1368 uint32_t reserved_1_10 : 10; 1369 uint32_t erbar_en : 1; /**< Expansion ROM Address Decode Enable */ 1370#else 1371 uint32_t erbar_en : 1; 1372 uint32_t reserved_1_10 : 10; 1373 uint32_t erbarz : 5; 1374 uint32_t erbar : 16; 1375#endif 1376 } s; 1377 struct cvmx_pci_cfg12_s cn30xx; 1378 struct cvmx_pci_cfg12_s cn31xx; 1379 struct cvmx_pci_cfg12_s cn38xx; 1380 struct cvmx_pci_cfg12_s cn38xxp2; 1381 struct cvmx_pci_cfg12_s cn50xx; 1382 struct cvmx_pci_cfg12_s cn58xx; 1383 struct cvmx_pci_cfg12_s cn58xxp1; 1384}; 1385typedef union cvmx_pci_cfg12 cvmx_pci_cfg12_t; 1386 1387/** 1388 * cvmx_pci_cfg13 1389 * 1390 * PCI_CFG13 = Fourteenth 32-bits of PCI config space (Capabilities Pointer Register) 1391 * 1392 */ 1393union cvmx_pci_cfg13 1394{ 1395 uint32_t u32; 1396 struct cvmx_pci_cfg13_s 1397 { 1398#if __BYTE_ORDER == __BIG_ENDIAN 1399 uint32_t reserved_8_31 : 24; 1400 uint32_t cp : 8; /**< Capabilities Pointer */ 1401#else 1402 uint32_t cp : 8; 1403 uint32_t reserved_8_31 : 24; 1404#endif 1405 } s; 1406 struct cvmx_pci_cfg13_s cn30xx; 1407 struct cvmx_pci_cfg13_s cn31xx; 1408 struct cvmx_pci_cfg13_s cn38xx; 1409 struct cvmx_pci_cfg13_s cn38xxp2; 1410 struct cvmx_pci_cfg13_s cn50xx; 1411 struct cvmx_pci_cfg13_s cn58xx; 1412 struct cvmx_pci_cfg13_s cn58xxp1; 1413}; 1414typedef union cvmx_pci_cfg13 cvmx_pci_cfg13_t; 1415 1416/** 1417 * cvmx_pci_cfg15 1418 * 1419 * PCI_CFG15 = Sixteenth 32-bits of PCI config space (INT/ARB/LATENCY Register) 1420 * 1421 */ 1422union cvmx_pci_cfg15 1423{ 1424 uint32_t u32; 1425 struct cvmx_pci_cfg15_s 1426 { 1427#if __BYTE_ORDER == __BIG_ENDIAN 1428 uint32_t ml : 8; /**< Maximum Latency */ 1429 uint32_t mg : 8; /**< Minimum Grant */ 1430 uint32_t inta : 8; /**< Interrupt Pin (INTA#) */ 1431 uint32_t il : 8; /**< Interrupt Line */ 1432#else 1433 uint32_t il : 8; 1434 uint32_t inta : 8; 1435 uint32_t mg : 8; 1436 uint32_t ml : 8; 1437#endif 1438 } s; 1439 struct cvmx_pci_cfg15_s cn30xx; 1440 struct cvmx_pci_cfg15_s cn31xx; 1441 struct cvmx_pci_cfg15_s cn38xx; 1442 struct cvmx_pci_cfg15_s cn38xxp2; 1443 struct cvmx_pci_cfg15_s cn50xx; 1444 struct cvmx_pci_cfg15_s cn58xx; 1445 struct cvmx_pci_cfg15_s cn58xxp1; 1446}; 1447typedef union cvmx_pci_cfg15 cvmx_pci_cfg15_t; 1448 1449/** 1450 * cvmx_pci_cfg16 1451 * 1452 * PCI_CFG16 = Seventeenth 32-bits of PCI config space (Target Implementation Register) 1453 * 1454 */ 1455union cvmx_pci_cfg16 1456{ 1457 uint32_t u32; 1458 struct cvmx_pci_cfg16_s 1459 { 1460#if __BYTE_ORDER == __BIG_ENDIAN 1461 uint32_t trdnpr : 1; /**< Target Read Delayed Transaction for I/O and 1462 non-prefetchable regions discarded. */ 1463 uint32_t trdard : 1; /**< Target Read Delayed Transaction for all regions 1464 discarded. */ 1465 uint32_t rdsati : 1; /**< Target(I/O and Memory) Read Delayed/Split at 1466 timeout/immediately (default timeout). 1467 Note: OCTEON requires that this bit MBZ(must be zero). */ 1468 uint32_t trdrs : 1; /**< Target(I/O and Memory) Read Delayed/Split or Retry 1469 select (of the application interface is not ready) 1470 0 = Delayed Split Transaction 1471 1 = Retry Transaction (always Immediate Retry, no 1472 AT_REQ to application). */ 1473 uint32_t trtae : 1; /**< Target(I/O and Memory) Read Target Abort Enable 1474 (if application interface is not ready at the 1475 latency timeout). 1476 Note: OCTEON as target will never target-abort, 1477 therefore this bit should never be set. */ 1478 uint32_t twsei : 1; /**< Target(I/O) Write Split Enable (at timeout / 1479 immediately; default timeout) */ 1480 uint32_t twsen : 1; /**< T(I/O) write split Enable (if the application 1481 interface is not ready) */ 1482 uint32_t twtae : 1; /**< Target(I/O and Memory) Write Target Abort Enable 1483 (if the application interface is not ready at the 1484 start of the cycle). 1485 Note: OCTEON as target will never target-abort, 1486 therefore this bit should never be set. */ 1487 uint32_t tmae : 1; /**< Target(Read/Write) Master Abort Enable; check 1488 at the start of each transaction. 1489 Note: This bit can be used to force a Master 1490 Abort when OCTEON is acting as the intended target 1491 device. */ 1492 uint32_t tslte : 3; /**< Target Subsequent(2nd-last) Latency Timeout Enable 1493 Valid range: [1..7] and 0=8. */ 1494 uint32_t tilt : 4; /**< Target Initial(1st data) Latency Timeout in PCI 1495 ModeValid range: [8..15] and 0=16. */ 1496 uint32_t pbe : 12; /**< Programmable Boundary Enable to disconnect/prefetch 1497 for target burst read cycles to prefetchable 1498 region in PCI. A value of 1 indicates end of 1499 boundary (64 KB down to 16 Bytes). */ 1500 uint32_t dppmr : 1; /**< Disconnect/Prefetch to prefetchable memory 1501 regions Enable. Prefetchable memory regions 1502 are always disconnected on a region boundary. 1503 Non-prefetchable regions for PCI are always 1504 disconnected on the first transfer. 1505 Note: OCTEON as target will never target-disconnect, 1506 therefore this bit should never be set. */ 1507 uint32_t reserved_2_2 : 1; 1508 uint32_t tswc : 1; /**< Target Split Write Control 1509 0 = Blocks all requests except PMW 1510 1 = Blocks all requests including PMW until 1511 split completion occurs. */ 1512 uint32_t mltd : 1; /**< Master Latency Timer Disable 1513 Note: For OCTEON, it is recommended that this bit 1514 be set(to disable the Master Latency timer). */ 1515#else 1516 uint32_t mltd : 1; 1517 uint32_t tswc : 1; 1518 uint32_t reserved_2_2 : 1; 1519 uint32_t dppmr : 1; 1520 uint32_t pbe : 12; 1521 uint32_t tilt : 4; 1522 uint32_t tslte : 3; 1523 uint32_t tmae : 1; 1524 uint32_t twtae : 1; 1525 uint32_t twsen : 1; 1526 uint32_t twsei : 1; 1527 uint32_t trtae : 1; 1528 uint32_t trdrs : 1; 1529 uint32_t rdsati : 1; 1530 uint32_t trdard : 1; 1531 uint32_t trdnpr : 1; 1532#endif 1533 } s; 1534 struct cvmx_pci_cfg16_s cn30xx; 1535 struct cvmx_pci_cfg16_s cn31xx; 1536 struct cvmx_pci_cfg16_s cn38xx; 1537 struct cvmx_pci_cfg16_s cn38xxp2; 1538 struct cvmx_pci_cfg16_s cn50xx; 1539 struct cvmx_pci_cfg16_s cn58xx; 1540 struct cvmx_pci_cfg16_s cn58xxp1; 1541}; 1542typedef union cvmx_pci_cfg16 cvmx_pci_cfg16_t; 1543 1544/** 1545 * cvmx_pci_cfg17 1546 * 1547 * PCI_CFG17 = Eighteenth 32-bits of PCI config space (Target Split Completion Message 1548 * Enable Register) 1549 */ 1550union cvmx_pci_cfg17 1551{ 1552 uint32_t u32; 1553 struct cvmx_pci_cfg17_s 1554 { 1555#if __BYTE_ORDER == __BIG_ENDIAN 1556 uint32_t tscme : 32; /**< Target Split Completion Message Enable 1557 [31:30]: 00 1558 [29]: Split Completion Error Indication 1559 [28]: 0 1560 [27:20]: Split Completion Message Index 1561 [19:0]: 0x00000 1562 For OCTEON, this register is intended for debug use 1563 only. (as such, it is recommended NOT to be written 1564 with anything other than ZEROES). */ 1565#else 1566 uint32_t tscme : 32; 1567#endif 1568 } s; 1569 struct cvmx_pci_cfg17_s cn30xx; 1570 struct cvmx_pci_cfg17_s cn31xx; 1571 struct cvmx_pci_cfg17_s cn38xx; 1572 struct cvmx_pci_cfg17_s cn38xxp2; 1573 struct cvmx_pci_cfg17_s cn50xx; 1574 struct cvmx_pci_cfg17_s cn58xx; 1575 struct cvmx_pci_cfg17_s cn58xxp1; 1576}; 1577typedef union cvmx_pci_cfg17 cvmx_pci_cfg17_t; 1578 1579/** 1580 * cvmx_pci_cfg18 1581 * 1582 * PCI_CFG18 = Nineteenth 32-bits of PCI config space (Target Delayed/Split Request 1583 * Pending Sequences) 1584 */ 1585union cvmx_pci_cfg18 1586{ 1587 uint32_t u32; 1588 struct cvmx_pci_cfg18_s 1589 { 1590#if __BYTE_ORDER == __BIG_ENDIAN 1591 uint32_t tdsrps : 32; /**< Target Delayed/Split Request Pending Sequences 1592 The application uses this address to remove a 1593 pending split sequence from the target queue by 1594 clearing the appropriate bit. Example: Clearing [14] 1595 clears the pending sequence \#14. An application 1596 or configuration write to this address can clear this 1597 register. 1598 For OCTEON, this register is intended for debug use 1599 only and MUST NEVER be written with anything other 1600 than ZEROES. */ 1601#else 1602 uint32_t tdsrps : 32; 1603#endif 1604 } s; 1605 struct cvmx_pci_cfg18_s cn30xx; 1606 struct cvmx_pci_cfg18_s cn31xx; 1607 struct cvmx_pci_cfg18_s cn38xx; 1608 struct cvmx_pci_cfg18_s cn38xxp2; 1609 struct cvmx_pci_cfg18_s cn50xx; 1610 struct cvmx_pci_cfg18_s cn58xx; 1611 struct cvmx_pci_cfg18_s cn58xxp1; 1612}; 1613typedef union cvmx_pci_cfg18 cvmx_pci_cfg18_t; 1614 1615/** 1616 * cvmx_pci_cfg19 1617 * 1618 * PCI_CFG19 = Twentieth 32-bits of PCI config space (Master/Target Implementation Register) 1619 * 1620 */ 1621union cvmx_pci_cfg19 1622{ 1623 uint32_t u32; 1624 struct cvmx_pci_cfg19_s 1625 { 1626#if __BYTE_ORDER == __BIG_ENDIAN 1627 uint32_t mrbcm : 1; /**< Master Request (Memory Read) Byte Count/Byte 1628 Enable select. 1629 0 = Byte Enables valid. In PCI mode, a burst 1630 transaction cannot be performed using 1631 Memory Read command=4'h6. 1632 1 = DWORD Byte Count valid (default). In PCI 1633 Mode, the memory read byte enables are 1634 automatically generated by the core. 1635 NOTE: For OCTEON, this bit must always be one 1636 for proper operation. */ 1637 uint32_t mrbci : 1; /**< Master Request (I/O and CR cycles) byte count/byte 1638 enable select. 1639 0 = Byte Enables valid (default) 1640 1 = DWORD byte count valid 1641 NOTE: For OCTEON, this bit must always be zero 1642 for proper operation (in support of 1643 Type0/1 Cfg Space accesses which require byte 1644 enable generation directly from a read mask). */ 1645 uint32_t mdwe : 1; /**< Master (Retry) Deferred Write Enable (allow 1646 read requests to pass). 1647 NOTE: Applicable to PCI Mode I/O and memory 1648 transactions only. 1649 0 = New read requests are NOT accepted until 1650 the current write cycle completes. [Reads 1651 cannot pass writes] 1652 1 = New read requests are accepted, even when 1653 there is a write cycle pending [Reads can 1654 pass writes]. 1655 NOTE: For OCTEON, this bit must always be zero 1656 for proper operation. */ 1657 uint32_t mdre : 1; /**< Master (Retry) Deferred Read Enable (Allows 1658 read/write requests to pass). 1659 NOTE: Applicable to PCI mode I/O and memory 1660 transactions only. 1661 0 = New read/write requests are NOT accepted 1662 until the current read cycle completes. 1663 [Read/write requests CANNOT pass reads] 1664 1 = New read/write requests are accepted, even 1665 when there is a read cycle pending. 1666 [Read/write requests CAN pass reads] 1667 NOTE: For OCTEON, this bit must always be zero 1668 for proper operation. */ 1669 uint32_t mdrimc : 1; /**< Master I/O Deferred/Split Request Outstanding 1670 Maximum Count 1671 0 = MDRRMC[26:24] 1672 1 = 1 */ 1673 uint32_t mdrrmc : 3; /**< Master Deferred Read Request Outstanding Max 1674 Count (PCI only). 1675 CR4C[26:24] Max SAC cycles MAX DAC cycles 1676 000 8 4 1677 001 1 0 1678 010 2 1 1679 011 3 1 1680 100 4 2 1681 101 5 2 1682 110 6 3 1683 111 7 3 1684 For example, if these bits are programmed to 1685 100, the core can support 2 DAC cycles, 4 SAC 1686 cycles or a combination of 1 DAC and 2 SAC cycles. 1687 NOTE: For the PCI-X maximum outstanding split 1688 transactions, refer to CRE0[22:20] */ 1689 uint32_t tmes : 8; /**< Target/Master Error Sequence \# */ 1690 uint32_t teci : 1; /**< Target Error Command Indication 1691 0 = Delayed/Split 1692 1 = Others */ 1693 uint32_t tmei : 1; /**< Target/Master Error Indication 1694 0 = Target 1695 1 = Master */ 1696 uint32_t tmse : 1; /**< Target/Master System Error. This bit is set 1697 whenever ATM_SERR_O is active. */ 1698 uint32_t tmdpes : 1; /**< Target/Master Data PERR# error status. This 1699 bit is set whenever ATM_DATA_PERR_O is active. */ 1700 uint32_t tmapes : 1; /**< Target/Master Address PERR# error status. This 1701 bit is set whenever ATM_ADDR_PERR_O is active. */ 1702 uint32_t reserved_9_10 : 2; 1703 uint32_t tibcd : 1; /**< Target Illegal I/O DWORD byte combinations detected. */ 1704 uint32_t tibde : 1; /**< Target Illegal I/O DWORD byte detection enable */ 1705 uint32_t reserved_6_6 : 1; 1706 uint32_t tidomc : 1; /**< Target I/O Delayed/Split request outstanding 1707 maximum count. 1708 0 = TDOMC[4:0] 1709 1 = 1 */ 1710 uint32_t tdomc : 5; /**< Target Delayed/Split request outstanding maximum 1711 count. [1..31] and 0=32. 1712 NOTE: If the user programs these bits beyond the 1713 Designed Maximum outstanding count, then the 1714 designed maximum table depth will be used instead. 1715 No additional Deferred/Split transactions will be 1716 accepted if this outstanding maximum count 1717 is reached. Furthermore, no additional 1718 deferred/split transactions will be accepted if 1719 the I/O delay/ I/O Split Request outstanding 1720 maximum is reached. 1721 NOTE: For OCTEON in PCI Mode, this field MUST BE 1722 programmed to 1. (OCTEON can only handle 1 delayed 1723 read at a time). 1724 For OCTEON in PCIX Mode, this field can range from 1725 1-4. (The designed maximum table depth is 4 1726 for PCIX mode splits). */ 1727#else 1728 uint32_t tdomc : 5; 1729 uint32_t tidomc : 1; 1730 uint32_t reserved_6_6 : 1; 1731 uint32_t tibde : 1; 1732 uint32_t tibcd : 1; 1733 uint32_t reserved_9_10 : 2; 1734 uint32_t tmapes : 1; 1735 uint32_t tmdpes : 1; 1736 uint32_t tmse : 1; 1737 uint32_t tmei : 1; 1738 uint32_t teci : 1; 1739 uint32_t tmes : 8; 1740 uint32_t mdrrmc : 3; 1741 uint32_t mdrimc : 1; 1742 uint32_t mdre : 1; 1743 uint32_t mdwe : 1; 1744 uint32_t mrbci : 1; 1745 uint32_t mrbcm : 1; 1746#endif 1747 } s; 1748 struct cvmx_pci_cfg19_s cn30xx; 1749 struct cvmx_pci_cfg19_s cn31xx; 1750 struct cvmx_pci_cfg19_s cn38xx; 1751 struct cvmx_pci_cfg19_s cn38xxp2; 1752 struct cvmx_pci_cfg19_s cn50xx; 1753 struct cvmx_pci_cfg19_s cn58xx; 1754 struct cvmx_pci_cfg19_s cn58xxp1; 1755}; 1756typedef union cvmx_pci_cfg19 cvmx_pci_cfg19_t; 1757 1758/** 1759 * cvmx_pci_cfg20 1760 * 1761 * PCI_CFG20 = Twenty-first 32-bits of PCI config space (Master Deferred/Split Sequence Pending) 1762 * 1763 */ 1764union cvmx_pci_cfg20 1765{ 1766 uint32_t u32; 1767 struct cvmx_pci_cfg20_s 1768 { 1769#if __BYTE_ORDER == __BIG_ENDIAN 1770 uint32_t mdsp : 32; /**< Master Deferred/Split sequence Pending 1771 For OCTEON, this register is intended for debug use 1772 only and MUST NEVER be written with anything other 1773 than ZEROES. */ 1774#else 1775 uint32_t mdsp : 32; 1776#endif 1777 } s; 1778 struct cvmx_pci_cfg20_s cn30xx; 1779 struct cvmx_pci_cfg20_s cn31xx; 1780 struct cvmx_pci_cfg20_s cn38xx; 1781 struct cvmx_pci_cfg20_s cn38xxp2; 1782 struct cvmx_pci_cfg20_s cn50xx; 1783 struct cvmx_pci_cfg20_s cn58xx; 1784 struct cvmx_pci_cfg20_s cn58xxp1; 1785}; 1786typedef union cvmx_pci_cfg20 cvmx_pci_cfg20_t; 1787 1788/** 1789 * cvmx_pci_cfg21 1790 * 1791 * PCI_CFG21 = Twenty-second 32-bits of PCI config space (Master Split Completion Message Register) 1792 * 1793 */ 1794union cvmx_pci_cfg21 1795{ 1796 uint32_t u32; 1797 struct cvmx_pci_cfg21_s 1798 { 1799#if __BYTE_ORDER == __BIG_ENDIAN 1800 uint32_t scmre : 32; /**< Master Split Completion message received with 1801 error message. 1802 For OCTEON, this register is intended for debug use 1803 only and MUST NEVER be written with anything other 1804 than ZEROES. */ 1805#else 1806 uint32_t scmre : 32; 1807#endif 1808 } s; 1809 struct cvmx_pci_cfg21_s cn30xx; 1810 struct cvmx_pci_cfg21_s cn31xx; 1811 struct cvmx_pci_cfg21_s cn38xx; 1812 struct cvmx_pci_cfg21_s cn38xxp2; 1813 struct cvmx_pci_cfg21_s cn50xx; 1814 struct cvmx_pci_cfg21_s cn58xx; 1815 struct cvmx_pci_cfg21_s cn58xxp1; 1816}; 1817typedef union cvmx_pci_cfg21 cvmx_pci_cfg21_t; 1818 1819/** 1820 * cvmx_pci_cfg22 1821 * 1822 * PCI_CFG22 = Twenty-third 32-bits of PCI config space (Master Arbiter Control Register) 1823 * 1824 */ 1825union cvmx_pci_cfg22 1826{ 1827 uint32_t u32; 1828 struct cvmx_pci_cfg22_s 1829 { 1830#if __BYTE_ORDER == __BIG_ENDIAN 1831 uint32_t mac : 7; /**< Master Arbiter Control 1832 [31:26]: Used only in Fixed Priority mode 1833 (when [25]=1) 1834 [31:30]: MSI Request 1835 00 = Highest Priority 1836 01 = Medium Priority 1837 10 = Lowest Priority 1838 11 = RESERVED 1839 [29:28]: Target Split Completion 1840 00 = Highest Priority 1841 01 = Medium Priority 1842 10 = Lowest Priority 1843 11 = RESERVED 1844 [27:26]: New Request; Deferred Read,Deferred Write 1845 00 = Highest Priority 1846 01 = Medium Priority 1847 10 = Lowest Priority 1848 11 = RESERVED 1849 [25]: Fixed/Round Robin Priority Selector 1850 0 = Round Robin 1851 1 = Fixed 1852 NOTE: When [25]=1(fixed priority), the three levels 1853 [31:26] MUST BE programmed to have mutually exclusive 1854 priority levels for proper operation. (Failure to do 1855 so may result in PCI hangs). */ 1856 uint32_t reserved_19_24 : 6; 1857 uint32_t flush : 1; /**< AM_DO_FLUSH_I control 1858 NOTE: This bit MUST BE ONE for proper OCTEON operation */ 1859 uint32_t mra : 1; /**< Master Retry Aborted */ 1860 uint32_t mtta : 1; /**< Master TRDY timeout aborted */ 1861 uint32_t mrv : 8; /**< Master Retry Value [1..255] and 0=infinite */ 1862 uint32_t mttv : 8; /**< Master TRDY timeout value [1..255] and 0=disabled 1863 NOTE: For OCTEON, this bit must always be zero 1864 for proper operation. (OCTEON does not support 1865 master TRDY timeout - target is expected to be 1866 well behaved). */ 1867#else 1868 uint32_t mttv : 8; 1869 uint32_t mrv : 8; 1870 uint32_t mtta : 1; 1871 uint32_t mra : 1; 1872 uint32_t flush : 1; 1873 uint32_t reserved_19_24 : 6; 1874 uint32_t mac : 7; 1875#endif 1876 } s; 1877 struct cvmx_pci_cfg22_s cn30xx; 1878 struct cvmx_pci_cfg22_s cn31xx; 1879 struct cvmx_pci_cfg22_s cn38xx; 1880 struct cvmx_pci_cfg22_s cn38xxp2; 1881 struct cvmx_pci_cfg22_s cn50xx; 1882 struct cvmx_pci_cfg22_s cn58xx; 1883 struct cvmx_pci_cfg22_s cn58xxp1; 1884}; 1885typedef union cvmx_pci_cfg22 cvmx_pci_cfg22_t; 1886 1887/** 1888 * cvmx_pci_cfg56 1889 * 1890 * PCI_CFG56 = Fifty-seventh 32-bits of PCI config space (PCIX Capabilities Register) 1891 * 1892 */ 1893union cvmx_pci_cfg56 1894{ 1895 uint32_t u32; 1896 struct cvmx_pci_cfg56_s 1897 { 1898#if __BYTE_ORDER == __BIG_ENDIAN 1899 uint32_t reserved_23_31 : 9; 1900 uint32_t most : 3; /**< Maximum outstanding Split transactions 1901 Encoded Value \#Max outstanding splits 1902 000 1 1903 001 2 1904 010 3 1905 011 4 1906 100 8 1907 101 8(clamped) 1908 110 8(clamped) 1909 111 8(clamped) 1910 NOTE: OCTEON only supports upto a MAXIMUM of 8 1911 outstanding master split transactions. */ 1912 uint32_t mmbc : 2; /**< Maximum Memory Byte Count 1913 [0=512B,1=1024B,2=2048B,3=4096B] 1914 NOTE: OCTEON does not support this field and has 1915 no effect on limiting the maximum memory byte count. */ 1916 uint32_t roe : 1; /**< Relaxed Ordering Enable */ 1917 uint32_t dpere : 1; /**< Data Parity Error Recovery Enable */ 1918 uint32_t ncp : 8; /**< Next Capability Pointer */ 1919 uint32_t pxcid : 8; /**< PCI-X Capability ID */ 1920#else 1921 uint32_t pxcid : 8; 1922 uint32_t ncp : 8; 1923 uint32_t dpere : 1; 1924 uint32_t roe : 1; 1925 uint32_t mmbc : 2; 1926 uint32_t most : 3; 1927 uint32_t reserved_23_31 : 9; 1928#endif 1929 } s; 1930 struct cvmx_pci_cfg56_s cn30xx; 1931 struct cvmx_pci_cfg56_s cn31xx; 1932 struct cvmx_pci_cfg56_s cn38xx; 1933 struct cvmx_pci_cfg56_s cn38xxp2; 1934 struct cvmx_pci_cfg56_s cn50xx; 1935 struct cvmx_pci_cfg56_s cn58xx; 1936 struct cvmx_pci_cfg56_s cn58xxp1; 1937}; 1938typedef union cvmx_pci_cfg56 cvmx_pci_cfg56_t; 1939 1940/** 1941 * cvmx_pci_cfg57 1942 * 1943 * PCI_CFG57 = Fifty-eigth 32-bits of PCI config space (PCIX Status Register) 1944 * 1945 */ 1946union cvmx_pci_cfg57 1947{ 1948 uint32_t u32; 1949 struct cvmx_pci_cfg57_s 1950 { 1951#if __BYTE_ORDER == __BIG_ENDIAN 1952 uint32_t reserved_30_31 : 2; 1953 uint32_t scemr : 1; /**< Split Completion Error Message Received */ 1954 uint32_t mcrsd : 3; /**< Maximum Cumulative Read Size designed */ 1955 uint32_t mostd : 3; /**< Maximum Outstanding Split transaction designed */ 1956 uint32_t mmrbcd : 2; /**< Maximum Memory Read byte count designed */ 1957 uint32_t dc : 1; /**< Device Complexity 1958 0 = Simple Device 1959 1 = Bridge Device */ 1960 uint32_t usc : 1; /**< Unexpected Split Completion */ 1961 uint32_t scd : 1; /**< Split Completion Discarded */ 1962 uint32_t m133 : 1; /**< 133MHz Capable */ 1963 uint32_t w64 : 1; /**< Indicates a 32b(=0) or 64b(=1) device */ 1964 uint32_t bn : 8; /**< Bus Number. Updated on all configuration write 1965 (0x11=PCI) cycles. Its value is dependent upon the PCI/X 1966 (0xFF=PCIX) mode. */ 1967 uint32_t dn : 5; /**< Device Number. Updated on all configuration 1968 write cycles. */ 1969 uint32_t fn : 3; /**< Function Number */ 1970#else 1971 uint32_t fn : 3; 1972 uint32_t dn : 5; 1973 uint32_t bn : 8; 1974 uint32_t w64 : 1; 1975 uint32_t m133 : 1; 1976 uint32_t scd : 1; 1977 uint32_t usc : 1; 1978 uint32_t dc : 1; 1979 uint32_t mmrbcd : 2; 1980 uint32_t mostd : 3; 1981 uint32_t mcrsd : 3; 1982 uint32_t scemr : 1; 1983 uint32_t reserved_30_31 : 2; 1984#endif 1985 } s; 1986 struct cvmx_pci_cfg57_s cn30xx; 1987 struct cvmx_pci_cfg57_s cn31xx; 1988 struct cvmx_pci_cfg57_s cn38xx; 1989 struct cvmx_pci_cfg57_s cn38xxp2; 1990 struct cvmx_pci_cfg57_s cn50xx; 1991 struct cvmx_pci_cfg57_s cn58xx; 1992 struct cvmx_pci_cfg57_s cn58xxp1; 1993}; 1994typedef union cvmx_pci_cfg57 cvmx_pci_cfg57_t; 1995 1996/** 1997 * cvmx_pci_cfg58 1998 * 1999 * PCI_CFG58 = Fifty-ninth 32-bits of PCI config space (Power Management Capabilities Register) 2000 * 2001 */ 2002union cvmx_pci_cfg58 2003{ 2004 uint32_t u32; 2005 struct cvmx_pci_cfg58_s 2006 { 2007#if __BYTE_ORDER == __BIG_ENDIAN 2008 uint32_t pmes : 5; /**< PME Support (D0 to D3cold) */ 2009 uint32_t d2s : 1; /**< D2_Support */ 2010 uint32_t d1s : 1; /**< D1_Support */ 2011 uint32_t auxc : 3; /**< AUX_Current (0..375mA) */ 2012 uint32_t dsi : 1; /**< Device Specific Initialization */ 2013 uint32_t reserved_20_20 : 1; 2014 uint32_t pmec : 1; /**< PME Clock */ 2015 uint32_t pcimiv : 3; /**< Indicates the version of the PCI 2016 Management 2017 Interface Specification with which the core 2018 complies. 2019 010b = Complies with PCI Management Interface 2020 Specification Revision 1.1 */ 2021 uint32_t ncp : 8; /**< Next Capability Pointer */ 2022 uint32_t pmcid : 8; /**< Power Management Capability ID */ 2023#else 2024 uint32_t pmcid : 8; 2025 uint32_t ncp : 8; 2026 uint32_t pcimiv : 3; 2027 uint32_t pmec : 1; 2028 uint32_t reserved_20_20 : 1; 2029 uint32_t dsi : 1; 2030 uint32_t auxc : 3; 2031 uint32_t d1s : 1; 2032 uint32_t d2s : 1; 2033 uint32_t pmes : 5; 2034#endif 2035 } s; 2036 struct cvmx_pci_cfg58_s cn30xx; 2037 struct cvmx_pci_cfg58_s cn31xx; 2038 struct cvmx_pci_cfg58_s cn38xx; 2039 struct cvmx_pci_cfg58_s cn38xxp2; 2040 struct cvmx_pci_cfg58_s cn50xx; 2041 struct cvmx_pci_cfg58_s cn58xx; 2042 struct cvmx_pci_cfg58_s cn58xxp1; 2043}; 2044typedef union cvmx_pci_cfg58 cvmx_pci_cfg58_t; 2045 2046/** 2047 * cvmx_pci_cfg59 2048 * 2049 * PCI_CFG59 = Sixtieth 32-bits of PCI config space (Power Management Data/PMCSR Register(s)) 2050 * 2051 */ 2052union cvmx_pci_cfg59 2053{ 2054 uint32_t u32; 2055 struct cvmx_pci_cfg59_s 2056 { 2057#if __BYTE_ORDER == __BIG_ENDIAN 2058 uint32_t pmdia : 8; /**< Power Management data input from application 2059 (PME_DATA) */ 2060 uint32_t bpccen : 1; /**< BPCC_En (bus power/clock control) enable */ 2061 uint32_t bd3h : 1; /**< B2_B3\#, B2/B3 Support for D3hot */ 2062 uint32_t reserved_16_21 : 6; 2063 uint32_t pmess : 1; /**< PME_Status sticky bit */ 2064 uint32_t pmedsia : 2; /**< PME_Data_Scale input from application 2065 Device (PME_DATA_SCALE[1:0]) 2066 Specific */ 2067 uint32_t pmds : 4; /**< Power Management Data_select */ 2068 uint32_t pmeens : 1; /**< PME_En sticky bit */ 2069 uint32_t reserved_2_7 : 6; 2070 uint32_t ps : 2; /**< Power State (D0 to D3) 2071 The N2 DOES NOT support D1/D2 Power Management 2072 states, therefore writing to this register has 2073 no effect (please refer to the PCI Power 2074 Management 2075 Specification v1.1 for further details about 2076 it?s R/W nature. This is not a conventional 2077 R/W style register. */ 2078#else 2079 uint32_t ps : 2; 2080 uint32_t reserved_2_7 : 6; 2081 uint32_t pmeens : 1; 2082 uint32_t pmds : 4; 2083 uint32_t pmedsia : 2; 2084 uint32_t pmess : 1; 2085 uint32_t reserved_16_21 : 6; 2086 uint32_t bd3h : 1; 2087 uint32_t bpccen : 1; 2088 uint32_t pmdia : 8; 2089#endif 2090 } s; 2091 struct cvmx_pci_cfg59_s cn30xx; 2092 struct cvmx_pci_cfg59_s cn31xx; 2093 struct cvmx_pci_cfg59_s cn38xx; 2094 struct cvmx_pci_cfg59_s cn38xxp2; 2095 struct cvmx_pci_cfg59_s cn50xx; 2096 struct cvmx_pci_cfg59_s cn58xx; 2097 struct cvmx_pci_cfg59_s cn58xxp1; 2098}; 2099typedef union cvmx_pci_cfg59 cvmx_pci_cfg59_t; 2100 2101/** 2102 * cvmx_pci_cfg60 2103 * 2104 * PCI_CFG60 = Sixty-first 32-bits of PCI config space (MSI Capabilities Register) 2105 * 2106 */ 2107union cvmx_pci_cfg60 2108{ 2109 uint32_t u32; 2110 struct cvmx_pci_cfg60_s 2111 { 2112#if __BYTE_ORDER == __BIG_ENDIAN 2113 uint32_t reserved_24_31 : 8; 2114 uint32_t m64 : 1; /**< 32/64 b message */ 2115 uint32_t mme : 3; /**< Multiple Message Enable(1,2,4,8,16,32) */ 2116 uint32_t mmc : 3; /**< Multiple Message Capable(0=1,1=2,2=4,3=8,4=16,5=32) */ 2117 uint32_t msien : 1; /**< MSI Enable */ 2118 uint32_t ncp : 8; /**< Next Capability Pointer */ 2119 uint32_t msicid : 8; /**< MSI Capability ID */ 2120#else 2121 uint32_t msicid : 8; 2122 uint32_t ncp : 8; 2123 uint32_t msien : 1; 2124 uint32_t mmc : 3; 2125 uint32_t mme : 3; 2126 uint32_t m64 : 1; 2127 uint32_t reserved_24_31 : 8; 2128#endif 2129 } s; 2130 struct cvmx_pci_cfg60_s cn30xx; 2131 struct cvmx_pci_cfg60_s cn31xx; 2132 struct cvmx_pci_cfg60_s cn38xx; 2133 struct cvmx_pci_cfg60_s cn38xxp2; 2134 struct cvmx_pci_cfg60_s cn50xx; 2135 struct cvmx_pci_cfg60_s cn58xx; 2136 struct cvmx_pci_cfg60_s cn58xxp1; 2137}; 2138typedef union cvmx_pci_cfg60 cvmx_pci_cfg60_t; 2139 2140/** 2141 * cvmx_pci_cfg61 2142 * 2143 * PCI_CFG61 = Sixty-second 32-bits of PCI config space (MSI Lower Address Register) 2144 * 2145 */ 2146union cvmx_pci_cfg61 2147{ 2148 uint32_t u32; 2149 struct cvmx_pci_cfg61_s 2150 { 2151#if __BYTE_ORDER == __BIG_ENDIAN 2152 uint32_t msi31t2 : 30; /**< App Specific MSI Address [31:2] */ 2153 uint32_t reserved_0_1 : 2; 2154#else 2155 uint32_t reserved_0_1 : 2; 2156 uint32_t msi31t2 : 30; 2157#endif 2158 } s; 2159 struct cvmx_pci_cfg61_s cn30xx; 2160 struct cvmx_pci_cfg61_s cn31xx; 2161 struct cvmx_pci_cfg61_s cn38xx; 2162 struct cvmx_pci_cfg61_s cn38xxp2; 2163 struct cvmx_pci_cfg61_s cn50xx; 2164 struct cvmx_pci_cfg61_s cn58xx; 2165 struct cvmx_pci_cfg61_s cn58xxp1; 2166}; 2167typedef union cvmx_pci_cfg61 cvmx_pci_cfg61_t; 2168 2169/** 2170 * cvmx_pci_cfg62 2171 * 2172 * PCI_CFG62 = Sixty-third 32-bits of PCI config space (MSI Upper Address Register) 2173 * 2174 */ 2175union cvmx_pci_cfg62 2176{ 2177 uint32_t u32; 2178 struct cvmx_pci_cfg62_s 2179 { 2180#if __BYTE_ORDER == __BIG_ENDIAN 2181 uint32_t msi : 32; /**< MSI Address [63:32] */ 2182#else 2183 uint32_t msi : 32; 2184#endif 2185 } s; 2186 struct cvmx_pci_cfg62_s cn30xx; 2187 struct cvmx_pci_cfg62_s cn31xx; 2188 struct cvmx_pci_cfg62_s cn38xx; 2189 struct cvmx_pci_cfg62_s cn38xxp2; 2190 struct cvmx_pci_cfg62_s cn50xx; 2191 struct cvmx_pci_cfg62_s cn58xx; 2192 struct cvmx_pci_cfg62_s cn58xxp1; 2193}; 2194typedef union cvmx_pci_cfg62 cvmx_pci_cfg62_t; 2195 2196/** 2197 * cvmx_pci_cfg63 2198 * 2199 * PCI_CFG63 = Sixty-fourth 32-bits of PCI config space (MSI Message Data Register) 2200 * 2201 */ 2202union cvmx_pci_cfg63 2203{ 2204 uint32_t u32; 2205 struct cvmx_pci_cfg63_s 2206 { 2207#if __BYTE_ORDER == __BIG_ENDIAN 2208 uint32_t reserved_16_31 : 16; 2209 uint32_t msimd : 16; /**< MSI Message Data */ 2210#else 2211 uint32_t msimd : 16; 2212 uint32_t reserved_16_31 : 16; 2213#endif 2214 } s; 2215 struct cvmx_pci_cfg63_s cn30xx; 2216 struct cvmx_pci_cfg63_s cn31xx; 2217 struct cvmx_pci_cfg63_s cn38xx; 2218 struct cvmx_pci_cfg63_s cn38xxp2; 2219 struct cvmx_pci_cfg63_s cn50xx; 2220 struct cvmx_pci_cfg63_s cn58xx; 2221 struct cvmx_pci_cfg63_s cn58xxp1; 2222}; 2223typedef union cvmx_pci_cfg63 cvmx_pci_cfg63_t; 2224 2225/** 2226 * cvmx_pci_cnt_reg 2227 * 2228 * PCI_CNT_REG = PCI Clock Count Register 2229 * 2230 * This register is provided to software as a means to determine PCI Bus Type/Speed. 2231 */ 2232union cvmx_pci_cnt_reg 2233{ 2234 uint64_t u64; 2235 struct cvmx_pci_cnt_reg_s 2236 { 2237#if __BYTE_ORDER == __BIG_ENDIAN 2238 uint64_t reserved_38_63 : 26; 2239 uint64_t hm_pcix : 1; /**< PCI Host Mode Sampled Bus Type (0:PCI/1:PCIX) 2240 This field represents what OCTEON(in Host mode) 2241 sampled as the 'intended' PCI Bus Type based on 2242 the PCI_PCIXCAP pin. (see HM_SPEED Bus Type/Speed 2243 encoding table). */ 2244 uint64_t hm_speed : 2; /**< PCI Host Mode Sampled Bus Speed 2245 This field represents what OCTEON(in Host mode) 2246 sampled as the 'intended' PCI Bus Speed based on 2247 the PCI100, PCI_M66EN and PCI_PCIXCAP pins. 2248 NOTE: This DOES NOT reflect what the actual PCI 2249 Bus Type/Speed values are. They only indicate what 2250 OCTEON sampled as the 'intended' values. 2251 PCI Host Mode Sampled Bus Type/Speed Table: 2252 M66EN | PCIXCAP | PCI100 | HM_PCIX | HM_SPEED[1:0] 2253 ---------+---------+---------+----------+------------- 2254 0 | 0 | 0 | 0=PCI | 00=33 MHz 2255 0 | 0 | 1 | 0=PCI | 00=33 MHz 2256 0 | Z | 0 | 0=PCI | 01=66 MHz 2257 0 | Z | 1 | 0=PCI | 01=66 MHz 2258 1 | 0 | 0 | 0=PCI | 01=66 MHz 2259 1 | 0 | 1 | 0=PCI | 01=66 MHz 2260 1 | Z | 0 | 0=PCI | 01=66 MHz 2261 1 | Z | 1 | 0=PCI | 01=66 MHz 2262 0 | 1 | 1 | 1=PCIX | 10=100 MHz 2263 1 | 1 | 1 | 1=PCIX | 10=100 MHz 2264 0 | 1 | 0 | 1=PCIX | 11=133 MHz 2265 1 | 1 | 0 | 1=PCIX | 11=133 MHz 2266 NOTE: PCIXCAP has tri-level value (0,1,Z). See PCI specification 2267 for more details on board level hookup to achieve these 2268 values. 2269 NOTE: Software can use the NPI_PCI_INT_ARB_CFG[PCI_OVR] 2270 to override the 'sampled' PCI Bus Type/Speed. 2271 NOTE: Software can also use the PCI_CNT_REG[PCICNT] to determine 2272 the exact PCI(X) Bus speed. 2273 Example: PCI_REF_CLKIN=133MHz 2274 PCI_HOST_MODE=1 2275 PCI_M66EN=0 2276 PCI_PCIXCAP=1 2277 PCI_PCI100=1 2278 For this example, OCTEON will generate 2279 PCI_CLK_OUT=100MHz and drive the proper PCI 2280 Initialization sequence (DEVSEL#=Deasserted, 2281 STOP#=Asserted, TRDY#=Asserted) during PCI_RST_N 2282 deassertion. 2283 NOTE: The HM_SPEED field is only valid after 2284 PLL_REF_CLK is active and PLL_DCOK is asserted. 2285 (see HRM description for power-on/reset sequence). 2286 NOTE: PCI_REF_CLKIN input must be 133MHz (and is used 2287 to generate the PCI_CLK_OUT pin in Host Mode). */ 2288 uint64_t ap_pcix : 1; /**< PCI(X) Bus Type (0:PCI/1:PCIX) 2289 At PCI_RST_N de-assertion, the PCI Initialization 2290 pattern(PCI_DEVSEL_N, PCI_STOP_N, PCI_TRDY_N) is 2291 captured to provide information to software regarding 2292 the PCI Bus Type(PCI/PCIX) and PCI Bus Speed Range. */ 2293 uint64_t ap_speed : 2; /**< PCI(X) Bus Speed (0:33/1:66/2:100/3:133) 2294 At PCI_RST_N de-assertion, the PCI Initialization 2295 pattern(PCI_DEVSEL_N, PCI_STOP_N, PCI_TRDY_N) is 2296 captured to provide information to software regarding 2297 the PCI Bus Type(PCI/PCIX) and PCI Bus Speed Range. 2298 PCI-X Initialization Pattern(see PCIX Spec): 2299 PCI_DEVSEL_N PCI_STOP_N PCI_TRDY_N Mode MaxClk(ns) MinClk(ns) MinClk(MHz) MaxClk(MHz) 2300 -------------+----------+----------+-------+---------+----------+----------+------------------ 2301 Deasserted Deasserted Deasserted PCI 33 -- 30 0 33 2302 PCI 66 30 15 33 66 2303 Deasserted Deasserted Asserted PCI-X 20 15 50 66 2304 Deasserted Asserted Deasserted PCI-X 15 10 66 100 2305 Deasserted Asserted Asserted PCI-X 10 7.5 100 133 2306 Asserted Deasserted Deasserted PCI-X Reserved Reserved Reserved Reserved 2307 Asserted Deasserted Asserted PCI-X Reserved Reserved Reserved Reserved 2308 Asserted Asserted Deasserted PCI-X Reserved Reserved Reserved Reserved 2309 Asserted Asserted Asserted PCI-X Reserved Reserved Reserved Reserved 2310 NOTE: The PCI Bus speed 'assumed' from the initialization 2311 pattern is really intended for an operational range. 2312 For example: If PINIT=100, this indicates PCI-X in the 2313 100-133MHz range. The PCI_CNT field can be used to further 2314 determine a more exacting PCI Bus frequency value if 2315 required. */ 2316 uint64_t pcicnt : 32; /**< Free Running PCI Clock counter. 2317 At PCI Reset, the PCICNT=0, and is auto-incremented 2318 on every PCI clock and will auto-wrap back to zero 2319 when saturated. 2320 NOTE: Writes override the auto-increment to allow 2321 software to preload any initial value. 2322 The PCICNT field is provided to software as a means 2323 to determine the PCI Bus Speed. 2324 Assuming software has knowledge of the core frequency 2325 (eclk), this register can be written with a value X, 2326 wait 'n' core clocks(eclk) and then read later(Y) to 2327 determine \#PCI clocks(Y-X) have elapsed within 'n' core 2328 clocks to determine the PCI input Clock frequency. */ 2329#else 2330 uint64_t pcicnt : 32; 2331 uint64_t ap_speed : 2; 2332 uint64_t ap_pcix : 1; 2333 uint64_t hm_speed : 2; 2334 uint64_t hm_pcix : 1; 2335 uint64_t reserved_38_63 : 26; 2336#endif 2337 } s; 2338 struct cvmx_pci_cnt_reg_s cn50xx; 2339 struct cvmx_pci_cnt_reg_s cn58xx; 2340 struct cvmx_pci_cnt_reg_s cn58xxp1; 2341}; 2342typedef union cvmx_pci_cnt_reg cvmx_pci_cnt_reg_t; 2343 2344/** 2345 * cvmx_pci_ctl_status_2 2346 * 2347 * PCI_CTL_STATUS_2 = PCI Control Status 2 Register 2348 * 2349 * Control status register accessable from both PCI and NCB. 2350 */ 2351union cvmx_pci_ctl_status_2 2352{ 2353 uint32_t u32; 2354 struct cvmx_pci_ctl_status_2_s 2355 { 2356#if __BYTE_ORDER == __BIG_ENDIAN 2357 uint32_t reserved_29_31 : 3; 2358 uint32_t bb1_hole : 3; /**< Big BAR 1 Hole 2359 NOT IN PASS 1 NOR PASS 2 2360 When PCI_CTL_STATUS_2[BB1]=1, this field defines 2361 an encoded size of the upper BAR1 region which 2362 OCTEON will mask out (ie: not respond to). 2363 (see definition of BB1_HOLE and BB1_SIZ encodings 2364 in the PCI_CTL_STATUS_2[BB1] definition below). */ 2365 uint32_t bb1_siz : 1; /**< Big BAR 1 Size 2366 NOT IN PASS 1 NOR PASS 2 2367 When PCI_CTL_STATUS_2[BB1]=1, this field defines 2368 the programmable SIZE of BAR 1. 2369 - 0: 1GB / 1: 2GB */ 2370 uint32_t bb_ca : 1; /**< Set to '1' for Big Bar Mode to do STT/LDT L2C 2371 operations. 2372 NOT IN PASS 1 NOR PASS 2 */ 2373 uint32_t bb_es : 2; /**< Big Bar Node Endian Swap Mode 2374 - 0: No Swizzle 2375 - 1: Byte Swizzle (per-QW) 2376 - 2: Byte Swizzle (per-LW) 2377 - 3: LongWord Swizzle 2378 NOT IN PASS 1 NOR PASS 2 */ 2379 uint32_t bb1 : 1; /**< Big Bar 1 Enable 2380 NOT IN PASS 1 NOR PASS 2 2381 When PCI_CTL_STATUS_2[BB1] is set, the following differences 2382 occur: 2383 - OCTEON's BAR1 becomes somewhere in the range 512-2048 MB rather 2384 than the default 128MB. 2385 - The following table indicates the effective size of 2386 BAR1 when BB1 is set: 2387 BB1_SIZ BB1_HOLE Effective size Comment 2388 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2389 0 0 1024 MB Normal 1GB BAR 2390 0 1 1008 MB 1 GB, 16 MB hole 2391 0 2 992 MB 1 GB, 32 MB hole 2392 0 3 960 MB 1 GB, 64 MB hole 2393 0 4 896 MB 1 GB,128 MB hole 2394 0 5 768 MB 1 GB,256 MB hole 2395 0 6 512 MB 1 GB,512 MB hole 2396 0 7 Illegal 2397 1 0 2048 MB Normal 2GB BAR 2398 1 1 2032 MB 2 GB, 16 MB hole 2399 1 2 2016 MB 2 GB, 32 MB hole 2400 1 3 1984 MB 2 GB, 64 MB hole 2401 1 4 1920 MB 2 GB,128 MB hole 2402 1 5 1792 MB 2 GB,256 MB hole 2403 1 6 1536 MB 2 GB,512 MB hole 2404 1 7 Illegal 2405 - When BB1_SIZ is 0: PCI_CFG06[LBASE<2:0>] reads as zero 2406 and are ignored on write. BAR1 is an entirely ordinary 2407 1 GB (power-of-two) BAR in all aspects when BB1_HOLE is 0. 2408 When BB1_HOLE is not zero, BAR1 addresses are programmed 2409 as if the BAR were 1GB, but, OCTEON does not respond 2410 to addresses in the programmed holes. 2411 - When BB1_SIZ is 1: PCI_CFG06[LBASE<3:0>] reads as zero 2412 and are ignored on write. BAR1 is an entirely ordinary 2413 2 GB (power-of-two) BAR in all aspects when BB1_HOLE is 0. 2414 When BB1_HOLE is not zero, BAR1 addresses are programmed 2415 as if the BAR were 2GB, but, OCTEON does not respond 2416 to addresses in the programmed holes. 2417 - Note that the BB1_HOLE value has no effect on the 2418 PCI_CFG06[LBASE] behavior. BB1_HOLE only affects whether 2419 OCTEON accepts an address. BB1_SIZ does affect PCI_CFG06[LBASE] 2420 behavior, however. 2421 - The first 128MB, i.e. addresses on the PCI bus in the range 2422 BAR1+0 .. BAR1+0x07FFFFFF 2423 access OCTEON's DRAM addresses with PCI_BAR1_INDEX CSR's 2424 as before 2425 - The remaining address space, i.e. addresses 2426 on the PCI bus in the range 2427 BAR1+0x08000000 .. BAR1+size-1, 2428 where size is the size of BAR1 as selected by the above 2429 table (based on the BB1_SIZ and BB1_HOLE values), are mapped to 2430 OCTEON physical DRAM addresses as follows: 2431 PCI Address Range OCTEON Physical Address Range 2432 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2433 BAR1+0x08000000 .. BAR1+size-1 | 0x88000000 .. 0x7FFFFFFF+size 2434 and PCI_CTL_STATUS_2[BB_ES] is the endian-swap and 2435 PCI_CTL_STATUS_2[BB_CA] is the L2 cache allocation bit 2436 for these references. 2437 The consequences of any burst that crosses the end of the PCI 2438 Address Range for BAR1 are unpredicable. 2439 - The consequences of any burst access that crosses the boundary 2440 between BAR1+0x07FFFFFF and BAR1+0x08000000 are unpredictable in PCI-X 2441 mode. OCTEON may disconnect PCI references at this boundary. */ 2442 uint32_t bb0 : 1; /**< Big Bar 0 Enable 2443 NOT IN PASS 1 NOR PASS 2 2444 When PCI_CTL_STATUS_2[BB0] is set, the following 2445 differences occur: 2446 - OCTEON's BAR0 becomes 2GB rather than the default 4KB. 2447 PCI_CFG04[LBASE<18:0>] reads as zero and is ignored on write. 2448 - OCTEON's BAR0 becomes burstable. (When BB0 is clear, OCTEON 2449 single-phase disconnects PCI BAR0 reads and PCI/PCI-X BAR0 2450 writes, and splits (burstably) PCI-X BAR0 reads.) 2451 - The first 4KB, i.e. addresses on the PCI bus in the range 2452 BAR0+0 .. BAR0+0xFFF 2453 access OCTEON's PCI-type CSR's as when BB0 is clear. 2454 - The remaining address space, i.e. addresses on the PCI bus 2455 in the range 2456 BAR0+0x1000 .. BAR0+0x7FFFFFFF 2457 are mapped to OCTEON physical DRAM addresses as follows: 2458 PCI Address Range OCTEON Physical Address Range 2459 ------------------------------------+------------------------------ 2460 BAR0+0x00001000 .. BAR0+0x0FFFFFFF | 0x000001000 .. 0x00FFFFFFF 2461 BAR0+0x10000000 .. BAR0+0x1FFFFFFF | 0x410000000 .. 0x41FFFFFFF 2462 BAR0+0x20000000 .. BAR0+0x7FFFFFFF | 0x020000000 .. 0x07FFFFFFF 2463 and PCI_CTL_STATUS_2[BB_ES] is the endian-swap and 2464 PCI_CTL_STATUS_2[BB_CA] is the L2 cache allocation bit 2465 for these references. 2466 The consequences of any burst that crosses the end of the PCI 2467 Address Range for BAR0 are unpredicable. 2468 - The consequences of any burst access that crosses the boundary 2469 between BAR0+0xFFF and BAR0+0x1000 are unpredictable in PCI-X 2470 mode. OCTEON may disconnect PCI references at this boundary. 2471 - The results of any burst read that crosses the boundary 2472 between BAR0+0x0FFFFFFF and BAR0+0x10000000 are unpredictable. 2473 The consequences of any burst write that crosses this same 2474 boundary are unpredictable. 2475 - The results of any burst read that crosses the boundary 2476 between BAR0+0x1FFFFFFF and BAR0+0x20000000 are unpredictable. 2477 The consequences of any burst write that crosses this same 2478 boundary are unpredictable. */ 2479 uint32_t erst_n : 1; /**< Reset active Low. PASS-2 */ 2480 uint32_t bar2pres : 1; /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN]) 2481 is NOT blown the value of this field is '0' after 2482 reset and BAR2 is NOT present. When the fuse IS 2483 blown the value of this field is '1' after reset 2484 and BAR2 is present. Note that SW can change this 2485 field after reset. This is a PASS-2 field. */ 2486 uint32_t scmtyp : 1; /**< Split Completion Message CMD Type (0=RD/1=WR) 2487 When SCM=1, SCMTYP specifies the CMD intent (R/W) */ 2488 uint32_t scm : 1; /**< Split Completion Message Detected (Read or Write) */ 2489 uint32_t en_wfilt : 1; /**< When '1' the window-access filter is enabled. 2490 Unfilter writes are: 2491 MIO, SubId0 2492 MIO, SubId7 2493 NPI, SubId0 2494 NPI, SubId7 2495 POW, SubId7 2496 DFA, SubId7 2497 IPD, SubId7 2498 Unfiltered Reads are: 2499 MIO, SubId0 2500 MIO, SubId7 2501 NPI, SubId0 2502 NPI, SubId7 2503 POW, SubId1 2504 POW, SubId2 2505 POW, SubId3 2506 POW, SubId7 2507 DFA, SubId7 2508 IPD, SubId7 */ 2509 uint32_t reserved_14_14 : 1; 2510 uint32_t ap_pcix : 1; /**< PCX Core Mode status (0=PCI Bus/1=PCIX) 2511 If one or more of PCI_DEVSEL_N, PCI_STOP_N, and 2512 PCI_TRDY_N are asserted at the rising edge of 2513 PCI_RST_N, the device enters PCI-X mode. 2514 Otherwise, the device enters conventional PCI 2515 mode at the rising edge of RST#. */ 2516 uint32_t ap_64ad : 1; /**< PCX Core Bus status (0=32b Bus/1=64b Bus) 2517 When PCI_RST_N pin is de-asserted, the state 2518 of PCI_REQ64_N(driven by central agent) determines 2519 the width of the PCI/X bus. */ 2520 uint32_t b12_bist : 1; /**< Bist Status For Memeory In B12 */ 2521 uint32_t pmo_amod : 1; /**< PMO-ARB Mode (0=FP[HP=CMD1,LP=CMD0]/1=RR) */ 2522 uint32_t pmo_fpc : 3; /**< PMO-ARB Fixed Priority Counter 2523 When PMO_AMOD=0 (FP mode), this field represents 2524 the \# of CMD1 requests that are issued (at higher 2525 priority) before a single lower priority CMD0 2526 is allowed to issue (to ensure foward progress). 2527 - 0: 1 CMD1 Request issued before CMD0 allowed 2528 - ... 2529 - 7: 8 CMD1 Requests issued before CMD0 allowed */ 2530 uint32_t tsr_hwm : 3; /**< Target Split-Read ADB(allowable disconnect boundary) 2531 High Water Mark. 2532 Specifies the number of ADBs(128 Byte aligned chunks) 2533 that are accumulated(pending) BEFORE the Target Split 2534 completion is attempted on the PCI bus. 2535 - 0: RESERVED/ILLEGAL 2536 - 1: 2 Pending ADBs (129B-256B) 2537 - 2: 3 Pending ADBs (257B-384B) 2538 - 3: 4 Pending ADBs (385B-512B) 2539 - 4: 5 Pending ADBs (513B-640B) 2540 - 5: 6 Pending ADBs (641B-768B) 2541 - 6: 7 Pending ADBs (769B-896B) 2542 - 7: 8 Pending ADBs (897B-1024B) 2543 Example: Suppose a 1KB target memory request with 2544 starting byte offset address[6:0]=0x7F is split by 2545 the OCTEON and the TSR_HWM=1(2 ADBs). 2546 The OCTEON will start the target split completion 2547 on the PCI Bus after 1B(1st ADB)+128B(2nd ADB)=129B 2548 of data have been received from memory (even though 2549 the remaining 895B has not yet been received). The 2550 OCTEON will continue the split completion until it 2551 has consumed all of the pended split data. If the 2552 full transaction length(1KB) of data was NOT entirely 2553 transferred, then OCTEON will terminate the split 2554 completion and again wait for another 2 ADB-aligned data 2555 chunks(256B) of pended split data to be received from 2556 memory before starting another split completion request. 2557 This allows Octeon (as split completer), to send back 2558 multiple split completions for a given large split 2559 transaction without having to wait for the entire 2560 transaction length to be received from memory. 2561 NOTE: For split transaction sizes 'smaller' than the 2562 specified TSR_HWM value, the split completion 2563 is started when the last datum has been received from 2564 memory. 2565 NOTE: It is IMPERATIVE that this field NEVER BE 2566 written to a ZERO value. A value of zero is 2567 reserved/illegal and can result in PCIX bus hangs). */ 2568 uint32_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when 2569 clear '0' BAR2 access will be target-aborted. */ 2570 uint32_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to 2571 determine the endian swap mode. */ 2572 uint32_t bar2_cax : 1; /**< Value will be XORed with pci-address[38] to 2573 determine the L2 cache attribute. 2574 When XOR result is 1, not cached in L2 */ 2575#else 2576 uint32_t bar2_cax : 1; 2577 uint32_t bar2_esx : 2; 2578 uint32_t bar2_enb : 1; 2579 uint32_t tsr_hwm : 3; 2580 uint32_t pmo_fpc : 3; 2581 uint32_t pmo_amod : 1; 2582 uint32_t b12_bist : 1; 2583 uint32_t ap_64ad : 1; 2584 uint32_t ap_pcix : 1; 2585 uint32_t reserved_14_14 : 1; 2586 uint32_t en_wfilt : 1; 2587 uint32_t scm : 1; 2588 uint32_t scmtyp : 1; 2589 uint32_t bar2pres : 1; 2590 uint32_t erst_n : 1; 2591 uint32_t bb0 : 1; 2592 uint32_t bb1 : 1; 2593 uint32_t bb_es : 2; 2594 uint32_t bb_ca : 1; 2595 uint32_t bb1_siz : 1; 2596 uint32_t bb1_hole : 3; 2597 uint32_t reserved_29_31 : 3; 2598#endif 2599 } s; 2600 struct cvmx_pci_ctl_status_2_s cn30xx; 2601 struct cvmx_pci_ctl_status_2_cn31xx 2602 { 2603#if __BYTE_ORDER == __BIG_ENDIAN 2604 uint32_t reserved_20_31 : 12; 2605 uint32_t erst_n : 1; /**< Reset active Low. */ 2606 uint32_t bar2pres : 1; /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN]) 2607 is NOT blown the value of this field is '0' after 2608 reset and BAR2 is NOT present. When the fuse IS 2609 blown the value of this field is '1' after reset 2610 and BAR2 is present. Note that SW can change this 2611 field after reset. */ 2612 uint32_t scmtyp : 1; /**< Split Completion Message CMD Type (0=RD/1=WR) 2613 When SCM=1, SCMTYP specifies the CMD intent (R/W) */ 2614 uint32_t scm : 1; /**< Split Completion Message Detected (Read or Write) */ 2615 uint32_t en_wfilt : 1; /**< When '1' the window-access filter is enabled. 2616 Unfilter writes are: 2617 MIO, SubId0 2618 MIO, SubId7 2619 NPI, SubId0 2620 NPI, SubId7 2621 POW, SubId7 2622 DFA, SubId7 2623 IPD, SubId7 2624 USBN, SubId7 2625 Unfiltered Reads are: 2626 MIO, SubId0 2627 MIO, SubId7 2628 NPI, SubId0 2629 NPI, SubId7 2630 POW, SubId1 2631 POW, SubId2 2632 POW, SubId3 2633 POW, SubId7 2634 DFA, SubId7 2635 IPD, SubId7 2636 USBN, SubId7 */ 2637 uint32_t reserved_14_14 : 1; 2638 uint32_t ap_pcix : 1; /**< PCX Core Mode status (0=PCI Bus/1=PCIX) */ 2639 uint32_t ap_64ad : 1; /**< PCX Core Bus status (0=32b Bus/1=64b Bus) */ 2640 uint32_t b12_bist : 1; /**< Bist Status For Memeory In B12 */ 2641 uint32_t pmo_amod : 1; /**< PMO-ARB Mode (0=FP[HP=CMD1,LP=CMD0]/1=RR) */ 2642 uint32_t pmo_fpc : 3; /**< PMO-ARB Fixed Priority Counter 2643 When PMO_AMOD=0 (FP mode), this field represents 2644 the \# of CMD1 requests that are issued (at higher 2645 priority) before a single lower priority CMD0 2646 is allowed to issue (to ensure foward progress). 2647 - 0: 1 CMD1 Request issued before CMD0 allowed 2648 - ... 2649 - 7: 8 CMD1 Requests issued before CMD0 allowed */ 2650 uint32_t tsr_hwm : 3; /**< Target Split-Read ADB(allowable disconnect boundary) 2651 High Water Mark. 2652 Specifies the number of ADBs(128 Byte aligned chunks) 2653 that are accumulated(pending) BEFORE the Target Split 2654 completion is attempted on the PCI bus. 2655 - 0: RESERVED/ILLEGAL 2656 - 1: 2 Pending ADBs (129B-256B) 2657 - 2: 3 Pending ADBs (257B-384B) 2658 - 3: 4 Pending ADBs (385B-512B) 2659 - 4: 5 Pending ADBs (513B-640B) 2660 - 5: 6 Pending ADBs (641B-768B) 2661 - 6: 7 Pending ADBs (769B-896B) 2662 - 7: 8 Pending ADBs (897B-1024B) 2663 Example: Suppose a 1KB target memory request with 2664 starting byte offset address[6:0]=0x7F is split by 2665 the OCTEON and the TSR_HWM=1(2 ADBs). 2666 The OCTEON will start the target split completion 2667 on the PCI Bus after 1B(1st ADB)+128B(2nd ADB)=129B 2668 of data have been received from memory (even though 2669 the remaining 895B has not yet been received). The 2670 OCTEON will continue the split completion until it 2671 has consumed all of the pended split data. If the 2672 full transaction length(1KB) of data was NOT entirely 2673 transferred, then OCTEON will terminate the split 2674 completion and again wait for another 2 ADB-aligned data 2675 chunks(256B) of pended split data to be received from 2676 memory before starting another split completion request. 2677 This allows Octeon (as split completer), to send back 2678 multiple split completions for a given large split 2679 transaction without having to wait for the entire 2680 transaction length to be received from memory. 2681 NOTE: For split transaction sizes 'smaller' than the 2682 specified TSR_HWM value, the split completion 2683 is started when the last datum has been received from 2684 memory. 2685 NOTE: It is IMPERATIVE that this field NEVER BE 2686 written to a ZERO value. A value of zero is 2687 reserved/illegal and can result in PCIX bus hangs). */ 2688 uint32_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when 2689 clear '0' BAR2 access will be target-aborted. */ 2690 uint32_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to 2691 determine the endian swap mode. */ 2692 uint32_t bar2_cax : 1; /**< Value will be XORed with pci-address[38] to 2693 determine the L2 cache attribute. 2694 When XOR result is 1, not allocated in L2 cache */ 2695#else 2696 uint32_t bar2_cax : 1; 2697 uint32_t bar2_esx : 2; 2698 uint32_t bar2_enb : 1; 2699 uint32_t tsr_hwm : 3; 2700 uint32_t pmo_fpc : 3; 2701 uint32_t pmo_amod : 1; 2702 uint32_t b12_bist : 1; 2703 uint32_t ap_64ad : 1; 2704 uint32_t ap_pcix : 1; 2705 uint32_t reserved_14_14 : 1; 2706 uint32_t en_wfilt : 1; 2707 uint32_t scm : 1; 2708 uint32_t scmtyp : 1; 2709 uint32_t bar2pres : 1; 2710 uint32_t erst_n : 1; 2711 uint32_t reserved_20_31 : 12; 2712#endif 2713 } cn31xx; 2714 struct cvmx_pci_ctl_status_2_s cn38xx; 2715 struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2; 2716 struct cvmx_pci_ctl_status_2_s cn50xx; 2717 struct cvmx_pci_ctl_status_2_s cn58xx; 2718 struct cvmx_pci_ctl_status_2_s cn58xxp1; 2719}; 2720typedef union cvmx_pci_ctl_status_2 cvmx_pci_ctl_status_2_t; 2721 2722/** 2723 * cvmx_pci_dbell# 2724 * 2725 * PCI_DBELL0 = PCI Doorbell-0 2726 * 2727 * The value to write to the doorbell 0 register. The value in this register is acted upon when the 2728 * least-significant-byte of this register is written. 2729 */ 2730union cvmx_pci_dbellx 2731{ 2732 uint32_t u32; 2733 struct cvmx_pci_dbellx_s 2734 { 2735#if __BYTE_ORDER == __BIG_ENDIAN 2736 uint32_t reserved_16_31 : 16; 2737 uint32_t inc_val : 16; /**< Software writes this register with the 2738 number of new Instructions to be processed 2739 on the Instruction Queue. When read this 2740 register contains the last write value. */ 2741#else 2742 uint32_t inc_val : 16; 2743 uint32_t reserved_16_31 : 16; 2744#endif 2745 } s; 2746 struct cvmx_pci_dbellx_s cn30xx; 2747 struct cvmx_pci_dbellx_s cn31xx; 2748 struct cvmx_pci_dbellx_s cn38xx; 2749 struct cvmx_pci_dbellx_s cn38xxp2; 2750 struct cvmx_pci_dbellx_s cn50xx; 2751 struct cvmx_pci_dbellx_s cn58xx; 2752 struct cvmx_pci_dbellx_s cn58xxp1; 2753}; 2754typedef union cvmx_pci_dbellx cvmx_pci_dbellx_t; 2755 2756/** 2757 * cvmx_pci_dma_cnt# 2758 * 2759 * PCI_DMA_CNT0 = PCI DMA Count0 2760 * 2761 * Keeps track of the number of DMAs or bytes sent by DMAs. The value in this register is acted upon when the 2762 * least-significant-byte of this register is written. 2763 */ 2764union cvmx_pci_dma_cntx 2765{ 2766 uint32_t u32; 2767 struct cvmx_pci_dma_cntx_s 2768 { 2769#if __BYTE_ORDER == __BIG_ENDIAN 2770 uint32_t dma_cnt : 32; /**< Update with the number of DMAs completed or the 2771 number of bytes sent for DMA's associated with 2772 this counter. When this register is written the 2773 value written to [15:0] will be subtracted from 2774 the value in this register. */ 2775#else 2776 uint32_t dma_cnt : 32; 2777#endif 2778 } s; 2779 struct cvmx_pci_dma_cntx_s cn30xx; 2780 struct cvmx_pci_dma_cntx_s cn31xx; 2781 struct cvmx_pci_dma_cntx_s cn38xx; 2782 struct cvmx_pci_dma_cntx_s cn38xxp2; 2783 struct cvmx_pci_dma_cntx_s cn50xx; 2784 struct cvmx_pci_dma_cntx_s cn58xx; 2785 struct cvmx_pci_dma_cntx_s cn58xxp1; 2786}; 2787typedef union cvmx_pci_dma_cntx cvmx_pci_dma_cntx_t; 2788 2789/** 2790 * cvmx_pci_dma_int_lev# 2791 * 2792 * PCI_DMA_INT_LEV0 = PCI DMA Sent Interrupt Level For DMA 0 2793 * 2794 * Interrupt when the value in PCI_DMA_CNT0 is equal to or greater than the register value. 2795 */ 2796union cvmx_pci_dma_int_levx 2797{ 2798 uint32_t u32; 2799 struct cvmx_pci_dma_int_levx_s 2800 { 2801#if __BYTE_ORDER == __BIG_ENDIAN 2802 uint32_t pkt_cnt : 32; /**< When PCI_DMA_CNT0 exceeds the value in this 2803 DCNT0 will be set in PCI_INT_SUM and PCI_INT_SUM2. */ 2804#else 2805 uint32_t pkt_cnt : 32; 2806#endif 2807 } s; 2808 struct cvmx_pci_dma_int_levx_s cn30xx; 2809 struct cvmx_pci_dma_int_levx_s cn31xx; 2810 struct cvmx_pci_dma_int_levx_s cn38xx; 2811 struct cvmx_pci_dma_int_levx_s cn38xxp2; 2812 struct cvmx_pci_dma_int_levx_s cn50xx; 2813 struct cvmx_pci_dma_int_levx_s cn58xx; 2814 struct cvmx_pci_dma_int_levx_s cn58xxp1; 2815}; 2816typedef union cvmx_pci_dma_int_levx cvmx_pci_dma_int_levx_t; 2817 2818/** 2819 * cvmx_pci_dma_time# 2820 * 2821 * PCI_DMA_TIME0 = PCI DMA Sent Timer For DMA0 2822 * 2823 * Time to wait from DMA being sent before issuing an interrupt. 2824 */ 2825union cvmx_pci_dma_timex 2826{ 2827 uint32_t u32; 2828 struct cvmx_pci_dma_timex_s 2829 { 2830#if __BYTE_ORDER == __BIG_ENDIAN 2831 uint32_t dma_time : 32; /**< Number of PCI clock cycle to wait before 2832 setting DTIME0 in PCI_INT_SUM and PCI_INT_SUM2. 2833 After PCI_DMA_CNT0 becomes non-zero. 2834 The timer is reset when the 2835 PCI_INT_SUM[27] register is cleared. */ 2836#else 2837 uint32_t dma_time : 32; 2838#endif 2839 } s; 2840 struct cvmx_pci_dma_timex_s cn30xx; 2841 struct cvmx_pci_dma_timex_s cn31xx; 2842 struct cvmx_pci_dma_timex_s cn38xx; 2843 struct cvmx_pci_dma_timex_s cn38xxp2; 2844 struct cvmx_pci_dma_timex_s cn50xx; 2845 struct cvmx_pci_dma_timex_s cn58xx; 2846 struct cvmx_pci_dma_timex_s cn58xxp1; 2847}; 2848typedef union cvmx_pci_dma_timex cvmx_pci_dma_timex_t; 2849 2850/** 2851 * cvmx_pci_instr_count# 2852 * 2853 * PCI_INSTR_COUNT0 = PCI Instructions Outstanding Request Count 2854 * 2855 * The number of instructions to be fetched by the Instruction-0 Engine. 2856 */ 2857union cvmx_pci_instr_countx 2858{ 2859 uint32_t u32; 2860 struct cvmx_pci_instr_countx_s 2861 { 2862#if __BYTE_ORDER == __BIG_ENDIAN 2863 uint32_t icnt : 32; /**< Number of Instructions to be fetched by the 2864 Instruction Engine. 2865 A write of any non zero value to this register 2866 will clear the value of this register. */ 2867#else 2868 uint32_t icnt : 32; 2869#endif 2870 } s; 2871 struct cvmx_pci_instr_countx_s cn30xx; 2872 struct cvmx_pci_instr_countx_s cn31xx; 2873 struct cvmx_pci_instr_countx_s cn38xx; 2874 struct cvmx_pci_instr_countx_s cn38xxp2; 2875 struct cvmx_pci_instr_countx_s cn50xx; 2876 struct cvmx_pci_instr_countx_s cn58xx; 2877 struct cvmx_pci_instr_countx_s cn58xxp1; 2878}; 2879typedef union cvmx_pci_instr_countx cvmx_pci_instr_countx_t; 2880 2881/** 2882 * cvmx_pci_int_enb 2883 * 2884 * PCI_INT_ENB = PCI Interrupt Enable 2885 * 2886 * Enables interrupt bits in the PCI_INT_SUM register. 2887 */ 2888union cvmx_pci_int_enb 2889{ 2890 uint64_t u64; 2891 struct cvmx_pci_int_enb_s 2892 { 2893#if __BYTE_ORDER == __BIG_ENDIAN 2894 uint64_t reserved_34_63 : 30; 2895 uint64_t ill_rd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */ 2896 uint64_t ill_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */ 2897 uint64_t win_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */ 2898 uint64_t dma1_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */ 2899 uint64_t dma0_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */ 2900 uint64_t idtime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */ 2901 uint64_t idtime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */ 2902 uint64_t idcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */ 2903 uint64_t idcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */ 2904 uint64_t iptime3 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[24] */ 2905 uint64_t iptime2 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[23] */ 2906 uint64_t iptime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[22] */ 2907 uint64_t iptime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */ 2908 uint64_t ipcnt3 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[20] */ 2909 uint64_t ipcnt2 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[19] */ 2910 uint64_t ipcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[18] */ 2911 uint64_t ipcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */ 2912 uint64_t irsl_int : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */ 2913 uint64_t ill_rrd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */ 2914 uint64_t ill_rwr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */ 2915 uint64_t idperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */ 2916 uint64_t iaperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */ 2917 uint64_t iserr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */ 2918 uint64_t itsr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */ 2919 uint64_t imsc_msg : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */ 2920 uint64_t imsi_mabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */ 2921 uint64_t imsi_tabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */ 2922 uint64_t imsi_per : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */ 2923 uint64_t imr_tto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */ 2924 uint64_t imr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */ 2925 uint64_t itr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */ 2926 uint64_t imr_wtto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */ 2927 uint64_t imr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */ 2928 uint64_t itr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */ 2929#else 2930 uint64_t itr_wabt : 1; 2931 uint64_t imr_wabt : 1; 2932 uint64_t imr_wtto : 1; 2933 uint64_t itr_abt : 1; 2934 uint64_t imr_abt : 1; 2935 uint64_t imr_tto : 1; 2936 uint64_t imsi_per : 1; 2937 uint64_t imsi_tabt : 1; 2938 uint64_t imsi_mabt : 1; 2939 uint64_t imsc_msg : 1; 2940 uint64_t itsr_abt : 1; 2941 uint64_t iserr : 1; 2942 uint64_t iaperr : 1; 2943 uint64_t idperr : 1; 2944 uint64_t ill_rwr : 1; 2945 uint64_t ill_rrd : 1; 2946 uint64_t irsl_int : 1; 2947 uint64_t ipcnt0 : 1; 2948 uint64_t ipcnt1 : 1; 2949 uint64_t ipcnt2 : 1; 2950 uint64_t ipcnt3 : 1; 2951 uint64_t iptime0 : 1; 2952 uint64_t iptime1 : 1; 2953 uint64_t iptime2 : 1; 2954 uint64_t iptime3 : 1; 2955 uint64_t idcnt0 : 1; 2956 uint64_t idcnt1 : 1; 2957 uint64_t idtime0 : 1; 2958 uint64_t idtime1 : 1; 2959 uint64_t dma0_fi : 1; 2960 uint64_t dma1_fi : 1; 2961 uint64_t win_wr : 1; 2962 uint64_t ill_wr : 1; 2963 uint64_t ill_rd : 1; 2964 uint64_t reserved_34_63 : 30; 2965#endif 2966 } s; 2967 struct cvmx_pci_int_enb_cn30xx 2968 { 2969#if __BYTE_ORDER == __BIG_ENDIAN 2970 uint64_t reserved_34_63 : 30; 2971 uint64_t ill_rd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */ 2972 uint64_t ill_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */ 2973 uint64_t win_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */ 2974 uint64_t dma1_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */ 2975 uint64_t dma0_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */ 2976 uint64_t idtime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */ 2977 uint64_t idtime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */ 2978 uint64_t idcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */ 2979 uint64_t idcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */ 2980 uint64_t reserved_22_24 : 3; 2981 uint64_t iptime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */ 2982 uint64_t reserved_18_20 : 3; 2983 uint64_t ipcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */ 2984 uint64_t irsl_int : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */ 2985 uint64_t ill_rrd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */ 2986 uint64_t ill_rwr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */ 2987 uint64_t idperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */ 2988 uint64_t iaperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */ 2989 uint64_t iserr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */ 2990 uint64_t itsr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */ 2991 uint64_t imsc_msg : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */ 2992 uint64_t imsi_mabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */ 2993 uint64_t imsi_tabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */ 2994 uint64_t imsi_per : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */ 2995 uint64_t imr_tto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */ 2996 uint64_t imr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */ 2997 uint64_t itr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */ 2998 uint64_t imr_wtto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */ 2999 uint64_t imr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */ 3000 uint64_t itr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */ 3001#else 3002 uint64_t itr_wabt : 1; 3003 uint64_t imr_wabt : 1; 3004 uint64_t imr_wtto : 1; 3005 uint64_t itr_abt : 1; 3006 uint64_t imr_abt : 1; 3007 uint64_t imr_tto : 1; 3008 uint64_t imsi_per : 1; 3009 uint64_t imsi_tabt : 1; 3010 uint64_t imsi_mabt : 1; 3011 uint64_t imsc_msg : 1; 3012 uint64_t itsr_abt : 1; 3013 uint64_t iserr : 1; 3014 uint64_t iaperr : 1; 3015 uint64_t idperr : 1; 3016 uint64_t ill_rwr : 1; 3017 uint64_t ill_rrd : 1; 3018 uint64_t irsl_int : 1; 3019 uint64_t ipcnt0 : 1; 3020 uint64_t reserved_18_20 : 3; 3021 uint64_t iptime0 : 1; 3022 uint64_t reserved_22_24 : 3; 3023 uint64_t idcnt0 : 1; 3024 uint64_t idcnt1 : 1; 3025 uint64_t idtime0 : 1; 3026 uint64_t idtime1 : 1; 3027 uint64_t dma0_fi : 1; 3028 uint64_t dma1_fi : 1; 3029 uint64_t win_wr : 1; 3030 uint64_t ill_wr : 1; 3031 uint64_t ill_rd : 1; 3032 uint64_t reserved_34_63 : 30; 3033#endif 3034 } cn30xx; 3035 struct cvmx_pci_int_enb_cn31xx 3036 { 3037#if __BYTE_ORDER == __BIG_ENDIAN 3038 uint64_t reserved_34_63 : 30; 3039 uint64_t ill_rd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */ 3040 uint64_t ill_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */ 3041 uint64_t win_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */ 3042 uint64_t dma1_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */ 3043 uint64_t dma0_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */ 3044 uint64_t idtime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */ 3045 uint64_t idtime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */ 3046 uint64_t idcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */ 3047 uint64_t idcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */ 3048 uint64_t reserved_23_24 : 2; 3049 uint64_t iptime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[22] */ 3050 uint64_t iptime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */ 3051 uint64_t reserved_19_20 : 2; 3052 uint64_t ipcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[18] */ 3053 uint64_t ipcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */ 3054 uint64_t irsl_int : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */ 3055 uint64_t ill_rrd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */ 3056 uint64_t ill_rwr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */ 3057 uint64_t idperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */ 3058 uint64_t iaperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */ 3059 uint64_t iserr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */ 3060 uint64_t itsr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */ 3061 uint64_t imsc_msg : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */ 3062 uint64_t imsi_mabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */ 3063 uint64_t imsi_tabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */ 3064 uint64_t imsi_per : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */ 3065 uint64_t imr_tto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */ 3066 uint64_t imr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */ 3067 uint64_t itr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */ 3068 uint64_t imr_wtto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */ 3069 uint64_t imr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */ 3070 uint64_t itr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */ 3071#else 3072 uint64_t itr_wabt : 1; 3073 uint64_t imr_wabt : 1; 3074 uint64_t imr_wtto : 1; 3075 uint64_t itr_abt : 1; 3076 uint64_t imr_abt : 1; 3077 uint64_t imr_tto : 1; 3078 uint64_t imsi_per : 1; 3079 uint64_t imsi_tabt : 1; 3080 uint64_t imsi_mabt : 1; 3081 uint64_t imsc_msg : 1; 3082 uint64_t itsr_abt : 1; 3083 uint64_t iserr : 1; 3084 uint64_t iaperr : 1; 3085 uint64_t idperr : 1; 3086 uint64_t ill_rwr : 1; 3087 uint64_t ill_rrd : 1; 3088 uint64_t irsl_int : 1; 3089 uint64_t ipcnt0 : 1; 3090 uint64_t ipcnt1 : 1; 3091 uint64_t reserved_19_20 : 2; 3092 uint64_t iptime0 : 1; 3093 uint64_t iptime1 : 1; 3094 uint64_t reserved_23_24 : 2; 3095 uint64_t idcnt0 : 1; 3096 uint64_t idcnt1 : 1; 3097 uint64_t idtime0 : 1; 3098 uint64_t idtime1 : 1; 3099 uint64_t dma0_fi : 1; 3100 uint64_t dma1_fi : 1; 3101 uint64_t win_wr : 1; 3102 uint64_t ill_wr : 1; 3103 uint64_t ill_rd : 1; 3104 uint64_t reserved_34_63 : 30; 3105#endif 3106 } cn31xx; 3107 struct cvmx_pci_int_enb_s cn38xx; 3108 struct cvmx_pci_int_enb_s cn38xxp2; 3109 struct cvmx_pci_int_enb_cn31xx cn50xx; 3110 struct cvmx_pci_int_enb_s cn58xx; 3111 struct cvmx_pci_int_enb_s cn58xxp1; 3112}; 3113typedef union cvmx_pci_int_enb cvmx_pci_int_enb_t; 3114 3115/** 3116 * cvmx_pci_int_enb2 3117 * 3118 * PCI_INT_ENB2 = PCI Interrupt Enable2 Register 3119 * 3120 * Enables interrupt bits in the PCI_INT_SUM2 register. 3121 */ 3122union cvmx_pci_int_enb2 3123{ 3124 uint64_t u64; 3125 struct cvmx_pci_int_enb2_s 3126 { 3127#if __BYTE_ORDER == __BIG_ENDIAN 3128 uint64_t reserved_34_63 : 30; 3129 uint64_t ill_rd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */ 3130 uint64_t ill_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */ 3131 uint64_t win_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */ 3132 uint64_t dma1_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */ 3133 uint64_t dma0_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */ 3134 uint64_t rdtime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */ 3135 uint64_t rdtime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */ 3136 uint64_t rdcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */ 3137 uint64_t rdcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */ 3138 uint64_t rptime3 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[24] */ 3139 uint64_t rptime2 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[23] */ 3140 uint64_t rptime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[22] */ 3141 uint64_t rptime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */ 3142 uint64_t rpcnt3 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[20] */ 3143 uint64_t rpcnt2 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[19] */ 3144 uint64_t rpcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[18] */ 3145 uint64_t rpcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */ 3146 uint64_t rrsl_int : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */ 3147 uint64_t ill_rrd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */ 3148 uint64_t ill_rwr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */ 3149 uint64_t rdperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */ 3150 uint64_t raperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */ 3151 uint64_t rserr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */ 3152 uint64_t rtsr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */ 3153 uint64_t rmsc_msg : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */ 3154 uint64_t rmsi_mabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */ 3155 uint64_t rmsi_tabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */ 3156 uint64_t rmsi_per : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */ 3157 uint64_t rmr_tto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */ 3158 uint64_t rmr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */ 3159 uint64_t rtr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */ 3160 uint64_t rmr_wtto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */ 3161 uint64_t rmr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */ 3162 uint64_t rtr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */ 3163#else 3164 uint64_t rtr_wabt : 1; 3165 uint64_t rmr_wabt : 1; 3166 uint64_t rmr_wtto : 1; 3167 uint64_t rtr_abt : 1; 3168 uint64_t rmr_abt : 1; 3169 uint64_t rmr_tto : 1; 3170 uint64_t rmsi_per : 1; 3171 uint64_t rmsi_tabt : 1; 3172 uint64_t rmsi_mabt : 1; 3173 uint64_t rmsc_msg : 1; 3174 uint64_t rtsr_abt : 1; 3175 uint64_t rserr : 1; 3176 uint64_t raperr : 1; 3177 uint64_t rdperr : 1; 3178 uint64_t ill_rwr : 1; 3179 uint64_t ill_rrd : 1; 3180 uint64_t rrsl_int : 1; 3181 uint64_t rpcnt0 : 1; 3182 uint64_t rpcnt1 : 1; 3183 uint64_t rpcnt2 : 1; 3184 uint64_t rpcnt3 : 1; 3185 uint64_t rptime0 : 1; 3186 uint64_t rptime1 : 1; 3187 uint64_t rptime2 : 1; 3188 uint64_t rptime3 : 1; 3189 uint64_t rdcnt0 : 1; 3190 uint64_t rdcnt1 : 1; 3191 uint64_t rdtime0 : 1; 3192 uint64_t rdtime1 : 1; 3193 uint64_t dma0_fi : 1; 3194 uint64_t dma1_fi : 1; 3195 uint64_t win_wr : 1; 3196 uint64_t ill_wr : 1; 3197 uint64_t ill_rd : 1; 3198 uint64_t reserved_34_63 : 30; 3199#endif 3200 } s; 3201 struct cvmx_pci_int_enb2_cn30xx 3202 { 3203#if __BYTE_ORDER == __BIG_ENDIAN 3204 uint64_t reserved_34_63 : 30; 3205 uint64_t ill_rd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */ 3206 uint64_t ill_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */ 3207 uint64_t win_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */ 3208 uint64_t dma1_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */ 3209 uint64_t dma0_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */ 3210 uint64_t rdtime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */ 3211 uint64_t rdtime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */ 3212 uint64_t rdcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */ 3213 uint64_t rdcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */ 3214 uint64_t reserved_22_24 : 3; 3215 uint64_t rptime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */ 3216 uint64_t reserved_18_20 : 3; 3217 uint64_t rpcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */ 3218 uint64_t rrsl_int : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */ 3219 uint64_t ill_rrd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */ 3220 uint64_t ill_rwr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */ 3221 uint64_t rdperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */ 3222 uint64_t raperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */ 3223 uint64_t rserr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */ 3224 uint64_t rtsr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */ 3225 uint64_t rmsc_msg : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */ 3226 uint64_t rmsi_mabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */ 3227 uint64_t rmsi_tabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */ 3228 uint64_t rmsi_per : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */ 3229 uint64_t rmr_tto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */ 3230 uint64_t rmr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */ 3231 uint64_t rtr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */ 3232 uint64_t rmr_wtto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */ 3233 uint64_t rmr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */ 3234 uint64_t rtr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */ 3235#else 3236 uint64_t rtr_wabt : 1; 3237 uint64_t rmr_wabt : 1; 3238 uint64_t rmr_wtto : 1; 3239 uint64_t rtr_abt : 1; 3240 uint64_t rmr_abt : 1; 3241 uint64_t rmr_tto : 1; 3242 uint64_t rmsi_per : 1; 3243 uint64_t rmsi_tabt : 1; 3244 uint64_t rmsi_mabt : 1; 3245 uint64_t rmsc_msg : 1; 3246 uint64_t rtsr_abt : 1; 3247 uint64_t rserr : 1; 3248 uint64_t raperr : 1; 3249 uint64_t rdperr : 1; 3250 uint64_t ill_rwr : 1; 3251 uint64_t ill_rrd : 1; 3252 uint64_t rrsl_int : 1; 3253 uint64_t rpcnt0 : 1; 3254 uint64_t reserved_18_20 : 3; 3255 uint64_t rptime0 : 1; 3256 uint64_t reserved_22_24 : 3; 3257 uint64_t rdcnt0 : 1; 3258 uint64_t rdcnt1 : 1; 3259 uint64_t rdtime0 : 1; 3260 uint64_t rdtime1 : 1; 3261 uint64_t dma0_fi : 1; 3262 uint64_t dma1_fi : 1; 3263 uint64_t win_wr : 1; 3264 uint64_t ill_wr : 1; 3265 uint64_t ill_rd : 1; 3266 uint64_t reserved_34_63 : 30; 3267#endif 3268 } cn30xx; 3269 struct cvmx_pci_int_enb2_cn31xx 3270 { 3271#if __BYTE_ORDER == __BIG_ENDIAN 3272 uint64_t reserved_34_63 : 30; 3273 uint64_t ill_rd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */ 3274 uint64_t ill_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */ 3275 uint64_t win_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */ 3276 uint64_t dma1_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */ 3277 uint64_t dma0_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */ 3278 uint64_t rdtime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */ 3279 uint64_t rdtime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */ 3280 uint64_t rdcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */ 3281 uint64_t rdcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */ 3282 uint64_t reserved_23_24 : 2; 3283 uint64_t rptime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[22] */ 3284 uint64_t rptime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */ 3285 uint64_t reserved_19_20 : 2; 3286 uint64_t rpcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[18] */ 3287 uint64_t rpcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */ 3288 uint64_t rrsl_int : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */ 3289 uint64_t ill_rrd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */ 3290 uint64_t ill_rwr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */ 3291 uint64_t rdperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */ 3292 uint64_t raperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */ 3293 uint64_t rserr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */ 3294 uint64_t rtsr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */ 3295 uint64_t rmsc_msg : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */ 3296 uint64_t rmsi_mabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */ 3297 uint64_t rmsi_tabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */ 3298 uint64_t rmsi_per : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */ 3299 uint64_t rmr_tto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */ 3300 uint64_t rmr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */ 3301 uint64_t rtr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */ 3302 uint64_t rmr_wtto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */ 3303 uint64_t rmr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */ 3304 uint64_t rtr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */ 3305#else 3306 uint64_t rtr_wabt : 1; 3307 uint64_t rmr_wabt : 1; 3308 uint64_t rmr_wtto : 1; 3309 uint64_t rtr_abt : 1; 3310 uint64_t rmr_abt : 1; 3311 uint64_t rmr_tto : 1; 3312 uint64_t rmsi_per : 1; 3313 uint64_t rmsi_tabt : 1; 3314 uint64_t rmsi_mabt : 1; 3315 uint64_t rmsc_msg : 1; 3316 uint64_t rtsr_abt : 1; 3317 uint64_t rserr : 1; 3318 uint64_t raperr : 1; 3319 uint64_t rdperr : 1; 3320 uint64_t ill_rwr : 1; 3321 uint64_t ill_rrd : 1; 3322 uint64_t rrsl_int : 1; 3323 uint64_t rpcnt0 : 1; 3324 uint64_t rpcnt1 : 1; 3325 uint64_t reserved_19_20 : 2; 3326 uint64_t rptime0 : 1; 3327 uint64_t rptime1 : 1; 3328 uint64_t reserved_23_24 : 2; 3329 uint64_t rdcnt0 : 1; 3330 uint64_t rdcnt1 : 1; 3331 uint64_t rdtime0 : 1; 3332 uint64_t rdtime1 : 1; 3333 uint64_t dma0_fi : 1; 3334 uint64_t dma1_fi : 1; 3335 uint64_t win_wr : 1; 3336 uint64_t ill_wr : 1; 3337 uint64_t ill_rd : 1; 3338 uint64_t reserved_34_63 : 30; 3339#endif 3340 } cn31xx; 3341 struct cvmx_pci_int_enb2_s cn38xx; 3342 struct cvmx_pci_int_enb2_s cn38xxp2; 3343 struct cvmx_pci_int_enb2_cn31xx cn50xx; 3344 struct cvmx_pci_int_enb2_s cn58xx; 3345 struct cvmx_pci_int_enb2_s cn58xxp1; 3346}; 3347typedef union cvmx_pci_int_enb2 cvmx_pci_int_enb2_t; 3348 3349/** 3350 * cvmx_pci_int_sum 3351 * 3352 * PCI_INT_SUM = PCI Interrupt Summary 3353 * 3354 * The PCI Interrupt Summary Register. 3355 */ 3356union cvmx_pci_int_sum 3357{ 3358 uint64_t u64; 3359 struct cvmx_pci_int_sum_s 3360 { 3361#if __BYTE_ORDER == __BIG_ENDIAN 3362 uint64_t reserved_34_63 : 30; 3363 uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3364 when the mem area is disabled. */ 3365 uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3366 when the mem area is disabled. */ 3367 uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3368 Read-Address Register took place. */ 3369 uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3370 required to set the FORCE-INT bit for counter 1. */ 3371 uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3372 required to set the FORCE-INT bit for counter 0. */ 3373 uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3374 register is not 0 the DMA_CNT1 timer counts. 3375 When the DMA1_CNT timer has a value greater 3376 than the PCI_DMA_TIME1 register this 3377 bit is set. The timer is reset when bit is 3378 written with a one. */ 3379 uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3380 register is not 0 the DMA_CNT0 timer counts. 3381 When the DMA0_CNT timer has a value greater 3382 than the PCI_DMA_TIME0 register this 3383 bit is set. The timer is reset when bit is 3384 written with a one. */ 3385 uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3386 value is greater than the value 3387 in the PCI_DMA_INT_LEV1 register. */ 3388 uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3389 value is greater than the value 3390 in the PCI_DMA_INT_LEV0 register. */ 3391 uint64_t ptime3 : 1; /**< When the value in the PCI_PKTS_SENT3 3392 register is not 0 the Sent-3 timer counts. 3393 When the Sent-3 timer has a value greater 3394 than the PCI_PKTS_SENT_TIME3 register this 3395 bit is set. The timer is reset when bit is 3396 written with a one. */ 3397 uint64_t ptime2 : 1; /**< When the value in the PCI_PKTS_SENT2 3398 register is not 0 the Sent-2 timer counts. 3399 When the Sent-2 timer has a value greater 3400 than the PCI_PKTS_SENT_TIME2 register this 3401 bit is set. The timer is reset when bit is 3402 written with a one. */ 3403 uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 3404 register is not 0 the Sent-1 timer counts. 3405 When the Sent-1 timer has a value greater 3406 than the PCI_PKTS_SENT_TIME1 register this 3407 bit is set. The timer is reset when bit is 3408 written with a one. */ 3409 uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3410 register is not 0 the Sent-0 timer counts. 3411 When the Sent-0 timer has a value greater 3412 than the PCI_PKTS_SENT_TIME0 register this 3413 bit is set. The timer is reset when bit is 3414 written with a one. */ 3415 uint64_t pcnt3 : 1; /**< This bit indicates that PCI_PKTS_SENT3 3416 value is greater than the value 3417 in the PCI_PKTS_SENT_INT_LEV3 register. */ 3418 uint64_t pcnt2 : 1; /**< This bit indicates that PCI_PKTS_SENT2 3419 value is greater than the value 3420 in the PCI_PKTS_SENT_INT_LEV2 register. */ 3421 uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 3422 value is greater than the value 3423 in the PCI_PKTS_SENT_INT_LEV1 register. */ 3424 uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3425 value is greater than the value 3426 in the PCI_PKTS_SENT_INT_LEV0 register. */ 3427 uint64_t rsl_int : 1; /**< This bit is set when the mio_pci_inta_dr wire 3428 is asserted by the MIO. */ 3429 uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3430 uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3431 uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3432 uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3433 uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3434 uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected 3435 CN58XX (as completer), has encountered an error 3436 which prevents the split transaction from 3437 completing. In this event, the CN58XX (as completer), 3438 sends a SCM (Split Completion Message) to the 3439 initiator. See: PCIX Spec v1.0a Fig 2-40. 3440 [31:28]: Message Class = 2(completer error) 3441 [27:20]: Message Index = 0x80 3442 [18:12]: Remaining Lower Address 3443 [11:0]: Remaining Byte Count */ 3444 uint64_t msc_msg : 1; /**< Master Split Completion Message (SCM) Detected 3445 for either a Split-Read/Write error case. 3446 Set if: 3447 a) A Split-Write SCM is detected with SCE=1. 3448 b) A Split-Read SCM is detected (regardless 3449 of SCE status). 3450 The Split completion message(SCM) 3451 is also latched into the PCI_SCM_REG[SCM] to 3452 assist SW with error recovery. */ 3453 uint64_t msi_mabt : 1; /**< PCI Master Abort on Master MSI */ 3454 uint64_t msi_tabt : 1; /**< PCI Target-Abort on Master MSI */ 3455 uint64_t msi_per : 1; /**< PCI Parity Error on Master MSI */ 3456 uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Master-Read */ 3457 uint64_t mr_abt : 1; /**< PCI Master Abort On Master-Read */ 3458 uint64_t tr_abt : 1; /**< PCI Target Abort On Master-Read */ 3459 uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on Master-write */ 3460 uint64_t mr_wabt : 1; /**< PCI Master Abort detected on Master-write */ 3461 uint64_t tr_wabt : 1; /**< PCI Target Abort detected on Master-write */ 3462#else 3463 uint64_t tr_wabt : 1; 3464 uint64_t mr_wabt : 1; 3465 uint64_t mr_wtto : 1; 3466 uint64_t tr_abt : 1; 3467 uint64_t mr_abt : 1; 3468 uint64_t mr_tto : 1; 3469 uint64_t msi_per : 1; 3470 uint64_t msi_tabt : 1; 3471 uint64_t msi_mabt : 1; 3472 uint64_t msc_msg : 1; 3473 uint64_t tsr_abt : 1; 3474 uint64_t serr : 1; 3475 uint64_t aperr : 1; 3476 uint64_t dperr : 1; 3477 uint64_t ill_rwr : 1; 3478 uint64_t ill_rrd : 1; 3479 uint64_t rsl_int : 1; 3480 uint64_t pcnt0 : 1; 3481 uint64_t pcnt1 : 1; 3482 uint64_t pcnt2 : 1; 3483 uint64_t pcnt3 : 1; 3484 uint64_t ptime0 : 1; 3485 uint64_t ptime1 : 1; 3486 uint64_t ptime2 : 1; 3487 uint64_t ptime3 : 1; 3488 uint64_t dcnt0 : 1; 3489 uint64_t dcnt1 : 1; 3490 uint64_t dtime0 : 1; 3491 uint64_t dtime1 : 1; 3492 uint64_t dma0_fi : 1; 3493 uint64_t dma1_fi : 1; 3494 uint64_t win_wr : 1; 3495 uint64_t ill_wr : 1; 3496 uint64_t ill_rd : 1; 3497 uint64_t reserved_34_63 : 30; 3498#endif 3499 } s; 3500 struct cvmx_pci_int_sum_cn30xx 3501 { 3502#if __BYTE_ORDER == __BIG_ENDIAN 3503 uint64_t reserved_34_63 : 30; 3504 uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3505 when the mem area is disabled. */ 3506 uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3507 when the mem area is disabled. */ 3508 uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3509 Read-Address Register took place. */ 3510 uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3511 required to set the FORCE-INT bit for counter 1. */ 3512 uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3513 required to set the FORCE-INT bit for counter 0. */ 3514 uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3515 register is not 0 the DMA_CNT1 timer counts. 3516 When the DMA1_CNT timer has a value greater 3517 than the PCI_DMA_TIME1 register this 3518 bit is set. The timer is reset when bit is 3519 written with a one. */ 3520 uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3521 register is not 0 the DMA_CNT0 timer counts. 3522 When the DMA0_CNT timer has a value greater 3523 than the PCI_DMA_TIME0 register this 3524 bit is set. The timer is reset when bit is 3525 written with a one. */ 3526 uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3527 value is greater than the value 3528 in the PCI_DMA_INT_LEV1 register. */ 3529 uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3530 value is greater than the value 3531 in the PCI_DMA_INT_LEV0 register. */ 3532 uint64_t reserved_22_24 : 3; 3533 uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3534 register is not 0 the Sent-0 timer counts. 3535 When the Sent-0 timer has a value greater 3536 than the PCI_PKTS_SENT_TIME0 register this 3537 bit is set. The timer is reset when bit is 3538 written with a one. */ 3539 uint64_t reserved_18_20 : 3; 3540 uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3541 value is greater than the value 3542 in the PCI_PKTS_SENT_INT_LEV0 register. */ 3543 uint64_t rsl_int : 1; /**< This bit is set when the mio_pci_inta_dr wire 3544 is asserted by the MIO */ 3545 uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3546 uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3547 uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3548 uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3549 uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3550 uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected 3551 N3K (as completer), has encountered an error 3552 which prevents the split transaction from 3553 completing. In this event, the N3K (as completer), 3554 sends a SCM (Split Completion Message) to the 3555 initiator. See: PCIX Spec v1.0a Fig 2-40. 3556 [31:28]: Message Class = 2(completer error) 3557 [27:20]: Message Index = 0x80 3558 [18:12]: Remaining Lower Address 3559 [11:0]: Remaining Byte Count */ 3560 uint64_t msc_msg : 1; /**< Master Split Completion Message (SCM) Detected 3561 for either a Split-Read/Write error case. 3562 Set if: 3563 a) A Split-Write SCM is detected with SCE=1. 3564 b) A Split-Read SCM is detected (regardless 3565 of SCE status). 3566 The Split completion message(SCM) 3567 is also latched into the PCI_SCM_REG[SCM] to 3568 assist SW with error recovery. */ 3569 uint64_t msi_mabt : 1; /**< PCI Master Abort on Master MSI */ 3570 uint64_t msi_tabt : 1; /**< PCI Target-Abort on Master MSI */ 3571 uint64_t msi_per : 1; /**< PCI Parity Error on Master MSI */ 3572 uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Master-Read */ 3573 uint64_t mr_abt : 1; /**< PCI Master Abort On Master-Read */ 3574 uint64_t tr_abt : 1; /**< PCI Target Abort On Master-Read */ 3575 uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on Master-write */ 3576 uint64_t mr_wabt : 1; /**< PCI Master Abort detected on Master-write */ 3577 uint64_t tr_wabt : 1; /**< PCI Target Abort detected on Master-write */ 3578#else 3579 uint64_t tr_wabt : 1; 3580 uint64_t mr_wabt : 1; 3581 uint64_t mr_wtto : 1; 3582 uint64_t tr_abt : 1; 3583 uint64_t mr_abt : 1; 3584 uint64_t mr_tto : 1; 3585 uint64_t msi_per : 1; 3586 uint64_t msi_tabt : 1; 3587 uint64_t msi_mabt : 1; 3588 uint64_t msc_msg : 1; 3589 uint64_t tsr_abt : 1; 3590 uint64_t serr : 1; 3591 uint64_t aperr : 1; 3592 uint64_t dperr : 1; 3593 uint64_t ill_rwr : 1; 3594 uint64_t ill_rrd : 1; 3595 uint64_t rsl_int : 1; 3596 uint64_t pcnt0 : 1; 3597 uint64_t reserved_18_20 : 3; 3598 uint64_t ptime0 : 1; 3599 uint64_t reserved_22_24 : 3; 3600 uint64_t dcnt0 : 1; 3601 uint64_t dcnt1 : 1; 3602 uint64_t dtime0 : 1; 3603 uint64_t dtime1 : 1; 3604 uint64_t dma0_fi : 1; 3605 uint64_t dma1_fi : 1; 3606 uint64_t win_wr : 1; 3607 uint64_t ill_wr : 1; 3608 uint64_t ill_rd : 1; 3609 uint64_t reserved_34_63 : 30; 3610#endif 3611 } cn30xx; 3612 struct cvmx_pci_int_sum_cn31xx 3613 { 3614#if __BYTE_ORDER == __BIG_ENDIAN 3615 uint64_t reserved_34_63 : 30; 3616 uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3617 when the mem area is disabled. */ 3618 uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3619 when the mem area is disabled. */ 3620 uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3621 Read-Address Register took place. */ 3622 uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3623 required to set the FORCE-INT bit for counter 1. */ 3624 uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3625 required to set the FORCE-INT bit for counter 0. */ 3626 uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3627 register is not 0 the DMA_CNT1 timer counts. 3628 When the DMA1_CNT timer has a value greater 3629 than the PCI_DMA_TIME1 register this 3630 bit is set. The timer is reset when bit is 3631 written with a one. */ 3632 uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3633 register is not 0 the DMA_CNT0 timer counts. 3634 When the DMA0_CNT timer has a value greater 3635 than the PCI_DMA_TIME0 register this 3636 bit is set. The timer is reset when bit is 3637 written with a one. */ 3638 uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3639 value is greater than the value 3640 in the PCI_DMA_INT_LEV1 register. */ 3641 uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3642 value is greater than the value 3643 in the PCI_DMA_INT_LEV0 register. */ 3644 uint64_t reserved_23_24 : 2; 3645 uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 3646 register is not 0 the Sent-1 timer counts. 3647 When the Sent-1 timer has a value greater 3648 than the PCI_PKTS_SENT_TIME1 register this 3649 bit is set. The timer is reset when bit is 3650 written with a one. */ 3651 uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3652 register is not 0 the Sent-0 timer counts. 3653 When the Sent-0 timer has a value greater 3654 than the PCI_PKTS_SENT_TIME0 register this 3655 bit is set. The timer is reset when bit is 3656 written with a one. */ 3657 uint64_t reserved_19_20 : 2; 3658 uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 3659 value is greater than the value 3660 in the PCI_PKTS_SENT_INT_LEV1 register. */ 3661 uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3662 value is greater than the value 3663 in the PCI_PKTS_SENT_INT_LEV0 register. */ 3664 uint64_t rsl_int : 1; /**< This bit is set when the mio_pci_inta_dr wire 3665 is asserted by the MIO */ 3666 uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3667 uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3668 uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3669 uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3670 uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3671 uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected 3672 N3K (as completer), has encountered an error 3673 which prevents the split transaction from 3674 completing. In this event, the N3K (as completer), 3675 sends a SCM (Split Completion Message) to the 3676 initiator. See: PCIX Spec v1.0a Fig 2-40. 3677 [31:28]: Message Class = 2(completer error) 3678 [27:20]: Message Index = 0x80 3679 [18:12]: Remaining Lower Address 3680 [11:0]: Remaining Byte Count */ 3681 uint64_t msc_msg : 1; /**< Master Split Completion Message (SCM) Detected 3682 for either a Split-Read/Write error case. 3683 Set if: 3684 a) A Split-Write SCM is detected with SCE=1. 3685 b) A Split-Read SCM is detected (regardless 3686 of SCE status). 3687 The Split completion message(SCM) 3688 is also latched into the PCI_SCM_REG[SCM] to 3689 assist SW with error recovery. */ 3690 uint64_t msi_mabt : 1; /**< PCI Master Abort on Master MSI */ 3691 uint64_t msi_tabt : 1; /**< PCI Target-Abort on Master MSI */ 3692 uint64_t msi_per : 1; /**< PCI Parity Error on Master MSI */ 3693 uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Master-Read */ 3694 uint64_t mr_abt : 1; /**< PCI Master Abort On Master-Read */ 3695 uint64_t tr_abt : 1; /**< PCI Target Abort On Master-Read */ 3696 uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on Master-write */ 3697 uint64_t mr_wabt : 1; /**< PCI Master Abort detected on Master-write */ 3698 uint64_t tr_wabt : 1; /**< PCI Target Abort detected on Master-write */ 3699#else 3700 uint64_t tr_wabt : 1; 3701 uint64_t mr_wabt : 1; 3702 uint64_t mr_wtto : 1; 3703 uint64_t tr_abt : 1; 3704 uint64_t mr_abt : 1; 3705 uint64_t mr_tto : 1; 3706 uint64_t msi_per : 1; 3707 uint64_t msi_tabt : 1; 3708 uint64_t msi_mabt : 1; 3709 uint64_t msc_msg : 1; 3710 uint64_t tsr_abt : 1; 3711 uint64_t serr : 1; 3712 uint64_t aperr : 1; 3713 uint64_t dperr : 1; 3714 uint64_t ill_rwr : 1; 3715 uint64_t ill_rrd : 1; 3716 uint64_t rsl_int : 1; 3717 uint64_t pcnt0 : 1; 3718 uint64_t pcnt1 : 1; 3719 uint64_t reserved_19_20 : 2; 3720 uint64_t ptime0 : 1; 3721 uint64_t ptime1 : 1; 3722 uint64_t reserved_23_24 : 2; 3723 uint64_t dcnt0 : 1; 3724 uint64_t dcnt1 : 1; 3725 uint64_t dtime0 : 1; 3726 uint64_t dtime1 : 1; 3727 uint64_t dma0_fi : 1; 3728 uint64_t dma1_fi : 1; 3729 uint64_t win_wr : 1; 3730 uint64_t ill_wr : 1; 3731 uint64_t ill_rd : 1; 3732 uint64_t reserved_34_63 : 30; 3733#endif 3734 } cn31xx; 3735 struct cvmx_pci_int_sum_s cn38xx; 3736 struct cvmx_pci_int_sum_s cn38xxp2; 3737 struct cvmx_pci_int_sum_cn31xx cn50xx; 3738 struct cvmx_pci_int_sum_s cn58xx; 3739 struct cvmx_pci_int_sum_s cn58xxp1; 3740}; 3741typedef union cvmx_pci_int_sum cvmx_pci_int_sum_t; 3742 3743/** 3744 * cvmx_pci_int_sum2 3745 * 3746 * PCI_INT_SUM2 = PCI Interrupt Summary2 Register 3747 * 3748 * The PCI Interrupt Summary2 Register copy used for RSL interrupts. 3749 */ 3750union cvmx_pci_int_sum2 3751{ 3752 uint64_t u64; 3753 struct cvmx_pci_int_sum2_s 3754 { 3755#if __BYTE_ORDER == __BIG_ENDIAN 3756 uint64_t reserved_34_63 : 30; 3757 uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3758 when the mem area is disabled. */ 3759 uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3760 when the mem area is disabled. */ 3761 uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3762 Read-Address Register took place. */ 3763 uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3764 required to set the FORCE-INT bit for counter 1. */ 3765 uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3766 required to set the FORCE-INT bit for counter 0. */ 3767 uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3768 register is not 0 the DMA_CNT1 timer counts. 3769 When the DMA1_CNT timer has a value greater 3770 than the PCI_DMA_TIME1 register this 3771 bit is set. The timer is reset when bit is 3772 written with a one. */ 3773 uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3774 register is not 0 the DMA_CNT0 timer counts. 3775 When the DMA0_CNT timer has a value greater 3776 than the PCI_DMA_TIME0 register this 3777 bit is set. The timer is reset when bit is 3778 written with a one. */ 3779 uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3780 value is greater than the value 3781 in the PCI_DMA_INT_LEV1 register. */ 3782 uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3783 value is greater than the value 3784 in the PCI_DMA_INT_LEV0 register. */ 3785 uint64_t ptime3 : 1; /**< When the value in the PCI_PKTS_SENT3 3786 register is not 0 the Sent-3 timer counts. 3787 When the Sent-3 timer has a value greater 3788 than the PCI_PKTS_SENT_TIME3 register this 3789 bit is set. The timer is reset when bit is 3790 written with a one. */ 3791 uint64_t ptime2 : 1; /**< When the value in the PCI_PKTS_SENT2 3792 register is not 0 the Sent-2 timer counts. 3793 When the Sent-2 timer has a value greater 3794 than the PCI_PKTS_SENT_TIME2 register this 3795 bit is set. The timer is reset when bit is 3796 written with a one. */ 3797 uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 3798 register is not 0 the Sent-1 timer counts. 3799 When the Sent-1 timer has a value greater 3800 than the PCI_PKTS_SENT_TIME1 register this 3801 bit is set. The timer is reset when bit is 3802 written with a one. */ 3803 uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3804 register is not 0 the Sent-0 timer counts. 3805 When the Sent-0 timer has a value greater 3806 than the PCI_PKTS_SENT_TIME0 register this 3807 bit is set. The timer is reset when bit is 3808 written with a one. */ 3809 uint64_t pcnt3 : 1; /**< This bit indicates that PCI_PKTS_SENT3 3810 value is greater than the value 3811 in the PCI_PKTS_SENT_INT_LEV3 register. */ 3812 uint64_t pcnt2 : 1; /**< This bit indicates that PCI_PKTS_SENT2 3813 value is greater than the value 3814 in the PCI_PKTS_SENT_INT_LEV2 register. */ 3815 uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 3816 value is greater than the value 3817 in the PCI_PKTS_SENT_INT_LEV1 register. */ 3818 uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3819 value is greater than the value 3820 in the PCI_PKTS_SENT_INT_LEV0 register. */ 3821 uint64_t rsl_int : 1; /**< This bit is set when the RSL Chain has 3822 generated an interrupt. */ 3823 uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3824 uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3825 uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3826 uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3827 uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3828 uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected */ 3829 uint64_t msc_msg : 1; /**< Master Split Completion Message Detected */ 3830 uint64_t msi_mabt : 1; /**< PCI MSI Master Abort. */ 3831 uint64_t msi_tabt : 1; /**< PCI MSI Target Abort. */ 3832 uint64_t msi_per : 1; /**< PCI MSI Parity Error. */ 3833 uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Read. */ 3834 uint64_t mr_abt : 1; /**< PCI Master Abort On Read. */ 3835 uint64_t tr_abt : 1; /**< PCI Target Abort On Read. */ 3836 uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on write. */ 3837 uint64_t mr_wabt : 1; /**< PCI Master Abort detected on write. */ 3838 uint64_t tr_wabt : 1; /**< PCI Target Abort detected on write. */ 3839#else 3840 uint64_t tr_wabt : 1; 3841 uint64_t mr_wabt : 1; 3842 uint64_t mr_wtto : 1; 3843 uint64_t tr_abt : 1; 3844 uint64_t mr_abt : 1; 3845 uint64_t mr_tto : 1; 3846 uint64_t msi_per : 1; 3847 uint64_t msi_tabt : 1; 3848 uint64_t msi_mabt : 1; 3849 uint64_t msc_msg : 1; 3850 uint64_t tsr_abt : 1; 3851 uint64_t serr : 1; 3852 uint64_t aperr : 1; 3853 uint64_t dperr : 1; 3854 uint64_t ill_rwr : 1; 3855 uint64_t ill_rrd : 1; 3856 uint64_t rsl_int : 1; 3857 uint64_t pcnt0 : 1; 3858 uint64_t pcnt1 : 1; 3859 uint64_t pcnt2 : 1; 3860 uint64_t pcnt3 : 1; 3861 uint64_t ptime0 : 1; 3862 uint64_t ptime1 : 1; 3863 uint64_t ptime2 : 1; 3864 uint64_t ptime3 : 1; 3865 uint64_t dcnt0 : 1; 3866 uint64_t dcnt1 : 1; 3867 uint64_t dtime0 : 1; 3868 uint64_t dtime1 : 1; 3869 uint64_t dma0_fi : 1; 3870 uint64_t dma1_fi : 1; 3871 uint64_t win_wr : 1; 3872 uint64_t ill_wr : 1; 3873 uint64_t ill_rd : 1; 3874 uint64_t reserved_34_63 : 30; 3875#endif 3876 } s; 3877 struct cvmx_pci_int_sum2_cn30xx 3878 { 3879#if __BYTE_ORDER == __BIG_ENDIAN 3880 uint64_t reserved_34_63 : 30; 3881 uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3882 when the mem area is disabled. */ 3883 uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3884 when the mem area is disabled. */ 3885 uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3886 Read-Address Register took place. */ 3887 uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3888 required to set the FORCE-INT bit for counter 1. */ 3889 uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3890 required to set the FORCE-INT bit for counter 0. */ 3891 uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3892 register is not 0 the DMA_CNT1 timer counts. 3893 When the DMA1_CNT timer has a value greater 3894 than the PCI_DMA_TIME1 register this 3895 bit is set. The timer is reset when bit is 3896 written with a one. */ 3897 uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3898 register is not 0 the DMA_CNT0 timer counts. 3899 When the DMA0_CNT timer has a value greater 3900 than the PCI_DMA_TIME0 register this 3901 bit is set. The timer is reset when bit is 3902 written with a one. */ 3903 uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3904 value is greater than the value 3905 in the PCI_DMA_INT_LEV1 register. */ 3906 uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3907 value is greater than the value 3908 in the PCI_DMA_INT_LEV0 register. */ 3909 uint64_t reserved_22_24 : 3; 3910 uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3911 register is not 0 the Sent-0 timer counts. 3912 When the Sent-0 timer has a value greater 3913 than the PCI_PKTS_SENT_TIME0 register this 3914 bit is set. The timer is reset when bit is 3915 written with a one. */ 3916 uint64_t reserved_18_20 : 3; 3917 uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3918 value is greater than the value 3919 in the PCI_PKTS_SENT_INT_LEV0 register. */ 3920 uint64_t rsl_int : 1; /**< This bit is set when the RSL Chain has 3921 generated an interrupt. */ 3922 uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3923 uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3924 uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3925 uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3926 uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3927 uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected */ 3928 uint64_t msc_msg : 1; /**< Master Split Completion Message Detected */ 3929 uint64_t msi_mabt : 1; /**< PCI MSI Master Abort. */ 3930 uint64_t msi_tabt : 1; /**< PCI MSI Target Abort. */ 3931 uint64_t msi_per : 1; /**< PCI MSI Parity Error. */ 3932 uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Read. */ 3933 uint64_t mr_abt : 1; /**< PCI Master Abort On Read. */ 3934 uint64_t tr_abt : 1; /**< PCI Target Abort On Read. */ 3935 uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on write. */ 3936 uint64_t mr_wabt : 1; /**< PCI Master Abort detected on write. */ 3937 uint64_t tr_wabt : 1; /**< PCI Target Abort detected on write. */ 3938#else 3939 uint64_t tr_wabt : 1; 3940 uint64_t mr_wabt : 1; 3941 uint64_t mr_wtto : 1; 3942 uint64_t tr_abt : 1; 3943 uint64_t mr_abt : 1; 3944 uint64_t mr_tto : 1; 3945 uint64_t msi_per : 1; 3946 uint64_t msi_tabt : 1; 3947 uint64_t msi_mabt : 1; 3948 uint64_t msc_msg : 1; 3949 uint64_t tsr_abt : 1; 3950 uint64_t serr : 1; 3951 uint64_t aperr : 1; 3952 uint64_t dperr : 1; 3953 uint64_t ill_rwr : 1; 3954 uint64_t ill_rrd : 1; 3955 uint64_t rsl_int : 1; 3956 uint64_t pcnt0 : 1; 3957 uint64_t reserved_18_20 : 3; 3958 uint64_t ptime0 : 1; 3959 uint64_t reserved_22_24 : 3; 3960 uint64_t dcnt0 : 1; 3961 uint64_t dcnt1 : 1; 3962 uint64_t dtime0 : 1; 3963 uint64_t dtime1 : 1; 3964 uint64_t dma0_fi : 1; 3965 uint64_t dma1_fi : 1; 3966 uint64_t win_wr : 1; 3967 uint64_t ill_wr : 1; 3968 uint64_t ill_rd : 1; 3969 uint64_t reserved_34_63 : 30; 3970#endif 3971 } cn30xx; 3972 struct cvmx_pci_int_sum2_cn31xx 3973 { 3974#if __BYTE_ORDER == __BIG_ENDIAN 3975 uint64_t reserved_34_63 : 30; 3976 uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3977 when the mem area is disabled. */ 3978 uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3979 when the mem area is disabled. */ 3980 uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3981 Read-Address Register took place. */ 3982 uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3983 required to set the FORCE-INT bit for counter 1. */ 3984 uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3985 required to set the FORCE-INT bit for counter 0. */ 3986 uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3987 register is not 0 the DMA_CNT1 timer counts. 3988 When the DMA1_CNT timer has a value greater 3989 than the PCI_DMA_TIME1 register this 3990 bit is set. The timer is reset when bit is 3991 written with a one. */ 3992 uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3993 register is not 0 the DMA_CNT0 timer counts. 3994 When the DMA0_CNT timer has a value greater 3995 than the PCI_DMA_TIME0 register this 3996 bit is set. The timer is reset when bit is 3997 written with a one. */ 3998 uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3999 value is greater than the value 4000 in the PCI_DMA_INT_LEV1 register. */ 4001 uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 4002 value is greater than the value 4003 in the PCI_DMA_INT_LEV0 register. */ 4004 uint64_t reserved_23_24 : 2; 4005 uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 4006 register is not 0 the Sent-1 timer counts. 4007 When the Sent-1 timer has a value greater 4008 than the PCI_PKTS_SENT_TIME1 register this 4009 bit is set. The timer is reset when bit is 4010 written with a one. */ 4011 uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 4012 register is not 0 the Sent-0 timer counts. 4013 When the Sent-0 timer has a value greater 4014 than the PCI_PKTS_SENT_TIME0 register this 4015 bit is set. The timer is reset when bit is 4016 written with a one. */ 4017 uint64_t reserved_19_20 : 2; 4018 uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 4019 value is greater than the value 4020 in the PCI_PKTS_SENT_INT_LEV1 register. */ 4021 uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 4022 value is greater than the value 4023 in the PCI_PKTS_SENT_INT_LEV0 register. */ 4024 uint64_t rsl_int : 1; /**< This bit is set when the RSL Chain has 4025 generated an interrupt. */ 4026 uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 4027 uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 4028 uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 4029 uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 4030 uint64_t serr : 1; /**< SERR# detected by PCX Core */ 4031 uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected */ 4032 uint64_t msc_msg : 1; /**< Master Split Completion Message Detected */ 4033 uint64_t msi_mabt : 1; /**< PCI MSI Master Abort. */ 4034 uint64_t msi_tabt : 1; /**< PCI MSI Target Abort. */ 4035 uint64_t msi_per : 1; /**< PCI MSI Parity Error. */ 4036 uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Read. */ 4037 uint64_t mr_abt : 1; /**< PCI Master Abort On Read. */ 4038 uint64_t tr_abt : 1; /**< PCI Target Abort On Read. */ 4039 uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on write. */ 4040 uint64_t mr_wabt : 1; /**< PCI Master Abort detected on write. */ 4041 uint64_t tr_wabt : 1; /**< PCI Target Abort detected on write. */ 4042#else 4043 uint64_t tr_wabt : 1; 4044 uint64_t mr_wabt : 1; 4045 uint64_t mr_wtto : 1; 4046 uint64_t tr_abt : 1; 4047 uint64_t mr_abt : 1; 4048 uint64_t mr_tto : 1; 4049 uint64_t msi_per : 1; 4050 uint64_t msi_tabt : 1; 4051 uint64_t msi_mabt : 1; 4052 uint64_t msc_msg : 1; 4053 uint64_t tsr_abt : 1; 4054 uint64_t serr : 1; 4055 uint64_t aperr : 1; 4056 uint64_t dperr : 1; 4057 uint64_t ill_rwr : 1; 4058 uint64_t ill_rrd : 1; 4059 uint64_t rsl_int : 1; 4060 uint64_t pcnt0 : 1; 4061 uint64_t pcnt1 : 1; 4062 uint64_t reserved_19_20 : 2; 4063 uint64_t ptime0 : 1; 4064 uint64_t ptime1 : 1; 4065 uint64_t reserved_23_24 : 2; 4066 uint64_t dcnt0 : 1; 4067 uint64_t dcnt1 : 1; 4068 uint64_t dtime0 : 1; 4069 uint64_t dtime1 : 1; 4070 uint64_t dma0_fi : 1; 4071 uint64_t dma1_fi : 1; 4072 uint64_t win_wr : 1; 4073 uint64_t ill_wr : 1; 4074 uint64_t ill_rd : 1; 4075 uint64_t reserved_34_63 : 30; 4076#endif 4077 } cn31xx; 4078 struct cvmx_pci_int_sum2_s cn38xx; 4079 struct cvmx_pci_int_sum2_s cn38xxp2; 4080 struct cvmx_pci_int_sum2_cn31xx cn50xx; 4081 struct cvmx_pci_int_sum2_s cn58xx; 4082 struct cvmx_pci_int_sum2_s cn58xxp1; 4083}; 4084typedef union cvmx_pci_int_sum2 cvmx_pci_int_sum2_t; 4085 4086/** 4087 * cvmx_pci_msi_rcv 4088 * 4089 * PCI_MSI_RCV = PCI's MSI Received Vector Register 4090 * 4091 * A bit is set in this register relative to the vector received during a MSI. The value in this 4092 * register is acted upon when the least-significant-byte of this register is written. 4093 */ 4094union cvmx_pci_msi_rcv 4095{ 4096 uint32_t u32; 4097 struct cvmx_pci_msi_rcv_s 4098 { 4099#if __BYTE_ORDER == __BIG_ENDIAN 4100 uint32_t reserved_6_31 : 26; 4101 uint32_t intr : 6; /**< When an MSI is received on the PCI the bit selected 4102 by data [5:0] will be set in this register. To 4103 clear this bit a write must take place to the 4104 NPI_MSI_RCV register where any bit set to 1 is 4105 cleared. Reading this address will return an 4106 unpredicatable value. */ 4107#else 4108 uint32_t intr : 6; 4109 uint32_t reserved_6_31 : 26; 4110#endif 4111 } s; 4112 struct cvmx_pci_msi_rcv_s cn30xx; 4113 struct cvmx_pci_msi_rcv_s cn31xx; 4114 struct cvmx_pci_msi_rcv_s cn38xx; 4115 struct cvmx_pci_msi_rcv_s cn38xxp2; 4116 struct cvmx_pci_msi_rcv_s cn50xx; 4117 struct cvmx_pci_msi_rcv_s cn58xx; 4118 struct cvmx_pci_msi_rcv_s cn58xxp1; 4119}; 4120typedef union cvmx_pci_msi_rcv cvmx_pci_msi_rcv_t; 4121 4122/** 4123 * cvmx_pci_pkt_credits# 4124 * 4125 * PCI_PKT_CREDITS0 = PCI Packet Credits For Output 0 4126 * 4127 * Used to decrease the number of packets to be processed by the host from Output-0 and return 4128 * buffer/info pointer pairs to OCTEON Output-0. The value in this register is acted upon when the 4129 * least-significant-byte of this register is written. 4130 */ 4131union cvmx_pci_pkt_creditsx 4132{ 4133 uint32_t u32; 4134 struct cvmx_pci_pkt_creditsx_s 4135 { 4136#if __BYTE_ORDER == __BIG_ENDIAN 4137 uint32_t pkt_cnt : 16; /**< The value written to this field will be 4138 subtracted from PCI_PKTS_SENT0[PKT_CNT]. */ 4139 uint32_t ptr_cnt : 16; /**< This field value is added to the 4140 NPI's internal Buffer/Info Pointer Pair count. */ 4141#else 4142 uint32_t ptr_cnt : 16; 4143 uint32_t pkt_cnt : 16; 4144#endif 4145 } s; 4146 struct cvmx_pci_pkt_creditsx_s cn30xx; 4147 struct cvmx_pci_pkt_creditsx_s cn31xx; 4148 struct cvmx_pci_pkt_creditsx_s cn38xx; 4149 struct cvmx_pci_pkt_creditsx_s cn38xxp2; 4150 struct cvmx_pci_pkt_creditsx_s cn50xx; 4151 struct cvmx_pci_pkt_creditsx_s cn58xx; 4152 struct cvmx_pci_pkt_creditsx_s cn58xxp1; 4153}; 4154typedef union cvmx_pci_pkt_creditsx cvmx_pci_pkt_creditsx_t; 4155 4156/** 4157 * cvmx_pci_pkts_sent# 4158 * 4159 * PCI_PKTS_SENT0 = PCI Packets Sent 0 4160 * 4161 * Number of packets sent to the host memory from PCI Output 0 4162 */ 4163union cvmx_pci_pkts_sentx 4164{ 4165 uint32_t u32; 4166 struct cvmx_pci_pkts_sentx_s 4167 { 4168#if __BYTE_ORDER == __BIG_ENDIAN 4169 uint32_t pkt_cnt : 32; /**< Each time a packet is written to the memory via 4170 PCI from PCI Output 0, this counter is 4171 incremented by 1 or the byte count of the packet 4172 as set in NPI_OUTPUT_CONTROL[P0_BMODE]. */ 4173#else 4174 uint32_t pkt_cnt : 32; 4175#endif 4176 } s; 4177 struct cvmx_pci_pkts_sentx_s cn30xx; 4178 struct cvmx_pci_pkts_sentx_s cn31xx; 4179 struct cvmx_pci_pkts_sentx_s cn38xx; 4180 struct cvmx_pci_pkts_sentx_s cn38xxp2; 4181 struct cvmx_pci_pkts_sentx_s cn50xx; 4182 struct cvmx_pci_pkts_sentx_s cn58xx; 4183 struct cvmx_pci_pkts_sentx_s cn58xxp1; 4184}; 4185typedef union cvmx_pci_pkts_sentx cvmx_pci_pkts_sentx_t; 4186 4187/** 4188 * cvmx_pci_pkts_sent_int_lev# 4189 * 4190 * PCI_PKTS_SENT_INT_LEV0 = PCI Packets Sent Interrupt Level For Output 0 4191 * 4192 * Interrupt when number of packets sent is equal to or greater than the register value. 4193 */ 4194union cvmx_pci_pkts_sent_int_levx 4195{ 4196 uint32_t u32; 4197 struct cvmx_pci_pkts_sent_int_levx_s 4198 { 4199#if __BYTE_ORDER == __BIG_ENDIAN 4200 uint32_t pkt_cnt : 32; /**< When corresponding port's PCI_PKTS_SENT0 value 4201 exceeds the value in this register, PCNT0 of the 4202 PCI_INT_SUM and PCI_INT_SUM2 will be set. */ 4203#else 4204 uint32_t pkt_cnt : 32; 4205#endif 4206 } s; 4207 struct cvmx_pci_pkts_sent_int_levx_s cn30xx; 4208 struct cvmx_pci_pkts_sent_int_levx_s cn31xx; 4209 struct cvmx_pci_pkts_sent_int_levx_s cn38xx; 4210 struct cvmx_pci_pkts_sent_int_levx_s cn38xxp2; 4211 struct cvmx_pci_pkts_sent_int_levx_s cn50xx; 4212 struct cvmx_pci_pkts_sent_int_levx_s cn58xx; 4213 struct cvmx_pci_pkts_sent_int_levx_s cn58xxp1; 4214}; 4215typedef union cvmx_pci_pkts_sent_int_levx cvmx_pci_pkts_sent_int_levx_t; 4216 4217/** 4218 * cvmx_pci_pkts_sent_time# 4219 * 4220 * PCI_PKTS_SENT_TIME0 = PCI Packets Sent Timer For Output-0 4221 * 4222 * Time to wait from packet being sent to host from Output-0 before issuing an interrupt. 4223 */ 4224union cvmx_pci_pkts_sent_timex 4225{ 4226 uint32_t u32; 4227 struct cvmx_pci_pkts_sent_timex_s 4228 { 4229#if __BYTE_ORDER == __BIG_ENDIAN 4230 uint32_t pkt_time : 32; /**< Number of PCI clock cycle to wait before 4231 issuing an interrupt to the host when a 4232 packet from this port has been sent to the 4233 host. The timer is reset when the 4234 PCI_INT_SUM[21] register is cleared. */ 4235#else 4236 uint32_t pkt_time : 32; 4237#endif 4238 } s; 4239 struct cvmx_pci_pkts_sent_timex_s cn30xx; 4240 struct cvmx_pci_pkts_sent_timex_s cn31xx; 4241 struct cvmx_pci_pkts_sent_timex_s cn38xx; 4242 struct cvmx_pci_pkts_sent_timex_s cn38xxp2; 4243 struct cvmx_pci_pkts_sent_timex_s cn50xx; 4244 struct cvmx_pci_pkts_sent_timex_s cn58xx; 4245 struct cvmx_pci_pkts_sent_timex_s cn58xxp1; 4246}; 4247typedef union cvmx_pci_pkts_sent_timex cvmx_pci_pkts_sent_timex_t; 4248 4249/** 4250 * cvmx_pci_read_cmd_6 4251 * 4252 * PCI_READ_CMD_6 = PCI Read Command 6 Register 4253 * 4254 * Contains control inforamtion related to a received PCI Command 6. 4255 */ 4256union cvmx_pci_read_cmd_6 4257{ 4258 uint32_t u32; 4259 struct cvmx_pci_read_cmd_6_s 4260 { 4261#if __BYTE_ORDER == __BIG_ENDIAN 4262 uint32_t reserved_9_31 : 23; 4263 uint32_t min_data : 6; /**< The number of words to have buffered in the PNI 4264 before informing the PCIX-Core that we have 4265 read data available for the outstanding Delayed 4266 read. 0 is treated as a 64. 4267 For reads to the expansion this value is not used. */ 4268 uint32_t prefetch : 3; /**< Control the amount of data to be preteched when 4269 this type of bhmstREAD command is received. 4270 0 = 1 32/64 bit word. 4271 1 = From address to end of 128B block. 4272 2 = From address to end of 128B block plus 128B. 4273 3 = From address to end of 128B block plus 256B. 4274 4 = From address to end of 128B block plus 384B. 4275 For reads to the expansion this value is not used. */ 4276#else 4277 uint32_t prefetch : 3; 4278 uint32_t min_data : 6; 4279 uint32_t reserved_9_31 : 23; 4280#endif 4281 } s; 4282 struct cvmx_pci_read_cmd_6_s cn30xx; 4283 struct cvmx_pci_read_cmd_6_s cn31xx; 4284 struct cvmx_pci_read_cmd_6_s cn38xx; 4285 struct cvmx_pci_read_cmd_6_s cn38xxp2; 4286 struct cvmx_pci_read_cmd_6_s cn50xx; 4287 struct cvmx_pci_read_cmd_6_s cn58xx; 4288 struct cvmx_pci_read_cmd_6_s cn58xxp1; 4289}; 4290typedef union cvmx_pci_read_cmd_6 cvmx_pci_read_cmd_6_t; 4291 4292/** 4293 * cvmx_pci_read_cmd_c 4294 * 4295 * PCI_READ_CMD_C = PCI Read Command C Register 4296 * 4297 * Contains control inforamtion related to a received PCI Command C. 4298 */ 4299union cvmx_pci_read_cmd_c 4300{ 4301 uint32_t u32; 4302 struct cvmx_pci_read_cmd_c_s 4303 { 4304#if __BYTE_ORDER == __BIG_ENDIAN 4305 uint32_t reserved_9_31 : 23; 4306 uint32_t min_data : 6; /**< The number of words to have buffered in the PNI 4307 before informing the PCIX-Core that we have 4308 read data available for the outstanding Delayed 4309 read. 0 is treated as a 64. 4310 For reads to the expansion this value is not used. */ 4311 uint32_t prefetch : 3; /**< Control the amount of data to be preteched when 4312 this type of READ command is received. 4313 0 = 1 32/64 bit word. 4314 1 = From address to end of 128B block. 4315 2 = From address to end of 128B block plus 128B. 4316 3 = From address to end of 128B block plus 256B. 4317 4 = From address to end of 128B block plus 384B. 4318 For reads to the expansion this value is not used. */ 4319#else 4320 uint32_t prefetch : 3; 4321 uint32_t min_data : 6; 4322 uint32_t reserved_9_31 : 23; 4323#endif 4324 } s; 4325 struct cvmx_pci_read_cmd_c_s cn30xx; 4326 struct cvmx_pci_read_cmd_c_s cn31xx; 4327 struct cvmx_pci_read_cmd_c_s cn38xx; 4328 struct cvmx_pci_read_cmd_c_s cn38xxp2; 4329 struct cvmx_pci_read_cmd_c_s cn50xx; 4330 struct cvmx_pci_read_cmd_c_s cn58xx; 4331 struct cvmx_pci_read_cmd_c_s cn58xxp1; 4332}; 4333typedef union cvmx_pci_read_cmd_c cvmx_pci_read_cmd_c_t; 4334 4335/** 4336 * cvmx_pci_read_cmd_e 4337 * 4338 * PCI_READ_CMD_E = PCI Read Command E Register 4339 * 4340 * Contains control inforamtion related to a received PCI Command 6. 4341 */ 4342union cvmx_pci_read_cmd_e 4343{ 4344 uint32_t u32; 4345 struct cvmx_pci_read_cmd_e_s 4346 { 4347#if __BYTE_ORDER == __BIG_ENDIAN 4348 uint32_t reserved_9_31 : 23; 4349 uint32_t min_data : 6; /**< The number of words to have buffered in the PNI 4350 before informaing the PCIX-Core that we have 4351 read data available for the outstanding Delayed 4352 read. 0 is treated as a 64. 4353 For reads to the expansion this value is not used. */ 4354 uint32_t prefetch : 3; /**< Control the amount of data to be preteched when 4355 this type of READ command is received. 4356 0 = 1 32/64 bit word. 4357 1 = From address to end of 128B block. 4358 2 = From address to end of 128B block plus 128B. 4359 3 = From address to end of 128B block plus 256B. 4360 4 = From address to end of 128B block plus 384B. 4361 For reads to the expansion this value is not used. */ 4362#else 4363 uint32_t prefetch : 3; 4364 uint32_t min_data : 6; 4365 uint32_t reserved_9_31 : 23; 4366#endif 4367 } s; 4368 struct cvmx_pci_read_cmd_e_s cn30xx; 4369 struct cvmx_pci_read_cmd_e_s cn31xx; 4370 struct cvmx_pci_read_cmd_e_s cn38xx; 4371 struct cvmx_pci_read_cmd_e_s cn38xxp2; 4372 struct cvmx_pci_read_cmd_e_s cn50xx; 4373 struct cvmx_pci_read_cmd_e_s cn58xx; 4374 struct cvmx_pci_read_cmd_e_s cn58xxp1; 4375}; 4376typedef union cvmx_pci_read_cmd_e cvmx_pci_read_cmd_e_t; 4377 4378/** 4379 * cvmx_pci_read_timeout 4380 * 4381 * PCI_READ_TIMEOUT = PCI Read Timeour Register 4382 * 4383 * The address to start reading Instructions from for Input-3. 4384 */ 4385union cvmx_pci_read_timeout 4386{ 4387 uint64_t u64; 4388 struct cvmx_pci_read_timeout_s 4389 { 4390#if __BYTE_ORDER == __BIG_ENDIAN 4391 uint64_t reserved_32_63 : 32; 4392 uint64_t enb : 1; /**< Enable the use of the Timeout function. */ 4393 uint64_t cnt : 31; /**< The number of eclk cycles to wait after issuing 4394 a read request to the PNI before setting a 4395 timeout and not expecting the data to return. 4396 This is considered a fatal condition by the NPI. */ 4397#else 4398 uint64_t cnt : 31; 4399 uint64_t enb : 1; 4400 uint64_t reserved_32_63 : 32; 4401#endif 4402 } s; 4403 struct cvmx_pci_read_timeout_s cn30xx; 4404 struct cvmx_pci_read_timeout_s cn31xx; 4405 struct cvmx_pci_read_timeout_s cn38xx; 4406 struct cvmx_pci_read_timeout_s cn38xxp2; 4407 struct cvmx_pci_read_timeout_s cn50xx; 4408 struct cvmx_pci_read_timeout_s cn58xx; 4409 struct cvmx_pci_read_timeout_s cn58xxp1; 4410}; 4411typedef union cvmx_pci_read_timeout cvmx_pci_read_timeout_t; 4412 4413/** 4414 * cvmx_pci_scm_reg 4415 * 4416 * PCI_SCM_REG = PCI Master Split Completion Message Register 4417 * 4418 * This register contains the Master Split Completion Message(SCM) generated when a master split 4419 * transaction is aborted. 4420 */ 4421union cvmx_pci_scm_reg 4422{ 4423 uint64_t u64; 4424 struct cvmx_pci_scm_reg_s 4425 { 4426#if __BYTE_ORDER == __BIG_ENDIAN 4427 uint64_t reserved_32_63 : 32; 4428 uint64_t scm : 32; /**< Contains the Split Completion Message (SCM) 4429 driven when a master-split transaction is aborted. 4430 [31:28]: Message Class 4431 [27:20]: Message Index 4432 [19]: Reserved 4433 [18:12]: Remaining Lower Address 4434 [11:8]: Upper Remaining Byte Count 4435 [7:0]: Lower Remaining Byte Count 4436 Refer to the PCIX1.0a specification, Fig 2-40 4437 for additional details for the split completion 4438 message format. */ 4439#else 4440 uint64_t scm : 32; 4441 uint64_t reserved_32_63 : 32; 4442#endif 4443 } s; 4444 struct cvmx_pci_scm_reg_s cn30xx; 4445 struct cvmx_pci_scm_reg_s cn31xx; 4446 struct cvmx_pci_scm_reg_s cn38xx; 4447 struct cvmx_pci_scm_reg_s cn38xxp2; 4448 struct cvmx_pci_scm_reg_s cn50xx; 4449 struct cvmx_pci_scm_reg_s cn58xx; 4450 struct cvmx_pci_scm_reg_s cn58xxp1; 4451}; 4452typedef union cvmx_pci_scm_reg cvmx_pci_scm_reg_t; 4453 4454/** 4455 * cvmx_pci_tsr_reg 4456 * 4457 * PCI_TSR_REG = PCI Target Split Attribute Register 4458 * 4459 * This register contains the Attribute field Master Split Completion Message(SCM) generated when a master split 4460 * transaction is aborted. 4461 */ 4462union cvmx_pci_tsr_reg 4463{ 4464 uint64_t u64; 4465 struct cvmx_pci_tsr_reg_s 4466 { 4467#if __BYTE_ORDER == __BIG_ENDIAN 4468 uint64_t reserved_36_63 : 28; 4469 uint64_t tsr : 36; /**< Contains the Target Split Attribute field when a 4470 target-split transaction is aborted. 4471 [35:32]: Upper Byte Count 4472 [31]: BCM=Byte Count Modified 4473 [30]: SCE=Split Completion Error 4474 [29]: SCM=Split Completion Message 4475 [28:24]: RESERVED 4476 [23:16]: Completer Bus Number 4477 [15:11]: Completer Device Number 4478 [10:8]: Completer Function Number 4479 [7:0]: Lower Byte Count 4480 Refer to the PCIX1.0a specification, Fig 2-39 4481 for additional details on the completer attribute 4482 bit assignments. */ 4483#else 4484 uint64_t tsr : 36; 4485 uint64_t reserved_36_63 : 28; 4486#endif 4487 } s; 4488 struct cvmx_pci_tsr_reg_s cn30xx; 4489 struct cvmx_pci_tsr_reg_s cn31xx; 4490 struct cvmx_pci_tsr_reg_s cn38xx; 4491 struct cvmx_pci_tsr_reg_s cn38xxp2; 4492 struct cvmx_pci_tsr_reg_s cn50xx; 4493 struct cvmx_pci_tsr_reg_s cn58xx; 4494 struct cvmx_pci_tsr_reg_s cn58xxp1; 4495}; 4496typedef union cvmx_pci_tsr_reg cvmx_pci_tsr_reg_t; 4497 4498/** 4499 * cvmx_pci_win_rd_addr 4500 * 4501 * PCI_WIN_RD_ADDR = PCI Window Read Address Register 4502 * 4503 * Writing the least-significant-byte of this register will cause a read operation to take place, 4504 * UNLESS, a read operation is already taking place. A read is consider to end when the PCI_WIN_RD_DATA 4505 * register is read. 4506 */ 4507union cvmx_pci_win_rd_addr 4508{ 4509 uint64_t u64; 4510 struct cvmx_pci_win_rd_addr_s 4511 { 4512#if __BYTE_ORDER == __BIG_ENDIAN 4513 uint64_t reserved_49_63 : 15; 4514 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4515 read as '0'. */ 4516 uint64_t reserved_0_47 : 48; 4517#else 4518 uint64_t reserved_0_47 : 48; 4519 uint64_t iobit : 1; 4520 uint64_t reserved_49_63 : 15; 4521#endif 4522 } s; 4523 struct cvmx_pci_win_rd_addr_cn30xx 4524 { 4525#if __BYTE_ORDER == __BIG_ENDIAN 4526 uint64_t reserved_49_63 : 15; 4527 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4528 read as '0'. */ 4529 uint64_t rd_addr : 46; /**< The address to be read from. Whenever the LSB of 4530 this register is written, the Read Operation will 4531 take place. 4532 [47:40] = NCB_ID 4533 [39:3] = Address 4534 When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 4535 [39:32] == x, Not Used 4536 [31:27] == RSL_ID 4537 [12:2] == RSL Register Offset 4538 [1:0] == x, Not Used */ 4539 uint64_t reserved_0_1 : 2; 4540#else 4541 uint64_t reserved_0_1 : 2; 4542 uint64_t rd_addr : 46; 4543 uint64_t iobit : 1; 4544 uint64_t reserved_49_63 : 15; 4545#endif 4546 } cn30xx; 4547 struct cvmx_pci_win_rd_addr_cn30xx cn31xx; 4548 struct cvmx_pci_win_rd_addr_cn38xx 4549 { 4550#if __BYTE_ORDER == __BIG_ENDIAN 4551 uint64_t reserved_49_63 : 15; 4552 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4553 read as '0'. */ 4554 uint64_t rd_addr : 45; /**< The address to be read from. Whenever the LSB of 4555 this register is written, the Read Operation will 4556 take place. 4557 [47:40] = NCB_ID 4558 [39:3] = Address 4559 When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 4560 [39:32] == x, Not Used 4561 [31:27] == RSL_ID 4562 [12:3] == RSL Register Offset 4563 [2:0] == x, Not Used */ 4564 uint64_t reserved_0_2 : 3; 4565#else 4566 uint64_t reserved_0_2 : 3; 4567 uint64_t rd_addr : 45; 4568 uint64_t iobit : 1; 4569 uint64_t reserved_49_63 : 15; 4570#endif 4571 } cn38xx; 4572 struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2; 4573 struct cvmx_pci_win_rd_addr_cn30xx cn50xx; 4574 struct cvmx_pci_win_rd_addr_cn38xx cn58xx; 4575 struct cvmx_pci_win_rd_addr_cn38xx cn58xxp1; 4576}; 4577typedef union cvmx_pci_win_rd_addr cvmx_pci_win_rd_addr_t; 4578 4579/** 4580 * cvmx_pci_win_rd_data 4581 * 4582 * PCI_WIN_RD_DATA = PCI Window Read Data Register 4583 * 4584 * Contains the result from the read operation that took place when the LSB of the PCI_WIN_RD_ADDR 4585 * register was written. 4586 */ 4587union cvmx_pci_win_rd_data 4588{ 4589 uint64_t u64; 4590 struct cvmx_pci_win_rd_data_s 4591 { 4592#if __BYTE_ORDER == __BIG_ENDIAN 4593 uint64_t rd_data : 64; /**< The read data. */ 4594#else 4595 uint64_t rd_data : 64; 4596#endif 4597 } s; 4598 struct cvmx_pci_win_rd_data_s cn30xx; 4599 struct cvmx_pci_win_rd_data_s cn31xx; 4600 struct cvmx_pci_win_rd_data_s cn38xx; 4601 struct cvmx_pci_win_rd_data_s cn38xxp2; 4602 struct cvmx_pci_win_rd_data_s cn50xx; 4603 struct cvmx_pci_win_rd_data_s cn58xx; 4604 struct cvmx_pci_win_rd_data_s cn58xxp1; 4605}; 4606typedef union cvmx_pci_win_rd_data cvmx_pci_win_rd_data_t; 4607 4608/** 4609 * cvmx_pci_win_wr_addr 4610 * 4611 * PCI_WIN_WR_ADDR = PCI Window Write Address Register 4612 * 4613 * Contains the address to be writen to when a write operation is started by writing the 4614 * PCI_WIN_WR_DATA register (see below). 4615 */ 4616union cvmx_pci_win_wr_addr 4617{ 4618 uint64_t u64; 4619 struct cvmx_pci_win_wr_addr_s 4620 { 4621#if __BYTE_ORDER == __BIG_ENDIAN 4622 uint64_t reserved_49_63 : 15; 4623 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4624 read as '0'. */ 4625 uint64_t wr_addr : 45; /**< The address that will be written to when the 4626 PCI_WIN_WR_DATA register is written. 4627 [47:40] = NCB_ID 4628 [39:3] = Address 4629 When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 4630 [39:32] == x, Not Used 4631 [31:27] == RSL_ID 4632 [12:3] == RSL Register Offset 4633 [2:0] == x, Not Used */ 4634 uint64_t reserved_0_2 : 3; 4635#else 4636 uint64_t reserved_0_2 : 3; 4637 uint64_t wr_addr : 45; 4638 uint64_t iobit : 1; 4639 uint64_t reserved_49_63 : 15; 4640#endif 4641 } s; 4642 struct cvmx_pci_win_wr_addr_s cn30xx; 4643 struct cvmx_pci_win_wr_addr_s cn31xx; 4644 struct cvmx_pci_win_wr_addr_s cn38xx; 4645 struct cvmx_pci_win_wr_addr_s cn38xxp2; 4646 struct cvmx_pci_win_wr_addr_s cn50xx; 4647 struct cvmx_pci_win_wr_addr_s cn58xx; 4648 struct cvmx_pci_win_wr_addr_s cn58xxp1; 4649}; 4650typedef union cvmx_pci_win_wr_addr cvmx_pci_win_wr_addr_t; 4651 4652/** 4653 * cvmx_pci_win_wr_data 4654 * 4655 * PCI_WIN_WR_DATA = PCI Window Write Data Register 4656 * 4657 * Contains the data to write to the address located in the PCI_WIN_WR_ADDR Register. 4658 * Writing the least-significant-byte of this register will cause a write operation to take place. 4659 */ 4660union cvmx_pci_win_wr_data 4661{ 4662 uint64_t u64; 4663 struct cvmx_pci_win_wr_data_s 4664 { 4665#if __BYTE_ORDER == __BIG_ENDIAN 4666 uint64_t wr_data : 64; /**< The data to be written. Whenever the LSB of this 4667 register is written, the Window Write will take 4668 place. */ 4669#else 4670 uint64_t wr_data : 64; 4671#endif 4672 } s; 4673 struct cvmx_pci_win_wr_data_s cn30xx; 4674 struct cvmx_pci_win_wr_data_s cn31xx; 4675 struct cvmx_pci_win_wr_data_s cn38xx; 4676 struct cvmx_pci_win_wr_data_s cn38xxp2; 4677 struct cvmx_pci_win_wr_data_s cn50xx; 4678 struct cvmx_pci_win_wr_data_s cn58xx; 4679 struct cvmx_pci_win_wr_data_s cn58xxp1; 4680}; 4681typedef union cvmx_pci_win_wr_data cvmx_pci_win_wr_data_t; 4682 4683/** 4684 * cvmx_pci_win_wr_mask 4685 * 4686 * PCI_WIN_WR_MASK = PCI Window Write Mask Register 4687 * 4688 * Contains the mask for the data in the PCI_WIN_WR_DATA Register. 4689 */ 4690union cvmx_pci_win_wr_mask 4691{ 4692 uint64_t u64; 4693 struct cvmx_pci_win_wr_mask_s 4694 { 4695#if __BYTE_ORDER == __BIG_ENDIAN 4696 uint64_t reserved_8_63 : 56; 4697 uint64_t wr_mask : 8; /**< The data to be written. When a bit is set '1' 4698 the corresponding byte will not be written. */ 4699#else 4700 uint64_t wr_mask : 8; 4701 uint64_t reserved_8_63 : 56; 4702#endif 4703 } s; 4704 struct cvmx_pci_win_wr_mask_s cn30xx; 4705 struct cvmx_pci_win_wr_mask_s cn31xx; 4706 struct cvmx_pci_win_wr_mask_s cn38xx; 4707 struct cvmx_pci_win_wr_mask_s cn38xxp2; 4708 struct cvmx_pci_win_wr_mask_s cn50xx; 4709 struct cvmx_pci_win_wr_mask_s cn58xx; 4710 struct cvmx_pci_win_wr_mask_s cn58xxp1; 4711}; 4712typedef union cvmx_pci_win_wr_mask cvmx_pci_win_wr_mask_t; 4713 4714#endif 4715