1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * This is file defines ASM primitives for the executive. 50 51 * <hr>$Revision: 52004 $<hr> 52 * 53 * 54 */ 55#ifndef __CVMX_ASM_H__ 56#define __CVMX_ASM_H__ 57 58#define COP0_INDEX $0,0 /* TLB read/write index */ 59#define COP0_RANDOM $1,0 /* TLB random index */ 60#define COP0_ENTRYLO0 $2,0 /* TLB entryLo0 */ 61#define COP0_ENTRYLO1 $3,0 /* TLB entryLo1 */ 62#define COP0_CONTEXT $4,0 /* Context */ 63#define COP0_PAGEMASK $5,0 /* TLB pagemask */ 64#define COP0_PAGEGRAIN $5,1 /* TLB config for max page sizes */ 65#define COP0_WIRED $6,0 /* TLB number of wired entries */ 66#define COP0_HWRENA $7,0 /* rdhw instruction enable per register */ 67#define COP0_BADVADDR $8,0 /* Bad virtual address */ 68#define COP0_COUNT $9,0 /* Mips count register */ 69#define COP0_CVMCOUNT $9,6 /* Cavium count register */ 70#define COP0_CVMCTL $9,7 /* Cavium control */ 71#define COP0_ENTRYHI $10,0 /* TLB entryHi */ 72#define COP0_COMPARE $11,0 /* Mips compare register */ 73#define COP0_POWTHROTTLE $11,6 /* Power throttle register */ 74#define COP0_CVMMEMCTL $11,7 /* Cavium memory control */ 75#define COP0_STATUS $12,0 /* Mips status register */ 76#define COP0_INTCTL $12,1 /* Useless (Vectored interrupts) */ 77#define COP0_SRSCTL $12,2 /* Useless (Shadow registers) */ 78#define COP0_CAUSE $13,0 /* Mips cause register */ 79#define COP0_EPC $14,0 /* Exception program counter */ 80#define COP0_PRID $15,0 /* Processor ID */ 81#define COP0_EBASE $15,1 /* Exception base */ 82#define COP0_CONFIG $16,0 /* Misc config options */ 83#define COP0_CONFIG1 $16,1 /* Misc config options */ 84#define COP0_CONFIG2 $16,2 /* Misc config options */ 85#define COP0_CONFIG3 $16,3 /* Misc config options */ 86#define COP0_WATCHLO0 $18,0 /* Address watch registers */ 87#define COP0_WATCHLO1 $18,1 /* Address watch registers */ 88#define COP0_WATCHHI0 $19,0 /* Address watch registers */ 89#define COP0_WATCHHI1 $19,1 /* Address watch registers */ 90#define COP0_XCONTEXT $20,0 /* OS context */ 91#define COP0_MULTICOREDEBUG $22,0 /* Cavium debug */ 92#define COP0_DEBUG $23,0 /* Debug status */ 93#define COP0_DEPC $24,0 /* Debug PC */ 94#define COP0_PERFCONTROL0 $25,0 /* Performance counter control */ 95#define COP0_PERFCONTROL1 $25,2 /* Performance counter control */ 96#define COP0_PERFVALUE0 $25,1 /* Performance counter */ 97#define COP0_PERFVALUE1 $25,3 /* Performance counter */ 98#define COP0_CACHEERRI $27,0 /* I cache error status */ 99#define COP0_CACHEERRD $27,1 /* D cache error status */ 100#define COP0_TAGLOI $28,0 /* I cache tagLo */ 101#define COP0_TAGLOD $28,2 /* D cache tagLo */ 102#define COP0_DATALOI $28,1 /* I cache dataLo */ 103#define COP0_DATALOD $28,3 /* D cahce dataLo */ 104#define COP0_TAGHI $29,2 /* ? */ 105#define COP0_DATAHII $29,1 /* ? */ 106#define COP0_DATAHID $29,3 /* ? */ 107#define COP0_ERROREPC $30,0 /* Error PC */ 108#define COP0_DESAVE $31,0 /* Debug scratch area */ 109 110/* This header file can be included from a .S file. Keep non-preprocessor 111 things under !__ASSEMBLER__. */ 112#ifndef __ASSEMBLER__ 113 114#include "octeon-model.h" 115 116#ifdef __cplusplus 117extern "C" { 118#endif 119 120/* turn the variable name into a string */ 121#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x) 122#define CVMX_TMP_STR2(x) #x 123 124#if !OCTEON_IS_COMMON_BINARY() 125 #if CVMX_COMPILED_FOR(OCTEON_CN63XX) 126 #define CVMX_CAVIUM_OCTEON2 127 #endif 128#endif 129 130/* other useful stuff */ 131#define CVMX_BREAK asm volatile ("break") 132#define CVMX_SYNC asm volatile ("sync" : : :"memory") 133/* String version of SYNCW macro for using in inline asm constructs */ 134#define CVMX_SYNCW_STR_OCTEON2 "syncw\n" 135#ifdef CVMX_CAVIUM_OCTEON2 136 #define CVMX_SYNCW_STR CVMX_SYNCW_STR_OCTEON2 137#else 138 #define CVMX_SYNCW_STR "syncw\nsyncw\n" 139#endif /* CVMX_CAVIUM_OCTEON2 */ 140 141#ifdef __OCTEON__ 142 #define CVMX_SYNCIO asm volatile ("nop") /* Deprecated, will be removed in future release */ 143 #define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : :"memory") 144 #define CVMX_SYNCIOALL asm volatile ("nop") /* Deprecated, will be removed in future release */ 145 /* We actually use two syncw instructions in a row when we need a write 146 memory barrier. This is because the CN3XXX series of Octeons have 147 errata Core-401. This can cause a single syncw to not enforce 148 ordering under very rare conditions. Even if it is rare, better safe 149 than sorry */ 150 #define CVMX_SYNCW_OCTEON2 asm volatile ("syncw\n" : : :"memory") 151 #ifdef CVMX_CAVIUM_OCTEON2 152 #define CVMX_SYNCW CVMX_SYNCW_OCTEON2 153 #else 154 #define CVMX_SYNCW asm volatile ("syncw\nsyncw\n" : : :"memory") 155 #endif /* CVMX_CAVIUM_OCTEON2 */ 156#if defined(VXWORKS) || defined(__linux__) 157 /* Define new sync instructions to be normal SYNC instructions for 158 operating systems that use threads */ 159 #define CVMX_SYNCWS CVMX_SYNCW 160 #define CVMX_SYNCS CVMX_SYNC 161 #define CVMX_SYNCWS_STR CVMX_SYNCW_STR 162 #define CVMX_SYNCWS_OCTEON2 CVMX_SYNCW_OCTEON2 163 #define CVMX_SYNCWS_STR_OCTEON2 CVMX_SYNCW_STR_OCTEON2 164#else 165 #if defined(CVMX_BUILD_FOR_TOOLCHAIN) 166 /* While building simple exec toolchain, always use syncw to 167 support all Octeon models. */ 168 #define CVMX_SYNCWS CVMX_SYNCW 169 #define CVMX_SYNCS CVMX_SYNC 170 #define CVMX_SYNCWS_STR CVMX_SYNCW_STR 171 #define CVMX_SYNCWS_OCTEON2 CVMX_SYNCW_OCTEON2 172 #define CVMX_SYNCWS_STR_OCTEON2 CVMX_SYNCW_STR_OCTEON2 173 #else 174 /* Again, just like syncw, we may need two syncws instructions in a row due 175 errata Core-401. Only one syncws is required for Octeon2 models */ 176 #define CVMX_SYNCS asm volatile ("syncs" : : :"memory") 177 #define CVMX_SYNCWS_OCTEON2 asm volatile ("syncws\n" : : :"memory") 178 #define CVMX_SYNCWS_STR_OCTEON2 "syncws\n" 179 #ifdef CVMX_CAVIUM_OCTEON2 180 #define CVMX_SYNCWS CVMX_SYNCWS_OCTEON2 181 #define CVMX_SYNCWS_STR CVMX_SYNCWS_STR_OCTEON2 182 #else 183 #define CVMX_SYNCWS asm volatile ("syncws\nsyncws\n" : : :"memory") 184 #define CVMX_SYNCWS_STR "syncws\nsyncws\n" 185 #endif /* CVMX_CAVIUM_OCTEON2 */ 186 #endif 187#endif 188#else /* !__OCTEON__ */ 189 /* Not using a Cavium compiler, always use the slower sync so the assembler stays happy */ 190 #define CVMX_SYNCIO asm volatile ("nop") /* Deprecated, will be removed in future release */ 191 #define CVMX_SYNCIOBDMA asm volatile ("sync" : : :"memory") 192 #define CVMX_SYNCIOALL asm volatile ("nop") /* Deprecated, will be removed in future release */ 193 #define CVMX_SYNCW asm volatile ("sync" : : :"memory") 194 #define CVMX_SYNCWS CVMX_SYNCW 195 #define CVMX_SYNCS CVMX_SYNC 196 #define CVMX_SYNCWS_STR CVMX_SYNCW_STR 197 #define CVMX_SYNCWS_OCTEON2 CVMX_SYNCW 198 #define CVMX_SYNCWS_STR_OCTEON2 CVMX_SYNCW_STR 199#endif 200#define CVMX_SYNCI(address, offset) asm volatile ("synci " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address) ) 201#define CVMX_PREFETCH0(address) CVMX_PREFETCH(address, 0) 202#define CVMX_PREFETCH128(address) CVMX_PREFETCH(address, 128) 203// a normal prefetch 204#define CVMX_PREFETCH(address, offset) CVMX_PREFETCH_PREF0(address, offset) 205// normal prefetches that use the pref instruction 206#define CVMX_PREFETCH_PREFX(X, address, offset) asm volatile ("pref %[type], %[off](%[rbase])" : : [rbase] "d" (address), [off] "I" (offset), [type] "n" (X)) 207#define CVMX_PREFETCH_PREF0(address, offset) CVMX_PREFETCH_PREFX(0, address, offset) 208#define CVMX_PREFETCH_PREF1(address, offset) CVMX_PREFETCH_PREFX(1, address, offset) 209#define CVMX_PREFETCH_PREF6(address, offset) CVMX_PREFETCH_PREFX(6, address, offset) 210#define CVMX_PREFETCH_PREF7(address, offset) CVMX_PREFETCH_PREFX(7, address, offset) 211// prefetch into L1, do not put the block in the L2 212#define CVMX_PREFETCH_NOTL2(address, offset) CVMX_PREFETCH_PREFX(4, address, offset) 213#define CVMX_PREFETCH_NOTL22(address, offset) CVMX_PREFETCH_PREFX(5, address, offset) 214// prefetch into L2, do not put the block in the L1 215#define CVMX_PREFETCH_L2(address, offset) CVMX_PREFETCH_PREFX(28, address, offset) 216// CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable (actually old value or zero) until 217// that byte is stored to (by this or another processor. Note that the value of each byte is not only 218// unpredictable, but may also change again - up until the point when one of the cores stores to the 219// byte. 220#define CVMX_PREPARE_FOR_STORE(address, offset) CVMX_PREFETCH_PREFX(30, address, offset) 221// This is a command headed to the L2 controller to tell it to clear its dirty bit for a 222// block. Basically, SW is telling HW that the current version of the block will not be 223// used. 224#define CVMX_DONT_WRITE_BACK(address, offset) CVMX_PREFETCH_PREFX(29, address, offset) 225 226#define CVMX_ICACHE_INVALIDATE { CVMX_SYNC; asm volatile ("synci 0($0)" : : ); } // flush stores, invalidate entire icache 227#define CVMX_ICACHE_INVALIDATE2 { CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); } // flush stores, invalidate entire icache 228#define CVMX_DCACHE_INVALIDATE { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); } // complete prefetches, invalidate entire dcache 229 230#define CVMX_CACHE(op, address, offset) asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address) ) 231#define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset) // fetch and lock the state. 232#define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset) // unlock the state. 233#define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset) // invalidate the cache block and clear the USED bits for the block 234#define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset) // load virtual tag and data for the L2 cache block into L2C_TAD0_TAG register 235 236/* new instruction to make RC4 run faster */ 237#define CVMX_BADDU(result, input1, input2) asm ("baddu %[rd],%[rs],%[rt]" : [rd] "=d" (result) : [rs] "d" (input1) , [rt] "d" (input2)) 238 239// misc v2 stuff 240#define CVMX_ROTR(result, input1, shiftconst) asm ("rotr %[rd],%[rs]," CVMX_TMP_STR(shiftconst) : [rd] "=d" (result) : [rs] "d" (input1)) 241#define CVMX_ROTRV(result, input1, input2) asm ("rotrv %[rd],%[rt],%[rs]" : [rd] "=d" (result) : [rt] "d" (input1) , [rs] "d" (input2)) 242#define CVMX_DROTR(result, input1, shiftconst) asm ("drotr %[rd],%[rs]," CVMX_TMP_STR(shiftconst) : [rd] "=d" (result) : [rs] "d" (input1)) 243#define CVMX_DROTRV(result, input1, input2) asm ("drotrv %[rd],%[rt],%[rs]" : [rd] "=d" (result) : [rt] "d" (input1) , [rs] "d" (input2)) 244#define CVMX_SEB(result, input1) asm ("seb %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1)) 245#define CVMX_SEH(result, input1) asm ("seh %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1)) 246#define CVMX_DSBH(result, input1) asm ("dsbh %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1)) 247#define CVMX_DSHD(result, input1) asm ("dshd %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1)) 248#define CVMX_WSBH(result, input1) asm ("wsbh %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1)) 249 250// Endian swap 251#define CVMX_ES64(result, input) \ 252 do {\ 253 CVMX_DSBH(result, input); \ 254 CVMX_DSHD(result, result); \ 255 } while (0) 256#define CVMX_ES32(result, input) \ 257 do {\ 258 CVMX_WSBH(result, input); \ 259 CVMX_ROTR(result, result, 16); \ 260 } while (0) 261 262 263/* extract and insert - NOTE that pos and len variables must be constants! */ 264/* the P variants take len rather than lenm1 */ 265/* the M1 variants take lenm1 rather than len */ 266#define CVMX_EXTS(result,input,pos,lenm1) asm ("exts %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : [rs] "d" (input)) 267#define CVMX_EXTSP(result,input,pos,len) CVMX_EXTS(result,input,pos,(len)-1) 268 269#define CVMX_DEXT(result,input,pos,len) asm ("dext %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len) : [rt] "=d" (result) : [rs] "d" (input)) 270#define CVMX_DEXTM1(result,input,pos,lenm1) CVMX_DEXT(result,input,pos,(lenm1)+1) 271 272#define CVMX_EXT(result,input,pos,len) asm ("ext %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len) : [rt] "=d" (result) : [rs] "d" (input)) 273#define CVMX_EXTM1(result,input,pos,lenm1) CVMX_EXT(result,input,pos,(lenm1)+1) 274 275// removed 276// #define CVMX_EXTU(result,input,pos,lenm1) asm ("extu %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : [rs] "d" (input)) 277// #define CVMX_EXTUP(result,input,pos,len) CVMX_EXTU(result,input,pos,(len)-1) 278 279#define CVMX_CINS(result,input,pos,lenm1) asm ("cins %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : [rs] "d" (input)) 280#define CVMX_CINSP(result,input,pos,len) CVMX_CINS(result,input,pos,(len)-1) 281 282#define CVMX_DINS(result,input,pos,len) asm ("dins %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): [rs] "d" (input), "[rt]" (result)) 283#define CVMX_DINSM1(result,input,pos,lenm1) CVMX_DINS(result,input,pos,(lenm1)+1) 284#define CVMX_DINSC(result,pos,len) asm ("dins %[rt],$0," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): "[rt]" (result)) 285#define CVMX_DINSCM1(result,pos,lenm1) CVMX_DINSC(result,pos,(lenm1)+1) 286 287#define CVMX_INS(result,input,pos,len) asm ("ins %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): [rs] "d" (input), "[rt]" (result)) 288#define CVMX_INSM1(result,input,pos,lenm1) CVMX_INS(result,input,pos,(lenm1)+1) 289#define CVMX_INSC(result,pos,len) asm ("ins %[rt],$0," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): "[rt]" (result)) 290#define CVMX_INSCM1(result,pos,lenm1) CVMX_INSC(result,pos,(lenm1)+1) 291 292// removed 293// #define CVMX_INS0(result,input,pos,lenm1) asm("ins0 %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1): [rt] "=d" (result): [rs] "d" (input), "[rt]" (result)) 294// #define CVMX_INS0P(result,input,pos,len) CVMX_INS0(result,input,pos,(len)-1) 295// #define CVMX_INS0C(result,pos,lenm1) asm ("ins0 %[rt],$0," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : "[rt]" (result)) 296// #define CVMX_INS0CP(result,pos,len) CVMX_INS0C(result,pos,(len)-1) 297 298#define CVMX_CLZ(result, input) asm ("clz %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) 299#define CVMX_DCLZ(result, input) asm ("dclz %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) 300#define CVMX_CLO(result, input) asm ("clo %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) 301#define CVMX_DCLO(result, input) asm ("dclo %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) 302#define CVMX_POP(result, input) asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) 303#define CVMX_DPOP(result, input) asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) 304 305#ifdef CVMX_ABI_O32 306 307 /* rdhwr $31 is the 64 bit cmvcount register, it needs to be split 308 into one or two (depending on the width of the result) properly 309 sign extended registers. All other registers are 32 bits wide 310 and already properly sign extended. */ 311# define CVMX_RDHWRX(result, regstr, ASM_STMT) ({ \ 312 if (regstr == 31) { \ 313 if (sizeof(result) == 8) { \ 314 ASM_STMT (".set\tpush\n" \ 315 "\t.set\tmips64r2\n" \ 316 "\trdhwr\t%L0,$31\n" \ 317 "\tdsra\t%M0,%L0,32\n" \ 318 "\tsll\t%L0,%L0,0\n" \ 319 "\t.set\tpop": "=d"(result)); \ 320 } else { \ 321 unsigned long _v; \ 322 ASM_STMT ("rdhwr\t%0,$31\n" \ 323 "\tsll\t%0,%0,0" : "=d"(_v)); \ 324 result = (__typeof(result))_v; \ 325 } \ 326 } else { \ 327 unsigned long _v; \ 328 ASM_STMT ("rdhwr\t%0,$" CVMX_TMP_STR(regstr) : "=d"(_v)); \ 329 result = (__typeof(result))_v; \ 330 }}) 331 332 333 334# define CVMX_RDHWR(result, regstr) CVMX_RDHWRX(result, regstr, asm volatile) 335# define CVMX_RDHWRNV(result, regstr) CVMX_RDHWRX(result, regstr, asm) 336#else 337# define CVMX_RDHWR(result, regstr) asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result)) 338# define CVMX_RDHWRNV(result, regstr) asm ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result)) 339#endif 340 341// some new cop0-like stuff 342#define CVMX_DI(result) asm volatile ("di %[rt]" : [rt] "=d" (result)) 343#define CVMX_DI_NULL asm volatile ("di") 344#define CVMX_EI(result) asm volatile ("ei %[rt]" : [rt] "=d" (result)) 345#define CVMX_EI_NULL asm volatile ("ei") 346#define CVMX_EHB asm volatile ("ehb") 347 348/* mul stuff */ 349#define CVMX_MTM0(m) asm volatile ("mtm0 %[rs]" : : [rs] "d" (m)) 350#define CVMX_MTM1(m) asm volatile ("mtm1 %[rs]" : : [rs] "d" (m)) 351#define CVMX_MTM2(m) asm volatile ("mtm2 %[rs]" : : [rs] "d" (m)) 352#define CVMX_MTP0(p) asm volatile ("mtp0 %[rs]" : : [rs] "d" (p)) 353#define CVMX_MTP1(p) asm volatile ("mtp1 %[rs]" : : [rs] "d" (p)) 354#define CVMX_MTP2(p) asm volatile ("mtp2 %[rs]" : : [rs] "d" (p)) 355#define CVMX_VMULU(dest,mpcand,accum) asm volatile ("vmulu %[rd],%[rs],%[rt]" : [rd] "=d" (dest) : [rs] "d" (mpcand), [rt] "d" (accum)) 356#define CVMX_VMM0(dest,mpcand,accum) asm volatile ("vmm0 %[rd],%[rs],%[rt]" : [rd] "=d" (dest) : [rs] "d" (mpcand), [rt] "d" (accum)) 357#define CVMX_V3MULU(dest,mpcand,accum) asm volatile ("v3mulu %[rd],%[rs],%[rt]" : [rd] "=d" (dest) : [rs] "d" (mpcand), [rt] "d" (accum)) 358 359/* branch stuff */ 360// these are hard to make work because the compiler does not realize that the 361// instruction is a branch so may optimize away the label 362// the labels to these next two macros must not include a ":" at the end 363#define CVMX_BBIT1(var, pos, label) asm volatile ("bbit1 %[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(label) : : [rs] "d" (var)) 364#define CVMX_BBIT0(var, pos, label) asm volatile ("bbit0 %[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(label) : : [rs] "d" (var)) 365// the label to this macro must include a ":" at the end 366#define CVMX_ASM_LABEL(label) label \ 367 asm volatile (CVMX_TMP_STR(label) : : ) 368 369// 370// Low-latency memory stuff 371// 372// set can be 0-1 373#define CVMX_MT_LLM_READ_ADDR(set,val) asm volatile ("dmtc2 %[rt],0x0400+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val)) 374#define CVMX_MT_LLM_WRITE_ADDR_INTERNAL(set,val) asm volatile ("dmtc2 %[rt],0x0401+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val)) 375#define CVMX_MT_LLM_READ64_ADDR(set,val) asm volatile ("dmtc2 %[rt],0x0404+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val)) 376#define CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(set,val) asm volatile ("dmtc2 %[rt],0x0405+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val)) 377#define CVMX_MT_LLM_DATA(set,val) asm volatile ("dmtc2 %[rt],0x0402+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val)) 378#define CVMX_MF_LLM_DATA(set,val) asm volatile ("dmfc2 %[rt],0x0402+(8*(" CVMX_TMP_STR(set) "))" : [rt] "=d" (val) : ) 379 380 381// load linked, store conditional 382#define CVMX_LL(dest, address, offset) asm volatile ("ll %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (dest) : [rbase] "d" (address) ) 383#define CVMX_LLD(dest, address, offset) asm volatile ("lld %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (dest) : [rbase] "d" (address) ) 384#define CVMX_SC(srcdest, address, offset) asm volatile ("sc %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) 385#define CVMX_SCD(srcdest, address, offset) asm volatile ("scd %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) 386 387// load/store word left/right 388#define CVMX_LWR(srcdest, address, offset) asm volatile ("lwr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) 389#define CVMX_LWL(srcdest, address, offset) asm volatile ("lwl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) 390#define CVMX_LDR(srcdest, address, offset) asm volatile ("ldr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) 391#define CVMX_LDL(srcdest, address, offset) asm volatile ("ldl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) 392 393#define CVMX_SWR(src, address, offset) asm volatile ("swr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) ) 394#define CVMX_SWL(src, address, offset) asm volatile ("swl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) ) 395#define CVMX_SDR(src, address, offset) asm volatile ("sdr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) ) 396#define CVMX_SDL(src, address, offset) asm volatile ("sdl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) ) 397 398 399 400// 401// Useful crypto ASM's 402// 403 404// CRC 405 406#define CVMX_MT_CRC_POLYNOMIAL(val) asm volatile ("dmtc2 %[rt],0x4200" : : [rt] "d" (val)) 407#define CVMX_MT_CRC_IV(val) asm volatile ("dmtc2 %[rt],0x0201" : : [rt] "d" (val)) 408#define CVMX_MT_CRC_LEN(val) asm volatile ("dmtc2 %[rt],0x1202" : : [rt] "d" (val)) 409#define CVMX_MT_CRC_BYTE(val) asm volatile ("dmtc2 %[rt],0x0204" : : [rt] "d" (val)) 410#define CVMX_MT_CRC_HALF(val) asm volatile ("dmtc2 %[rt],0x0205" : : [rt] "d" (val)) 411#define CVMX_MT_CRC_WORD(val) asm volatile ("dmtc2 %[rt],0x0206" : : [rt] "d" (val)) 412#define CVMX_MT_CRC_DWORD(val) asm volatile ("dmtc2 %[rt],0x1207" : : [rt] "d" (val)) 413#define CVMX_MT_CRC_VAR(val) asm volatile ("dmtc2 %[rt],0x1208" : : [rt] "d" (val)) 414#define CVMX_MT_CRC_POLYNOMIAL_REFLECT(val) asm volatile ("dmtc2 %[rt],0x4210" : : [rt] "d" (val)) 415#define CVMX_MT_CRC_IV_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0211" : : [rt] "d" (val)) 416#define CVMX_MT_CRC_BYTE_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0214" : : [rt] "d" (val)) 417#define CVMX_MT_CRC_HALF_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0215" : : [rt] "d" (val)) 418#define CVMX_MT_CRC_WORD_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0216" : : [rt] "d" (val)) 419#define CVMX_MT_CRC_DWORD_REFLECT(val) asm volatile ("dmtc2 %[rt],0x1217" : : [rt] "d" (val)) 420#define CVMX_MT_CRC_VAR_REFLECT(val) asm volatile ("dmtc2 %[rt],0x1218" : : [rt] "d" (val)) 421 422#define CVMX_MF_CRC_POLYNOMIAL(val) asm volatile ("dmfc2 %[rt],0x0200" : [rt] "=d" (val) : ) 423#define CVMX_MF_CRC_IV(val) asm volatile ("dmfc2 %[rt],0x0201" : [rt] "=d" (val) : ) 424#define CVMX_MF_CRC_IV_REFLECT(val) asm volatile ("dmfc2 %[rt],0x0203" : [rt] "=d" (val) : ) 425#define CVMX_MF_CRC_LEN(val) asm volatile ("dmfc2 %[rt],0x0202" : [rt] "=d" (val) : ) 426 427// MD5 and SHA-1 428 429// pos can be 0-6 430#define CVMX_MT_HSH_DAT(val,pos) asm volatile ("dmtc2 %[rt],0x0040+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 431#define CVMX_MT_HSH_DATZ(pos) asm volatile ("dmtc2 $0,0x0040+" CVMX_TMP_STR(pos) : : ) 432// pos can be 0-14 433#define CVMX_MT_HSH_DATW(val,pos) asm volatile ("dmtc2 %[rt],0x0240+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 434#define CVMX_MT_HSH_DATWZ(pos) asm volatile ("dmtc2 $0,0x0240+" CVMX_TMP_STR(pos) : : ) 435#define CVMX_MT_HSH_STARTMD5(val) asm volatile ("dmtc2 %[rt],0x4047" : : [rt] "d" (val)) 436#define CVMX_MT_HSH_STARTSHA(val) asm volatile ("dmtc2 %[rt],0x4057" : : [rt] "d" (val)) 437#define CVMX_MT_HSH_STARTSHA256(val) asm volatile ("dmtc2 %[rt],0x404f" : : [rt] "d" (val)) 438#define CVMX_MT_HSH_STARTSHA512(val) asm volatile ("dmtc2 %[rt],0x424f" : : [rt] "d" (val)) 439// pos can be 0-3 440#define CVMX_MT_HSH_IV(val,pos) asm volatile ("dmtc2 %[rt],0x0048+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 441// pos can be 0-7 442#define CVMX_MT_HSH_IVW(val,pos) asm volatile ("dmtc2 %[rt],0x0250+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 443 444// pos can be 0-6 445#define CVMX_MF_HSH_DAT(val,pos) asm volatile ("dmfc2 %[rt],0x0040+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 446// pos can be 0-14 447#define CVMX_MF_HSH_DATW(val,pos) asm volatile ("dmfc2 %[rt],0x0240+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 448// pos can be 0-3 449#define CVMX_MF_HSH_IV(val,pos) asm volatile ("dmfc2 %[rt],0x0048+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 450// pos can be 0-7 451#define CVMX_MF_HSH_IVW(val,pos) asm volatile ("dmfc2 %[rt],0x0250+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 452 453// 3DES 454 455// pos can be 0-2 456#define CVMX_MT_3DES_KEY(val,pos) asm volatile ("dmtc2 %[rt],0x0080+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 457#define CVMX_MT_3DES_IV(val) asm volatile ("dmtc2 %[rt],0x0084" : : [rt] "d" (val)) 458#define CVMX_MT_3DES_ENC_CBC(val) asm volatile ("dmtc2 %[rt],0x4088" : : [rt] "d" (val)) 459#define CVMX_MT_3DES_ENC(val) asm volatile ("dmtc2 %[rt],0x408a" : : [rt] "d" (val)) 460#define CVMX_MT_3DES_DEC_CBC(val) asm volatile ("dmtc2 %[rt],0x408c" : : [rt] "d" (val)) 461#define CVMX_MT_3DES_DEC(val) asm volatile ("dmtc2 %[rt],0x408e" : : [rt] "d" (val)) 462#define CVMX_MT_3DES_RESULT(val) asm volatile ("dmtc2 %[rt],0x0098" : : [rt] "d" (val)) 463 464// pos can be 0-2 465#define CVMX_MF_3DES_KEY(val,pos) asm volatile ("dmfc2 %[rt],0x0080+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 466#define CVMX_MF_3DES_IV(val) asm volatile ("dmfc2 %[rt],0x0084" : [rt] "=d" (val) : ) 467#define CVMX_MF_3DES_RESULT(val) asm volatile ("dmfc2 %[rt],0x0088" : [rt] "=d" (val) : ) 468 469// KASUMI 470 471// pos can be 0-1 472#define CVMX_MT_KAS_KEY(val,pos) CVMX_MT_3DES_KEY(val,pos) 473#define CVMX_MT_KAS_ENC_CBC(val) asm volatile ("dmtc2 %[rt],0x4089" : : [rt] "d" (val)) 474#define CVMX_MT_KAS_ENC(val) asm volatile ("dmtc2 %[rt],0x408b" : : [rt] "d" (val)) 475#define CVMX_MT_KAS_RESULT(val) CVMX_MT_3DES_RESULT(val) 476 477// pos can be 0-1 478#define CVMX_MF_KAS_KEY(val,pos) CVMX_MF_3DES_KEY(val,pos) 479#define CVMX_MF_KAS_RESULT(val) CVMX_MF_3DES_RESULT(val) 480 481// AES 482 483#define CVMX_MT_AES_ENC_CBC0(val) asm volatile ("dmtc2 %[rt],0x0108" : : [rt] "d" (val)) 484#define CVMX_MT_AES_ENC_CBC1(val) asm volatile ("dmtc2 %[rt],0x3109" : : [rt] "d" (val)) 485#define CVMX_MT_AES_ENC0(val) asm volatile ("dmtc2 %[rt],0x010a" : : [rt] "d" (val)) 486#define CVMX_MT_AES_ENC1(val) asm volatile ("dmtc2 %[rt],0x310b" : : [rt] "d" (val)) 487#define CVMX_MT_AES_DEC_CBC0(val) asm volatile ("dmtc2 %[rt],0x010c" : : [rt] "d" (val)) 488#define CVMX_MT_AES_DEC_CBC1(val) asm volatile ("dmtc2 %[rt],0x310d" : : [rt] "d" (val)) 489#define CVMX_MT_AES_DEC0(val) asm volatile ("dmtc2 %[rt],0x010e" : : [rt] "d" (val)) 490#define CVMX_MT_AES_DEC1(val) asm volatile ("dmtc2 %[rt],0x310f" : : [rt] "d" (val)) 491// pos can be 0-3 492#define CVMX_MT_AES_KEY(val,pos) asm volatile ("dmtc2 %[rt],0x0104+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 493// pos can be 0-1 494#define CVMX_MT_AES_IV(val,pos) asm volatile ("dmtc2 %[rt],0x0102+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 495#define CVMX_MT_AES_KEYLENGTH(val) asm volatile ("dmtc2 %[rt],0x0110" : : [rt] "d" (val)) // write the keylen 496// pos can be 0-1 497#define CVMX_MT_AES_RESULT(val,pos) asm volatile ("dmtc2 %[rt],0x0100+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 498 499// pos can be 0-1 500#define CVMX_MF_AES_RESULT(val,pos) asm volatile ("dmfc2 %[rt],0x0100+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 501// pos can be 0-1 502#define CVMX_MF_AES_IV(val,pos) asm volatile ("dmfc2 %[rt],0x0102+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 503// pos can be 0-3 504#define CVMX_MF_AES_KEY(val,pos) asm volatile ("dmfc2 %[rt],0x0104+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 505#define CVMX_MF_AES_KEYLENGTH(val) asm volatile ("dmfc2 %[rt],0x0110" : [rt] "=d" (val) : ) // read the keylen 506#define CVMX_MF_AES_DAT0(val) asm volatile ("dmfc2 %[rt],0x0111" : [rt] "=d" (val) : ) // first piece of input data 507 508// GFM 509 510// pos can be 0-1 511#define CVMX_MF_GFM_MUL(val,pos) asm volatile ("dmfc2 %[rt],0x0258+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 512#define CVMX_MF_GFM_POLY(val) asm volatile ("dmfc2 %[rt],0x025e" : [rt] "=d" (val) : ) 513// pos can be 0-1 514#define CVMX_MF_GFM_RESINP(val,pos) asm volatile ("dmfc2 %[rt],0x025a+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 515// pos can be 0-1 516#define CVMX_MF_GFM_RESINP_REFLECT(val,pos) asm volatile ("dmfc2 %[rt],0x005a+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 517 518// pos can be 0-1 519#define CVMX_MT_GFM_MUL(val,pos) asm volatile ("dmtc2 %[rt],0x0258+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 520#define CVMX_MT_GFM_POLY(val) asm volatile ("dmtc2 %[rt],0x025e" : : [rt] "d" (val)) 521// pos can be 0-1 522#define CVMX_MT_GFM_RESINP(val,pos) asm volatile ("dmtc2 %[rt],0x025a+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 523#define CVMX_MT_GFM_XOR0(val) asm volatile ("dmtc2 %[rt],0x025c" : : [rt] "d" (val)) 524#define CVMX_MT_GFM_XORMUL1(val) asm volatile ("dmtc2 %[rt],0x425d" : : [rt] "d" (val)) 525// pos can be 0-1 526#define CVMX_MT_GFM_MUL_REFLECT(val,pos) asm volatile ("dmtc2 %[rt],0x0058+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 527#define CVMX_MT_GFM_XOR0_REFLECT(val) asm volatile ("dmtc2 %[rt],0x005c" : : [rt] "d" (val)) 528#define CVMX_MT_GFM_XORMUL1_REFLECT(val) asm volatile ("dmtc2 %[rt],0x405d" : : [rt] "d" (val)) 529 530// SNOW 3G 531 532// pos can be 0-7 533#define CVMX_MF_SNOW3G_LFSR(val,pos) asm volatile ("dmfc2 %[rt],0x0240+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 534// pos can be 0-2 535#define CVMX_MF_SNOW3G_FSM(val,pos) asm volatile ("dmfc2 %[rt],0x0251+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 536#define CVMX_MF_SNOW3G_RESULT(val) asm volatile ("dmfc2 %[rt],0x0250" : [rt] "=d" (val) : ) 537 538// pos can be 0-7 539#define CVMX_MT_SNOW3G_LFSR(val,pos) asm volatile ("dmtc2 %[rt],0x0240+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 540// pos can be 0-2 541#define CVMX_MT_SNOW3G_FSM(val,pos) asm volatile ("dmtc2 %[rt],0x0251+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 542#define CVMX_MT_SNOW3G_RESULT(val) asm volatile ("dmtc2 %[rt],0x0250" : : [rt] "d" (val)) 543#define CVMX_MT_SNOW3G_START(val) asm volatile ("dmtc2 %[rt],0x404d" : : [rt] "d" (val)) 544#define CVMX_MT_SNOW3G_MORE(val) asm volatile ("dmtc2 %[rt],0x404e" : : [rt] "d" (val)) 545 546// SMS4 547 548// pos can be 0-1 549#define CVMX_MF_SMS4_IV(val,pos) asm volatile ("dmfc2 %[rt],0x0102+"CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 550// pos can be 0-1 551#define CVMX_MF_SMS4_KEY(val,pos) asm volatile ("dmfc2 %[rt],0x0104+"CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 552// pos can be 0-1 553#define CVMX_MF_SMS4_RESINP(val,pos) asm volatile ("dmfc2 %[rt],0x0100+"CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 554#define CVMX_MT_SMS4_DEC_CBC0(val) asm volatile ("dmtc2 %[rt],0x010c" : : [rt] "d" (val)) 555#define CVMX_MT_SMS4_DEC_CBC1(val) asm volatile ("dmtc2 %[rt],0x311d" : : [rt] "d" (val)) 556#define CVMX_MT_SMS4_DEC0(val) asm volatile ("dmtc2 %[rt],0x010e" : : [rt] "d" (val)) 557#define CVMX_MT_SMS4_DEC1(val) asm volatile ("dmtc2 %[rt],0x311f" : : [rt] "d" (val)) 558#define CVMX_MT_SMS4_ENC_CBC0(val) asm volatile ("dmtc2 %[rt],0x0108" : : [rt] "d" (val)) 559#define CVMX_MT_SMS4_ENC_CBC1(val) asm volatile ("dmtc2 %[rt],0x3119" : : [rt] "d" (val)) 560#define CVMX_MT_SMS4_ENC0(val) asm volatile ("dmtc2 %[rt],0x010a" : : [rt] "d" (val)) 561#define CVMX_MT_SMS4_ENC1(val) asm volatile ("dmtc2 %[rt],0x311b" : : [rt] "d" (val)) 562// pos can be 0-1 563#define CVMX_MT_SMS4_IV(val,pos) asm volatile ("dmtc2 %[rt],0x0102+"CVMX_TMP_STR(pos) : : [rt] "d" (val)) 564// pos can be 0-1 565#define CVMX_MT_SMS4_KEY(val,pos) asm volatile ("dmtc2 %[rt],0x0104+"CVMX_TMP_STR(pos) : : [rt] "d" (val)) 566// pos can be 0-1 567#define CVMX_MT_SMS4_RESINP(val,pos) asm volatile ("dmtc2 %[rt],0x0100+"CVMX_TMP_STR(pos) : : [rt] "d" (val)) 568 569/* check_ordering stuff */ 570#if 0 571#define CVMX_MF_CHORD(dest) asm volatile ("dmfc2 %[rt],0x400" : [rt] "=d" (dest) : ) 572#else 573#define CVMX_MF_CHORD(dest) CVMX_RDHWR(dest, 30) 574#endif 575 576#if 0 577#define CVMX_MF_CYCLE(dest) asm volatile ("dmfc0 %[rt],$9,6" : [rt] "=d" (dest) : ) // Use (64-bit) CvmCount register rather than Count 578#else 579#define CVMX_MF_CYCLE(dest) CVMX_RDHWR(dest, 31) /* reads the current (64-bit) CvmCount value */ 580#endif 581 582#define CVMX_MT_CYCLE(src) asm volatile ("dmtc0 %[rt],$9,6" :: [rt] "d" (src)) 583 584#define VASTR(...) #__VA_ARGS__ 585 586#define CVMX_MF_COP0(val, cop0) asm volatile ("dmfc0 %[rt]," VASTR(cop0) : [rt] "=d" (val)); 587#define CVMX_MT_COP0(val, cop0) asm volatile ("dmtc0 %[rt]," VASTR(cop0) : : [rt] "d" (val)); 588 589#define CVMX_MF_CACHE_ERR(val) CVMX_MF_COP0(val, COP0_CACHEERRI) 590#define CVMX_MF_DCACHE_ERR(val) CVMX_MF_COP0(val, COP0_CACHEERRD) 591#define CVMX_MF_CVM_MEM_CTL(val) CVMX_MF_COP0(val, COP0_CVMMEMCTL) 592#define CVMX_MF_CVM_CTL(val) CVMX_MF_COP0(val, COP0_CVMCTL) 593#define CVMX_MT_CACHE_ERR(val) CVMX_MT_COP0(val, COP0_CACHEERRI) 594#define CVMX_MT_DCACHE_ERR(val) CVMX_MT_COP0(val, COP0_CACHEERRD) 595#define CVMX_MT_CVM_MEM_CTL(val) CVMX_MT_COP0(val, COP0_CVMMEMCTL) 596#define CVMX_MT_CVM_CTL(val) CVMX_MT_COP0(val, COP0_CVMCTL) 597 598/* Macros for TLB */ 599#define CVMX_TLBWI asm volatile ("tlbwi" : : ) 600#define CVMX_TLBWR asm volatile ("tlbwr" : : ) 601#define CVMX_TLBR asm volatile ("tlbr" : : ) 602#define CVMX_TLBP asm volatile ("tlbp" : : ) 603#define CVMX_MT_ENTRY_HIGH(val) asm volatile ("dmtc0 %[rt],$10,0" : : [rt] "d" (val)) 604#define CVMX_MT_ENTRY_LO_0(val) asm volatile ("dmtc0 %[rt],$2,0" : : [rt] "d" (val)) 605#define CVMX_MT_ENTRY_LO_1(val) asm volatile ("dmtc0 %[rt],$3,0" : : [rt] "d" (val)) 606#define CVMX_MT_PAGEMASK(val) asm volatile ("mtc0 %[rt],$5,0" : : [rt] "d" (val)) 607#define CVMX_MT_PAGEGRAIN(val) asm volatile ("mtc0 %[rt],$5,1" : : [rt] "d" (val)) 608#define CVMX_MT_TLB_INDEX(val) asm volatile ("mtc0 %[rt],$0,0" : : [rt] "d" (val)) 609#define CVMX_MT_TLB_CONTEXT(val) asm volatile ("dmtc0 %[rt],$4,0" : : [rt] "d" (val)) 610#define CVMX_MT_TLB_WIRED(val) asm volatile ("mtc0 %[rt],$6,0" : : [rt] "d" (val)) 611#define CVMX_MT_TLB_RANDOM(val) asm volatile ("mtc0 %[rt],$1,0" : : [rt] "d" (val)) 612#define CVMX_MF_ENTRY_LO_0(val) asm volatile ("dmfc0 %[rt],$2,0" : [rt] "=d" (val):) 613#define CVMX_MF_ENTRY_LO_1(val) asm volatile ("dmfc0 %[rt],$3,0" : [rt] "=d" (val):) 614#define CVMX_MF_ENTRY_HIGH(val) asm volatile ("dmfc0 %[rt],$10,0" : [rt] "=d" (val):) 615#define CVMX_MF_PAGEMASK(val) asm volatile ("mfc0 %[rt],$5,0" : [rt] "=d" (val):) 616#define CVMX_MF_PAGEGRAIN(val) asm volatile ("mfc0 %[rt],$5,1" : [rt] "=d" (val):) 617#define CVMX_MF_TLB_WIRED(val) asm volatile ("mfc0 %[rt],$6,0" : [rt] "=d" (val):) 618#define CVMX_MF_TLB_INDEX(val) asm volatile ("mfc0 %[rt],$0,0" : [rt] "=d" (val):) 619#define CVMX_MF_TLB_RANDOM(val) asm volatile ("mfc0 %[rt],$1,0" : [rt] "=d" (val):) 620#define TLB_DIRTY (0x1ULL<<2) 621#define TLB_VALID (0x1ULL<<1) 622#define TLB_GLOBAL (0x1ULL<<0) 623 624 625#if !defined(__FreeBSD__) || !defined(_KERNEL) 626/* Macros to PUSH and POP Octeon2 ISA. */ 627#define CVMX_PUSH_OCTEON2 asm volatile (".set push\n.set arch=octeon2") 628#define CVMX_POP_OCTEON2 asm volatile (".set pop") 629#endif 630 631/* assembler macros to guarantee byte loads/stores are used */ 632/* for an unaligned 16-bit access (these use AT register) */ 633/* we need the hidden argument (__a) so that GCC gets the dependencies right */ 634#define CVMX_LOADUNA_INT16(result, address, offset) \ 635 { char *__a = (char *)(address); \ 636 asm ("ulh %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : [rbase] "d" (__a), "m"(__a[offset]), "m"(__a[offset + 1])); } 637#define CVMX_LOADUNA_UINT16(result, address, offset) \ 638 { char *__a = (char *)(address); \ 639 asm ("ulhu %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : [rbase] "d" (__a), "m"(__a[offset + 0]), "m"(__a[offset + 1])); } 640#define CVMX_STOREUNA_INT16(data, address, offset) \ 641 { char *__a = (char *)(address); \ 642 asm ("ush %[rsrc], " CVMX_TMP_STR(offset) "(%[rbase])" : "=m"(__a[offset + 0]), "=m"(__a[offset + 1]): [rsrc] "d" (data), [rbase] "d" (__a)); } 643 644#define CVMX_LOADUNA_INT32(result, address, offset) \ 645 { char *__a = (char *)(address); \ 646 asm ("ulw %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : \ 647 [rbase] "d" (__a), "m"(__a[offset + 0]), "m"(__a[offset + 1]), "m"(__a[offset + 2]), "m"(__a[offset + 3])); } 648#define CVMX_STOREUNA_INT32(data, address, offset) \ 649 { char *__a = (char *)(address); \ 650 asm ("usw %[rsrc], " CVMX_TMP_STR(offset) "(%[rbase])" : \ 651 "=m"(__a[offset + 0]), "=m"(__a[offset + 1]), "=m"(__a[offset + 2]), "=m"(__a[offset + 3]) : \ 652 [rsrc] "d" (data), [rbase] "d" (__a)); } 653 654#define CVMX_LOADUNA_INT64(result, address, offset) \ 655 { char *__a = (char *)(address); \ 656 asm ("uld %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : \ 657 [rbase] "d" (__a), "m"(__a[offset + 0]), "m"(__a[offset + 1]), "m"(__a[offset + 2]), "m"(__a[offset + 3]), \ 658 "m"(__a[offset + 4]), "m"(__a[offset + 5]), "m"(__a[offset + 6]), "m"(__a[offset + 7])); } 659#define CVMX_STOREUNA_INT64(data, address, offset) \ 660 { char *__a = (char *)(address); \ 661 asm ("usd %[rsrc], " CVMX_TMP_STR(offset) "(%[rbase])" : \ 662 "=m"(__a[offset + 0]), "=m"(__a[offset + 1]), "=m"(__a[offset + 2]), "=m"(__a[offset + 3]), \ 663 "=m"(__a[offset + 4]), "=m"(__a[offset + 5]), "=m"(__a[offset + 6]), "=m"(__a[offset + 7]) : \ 664 [rsrc] "d" (data), [rbase] "d" (__a)); } 665 666#ifdef __cplusplus 667} 668#endif 669 670#endif /* __ASSEMBLER__ */ 671 672#endif /* __CVMX_ASM_H__ */ 673