1/*- 2 * Copyright (C) 2010 Nathan Whitehorn 3 * Copyright (C) 2011 glevand (geoffrey.levand@mail.ru) 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 24 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29/* Hypercall stubs. Note: this is all a hack and should die. */ 30 31#define hc .long 0x44000022 32 33#define LD64_IM(r, highest, higher, high, low) \ 34 lis r,highest; \ 35 addi r,r,higher; \ 36 sldi r,r,32; \ 37 addis r,r,high; \ 38 addi r,r,low; 39 40#define SIMPLE_HVCALL(x, c) \ 41.global x; \ 42x: \ 43 mflr %r0; \ 44 stw %r0,4(%r1); \ 45 clrldi %r3,%r3,32; \ 46 clrldi %r4,%r4,32; \ 47 clrldi %r5,%r5,32; \ 48 clrldi %r6,%r6,32; \ 49 clrldi %r7,%r7,32; \ 50 clrldi %r8,%r8,32; \ 51 clrldi %r9,%r9,32; \ 52 clrldi %r10,%r10,32; \ 53 li %r11,c; \ 54 hc; \ 55 extsw %r3,%r3; \ 56 lwz %r0,4(%r1); \ 57 mtlr %r0; \ 58 blr 59 60SIMPLE_HVCALL(lv1_open_device, 170) 61SIMPLE_HVCALL(lv1_close_device, 171) 62SIMPLE_HVCALL(lv1_gpu_open, 210) 63SIMPLE_HVCALL(lv1_gpu_context_attribute, 225) 64SIMPLE_HVCALL(lv1_panic, 255) 65SIMPLE_HVCALL(lv1_net_start_tx_dma, 187) 66SIMPLE_HVCALL(lv1_net_stop_tx_dma, 188) 67SIMPLE_HVCALL(lv1_net_start_rx_dma, 189) 68SIMPLE_HVCALL(lv1_net_stop_rx_dma, 190) 69 70.global lv1_get_physmem 71lv1_get_physmem: 72 mflr %r0 73 stw %r0,4(%r1) 74 stw %r3,-8(%r1) /* Address for maxmem */ 75 76 li %r11,69 /* Get PU ID */ 77 hc 78 std %r4,-16(%r1) 79 80 li %r11,74 /* Get LPAR ID */ 81 hc 82 std %r4,-24(%r1) 83 84 ld %r3,-24(%r1) 85 LD64_IM(%r4,0x0000,0x0000,0x6269,0x0000 /* "bi" */) 86 LD64_IM(%r5,0x7075,0x0000,0x0000,0x0000 /* "pu" */) 87 ld %r6,-16(%r1) 88 LD64_IM(%r7,0x726d,0x5f73,0x697a,0x6500 /* "rm_size" */) 89 li %r11,91 90 hc 91 extsw %r3,%r3 92 93 lwz %r5,-8(%r1) 94 std %r4,0(%r5) 95 96 lwz %r0,4(%r1) 97 mtlr %r0 98 blr 99 100.global lv1_setup_address_space 101lv1_setup_address_space: 102 mflr %r0 103 stw %r0,4(%r1) 104 105 stw %r3,-4(%r1) 106 stw %r4,-8(%r1) 107 108 li %r3,18 /* PT size: log2(256 KB) */ 109 li %r4,2 /* Two page sizes */ 110 li %r5,24 /* Page sizes: (24 << 56) | (16 << 48) */ 111 sldi %r5,%r5,24 112 li %r6,16 113 sldi %r6,%r6,16 114 or %r5,%r5,%r6 115 sldi %r5,%r5,32 116 117 li %r11,2 /* lv1_construct_virtual_address_space */ 118 hc 119 120 lwz %r6,-4(%r1) 121 lwz %r7,-8(%r1) 122 std %r4,0(%r6) 123 std %r5,0(%r7) 124 125 /* AS_ID in r4 */ 126 mr %r3,%r4 127 li %r11,7 /* lv1_select_virtual_address_space */ 128 hc 129 extsw %r3,%r3 130 131 lwz %r0,4(%r1) 132 mtlr %r0 133 blr 134 135.global lv1_insert_pte 136lv1_insert_pte: 137 mflr %r0 138 stw %r0,4(%r1) 139 140 mr %r11,%r4 /* Save R4 */ 141 142 clrldi %r3,%r3,32 143 clrldi %r7,%r5,32 144 145 sldi %r4,%r3,3 /* Convert ptegidx into base PTE slot */ 146 li %r3,0 /* Current address space */ 147 ld %r5,0(%r11) 148 ld %r6,8(%r11) 149 li %r8,0 /* No other flags */ 150 151 li %r11,158 152 hc 153 extsw %r3,%r3 154 155 lwz %r0,4(%r1) 156 mtlr %r0 157 blr 158 159.global lv1_gpu_context_allocate 160lv1_gpu_context_allocate: 161 mflr %r0 162 stw %r0,4(%r1) 163 stw %r7,-4(%r1) 164 165 sldi %r3,%r3,32 166 clrldi %r4,%r4,32 167 or %r3,%r3,%r4 168 clrldi %r4,%r5,32 169 clrldi %r5,%r6,32 170 171 li %r11,217 172 hc 173 extsw %r3,%r3 174 175 lwz %r7,-4(%r1) 176 std %r4,0(%r7) 177 178 lwz %r0,4(%r1) 179 mtlr %r0 180 blr 181 182.global lv1_gpu_memory_allocate 183lv1_gpu_memory_allocate: 184 mflr %r0 185 stw %r0,4(%r1) 186 stw %r8,-4(%r1) 187 stw %r9,-8(%r1) 188 189 li %r11,214 190 hc 191 extsw %r3,%r3 192 193 lwz %r8,-4(%r1) 194 lwz %r9,-8(%r1) 195 std %r4,0(%r8) 196 std %r5,0(%r9) 197 198 lwz %r0,4(%r1) 199 mtlr %r0 200 blr 201 202.global lv1_net_control 203lv1_net_control: 204 mflr %r0 205 stw %r0,4(%r1) 206 stw %r9,-4(%r1) 207 208 li %r11,194 209 hc 210 extsw %r3,%r3 211 212 lwz %r8,-4(%r1) 213 std %r4,0(%r8) 214 215 lwz %r0,4(%r1) 216 mtlr %r0 217 blr 218 219.global lv1_setup_dma 220lv1_setup_dma: 221 mflr %r0 222 stw %r0,4(%r1) 223 stw %r3,-4(%r1) 224 stw %r4,-8(%r1) 225 stw %r5,-12(%r1) 226 227 lwz %r3,-4(%r1) 228 lwz %r4,-8(%r1) 229 lis %r5,0x0800 /* 128 MB */ 230 li %r6,24 /* log2(IO_PAGESIZE) */ 231 li %r7,0 /* flags */ 232 li %r11,174 /* lv1_allocate_device_dma_region */ 233 hc 234 extsw %r3,%r3 235 cmpdi %r3,0 236 bne 1f 237 std %r4,-24(%r1) 238 239 lwz %r3,-4(%r1) 240 lwz %r4,-8(%r1) 241 li %r5,0 242 ld %r6,-24(%r1) 243 lis %r7,0x0800 /* 128 MB */ 244 lis %r8,0xf800 /* flags */ 245 sldi %r8,%r8,32 246 li %r11,176 /* lv1_map_device_dma_region */ 247 hc 248 extsw %r3,%r3 249 250 lwz %r9,-12(%r1) 251 ld %r6,-24(%r1) 252 std %r6,0(%r9) 253 2541: lwz %r0,4(%r1) 255 mtlr %r0 256 blr 257 258.global lv1_get_repository_node_value 259lv1_get_repository_node_value: 260 mflr %r0 261 stw %r0,4(%r1) 262 263 sldi %r3,%r3,32 264 clrldi %r4,%r4,32 265 or %r3,%r3,%r4 266 sldi %r4,%r5,32 267 clrldi %r5,%r6,32 268 or %r4,%r4,%r5 269 sldi %r5,%r7,32 270 clrldi %r6,%r8,32 271 or %r5,%r5,%r6 272 sldi %r6,%r9,32 273 clrldi %r7,%r10,32 274 or %r6,%r6,%r7 275 lwz %r7,8(%r1) 276 lwz %r8,12(%r1) 277 sldi %r7,%r7,32 278 or %r7,%r7,%r8 279 280 li %r11,91 281 hc 282 extsw %r3,%r3 283 284 lwz %r6,16(%r1) 285 std %r4,0(%r6) 286 lwz %r6,20(%r1) 287 std %r5,0(%r6) 288 289 lwz %r0,4(%r1) 290 mtlr %r0 291 blr 292 293.global lv1_storage_read 294lv1_storage_read: 295 mflr %r0 296 stw %r0,4(%r1) 297 298 sldi %r3,%r3,32 299 clrldi %r4,%r4,32 300 or %r3,%r3,%r4 301 sldi %r4,%r5,32 302 clrldi %r5,%r6,32 303 or %r4,%r4,%r5 304 sldi %r5,%r7,32 305 clrldi %r6,%r8,32 306 or %r5,%r5,%r6 307 sldi %r6,%r9,32 308 clrldi %r7,%r10,32 309 or %r6,%r6,%r7 310 ld %r7,8(%r1) 311 ld %r8,16(%r1) 312 313 li %r11,245 314 hc 315 extsw %r3,%r3 316 317 lwz %r5,24(%r1) 318 std %r4,0(%r5) 319 320 lwz %r0,4(%r1) 321 mtlr %r0 322 blr 323 324.global lv1_storage_check_async_status 325lv1_storage_check_async_status: 326 mflr %r0 327 stw %r0,4(%r1) 328 stw %r7,-4(%r1) 329 330 sldi %r3,%r3,32 331 clrldi %r4,%r4,32 332 or %r3,%r3,%r4 333 sldi %r4,%r5,32 334 clrldi %r5,%r6,32 335 or %r4,%r4,%r5 336 337 li %r11,254 338 hc 339 extsw %r3,%r3 340 341 lwz %r5,-4(%r1) 342 std %r4,0(%r5) 343 344 lwz %r0,4(%r1) 345 mtlr %r0 346 blr 347