1/*- 2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD$"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38 39#include <machine/bus.h> 40#include <machine/fdt.h> 41 42#include <arm/mv/mvreg.h> 43#include <arm/mv/mvvar.h> 44#include <arm/mv/mvwin.h> 45 46#if 0 47extern const struct obio_pci_irq_map pci_irq_map[]; 48const struct obio_pci mv_pci_info[] = { 49 { MV_TYPE_PCIE, 50 MV_PCIE_BASE, MV_PCIE_SIZE, 51 MV_PCIE_IO_BASE, MV_PCIE_IO_SIZE, 4, 0x51, 52 MV_PCIE_MEM_BASE, MV_PCIE_MEM_SIZE, 4, 0x59, 53 NULL, MV_INT_PEX0 54 }, 55 56 { MV_TYPE_PCI, 57 MV_PCI_BASE, MV_PCI_SIZE, 58 MV_PCI_IO_BASE, MV_PCI_IO_SIZE, 3, 0x51, 59 MV_PCI_MEM_BASE, MV_PCI_MEM_SIZE, 3, 0x59, 60 pci_irq_map, -1 61 }, 62 63 { 0, 0, 0 } 64}; 65#endif 66 67struct resource_spec mv_gpio_res[] = { 68 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 69 { SYS_RES_IRQ, 0, RF_ACTIVE }, 70 { SYS_RES_IRQ, 1, RF_ACTIVE }, 71 { SYS_RES_IRQ, 2, RF_ACTIVE }, 72 { SYS_RES_IRQ, 3, RF_ACTIVE }, 73 { -1, 0 } 74}; 75 76const struct decode_win idma_win_tbl[] = { 77 { 0 }, 78}; 79const struct decode_win *idma_wins = idma_win_tbl; 80int idma_wins_no = 0; 81 82uint32_t 83get_tclk(void) 84{ 85 uint32_t sar; 86 87 /* 88 * On Orion TCLK is can be configured to 150 MHz or 166 MHz. 89 * Current setting is read from Sample At Reset register. 90 */ 91 /* XXX MPP addr should be retrieved from the DT */ 92 sar = bus_space_read_4(fdtbus_bs_tag, MV_MPP_BASE, SAMPLE_AT_RESET); 93 sar = (sar & TCLK_MASK) >> TCLK_SHIFT; 94 switch (sar) { 95 case 1: 96 return (TCLK_150MHZ); 97 case 2: 98 return (TCLK_166MHZ); 99 default: 100 panic("Unknown TCLK settings!"); 101 } 102} 103