1/*-
2 * Copyright (c) 2006 M. Warner Losh.  All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26/* $FreeBSD$ */
27
28#ifndef ARM_AT91_AT91_PIOREG_H
29#define ARM_AT91_AT91_PIOREG_H
30
31/* Registers */
32#define PIO_PER		0x00		/* PIO Enable Register */
33#define PIO_PDR		0x04		/* PIO Disable Register */
34#define PIO_PSR		0x08		/* PIO Status Register */
35		/*	0x0c		   reserved */
36#define PIO_OER		0x10		/* PIO Output Enable Register */
37#define PIO_ODR		0x14		/* PIO Output Disable Register */
38#define PIO_OSR		0x18		/* PIO Output Status Register */
39		/*	0x1c		   reserved */
40#define PIO_IFER	0x20		/* PIO Glitch Input Enable Register */
41#define PIO_IFDR	0x24		/* PIO Glitch Input Disable Register */
42#define PIO_IFSR	0x28		/* PIO Glitch Input Status Register */
43		/*	0x2c		   reserved */
44#define PIO_SODR	0x30		/* PIO Set Output Data Register */
45#define PIO_CODR	0x34		/* PIO Clear Output Data Register */
46#define PIO_ODSR	0x38		/* PIO Output Data Status Register */
47#define PIO_PDSR	0x3c		/* PIO Pin Data Status Register */
48#define PIO_IER		0x40		/* PIO Interrupt Enable Register */
49#define PIO_IDR		0x44		/* PIO Interrupt Disable Register */
50#define PIO_IMR		0x48		/* PIO Interrupt Mask Register */
51#define PIO_ISR		0x4c		/* PIO Interrupt Status Register */
52#define PIO_MDER	0x50		/* PIO Multi-Driver Enable Register */
53#define PIO_MDDR	0x54		/* PIO Multi-Driver Disable Register */
54#define PIO_MDSR	0x58		/* PIO Multi-Driver Status Register */
55		/*	0x5c		   reserved */
56#define PIO_PUDR	0x60		/* PIO Pull-up Disable Register */
57#define PIO_PUER	0x64		/* PIO Pull-up Enable Register */
58#define PIO_PUSR	0x68		/* PIO Pull-up Status Register */
59		/*	0x6c		   reserved */
60#define PIO_ASR		0x70		/* PIO Peripheral A Select Register */
61#define PIO_BSR		0x74		/* PIO Peripheral B Select Register */
62#define PIO_ABSR	0x78		/* PIO AB Status Register */
63		/*	0x7c-0x9c	   reserved */
64#define PIO_OWER	0xa0		/* PIO Output Write Enable Register */
65#define PIO_OWDR	0xa4		/* PIO Output Write Disable Register */
66#define PIO_OWSR	0xa8		/* PIO Output Write Status Register */
67		/*	0xac		   reserved */
68
69#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
70#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
71#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
72#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
73#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
74#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
75#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
76#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
77#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
78#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
79#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
80#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
81#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
82#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
83#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
84#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
85#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
86#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
87#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
88#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
89#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
90#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
91#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
92#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
93#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
94#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
95#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
96#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
97#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
98#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
99#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
100#define AT91C_PIO_PA31       ((unsigned int) 1 << 31) // Pin Controlled by PA31
101#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
102#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
103#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
104#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
105#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
106#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
107#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
108#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
109#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
110#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
111#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
112#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
113#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
114#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
115#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
116#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
117#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
118#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
119#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
120#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
121#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
122#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
123#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
124#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
125#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
126#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
127#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
128#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
129#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
130#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
131#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
132#define AT91C_PIO_PB31       ((unsigned int) 1 << 31) // Pin Controlled by PB31
133#define AT91C_PIO_PC0        ((unsigned int) 1 <<  0) // Pin Controlled by PC0
134#define AT91C_PIO_PC1        ((unsigned int) 1 <<  1) // Pin Controlled by PC1
135#define AT91C_PIO_PC2        ((unsigned int) 1 <<  2) // Pin Controlled by PC2
136#define AT91C_PIO_PC3        ((unsigned int) 1 <<  3) // Pin Controlled by PC3
137#define AT91C_PIO_PC4        ((unsigned int) 1 <<  4) // Pin Controlled by PC4
138#define AT91C_PIO_PC5        ((unsigned int) 1 <<  5) // Pin Controlled by PC5
139#define AT91C_PIO_PC6        ((unsigned int) 1 <<  6) // Pin Controlled by PC6
140#define AT91C_PIO_PC7        ((unsigned int) 1 <<  7) // Pin Controlled by PC7
141#define AT91C_PIO_PC8        ((unsigned int) 1 <<  8) // Pin Controlled by PC8
142#define AT91C_PIO_PC9        ((unsigned int) 1 <<  9) // Pin Controlled by PC9
143#define AT91C_PIO_PC10       ((unsigned int) 1 << 10) // Pin Controlled by PC10
144#define AT91C_PIO_PC11       ((unsigned int) 1 << 11) // Pin Controlled by PC11
145#define AT91C_PIO_PC12       ((unsigned int) 1 << 12) // Pin Controlled by PC12
146#define AT91C_PIO_PC13       ((unsigned int) 1 << 13) // Pin Controlled by PC13
147#define AT91C_PIO_PC14       ((unsigned int) 1 << 14) // Pin Controlled by PC14
148#define AT91C_PIO_PC15       ((unsigned int) 1 << 15) // Pin Controlled by PC15
149#define AT91C_PIO_PC16       ((unsigned int) 1 << 16) // Pin Controlled by PC16
150#define AT91C_PIO_PC17       ((unsigned int) 1 << 17) // Pin Controlled by PC17
151#define AT91C_PIO_PC18       ((unsigned int) 1 << 18) // Pin Controlled by PC18
152#define AT91C_PIO_PC19       ((unsigned int) 1 << 19) // Pin Controlled by PC19
153#define AT91C_PIO_PC20       ((unsigned int) 1 << 20) // Pin Controlled by PC20
154#define AT91C_PIO_PC21       ((unsigned int) 1 << 21) // Pin Controlled by PC21
155#define AT91C_PIO_PC22       ((unsigned int) 1 << 22) // Pin Controlled by PC22
156#define AT91C_PIO_PC23       ((unsigned int) 1 << 23) // Pin Controlled by PC23
157#define AT91C_PIO_PC24       ((unsigned int) 1 << 24) // Pin Controlled by PC24
158#define AT91C_PIO_PC25       ((unsigned int) 1 << 25) // Pin Controlled by PC25
159#define AT91C_PIO_PC26       ((unsigned int) 1 << 26) // Pin Controlled by PC26
160#define AT91C_PIO_PC27       ((unsigned int) 1 << 27) // Pin Controlled by PC27
161#define AT91C_PIO_PC28       ((unsigned int) 1 << 28) // Pin Controlled by PC28
162#define AT91C_PIO_PC29       ((unsigned int) 1 << 29) // Pin Controlled by PC29
163#define AT91C_PIO_PC30       ((unsigned int) 1 << 30) // Pin Controlled by PC30
164#define AT91C_PIO_PC31       ((unsigned int) 1 << 31) // Pin Controlled by PC31
165
166#endif /* ARM_AT91_AT91_PIOREG_H */
167