1.file "__udivsi3.s" 2 3// 4// Copyright (c) 2000, Intel Corporation 5// All rights reserved. 6// 7// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, 8// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, 9// Intel Corporation. 10// 11// WARRANTY DISCLAIMER 12// 13// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 14// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 15// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 16// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS 17// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 18// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 19// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 21// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING 22// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24// 25// Intel Corporation is the author of this code, and requests that all 26// problem reports or change requests be submitted to it directly at 27// http://developer.intel.com/opensource. 28// 29 30#include <machine/asm.h> 31__FBSDID("$FreeBSD$"); 32 33.section .text 34 35// 32-bit unsigned integer divide 36 37.proc __udivsi3# 38.align 32 39.global __udivsi3# 40.align 32 41 42__udivsi3: 43 44{ .mii 45 alloc r31=ar.pfs,2,0,0,0 46 nop.i 0 47 nop.i 0;; 48} { .mii 49 nop.m 0 50 51 // 32-BIT UNSIGNED INTEGER DIVIDE BEGINS HERE 52 53 // general register used: 54 // r32 - 32-bit unsigned integer dividend 55 // r33 - 32-bit unsigned integer divisor 56 // r8 - 32-bit unsigned integer result 57 // r2 - scratch register 58 // floating-point registers used: f6, f7, f8, f9 59 // predicate registers used: p6 60 61 zxt4 r32=r32 62 zxt4 r33=r33;; 63} { .mmb 64 setf.sig f6=r32 65 setf.sig f7=r33 66 nop.b 0;; 67} { .mfi 68 nop.m 0 69 fcvt.xf f6=f6 70 nop.i 0 71} { .mfi 72 nop.m 0 73 fcvt.xf f7=f7 74 mov r2 = 0x0ffdd;; 75} { .mfi 76 setf.exp f9 = r2 77 // (1) y0 78 frcpa.s1 f8,p6=f6,f7 79 nop.i 0;; 80} { .mfi 81 nop.m 0 82 // (2) q0 = a * y0 83 (p6) fma.s1 f6=f6,f8,f0 84 nop.i 0 85} { .mfi 86 nop.m 0 87 // (3) e0 = 1 - b * y0 88 (p6) fnma.s1 f7=f7,f8,f1 89 nop.i 0;; 90} { .mfi 91 nop.m 0 92 // (4) q1 = q0 + e0 * q0 93 (p6) fma.s1 f6=f7,f6,f6 94 nop.i 0 95} { .mfi 96 nop.m 0 97 // (5) e1 = e0 * e0 + 2^-34 98 (p6) fma.s1 f7=f7,f7,f9 99 nop.i 0;; 100} { .mfi 101 nop.m 0 102 // (6) q2 = q1 + e1 * q1 103 (p6) fma.s1 f8=f7,f6,f6 104 nop.i 0;; 105} { .mfi 106 nop.m 0 107 // (7) q = trunc(q2) 108 fcvt.fxu.trunc.s1 f8=f8 109 nop.i 0;; 110} { .mmi 111 // quotient will be in the least significant 32 bits of r8 (if b != 0) 112 getf.sig r8=f8 113 nop.m 0 114 nop.i 0;; 115} 116 117 // 32-BIT UNSIGNED INTEGER DIVIDE ENDS HERE 118 119{ .mmb 120 nop.m 0 121 nop.m 0 122 br.ret.sptk b0;; 123} 124 125.endp __udivsi3 126