1/*
2 * Copyright (c) 2007 Cisco, Inc.  All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses.  You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 *     Redistribution and use in source and binary forms, with or
11 *     without modification, are permitted provided that the following
12 *     conditions are met:
13 *
14 *      - Redistributions of source code must retain the above
15 *        copyright notice, this list of conditions and the following
16 *        disclaimer.
17 *
18 *      - Redistributions in binary form must reproduce the above
19 *        copyright notice, this list of conditions and the following
20 *        disclaimer in the documentation and/or other materials
21 *        provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef WQE_H
34#define WQE_H
35
36enum {
37	MLX4_SEND_DOORBELL	= 0x14,
38};
39
40enum {
41	MLX4_WQE_CTRL_FENCE	= 1 << 6,
42	MLX4_WQE_CTRL_CQ_UPDATE	= 3 << 2,
43	MLX4_WQE_CTRL_SOLICIT	= 1 << 1,
44};
45
46enum {
47	MLX4_INLINE_SEG		= 1 << 31,
48	MLX4_INLINE_ALIGN	= 64,
49};
50
51enum {
52	MLX4_INVALID_LKEY	= 0x100,
53};
54
55struct mlx4_wqe_ctrl_seg {
56	uint32_t		owner_opcode;
57	uint16_t                vlan_tag;
58	uint8_t                 ins_vlan;
59	uint8_t			fence_size;
60	/*
61	 * High 24 bits are SRC remote buffer; low 8 bits are flags:
62	 * [7]   SO (strong ordering)
63	 * [5]   TCP/UDP checksum
64	 * [4]   IP checksum
65	 * [3:2] C (generate completion queue entry)
66	 * [1]   SE (solicited event)
67	 * [0]   FL (force loopback)
68	 */
69	uint32_t		xrcrb_flags;
70	/*
71	 * imm is immediate data for send/RDMA write w/ immediate;
72	 * also invalidation key for send with invalidate; input
73	 * modifier for WQEs on CCQs.
74	 */
75	uint32_t		imm;
76};
77
78struct mlx4_wqe_datagram_seg {
79	uint32_t		av[8];
80	uint32_t		dqpn;
81	uint32_t		qkey;
82	uint16_t		vlan;
83	uint8_t			mac[6];
84};
85
86struct mlx4_wqe_data_seg {
87	uint32_t		byte_count;
88	uint32_t		lkey;
89	uint64_t		addr;
90};
91
92struct mlx4_wqe_inline_seg {
93	uint32_t		byte_count;
94};
95
96struct mlx4_wqe_srq_next_seg {
97	uint16_t		reserved1;
98	uint16_t		next_wqe_index;
99	uint32_t		reserved2[3];
100};
101
102struct mlx4_wqe_raddr_seg {
103	uint64_t		raddr;
104	uint32_t		rkey;
105	uint32_t		reserved;
106};
107
108struct mlx4_wqe_atomic_seg {
109	uint64_t		swap_add;
110	uint64_t		compare;
111};
112
113struct mlx4_wqe_bind_seg {
114	uint32_t		flags1;
115	uint32_t		flags2;
116	uint32_t		new_rkey;
117	uint32_t		lkey;
118	uint64_t		addr;
119	uint64_t		length;
120};
121
122#endif /* WQE_H */
123