1Pull in r199033 from upstream llvm trunk (by Venkatraman Govindaraju): 2 3 [Sparc] Add support for parsing floating point instructions. 4 5Introduced here: http://svn.freebsd.org/changeset/base/262261 6 7Index: lib/Target/Sparc/SparcInstrInfo.td 8=================================================================== 9--- lib/Target/Sparc/SparcInstrInfo.td 10+++ lib/Target/Sparc/SparcInstrInfo.td 11@@ -601,91 +601,91 @@ let Defs = [Y], rd = 0 in { 12 } 13 // Convert Integer to Floating-point Instructions, p. 141 14 def FITOS : F3_3u<2, 0b110100, 0b011000100, 15- (outs FPRegs:$dst), (ins FPRegs:$src), 16- "fitos $src, $dst", 17- [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 18+ (outs FPRegs:$rd), (ins FPRegs:$rs2), 19+ "fitos $rs2, $rd", 20+ [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>; 21 def FITOD : F3_3u<2, 0b110100, 0b011001000, 22- (outs DFPRegs:$dst), (ins FPRegs:$src), 23- "fitod $src, $dst", 24- [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 25+ (outs DFPRegs:$rd), (ins FPRegs:$rs2), 26+ "fitod $rs2, $rd", 27+ [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>; 28 def FITOQ : F3_3u<2, 0b110100, 0b011001100, 29- (outs QFPRegs:$dst), (ins FPRegs:$src), 30- "fitoq $src, $dst", 31- [(set QFPRegs:$dst, (SPitof FPRegs:$src))]>, 32+ (outs QFPRegs:$rd), (ins FPRegs:$rs2), 33+ "fitoq $rs2, $rd", 34+ [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>, 35 Requires<[HasHardQuad]>; 36 37 // Convert Floating-point to Integer Instructions, p. 142 38 def FSTOI : F3_3u<2, 0b110100, 0b011010001, 39- (outs FPRegs:$dst), (ins FPRegs:$src), 40- "fstoi $src, $dst", 41- [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 42+ (outs FPRegs:$rd), (ins FPRegs:$rs2), 43+ "fstoi $rs2, $rd", 44+ [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))]>; 45 def FDTOI : F3_3u<2, 0b110100, 0b011010010, 46- (outs FPRegs:$dst), (ins DFPRegs:$src), 47- "fdtoi $src, $dst", 48- [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 49+ (outs FPRegs:$rd), (ins DFPRegs:$rs2), 50+ "fdtoi $rs2, $rd", 51+ [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))]>; 52 def FQTOI : F3_3u<2, 0b110100, 0b011010011, 53- (outs FPRegs:$dst), (ins QFPRegs:$src), 54- "fqtoi $src, $dst", 55- [(set FPRegs:$dst, (SPftoi QFPRegs:$src))]>, 56+ (outs FPRegs:$rd), (ins QFPRegs:$rs2), 57+ "fqtoi $rs2, $rd", 58+ [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>, 59 Requires<[HasHardQuad]>; 60 61 // Convert between Floating-point Formats Instructions, p. 143 62 def FSTOD : F3_3u<2, 0b110100, 0b011001001, 63- (outs DFPRegs:$dst), (ins FPRegs:$src), 64- "fstod $src, $dst", 65- [(set f64:$dst, (fextend f32:$src))]>; 66+ (outs DFPRegs:$rd), (ins FPRegs:$rs2), 67+ "fstod $rs2, $rd", 68+ [(set f64:$rd, (fextend f32:$rs2))]>; 69 def FSTOQ : F3_3u<2, 0b110100, 0b011001101, 70- (outs QFPRegs:$dst), (ins FPRegs:$src), 71- "fstoq $src, $dst", 72- [(set f128:$dst, (fextend f32:$src))]>, 73+ (outs QFPRegs:$rd), (ins FPRegs:$rs2), 74+ "fstoq $rs2, $rd", 75+ [(set f128:$rd, (fextend f32:$rs2))]>, 76 Requires<[HasHardQuad]>; 77 def FDTOS : F3_3u<2, 0b110100, 0b011000110, 78- (outs FPRegs:$dst), (ins DFPRegs:$src), 79- "fdtos $src, $dst", 80- [(set f32:$dst, (fround f64:$src))]>; 81-def FDTOQ : F3_3u<2, 0b110100, 0b01101110, 82- (outs QFPRegs:$dst), (ins DFPRegs:$src), 83- "fdtoq $src, $dst", 84- [(set f128:$dst, (fextend f64:$src))]>, 85+ (outs FPRegs:$rd), (ins DFPRegs:$rs2), 86+ "fdtos $rs2, $rd", 87+ [(set f32:$rd, (fround f64:$rs2))]>; 88+def FDTOQ : F3_3u<2, 0b110100, 0b011001110, 89+ (outs QFPRegs:$rd), (ins DFPRegs:$rs2), 90+ "fdtoq $rs2, $rd", 91+ [(set f128:$rd, (fextend f64:$rs2))]>, 92 Requires<[HasHardQuad]>; 93 def FQTOS : F3_3u<2, 0b110100, 0b011000111, 94- (outs FPRegs:$dst), (ins QFPRegs:$src), 95- "fqtos $src, $dst", 96- [(set f32:$dst, (fround f128:$src))]>, 97+ (outs FPRegs:$rd), (ins QFPRegs:$rs2), 98+ "fqtos $rs2, $rd", 99+ [(set f32:$rd, (fround f128:$rs2))]>, 100 Requires<[HasHardQuad]>; 101 def FQTOD : F3_3u<2, 0b110100, 0b011001011, 102- (outs DFPRegs:$dst), (ins QFPRegs:$src), 103- "fqtod $src, $dst", 104- [(set f64:$dst, (fround f128:$src))]>, 105+ (outs DFPRegs:$rd), (ins QFPRegs:$rs2), 106+ "fqtod $rs2, $rd", 107+ [(set f64:$rd, (fround f128:$rs2))]>, 108 Requires<[HasHardQuad]>; 109 110 // Floating-point Move Instructions, p. 144 111 def FMOVS : F3_3u<2, 0b110100, 0b000000001, 112- (outs FPRegs:$dst), (ins FPRegs:$src), 113- "fmovs $src, $dst", []>; 114+ (outs FPRegs:$rd), (ins FPRegs:$rs2), 115+ "fmovs $rs2, $rd", []>; 116 def FNEGS : F3_3u<2, 0b110100, 0b000000101, 117- (outs FPRegs:$dst), (ins FPRegs:$src), 118- "fnegs $src, $dst", 119- [(set f32:$dst, (fneg f32:$src))]>; 120+ (outs FPRegs:$rd), (ins FPRegs:$rs2), 121+ "fnegs $rs2, $rd", 122+ [(set f32:$rd, (fneg f32:$rs2))]>; 123 def FABSS : F3_3u<2, 0b110100, 0b000001001, 124- (outs FPRegs:$dst), (ins FPRegs:$src), 125- "fabss $src, $dst", 126- [(set f32:$dst, (fabs f32:$src))]>; 127+ (outs FPRegs:$rd), (ins FPRegs:$rs2), 128+ "fabss $rs2, $rd", 129+ [(set f32:$rd, (fabs f32:$rs2))]>; 130 131 132 // Floating-point Square Root Instructions, p.145 133 def FSQRTS : F3_3u<2, 0b110100, 0b000101001, 134- (outs FPRegs:$dst), (ins FPRegs:$src), 135- "fsqrts $src, $dst", 136- [(set f32:$dst, (fsqrt f32:$src))]>; 137+ (outs FPRegs:$rd), (ins FPRegs:$rs2), 138+ "fsqrts $rs2, $rd", 139+ [(set f32:$rd, (fsqrt f32:$rs2))]>; 140 def FSQRTD : F3_3u<2, 0b110100, 0b000101010, 141- (outs DFPRegs:$dst), (ins DFPRegs:$src), 142- "fsqrtd $src, $dst", 143- [(set f64:$dst, (fsqrt f64:$src))]>; 144+ (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 145+ "fsqrtd $rs2, $rd", 146+ [(set f64:$rd, (fsqrt f64:$rs2))]>; 147 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011, 148- (outs QFPRegs:$dst), (ins QFPRegs:$src), 149- "fsqrtq $src, $dst", 150- [(set f128:$dst, (fsqrt f128:$src))]>, 151+ (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 152+ "fsqrtq $rs2, $rd", 153+ [(set f128:$rd, (fsqrt f128:$rs2))]>, 154 Requires<[HasHardQuad]>; 155 156 157@@ -692,73 +692,73 @@ def FSQRTQ : F3_3u<2, 0b110100, 0b000101011, 158 159 // Floating-point Add and Subtract Instructions, p. 146 160 def FADDS : F3_3<2, 0b110100, 0b001000001, 161- (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 162- "fadds $src1, $src2, $dst", 163- [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>; 164+ (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 165+ "fadds $rs1, $rs2, $rd", 166+ [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>; 167 def FADDD : F3_3<2, 0b110100, 0b001000010, 168- (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 169- "faddd $src1, $src2, $dst", 170- [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>; 171+ (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 172+ "faddd $rs1, $rs2, $rd", 173+ [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>; 174 def FADDQ : F3_3<2, 0b110100, 0b001000011, 175- (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 176- "faddq $src1, $src2, $dst", 177- [(set f128:$dst, (fadd f128:$src1, f128:$src2))]>, 178+ (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 179+ "faddq $rs1, $rs2, $rd", 180+ [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>, 181 Requires<[HasHardQuad]>; 182 183 def FSUBS : F3_3<2, 0b110100, 0b001000101, 184- (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 185- "fsubs $src1, $src2, $dst", 186- [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>; 187+ (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 188+ "fsubs $rs1, $rs2, $rd", 189+ [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))]>; 190 def FSUBD : F3_3<2, 0b110100, 0b001000110, 191- (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 192- "fsubd $src1, $src2, $dst", 193- [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>; 194+ (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 195+ "fsubd $rs1, $rs2, $rd", 196+ [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))]>; 197 def FSUBQ : F3_3<2, 0b110100, 0b001000111, 198- (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 199- "fsubq $src1, $src2, $dst", 200- [(set f128:$dst, (fsub f128:$src1, f128:$src2))]>, 201+ (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 202+ "fsubq $rs1, $rs2, $rd", 203+ [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>, 204 Requires<[HasHardQuad]>; 205 206 207 // Floating-point Multiply and Divide Instructions, p. 147 208 def FMULS : F3_3<2, 0b110100, 0b001001001, 209- (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 210- "fmuls $src1, $src2, $dst", 211- [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>; 212+ (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 213+ "fmuls $rs1, $rs2, $rd", 214+ [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))]>; 215 def FMULD : F3_3<2, 0b110100, 0b001001010, 216- (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 217- "fmuld $src1, $src2, $dst", 218- [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>; 219+ (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 220+ "fmuld $rs1, $rs2, $rd", 221+ [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))]>; 222 def FMULQ : F3_3<2, 0b110100, 0b001001011, 223- (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 224- "fmulq $src1, $src2, $dst", 225- [(set f128:$dst, (fmul f128:$src1, f128:$src2))]>, 226+ (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 227+ "fmulq $rs1, $rs2, $rd", 228+ [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>, 229 Requires<[HasHardQuad]>; 230 231 def FSMULD : F3_3<2, 0b110100, 0b001101001, 232- (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 233- "fsmuld $src1, $src2, $dst", 234- [(set f64:$dst, (fmul (fextend f32:$src1), 235- (fextend f32:$src2)))]>; 236+ (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 237+ "fsmuld $rs1, $rs2, $rd", 238+ [(set f64:$rd, (fmul (fextend f32:$rs1), 239+ (fextend f32:$rs2)))]>; 240 def FDMULQ : F3_3<2, 0b110100, 0b001101110, 241- (outs QFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 242- "fdmulq $src1, $src2, $dst", 243- [(set f128:$dst, (fmul (fextend f64:$src1), 244- (fextend f64:$src2)))]>, 245+ (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 246+ "fdmulq $rs1, $rs2, $rd", 247+ [(set f128:$rd, (fmul (fextend f64:$rs1), 248+ (fextend f64:$rs2)))]>, 249 Requires<[HasHardQuad]>; 250 251 def FDIVS : F3_3<2, 0b110100, 0b001001101, 252- (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 253- "fdivs $src1, $src2, $dst", 254- [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>; 255+ (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 256+ "fdivs $rs1, $rs2, $rd", 257+ [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))]>; 258 def FDIVD : F3_3<2, 0b110100, 0b001001110, 259- (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 260- "fdivd $src1, $src2, $dst", 261- [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>; 262+ (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 263+ "fdivd $rs1, $rs2, $rd", 264+ [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))]>; 265 def FDIVQ : F3_3<2, 0b110100, 0b001001111, 266- (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 267- "fdivq $src1, $src2, $dst", 268- [(set f128:$dst, (fdiv f128:$src1, f128:$src2))]>, 269+ (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 270+ "fdivq $rs1, $rs2, $rd", 271+ [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>, 272 Requires<[HasHardQuad]>; 273 274 // Floating-point Compare Instructions, p. 148 275@@ -770,17 +770,17 @@ def FDIVQ : F3_3<2, 0b110100, 0b001001111, 276 277 let Defs = [FCC] in { 278 def FCMPS : F3_3c<2, 0b110101, 0b001010001, 279- (outs), (ins FPRegs:$src1, FPRegs:$src2), 280- "fcmps $src1, $src2", 281- [(SPcmpfcc f32:$src1, f32:$src2)]>; 282+ (outs), (ins FPRegs:$rs1, FPRegs:$rs2), 283+ "fcmps $rs1, $rs2", 284+ [(SPcmpfcc f32:$rs1, f32:$rs2)]>; 285 def FCMPD : F3_3c<2, 0b110101, 0b001010010, 286- (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 287- "fcmpd $src1, $src2", 288- [(SPcmpfcc f64:$src1, f64:$src2)]>; 289+ (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2), 290+ "fcmpd $rs1, $rs2", 291+ [(SPcmpfcc f64:$rs1, f64:$rs2)]>; 292 def FCMPQ : F3_3c<2, 0b110101, 0b001010011, 293- (outs), (ins QFPRegs:$src1, QFPRegs:$src2), 294- "fcmpq $src1, $src2", 295- [(SPcmpfcc f128:$src1, f128:$src2)]>, 296+ (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2), 297+ "fcmpq $rs1, $rs2", 298+ [(SPcmpfcc f128:$rs1, f128:$rs2)]>, 299 Requires<[HasHardQuad]>; 300 } 301 302@@ -892,29 +892,29 @@ let Predicates = [HasV9], Constraints = "$f = $rd" 303 // Floating-Point Move Instructions, p. 164 of the V9 manual. 304 let Predicates = [HasV9] in { 305 def FMOVD : F3_3u<2, 0b110100, 0b000000010, 306- (outs DFPRegs:$dst), (ins DFPRegs:$src), 307- "fmovd $src, $dst", []>; 308+ (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 309+ "fmovd $rs2, $rd", []>; 310 def FMOVQ : F3_3u<2, 0b110100, 0b000000011, 311- (outs QFPRegs:$dst), (ins QFPRegs:$src), 312- "fmovq $src, $dst", []>, 313+ (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 314+ "fmovq $rs2, $rd", []>, 315 Requires<[HasHardQuad]>; 316 def FNEGD : F3_3u<2, 0b110100, 0b000000110, 317- (outs DFPRegs:$dst), (ins DFPRegs:$src), 318- "fnegd $src, $dst", 319- [(set f64:$dst, (fneg f64:$src))]>; 320+ (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 321+ "fnegd $rs2, $rd", 322+ [(set f64:$rd, (fneg f64:$rs2))]>; 323 def FNEGQ : F3_3u<2, 0b110100, 0b000000111, 324- (outs QFPRegs:$dst), (ins QFPRegs:$src), 325- "fnegq $src, $dst", 326- [(set f128:$dst, (fneg f128:$src))]>, 327+ (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 328+ "fnegq $rs2, $rd", 329+ [(set f128:$rd, (fneg f128:$rs2))]>, 330 Requires<[HasHardQuad]>; 331 def FABSD : F3_3u<2, 0b110100, 0b000001010, 332- (outs DFPRegs:$dst), (ins DFPRegs:$src), 333- "fabsd $src, $dst", 334- [(set f64:$dst, (fabs f64:$src))]>; 335+ (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 336+ "fabsd $rs2, $rd", 337+ [(set f64:$rd, (fabs f64:$rs2))]>; 338 def FABSQ : F3_3u<2, 0b110100, 0b000001011, 339- (outs QFPRegs:$dst), (ins QFPRegs:$src), 340- "fabsq $src, $dst", 341- [(set f128:$dst, (fabs f128:$src))]>, 342+ (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 343+ "fabsq $rs2, $rd", 344+ [(set f128:$rd, (fabs f128:$rs2))]>, 345 Requires<[HasHardQuad]>; 346 } 347 348Index: lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 349=================================================================== 350--- lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 351+++ lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 352@@ -54,6 +54,8 @@ class SparcAsmParser : public MCTargetAsmParser { 353 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 354 bool ParseDirective(AsmToken DirectiveID); 355 356+ virtual unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, 357+ unsigned Kind); 358 359 // Custom parse functions for Sparc specific operands. 360 OperandMatchResultTy 361@@ -67,8 +69,9 @@ class SparcAsmParser : public MCTargetAsmParser { 362 parseSparcAsmOperand(SparcOperand *&Operand); 363 364 // returns true if Tok is matched to a register and returns register in RegNo. 365- bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo, bool isDFP, 366- bool isQFP); 367+ bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo, 368+ unsigned &RegKind); 369+ 370 bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc); 371 372 public: 373@@ -178,6 +181,16 @@ class SparcOperand : public MCParsedAsmOperand { 374 bool isMEMrr() const { return Kind == k_MemoryReg; } 375 bool isMEMri() const { return Kind == k_MemoryImm; } 376 377+ bool isFloatReg() const { 378+ return (Kind == k_Register && Reg.Kind == rk_FloatReg); 379+ } 380+ 381+ bool isFloatOrDoubleReg() const { 382+ return (Kind == k_Register && (Reg.Kind == rk_FloatReg 383+ || Reg.Kind == rk_DoubleReg)); 384+ } 385+ 386+ 387 StringRef getToken() const { 388 assert(Kind == k_Token && "Invalid access!"); 389 return StringRef(Tok.Data, Tok.Length); 390@@ -280,11 +293,11 @@ class SparcOperand : public MCParsedAsmOperand { 391 } 392 393 static SparcOperand *CreateReg(unsigned RegNum, 394- SparcOperand::RegisterKind Kind, 395+ unsigned Kind, 396 SMLoc S, SMLoc E) { 397 SparcOperand *Op = new SparcOperand(k_Register); 398 Op->Reg.RegNum = RegNum; 399- Op->Reg.Kind = Kind; 400+ Op->Reg.Kind = (SparcOperand::RegisterKind)Kind; 401 Op->StartLoc = S; 402 Op->EndLoc = E; 403 return Op; 404@@ -298,6 +311,40 @@ class SparcOperand : public MCParsedAsmOperand { 405 return Op; 406 } 407 408+ static SparcOperand *MorphToDoubleReg(SparcOperand *Op) { 409+ unsigned Reg = Op->getReg(); 410+ assert(Op->Reg.Kind == rk_FloatReg); 411+ unsigned regIdx = Reg - Sparc::F0; 412+ if (regIdx % 2 || regIdx > 31) 413+ return 0; 414+ Op->Reg.RegNum = DoubleRegs[regIdx / 2]; 415+ Op->Reg.Kind = rk_DoubleReg; 416+ return Op; 417+ } 418+ 419+ static SparcOperand *MorphToQuadReg(SparcOperand *Op) { 420+ unsigned Reg = Op->getReg(); 421+ unsigned regIdx = 0; 422+ switch (Op->Reg.Kind) { 423+ default: assert(0 && "Unexpected register kind!"); 424+ case rk_FloatReg: 425+ regIdx = Reg - Sparc::F0; 426+ if (regIdx % 4 || regIdx > 31) 427+ return 0; 428+ Reg = QuadFPRegs[regIdx / 4]; 429+ break; 430+ case rk_DoubleReg: 431+ regIdx = Reg - Sparc::D0; 432+ if (regIdx % 2 || regIdx > 31) 433+ return 0; 434+ Reg = QuadFPRegs[regIdx / 2]; 435+ break; 436+ } 437+ Op->Reg.RegNum = Reg; 438+ Op->Reg.Kind = rk_QuadReg; 439+ return Op; 440+ } 441+ 442 static SparcOperand *MorphToMEMrr(unsigned Base, SparcOperand *Op) { 443 unsigned offsetReg = Op->getReg(); 444 Op->Kind = k_MemoryReg; 445@@ -383,7 +430,8 @@ ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SM 446 if (getLexer().getKind() != AsmToken::Percent) 447 return false; 448 Parser.Lex(); 449- if (matchRegisterName(Tok, RegNo, false, false)) { 450+ unsigned regKind = SparcOperand::rk_None; 451+ if (matchRegisterName(Tok, RegNo, regKind)) { 452 Parser.Lex(); 453 return false; 454 } 455@@ -537,13 +585,14 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand 456 case AsmToken::Percent: 457 Parser.Lex(); // Eat the '%'. 458 unsigned RegNo; 459- if (matchRegisterName(Parser.getTok(), RegNo, false, false)) { 460+ unsigned RegKind; 461+ if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) { 462 StringRef name = Parser.getTok().getString(); 463 Parser.Lex(); // Eat the identifier token. 464 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 465 switch (RegNo) { 466 default: 467- Op = SparcOperand::CreateReg(RegNo, SparcOperand::rk_None, S, E); 468+ Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); 469 break; 470 case Sparc::Y: 471 Op = SparcOperand::CreateToken("%y", S); 472@@ -593,11 +642,11 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand 473 474 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, 475 unsigned &RegNo, 476- bool isDFP, 477- bool isQFP) 478+ unsigned &RegKind) 479 { 480 int64_t intVal = 0; 481 RegNo = 0; 482+ RegKind = SparcOperand::rk_None; 483 if (Tok.is(AsmToken::Identifier)) { 484 StringRef name = Tok.getString(); 485 486@@ -604,21 +653,25 @@ bool SparcAsmParser::matchRegisterName(const AsmTo 487 // %fp 488 if (name.equals("fp")) { 489 RegNo = Sparc::I6; 490+ RegKind = SparcOperand::rk_IntReg; 491 return true; 492 } 493 // %sp 494 if (name.equals("sp")) { 495 RegNo = Sparc::O6; 496+ RegKind = SparcOperand::rk_IntReg; 497 return true; 498 } 499 500 if (name.equals("y")) { 501 RegNo = Sparc::Y; 502+ RegKind = SparcOperand::rk_Y; 503 return true; 504 } 505 506 if (name.equals("icc")) { 507 RegNo = Sparc::ICC; 508+ RegKind = SparcOperand::rk_CCReg; 509 return true; 510 } 511 512@@ -625,6 +678,7 @@ bool SparcAsmParser::matchRegisterName(const AsmTo 513 if (name.equals("xcc")) { 514 // FIXME:: check 64bit. 515 RegNo = Sparc::ICC; 516+ RegKind = SparcOperand::rk_CCReg; 517 return true; 518 } 519 520@@ -634,6 +688,7 @@ bool SparcAsmParser::matchRegisterName(const AsmTo 521 && intVal < 4) { 522 // FIXME: check 64bit and handle %fcc1 - %fcc3 523 RegNo = Sparc::FCC; 524+ RegKind = SparcOperand::rk_CCReg; 525 return true; 526 } 527 528@@ -642,6 +697,7 @@ bool SparcAsmParser::matchRegisterName(const AsmTo 529 && !name.substr(1).getAsInteger(10, intVal) 530 && intVal < 8) { 531 RegNo = IntRegs[intVal]; 532+ RegKind = SparcOperand::rk_IntReg; 533 return true; 534 } 535 // %o0 - %o7 536@@ -649,6 +705,7 @@ bool SparcAsmParser::matchRegisterName(const AsmTo 537 && !name.substr(1).getAsInteger(10, intVal) 538 && intVal < 8) { 539 RegNo = IntRegs[8 + intVal]; 540+ RegKind = SparcOperand::rk_IntReg; 541 return true; 542 } 543 if (name.substr(0, 1).equals_lower("l") 544@@ -655,6 +712,7 @@ bool SparcAsmParser::matchRegisterName(const AsmTo 545 && !name.substr(1).getAsInteger(10, intVal) 546 && intVal < 8) { 547 RegNo = IntRegs[16 + intVal]; 548+ RegKind = SparcOperand::rk_IntReg; 549 return true; 550 } 551 if (name.substr(0, 1).equals_lower("i") 552@@ -661,18 +719,14 @@ bool SparcAsmParser::matchRegisterName(const AsmTo 553 && !name.substr(1).getAsInteger(10, intVal) 554 && intVal < 8) { 555 RegNo = IntRegs[24 + intVal]; 556+ RegKind = SparcOperand::rk_IntReg; 557 return true; 558 } 559 // %f0 - %f31 560 if (name.substr(0, 1).equals_lower("f") 561 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) { 562- if (isDFP && (intVal%2 == 0)) { 563- RegNo = DoubleRegs[intVal/2]; 564- } else if (isQFP && (intVal%4 == 0)) { 565- RegNo = QuadFPRegs[intVal/4]; 566- } else { 567- RegNo = FloatRegs[intVal]; 568- } 569+ RegNo = FloatRegs[intVal]; 570+ RegKind = SparcOperand::rk_FloatReg; 571 return true; 572 } 573 // %f32 - %f62 574@@ -679,13 +733,9 @@ bool SparcAsmParser::matchRegisterName(const AsmTo 575 if (name.substr(0, 1).equals_lower("f") 576 && !name.substr(1, 2).getAsInteger(10, intVal) 577 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) { 578- if (isDFP) { 579- RegNo = DoubleRegs[16 + intVal/2]; 580- } else if (isQFP && (intVal % 4 == 0)) { 581- RegNo = QuadFPRegs[8 + intVal/4]; 582- } else { 583- return false; 584- } 585+ // FIXME: Check V9 586+ RegNo = DoubleRegs[16 + intVal/2]; 587+ RegKind = SparcOperand::rk_DoubleReg; 588 return true; 589 } 590 591@@ -693,6 +743,7 @@ bool SparcAsmParser::matchRegisterName(const AsmTo 592 if (name.substr(0, 1).equals_lower("r") 593 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) { 594 RegNo = IntRegs[intVal]; 595+ RegKind = SparcOperand::rk_IntReg; 596 return true; 597 } 598 } 599@@ -735,3 +786,26 @@ extern "C" void LLVMInitializeSparcAsmParser() { 600 #define GET_REGISTER_MATCHER 601 #define GET_MATCHER_IMPLEMENTATION 602 #include "SparcGenAsmMatcher.inc" 603+ 604+ 605+ 606+unsigned SparcAsmParser:: 607+validateTargetOperandClass(MCParsedAsmOperand *GOp, 608+ unsigned Kind) 609+{ 610+ SparcOperand *Op = (SparcOperand*)GOp; 611+ if (Op->isFloatOrDoubleReg()) { 612+ switch (Kind) { 613+ default: break; 614+ case MCK_DFPRegs: 615+ if (!Op->isFloatReg() || SparcOperand::MorphToDoubleReg(Op)) 616+ return MCTargetAsmParser::Match_Success; 617+ break; 618+ case MCK_QFPRegs: 619+ if (SparcOperand::MorphToQuadReg(Op)) 620+ return MCTargetAsmParser::Match_Success; 621+ break; 622+ } 623+ } 624+ return Match_InvalidOperand; 625+} 626Index: lib/Target/Sparc/SparcInstr64Bit.td 627=================================================================== 628--- lib/Target/Sparc/SparcInstr64Bit.td 629+++ lib/Target/Sparc/SparcInstr64Bit.td 630@@ -358,31 +358,31 @@ def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFP 631 let Predicates = [Is64Bit] in { 632 633 def FXTOS : F3_3u<2, 0b110100, 0b010000100, 634- (outs FPRegs:$dst), (ins DFPRegs:$src), 635- "fxtos $src, $dst", 636- [(set FPRegs:$dst, (SPxtof DFPRegs:$src))]>; 637+ (outs FPRegs:$rd), (ins DFPRegs:$rs2), 638+ "fxtos $rs2, $rd", 639+ [(set FPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 640 def FXTOD : F3_3u<2, 0b110100, 0b010001000, 641- (outs DFPRegs:$dst), (ins DFPRegs:$src), 642- "fxtod $src, $dst", 643- [(set DFPRegs:$dst, (SPxtof DFPRegs:$src))]>; 644+ (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 645+ "fxtod $rs2, $rd", 646+ [(set DFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 647 def FXTOQ : F3_3u<2, 0b110100, 0b010001100, 648- (outs QFPRegs:$dst), (ins DFPRegs:$src), 649- "fxtoq $src, $dst", 650- [(set QFPRegs:$dst, (SPxtof DFPRegs:$src))]>, 651+ (outs QFPRegs:$rd), (ins DFPRegs:$rs2), 652+ "fxtoq $rs2, $rd", 653+ [(set QFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>, 654 Requires<[HasHardQuad]>; 655 656 def FSTOX : F3_3u<2, 0b110100, 0b010000001, 657- (outs DFPRegs:$dst), (ins FPRegs:$src), 658- "fstox $src, $dst", 659- [(set DFPRegs:$dst, (SPftox FPRegs:$src))]>; 660+ (outs DFPRegs:$rd), (ins FPRegs:$rs2), 661+ "fstox $rs2, $rd", 662+ [(set DFPRegs:$rd, (SPftox FPRegs:$rs2))]>; 663 def FDTOX : F3_3u<2, 0b110100, 0b010000010, 664- (outs DFPRegs:$dst), (ins DFPRegs:$src), 665- "fdtox $src, $dst", 666- [(set DFPRegs:$dst, (SPftox DFPRegs:$src))]>; 667+ (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 668+ "fdtox $rs2, $rd", 669+ [(set DFPRegs:$rd, (SPftox DFPRegs:$rs2))]>; 670 def FQTOX : F3_3u<2, 0b110100, 0b010000011, 671- (outs DFPRegs:$dst), (ins QFPRegs:$src), 672- "fqtox $src, $dst", 673- [(set DFPRegs:$dst, (SPftox QFPRegs:$src))]>, 674+ (outs DFPRegs:$rd), (ins QFPRegs:$rs2), 675+ "fqtox $rs2, $rd", 676+ [(set DFPRegs:$rd, (SPftox QFPRegs:$rs2))]>, 677 Requires<[HasHardQuad]>; 678 679 } // Predicates = [Is64Bit] 680Index: test/MC/Disassembler/Sparc/sparc-fp.txt 681=================================================================== 682--- test/MC/Disassembler/Sparc/sparc-fp.txt 683+++ test/MC/Disassembler/Sparc/sparc-fp.txt 684@@ -0,0 +1,142 @@ 685+# RUN: llvm-mc --disassemble %s -triple=sparc64-linux-gnu | FileCheck %s 686+ 687+ 688+# CHECK: fitos %f0, %f4 689+0x89 0xa0 0x18 0x80 690+ 691+# CHECK: fitod %f0, %f4 692+0x89 0xa0 0x19 0x00 693+ 694+# CHECK: fitoq %f0, %f4 695+0x89 0xa0 0x19 0x80 696+ 697+# CHECK: fstoi %f0, %f4 698+0x89 0xa0 0x1a 0x20 699+ 700+# CHECK: fdtoi %f0, %f4 701+0x89 0xa0 0x1a 0x40 702+ 703+# CHECK: fqtoi %f0, %f4 704+0x89 0xa0 0x1a 0x60 705+ 706+# CHECK: fstod %f0, %f4 707+0x89 0xa0 0x19 0x20 708+# CHECK: fstoq %f0, %f4 709+0x89 0xa0 0x19 0xa0 710+ 711+# CHECK: fdtos %f0, %f4 712+0x89 0xa0 0x18 0xc0 713+ 714+# CHECK: fdtoq %f0, %f4 715+0x89 0xa0 0x19 0xc0 716+ 717+# CHECK: fqtos %f0, %f4 718+0x89 0xa0 0x18 0xe0 719+ 720+# CHECK: fqtod %f0, %f4 721+0x89 0xa0 0x19 0x60 722+ 723+# CHECK: fmovs %f0, %f4 724+0x89 0xa0 0x00 0x20 725+ 726+# CHECK: fmovd %f0, %f4 727+0x89 0xa0 0x00 0x40 728+ 729+# CHECK: fmovq %f0, %f4 730+0x89 0xa0 0x00 0x60 731+ 732+# CHECK: fnegs %f0, %f4 733+0x89 0xa0 0x00 0xa0 734+ 735+# CHECK: fnegd %f0, %f4 736+0x89 0xa0 0x00 0xc0 737+ 738+# CHECK: fnegq %f0, %f4 739+0x89 0xa0 0x00 0xe0 740+ 741+# CHECK: fabss %f0, %f4 742+0x89 0xa0 0x01 0x20 743+ 744+# CHECK: fabsd %f0, %f4 745+0x89 0xa0 0x01 0x40 746+ 747+# CHECK: fabsq %f0, %f4 748+0x89 0xa0 0x01 0x60 749+ 750+# CHECK: fsqrts %f0, %f4 751+0x89 0xa0 0x05 0x20 752+ 753+# CHECK: fsqrtd %f0, %f4 754+0x89 0xa0 0x05 0x40 755+ 756+# CHECK: fsqrtq %f0, %f4 757+0x89 0xa0 0x05 0x60 758+ 759+# CHECK: fadds %f0, %f4, %f8 760+0x91 0xa0 0x08 0x24 761+ 762+# CHECK: faddd %f0, %f4, %f8 763+0x91 0xa0 0x08 0x44 764+ 765+# CHECK: faddq %f0, %f4, %f8 766+0x91 0xa0 0x08 0x64 767+ 768+# CHECK: fsubs %f0, %f4, %f8 769+0x91 0xa0 0x08 0xa4 770+ 771+# CHECK: fsubd %f0, %f4, %f8 772+0x91 0xa0 0x08 0xc4 773+ 774+# CHECK: fsubq %f0, %f4, %f8 775+0x91 0xa0 0x08 0xe4 776+ 777+# CHECK: fmuls %f0, %f4, %f8 778+0x91 0xa0 0x09 0x24 779+ 780+# CHECK: fmuld %f0, %f4, %f8 781+0x91 0xa0 0x09 0x44 782+ 783+# CHECK: fmulq %f0, %f4, %f8 784+0x91 0xa0 0x09 0x64 785+ 786+# CHECK: fsmuld %f0, %f4, %f8 787+0x91 0xa0 0x0d 0x24 788+ 789+# CHECK: fdmulq %f0, %f4, %f8 790+0x91 0xa0 0x0d 0xc4 791+ 792+# CHECK: fdivs %f0, %f4, %f8 793+0x91 0xa0 0x09 0xa4 794+ 795+# CHECK: fdivd %f0, %f4, %f8 796+0x91 0xa0 0x09 0xc4 797+ 798+# CHECK: fdivq %f0, %f4, %f8 799+0x91 0xa0 0x09 0xe4 800+ 801+# CHECK: fcmps %f0, %f4 802+0x81 0xa8 0x0a 0x24 803+ 804+# CHECK: fcmpd %f0, %f4 805+0x81 0xa8 0x0a 0x44 806+ 807+# CHECK: fcmpq %f0, %f4 808+0x81 0xa8 0x0a 0x64 809+ 810+# CHECK: fxtos %f0, %f4 811+0x89 0xa0 0x10 0x80 812+ 813+# CHECK: fxtod %f0, %f4 814+0x89 0xa0 0x11 0x00 815+ 816+# CHECK: fxtoq %f0, %f4 817+0x89 0xa0 0x11 0x80 818+ 819+# CHECK: fstox %f0, %f4 820+0x89 0xa0 0x10 0x20 821+ 822+# CHECK: fdtox %f0, %f4 823+0x89 0xa0 0x10 0x40 824+ 825+# CHECK: fqtox %f0, %f4 826+0x89 0xa0 0x10 0x60 827Index: test/MC/Sparc/sparc-fp-instructions.s 828=================================================================== 829--- test/MC/Sparc/sparc-fp-instructions.s 830+++ test/MC/Sparc/sparc-fp-instructions.s 831@@ -0,0 +1,113 @@ 832+! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s 833+ 834+ ! CHECK: fitos %f0, %f4 ! encoding: [0x89,0xa0,0x18,0x80] 835+ ! CHECK: fitod %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x00] 836+ ! CHECK: fitoq %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x80] 837+ fitos %f0, %f4 838+ fitod %f0, %f4 839+ fitoq %f0, %f4 840+ 841+ ! CHECK: fstoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x20] 842+ ! CHECK: fdtoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x40] 843+ ! CHECK: fqtoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x60] 844+ fstoi %f0, %f4 845+ fdtoi %f0, %f4 846+ fqtoi %f0, %f4 847+ 848+ ! CHECK: fstod %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x20] 849+ ! CHECK: fstoq %f0, %f4 ! encoding: [0x89,0xa0,0x19,0xa0] 850+ fstod %f0, %f4 851+ fstoq %f0, %f4 852+ 853+ ! CHECK: fdtos %f0, %f4 ! encoding: [0x89,0xa0,0x18,0xc0] 854+ ! CHECK: fdtoq %f0, %f4 ! encoding: [0x89,0xa0,0x19,0xc0] 855+ fdtos %f0, %f4 856+ fdtoq %f0, %f4 857+ 858+ ! CHECK: fqtos %f0, %f4 ! encoding: [0x89,0xa0,0x18,0xe0] 859+ ! CHECK: fqtod %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x60] 860+ fqtos %f0, %f4 861+ fqtod %f0, %f4 862+ 863+ ! CHECK: fmovs %f0, %f4 ! encoding: [0x89,0xa0,0x00,0x20] 864+ ! CHECK: fmovd %f0, %f4 ! encoding: [0x89,0xa0,0x00,0x40] 865+ ! CHECK: fmovq %f0, %f4 ! encoding: [0x89,0xa0,0x00,0x60] 866+ fmovs %f0, %f4 867+ fmovd %f0, %f4 868+ fmovq %f0, %f4 869+ 870+ ! CHECK: fnegs %f0, %f4 ! encoding: [0x89,0xa0,0x00,0xa0] 871+ ! CHECK: fnegd %f0, %f4 ! encoding: [0x89,0xa0,0x00,0xc0] 872+ ! CHECK: fnegq %f0, %f4 ! encoding: [0x89,0xa0,0x00,0xe0] 873+ fnegs %f0, %f4 874+ fnegd %f0, %f4 875+ fnegq %f0, %f4 876+ 877+ ! CHECK: fabss %f0, %f4 ! encoding: [0x89,0xa0,0x01,0x20] 878+ ! CHECK: fabsd %f0, %f4 ! encoding: [0x89,0xa0,0x01,0x40] 879+ ! CHECK: fabsq %f0, %f4 ! encoding: [0x89,0xa0,0x01,0x60] 880+ fabss %f0, %f4 881+ fabsd %f0, %f4 882+ fabsq %f0, %f4 883+ 884+ ! CHECK: fsqrts %f0, %f4 ! encoding: [0x89,0xa0,0x05,0x20] 885+ ! CHECK: fsqrtd %f0, %f4 ! encoding: [0x89,0xa0,0x05,0x40] 886+ ! CHECK: fsqrtq %f0, %f4 ! encoding: [0x89,0xa0,0x05,0x60] 887+ fsqrts %f0, %f4 888+ fsqrtd %f0, %f4 889+ fsqrtq %f0, %f4 890+ 891+ ! CHECK: fadds %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x08,0x24] 892+ ! CHECK: faddd %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x08,0x44] 893+ ! CHECK: faddq %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x08,0x64] 894+ fadds %f0, %f4, %f8 895+ faddd %f0, %f4, %f8 896+ faddq %f0, %f4, %f8 897+ 898+ ! CHECK: fsubs %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x08,0xa4] 899+ ! CHECK: fsubd %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x08,0xc4] 900+ ! CHECK: fsubq %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x08,0xe4] 901+ fsubs %f0, %f4, %f8 902+ fsubd %f0, %f4, %f8 903+ fsubq %f0, %f4, %f8 904+ 905+ ! CHECK: fmuls %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x09,0x24] 906+ ! CHECK: fmuld %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x09,0x44] 907+ ! CHECK: fmulq %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x09,0x64] 908+ fmuls %f0, %f4, %f8 909+ fmuld %f0, %f4, %f8 910+ fmulq %f0, %f4, %f8 911+ 912+ ! CHECK: fsmuld %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x0d,0x24] 913+ ! CHECK: fdmulq %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x0d,0xc4] 914+ fsmuld %f0, %f4, %f8 915+ fdmulq %f0, %f4, %f8 916+ 917+ ! CHECK: fdivs %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x09,0xa4] 918+ ! CHECK: fdivd %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x09,0xc4] 919+ ! CHECK: fdivq %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x09,0xe4] 920+ fdivs %f0, %f4, %f8 921+ fdivd %f0, %f4, %f8 922+ fdivq %f0, %f4, %f8 923+ 924+ ! CHECK: fcmps %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x24] 925+ ! CHECK: fcmpd %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x44] 926+ ! CHECK: fcmpq %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x64] 927+ fcmps %f0, %f4 928+ fcmpd %f0, %f4 929+ fcmpq %f0, %f4 930+ 931+ ! CHECK: fxtos %f0, %f4 ! encoding: [0x89,0xa0,0x10,0x80] 932+ ! CHECK: fxtod %f0, %f4 ! encoding: [0x89,0xa0,0x11,0x00] 933+ ! CHECK: fxtoq %f0, %f4 ! encoding: [0x89,0xa0,0x11,0x80] 934+ fxtos %f0, %f4 935+ fxtod %f0, %f4 936+ fxtoq %f0, %f4 937+ 938+ ! CHECK: fstox %f0, %f4 ! encoding: [0x89,0xa0,0x10,0x20] 939+ ! CHECK: fdtox %f0, %f4 ! encoding: [0x89,0xa0,0x10,0x40] 940+ ! CHECK: fqtox %f0, %f4 ! encoding: [0x89,0xa0,0x10,0x60] 941+ fstox %f0, %f4 942+ fdtox %f0, %f4 943+ fqtox %f0, %f4 944+ 945