1//===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "SystemZMCTargetDesc.h" 11#include "InstPrinter/SystemZInstPrinter.h" 12#include "SystemZMCAsmInfo.h" 13#include "llvm/MC/MCCodeGenInfo.h" 14#include "llvm/MC/MCInstrInfo.h" 15#include "llvm/MC/MCStreamer.h" 16#include "llvm/MC/MCSubtargetInfo.h" 17#include "llvm/Support/TargetRegistry.h" 18 19#define GET_INSTRINFO_MC_DESC 20#include "SystemZGenInstrInfo.inc" 21 22#define GET_SUBTARGETINFO_MC_DESC 23#include "SystemZGenSubtargetInfo.inc" 24 25#define GET_REGINFO_MC_DESC 26#include "SystemZGenRegisterInfo.inc" 27 28using namespace llvm; 29 30const unsigned SystemZMC::GR32Regs[16] = { 31 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, 32 SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, 33 SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, 34 SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L 35}; 36 37const unsigned SystemZMC::GRH32Regs[16] = { 38 SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, 39 SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H, 40 SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H, 41 SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H 42}; 43 44const unsigned SystemZMC::GR64Regs[16] = { 45 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, 46 SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, 47 SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, 48 SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D 49}; 50 51const unsigned SystemZMC::GR128Regs[16] = { 52 SystemZ::R0Q, 0, SystemZ::R2Q, 0, 53 SystemZ::R4Q, 0, SystemZ::R6Q, 0, 54 SystemZ::R8Q, 0, SystemZ::R10Q, 0, 55 SystemZ::R12Q, 0, SystemZ::R14Q, 0 56}; 57 58const unsigned SystemZMC::FP32Regs[16] = { 59 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, 60 SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, 61 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, 62 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S 63}; 64 65const unsigned SystemZMC::FP64Regs[16] = { 66 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, 67 SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, 68 SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, 69 SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D 70}; 71 72const unsigned SystemZMC::FP128Regs[16] = { 73 SystemZ::F0Q, SystemZ::F1Q, 0, 0, 74 SystemZ::F4Q, SystemZ::F5Q, 0, 0, 75 SystemZ::F8Q, SystemZ::F9Q, 0, 0, 76 SystemZ::F12Q, SystemZ::F13Q, 0, 0 77}; 78 79unsigned SystemZMC::getFirstReg(unsigned Reg) { 80 static unsigned Map[SystemZ::NUM_TARGET_REGS]; 81 static bool Initialized = false; 82 if (!Initialized) { 83 for (unsigned I = 0; I < 16; ++I) { 84 Map[GR32Regs[I]] = I; 85 Map[GRH32Regs[I]] = I; 86 Map[GR64Regs[I]] = I; 87 Map[GR128Regs[I]] = I; 88 Map[FP32Regs[I]] = I; 89 Map[FP64Regs[I]] = I; 90 Map[FP128Regs[I]] = I; 91 } 92 } 93 assert(Reg < SystemZ::NUM_TARGET_REGS); 94 return Map[Reg]; 95} 96 97static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI, 98 StringRef TT) { 99 MCAsmInfo *MAI = new SystemZMCAsmInfo(TT); 100 MCCFIInstruction Inst = 101 MCCFIInstruction::createDefCfa(0, MRI.getDwarfRegNum(SystemZ::R15D, true), 102 SystemZMC::CFAOffsetFromInitialSP); 103 MAI->addInitialFrameState(Inst); 104 return MAI; 105} 106 107static MCInstrInfo *createSystemZMCInstrInfo() { 108 MCInstrInfo *X = new MCInstrInfo(); 109 InitSystemZMCInstrInfo(X); 110 return X; 111} 112 113static MCRegisterInfo *createSystemZMCRegisterInfo(StringRef TT) { 114 MCRegisterInfo *X = new MCRegisterInfo(); 115 InitSystemZMCRegisterInfo(X, SystemZ::R14D); 116 return X; 117} 118 119static MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, 120 StringRef CPU, 121 StringRef FS) { 122 MCSubtargetInfo *X = new MCSubtargetInfo(); 123 InitSystemZMCSubtargetInfo(X, TT, CPU, FS); 124 return X; 125} 126 127static MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM, 128 CodeModel::Model CM, 129 CodeGenOpt::Level OL) { 130 MCCodeGenInfo *X = new MCCodeGenInfo(); 131 132 // Static code is suitable for use in a dynamic executable; there is no 133 // separate DynamicNoPIC model. 134 if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC) 135 RM = Reloc::Static; 136 137 // For SystemZ we define the models as follows: 138 // 139 // Small: BRASL can call any function and will use a stub if necessary. 140 // Locally-binding symbols will always be in range of LARL. 141 // 142 // Medium: BRASL can call any function and will use a stub if necessary. 143 // GOT slots and locally-defined text will always be in range 144 // of LARL, but other symbols might not be. 145 // 146 // Large: Equivalent to Medium for now. 147 // 148 // Kernel: Equivalent to Medium for now. 149 // 150 // This means that any PIC module smaller than 4GB meets the 151 // requirements of Small, so Small seems like the best default there. 152 // 153 // All symbols bind locally in a non-PIC module, so the choice is less 154 // obvious. There are two cases: 155 // 156 // - When creating an executable, PLTs and copy relocations allow 157 // us to treat external symbols as part of the executable. 158 // Any executable smaller than 4GB meets the requirements of Small, 159 // so that seems like the best default. 160 // 161 // - When creating JIT code, stubs will be in range of BRASL if the 162 // image is less than 4GB in size. GOT entries will likewise be 163 // in range of LARL. However, the JIT environment has no equivalent 164 // of copy relocs, so locally-binding data symbols might not be in 165 // the range of LARL. We need the Medium model in that case. 166 if (CM == CodeModel::Default) 167 CM = CodeModel::Small; 168 else if (CM == CodeModel::JITDefault) 169 CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; 170 X->InitMCCodeGenInfo(RM, CM, OL); 171 return X; 172} 173 174static MCInstPrinter *createSystemZMCInstPrinter(const Target &T, 175 unsigned SyntaxVariant, 176 const MCAsmInfo &MAI, 177 const MCInstrInfo &MII, 178 const MCRegisterInfo &MRI, 179 const MCSubtargetInfo &STI) { 180 return new SystemZInstPrinter(MAI, MII, MRI); 181} 182 183static MCStreamer *createSystemZMCObjectStreamer(const Target &T, StringRef TT, 184 MCContext &Ctx, 185 MCAsmBackend &MAB, 186 raw_ostream &OS, 187 MCCodeEmitter *Emitter, 188 bool RelaxAll, 189 bool NoExecStack) { 190 return createELFStreamer(Ctx, 0, MAB, OS, Emitter, RelaxAll, NoExecStack); 191} 192 193extern "C" void LLVMInitializeSystemZTargetMC() { 194 // Register the MCAsmInfo. 195 TargetRegistry::RegisterMCAsmInfo(TheSystemZTarget, 196 createSystemZMCAsmInfo); 197 198 // Register the MCCodeGenInfo. 199 TargetRegistry::RegisterMCCodeGenInfo(TheSystemZTarget, 200 createSystemZMCCodeGenInfo); 201 202 // Register the MCCodeEmitter. 203 TargetRegistry::RegisterMCCodeEmitter(TheSystemZTarget, 204 createSystemZMCCodeEmitter); 205 206 // Register the MCInstrInfo. 207 TargetRegistry::RegisterMCInstrInfo(TheSystemZTarget, 208 createSystemZMCInstrInfo); 209 210 // Register the MCRegisterInfo. 211 TargetRegistry::RegisterMCRegInfo(TheSystemZTarget, 212 createSystemZMCRegisterInfo); 213 214 // Register the MCSubtargetInfo. 215 TargetRegistry::RegisterMCSubtargetInfo(TheSystemZTarget, 216 createSystemZMCSubtargetInfo); 217 218 // Register the MCAsmBackend. 219 TargetRegistry::RegisterMCAsmBackend(TheSystemZTarget, 220 createSystemZMCAsmBackend); 221 222 // Register the MCInstPrinter. 223 TargetRegistry::RegisterMCInstPrinter(TheSystemZTarget, 224 createSystemZMCInstPrinter); 225 226 // Register the MCObjectStreamer; 227 TargetRegistry::RegisterMCObjectStreamer(TheSystemZTarget, 228 createSystemZMCObjectStreamer); 229} 230