1//===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// SPARC Subtarget features.
21//
22
23def FeatureV9
24  : SubtargetFeature<"v9", "IsV9", "true",
25                     "Enable SPARC-V9 instructions">;
26def FeatureV8Deprecated
27  : SubtargetFeature<"deprecated-v8", "V8DeprecatedInsts", "true",
28                     "Enable deprecated V8 instructions in V9 mode">;
29def FeatureVIS
30  : SubtargetFeature<"vis", "IsVIS", "true",
31                     "Enable UltraSPARC Visual Instruction Set extensions">;
32
33def FeatureHardQuad
34  : SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
35                     "Enable quad-word floating point instructions">;
36
37def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
38                               "Use the popc (population count) instruction">;
39
40//===----------------------------------------------------------------------===//
41// Register File, Calling Conv, Instruction Descriptions
42//===----------------------------------------------------------------------===//
43
44include "SparcRegisterInfo.td"
45include "SparcCallingConv.td"
46include "SparcInstrInfo.td"
47
48def SparcInstrInfo : InstrInfo;
49
50def SparcAsmParser : AsmParser {
51  bit ShouldEmitMatchRegisterName = 0;
52}
53
54//===----------------------------------------------------------------------===//
55// SPARC processors supported.
56//===----------------------------------------------------------------------===//
57
58class Proc<string Name, list<SubtargetFeature> Features>
59 : Processor<Name, NoItineraries, Features>;
60
61def : Proc<"generic",         []>;
62def : Proc<"v7",              []>;
63def : Proc<"v8",              []>;
64def : Proc<"supersparc",      []>;
65def : Proc<"sparclite",       []>;
66def : Proc<"f934",            []>;
67def : Proc<"hypersparc",      []>;
68def : Proc<"sparclite86x",    []>;
69def : Proc<"sparclet",        []>;
70def : Proc<"tsc701",          []>;
71def : Proc<"v9",              [FeatureV9]>;
72def : Proc<"ultrasparc",      [FeatureV9, FeatureV8Deprecated]>;
73def : Proc<"ultrasparc3",     [FeatureV9, FeatureV8Deprecated]>;
74def : Proc<"niagara",         [FeatureV9, FeatureV8Deprecated]>;
75def : Proc<"niagara2",        [FeatureV9, FeatureV8Deprecated, UsePopc]>;
76def : Proc<"niagara3",        [FeatureV9, FeatureV8Deprecated, UsePopc]>;
77def : Proc<"niagara4",        [FeatureV9, FeatureV8Deprecated, UsePopc]>;
78
79def SparcAsmWriter : AsmWriter {
80  string AsmWriterClassName  = "InstPrinter";
81  bit isMCAsmWriter = 1;
82}
83
84//===----------------------------------------------------------------------===//
85// Declare the target which we are implementing
86//===----------------------------------------------------------------------===//
87
88def Sparc : Target {
89  // Pull in Instruction Info:
90  let InstructionSet = SparcInstrInfo;
91  let AssemblyParsers  = [SparcAsmParser];
92
93  let AssemblyWriters = [SparcAsmWriter];
94}
95