MachineInstr.cpp revision 224145
1250323Sdteske//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2250323Sdteske// 3294864Sdteske// The LLVM Compiler Infrastructure 4252980Sdteske// 5250323Sdteske// This file is distributed under the University of Illinois Open Source 6250323Sdteske// License. See LICENSE.TXT for details. 7250323Sdteske// 8250323Sdteske//===----------------------------------------------------------------------===// 9250323Sdteske// 10250323Sdteske// Methods common to all machine instructions. 11250323Sdteske// 12250323Sdteske//===----------------------------------------------------------------------===// 13250323Sdteske 14250323Sdteske#include "llvm/CodeGen/MachineInstr.h" 15250323Sdteske#include "llvm/Constants.h" 16252987Sdteske#include "llvm/Function.h" 17250323Sdteske#include "llvm/InlineAsm.h" 18250323Sdteske#include "llvm/LLVMContext.h" 19250323Sdteske#include "llvm/Metadata.h" 20252987Sdteske#include "llvm/Module.h" 21250323Sdteske#include "llvm/Type.h" 22250323Sdteske#include "llvm/Value.h" 23250323Sdteske#include "llvm/Assembly/Writer.h" 24250323Sdteske#include "llvm/CodeGen/MachineConstantPool.h" 25250323Sdteske#include "llvm/CodeGen/MachineFunction.h" 26250323Sdteske#include "llvm/CodeGen/MachineMemOperand.h" 27250323Sdteske#include "llvm/CodeGen/MachineModuleInfo.h" 28250323Sdteske#include "llvm/CodeGen/MachineRegisterInfo.h" 29250323Sdteske#include "llvm/CodeGen/PseudoSourceValue.h" 30250323Sdteske#include "llvm/MC/MCInstrDesc.h" 31250323Sdteske#include "llvm/MC/MCSymbol.h" 32250323Sdteske#include "llvm/Target/TargetMachine.h" 33250323Sdteske#include "llvm/Target/TargetInstrInfo.h" 34250323Sdteske#include "llvm/Target/TargetRegisterInfo.h" 35250323Sdteske#include "llvm/Analysis/AliasAnalysis.h" 36268999Sdteske#include "llvm/Analysis/DebugInfo.h" 37250323Sdteske#include "llvm/Support/Debug.h" 38250323Sdteske#include "llvm/Support/ErrorHandling.h" 39250323Sdteske#include "llvm/Support/LeakDetector.h" 40250323Sdteske#include "llvm/Support/MathExtras.h" 41250323Sdteske#include "llvm/Support/raw_ostream.h" 42250323Sdteske#include "llvm/ADT/FoldingSet.h" 43250323Sdteskeusing namespace llvm; 44250323Sdteske 45250323Sdteske//===----------------------------------------------------------------------===// 46250323Sdteske// MachineOperand Implementation 47257795Sdteske//===----------------------------------------------------------------------===// 48257795Sdteske 49257795Sdteske/// AddRegOperandToRegInfo - Add this register operand to the specified 50294864Sdteske/// MachineRegisterInfo. If it is null, then the next/prev fields should be 51257795Sdteske/// explicitly nulled out. 52257795Sdteskevoid MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { 53257795Sdteske assert(isReg() && "Can only add reg operand to use lists"); 54257795Sdteske 55257795Sdteske // If the reginfo pointer is null, just explicitly null out or next/prev 56257795Sdteske // pointers, to ensure they are not garbage. 57250323Sdteske if (RegInfo == 0) { 58250323Sdteske Contents.Reg.Prev = 0; 59257795Sdteske Contents.Reg.Next = 0; 60250323Sdteske return; 61257795Sdteske } 62257795Sdteske 63257795Sdteske // Otherwise, add this operand to the head of the registers use/def list. 64250323Sdteske MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg()); 65250323Sdteske 66250323Sdteske // For SSA values, we prefer to keep the definition at the start of the list. 67250323Sdteske // we do this by skipping over the definition if it is at the head of the 68250323Sdteske // list. 69258265Sdteske if (*Head && (*Head)->isDef()) 70268999Sdteske Head = &(*Head)->Contents.Reg.Next; 71250323Sdteske 72250323Sdteske Contents.Reg.Next = *Head; 73250323Sdteske if (Contents.Reg.Next) { 74250323Sdteske assert(getReg() == Contents.Reg.Next->getReg() && 75250323Sdteske "Different regs on the same list!"); 76250323Sdteske Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next; 77268999Sdteske } 78268999Sdteske 79268999Sdteske Contents.Reg.Prev = Head; 80250323Sdteske *Head = this; 81264840Sdteske} 82250323Sdteske 83257795Sdteske/// RemoveRegOperandFromRegInfo - Remove this register operand from the 84257795Sdteske/// MachineRegisterInfo it is linked with. 85257795Sdteskevoid MachineOperand::RemoveRegOperandFromRegInfo() { 86257795Sdteske assert(isOnRegUseList() && "Reg operand is not on a use list"); 87257795Sdteske // Unlink this from the doubly linked list of operands. 88257795Sdteske MachineOperand *NextOp = Contents.Reg.Next; 89257795Sdteske *Contents.Reg.Prev = NextOp; 90257795Sdteske if (NextOp) { 91257795Sdteske assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!"); 92258267Sdteske NextOp->Contents.Reg.Prev = Contents.Reg.Prev; 93258267Sdteske } 94258267Sdteske Contents.Reg.Prev = 0; 95258267Sdteske Contents.Reg.Next = 0; 96258267Sdteske} 97258267Sdteske 98258267Sdteskevoid MachineOperand::setReg(unsigned Reg) { 99258267Sdteske if (getReg() == Reg) return; // No change. 100258267Sdteske 101258267Sdteske // Otherwise, we have to change the register. If this operand is embedded 102258267Sdteske // into a machine function, we need to update the old and new register's 103258267Sdteske // use/def lists. 104258267Sdteske if (MachineInstr *MI = getParent()) 105259427Sgjb if (MachineBasicBlock *MBB = MI->getParent()) 106259427Sgjb if (MachineFunction *MF = MBB->getParent()) { 107259427Sgjb RemoveRegOperandFromRegInfo(); 108258267Sdteske SmallContents.RegNo = Reg; 109258267Sdteske AddRegOperandToRegInfo(&MF->getRegInfo()); 110257795Sdteske return; 111257795Sdteske } 112268999Sdteske 113268999Sdteske // Otherwise, just change the register, no problem. :) 114268999Sdteske SmallContents.RegNo = Reg; 115268999Sdteske} 116257795Sdteske 117264840Sdteskevoid MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, 118250323Sdteske const TargetRegisterInfo &TRI) { 119250323Sdteske assert(TargetRegisterInfo::isVirtualRegister(Reg)); 120257795Sdteske if (SubIdx && getSubReg()) 121257795Sdteske SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); 122257795Sdteske setReg(Reg); 123257795Sdteske if (SubIdx) 124257795Sdteske setSubReg(SubIdx); 125257795Sdteske} 126298884Spfg 127257795Sdteskevoid MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { 128257795Sdteske assert(TargetRegisterInfo::isPhysicalRegister(Reg)); 129257795Sdteske if (getSubReg()) { 130257795Sdteske Reg = TRI.getSubReg(Reg, getSubReg()); 131257795Sdteske // Note that getSubReg() may return 0 if the sub-register doesn't exist. 132257795Sdteske // That won't happen in legal code. 133264840Sdteske setSubReg(0); 134257795Sdteske } 135257795Sdteske setReg(Reg); 136257795Sdteske} 137257795Sdteske 138298884Spfg/// ChangeToImmediate - Replace this operand with a new immediate operand of 139257795Sdteske/// the specified value. If an operand is known to be an immediate already, 140257795Sdteske/// the setImm method should be used. 141257795Sdteskevoid MachineOperand::ChangeToImmediate(int64_t ImmVal) { 142257795Sdteske // If this operand is currently a register operand, and if this is in a 143257795Sdteske // function, deregister the operand from the register's use/def list. 144257795Sdteske if (isReg() && getParent() && getParent()->getParent() && 145257795Sdteske getParent()->getParent()->getParent()) 146257795Sdteske RemoveRegOperandFromRegInfo(); 147257795Sdteske 148257795Sdteske OpKind = MO_Immediate; 149257795Sdteske Contents.ImmVal = ImmVal; 150257795Sdteske} 151257795Sdteske 152257795Sdteske/// ChangeToRegister - Replace this operand with a new register operand of 153257795Sdteske/// the specified value. If an operand is known to be an register already, 154257795Sdteske/// the setReg method should be used. 155257795Sdteskevoid MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 156257795Sdteske bool isKill, bool isDead, bool isUndef, 157257795Sdteske bool isDebug) { 158257795Sdteske // If this operand is already a register operand, use setReg to update the 159257795Sdteske // register's use/def lists. 160257795Sdteske if (isReg()) { 161257795Sdteske assert(!isEarlyClobber()); 162257795Sdteske setReg(Reg); 163257795Sdteske } else { 164257795Sdteske // Otherwise, change this to a register and set the reg#. 165257795Sdteske OpKind = MO_Register; 166257795Sdteske SmallContents.RegNo = Reg; 167257795Sdteske 168257795Sdteske // If this operand is embedded in a function, add the operand to the 169257795Sdteske // register's use/def list. 170257795Sdteske if (MachineInstr *MI = getParent()) 171257795Sdteske if (MachineBasicBlock *MBB = MI->getParent()) 172257795Sdteske if (MachineFunction *MF = MBB->getParent()) 173257795Sdteske AddRegOperandToRegInfo(&MF->getRegInfo()); 174257795Sdteske } 175257795Sdteske 176257795Sdteske IsDef = isDef; 177257795Sdteske IsImp = isImp; 178257795Sdteske IsKill = isKill; 179257795Sdteske IsDead = isDead; 180294866Sdteske IsUndef = isUndef; 181294866Sdteske IsEarlyClobber = false; 182294866Sdteske IsDebug = isDebug; 183294866Sdteske SubReg = 0; 184294866Sdteske} 185250323Sdteske 186257795Sdteske/// isIdenticalTo - Return true if this operand is identical to the specified 187298884Spfg/// operand. 188257795Sdteskebool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 189257795Sdteske if (getType() != Other.getType() || 190257795Sdteske getTargetFlags() != Other.getTargetFlags()) 191259054Sdteske return false; 192259054Sdteske 193259054Sdteske switch (getType()) { 194259054Sdteske default: llvm_unreachable("Unrecognized operand type"); 195257795Sdteske case MachineOperand::MO_Register: 196257795Sdteske return getReg() == Other.getReg() && isDef() == Other.isDef() && 197257795Sdteske getSubReg() == Other.getSubReg(); 198257795Sdteske case MachineOperand::MO_Immediate: 199257795Sdteske return getImm() == Other.getImm(); 200257795Sdteske case MachineOperand::MO_CImmediate: 201267680Sdteske return getCImm() == Other.getCImm(); 202259054Sdteske case MachineOperand::MO_FPImmediate: 203257795Sdteske return getFPImm() == Other.getFPImm(); 204259054Sdteske case MachineOperand::MO_MachineBasicBlock: 205259054Sdteske return getMBB() == Other.getMBB(); 206257795Sdteske case MachineOperand::MO_FrameIndex: 207257795Sdteske return getIndex() == Other.getIndex(); 208250323Sdteske case MachineOperand::MO_ConstantPoolIndex: 209257795Sdteske return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 210250323Sdteske case MachineOperand::MO_JumpTableIndex: 211250323Sdteske return getIndex() == Other.getIndex(); 212250323Sdteske case MachineOperand::MO_GlobalAddress: 213250323Sdteske return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 214250323Sdteske case MachineOperand::MO_ExternalSymbol: 215250323Sdteske return !strcmp(getSymbolName(), Other.getSymbolName()) && 216250323Sdteske getOffset() == Other.getOffset(); 217250323Sdteske case MachineOperand::MO_BlockAddress: 218250323Sdteske return getBlockAddress() == Other.getBlockAddress(); 219250323Sdteske case MachineOperand::MO_MCSymbol: 220250323Sdteske return getMCSymbol() == Other.getMCSymbol(); 221250323Sdteske case MachineOperand::MO_Metadata: 222250323Sdteske return getMetadata() == Other.getMetadata(); 223250323Sdteske } 224250323Sdteske} 225250323Sdteske 226250323Sdteske/// print - Print the specified machine operand. 227250323Sdteske/// 228250323Sdteskevoid MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 229250323Sdteske // If the instruction is embedded into a basic block, we can find the 230250323Sdteske // target info for the instruction. 231250323Sdteske if (!TM) 232250323Sdteske if (const MachineInstr *MI = getParent()) 233250323Sdteske if (const MachineBasicBlock *MBB = MI->getParent()) 234250323Sdteske if (const MachineFunction *MF = MBB->getParent()) 235250323Sdteske TM = &MF->getTarget(); 236250323Sdteske const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0; 237250323Sdteske 238250323Sdteske switch (getType()) { 239250323Sdteske case MachineOperand::MO_Register: 240250323Sdteske OS << PrintReg(getReg(), TRI, getSubReg()); 241250538Sdteske 242250323Sdteske if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || 243250323Sdteske isEarlyClobber()) { 244273068Sdteske OS << '<'; 245250323Sdteske bool NeedComma = false; 246273067Sdteske if (isDef()) { 247273067Sdteske if (NeedComma) OS << ','; 248250323Sdteske if (isEarlyClobber()) 249273067Sdteske OS << "earlyclobber,"; 250250323Sdteske if (isImplicit()) 251250323Sdteske OS << "imp-"; 252250323Sdteske OS << "def"; 253250323Sdteske NeedComma = true; 254250323Sdteske } else if (isImplicit()) { 255250323Sdteske OS << "imp-use"; 256250323Sdteske NeedComma = true; 257250323Sdteske } 258250323Sdteske 259250323Sdteske if (isKill() || isDead() || isUndef()) { 260250323Sdteske if (NeedComma) OS << ','; 261250323Sdteske if (isKill()) OS << "kill"; 262250323Sdteske if (isDead()) OS << "dead"; 263250323Sdteske if (isUndef()) { 264250323Sdteske if (isKill() || isDead()) 265250323Sdteske OS << ','; 266250323Sdteske OS << "undef"; 267250323Sdteske } 268250323Sdteske } 269250323Sdteske OS << '>'; 270250323Sdteske } 271250323Sdteske break; 272250538Sdteske case MachineOperand::MO_Immediate: 273250323Sdteske OS << getImm(); 274250323Sdteske break; 275250323Sdteske case MachineOperand::MO_CImmediate: 276250323Sdteske getCImm()->getValue().print(OS, false); 277250323Sdteske break; 278250538Sdteske case MachineOperand::MO_FPImmediate: 279250410Sdteske if (getFPImm()->getType()->isFloatTy()) 280250323Sdteske OS << getFPImm()->getValueAPF().convertToFloat(); 281250323Sdteske else 282250323Sdteske OS << getFPImm()->getValueAPF().convertToDouble(); 283250410Sdteske break; 284250323Sdteske case MachineOperand::MO_MachineBasicBlock: 285250323Sdteske OS << "<BB#" << getMBB()->getNumber() << ">"; 286250323Sdteske break; 287250323Sdteske case MachineOperand::MO_FrameIndex: 288250323Sdteske OS << "<fi#" << getIndex() << '>'; 289250323Sdteske break; 290250323Sdteske case MachineOperand::MO_ConstantPoolIndex: 291250323Sdteske OS << "<cp#" << getIndex(); 292250323Sdteske if (getOffset()) OS << "+" << getOffset(); 293250410Sdteske OS << '>'; 294250323Sdteske break; 295273068Sdteske case MachineOperand::MO_JumpTableIndex: 296250323Sdteske OS << "<jt#" << getIndex() << '>'; 297250323Sdteske break; 298250323Sdteske case MachineOperand::MO_GlobalAddress: 299250323Sdteske OS << "<ga:"; 300250323Sdteske WriteAsOperand(OS, getGlobal(), /*PrintType=*/false); 301250323Sdteske if (getOffset()) OS << "+" << getOffset(); 302250323Sdteske OS << '>'; 303250323Sdteske break; 304250323Sdteske case MachineOperand::MO_ExternalSymbol: 305250323Sdteske OS << "<es:" << getSymbolName(); 306250323Sdteske if (getOffset()) OS << "+" << getOffset(); 307250323Sdteske OS << '>'; 308250410Sdteske break; 309250323Sdteske case MachineOperand::MO_BlockAddress: 310250323Sdteske OS << '<'; 311250323Sdteske WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false); 312250323Sdteske OS << '>'; 313250323Sdteske break; 314250323Sdteske case MachineOperand::MO_Metadata: 315250323Sdteske OS << '<'; 316250323Sdteske WriteAsOperand(OS, getMetadata(), /*PrintType=*/false); 317250323Sdteske OS << '>'; 318250323Sdteske break; 319250323Sdteske case MachineOperand::MO_MCSymbol: 320250323Sdteske OS << "<MCSym=" << *getMCSymbol() << '>'; 321250323Sdteske break; 322250323Sdteske default: 323250323Sdteske llvm_unreachable("Unrecognized operand type"); 324250323Sdteske } 325250323Sdteske 326250323Sdteske if (unsigned TF = getTargetFlags()) 327250323Sdteske OS << "[TF=" << TF << ']'; 328250323Sdteske} 329250323Sdteske 330250323Sdteske//===----------------------------------------------------------------------===// 331250323Sdteske// MachineMemOperand Implementation 332294866Sdteske//===----------------------------------------------------------------------===// 333294866Sdteske 334294866Sdteske/// getAddrSpace - Return the LLVM IR address space number that this pointer 335250323Sdteske/// points into. 336250323Sdteskeunsigned MachinePointerInfo::getAddrSpace() const { 337250323Sdteske if (V == 0) return 0; 338250323Sdteske return cast<PointerType>(V->getType())->getAddressSpace(); 339252738Sdteske} 340252738Sdteske 341250323Sdteske/// getConstantPool - Return a MachinePointerInfo record that refers to the 342250323Sdteske/// constant pool. 343250323SdteskeMachinePointerInfo MachinePointerInfo::getConstantPool() { 344250323Sdteske return MachinePointerInfo(PseudoSourceValue::getConstantPool()); 345250323Sdteske} 346250323Sdteske 347250323Sdteske/// getFixedStack - Return a MachinePointerInfo record that refers to the 348250323Sdteske/// the specified FrameIndex. 349250323SdteskeMachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) { 350252738Sdteske return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset); 351250323Sdteske} 352250323Sdteske 353250323SdteskeMachinePointerInfo MachinePointerInfo::getJumpTable() { 354250323Sdteske return MachinePointerInfo(PseudoSourceValue::getJumpTable()); 355250323Sdteske} 356250323Sdteske 357250538SdteskeMachinePointerInfo MachinePointerInfo::getGOT() { 358250538Sdteske return MachinePointerInfo(PseudoSourceValue::getGOT()); 359250323Sdteske} 360250323Sdteske 361250323SdteskeMachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) { 362250538Sdteske return MachinePointerInfo(PseudoSourceValue::getStack(), Offset); 363250323Sdteske} 364250323Sdteske 365250323SdteskeMachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f, 366250323Sdteske uint64_t s, unsigned int a, 367250323Sdteske const MDNode *TBAAInfo) 368250323Sdteske : PtrInfo(ptrinfo), Size(s), 369250323Sdteske Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)), 370250323Sdteske TBAAInfo(TBAAInfo) { 371250323Sdteske assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) && 372250323Sdteske "invalid pointer value"); 373250323Sdteske assert(getBaseAlignment() == a && "Alignment is not a power of 2!"); 374252745Sdteske assert((isLoad() || isStore()) && "Not a load/store!"); 375252745Sdteske} 376252753Sdteske 377252745Sdteske/// Profile - Gather unique data for the object. 378252745Sdteske/// 379252745Sdteskevoid MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 380252745Sdteske ID.AddInteger(getOffset()); 381252745Sdteske ID.AddInteger(Size); 382252745Sdteske ID.AddPointer(getValue()); 383252745Sdteske ID.AddInteger(Flags); 384252745Sdteske} 385252745Sdteske 386252745Sdteskevoid MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { 387252745Sdteske // The Value and Offset may differ due to CSE. But the flags and size 388252745Sdteske // should be the same. 389252745Sdteske assert(MMO->getFlags() == getFlags() && "Flags mismatch!"); 390252745Sdteske assert(MMO->getSize() == getSize() && "Size mismatch!"); 391252745Sdteske 392252745Sdteske if (MMO->getBaseAlignment() >= getBaseAlignment()) { 393252745Sdteske // Update the alignment value. 394252745Sdteske Flags = (Flags & ((1 << MOMaxBits) - 1)) | 395252745Sdteske ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits); 396252745Sdteske // Also update the base and offset, because the new alignment may 397252745Sdteske // not be applicable with the old ones. 398252745Sdteske PtrInfo = MMO->PtrInfo; 399252745Sdteske } 400252745Sdteske} 401252745Sdteske 402252745Sdteske/// getAlignment - Return the minimum known alignment in bytes of the 403252745Sdteske/// actual memory reference. 404252745Sdteskeuint64_t MachineMemOperand::getAlignment() const { 405252745Sdteske return MinAlign(getBaseAlignment(), getOffset()); 406252745Sdteske} 407252745Sdteske 408252745Sdteskeraw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) { 409252745Sdteske assert((MMO.isLoad() || MMO.isStore()) && 410252745Sdteske "SV has to be a load, store or both."); 411252745Sdteske 412250323Sdteske if (MMO.isVolatile()) 413250323Sdteske OS << "Volatile "; 414250323Sdteske 415250323Sdteske if (MMO.isLoad()) 416250323Sdteske OS << "LD"; 417 if (MMO.isStore()) 418 OS << "ST"; 419 OS << MMO.getSize(); 420 421 // Print the address information. 422 OS << "["; 423 if (!MMO.getValue()) 424 OS << "<unknown>"; 425 else 426 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false); 427 428 // If the alignment of the memory reference itself differs from the alignment 429 // of the base pointer, print the base alignment explicitly, next to the base 430 // pointer. 431 if (MMO.getBaseAlignment() != MMO.getAlignment()) 432 OS << "(align=" << MMO.getBaseAlignment() << ")"; 433 434 if (MMO.getOffset() != 0) 435 OS << "+" << MMO.getOffset(); 436 OS << "]"; 437 438 // Print the alignment of the reference. 439 if (MMO.getBaseAlignment() != MMO.getAlignment() || 440 MMO.getBaseAlignment() != MMO.getSize()) 441 OS << "(align=" << MMO.getAlignment() << ")"; 442 443 // Print TBAA info. 444 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) { 445 OS << "(tbaa="; 446 if (TBAAInfo->getNumOperands() > 0) 447 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false); 448 else 449 OS << "<unknown>"; 450 OS << ")"; 451 } 452 453 // Print nontemporal info. 454 if (MMO.isNonTemporal()) 455 OS << "(nontemporal)"; 456 457 return OS; 458} 459 460//===----------------------------------------------------------------------===// 461// MachineInstr Implementation 462//===----------------------------------------------------------------------===// 463 464/// MachineInstr ctor - This constructor creates a dummy MachineInstr with 465/// MCID NULL and no operands. 466MachineInstr::MachineInstr() 467 : MCID(0), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), 468 MemRefs(0), MemRefsEnd(0), 469 Parent(0) { 470 // Make sure that we get added to a machine basicblock 471 LeakDetector::addGarbageObject(this); 472} 473 474void MachineInstr::addImplicitDefUseOperands() { 475 if (MCID->ImplicitDefs) 476 for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs) 477 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 478 if (MCID->ImplicitUses) 479 for (const unsigned *ImpUses = MCID->ImplicitUses; *ImpUses; ++ImpUses) 480 addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 481} 482 483/// MachineInstr ctor - This constructor creates a MachineInstr and adds the 484/// implicit operands. It reserves space for the number of operands specified by 485/// the MCInstrDesc. 486MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp) 487 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), 488 MemRefs(0), MemRefsEnd(0), Parent(0) { 489 if (!NoImp) 490 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 491 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 492 if (!NoImp) 493 addImplicitDefUseOperands(); 494 // Make sure that we get added to a machine basicblock 495 LeakDetector::addGarbageObject(this); 496} 497 498/// MachineInstr ctor - As above, but with a DebugLoc. 499MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl, 500 bool NoImp) 501 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), 502 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) { 503 if (!NoImp) 504 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 505 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 506 if (!NoImp) 507 addImplicitDefUseOperands(); 508 // Make sure that we get added to a machine basicblock 509 LeakDetector::addGarbageObject(this); 510} 511 512/// MachineInstr ctor - Work exactly the same as the ctor two above, except 513/// that the MachineInstr is created and added to the end of the specified 514/// basic block. 515MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid) 516 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), 517 MemRefs(0), MemRefsEnd(0), Parent(0) { 518 assert(MBB && "Cannot use inserting ctor with null basic block!"); 519 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 520 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 521 addImplicitDefUseOperands(); 522 // Make sure that we get added to a machine basicblock 523 LeakDetector::addGarbageObject(this); 524 MBB->push_back(this); // Add instruction to end of basic block! 525} 526 527/// MachineInstr ctor - As above, but with a DebugLoc. 528/// 529MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, 530 const MCInstrDesc &tid) 531 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), 532 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) { 533 assert(MBB && "Cannot use inserting ctor with null basic block!"); 534 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 535 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 536 addImplicitDefUseOperands(); 537 // Make sure that we get added to a machine basicblock 538 LeakDetector::addGarbageObject(this); 539 MBB->push_back(this); // Add instruction to end of basic block! 540} 541 542/// MachineInstr ctor - Copies MachineInstr arg exactly 543/// 544MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 545 : MCID(&MI.getDesc()), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), 546 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd), 547 Parent(0), debugLoc(MI.getDebugLoc()) { 548 Operands.reserve(MI.getNumOperands()); 549 550 // Add operands 551 for (unsigned i = 0; i != MI.getNumOperands(); ++i) 552 addOperand(MI.getOperand(i)); 553 NumImplicitOps = MI.NumImplicitOps; 554 555 // Copy all the flags. 556 Flags = MI.Flags; 557 558 // Set parent to null. 559 Parent = 0; 560 561 LeakDetector::addGarbageObject(this); 562} 563 564MachineInstr::~MachineInstr() { 565 LeakDetector::removeGarbageObject(this); 566#ifndef NDEBUG 567 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 568 assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 569 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 570 "Reg operand def/use list corrupted"); 571 } 572#endif 573} 574 575/// getRegInfo - If this instruction is embedded into a MachineFunction, 576/// return the MachineRegisterInfo object for the current function, otherwise 577/// return null. 578MachineRegisterInfo *MachineInstr::getRegInfo() { 579 if (MachineBasicBlock *MBB = getParent()) 580 return &MBB->getParent()->getRegInfo(); 581 return 0; 582} 583 584/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 585/// this instruction from their respective use lists. This requires that the 586/// operands already be on their use lists. 587void MachineInstr::RemoveRegOperandsFromUseLists() { 588 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 589 if (Operands[i].isReg()) 590 Operands[i].RemoveRegOperandFromRegInfo(); 591 } 592} 593 594/// AddRegOperandsToUseLists - Add all of the register operands in 595/// this instruction from their respective use lists. This requires that the 596/// operands not be on their use lists yet. 597void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { 598 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 599 if (Operands[i].isReg()) 600 Operands[i].AddRegOperandToRegInfo(&RegInfo); 601 } 602} 603 604 605/// addOperand - Add the specified operand to the instruction. If it is an 606/// implicit operand, it is added to the end of the operand list. If it is 607/// an explicit operand it is added at the end of the explicit operand list 608/// (before the first implicit operand). 609void MachineInstr::addOperand(const MachineOperand &Op) { 610 bool isImpReg = Op.isReg() && Op.isImplicit(); 611 assert((isImpReg || !OperandsComplete()) && 612 "Trying to add an operand to a machine instr that is already done!"); 613 614 MachineRegisterInfo *RegInfo = getRegInfo(); 615 616 // If we are adding the operand to the end of the list, our job is simpler. 617 // This is true most of the time, so this is a reasonable optimization. 618 if (isImpReg || NumImplicitOps == 0) { 619 // We can only do this optimization if we know that the operand list won't 620 // reallocate. 621 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) { 622 Operands.push_back(Op); 623 624 // Set the parent of the operand. 625 Operands.back().ParentMI = this; 626 627 // If the operand is a register, update the operand's use list. 628 if (Op.isReg()) { 629 Operands.back().AddRegOperandToRegInfo(RegInfo); 630 // If the register operand is flagged as early, mark the operand as such 631 unsigned OpNo = Operands.size() - 1; 632 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) 633 Operands[OpNo].setIsEarlyClobber(true); 634 } 635 return; 636 } 637 } 638 639 // Otherwise, we have to insert a real operand before any implicit ones. 640 unsigned OpNo = Operands.size()-NumImplicitOps; 641 642 // If this instruction isn't embedded into a function, then we don't need to 643 // update any operand lists. 644 if (RegInfo == 0) { 645 // Simple insertion, no reginfo update needed for other register operands. 646 Operands.insert(Operands.begin()+OpNo, Op); 647 Operands[OpNo].ParentMI = this; 648 649 // Do explicitly set the reginfo for this operand though, to ensure the 650 // next/prev fields are properly nulled out. 651 if (Operands[OpNo].isReg()) { 652 Operands[OpNo].AddRegOperandToRegInfo(0); 653 // If the register operand is flagged as early, mark the operand as such 654 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) 655 Operands[OpNo].setIsEarlyClobber(true); 656 } 657 658 } else if (Operands.size()+1 <= Operands.capacity()) { 659 // Otherwise, we have to remove register operands from their register use 660 // list, add the operand, then add the register operands back to their use 661 // list. This also must handle the case when the operand list reallocates 662 // to somewhere else. 663 664 // If insertion of this operand won't cause reallocation of the operand 665 // list, just remove the implicit operands, add the operand, then re-add all 666 // the rest of the operands. 667 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 668 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 669 Operands[i].RemoveRegOperandFromRegInfo(); 670 } 671 672 // Add the operand. If it is a register, add it to the reg list. 673 Operands.insert(Operands.begin()+OpNo, Op); 674 Operands[OpNo].ParentMI = this; 675 676 if (Operands[OpNo].isReg()) { 677 Operands[OpNo].AddRegOperandToRegInfo(RegInfo); 678 // If the register operand is flagged as early, mark the operand as such 679 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) 680 Operands[OpNo].setIsEarlyClobber(true); 681 } 682 683 // Re-add all the implicit ops. 684 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) { 685 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 686 Operands[i].AddRegOperandToRegInfo(RegInfo); 687 } 688 } else { 689 // Otherwise, we will be reallocating the operand list. Remove all reg 690 // operands from their list, then readd them after the operand list is 691 // reallocated. 692 RemoveRegOperandsFromUseLists(); 693 694 Operands.insert(Operands.begin()+OpNo, Op); 695 Operands[OpNo].ParentMI = this; 696 697 // Re-add all the operands. 698 AddRegOperandsToUseLists(*RegInfo); 699 700 // If the register operand is flagged as early, mark the operand as such 701 if (Operands[OpNo].isReg() 702 && MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) 703 Operands[OpNo].setIsEarlyClobber(true); 704 } 705} 706 707/// RemoveOperand - Erase an operand from an instruction, leaving it with one 708/// fewer operand than it started with. 709/// 710void MachineInstr::RemoveOperand(unsigned OpNo) { 711 assert(OpNo < Operands.size() && "Invalid operand number"); 712 713 // Special case removing the last one. 714 if (OpNo == Operands.size()-1) { 715 // If needed, remove from the reg def/use list. 716 if (Operands.back().isReg() && Operands.back().isOnRegUseList()) 717 Operands.back().RemoveRegOperandFromRegInfo(); 718 719 Operands.pop_back(); 720 return; 721 } 722 723 // Otherwise, we are removing an interior operand. If we have reginfo to 724 // update, remove all operands that will be shifted down from their reg lists, 725 // move everything down, then re-add them. 726 MachineRegisterInfo *RegInfo = getRegInfo(); 727 if (RegInfo) { 728 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 729 if (Operands[i].isReg()) 730 Operands[i].RemoveRegOperandFromRegInfo(); 731 } 732 } 733 734 Operands.erase(Operands.begin()+OpNo); 735 736 if (RegInfo) { 737 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 738 if (Operands[i].isReg()) 739 Operands[i].AddRegOperandToRegInfo(RegInfo); 740 } 741 } 742} 743 744/// addMemOperand - Add a MachineMemOperand to the machine instruction. 745/// This function should be used only occasionally. The setMemRefs function 746/// is the primary method for setting up a MachineInstr's MemRefs list. 747void MachineInstr::addMemOperand(MachineFunction &MF, 748 MachineMemOperand *MO) { 749 mmo_iterator OldMemRefs = MemRefs; 750 mmo_iterator OldMemRefsEnd = MemRefsEnd; 751 752 size_t NewNum = (MemRefsEnd - MemRefs) + 1; 753 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum); 754 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum; 755 756 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs); 757 NewMemRefs[NewNum - 1] = MO; 758 759 MemRefs = NewMemRefs; 760 MemRefsEnd = NewMemRefsEnd; 761} 762 763bool MachineInstr::isIdenticalTo(const MachineInstr *Other, 764 MICheckType Check) const { 765 // If opcodes or number of operands are not the same then the two 766 // instructions are obviously not identical. 767 if (Other->getOpcode() != getOpcode() || 768 Other->getNumOperands() != getNumOperands()) 769 return false; 770 771 // Check operands to make sure they match. 772 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 773 const MachineOperand &MO = getOperand(i); 774 const MachineOperand &OMO = Other->getOperand(i); 775 if (!MO.isReg()) { 776 if (!MO.isIdenticalTo(OMO)) 777 return false; 778 continue; 779 } 780 781 // Clients may or may not want to ignore defs when testing for equality. 782 // For example, machine CSE pass only cares about finding common 783 // subexpressions, so it's safe to ignore virtual register defs. 784 if (MO.isDef()) { 785 if (Check == IgnoreDefs) 786 continue; 787 else if (Check == IgnoreVRegDefs) { 788 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) || 789 TargetRegisterInfo::isPhysicalRegister(OMO.getReg())) 790 if (MO.getReg() != OMO.getReg()) 791 return false; 792 } else { 793 if (!MO.isIdenticalTo(OMO)) 794 return false; 795 if (Check == CheckKillDead && MO.isDead() != OMO.isDead()) 796 return false; 797 } 798 } else { 799 if (!MO.isIdenticalTo(OMO)) 800 return false; 801 if (Check == CheckKillDead && MO.isKill() != OMO.isKill()) 802 return false; 803 } 804 } 805 // If DebugLoc does not match then two dbg.values are not identical. 806 if (isDebugValue()) 807 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown() 808 && getDebugLoc() != Other->getDebugLoc()) 809 return false; 810 return true; 811} 812 813/// removeFromParent - This method unlinks 'this' from the containing basic 814/// block, and returns it, but does not delete it. 815MachineInstr *MachineInstr::removeFromParent() { 816 assert(getParent() && "Not embedded in a basic block!"); 817 getParent()->remove(this); 818 return this; 819} 820 821 822/// eraseFromParent - This method unlinks 'this' from the containing basic 823/// block, and deletes it. 824void MachineInstr::eraseFromParent() { 825 assert(getParent() && "Not embedded in a basic block!"); 826 getParent()->erase(this); 827} 828 829 830/// OperandComplete - Return true if it's illegal to add a new operand 831/// 832bool MachineInstr::OperandsComplete() const { 833 unsigned short NumOperands = MCID->getNumOperands(); 834 if (!MCID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands) 835 return true; // Broken: we have all the operands of this instruction! 836 return false; 837} 838 839/// getNumExplicitOperands - Returns the number of non-implicit operands. 840/// 841unsigned MachineInstr::getNumExplicitOperands() const { 842 unsigned NumOperands = MCID->getNumOperands(); 843 if (!MCID->isVariadic()) 844 return NumOperands; 845 846 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) { 847 const MachineOperand &MO = getOperand(i); 848 if (!MO.isReg() || !MO.isImplicit()) 849 NumOperands++; 850 } 851 return NumOperands; 852} 853 854bool MachineInstr::isStackAligningInlineAsm() const { 855 if (isInlineAsm()) { 856 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 857 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 858 return true; 859 } 860 return false; 861} 862 863/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 864/// the specific register or -1 if it is not found. It further tightens 865/// the search criteria to a use that kills the register if isKill is true. 866int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 867 const TargetRegisterInfo *TRI) const { 868 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 869 const MachineOperand &MO = getOperand(i); 870 if (!MO.isReg() || !MO.isUse()) 871 continue; 872 unsigned MOReg = MO.getReg(); 873 if (!MOReg) 874 continue; 875 if (MOReg == Reg || 876 (TRI && 877 TargetRegisterInfo::isPhysicalRegister(MOReg) && 878 TargetRegisterInfo::isPhysicalRegister(Reg) && 879 TRI->isSubRegister(MOReg, Reg))) 880 if (!isKill || MO.isKill()) 881 return i; 882 } 883 return -1; 884} 885 886/// readsWritesVirtualRegister - Return a pair of bools (reads, writes) 887/// indicating if this instruction reads or writes Reg. This also considers 888/// partial defines. 889std::pair<bool,bool> 890MachineInstr::readsWritesVirtualRegister(unsigned Reg, 891 SmallVectorImpl<unsigned> *Ops) const { 892 bool PartDef = false; // Partial redefine. 893 bool FullDef = false; // Full define. 894 bool Use = false; 895 896 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 897 const MachineOperand &MO = getOperand(i); 898 if (!MO.isReg() || MO.getReg() != Reg) 899 continue; 900 if (Ops) 901 Ops->push_back(i); 902 if (MO.isUse()) 903 Use |= !MO.isUndef(); 904 else if (MO.getSubReg()) 905 PartDef = true; 906 else 907 FullDef = true; 908 } 909 // A partial redefine uses Reg unless there is also a full define. 910 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef); 911} 912 913/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 914/// the specified register or -1 if it is not found. If isDead is true, defs 915/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 916/// also checks if there is a def of a super-register. 917int 918MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, 919 const TargetRegisterInfo *TRI) const { 920 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg); 921 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 922 const MachineOperand &MO = getOperand(i); 923 if (!MO.isReg() || !MO.isDef()) 924 continue; 925 unsigned MOReg = MO.getReg(); 926 bool Found = (MOReg == Reg); 927 if (!Found && TRI && isPhys && 928 TargetRegisterInfo::isPhysicalRegister(MOReg)) { 929 if (Overlap) 930 Found = TRI->regsOverlap(MOReg, Reg); 931 else 932 Found = TRI->isSubRegister(MOReg, Reg); 933 } 934 if (Found && (!isDead || MO.isDead())) 935 return i; 936 } 937 return -1; 938} 939 940/// findFirstPredOperandIdx() - Find the index of the first operand in the 941/// operand list that is used to represent the predicate. It returns -1 if 942/// none is found. 943int MachineInstr::findFirstPredOperandIdx() const { 944 const MCInstrDesc &MCID = getDesc(); 945 if (MCID.isPredicable()) { 946 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 947 if (MCID.OpInfo[i].isPredicate()) 948 return i; 949 } 950 951 return -1; 952} 953 954/// isRegTiedToUseOperand - Given the index of a register def operand, 955/// check if the register def is tied to a source operand, due to either 956/// two-address elimination or inline assembly constraints. Returns the 957/// first tied use operand index by reference is UseOpIdx is not null. 958bool MachineInstr:: 959isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const { 960 if (isInlineAsm()) { 961 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand); 962 const MachineOperand &MO = getOperand(DefOpIdx); 963 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0) 964 return false; 965 // Determine the actual operand index that corresponds to this index. 966 unsigned DefNo = 0; 967 unsigned DefPart = 0; 968 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); 969 i < e; ) { 970 const MachineOperand &FMO = getOperand(i); 971 // After the normal asm operands there may be additional imp-def regs. 972 if (!FMO.isImm()) 973 return false; 974 // Skip over this def. 975 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm()); 976 unsigned PrevDef = i + 1; 977 i = PrevDef + NumOps; 978 if (i > DefOpIdx) { 979 DefPart = DefOpIdx - PrevDef; 980 break; 981 } 982 ++DefNo; 983 } 984 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); 985 i != e; ++i) { 986 const MachineOperand &FMO = getOperand(i); 987 if (!FMO.isImm()) 988 continue; 989 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse()) 990 continue; 991 unsigned Idx; 992 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) && 993 Idx == DefNo) { 994 if (UseOpIdx) 995 *UseOpIdx = (unsigned)i + 1 + DefPart; 996 return true; 997 } 998 } 999 return false; 1000 } 1001 1002 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!"); 1003 const MCInstrDesc &MCID = getDesc(); 1004 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { 1005 const MachineOperand &MO = getOperand(i); 1006 if (MO.isReg() && MO.isUse() && 1007 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) { 1008 if (UseOpIdx) 1009 *UseOpIdx = (unsigned)i; 1010 return true; 1011 } 1012 } 1013 return false; 1014} 1015 1016/// isRegTiedToDefOperand - Return true if the operand of the specified index 1017/// is a register use and it is tied to an def operand. It also returns the def 1018/// operand index by reference. 1019bool MachineInstr:: 1020isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const { 1021 if (isInlineAsm()) { 1022 const MachineOperand &MO = getOperand(UseOpIdx); 1023 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0) 1024 return false; 1025 1026 // Find the flag operand corresponding to UseOpIdx 1027 unsigned FlagIdx, NumOps=0; 1028 for (FlagIdx = InlineAsm::MIOp_FirstOperand; 1029 FlagIdx < UseOpIdx; FlagIdx += NumOps+1) { 1030 const MachineOperand &UFMO = getOperand(FlagIdx); 1031 // After the normal asm operands there may be additional imp-def regs. 1032 if (!UFMO.isImm()) 1033 return false; 1034 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm()); 1035 assert(NumOps < getNumOperands() && "Invalid inline asm flag"); 1036 if (UseOpIdx < FlagIdx+NumOps+1) 1037 break; 1038 } 1039 if (FlagIdx >= UseOpIdx) 1040 return false; 1041 const MachineOperand &UFMO = getOperand(FlagIdx); 1042 unsigned DefNo; 1043 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) { 1044 if (!DefOpIdx) 1045 return true; 1046 1047 unsigned DefIdx = InlineAsm::MIOp_FirstOperand; 1048 // Remember to adjust the index. First operand is asm string, second is 1049 // the HasSideEffects and AlignStack bits, then there is a flag for each. 1050 while (DefNo) { 1051 const MachineOperand &FMO = getOperand(DefIdx); 1052 assert(FMO.isImm()); 1053 // Skip over this def. 1054 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1; 1055 --DefNo; 1056 } 1057 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx; 1058 return true; 1059 } 1060 return false; 1061 } 1062 1063 const MCInstrDesc &MCID = getDesc(); 1064 if (UseOpIdx >= MCID.getNumOperands()) 1065 return false; 1066 const MachineOperand &MO = getOperand(UseOpIdx); 1067 if (!MO.isReg() || !MO.isUse()) 1068 return false; 1069 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO); 1070 if (DefIdx == -1) 1071 return false; 1072 if (DefOpIdx) 1073 *DefOpIdx = (unsigned)DefIdx; 1074 return true; 1075} 1076 1077/// clearKillInfo - Clears kill flags on all operands. 1078/// 1079void MachineInstr::clearKillInfo() { 1080 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1081 MachineOperand &MO = getOperand(i); 1082 if (MO.isReg() && MO.isUse()) 1083 MO.setIsKill(false); 1084 } 1085} 1086 1087/// copyKillDeadInfo - Copies kill / dead operand properties from MI. 1088/// 1089void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 1090 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1091 const MachineOperand &MO = MI->getOperand(i); 1092 if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) 1093 continue; 1094 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 1095 MachineOperand &MOp = getOperand(j); 1096 if (!MOp.isIdenticalTo(MO)) 1097 continue; 1098 if (MO.isKill()) 1099 MOp.setIsKill(); 1100 else 1101 MOp.setIsDead(); 1102 break; 1103 } 1104 } 1105} 1106 1107/// copyPredicates - Copies predicate operand(s) from MI. 1108void MachineInstr::copyPredicates(const MachineInstr *MI) { 1109 const MCInstrDesc &MCID = MI->getDesc(); 1110 if (!MCID.isPredicable()) 1111 return; 1112 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1113 if (MCID.OpInfo[i].isPredicate()) { 1114 // Predicated operands must be last operands. 1115 addOperand(MI->getOperand(i)); 1116 } 1117 } 1118} 1119 1120void MachineInstr::substituteRegister(unsigned FromReg, 1121 unsigned ToReg, 1122 unsigned SubIdx, 1123 const TargetRegisterInfo &RegInfo) { 1124 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) { 1125 if (SubIdx) 1126 ToReg = RegInfo.getSubReg(ToReg, SubIdx); 1127 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1128 MachineOperand &MO = getOperand(i); 1129 if (!MO.isReg() || MO.getReg() != FromReg) 1130 continue; 1131 MO.substPhysReg(ToReg, RegInfo); 1132 } 1133 } else { 1134 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1135 MachineOperand &MO = getOperand(i); 1136 if (!MO.isReg() || MO.getReg() != FromReg) 1137 continue; 1138 MO.substVirtReg(ToReg, SubIdx, RegInfo); 1139 } 1140 } 1141} 1142 1143/// isSafeToMove - Return true if it is safe to move this instruction. If 1144/// SawStore is set to true, it means that there is a store (or call) between 1145/// the instruction's location and its intended destination. 1146bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, 1147 AliasAnalysis *AA, 1148 bool &SawStore) const { 1149 // Ignore stuff that we obviously can't move. 1150 if (MCID->mayStore() || MCID->isCall()) { 1151 SawStore = true; 1152 return false; 1153 } 1154 1155 if (isLabel() || isDebugValue() || 1156 MCID->isTerminator() || hasUnmodeledSideEffects()) 1157 return false; 1158 1159 // See if this instruction does a load. If so, we have to guarantee that the 1160 // loaded value doesn't change between the load and the its intended 1161 // destination. The check for isInvariantLoad gives the targe the chance to 1162 // classify the load as always returning a constant, e.g. a constant pool 1163 // load. 1164 if (MCID->mayLoad() && !isInvariantLoad(AA)) 1165 // Otherwise, this is a real load. If there is a store between the load and 1166 // end of block, or if the load is volatile, we can't move it. 1167 return !SawStore && !hasVolatileMemoryRef(); 1168 1169 return true; 1170} 1171 1172/// isSafeToReMat - Return true if it's safe to rematerialize the specified 1173/// instruction which defined the specified register instead of copying it. 1174bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, 1175 AliasAnalysis *AA, 1176 unsigned DstReg) const { 1177 bool SawStore = false; 1178 if (!TII->isTriviallyReMaterializable(this, AA) || 1179 !isSafeToMove(TII, AA, SawStore)) 1180 return false; 1181 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1182 const MachineOperand &MO = getOperand(i); 1183 if (!MO.isReg()) 1184 continue; 1185 // FIXME: For now, do not remat any instruction with register operands. 1186 // Later on, we can loosen the restriction is the register operands have 1187 // not been modified between the def and use. Note, this is different from 1188 // MachineSink because the code is no longer in two-address form (at least 1189 // partially). 1190 if (MO.isUse()) 1191 return false; 1192 else if (!MO.isDead() && MO.getReg() != DstReg) 1193 return false; 1194 } 1195 return true; 1196} 1197 1198/// hasVolatileMemoryRef - Return true if this instruction may have a 1199/// volatile memory reference, or if the information describing the 1200/// memory reference is not available. Return false if it is known to 1201/// have no volatile memory references. 1202bool MachineInstr::hasVolatileMemoryRef() const { 1203 // An instruction known never to access memory won't have a volatile access. 1204 if (!MCID->mayStore() && 1205 !MCID->mayLoad() && 1206 !MCID->isCall() && 1207 !hasUnmodeledSideEffects()) 1208 return false; 1209 1210 // Otherwise, if the instruction has no memory reference information, 1211 // conservatively assume it wasn't preserved. 1212 if (memoperands_empty()) 1213 return true; 1214 1215 // Check the memory reference information for volatile references. 1216 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I) 1217 if ((*I)->isVolatile()) 1218 return true; 1219 1220 return false; 1221} 1222 1223/// isInvariantLoad - Return true if this instruction is loading from a 1224/// location whose value is invariant across the function. For example, 1225/// loading a value from the constant pool or from the argument area 1226/// of a function if it does not change. This should only return true of 1227/// *all* loads the instruction does are invariant (if it does multiple loads). 1228bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const { 1229 // If the instruction doesn't load at all, it isn't an invariant load. 1230 if (!MCID->mayLoad()) 1231 return false; 1232 1233 // If the instruction has lost its memoperands, conservatively assume that 1234 // it may not be an invariant load. 1235 if (memoperands_empty()) 1236 return false; 1237 1238 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo(); 1239 1240 for (mmo_iterator I = memoperands_begin(), 1241 E = memoperands_end(); I != E; ++I) { 1242 if ((*I)->isVolatile()) return false; 1243 if ((*I)->isStore()) return false; 1244 1245 if (const Value *V = (*I)->getValue()) { 1246 // A load from a constant PseudoSourceValue is invariant. 1247 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) 1248 if (PSV->isConstant(MFI)) 1249 continue; 1250 // If we have an AliasAnalysis, ask it whether the memory is constant. 1251 if (AA && AA->pointsToConstantMemory( 1252 AliasAnalysis::Location(V, (*I)->getSize(), 1253 (*I)->getTBAAInfo()))) 1254 continue; 1255 } 1256 1257 // Otherwise assume conservatively. 1258 return false; 1259 } 1260 1261 // Everything checks out. 1262 return true; 1263} 1264 1265/// isConstantValuePHI - If the specified instruction is a PHI that always 1266/// merges together the same virtual register, return the register, otherwise 1267/// return 0. 1268unsigned MachineInstr::isConstantValuePHI() const { 1269 if (!isPHI()) 1270 return 0; 1271 assert(getNumOperands() >= 3 && 1272 "It's illegal to have a PHI without source operands"); 1273 1274 unsigned Reg = getOperand(1).getReg(); 1275 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) 1276 if (getOperand(i).getReg() != Reg) 1277 return 0; 1278 return Reg; 1279} 1280 1281bool MachineInstr::hasUnmodeledSideEffects() const { 1282 if (getDesc().hasUnmodeledSideEffects()) 1283 return true; 1284 if (isInlineAsm()) { 1285 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1286 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1287 return true; 1288 } 1289 1290 return false; 1291} 1292 1293/// allDefsAreDead - Return true if all the defs of this instruction are dead. 1294/// 1295bool MachineInstr::allDefsAreDead() const { 1296 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) { 1297 const MachineOperand &MO = getOperand(i); 1298 if (!MO.isReg() || MO.isUse()) 1299 continue; 1300 if (!MO.isDead()) 1301 return false; 1302 } 1303 return true; 1304} 1305 1306/// copyImplicitOps - Copy implicit register operands from specified 1307/// instruction to this instruction. 1308void MachineInstr::copyImplicitOps(const MachineInstr *MI) { 1309 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands(); 1310 i != e; ++i) { 1311 const MachineOperand &MO = MI->getOperand(i); 1312 if (MO.isReg() && MO.isImplicit()) 1313 addOperand(MO); 1314 } 1315} 1316 1317void MachineInstr::dump() const { 1318 dbgs() << " " << *this; 1319} 1320 1321static void printDebugLoc(DebugLoc DL, const MachineFunction *MF, 1322 raw_ostream &CommentOS) { 1323 const LLVMContext &Ctx = MF->getFunction()->getContext(); 1324 if (!DL.isUnknown()) { // Print source line info. 1325 DIScope Scope(DL.getScope(Ctx)); 1326 // Omit the directory, because it's likely to be long and uninteresting. 1327 if (Scope.Verify()) 1328 CommentOS << Scope.getFilename(); 1329 else 1330 CommentOS << "<unknown>"; 1331 CommentOS << ':' << DL.getLine(); 1332 if (DL.getCol() != 0) 1333 CommentOS << ':' << DL.getCol(); 1334 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx)); 1335 if (!InlinedAtDL.isUnknown()) { 1336 CommentOS << " @[ "; 1337 printDebugLoc(InlinedAtDL, MF, CommentOS); 1338 CommentOS << " ]"; 1339 } 1340 } 1341} 1342 1343void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { 1344 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction. 1345 const MachineFunction *MF = 0; 1346 const MachineRegisterInfo *MRI = 0; 1347 if (const MachineBasicBlock *MBB = getParent()) { 1348 MF = MBB->getParent(); 1349 if (!TM && MF) 1350 TM = &MF->getTarget(); 1351 if (MF) 1352 MRI = &MF->getRegInfo(); 1353 } 1354 1355 // Save a list of virtual registers. 1356 SmallVector<unsigned, 8> VirtRegs; 1357 1358 // Print explicitly defined operands on the left of an assignment syntax. 1359 unsigned StartOp = 0, e = getNumOperands(); 1360 for (; StartOp < e && getOperand(StartOp).isReg() && 1361 getOperand(StartOp).isDef() && 1362 !getOperand(StartOp).isImplicit(); 1363 ++StartOp) { 1364 if (StartOp != 0) OS << ", "; 1365 getOperand(StartOp).print(OS, TM); 1366 unsigned Reg = getOperand(StartOp).getReg(); 1367 if (TargetRegisterInfo::isVirtualRegister(Reg)) 1368 VirtRegs.push_back(Reg); 1369 } 1370 1371 if (StartOp != 0) 1372 OS << " = "; 1373 1374 // Print the opcode name. 1375 OS << getDesc().getName(); 1376 1377 // Print the rest of the operands. 1378 bool OmittedAnyCallClobbers = false; 1379 bool FirstOp = true; 1380 unsigned AsmDescOp = ~0u; 1381 unsigned AsmOpCount = 0; 1382 1383 if (isInlineAsm()) { 1384 // Print asm string. 1385 OS << " "; 1386 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM); 1387 1388 // Print HasSideEffects, IsAlignStack 1389 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1390 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1391 OS << " [sideeffect]"; 1392 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 1393 OS << " [alignstack]"; 1394 1395 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand; 1396 FirstOp = false; 1397 } 1398 1399 1400 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 1401 const MachineOperand &MO = getOperand(i); 1402 1403 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1404 VirtRegs.push_back(MO.getReg()); 1405 1406 // Omit call-clobbered registers which aren't used anywhere. This makes 1407 // call instructions much less noisy on targets where calls clobber lots 1408 // of registers. Don't rely on MO.isDead() because we may be called before 1409 // LiveVariables is run, or we may be looking at a non-allocatable reg. 1410 if (MF && getDesc().isCall() && 1411 MO.isReg() && MO.isImplicit() && MO.isDef()) { 1412 unsigned Reg = MO.getReg(); 1413 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 1414 const MachineRegisterInfo &MRI = MF->getRegInfo(); 1415 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) { 1416 bool HasAliasLive = false; 1417 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg); 1418 unsigned AliasReg = *Alias; ++Alias) 1419 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) { 1420 HasAliasLive = true; 1421 break; 1422 } 1423 if (!HasAliasLive) { 1424 OmittedAnyCallClobbers = true; 1425 continue; 1426 } 1427 } 1428 } 1429 } 1430 1431 if (FirstOp) FirstOp = false; else OS << ","; 1432 OS << " "; 1433 if (i < getDesc().NumOperands) { 1434 const MCOperandInfo &MCOI = getDesc().OpInfo[i]; 1435 if (MCOI.isPredicate()) 1436 OS << "pred:"; 1437 if (MCOI.isOptionalDef()) 1438 OS << "opt:"; 1439 } 1440 if (isDebugValue() && MO.isMetadata()) { 1441 // Pretty print DBG_VALUE instructions. 1442 const MDNode *MD = MO.getMetadata(); 1443 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2))) 1444 OS << "!\"" << MDS->getString() << '\"'; 1445 else 1446 MO.print(OS, TM); 1447 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) { 1448 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm()); 1449 } else if (i == AsmDescOp && MO.isImm()) { 1450 // Pretty print the inline asm operand descriptor. 1451 OS << '$' << AsmOpCount++; 1452 unsigned Flag = MO.getImm(); 1453 switch (InlineAsm::getKind(Flag)) { 1454 case InlineAsm::Kind_RegUse: OS << ":[reguse]"; break; 1455 case InlineAsm::Kind_RegDef: OS << ":[regdef]"; break; 1456 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec]"; break; 1457 case InlineAsm::Kind_Clobber: OS << ":[clobber]"; break; 1458 case InlineAsm::Kind_Imm: OS << ":[imm]"; break; 1459 case InlineAsm::Kind_Mem: OS << ":[mem]"; break; 1460 default: OS << ":[??" << InlineAsm::getKind(Flag) << ']'; break; 1461 } 1462 1463 unsigned TiedTo = 0; 1464 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) 1465 OS << " [tiedto:$" << TiedTo << ']'; 1466 1467 // Compute the index of the next operand descriptor. 1468 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag); 1469 } else 1470 MO.print(OS, TM); 1471 } 1472 1473 // Briefly indicate whether any call clobbers were omitted. 1474 if (OmittedAnyCallClobbers) { 1475 if (!FirstOp) OS << ","; 1476 OS << " ..."; 1477 } 1478 1479 bool HaveSemi = false; 1480 if (Flags) { 1481 if (!HaveSemi) OS << ";"; HaveSemi = true; 1482 OS << " flags: "; 1483 1484 if (Flags & FrameSetup) 1485 OS << "FrameSetup"; 1486 } 1487 1488 if (!memoperands_empty()) { 1489 if (!HaveSemi) OS << ";"; HaveSemi = true; 1490 1491 OS << " mem:"; 1492 for (mmo_iterator i = memoperands_begin(), e = memoperands_end(); 1493 i != e; ++i) { 1494 OS << **i; 1495 if (llvm::next(i) != e) 1496 OS << " "; 1497 } 1498 } 1499 1500 // Print the regclass of any virtual registers encountered. 1501 if (MRI && !VirtRegs.empty()) { 1502 if (!HaveSemi) OS << ";"; HaveSemi = true; 1503 for (unsigned i = 0; i != VirtRegs.size(); ++i) { 1504 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]); 1505 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]); 1506 for (unsigned j = i+1; j != VirtRegs.size();) { 1507 if (MRI->getRegClass(VirtRegs[j]) != RC) { 1508 ++j; 1509 continue; 1510 } 1511 if (VirtRegs[i] != VirtRegs[j]) 1512 OS << "," << PrintReg(VirtRegs[j]); 1513 VirtRegs.erase(VirtRegs.begin()+j); 1514 } 1515 } 1516 } 1517 1518 // Print debug location information. 1519 if (!debugLoc.isUnknown() && MF) { 1520 if (!HaveSemi) OS << ";"; HaveSemi = true; 1521 OS << " dbg:"; 1522 printDebugLoc(debugLoc, MF, OS); 1523 } 1524 1525 OS << '\n'; 1526} 1527 1528bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 1529 const TargetRegisterInfo *RegInfo, 1530 bool AddIfNotFound) { 1531 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1532 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 1533 bool Found = false; 1534 SmallVector<unsigned,4> DeadOps; 1535 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1536 MachineOperand &MO = getOperand(i); 1537 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) 1538 continue; 1539 unsigned Reg = MO.getReg(); 1540 if (!Reg) 1541 continue; 1542 1543 if (Reg == IncomingReg) { 1544 if (!Found) { 1545 if (MO.isKill()) 1546 // The register is already marked kill. 1547 return true; 1548 if (isPhysReg && isRegTiedToDefOperand(i)) 1549 // Two-address uses of physregs must not be marked kill. 1550 return true; 1551 MO.setIsKill(); 1552 Found = true; 1553 } 1554 } else if (hasAliases && MO.isKill() && 1555 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1556 // A super-register kill already exists. 1557 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1558 return true; 1559 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1560 DeadOps.push_back(i); 1561 } 1562 } 1563 1564 // Trim unneeded kill operands. 1565 while (!DeadOps.empty()) { 1566 unsigned OpIdx = DeadOps.back(); 1567 if (getOperand(OpIdx).isImplicit()) 1568 RemoveOperand(OpIdx); 1569 else 1570 getOperand(OpIdx).setIsKill(false); 1571 DeadOps.pop_back(); 1572 } 1573 1574 // If not found, this means an alias of one of the operands is killed. Add a 1575 // new implicit operand if required. 1576 if (!Found && AddIfNotFound) { 1577 addOperand(MachineOperand::CreateReg(IncomingReg, 1578 false /*IsDef*/, 1579 true /*IsImp*/, 1580 true /*IsKill*/)); 1581 return true; 1582 } 1583 return Found; 1584} 1585 1586bool MachineInstr::addRegisterDead(unsigned IncomingReg, 1587 const TargetRegisterInfo *RegInfo, 1588 bool AddIfNotFound) { 1589 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1590 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 1591 bool Found = false; 1592 SmallVector<unsigned,4> DeadOps; 1593 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1594 MachineOperand &MO = getOperand(i); 1595 if (!MO.isReg() || !MO.isDef()) 1596 continue; 1597 unsigned Reg = MO.getReg(); 1598 if (!Reg) 1599 continue; 1600 1601 if (Reg == IncomingReg) { 1602 MO.setIsDead(); 1603 Found = true; 1604 } else if (hasAliases && MO.isDead() && 1605 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1606 // There exists a super-register that's marked dead. 1607 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1608 return true; 1609 if (RegInfo->getSubRegisters(IncomingReg) && 1610 RegInfo->getSuperRegisters(Reg) && 1611 RegInfo->isSubRegister(IncomingReg, Reg)) 1612 DeadOps.push_back(i); 1613 } 1614 } 1615 1616 // Trim unneeded dead operands. 1617 while (!DeadOps.empty()) { 1618 unsigned OpIdx = DeadOps.back(); 1619 if (getOperand(OpIdx).isImplicit()) 1620 RemoveOperand(OpIdx); 1621 else 1622 getOperand(OpIdx).setIsDead(false); 1623 DeadOps.pop_back(); 1624 } 1625 1626 // If not found, this means an alias of one of the operands is dead. Add a 1627 // new implicit operand if required. 1628 if (Found || !AddIfNotFound) 1629 return Found; 1630 1631 addOperand(MachineOperand::CreateReg(IncomingReg, 1632 true /*IsDef*/, 1633 true /*IsImp*/, 1634 false /*IsKill*/, 1635 true /*IsDead*/)); 1636 return true; 1637} 1638 1639void MachineInstr::addRegisterDefined(unsigned IncomingReg, 1640 const TargetRegisterInfo *RegInfo) { 1641 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) { 1642 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo); 1643 if (MO) 1644 return; 1645 } else { 1646 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1647 const MachineOperand &MO = getOperand(i); 1648 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() && 1649 MO.getSubReg() == 0) 1650 return; 1651 } 1652 } 1653 addOperand(MachineOperand::CreateReg(IncomingReg, 1654 true /*IsDef*/, 1655 true /*IsImp*/)); 1656} 1657 1658void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs, 1659 const TargetRegisterInfo &TRI) { 1660 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1661 MachineOperand &MO = getOperand(i); 1662 if (!MO.isReg() || !MO.isDef()) continue; 1663 unsigned Reg = MO.getReg(); 1664 if (Reg == 0) continue; 1665 bool Dead = true; 1666 for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(), 1667 E = UsedRegs.end(); I != E; ++I) 1668 if (TRI.regsOverlap(*I, Reg)) { 1669 Dead = false; 1670 break; 1671 } 1672 // If there are no uses, including partial uses, the def is dead. 1673 if (Dead) MO.setIsDead(); 1674 } 1675} 1676 1677unsigned 1678MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) { 1679 unsigned Hash = MI->getOpcode() * 37; 1680 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1681 const MachineOperand &MO = MI->getOperand(i); 1682 uint64_t Key = (uint64_t)MO.getType() << 32; 1683 switch (MO.getType()) { 1684 default: break; 1685 case MachineOperand::MO_Register: 1686 if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1687 continue; // Skip virtual register defs. 1688 Key |= MO.getReg(); 1689 break; 1690 case MachineOperand::MO_Immediate: 1691 Key |= MO.getImm(); 1692 break; 1693 case MachineOperand::MO_FrameIndex: 1694 case MachineOperand::MO_ConstantPoolIndex: 1695 case MachineOperand::MO_JumpTableIndex: 1696 Key |= MO.getIndex(); 1697 break; 1698 case MachineOperand::MO_MachineBasicBlock: 1699 Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB()); 1700 break; 1701 case MachineOperand::MO_GlobalAddress: 1702 Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal()); 1703 break; 1704 case MachineOperand::MO_BlockAddress: 1705 Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress()); 1706 break; 1707 case MachineOperand::MO_MCSymbol: 1708 Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol()); 1709 break; 1710 } 1711 Key += ~(Key << 32); 1712 Key ^= (Key >> 22); 1713 Key += ~(Key << 13); 1714 Key ^= (Key >> 8); 1715 Key += (Key << 3); 1716 Key ^= (Key >> 15); 1717 Key += ~(Key << 27); 1718 Key ^= (Key >> 31); 1719 Hash = (unsigned)Key + Hash * 37; 1720 } 1721 return Hash; 1722} 1723 1724void MachineInstr::emitError(StringRef Msg) const { 1725 // Find the source location cookie. 1726 unsigned LocCookie = 0; 1727 const MDNode *LocMD = 0; 1728 for (unsigned i = getNumOperands(); i != 0; --i) { 1729 if (getOperand(i-1).isMetadata() && 1730 (LocMD = getOperand(i-1).getMetadata()) && 1731 LocMD->getNumOperands() != 0) { 1732 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) { 1733 LocCookie = CI->getZExtValue(); 1734 break; 1735 } 1736 } 1737 } 1738 1739 if (const MachineBasicBlock *MBB = getParent()) 1740 if (const MachineFunction *MF = MBB->getParent()) 1741 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg); 1742 report_fatal_error(Msg); 1743} 1744