1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/ADT/FoldingSet.h"
16#include "llvm/ADT/Hashing.h"
17#include "llvm/Analysis/AliasAnalysis.h"
18#include "llvm/Assembly/Writer.h"
19#include "llvm/CodeGen/MachineConstantPool.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineMemOperand.h"
22#include "llvm/CodeGen/MachineModuleInfo.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/PseudoSourceValue.h"
25#include "llvm/DebugInfo.h"
26#include "llvm/IR/Constants.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/InlineAsm.h"
29#include "llvm/IR/LLVMContext.h"
30#include "llvm/IR/Metadata.h"
31#include "llvm/IR/Module.h"
32#include "llvm/IR/Type.h"
33#include "llvm/IR/Value.h"
34#include "llvm/MC/MCInstrDesc.h"
35#include "llvm/MC/MCSymbol.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/MathExtras.h"
39#include "llvm/Support/raw_ostream.h"
40#include "llvm/Target/TargetInstrInfo.h"
41#include "llvm/Target/TargetMachine.h"
42#include "llvm/Target/TargetRegisterInfo.h"
43using namespace llvm;
44
45//===----------------------------------------------------------------------===//
46// MachineOperand Implementation
47//===----------------------------------------------------------------------===//
48
49void MachineOperand::setReg(unsigned Reg) {
50  if (getReg() == Reg) return; // No change.
51
52  // Otherwise, we have to change the register.  If this operand is embedded
53  // into a machine function, we need to update the old and new register's
54  // use/def lists.
55  if (MachineInstr *MI = getParent())
56    if (MachineBasicBlock *MBB = MI->getParent())
57      if (MachineFunction *MF = MBB->getParent()) {
58        MachineRegisterInfo &MRI = MF->getRegInfo();
59        MRI.removeRegOperandFromUseList(this);
60        SmallContents.RegNo = Reg;
61        MRI.addRegOperandToUseList(this);
62        return;
63      }
64
65  // Otherwise, just change the register, no problem.  :)
66  SmallContents.RegNo = Reg;
67}
68
69void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
70                                  const TargetRegisterInfo &TRI) {
71  assert(TargetRegisterInfo::isVirtualRegister(Reg));
72  if (SubIdx && getSubReg())
73    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
74  setReg(Reg);
75  if (SubIdx)
76    setSubReg(SubIdx);
77}
78
79void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
80  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
81  if (getSubReg()) {
82    Reg = TRI.getSubReg(Reg, getSubReg());
83    // Note that getSubReg() may return 0 if the sub-register doesn't exist.
84    // That won't happen in legal code.
85    setSubReg(0);
86  }
87  setReg(Reg);
88}
89
90/// Change a def to a use, or a use to a def.
91void MachineOperand::setIsDef(bool Val) {
92  assert(isReg() && "Wrong MachineOperand accessor");
93  assert((!Val || !isDebug()) && "Marking a debug operation as def");
94  if (IsDef == Val)
95    return;
96  // MRI may keep uses and defs in different list positions.
97  if (MachineInstr *MI = getParent())
98    if (MachineBasicBlock *MBB = MI->getParent())
99      if (MachineFunction *MF = MBB->getParent()) {
100        MachineRegisterInfo &MRI = MF->getRegInfo();
101        MRI.removeRegOperandFromUseList(this);
102        IsDef = Val;
103        MRI.addRegOperandToUseList(this);
104        return;
105      }
106  IsDef = Val;
107}
108
109/// ChangeToImmediate - Replace this operand with a new immediate operand of
110/// the specified value.  If an operand is known to be an immediate already,
111/// the setImm method should be used.
112void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
113  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
114  // If this operand is currently a register operand, and if this is in a
115  // function, deregister the operand from the register's use/def list.
116  if (isReg() && isOnRegUseList())
117    if (MachineInstr *MI = getParent())
118      if (MachineBasicBlock *MBB = MI->getParent())
119        if (MachineFunction *MF = MBB->getParent())
120          MF->getRegInfo().removeRegOperandFromUseList(this);
121
122  OpKind = MO_Immediate;
123  Contents.ImmVal = ImmVal;
124}
125
126/// ChangeToRegister - Replace this operand with a new register operand of
127/// the specified value.  If an operand is known to be an register already,
128/// the setReg method should be used.
129void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
130                                      bool isKill, bool isDead, bool isUndef,
131                                      bool isDebug) {
132  MachineRegisterInfo *RegInfo = 0;
133  if (MachineInstr *MI = getParent())
134    if (MachineBasicBlock *MBB = MI->getParent())
135      if (MachineFunction *MF = MBB->getParent())
136        RegInfo = &MF->getRegInfo();
137  // If this operand is already a register operand, remove it from the
138  // register's use/def lists.
139  bool WasReg = isReg();
140  if (RegInfo && WasReg)
141    RegInfo->removeRegOperandFromUseList(this);
142
143  // Change this to a register and set the reg#.
144  OpKind = MO_Register;
145  SmallContents.RegNo = Reg;
146  SubReg_TargetFlags = 0;
147  IsDef = isDef;
148  IsImp = isImp;
149  IsKill = isKill;
150  IsDead = isDead;
151  IsUndef = isUndef;
152  IsInternalRead = false;
153  IsEarlyClobber = false;
154  IsDebug = isDebug;
155  // Ensure isOnRegUseList() returns false.
156  Contents.Reg.Prev = 0;
157  // Preserve the tie when the operand was already a register.
158  if (!WasReg)
159    TiedTo = 0;
160
161  // If this operand is embedded in a function, add the operand to the
162  // register's use/def list.
163  if (RegInfo)
164    RegInfo->addRegOperandToUseList(this);
165}
166
167/// isIdenticalTo - Return true if this operand is identical to the specified
168/// operand. Note that this should stay in sync with the hash_value overload
169/// below.
170bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
171  if (getType() != Other.getType() ||
172      getTargetFlags() != Other.getTargetFlags())
173    return false;
174
175  switch (getType()) {
176  case MachineOperand::MO_Register:
177    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
178           getSubReg() == Other.getSubReg();
179  case MachineOperand::MO_Immediate:
180    return getImm() == Other.getImm();
181  case MachineOperand::MO_CImmediate:
182    return getCImm() == Other.getCImm();
183  case MachineOperand::MO_FPImmediate:
184    return getFPImm() == Other.getFPImm();
185  case MachineOperand::MO_MachineBasicBlock:
186    return getMBB() == Other.getMBB();
187  case MachineOperand::MO_FrameIndex:
188    return getIndex() == Other.getIndex();
189  case MachineOperand::MO_ConstantPoolIndex:
190  case MachineOperand::MO_TargetIndex:
191    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
192  case MachineOperand::MO_JumpTableIndex:
193    return getIndex() == Other.getIndex();
194  case MachineOperand::MO_GlobalAddress:
195    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
196  case MachineOperand::MO_ExternalSymbol:
197    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
198           getOffset() == Other.getOffset();
199  case MachineOperand::MO_BlockAddress:
200    return getBlockAddress() == Other.getBlockAddress() &&
201           getOffset() == Other.getOffset();
202  case MO_RegisterMask:
203    return getRegMask() == Other.getRegMask();
204  case MachineOperand::MO_MCSymbol:
205    return getMCSymbol() == Other.getMCSymbol();
206  case MachineOperand::MO_Metadata:
207    return getMetadata() == Other.getMetadata();
208  }
209  llvm_unreachable("Invalid machine operand type");
210}
211
212// Note: this must stay exactly in sync with isIdenticalTo above.
213hash_code llvm::hash_value(const MachineOperand &MO) {
214  switch (MO.getType()) {
215  case MachineOperand::MO_Register:
216    // Register operands don't have target flags.
217    return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
218  case MachineOperand::MO_Immediate:
219    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
220  case MachineOperand::MO_CImmediate:
221    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
222  case MachineOperand::MO_FPImmediate:
223    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
224  case MachineOperand::MO_MachineBasicBlock:
225    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
226  case MachineOperand::MO_FrameIndex:
227    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
228  case MachineOperand::MO_ConstantPoolIndex:
229  case MachineOperand::MO_TargetIndex:
230    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
231                        MO.getOffset());
232  case MachineOperand::MO_JumpTableIndex:
233    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
234  case MachineOperand::MO_ExternalSymbol:
235    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
236                        MO.getSymbolName());
237  case MachineOperand::MO_GlobalAddress:
238    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
239                        MO.getOffset());
240  case MachineOperand::MO_BlockAddress:
241    return hash_combine(MO.getType(), MO.getTargetFlags(),
242                        MO.getBlockAddress(), MO.getOffset());
243  case MachineOperand::MO_RegisterMask:
244    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
245  case MachineOperand::MO_Metadata:
246    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
247  case MachineOperand::MO_MCSymbol:
248    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
249  }
250  llvm_unreachable("Invalid machine operand type");
251}
252
253/// print - Print the specified machine operand.
254///
255void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
256  // If the instruction is embedded into a basic block, we can find the
257  // target info for the instruction.
258  if (!TM)
259    if (const MachineInstr *MI = getParent())
260      if (const MachineBasicBlock *MBB = MI->getParent())
261        if (const MachineFunction *MF = MBB->getParent())
262          TM = &MF->getTarget();
263  const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
264
265  switch (getType()) {
266  case MachineOperand::MO_Register:
267    OS << PrintReg(getReg(), TRI, getSubReg());
268
269    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
270        isInternalRead() || isEarlyClobber() || isTied()) {
271      OS << '<';
272      bool NeedComma = false;
273      if (isDef()) {
274        if (NeedComma) OS << ',';
275        if (isEarlyClobber())
276          OS << "earlyclobber,";
277        if (isImplicit())
278          OS << "imp-";
279        OS << "def";
280        NeedComma = true;
281        // <def,read-undef> only makes sense when getSubReg() is set.
282        // Don't clutter the output otherwise.
283        if (isUndef() && getSubReg())
284          OS << ",read-undef";
285      } else if (isImplicit()) {
286          OS << "imp-use";
287          NeedComma = true;
288      }
289
290      if (isKill()) {
291        if (NeedComma) OS << ',';
292        OS << "kill";
293        NeedComma = true;
294      }
295      if (isDead()) {
296        if (NeedComma) OS << ',';
297        OS << "dead";
298        NeedComma = true;
299      }
300      if (isUndef() && isUse()) {
301        if (NeedComma) OS << ',';
302        OS << "undef";
303        NeedComma = true;
304      }
305      if (isInternalRead()) {
306        if (NeedComma) OS << ',';
307        OS << "internal";
308        NeedComma = true;
309      }
310      if (isTied()) {
311        if (NeedComma) OS << ',';
312        OS << "tied";
313        if (TiedTo != 15)
314          OS << unsigned(TiedTo - 1);
315        NeedComma = true;
316      }
317      OS << '>';
318    }
319    break;
320  case MachineOperand::MO_Immediate:
321    OS << getImm();
322    break;
323  case MachineOperand::MO_CImmediate:
324    getCImm()->getValue().print(OS, false);
325    break;
326  case MachineOperand::MO_FPImmediate:
327    if (getFPImm()->getType()->isFloatTy())
328      OS << getFPImm()->getValueAPF().convertToFloat();
329    else
330      OS << getFPImm()->getValueAPF().convertToDouble();
331    break;
332  case MachineOperand::MO_MachineBasicBlock:
333    OS << "<BB#" << getMBB()->getNumber() << ">";
334    break;
335  case MachineOperand::MO_FrameIndex:
336    OS << "<fi#" << getIndex() << '>';
337    break;
338  case MachineOperand::MO_ConstantPoolIndex:
339    OS << "<cp#" << getIndex();
340    if (getOffset()) OS << "+" << getOffset();
341    OS << '>';
342    break;
343  case MachineOperand::MO_TargetIndex:
344    OS << "<ti#" << getIndex();
345    if (getOffset()) OS << "+" << getOffset();
346    OS << '>';
347    break;
348  case MachineOperand::MO_JumpTableIndex:
349    OS << "<jt#" << getIndex() << '>';
350    break;
351  case MachineOperand::MO_GlobalAddress:
352    OS << "<ga:";
353    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
354    if (getOffset()) OS << "+" << getOffset();
355    OS << '>';
356    break;
357  case MachineOperand::MO_ExternalSymbol:
358    OS << "<es:" << getSymbolName();
359    if (getOffset()) OS << "+" << getOffset();
360    OS << '>';
361    break;
362  case MachineOperand::MO_BlockAddress:
363    OS << '<';
364    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
365    if (getOffset()) OS << "+" << getOffset();
366    OS << '>';
367    break;
368  case MachineOperand::MO_RegisterMask:
369    OS << "<regmask>";
370    break;
371  case MachineOperand::MO_Metadata:
372    OS << '<';
373    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
374    OS << '>';
375    break;
376  case MachineOperand::MO_MCSymbol:
377    OS << "<MCSym=" << *getMCSymbol() << '>';
378    break;
379  }
380
381  if (unsigned TF = getTargetFlags())
382    OS << "[TF=" << TF << ']';
383}
384
385//===----------------------------------------------------------------------===//
386// MachineMemOperand Implementation
387//===----------------------------------------------------------------------===//
388
389/// getAddrSpace - Return the LLVM IR address space number that this pointer
390/// points into.
391unsigned MachinePointerInfo::getAddrSpace() const {
392  if (V == 0) return 0;
393  return cast<PointerType>(V->getType())->getAddressSpace();
394}
395
396/// getConstantPool - Return a MachinePointerInfo record that refers to the
397/// constant pool.
398MachinePointerInfo MachinePointerInfo::getConstantPool() {
399  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
400}
401
402/// getFixedStack - Return a MachinePointerInfo record that refers to the
403/// the specified FrameIndex.
404MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
405  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
406}
407
408MachinePointerInfo MachinePointerInfo::getJumpTable() {
409  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
410}
411
412MachinePointerInfo MachinePointerInfo::getGOT() {
413  return MachinePointerInfo(PseudoSourceValue::getGOT());
414}
415
416MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
417  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
418}
419
420MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
421                                     uint64_t s, unsigned int a,
422                                     const MDNode *TBAAInfo,
423                                     const MDNode *Ranges)
424  : PtrInfo(ptrinfo), Size(s),
425    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
426    TBAAInfo(TBAAInfo), Ranges(Ranges) {
427  assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
428         "invalid pointer value");
429  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
430  assert((isLoad() || isStore()) && "Not a load/store!");
431}
432
433/// Profile - Gather unique data for the object.
434///
435void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
436  ID.AddInteger(getOffset());
437  ID.AddInteger(Size);
438  ID.AddPointer(getValue());
439  ID.AddInteger(Flags);
440}
441
442void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
443  // The Value and Offset may differ due to CSE. But the flags and size
444  // should be the same.
445  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
446  assert(MMO->getSize() == getSize() && "Size mismatch!");
447
448  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
449    // Update the alignment value.
450    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
451      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
452    // Also update the base and offset, because the new alignment may
453    // not be applicable with the old ones.
454    PtrInfo = MMO->PtrInfo;
455  }
456}
457
458/// getAlignment - Return the minimum known alignment in bytes of the
459/// actual memory reference.
460uint64_t MachineMemOperand::getAlignment() const {
461  return MinAlign(getBaseAlignment(), getOffset());
462}
463
464raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
465  assert((MMO.isLoad() || MMO.isStore()) &&
466         "SV has to be a load, store or both.");
467
468  if (MMO.isVolatile())
469    OS << "Volatile ";
470
471  if (MMO.isLoad())
472    OS << "LD";
473  if (MMO.isStore())
474    OS << "ST";
475  OS << MMO.getSize();
476
477  // Print the address information.
478  OS << "[";
479  if (!MMO.getValue())
480    OS << "<unknown>";
481  else
482    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
483
484  // If the alignment of the memory reference itself differs from the alignment
485  // of the base pointer, print the base alignment explicitly, next to the base
486  // pointer.
487  if (MMO.getBaseAlignment() != MMO.getAlignment())
488    OS << "(align=" << MMO.getBaseAlignment() << ")";
489
490  if (MMO.getOffset() != 0)
491    OS << "+" << MMO.getOffset();
492  OS << "]";
493
494  // Print the alignment of the reference.
495  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
496      MMO.getBaseAlignment() != MMO.getSize())
497    OS << "(align=" << MMO.getAlignment() << ")";
498
499  // Print TBAA info.
500  if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
501    OS << "(tbaa=";
502    if (TBAAInfo->getNumOperands() > 0)
503      WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
504    else
505      OS << "<unknown>";
506    OS << ")";
507  }
508
509  // Print nontemporal info.
510  if (MMO.isNonTemporal())
511    OS << "(nontemporal)";
512
513  return OS;
514}
515
516//===----------------------------------------------------------------------===//
517// MachineInstr Implementation
518//===----------------------------------------------------------------------===//
519
520void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
521  if (MCID->ImplicitDefs)
522    for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
523      addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
524  if (MCID->ImplicitUses)
525    for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
526      addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
527}
528
529/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
530/// implicit operands. It reserves space for the number of operands specified by
531/// the MCInstrDesc.
532MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
533                           const DebugLoc dl, bool NoImp)
534  : MCID(&tid), Parent(0), Operands(0), NumOperands(0),
535    Flags(0), AsmPrinterFlags(0),
536    NumMemRefs(0), MemRefs(0), debugLoc(dl) {
537  // Reserve space for the expected number of operands.
538  if (unsigned NumOps = MCID->getNumOperands() +
539    MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
540    CapOperands = OperandCapacity::get(NumOps);
541    Operands = MF.allocateOperandArray(CapOperands);
542  }
543
544  if (!NoImp)
545    addImplicitDefUseOperands(MF);
546}
547
548/// MachineInstr ctor - Copies MachineInstr arg exactly
549///
550MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
551  : MCID(&MI.getDesc()), Parent(0), Operands(0), NumOperands(0),
552    Flags(0), AsmPrinterFlags(0),
553    NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
554    debugLoc(MI.getDebugLoc()) {
555  CapOperands = OperandCapacity::get(MI.getNumOperands());
556  Operands = MF.allocateOperandArray(CapOperands);
557
558  // Copy operands.
559  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
560    addOperand(MF, MI.getOperand(i));
561
562  // Copy all the sensible flags.
563  setFlags(MI.Flags);
564}
565
566/// getRegInfo - If this instruction is embedded into a MachineFunction,
567/// return the MachineRegisterInfo object for the current function, otherwise
568/// return null.
569MachineRegisterInfo *MachineInstr::getRegInfo() {
570  if (MachineBasicBlock *MBB = getParent())
571    return &MBB->getParent()->getRegInfo();
572  return 0;
573}
574
575/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
576/// this instruction from their respective use lists.  This requires that the
577/// operands already be on their use lists.
578void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
579  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
580    if (Operands[i].isReg())
581      MRI.removeRegOperandFromUseList(&Operands[i]);
582}
583
584/// AddRegOperandsToUseLists - Add all of the register operands in
585/// this instruction from their respective use lists.  This requires that the
586/// operands not be on their use lists yet.
587void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
588  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
589    if (Operands[i].isReg())
590      MRI.addRegOperandToUseList(&Operands[i]);
591}
592
593void MachineInstr::addOperand(const MachineOperand &Op) {
594  MachineBasicBlock *MBB = getParent();
595  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
596  MachineFunction *MF = MBB->getParent();
597  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
598  addOperand(*MF, Op);
599}
600
601/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
602/// ranges. If MRI is non-null also update use-def chains.
603static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
604                         unsigned NumOps, MachineRegisterInfo *MRI) {
605  if (MRI)
606    return MRI->moveOperands(Dst, Src, NumOps);
607
608  // Here it would be convenient to call memmove, so that isn't allowed because
609  // MachineOperand has a constructor and so isn't a POD type.
610  if (Dst < Src)
611    for (unsigned i = 0; i != NumOps; ++i)
612      new (Dst + i) MachineOperand(Src[i]);
613  else
614    for (unsigned i = NumOps; i ; --i)
615      new (Dst + i - 1) MachineOperand(Src[i - 1]);
616}
617
618/// addOperand - Add the specified operand to the instruction.  If it is an
619/// implicit operand, it is added to the end of the operand list.  If it is
620/// an explicit operand it is added at the end of the explicit operand list
621/// (before the first implicit operand).
622void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
623  assert(MCID && "Cannot add operands before providing an instr descriptor");
624
625  // Check if we're adding one of our existing operands.
626  if (&Op >= Operands && &Op < Operands + NumOperands) {
627    // This is unusual: MI->addOperand(MI->getOperand(i)).
628    // If adding Op requires reallocating or moving existing operands around,
629    // the Op reference could go stale. Support it by copying Op.
630    MachineOperand CopyOp(Op);
631    return addOperand(MF, CopyOp);
632  }
633
634  // Find the insert location for the new operand.  Implicit registers go at
635  // the end, everything else goes before the implicit regs.
636  //
637  // FIXME: Allow mixed explicit and implicit operands on inline asm.
638  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
639  // implicit-defs, but they must not be moved around.  See the FIXME in
640  // InstrEmitter.cpp.
641  unsigned OpNo = getNumOperands();
642  bool isImpReg = Op.isReg() && Op.isImplicit();
643  if (!isImpReg && !isInlineAsm()) {
644    while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
645      --OpNo;
646      assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
647    }
648  }
649
650#ifndef NDEBUG
651  bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
652  // OpNo now points as the desired insertion point.  Unless this is a variadic
653  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
654  // RegMask operands go between the explicit and implicit operands.
655  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
656          OpNo < MCID->getNumOperands() || isMetaDataOp) &&
657         "Trying to add an operand to a machine instr that is already done!");
658#endif
659
660  MachineRegisterInfo *MRI = getRegInfo();
661
662  // Determine if the Operands array needs to be reallocated.
663  // Save the old capacity and operand array.
664  OperandCapacity OldCap = CapOperands;
665  MachineOperand *OldOperands = Operands;
666  if (!OldOperands || OldCap.getSize() == getNumOperands()) {
667    CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
668    Operands = MF.allocateOperandArray(CapOperands);
669    // Move the operands before the insertion point.
670    if (OpNo)
671      moveOperands(Operands, OldOperands, OpNo, MRI);
672  }
673
674  // Move the operands following the insertion point.
675  if (OpNo != NumOperands)
676    moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
677                 MRI);
678  ++NumOperands;
679
680  // Deallocate the old operand array.
681  if (OldOperands != Operands && OldOperands)
682    MF.deallocateOperandArray(OldCap, OldOperands);
683
684  // Copy Op into place. It still needs to be inserted into the MRI use lists.
685  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
686  NewMO->ParentMI = this;
687
688  // When adding a register operand, tell MRI about it.
689  if (NewMO->isReg()) {
690    // Ensure isOnRegUseList() returns false, regardless of Op's status.
691    NewMO->Contents.Reg.Prev = 0;
692    // Ignore existing ties. This is not a property that can be copied.
693    NewMO->TiedTo = 0;
694    // Add the new operand to MRI, but only for instructions in an MBB.
695    if (MRI)
696      MRI->addRegOperandToUseList(NewMO);
697    // The MCID operand information isn't accurate until we start adding
698    // explicit operands. The implicit operands are added first, then the
699    // explicits are inserted before them.
700    if (!isImpReg) {
701      // Tie uses to defs as indicated in MCInstrDesc.
702      if (NewMO->isUse()) {
703        int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
704        if (DefIdx != -1)
705          tieOperands(DefIdx, OpNo);
706      }
707      // If the register operand is flagged as early, mark the operand as such.
708      if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
709        NewMO->setIsEarlyClobber(true);
710    }
711  }
712}
713
714/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
715/// fewer operand than it started with.
716///
717void MachineInstr::RemoveOperand(unsigned OpNo) {
718  assert(OpNo < getNumOperands() && "Invalid operand number");
719  untieRegOperand(OpNo);
720
721#ifndef NDEBUG
722  // Moving tied operands would break the ties.
723  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
724    if (Operands[i].isReg())
725      assert(!Operands[i].isTied() && "Cannot move tied operands");
726#endif
727
728  MachineRegisterInfo *MRI = getRegInfo();
729  if (MRI && Operands[OpNo].isReg())
730    MRI->removeRegOperandFromUseList(Operands + OpNo);
731
732  // Don't call the MachineOperand destructor. A lot of this code depends on
733  // MachineOperand having a trivial destructor anyway, and adding a call here
734  // wouldn't make it 'destructor-correct'.
735
736  if (unsigned N = NumOperands - 1 - OpNo)
737    moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
738  --NumOperands;
739}
740
741/// addMemOperand - Add a MachineMemOperand to the machine instruction.
742/// This function should be used only occasionally. The setMemRefs function
743/// is the primary method for setting up a MachineInstr's MemRefs list.
744void MachineInstr::addMemOperand(MachineFunction &MF,
745                                 MachineMemOperand *MO) {
746  mmo_iterator OldMemRefs = MemRefs;
747  unsigned OldNumMemRefs = NumMemRefs;
748
749  unsigned NewNum = NumMemRefs + 1;
750  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
751
752  std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
753  NewMemRefs[NewNum - 1] = MO;
754  setMemRefs(NewMemRefs, NewMemRefs + NewNum);
755}
756
757bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
758  assert(!isBundledWithPred() && "Must be called on bundle header");
759  for (MachineBasicBlock::const_instr_iterator MII = this;; ++MII) {
760    if (MII->getDesc().getFlags() & Mask) {
761      if (Type == AnyInBundle)
762        return true;
763    } else {
764      if (Type == AllInBundle && !MII->isBundle())
765        return false;
766    }
767    // This was the last instruction in the bundle.
768    if (!MII->isBundledWithSucc())
769      return Type == AllInBundle;
770  }
771}
772
773bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
774                                 MICheckType Check) const {
775  // If opcodes or number of operands are not the same then the two
776  // instructions are obviously not identical.
777  if (Other->getOpcode() != getOpcode() ||
778      Other->getNumOperands() != getNumOperands())
779    return false;
780
781  if (isBundle()) {
782    // Both instructions are bundles, compare MIs inside the bundle.
783    MachineBasicBlock::const_instr_iterator I1 = *this;
784    MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
785    MachineBasicBlock::const_instr_iterator I2 = *Other;
786    MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
787    while (++I1 != E1 && I1->isInsideBundle()) {
788      ++I2;
789      if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
790        return false;
791    }
792  }
793
794  // Check operands to make sure they match.
795  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
796    const MachineOperand &MO = getOperand(i);
797    const MachineOperand &OMO = Other->getOperand(i);
798    if (!MO.isReg()) {
799      if (!MO.isIdenticalTo(OMO))
800        return false;
801      continue;
802    }
803
804    // Clients may or may not want to ignore defs when testing for equality.
805    // For example, machine CSE pass only cares about finding common
806    // subexpressions, so it's safe to ignore virtual register defs.
807    if (MO.isDef()) {
808      if (Check == IgnoreDefs)
809        continue;
810      else if (Check == IgnoreVRegDefs) {
811        if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
812            TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
813          if (MO.getReg() != OMO.getReg())
814            return false;
815      } else {
816        if (!MO.isIdenticalTo(OMO))
817          return false;
818        if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
819          return false;
820      }
821    } else {
822      if (!MO.isIdenticalTo(OMO))
823        return false;
824      if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
825        return false;
826    }
827  }
828  // If DebugLoc does not match then two dbg.values are not identical.
829  if (isDebugValue())
830    if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
831        && getDebugLoc() != Other->getDebugLoc())
832      return false;
833  return true;
834}
835
836MachineInstr *MachineInstr::removeFromParent() {
837  assert(getParent() && "Not embedded in a basic block!");
838  return getParent()->remove(this);
839}
840
841MachineInstr *MachineInstr::removeFromBundle() {
842  assert(getParent() && "Not embedded in a basic block!");
843  return getParent()->remove_instr(this);
844}
845
846void MachineInstr::eraseFromParent() {
847  assert(getParent() && "Not embedded in a basic block!");
848  getParent()->erase(this);
849}
850
851void MachineInstr::eraseFromBundle() {
852  assert(getParent() && "Not embedded in a basic block!");
853  getParent()->erase_instr(this);
854}
855
856/// getNumExplicitOperands - Returns the number of non-implicit operands.
857///
858unsigned MachineInstr::getNumExplicitOperands() const {
859  unsigned NumOperands = MCID->getNumOperands();
860  if (!MCID->isVariadic())
861    return NumOperands;
862
863  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
864    const MachineOperand &MO = getOperand(i);
865    if (!MO.isReg() || !MO.isImplicit())
866      NumOperands++;
867  }
868  return NumOperands;
869}
870
871void MachineInstr::bundleWithPred() {
872  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
873  setFlag(BundledPred);
874  MachineBasicBlock::instr_iterator Pred = this;
875  --Pred;
876  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
877  Pred->setFlag(BundledSucc);
878}
879
880void MachineInstr::bundleWithSucc() {
881  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
882  setFlag(BundledSucc);
883  MachineBasicBlock::instr_iterator Succ = this;
884  ++Succ;
885  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
886  Succ->setFlag(BundledPred);
887}
888
889void MachineInstr::unbundleFromPred() {
890  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
891  clearFlag(BundledPred);
892  MachineBasicBlock::instr_iterator Pred = this;
893  --Pred;
894  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
895  Pred->clearFlag(BundledSucc);
896}
897
898void MachineInstr::unbundleFromSucc() {
899  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
900  clearFlag(BundledSucc);
901  MachineBasicBlock::instr_iterator Succ = this;
902  ++Succ;
903  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
904  Succ->clearFlag(BundledPred);
905}
906
907bool MachineInstr::isStackAligningInlineAsm() const {
908  if (isInlineAsm()) {
909    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
910    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
911      return true;
912  }
913  return false;
914}
915
916InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
917  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
918  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
919  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
920}
921
922int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
923                                       unsigned *GroupNo) const {
924  assert(isInlineAsm() && "Expected an inline asm instruction");
925  assert(OpIdx < getNumOperands() && "OpIdx out of range");
926
927  // Ignore queries about the initial operands.
928  if (OpIdx < InlineAsm::MIOp_FirstOperand)
929    return -1;
930
931  unsigned Group = 0;
932  unsigned NumOps;
933  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
934       i += NumOps) {
935    const MachineOperand &FlagMO = getOperand(i);
936    // If we reach the implicit register operands, stop looking.
937    if (!FlagMO.isImm())
938      return -1;
939    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
940    if (i + NumOps > OpIdx) {
941      if (GroupNo)
942        *GroupNo = Group;
943      return i;
944    }
945    ++Group;
946  }
947  return -1;
948}
949
950const TargetRegisterClass*
951MachineInstr::getRegClassConstraint(unsigned OpIdx,
952                                    const TargetInstrInfo *TII,
953                                    const TargetRegisterInfo *TRI) const {
954  assert(getParent() && "Can't have an MBB reference here!");
955  assert(getParent()->getParent() && "Can't have an MF reference here!");
956  const MachineFunction &MF = *getParent()->getParent();
957
958  // Most opcodes have fixed constraints in their MCInstrDesc.
959  if (!isInlineAsm())
960    return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
961
962  if (!getOperand(OpIdx).isReg())
963    return NULL;
964
965  // For tied uses on inline asm, get the constraint from the def.
966  unsigned DefIdx;
967  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
968    OpIdx = DefIdx;
969
970  // Inline asm stores register class constraints in the flag word.
971  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
972  if (FlagIdx < 0)
973    return NULL;
974
975  unsigned Flag = getOperand(FlagIdx).getImm();
976  unsigned RCID;
977  if (InlineAsm::hasRegClassConstraint(Flag, RCID))
978    return TRI->getRegClass(RCID);
979
980  // Assume that all registers in a memory operand are pointers.
981  if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
982    return TRI->getPointerRegClass(MF);
983
984  return NULL;
985}
986
987/// Return the number of instructions inside the MI bundle, not counting the
988/// header instruction.
989unsigned MachineInstr::getBundleSize() const {
990  MachineBasicBlock::const_instr_iterator I = this;
991  unsigned Size = 0;
992  while (I->isBundledWithSucc())
993    ++Size, ++I;
994  return Size;
995}
996
997/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
998/// the specific register or -1 if it is not found. It further tightens
999/// the search criteria to a use that kills the register if isKill is true.
1000int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1001                                          const TargetRegisterInfo *TRI) const {
1002  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1003    const MachineOperand &MO = getOperand(i);
1004    if (!MO.isReg() || !MO.isUse())
1005      continue;
1006    unsigned MOReg = MO.getReg();
1007    if (!MOReg)
1008      continue;
1009    if (MOReg == Reg ||
1010        (TRI &&
1011         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1012         TargetRegisterInfo::isPhysicalRegister(Reg) &&
1013         TRI->isSubRegister(MOReg, Reg)))
1014      if (!isKill || MO.isKill())
1015        return i;
1016  }
1017  return -1;
1018}
1019
1020/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1021/// indicating if this instruction reads or writes Reg. This also considers
1022/// partial defines.
1023std::pair<bool,bool>
1024MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1025                                         SmallVectorImpl<unsigned> *Ops) const {
1026  bool PartDef = false; // Partial redefine.
1027  bool FullDef = false; // Full define.
1028  bool Use = false;
1029
1030  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1031    const MachineOperand &MO = getOperand(i);
1032    if (!MO.isReg() || MO.getReg() != Reg)
1033      continue;
1034    if (Ops)
1035      Ops->push_back(i);
1036    if (MO.isUse())
1037      Use |= !MO.isUndef();
1038    else if (MO.getSubReg() && !MO.isUndef())
1039      // A partial <def,undef> doesn't count as reading the register.
1040      PartDef = true;
1041    else
1042      FullDef = true;
1043  }
1044  // A partial redefine uses Reg unless there is also a full define.
1045  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1046}
1047
1048/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1049/// the specified register or -1 if it is not found. If isDead is true, defs
1050/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1051/// also checks if there is a def of a super-register.
1052int
1053MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1054                                        const TargetRegisterInfo *TRI) const {
1055  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1056  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1057    const MachineOperand &MO = getOperand(i);
1058    // Accept regmask operands when Overlap is set.
1059    // Ignore them when looking for a specific def operand (Overlap == false).
1060    if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1061      return i;
1062    if (!MO.isReg() || !MO.isDef())
1063      continue;
1064    unsigned MOReg = MO.getReg();
1065    bool Found = (MOReg == Reg);
1066    if (!Found && TRI && isPhys &&
1067        TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1068      if (Overlap)
1069        Found = TRI->regsOverlap(MOReg, Reg);
1070      else
1071        Found = TRI->isSubRegister(MOReg, Reg);
1072    }
1073    if (Found && (!isDead || MO.isDead()))
1074      return i;
1075  }
1076  return -1;
1077}
1078
1079/// findFirstPredOperandIdx() - Find the index of the first operand in the
1080/// operand list that is used to represent the predicate. It returns -1 if
1081/// none is found.
1082int MachineInstr::findFirstPredOperandIdx() const {
1083  // Don't call MCID.findFirstPredOperandIdx() because this variant
1084  // is sometimes called on an instruction that's not yet complete, and
1085  // so the number of operands is less than the MCID indicates. In
1086  // particular, the PTX target does this.
1087  const MCInstrDesc &MCID = getDesc();
1088  if (MCID.isPredicable()) {
1089    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1090      if (MCID.OpInfo[i].isPredicate())
1091        return i;
1092  }
1093
1094  return -1;
1095}
1096
1097// MachineOperand::TiedTo is 4 bits wide.
1098const unsigned TiedMax = 15;
1099
1100/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1101///
1102/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1103/// field. TiedTo can have these values:
1104///
1105/// 0:              Operand is not tied to anything.
1106/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1107/// TiedMax:        Tied to an operand >= TiedMax-1.
1108///
1109/// The tied def must be one of the first TiedMax operands on a normal
1110/// instruction. INLINEASM instructions allow more tied defs.
1111///
1112void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1113  MachineOperand &DefMO = getOperand(DefIdx);
1114  MachineOperand &UseMO = getOperand(UseIdx);
1115  assert(DefMO.isDef() && "DefIdx must be a def operand");
1116  assert(UseMO.isUse() && "UseIdx must be a use operand");
1117  assert(!DefMO.isTied() && "Def is already tied to another use");
1118  assert(!UseMO.isTied() && "Use is already tied to another def");
1119
1120  if (DefIdx < TiedMax)
1121    UseMO.TiedTo = DefIdx + 1;
1122  else {
1123    // Inline asm can use the group descriptors to find tied operands, but on
1124    // normal instruction, the tied def must be within the first TiedMax
1125    // operands.
1126    assert(isInlineAsm() && "DefIdx out of range");
1127    UseMO.TiedTo = TiedMax;
1128  }
1129
1130  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1131  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1132}
1133
1134/// Given the index of a tied register operand, find the operand it is tied to.
1135/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1136/// which must exist.
1137unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1138  const MachineOperand &MO = getOperand(OpIdx);
1139  assert(MO.isTied() && "Operand isn't tied");
1140
1141  // Normally TiedTo is in range.
1142  if (MO.TiedTo < TiedMax)
1143    return MO.TiedTo - 1;
1144
1145  // Uses on normal instructions can be out of range.
1146  if (!isInlineAsm()) {
1147    // Normal tied defs must be in the 0..TiedMax-1 range.
1148    if (MO.isUse())
1149      return TiedMax - 1;
1150    // MO is a def. Search for the tied use.
1151    for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1152      const MachineOperand &UseMO = getOperand(i);
1153      if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1154        return i;
1155    }
1156    llvm_unreachable("Can't find tied use");
1157  }
1158
1159  // Now deal with inline asm by parsing the operand group descriptor flags.
1160  // Find the beginning of each operand group.
1161  SmallVector<unsigned, 8> GroupIdx;
1162  unsigned OpIdxGroup = ~0u;
1163  unsigned NumOps;
1164  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1165       i += NumOps) {
1166    const MachineOperand &FlagMO = getOperand(i);
1167    assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1168    unsigned CurGroup = GroupIdx.size();
1169    GroupIdx.push_back(i);
1170    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1171    // OpIdx belongs to this operand group.
1172    if (OpIdx > i && OpIdx < i + NumOps)
1173      OpIdxGroup = CurGroup;
1174    unsigned TiedGroup;
1175    if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1176      continue;
1177    // Operands in this group are tied to operands in TiedGroup which must be
1178    // earlier. Find the number of operands between the two groups.
1179    unsigned Delta = i - GroupIdx[TiedGroup];
1180
1181    // OpIdx is a use tied to TiedGroup.
1182    if (OpIdxGroup == CurGroup)
1183      return OpIdx - Delta;
1184
1185    // OpIdx is a def tied to this use group.
1186    if (OpIdxGroup == TiedGroup)
1187      return OpIdx + Delta;
1188  }
1189  llvm_unreachable("Invalid tied operand on inline asm");
1190}
1191
1192/// clearKillInfo - Clears kill flags on all operands.
1193///
1194void MachineInstr::clearKillInfo() {
1195  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1196    MachineOperand &MO = getOperand(i);
1197    if (MO.isReg() && MO.isUse())
1198      MO.setIsKill(false);
1199  }
1200}
1201
1202void MachineInstr::substituteRegister(unsigned FromReg,
1203                                      unsigned ToReg,
1204                                      unsigned SubIdx,
1205                                      const TargetRegisterInfo &RegInfo) {
1206  if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1207    if (SubIdx)
1208      ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1209    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1210      MachineOperand &MO = getOperand(i);
1211      if (!MO.isReg() || MO.getReg() != FromReg)
1212        continue;
1213      MO.substPhysReg(ToReg, RegInfo);
1214    }
1215  } else {
1216    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1217      MachineOperand &MO = getOperand(i);
1218      if (!MO.isReg() || MO.getReg() != FromReg)
1219        continue;
1220      MO.substVirtReg(ToReg, SubIdx, RegInfo);
1221    }
1222  }
1223}
1224
1225/// isSafeToMove - Return true if it is safe to move this instruction. If
1226/// SawStore is set to true, it means that there is a store (or call) between
1227/// the instruction's location and its intended destination.
1228bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1229                                AliasAnalysis *AA,
1230                                bool &SawStore) const {
1231  // Ignore stuff that we obviously can't move.
1232  //
1233  // Treat volatile loads as stores. This is not strictly necessary for
1234  // volatiles, but it is required for atomic loads. It is not allowed to move
1235  // a load across an atomic load with Ordering > Monotonic.
1236  if (mayStore() || isCall() ||
1237      (mayLoad() && hasOrderedMemoryRef())) {
1238    SawStore = true;
1239    return false;
1240  }
1241
1242  if (isLabel() || isDebugValue() ||
1243      isTerminator() || hasUnmodeledSideEffects())
1244    return false;
1245
1246  // See if this instruction does a load.  If so, we have to guarantee that the
1247  // loaded value doesn't change between the load and the its intended
1248  // destination. The check for isInvariantLoad gives the targe the chance to
1249  // classify the load as always returning a constant, e.g. a constant pool
1250  // load.
1251  if (mayLoad() && !isInvariantLoad(AA))
1252    // Otherwise, this is a real load.  If there is a store between the load and
1253    // end of block, we can't move it.
1254    return !SawStore;
1255
1256  return true;
1257}
1258
1259/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1260/// or volatile memory reference, or if the information describing the memory
1261/// reference is not available. Return false if it is known to have no ordered
1262/// memory references.
1263bool MachineInstr::hasOrderedMemoryRef() const {
1264  // An instruction known never to access memory won't have a volatile access.
1265  if (!mayStore() &&
1266      !mayLoad() &&
1267      !isCall() &&
1268      !hasUnmodeledSideEffects())
1269    return false;
1270
1271  // Otherwise, if the instruction has no memory reference information,
1272  // conservatively assume it wasn't preserved.
1273  if (memoperands_empty())
1274    return true;
1275
1276  // Check the memory reference information for ordered references.
1277  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1278    if (!(*I)->isUnordered())
1279      return true;
1280
1281  return false;
1282}
1283
1284/// isInvariantLoad - Return true if this instruction is loading from a
1285/// location whose value is invariant across the function.  For example,
1286/// loading a value from the constant pool or from the argument area
1287/// of a function if it does not change.  This should only return true of
1288/// *all* loads the instruction does are invariant (if it does multiple loads).
1289bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1290  // If the instruction doesn't load at all, it isn't an invariant load.
1291  if (!mayLoad())
1292    return false;
1293
1294  // If the instruction has lost its memoperands, conservatively assume that
1295  // it may not be an invariant load.
1296  if (memoperands_empty())
1297    return false;
1298
1299  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1300
1301  for (mmo_iterator I = memoperands_begin(),
1302       E = memoperands_end(); I != E; ++I) {
1303    if ((*I)->isVolatile()) return false;
1304    if ((*I)->isStore()) return false;
1305    if ((*I)->isInvariant()) return true;
1306
1307    if (const Value *V = (*I)->getValue()) {
1308      // A load from a constant PseudoSourceValue is invariant.
1309      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1310        if (PSV->isConstant(MFI))
1311          continue;
1312      // If we have an AliasAnalysis, ask it whether the memory is constant.
1313      if (AA && AA->pointsToConstantMemory(
1314                      AliasAnalysis::Location(V, (*I)->getSize(),
1315                                              (*I)->getTBAAInfo())))
1316        continue;
1317    }
1318
1319    // Otherwise assume conservatively.
1320    return false;
1321  }
1322
1323  // Everything checks out.
1324  return true;
1325}
1326
1327/// isConstantValuePHI - If the specified instruction is a PHI that always
1328/// merges together the same virtual register, return the register, otherwise
1329/// return 0.
1330unsigned MachineInstr::isConstantValuePHI() const {
1331  if (!isPHI())
1332    return 0;
1333  assert(getNumOperands() >= 3 &&
1334         "It's illegal to have a PHI without source operands");
1335
1336  unsigned Reg = getOperand(1).getReg();
1337  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1338    if (getOperand(i).getReg() != Reg)
1339      return 0;
1340  return Reg;
1341}
1342
1343bool MachineInstr::hasUnmodeledSideEffects() const {
1344  if (hasProperty(MCID::UnmodeledSideEffects))
1345    return true;
1346  if (isInlineAsm()) {
1347    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1348    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1349      return true;
1350  }
1351
1352  return false;
1353}
1354
1355/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1356///
1357bool MachineInstr::allDefsAreDead() const {
1358  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1359    const MachineOperand &MO = getOperand(i);
1360    if (!MO.isReg() || MO.isUse())
1361      continue;
1362    if (!MO.isDead())
1363      return false;
1364  }
1365  return true;
1366}
1367
1368/// copyImplicitOps - Copy implicit register operands from specified
1369/// instruction to this instruction.
1370void MachineInstr::copyImplicitOps(MachineFunction &MF,
1371                                   const MachineInstr *MI) {
1372  for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1373       i != e; ++i) {
1374    const MachineOperand &MO = MI->getOperand(i);
1375    if (MO.isReg() && MO.isImplicit())
1376      addOperand(MF, MO);
1377  }
1378}
1379
1380void MachineInstr::dump() const {
1381#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1382  dbgs() << "  " << *this;
1383#endif
1384}
1385
1386static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1387                         raw_ostream &CommentOS) {
1388  const LLVMContext &Ctx = MF->getFunction()->getContext();
1389  if (!DL.isUnknown()) {          // Print source line info.
1390    DIScope Scope(DL.getScope(Ctx));
1391    assert((!Scope || Scope.isScope()) &&
1392      "Scope of a DebugLoc should be null or a DIScope.");
1393    // Omit the directory, because it's likely to be long and uninteresting.
1394    if (Scope)
1395      CommentOS << Scope.getFilename();
1396    else
1397      CommentOS << "<unknown>";
1398    CommentOS << ':' << DL.getLine();
1399    if (DL.getCol() != 0)
1400      CommentOS << ':' << DL.getCol();
1401    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1402    if (!InlinedAtDL.isUnknown()) {
1403      CommentOS << " @[ ";
1404      printDebugLoc(InlinedAtDL, MF, CommentOS);
1405      CommentOS << " ]";
1406    }
1407  }
1408}
1409
1410void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
1411                         bool SkipOpers) const {
1412  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1413  const MachineFunction *MF = 0;
1414  const MachineRegisterInfo *MRI = 0;
1415  if (const MachineBasicBlock *MBB = getParent()) {
1416    MF = MBB->getParent();
1417    if (!TM && MF)
1418      TM = &MF->getTarget();
1419    if (MF)
1420      MRI = &MF->getRegInfo();
1421  }
1422
1423  // Save a list of virtual registers.
1424  SmallVector<unsigned, 8> VirtRegs;
1425
1426  // Print explicitly defined operands on the left of an assignment syntax.
1427  unsigned StartOp = 0, e = getNumOperands();
1428  for (; StartOp < e && getOperand(StartOp).isReg() &&
1429         getOperand(StartOp).isDef() &&
1430         !getOperand(StartOp).isImplicit();
1431       ++StartOp) {
1432    if (StartOp != 0) OS << ", ";
1433    getOperand(StartOp).print(OS, TM);
1434    unsigned Reg = getOperand(StartOp).getReg();
1435    if (TargetRegisterInfo::isVirtualRegister(Reg))
1436      VirtRegs.push_back(Reg);
1437  }
1438
1439  if (StartOp != 0)
1440    OS << " = ";
1441
1442  // Print the opcode name.
1443  if (TM && TM->getInstrInfo())
1444    OS << TM->getInstrInfo()->getName(getOpcode());
1445  else
1446    OS << "UNKNOWN";
1447
1448  if (SkipOpers)
1449    return;
1450
1451  // Print the rest of the operands.
1452  bool OmittedAnyCallClobbers = false;
1453  bool FirstOp = true;
1454  unsigned AsmDescOp = ~0u;
1455  unsigned AsmOpCount = 0;
1456
1457  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1458    // Print asm string.
1459    OS << " ";
1460    getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1461
1462    // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1463    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1464    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1465      OS << " [sideeffect]";
1466    if (ExtraInfo & InlineAsm::Extra_MayLoad)
1467      OS << " [mayload]";
1468    if (ExtraInfo & InlineAsm::Extra_MayStore)
1469      OS << " [maystore]";
1470    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1471      OS << " [alignstack]";
1472    if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1473      OS << " [attdialect]";
1474    if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1475      OS << " [inteldialect]";
1476
1477    StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1478    FirstOp = false;
1479  }
1480
1481
1482  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1483    const MachineOperand &MO = getOperand(i);
1484
1485    if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1486      VirtRegs.push_back(MO.getReg());
1487
1488    // Omit call-clobbered registers which aren't used anywhere. This makes
1489    // call instructions much less noisy on targets where calls clobber lots
1490    // of registers. Don't rely on MO.isDead() because we may be called before
1491    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1492    if (MF && isCall() &&
1493        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1494      unsigned Reg = MO.getReg();
1495      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1496        const MachineRegisterInfo &MRI = MF->getRegInfo();
1497        if (MRI.use_empty(Reg)) {
1498          bool HasAliasLive = false;
1499          for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
1500               AI.isValid(); ++AI) {
1501            unsigned AliasReg = *AI;
1502            if (!MRI.use_empty(AliasReg)) {
1503              HasAliasLive = true;
1504              break;
1505            }
1506          }
1507          if (!HasAliasLive) {
1508            OmittedAnyCallClobbers = true;
1509            continue;
1510          }
1511        }
1512      }
1513    }
1514
1515    if (FirstOp) FirstOp = false; else OS << ",";
1516    OS << " ";
1517    if (i < getDesc().NumOperands) {
1518      const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1519      if (MCOI.isPredicate())
1520        OS << "pred:";
1521      if (MCOI.isOptionalDef())
1522        OS << "opt:";
1523    }
1524    if (isDebugValue() && MO.isMetadata()) {
1525      // Pretty print DBG_VALUE instructions.
1526      const MDNode *MD = MO.getMetadata();
1527      if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1528        OS << "!\"" << MDS->getString() << '\"';
1529      else
1530        MO.print(OS, TM);
1531    } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1532      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1533    } else if (i == AsmDescOp && MO.isImm()) {
1534      // Pretty print the inline asm operand descriptor.
1535      OS << '$' << AsmOpCount++;
1536      unsigned Flag = MO.getImm();
1537      switch (InlineAsm::getKind(Flag)) {
1538      case InlineAsm::Kind_RegUse:             OS << ":[reguse"; break;
1539      case InlineAsm::Kind_RegDef:             OS << ":[regdef"; break;
1540      case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1541      case InlineAsm::Kind_Clobber:            OS << ":[clobber"; break;
1542      case InlineAsm::Kind_Imm:                OS << ":[imm"; break;
1543      case InlineAsm::Kind_Mem:                OS << ":[mem"; break;
1544      default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1545      }
1546
1547      unsigned RCID = 0;
1548      if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1549        if (TM)
1550          OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1551        else
1552          OS << ":RC" << RCID;
1553      }
1554
1555      unsigned TiedTo = 0;
1556      if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1557        OS << " tiedto:$" << TiedTo;
1558
1559      OS << ']';
1560
1561      // Compute the index of the next operand descriptor.
1562      AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1563    } else
1564      MO.print(OS, TM);
1565  }
1566
1567  // Briefly indicate whether any call clobbers were omitted.
1568  if (OmittedAnyCallClobbers) {
1569    if (!FirstOp) OS << ",";
1570    OS << " ...";
1571  }
1572
1573  bool HaveSemi = false;
1574  const unsigned PrintableFlags = FrameSetup;
1575  if (Flags & PrintableFlags) {
1576    if (!HaveSemi) OS << ";"; HaveSemi = true;
1577    OS << " flags: ";
1578
1579    if (Flags & FrameSetup)
1580      OS << "FrameSetup";
1581  }
1582
1583  if (!memoperands_empty()) {
1584    if (!HaveSemi) OS << ";"; HaveSemi = true;
1585
1586    OS << " mem:";
1587    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1588         i != e; ++i) {
1589      OS << **i;
1590      if (llvm::next(i) != e)
1591        OS << " ";
1592    }
1593  }
1594
1595  // Print the regclass of any virtual registers encountered.
1596  if (MRI && !VirtRegs.empty()) {
1597    if (!HaveSemi) OS << ";"; HaveSemi = true;
1598    for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1599      const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1600      OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1601      for (unsigned j = i+1; j != VirtRegs.size();) {
1602        if (MRI->getRegClass(VirtRegs[j]) != RC) {
1603          ++j;
1604          continue;
1605        }
1606        if (VirtRegs[i] != VirtRegs[j])
1607          OS << "," << PrintReg(VirtRegs[j]);
1608        VirtRegs.erase(VirtRegs.begin()+j);
1609      }
1610    }
1611  }
1612
1613  // Print debug location information.
1614  if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1615    if (!HaveSemi) OS << ";"; HaveSemi = true;
1616    DIVariable DV(getOperand(e - 1).getMetadata());
1617    OS << " line no:" <<  DV.getLineNumber();
1618    if (MDNode *InlinedAt = DV.getInlinedAt()) {
1619      DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1620      if (!InlinedAtDL.isUnknown()) {
1621        OS << " inlined @[ ";
1622        printDebugLoc(InlinedAtDL, MF, OS);
1623        OS << " ]";
1624      }
1625    }
1626  } else if (!debugLoc.isUnknown() && MF) {
1627    if (!HaveSemi) OS << ";"; HaveSemi = true;
1628    OS << " dbg:";
1629    printDebugLoc(debugLoc, MF, OS);
1630  }
1631
1632  OS << '\n';
1633}
1634
1635bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1636                                     const TargetRegisterInfo *RegInfo,
1637                                     bool AddIfNotFound) {
1638  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1639  bool hasAliases = isPhysReg &&
1640    MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1641  bool Found = false;
1642  SmallVector<unsigned,4> DeadOps;
1643  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1644    MachineOperand &MO = getOperand(i);
1645    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1646      continue;
1647    unsigned Reg = MO.getReg();
1648    if (!Reg)
1649      continue;
1650
1651    if (Reg == IncomingReg) {
1652      if (!Found) {
1653        if (MO.isKill())
1654          // The register is already marked kill.
1655          return true;
1656        if (isPhysReg && isRegTiedToDefOperand(i))
1657          // Two-address uses of physregs must not be marked kill.
1658          return true;
1659        MO.setIsKill();
1660        Found = true;
1661      }
1662    } else if (hasAliases && MO.isKill() &&
1663               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1664      // A super-register kill already exists.
1665      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1666        return true;
1667      if (RegInfo->isSubRegister(IncomingReg, Reg))
1668        DeadOps.push_back(i);
1669    }
1670  }
1671
1672  // Trim unneeded kill operands.
1673  while (!DeadOps.empty()) {
1674    unsigned OpIdx = DeadOps.back();
1675    if (getOperand(OpIdx).isImplicit())
1676      RemoveOperand(OpIdx);
1677    else
1678      getOperand(OpIdx).setIsKill(false);
1679    DeadOps.pop_back();
1680  }
1681
1682  // If not found, this means an alias of one of the operands is killed. Add a
1683  // new implicit operand if required.
1684  if (!Found && AddIfNotFound) {
1685    addOperand(MachineOperand::CreateReg(IncomingReg,
1686                                         false /*IsDef*/,
1687                                         true  /*IsImp*/,
1688                                         true  /*IsKill*/));
1689    return true;
1690  }
1691  return Found;
1692}
1693
1694void MachineInstr::clearRegisterKills(unsigned Reg,
1695                                      const TargetRegisterInfo *RegInfo) {
1696  if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1697    RegInfo = 0;
1698  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1699    MachineOperand &MO = getOperand(i);
1700    if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1701      continue;
1702    unsigned OpReg = MO.getReg();
1703    if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1704      MO.setIsKill(false);
1705  }
1706}
1707
1708bool MachineInstr::addRegisterDead(unsigned Reg,
1709                                   const TargetRegisterInfo *RegInfo,
1710                                   bool AddIfNotFound) {
1711  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1712  bool hasAliases = isPhysReg &&
1713    MCRegAliasIterator(Reg, RegInfo, false).isValid();
1714  bool Found = false;
1715  SmallVector<unsigned,4> DeadOps;
1716  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1717    MachineOperand &MO = getOperand(i);
1718    if (!MO.isReg() || !MO.isDef())
1719      continue;
1720    unsigned MOReg = MO.getReg();
1721    if (!MOReg)
1722      continue;
1723
1724    if (MOReg == Reg) {
1725      MO.setIsDead();
1726      Found = true;
1727    } else if (hasAliases && MO.isDead() &&
1728               TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1729      // There exists a super-register that's marked dead.
1730      if (RegInfo->isSuperRegister(Reg, MOReg))
1731        return true;
1732      if (RegInfo->isSubRegister(Reg, MOReg))
1733        DeadOps.push_back(i);
1734    }
1735  }
1736
1737  // Trim unneeded dead operands.
1738  while (!DeadOps.empty()) {
1739    unsigned OpIdx = DeadOps.back();
1740    if (getOperand(OpIdx).isImplicit())
1741      RemoveOperand(OpIdx);
1742    else
1743      getOperand(OpIdx).setIsDead(false);
1744    DeadOps.pop_back();
1745  }
1746
1747  // If not found, this means an alias of one of the operands is dead. Add a
1748  // new implicit operand if required.
1749  if (Found || !AddIfNotFound)
1750    return Found;
1751
1752  addOperand(MachineOperand::CreateReg(Reg,
1753                                       true  /*IsDef*/,
1754                                       true  /*IsImp*/,
1755                                       false /*IsKill*/,
1756                                       true  /*IsDead*/));
1757  return true;
1758}
1759
1760void MachineInstr::addRegisterDefined(unsigned Reg,
1761                                      const TargetRegisterInfo *RegInfo) {
1762  if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1763    MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1764    if (MO)
1765      return;
1766  } else {
1767    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1768      const MachineOperand &MO = getOperand(i);
1769      if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1770          MO.getSubReg() == 0)
1771        return;
1772    }
1773  }
1774  addOperand(MachineOperand::CreateReg(Reg,
1775                                       true  /*IsDef*/,
1776                                       true  /*IsImp*/));
1777}
1778
1779void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1780                                         const TargetRegisterInfo &TRI) {
1781  bool HasRegMask = false;
1782  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1783    MachineOperand &MO = getOperand(i);
1784    if (MO.isRegMask()) {
1785      HasRegMask = true;
1786      continue;
1787    }
1788    if (!MO.isReg() || !MO.isDef()) continue;
1789    unsigned Reg = MO.getReg();
1790    if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1791    bool Dead = true;
1792    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1793         I != E; ++I)
1794      if (TRI.regsOverlap(*I, Reg)) {
1795        Dead = false;
1796        break;
1797      }
1798    // If there are no uses, including partial uses, the def is dead.
1799    if (Dead) MO.setIsDead();
1800  }
1801
1802  // This is a call with a register mask operand.
1803  // Mask clobbers are always dead, so add defs for the non-dead defines.
1804  if (HasRegMask)
1805    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1806         I != E; ++I)
1807      addRegisterDefined(*I, &TRI);
1808}
1809
1810unsigned
1811MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1812  // Build up a buffer of hash code components.
1813  SmallVector<size_t, 8> HashComponents;
1814  HashComponents.reserve(MI->getNumOperands() + 1);
1815  HashComponents.push_back(MI->getOpcode());
1816  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1817    const MachineOperand &MO = MI->getOperand(i);
1818    if (MO.isReg() && MO.isDef() &&
1819        TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1820      continue;  // Skip virtual register defs.
1821
1822    HashComponents.push_back(hash_value(MO));
1823  }
1824  return hash_combine_range(HashComponents.begin(), HashComponents.end());
1825}
1826
1827void MachineInstr::emitError(StringRef Msg) const {
1828  // Find the source location cookie.
1829  unsigned LocCookie = 0;
1830  const MDNode *LocMD = 0;
1831  for (unsigned i = getNumOperands(); i != 0; --i) {
1832    if (getOperand(i-1).isMetadata() &&
1833        (LocMD = getOperand(i-1).getMetadata()) &&
1834        LocMD->getNumOperands() != 0) {
1835      if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1836        LocCookie = CI->getZExtValue();
1837        break;
1838      }
1839    }
1840  }
1841
1842  if (const MachineBasicBlock *MBB = getParent())
1843    if (const MachineFunction *MF = MBB->getParent())
1844      return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1845  report_fatal_error(Msg);
1846}
1847