MachineInstr.cpp revision 204642
1199989Srdivacky//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2199989Srdivacky// 3199989Srdivacky// The LLVM Compiler Infrastructure 4199989Srdivacky// 5199989Srdivacky// This file is distributed under the University of Illinois Open Source 6199989Srdivacky// License. See LICENSE.TXT for details. 7199989Srdivacky// 8199989Srdivacky//===----------------------------------------------------------------------===// 9199989Srdivacky// 10199989Srdivacky// Methods common to all machine instructions. 11199989Srdivacky// 12199989Srdivacky//===----------------------------------------------------------------------===// 13199989Srdivacky 14199989Srdivacky#include "llvm/CodeGen/MachineInstr.h" 15249423Sdim#include "llvm/Constants.h" 16205218Srdivacky#include "llvm/Function.h" 17199989Srdivacky#include "llvm/InlineAsm.h" 18263508Sdim#include "llvm/Type.h" 19199989Srdivacky#include "llvm/Value.h" 20199989Srdivacky#include "llvm/Assembly/Writer.h" 21249423Sdim#include "llvm/CodeGen/MachineConstantPool.h" 22201360Srdivacky#include "llvm/CodeGen/MachineFunction.h" 23243830Sdim#include "llvm/CodeGen/MachineMemOperand.h" 24207618Srdivacky#include "llvm/CodeGen/MachineRegisterInfo.h" 25199989Srdivacky#include "llvm/CodeGen/PseudoSourceValue.h" 26210299Sed#include "llvm/Target/TargetMachine.h" 27249423Sdim#include "llvm/Target/TargetInstrInfo.h" 28199989Srdivacky#include "llvm/Target/TargetInstrDesc.h" 29249423Sdim#include "llvm/Target/TargetRegisterInfo.h" 30199989Srdivacky#include "llvm/Analysis/AliasAnalysis.h" 31199989Srdivacky#include "llvm/Analysis/DebugInfo.h" 32199989Srdivacky#include "llvm/Support/Debug.h" 33199989Srdivacky#include "llvm/Support/ErrorHandling.h" 34199989Srdivacky#include "llvm/Support/LeakDetector.h" 35199989Srdivacky#include "llvm/Support/MathExtras.h" 36263508Sdim#include "llvm/Support/raw_ostream.h" 37249423Sdim#include "llvm/ADT/FoldingSet.h" 38249423Sdim#include "llvm/Metadata.h" 39249423Sdimusing namespace llvm; 40249423Sdim 41249423Sdim//===----------------------------------------------------------------------===// 42249423Sdim// MachineOperand Implementation 43249423Sdim//===----------------------------------------------------------------------===// 44249423Sdim 45249423Sdim/// AddRegOperandToRegInfo - Add this register operand to the specified 46249423Sdim/// MachineRegisterInfo. If it is null, then the next/prev fields should be 47249423Sdim/// explicitly nulled out. 48249423Sdimvoid MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { 49249423Sdim assert(isReg() && "Can only add reg operand to use lists"); 50249423Sdim 51249423Sdim // If the reginfo pointer is null, just explicitly null out or next/prev 52249423Sdim // pointers, to ensure they are not garbage. 53249423Sdim if (RegInfo == 0) { 54249423Sdim Contents.Reg.Prev = 0; 55218893Sdim Contents.Reg.Next = 0; 56199989Srdivacky return; 57199989Srdivacky } 58234353Sdim 59199989Srdivacky // Otherwise, add this operand to the head of the registers use/def list. 60199989Srdivacky MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg()); 61263508Sdim 62199989Srdivacky // For SSA values, we prefer to keep the definition at the start of the list. 63199989Srdivacky // we do this by skipping over the definition if it is at the head of the 64199989Srdivacky // list. 65199989Srdivacky if (*Head && (*Head)->isDef()) 66199989Srdivacky Head = &(*Head)->Contents.Reg.Next; 67199989Srdivacky 68199989Srdivacky Contents.Reg.Next = *Head; 69199989Srdivacky if (Contents.Reg.Next) { 70199989Srdivacky assert(getReg() == Contents.Reg.Next->getReg() && 71199989Srdivacky "Different regs on the same list!"); 72199989Srdivacky Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next; 73199989Srdivacky } 74199989Srdivacky 75199989Srdivacky Contents.Reg.Prev = Head; 76218893Sdim *Head = this; 77218893Sdim} 78218893Sdim 79218893Sdim/// RemoveRegOperandFromRegInfo - Remove this register operand from the 80218893Sdim/// MachineRegisterInfo it is linked with. 81218893Sdimvoid MachineOperand::RemoveRegOperandFromRegInfo() { 82218893Sdim assert(isOnRegUseList() && "Reg operand is not on a use list"); 83218893Sdim // Unlink this from the doubly linked list of operands. 84218893Sdim MachineOperand *NextOp = Contents.Reg.Next; 85218893Sdim *Contents.Reg.Prev = NextOp; 86218893Sdim if (NextOp) { 87218893Sdim assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!"); 88218893Sdim NextOp->Contents.Reg.Prev = Contents.Reg.Prev; 89218893Sdim } 90221345Sdim Contents.Reg.Prev = 0; 91218893Sdim Contents.Reg.Next = 0; 92263508Sdim} 93212904Sdim 94249423Sdimvoid MachineOperand::setReg(unsigned Reg) { 95218893Sdim if (getReg() == Reg) return; // No change. 96199989Srdivacky 97199989Srdivacky // Otherwise, we have to change the register. If this operand is embedded 98199989Srdivacky // into a machine function, we need to update the old and new register's 99199989Srdivacky // use/def lists. 100199989Srdivacky if (MachineInstr *MI = getParent()) 101263508Sdim if (MachineBasicBlock *MBB = MI->getParent()) 102199989Srdivacky if (MachineFunction *MF = MBB->getParent()) { 103249423Sdim RemoveRegOperandFromRegInfo(); 104243830Sdim Contents.Reg.RegNo = Reg; 105199989Srdivacky AddRegOperandToRegInfo(&MF->getRegInfo()); 106212904Sdim return; 107243830Sdim } 108243830Sdim 109218893Sdim // Otherwise, just change the register, no problem. :) 110199989Srdivacky Contents.Reg.RegNo = Reg; 111199989Srdivacky} 112199989Srdivacky 113199989Srdivacky/// ChangeToImmediate - Replace this operand with a new immediate operand of 114199989Srdivacky/// the specified value. If an operand is known to be an immediate already, 115199989Srdivacky/// the setImm method should be used. 116212904Sdimvoid MachineOperand::ChangeToImmediate(int64_t ImmVal) { 117199989Srdivacky // If this operand is currently a register operand, and if this is in a 118199989Srdivacky // function, deregister the operand from the register's use/def list. 119199989Srdivacky if (isReg() && getParent() && getParent()->getParent() && 120199989Srdivacky getParent()->getParent()->getParent()) 121199989Srdivacky RemoveRegOperandFromRegInfo(); 122199989Srdivacky 123199989Srdivacky OpKind = MO_Immediate; 124199989Srdivacky Contents.ImmVal = ImmVal; 125199989Srdivacky} 126199989Srdivacky 127199989Srdivacky/// ChangeToRegister - Replace this operand with a new register operand of 128199989Srdivacky/// the specified value. If an operand is known to be an register already, 129199989Srdivacky/// the setReg method should be used. 130199989Srdivackyvoid MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 131212904Sdim bool isKill, bool isDead, bool isUndef, 132243830Sdim bool isDebug) { 133212904Sdim // If this operand is already a register operand, use setReg to update the 134243830Sdim // register's use/def lists. 135199989Srdivacky if (isReg()) { 136218893Sdim assert(!isEarlyClobber()); 137218893Sdim setReg(Reg); 138199989Srdivacky } else { 139201360Srdivacky // Otherwise, change this to a register and set the reg#. 140199989Srdivacky OpKind = MO_Register; 141199989Srdivacky Contents.Reg.RegNo = Reg; 142201360Srdivacky 143212904Sdim // If this operand is embedded in a function, add the operand to the 144199989Srdivacky // register's use/def list. 145199989Srdivacky if (MachineInstr *MI = getParent()) 146199989Srdivacky if (MachineBasicBlock *MBB = MI->getParent()) 147199989Srdivacky if (MachineFunction *MF = MBB->getParent()) 148199989Srdivacky AddRegOperandToRegInfo(&MF->getRegInfo()); 149212904Sdim } 150243830Sdim 151199989Srdivacky IsDef = isDef; 152199989Srdivacky IsImp = isImp; 153199989Srdivacky IsKill = isKill; 154199989Srdivacky IsDead = isDead; 155199989Srdivacky IsUndef = isUndef; 156199989Srdivacky IsEarlyClobber = false; 157212904Sdim IsDebug = isDebug; 158212904Sdim SubReg = 0; 159199989Srdivacky} 160199989Srdivacky 161212904Sdim/// isIdenticalTo - Return true if this operand is identical to the specified 162212904Sdim/// operand. 163199989Srdivackybool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 164199989Srdivacky if (getType() != Other.getType() || 165199989Srdivacky getTargetFlags() != Other.getTargetFlags()) 166249423Sdim return false; 167199989Srdivacky 168199989Srdivacky switch (getType()) { 169218893Sdim default: llvm_unreachable("Unrecognized operand type"); 170218893Sdim case MachineOperand::MO_Register: 171199989Srdivacky return getReg() == Other.getReg() && isDef() == Other.isDef() && 172199989Srdivacky getSubReg() == Other.getSubReg(); 173212904Sdim case MachineOperand::MO_Immediate: 174199989Srdivacky return getImm() == Other.getImm(); 175199989Srdivacky case MachineOperand::MO_FPImmediate: 176199989Srdivacky return getFPImm() == Other.getFPImm(); 177199989Srdivacky case MachineOperand::MO_MachineBasicBlock: 178199989Srdivacky return getMBB() == Other.getMBB(); 179243830Sdim case MachineOperand::MO_FrameIndex: 180199989Srdivacky return getIndex() == Other.getIndex(); 181199989Srdivacky case MachineOperand::MO_ConstantPoolIndex: 182199989Srdivacky return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 183199989Srdivacky case MachineOperand::MO_JumpTableIndex: 184249423Sdim return getIndex() == Other.getIndex(); 185199989Srdivacky case MachineOperand::MO_GlobalAddress: 186249423Sdim return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 187199989Srdivacky case MachineOperand::MO_ExternalSymbol: 188199989Srdivacky return !strcmp(getSymbolName(), Other.getSymbolName()) && 189249423Sdim getOffset() == Other.getOffset(); 190249423Sdim case MachineOperand::MO_BlockAddress: 191199989Srdivacky return getBlockAddress() == Other.getBlockAddress(); 192199989Srdivacky } 193199989Srdivacky} 194199989Srdivacky 195249423Sdim/// print - Print the specified machine operand. 196199989Srdivacky/// 197212904Sdimvoid MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 198199989Srdivacky // If the instruction is embedded into a basic block, we can find the 199212904Sdim // target info for the instruction. 200199989Srdivacky if (!TM) 201199989Srdivacky if (const MachineInstr *MI = getParent()) 202249423Sdim if (const MachineBasicBlock *MBB = MI->getParent()) 203212904Sdim if (const MachineFunction *MF = MBB->getParent()) 204212904Sdim TM = &MF->getTarget(); 205212904Sdim 206234353Sdim switch (getType()) { 207201360Srdivacky case MachineOperand::MO_Register: 208212904Sdim if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) { 209199989Srdivacky OS << "%reg" << getReg(); 210199989Srdivacky } else { 211249423Sdim if (TM) 212218893Sdim OS << "%" << TM->getRegisterInfo()->get(getReg()).Name; 213199989Srdivacky else 214199989Srdivacky OS << "%physreg" << getReg(); 215199989Srdivacky } 216199989Srdivacky 217243830Sdim if (getSubReg() != 0) 218243830Sdim OS << ':' << getSubReg(); 219243830Sdim 220243830Sdim if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || 221243830Sdim isEarlyClobber()) { 222263508Sdim OS << '<'; 223212904Sdim bool NeedComma = false; 224249423Sdim if (isDef()) { 225212904Sdim if (NeedComma) OS << ','; 226212904Sdim if (isEarlyClobber()) 227212904Sdim OS << "earlyclobber,"; 228212904Sdim if (isImplicit()) 229218893Sdim OS << "imp-"; 230212904Sdim OS << "def"; 231212904Sdim NeedComma = true; 232249423Sdim } else if (isImplicit()) { 233249423Sdim OS << "imp-use"; 234212904Sdim NeedComma = true; 235212904Sdim } 236212904Sdim 237212904Sdim if (isKill() || isDead() || isUndef()) { 238212904Sdim if (NeedComma) OS << ','; 239212904Sdim if (isKill()) OS << "kill"; 240212904Sdim if (isDead()) OS << "dead"; 241249423Sdim if (isUndef()) { 242212904Sdim if (isKill() || isDead()) 243218893Sdim OS << ','; 244212904Sdim OS << "undef"; 245212904Sdim } 246212904Sdim } 247212904Sdim OS << '>'; 248212904Sdim } 249212904Sdim break; 250212904Sdim case MachineOperand::MO_Immediate: 251243830Sdim OS << getImm(); 252212904Sdim break; 253212904Sdim case MachineOperand::MO_FPImmediate: 254212904Sdim if (getFPImm()->getType()->isFloatTy()) 255212904Sdim OS << getFPImm()->getValueAPF().convertToFloat(); 256212904Sdim else 257212904Sdim OS << getFPImm()->getValueAPF().convertToDouble(); 258212904Sdim break; 259212904Sdim case MachineOperand::MO_MachineBasicBlock: 260243830Sdim OS << "<BB#" << getMBB()->getNumber() << ">"; 261212904Sdim break; 262218893Sdim case MachineOperand::MO_FrameIndex: 263212904Sdim OS << "<fi#" << getIndex() << '>'; 264212904Sdim break; 265212904Sdim case MachineOperand::MO_ConstantPoolIndex: 266212904Sdim OS << "<cp#" << getIndex(); 267212904Sdim if (getOffset()) OS << "+" << getOffset(); 268212904Sdim OS << '>'; 269218893Sdim break; 270212904Sdim case MachineOperand::MO_JumpTableIndex: 271249423Sdim OS << "<jt#" << getIndex() << '>'; 272218893Sdim break; 273249423Sdim case MachineOperand::MO_GlobalAddress: 274212904Sdim OS << "<ga:"; 275218893Sdim WriteAsOperand(OS, getGlobal(), /*PrintType=*/false); 276249423Sdim if (getOffset()) OS << "+" << getOffset(); 277212904Sdim OS << '>'; 278212904Sdim break; 279212904Sdim case MachineOperand::MO_ExternalSymbol: 280212904Sdim OS << "<es:" << getSymbolName(); 281249423Sdim if (getOffset()) OS << "+" << getOffset(); 282249423Sdim OS << '>'; 283212904Sdim break; 284212904Sdim case MachineOperand::MO_BlockAddress: 285263508Sdim OS << '<'; 286218893Sdim WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false); 287218893Sdim OS << '>'; 288212904Sdim break; 289249423Sdim case MachineOperand::MO_Metadata: 290223017Sdim OS << '<'; 291223017Sdim WriteAsOperand(OS, getMetadata(), /*PrintType=*/false); 292249423Sdim OS << '>'; 293223017Sdim break; 294223017Sdim default: 295249423Sdim llvm_unreachable("Unrecognized operand type"); 296224145Sdim } 297224145Sdim 298223017Sdim if (unsigned TF = getTargetFlags()) 299212904Sdim OS << "[TF=" << TF << ']'; 300218893Sdim} 301223017Sdim 302223017Sdim//===----------------------------------------------------------------------===// 303249423Sdim// MachineMemOperand Implementation 304223017Sdim//===----------------------------------------------------------------------===// 305223017Sdim 306223017SdimMachineMemOperand::MachineMemOperand(const Value *v, unsigned int f, 307224145Sdim int64_t o, uint64_t s, unsigned int a) 308243830Sdim : Offset(o), Size(s), V(v), 309243830Sdim Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)) { 310243830Sdim assert(getBaseAlignment() == a && "Alignment is not a power of 2!"); 311243830Sdim assert((isLoad() || isStore()) && "Not a load/store!"); 312243830Sdim} 313243830Sdim 314243830Sdim/// Profile - Gather unique data for the object. 315243830Sdim/// 316243830Sdimvoid MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 317243830Sdim ID.AddInteger(Offset); 318243830Sdim ID.AddInteger(Size); 319251662Sdim ID.AddPointer(V); 320243830Sdim ID.AddInteger(Flags); 321224145Sdim} 322224145Sdim 323249423Sdimvoid MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { 324249423Sdim // The Value and Offset may differ due to CSE. But the flags and size 325224145Sdim // should be the same. 326224145Sdim assert(MMO->getFlags() == getFlags() && "Flags mismatch!"); 327224145Sdim assert(MMO->getSize() == getSize() && "Size mismatch!"); 328224145Sdim 329212904Sdim if (MMO->getBaseAlignment() >= getBaseAlignment()) { 330212904Sdim // Update the alignment value. 331212904Sdim Flags = (Flags & ((1 << MOMaxBits) - 1)) | 332263508Sdim ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits); 333212904Sdim // Also update the base and offset, because the new alignment may 334249423Sdim // not be applicable with the old ones. 335218893Sdim V = MMO->getValue(); 336199989Srdivacky Offset = MMO->getOffset(); 337199989Srdivacky } 338199989Srdivacky} 339263508Sdim 340201360Srdivacky/// getAlignment - Return the minimum known alignment in bytes of the 341249423Sdim/// actual memory reference. 342199989Srdivackyuint64_t MachineMemOperand::getAlignment() const { 343212904Sdim return MinAlign(getBaseAlignment(), getOffset()); 344218893Sdim} 345212904Sdim 346212904Sdimraw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) { 347243830Sdim assert((MMO.isLoad() || MMO.isStore()) && 348218893Sdim "SV has to be a load, store or both."); 349199989Srdivacky 350199989Srdivacky if (MMO.isVolatile()) 351199989Srdivacky OS << "Volatile "; 352199989Srdivacky 353199989Srdivacky if (MMO.isLoad()) 354212904Sdim OS << "LD"; 355199989Srdivacky if (MMO.isStore()) 356199989Srdivacky OS << "ST"; 357212904Sdim OS << MMO.getSize(); 358249423Sdim 359249423Sdim // Print the address information. 360212904Sdim OS << "["; 361212904Sdim if (!MMO.getValue()) 362212904Sdim OS << "<unknown>"; 363212904Sdim else 364199989Srdivacky WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false); 365212904Sdim 366212904Sdim // If the alignment of the memory reference itself differs from the alignment 367212904Sdim // of the base pointer, print the base alignment explicitly, next to the base 368212904Sdim // pointer. 369212904Sdim if (MMO.getBaseAlignment() != MMO.getAlignment()) 370212904Sdim OS << "(align=" << MMO.getBaseAlignment() << ")"; 371234353Sdim 372234353Sdim if (MMO.getOffset() != 0) 373218893Sdim OS << "+" << MMO.getOffset(); 374212904Sdim OS << "]"; 375212904Sdim 376234353Sdim // Print the alignment of the reference. 377234353Sdim if (MMO.getBaseAlignment() != MMO.getAlignment() || 378199989Srdivacky MMO.getBaseAlignment() != MMO.getSize()) 379212904Sdim OS << "(align=" << MMO.getAlignment() << ")"; 380212904Sdim 381249423Sdim return OS; 382218893Sdim} 383212904Sdim 384212904Sdim//===----------------------------------------------------------------------===// 385234353Sdim// MachineInstr Implementation 386234353Sdim//===----------------------------------------------------------------------===// 387212904Sdim 388212904Sdim/// MachineInstr ctor - This constructor creates a dummy MachineInstr with 389212904Sdim/// TID NULL and no operands. 390234353SdimMachineInstr::MachineInstr() 391234353Sdim : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), 392212904Sdim Parent(0), debugLoc(DebugLoc::getUnknownLoc()) { 393199989Srdivacky // Make sure that we get added to a machine basicblock 394212904Sdim LeakDetector::addGarbageObject(this); 395212904Sdim} 396212904Sdim 397212904Sdimvoid MachineInstr::addImplicitDefUseOperands() { 398199989Srdivacky if (TID->ImplicitDefs) 399212904Sdim for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) 400249423Sdim addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 401243830Sdim if (TID->ImplicitUses) 402243830Sdim for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) 403243830Sdim addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 404243830Sdim} 405243830Sdim 406243830Sdim/// MachineInstr ctor - This constructor create a MachineInstr and add the 407243830Sdim/// implicit operands. It reserves space for number of operands specified by 408243830Sdim/// TargetInstrDesc or the numOperands if it is not zero. (for 409243830Sdim/// instructions with variable number of operands). 410243830SdimMachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) 411243830Sdim : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), 412243830Sdim MemRefs(0), MemRefsEnd(0), Parent(0), 413212904Sdim debugLoc(DebugLoc::getUnknownLoc()) { 414212904Sdim if (!NoImp && TID->getImplicitDefs()) 415212904Sdim for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 416199989Srdivacky NumImplicitOps++; 417212904Sdim if (!NoImp && TID->getImplicitUses()) 418212904Sdim for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 419212904Sdim NumImplicitOps++; 420212904Sdim Operands.reserve(NumImplicitOps + TID->getNumOperands()); 421212904Sdim if (!NoImp) 422212904Sdim addImplicitDefUseOperands(); 423212904Sdim // Make sure that we get added to a machine basicblock 424212904Sdim LeakDetector::addGarbageObject(this); 425212904Sdim} 426212904Sdim 427243830Sdim/// MachineInstr ctor - As above, but with a DebugLoc. 428201360SrdivackyMachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl, 429212904Sdim bool NoImp) 430212904Sdim : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), 431212904Sdim Parent(0), debugLoc(dl) { 432201360Srdivacky if (!NoImp && TID->getImplicitDefs()) 433212904Sdim for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 434212904Sdim NumImplicitOps++; 435212904Sdim if (!NoImp && TID->getImplicitUses()) 436212904Sdim for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 437199989Srdivacky NumImplicitOps++; 438212904Sdim Operands.reserve(NumImplicitOps + TID->getNumOperands()); 439212904Sdim if (!NoImp) 440218893Sdim addImplicitDefUseOperands(); 441212904Sdim // Make sure that we get added to a machine basicblock 442212904Sdim LeakDetector::addGarbageObject(this); 443212904Sdim} 444201360Srdivacky 445212904Sdim/// MachineInstr ctor - Work exactly the same as the ctor two above, except 446212904Sdim/// that the MachineInstr is created and added to the end of the specified 447212904Sdim/// basic block. 448212904Sdim/// 449212904SdimMachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid) 450212904Sdim : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), 451199989Srdivacky MemRefs(0), MemRefsEnd(0), Parent(0), 452212904Sdim debugLoc(DebugLoc::getUnknownLoc()) { 453212904Sdim assert(MBB && "Cannot use inserting ctor with null basic block!"); 454212904Sdim if (TID->ImplicitDefs) 455212904Sdim for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 456199989Srdivacky NumImplicitOps++; 457212904Sdim if (TID->ImplicitUses) 458218893Sdim for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 459218893Sdim NumImplicitOps++; 460199989Srdivacky Operands.reserve(NumImplicitOps + TID->getNumOperands()); 461199989Srdivacky addImplicitDefUseOperands(); 462212904Sdim // Make sure that we get added to a machine basicblock 463199989Srdivacky LeakDetector::addGarbageObject(this); 464212904Sdim MBB->push_back(this); // Add instruction to end of basic block! 465212904Sdim} 466212904Sdim 467199989Srdivacky/// MachineInstr ctor - As above, but with a DebugLoc. 468199989Srdivacky/// 469212904SdimMachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, 470212904Sdim const TargetInstrDesc &tid) 471263508Sdim : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), 472212904Sdim Parent(0), debugLoc(dl) { 473249423Sdim assert(MBB && "Cannot use inserting ctor with null basic block!"); 474212904Sdim if (TID->ImplicitDefs) 475212904Sdim for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 476212904Sdim NumImplicitOps++; 477218893Sdim if (TID->ImplicitUses) 478199989Srdivacky for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 479249423Sdim NumImplicitOps++; 480249423Sdim Operands.reserve(NumImplicitOps + TID->getNumOperands()); 481212904Sdim addImplicitDefUseOperands(); 482212904Sdim // Make sure that we get added to a machine basicblock 483212904Sdim LeakDetector::addGarbageObject(this); 484218893Sdim MBB->push_back(this); // Add instruction to end of basic block! 485212904Sdim} 486249423Sdim 487249423Sdim/// MachineInstr ctor - Copies MachineInstr arg exactly 488212904Sdim/// 489212904SdimMachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 490212904Sdim : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0), 491212904Sdim MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd), 492212904Sdim Parent(0), debugLoc(MI.getDebugLoc()) { 493212904Sdim Operands.reserve(MI.getNumOperands()); 494263508Sdim 495263508Sdim // Add operands 496218893Sdim for (unsigned i = 0; i != MI.getNumOperands(); ++i) 497212904Sdim addOperand(MI.getOperand(i)); 498212904Sdim NumImplicitOps = MI.NumImplicitOps; 499212904Sdim 500212904Sdim // Set parent to null. 501212904Sdim Parent = 0; 502212904Sdim 503212904Sdim LeakDetector::addGarbageObject(this); 504218893Sdim} 505212904Sdim 506212904SdimMachineInstr::~MachineInstr() { 507223017Sdim LeakDetector::removeGarbageObject(this); 508249423Sdim#ifndef NDEBUG 509224145Sdim for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 510249423Sdim assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 511223017Sdim assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 512223017Sdim "Reg operand def/use list corrupted"); 513249423Sdim } 514224145Sdim#endif 515224145Sdim} 516223017Sdim 517212904Sdim/// getRegInfo - If this instruction is embedded into a MachineFunction, 518224145Sdim/// return the MachineRegisterInfo object for the current function, otherwise 519212904Sdim/// return null. 520212904SdimMachineRegisterInfo *MachineInstr::getRegInfo() { 521263508Sdim if (MachineBasicBlock *MBB = getParent()) 522224145Sdim return &MBB->getParent()->getRegInfo(); 523224145Sdim return 0; 524224145Sdim} 525224145Sdim 526199989Srdivacky/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 527218893Sdim/// this instruction from their respective use lists. This requires that the 528199989Srdivacky/// operands already be on their use lists. 529199989Srdivackyvoid MachineInstr::RemoveRegOperandsFromUseLists() { 530199989Srdivacky for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 531218893Sdim if (Operands[i].isReg()) 532199989Srdivacky Operands[i].RemoveRegOperandFromRegInfo(); 533249423Sdim } 534249423Sdim} 535199989Srdivacky 536199989Srdivacky/// AddRegOperandsToUseLists - Add all of the register operands in 537212904Sdim/// this instruction from their respective use lists. This requires that the 538212904Sdim/// operands not be on their use lists yet. 539199989Srdivackyvoid MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { 540218893Sdim for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 541199989Srdivacky if (Operands[i].isReg()) 542199989Srdivacky Operands[i].AddRegOperandToRegInfo(&RegInfo); 543199989Srdivacky } 544218893Sdim} 545199989Srdivacky 546199989Srdivacky 547201360Srdivacky/// addOperand - Add the specified operand to the instruction. If it is an 548199989Srdivacky/// implicit operand, it is added to the end of the operand list. If it is 549212904Sdim/// an explicit operand it is added at the end of the explicit operand list 550199989Srdivacky/// (before the first implicit operand). 551263508Sdimvoid MachineInstr::addOperand(const MachineOperand &Op) { 552263508Sdim bool isImpReg = Op.isReg() && Op.isImplicit(); 553199989Srdivacky assert((isImpReg || !OperandsComplete()) && 554212904Sdim "Trying to add an operand to a machine instr that is already done!"); 555263508Sdim 556263508Sdim MachineRegisterInfo *RegInfo = getRegInfo(); 557201360Srdivacky 558218893Sdim // If we are adding the operand to the end of the list, our job is simpler. 559199989Srdivacky // This is true most of the time, so this is a reasonable optimization. 560199989Srdivacky if (isImpReg || NumImplicitOps == 0) { 561199989Srdivacky // We can only do this optimization if we know that the operand list won't 562199989Srdivacky // reallocate. 563199989Srdivacky if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) { 564243830Sdim Operands.push_back(Op); 565199989Srdivacky 566199989Srdivacky // Set the parent of the operand. 567199989Srdivacky Operands.back().ParentMI = this; 568199989Srdivacky 569199989Srdivacky // If the operand is a register, update the operand's use list. 570199989Srdivacky if (Op.isReg()) { 571199989Srdivacky Operands.back().AddRegOperandToRegInfo(RegInfo); 572243830Sdim // If the register operand is flagged as early, mark the operand as such 573199989Srdivacky unsigned OpNo = Operands.size() - 1; 574199989Srdivacky if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 575199989Srdivacky Operands[OpNo].setIsEarlyClobber(true); 576210299Sed } 577210299Sed return; 578210299Sed } 579210299Sed } 580210299Sed 581210299Sed // Otherwise, we have to insert a real operand before any implicit ones. 582210299Sed unsigned OpNo = Operands.size()-NumImplicitOps; 583210299Sed 584210299Sed // If this instruction isn't embedded into a function, then we don't need to 585210299Sed // update any operand lists. 586210299Sed if (RegInfo == 0) { 587210299Sed // Simple insertion, no reginfo update needed for other register operands. 588210299Sed Operands.insert(Operands.begin()+OpNo, Op); 589210299Sed Operands[OpNo].ParentMI = this; 590210299Sed 591199989Srdivacky // Do explicitly set the reginfo for this operand though, to ensure the 592210299Sed // next/prev fields are properly nulled out. 593210299Sed if (Operands[OpNo].isReg()) { 594210299Sed Operands[OpNo].AddRegOperandToRegInfo(0); 595210299Sed // If the register operand is flagged as early, mark the operand as such 596210299Sed if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 597210299Sed Operands[OpNo].setIsEarlyClobber(true); 598210299Sed } 599210299Sed 600210299Sed } else if (Operands.size()+1 <= Operands.capacity()) { 601249423Sdim // Otherwise, we have to remove register operands from their register use 602210299Sed // list, add the operand, then add the register operands back to their use 603210299Sed // list. This also must handle the case when the operand list reallocates 604210299Sed // to somewhere else. 605210299Sed 606210299Sed // If insertion of this operand won't cause reallocation of the operand 607210299Sed // list, just remove the implicit operands, add the operand, then re-add all 608210299Sed // the rest of the operands. 609210299Sed for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 610210299Sed assert(Operands[i].isReg() && "Should only be an implicit reg!"); 611210299Sed Operands[i].RemoveRegOperandFromRegInfo(); 612249423Sdim } 613210299Sed 614210299Sed // Add the operand. If it is a register, add it to the reg list. 615210299Sed Operands.insert(Operands.begin()+OpNo, Op); 616226633Sdim Operands[OpNo].ParentMI = this; 617210299Sed 618210299Sed if (Operands[OpNo].isReg()) { 619210299Sed Operands[OpNo].AddRegOperandToRegInfo(RegInfo); 620210299Sed // If the register operand is flagged as early, mark the operand as such 621210299Sed if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 622249423Sdim Operands[OpNo].setIsEarlyClobber(true); 623210299Sed } 624210299Sed 625210299Sed // Re-add all the implicit ops. 626210299Sed for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) { 627210299Sed assert(Operands[i].isReg() && "Should only be an implicit reg!"); 628210299Sed Operands[i].AddRegOperandToRegInfo(RegInfo); 629210299Sed } 630210299Sed } else { 631210299Sed // Otherwise, we will be reallocating the operand list. Remove all reg 632210299Sed // operands from their list, then readd them after the operand list is 633249423Sdim // reallocated. 634210299Sed RemoveRegOperandsFromUseLists(); 635210299Sed 636210299Sed Operands.insert(Operands.begin()+OpNo, Op); 637210299Sed Operands[OpNo].ParentMI = this; 638210299Sed 639210299Sed // Re-add all the operands. 640210299Sed AddRegOperandsToUseLists(*RegInfo); 641210299Sed 642210299Sed // If the register operand is flagged as early, mark the operand as such 643210299Sed if (Operands[OpNo].isReg() 644210299Sed && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 645210299Sed Operands[OpNo].setIsEarlyClobber(true); 646210299Sed } 647210299Sed} 648210299Sed 649210299Sed/// RemoveOperand - Erase an operand from an instruction, leaving it with one 650210299Sed/// fewer operand than it started with. 651210299Sed/// 652263508Sdimvoid MachineInstr::RemoveOperand(unsigned OpNo) { 653243830Sdim assert(OpNo < Operands.size() && "Invalid operand number"); 654243830Sdim 655210299Sed // Special case removing the last one. 656210299Sed if (OpNo == Operands.size()-1) { 657210299Sed // If needed, remove from the reg def/use list. 658210299Sed if (Operands.back().isReg() && Operands.back().isOnRegUseList()) 659210299Sed Operands.back().RemoveRegOperandFromRegInfo(); 660263508Sdim 661243830Sdim Operands.pop_back(); 662210299Sed return; 663210299Sed } 664210299Sed 665210299Sed // Otherwise, we are removing an interior operand. If we have reginfo to 666210299Sed // update, remove all operands that will be shifted down from their reg lists, 667210299Sed // move everything down, then re-add them. 668210299Sed MachineRegisterInfo *RegInfo = getRegInfo(); 669210299Sed if (RegInfo) { 670210299Sed for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 671210299Sed if (Operands[i].isReg()) 672210299Sed Operands[i].RemoveRegOperandFromRegInfo(); 673210299Sed } 674210299Sed } 675210299Sed 676210299Sed Operands.erase(Operands.begin()+OpNo); 677210299Sed 678210299Sed if (RegInfo) { 679263508Sdim for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 680243830Sdim if (Operands[i].isReg()) 681243830Sdim Operands[i].AddRegOperandToRegInfo(RegInfo); 682212904Sdim } 683212904Sdim } 684212904Sdim} 685212904Sdim 686210299Sed/// addMemOperand - Add a MachineMemOperand to the machine instruction. 687210299Sed/// This function should be used only occasionally. The setMemRefs function 688210299Sed/// is the primary method for setting up a MachineInstr's MemRefs list. 689210299Sedvoid MachineInstr::addMemOperand(MachineFunction &MF, 690210299Sed MachineMemOperand *MO) { 691210299Sed mmo_iterator OldMemRefs = MemRefs; 692210299Sed mmo_iterator OldMemRefsEnd = MemRefsEnd; 693210299Sed 694210299Sed size_t NewNum = (MemRefsEnd - MemRefs) + 1; 695249423Sdim mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum); 696210299Sed mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum; 697210299Sed 698210299Sed std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs); 699210299Sed NewMemRefs[NewNum - 1] = MO; 700210299Sed 701210299Sed MemRefs = NewMemRefs; 702210299Sed MemRefsEnd = NewMemRefsEnd; 703210299Sed} 704210299Sed 705210299Sedbool MachineInstr::isIdenticalTo(const MachineInstr *Other, 706210299Sed MICheckType Check) const { 707210299Sed if (Other->getOpcode() != getOpcode() || 708218893Sdim Other->getNumOperands() != getNumOperands()) 709210299Sed return false; 710210299Sed for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 711210299Sed const MachineOperand &MO = getOperand(i); 712218893Sdim const MachineOperand &OMO = Other->getOperand(i); 713219077Sdim if (Check != CheckDefs && MO.isReg() && MO.isDef()) { 714218893Sdim if (Check == IgnoreDefs) 715210299Sed continue; 716219077Sdim // Check == IgnoreVRegDefs 717219077Sdim if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) || 718219077Sdim TargetRegisterInfo::isPhysicalRegister(OMO.getReg())) 719219077Sdim if (MO.getReg() != OMO.getReg()) 720219077Sdim return false; 721218893Sdim } else if (!MO.isIdenticalTo(OMO)) 722219077Sdim return false; 723219077Sdim } 724210299Sed return true; 725263508Sdim} 726263508Sdim 727263508Sdim/// removeFromParent - This method unlinks 'this' from the containing basic 728263508Sdim/// block, and returns it, but does not delete it. 729263508SdimMachineInstr *MachineInstr::removeFromParent() { 730263508Sdim assert(getParent() && "Not embedded in a basic block!"); 731263508Sdim getParent()->remove(this); 732263508Sdim return this; 733218893Sdim} 734218893Sdim 735218893Sdim 736218893Sdim/// eraseFromParent - This method unlinks 'this' from the containing basic 737218893Sdim/// block, and deletes it. 738218893Sdimvoid MachineInstr::eraseFromParent() { 739218893Sdim assert(getParent() && "Not embedded in a basic block!"); 740218893Sdim getParent()->erase(this); 741218893Sdim} 742218893Sdim 743218893Sdim 744218893Sdim/// OperandComplete - Return true if it's illegal to add a new operand 745218893Sdim/// 746218893Sdimbool MachineInstr::OperandsComplete() const { 747218893Sdim unsigned short NumOperands = TID->getNumOperands(); 748218893Sdim if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands) 749218893Sdim return true; // Broken: we have all the operands of this instruction! 750218893Sdim return false; 751218893Sdim} 752218893Sdim 753218893Sdim/// getNumExplicitOperands - Returns the number of non-implicit operands. 754218893Sdim/// 755210299Sedunsigned MachineInstr::getNumExplicitOperands() const { 756218893Sdim unsigned NumOperands = TID->getNumOperands(); 757218893Sdim if (!TID->isVariadic()) 758218893Sdim return NumOperands; 759218893Sdim 760210299Sed for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) { 761210299Sed const MachineOperand &MO = getOperand(i); 762210299Sed if (!MO.isReg() || !MO.isImplicit()) 763243830Sdim NumOperands++; 764210299Sed } 765210299Sed return NumOperands; 766210299Sed} 767210299Sed 768210299Sed 769210299Sed/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 770210299Sed/// the specific register or -1 if it is not found. It further tightens 771210299Sed/// the search criteria to a use that kills the register if isKill is true. 772210299Sedint MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 773210299Sed const TargetRegisterInfo *TRI) const { 774210299Sed for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 775210299Sed const MachineOperand &MO = getOperand(i); 776210299Sed if (!MO.isReg() || !MO.isUse()) 777263508Sdim continue; 778243830Sdim unsigned MOReg = MO.getReg(); 779243830Sdim if (!MOReg) 780210299Sed continue; 781210299Sed if (MOReg == Reg || 782210299Sed (TRI && 783210299Sed TargetRegisterInfo::isPhysicalRegister(MOReg) && 784210299Sed TargetRegisterInfo::isPhysicalRegister(Reg) && 785210299Sed TRI->isSubRegister(MOReg, Reg))) 786210299Sed if (!isKill || MO.isKill()) 787210299Sed return i; 788249423Sdim } 789249423Sdim return -1; 790249423Sdim} 791210299Sed 792212904Sdim/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 793249423Sdim/// the specified register or -1 if it is not found. If isDead is true, defs 794210299Sed/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 795210299Sed/// also checks if there is a def of a super-register. 796210299Sedint MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, 797210299Sed const TargetRegisterInfo *TRI) const { 798210299Sed for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 799210299Sed const MachineOperand &MO = getOperand(i); 800210299Sed if (!MO.isReg() || !MO.isDef()) 801210299Sed continue; 802210299Sed unsigned MOReg = MO.getReg(); 803210299Sed if (MOReg == Reg || 804210299Sed (TRI && 805210299Sed TargetRegisterInfo::isPhysicalRegister(MOReg) && 806210299Sed TargetRegisterInfo::isPhysicalRegister(Reg) && 807210299Sed TRI->isSubRegister(MOReg, Reg))) 808210299Sed if (!isDead || MO.isDead()) 809210299Sed return i; 810210299Sed } 811210299Sed return -1; 812210299Sed} 813210299Sed 814210299Sed/// findFirstPredOperandIdx() - Find the index of the first operand in the 815210299Sed/// operand list that is used to represent the predicate. It returns -1 if 816210299Sed/// none is found. 817210299Sedint MachineInstr::findFirstPredOperandIdx() const { 818210299Sed const TargetInstrDesc &TID = getDesc(); 819210299Sed if (TID.isPredicable()) { 820210299Sed for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 821210299Sed if (TID.OpInfo[i].isPredicate()) 822210299Sed return i; 823210299Sed } 824210299Sed 825210299Sed return -1; 826210299Sed} 827210299Sed 828210299Sed/// isRegTiedToUseOperand - Given the index of a register def operand, 829210299Sed/// check if the register def is tied to a source operand, due to either 830210299Sed/// two-address elimination or inline assembly constraints. Returns the 831210299Sed/// first tied use operand index by reference is UseOpIdx is not null. 832210299Sedbool MachineInstr:: 833210299SedisRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const { 834210299Sed if (isInlineAsm()) { 835210299Sed assert(DefOpIdx >= 2); 836210299Sed const MachineOperand &MO = getOperand(DefOpIdx); 837210299Sed if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0) 838210299Sed return false; 839226633Sdim // Determine the actual operand index that corresponds to this index. 840226633Sdim unsigned DefNo = 0; 841226633Sdim unsigned DefPart = 0; 842226633Sdim for (unsigned i = 1, e = getNumOperands(); i < e; ) { 843226633Sdim const MachineOperand &FMO = getOperand(i); 844226633Sdim // After the normal asm operands there may be additional imp-def regs. 845226633Sdim if (!FMO.isImm()) 846226633Sdim return false; 847226633Sdim // Skip over this def. 848226633Sdim unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm()); 849226633Sdim unsigned PrevDef = i + 1; 850226633Sdim i = PrevDef + NumOps; 851210299Sed if (i > DefOpIdx) { 852210299Sed DefPart = DefOpIdx - PrevDef; 853210299Sed break; 854263765Sdim } 855210299Sed ++DefNo; 856210299Sed } 857249423Sdim for (unsigned i = 1, e = getNumOperands(); i != e; ++i) { 858210299Sed const MachineOperand &FMO = getOperand(i); 859210299Sed if (!FMO.isImm()) 860263765Sdim continue; 861263765Sdim if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse()) 862263765Sdim continue; 863263765Sdim unsigned Idx; 864263765Sdim if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) && 865263765Sdim Idx == DefNo) { 866263765Sdim if (UseOpIdx) 867263765Sdim *UseOpIdx = (unsigned)i + 1 + DefPart; 868210299Sed return true; 869210299Sed } 870210299Sed } 871210299Sed return false; 872234353Sdim } 873234353Sdim 874199989Srdivacky assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!"); 875199989Srdivacky const TargetInstrDesc &TID = getDesc(); 876234353Sdim for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { 877243830Sdim const MachineOperand &MO = getOperand(i); 878243830Sdim if (MO.isReg() && MO.isUse() && 879226633Sdim TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) { 880199989Srdivacky if (UseOpIdx) 881199989Srdivacky *UseOpIdx = (unsigned)i; 882207618Srdivacky return true; 883199989Srdivacky } 884199989Srdivacky } 885199989Srdivacky return false; 886199989Srdivacky} 887199989Srdivacky 888199989Srdivacky/// isRegTiedToDefOperand - Return true if the operand of the specified index 889199989Srdivacky/// is a register use and it is tied to an def operand. It also returns the def 890210299Sed/// operand index by reference. 891199989Srdivackybool MachineInstr:: 892199989SrdivackyisRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const { 893263508Sdim if (isInlineAsm()) { 894199989Srdivacky const MachineOperand &MO = getOperand(UseOpIdx); 895199989Srdivacky if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0) 896199989Srdivacky return false; 897223017Sdim 898239462Sdim // Find the flag operand corresponding to UseOpIdx 899223017Sdim unsigned FlagIdx, NumOps=0; 900223017Sdim for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) { 901223017Sdim const MachineOperand &UFMO = getOperand(FlagIdx); 902223017Sdim // After the normal asm operands there may be additional imp-def regs. 903223017Sdim if (!UFMO.isImm()) 904223017Sdim return false; 905223017Sdim NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm()); 906223017Sdim assert(NumOps < getNumOperands() && "Invalid inline asm flag"); 907199989Srdivacky if (UseOpIdx < FlagIdx+NumOps+1) 908199989Srdivacky break; 909199989Srdivacky } 910199989Srdivacky if (FlagIdx >= UseOpIdx) 911199989Srdivacky return false; 912199989Srdivacky const MachineOperand &UFMO = getOperand(FlagIdx); 913199989Srdivacky unsigned DefNo; 914199989Srdivacky if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) { 915199989Srdivacky if (!DefOpIdx) 916199989Srdivacky return true; 917199989Srdivacky 918199989Srdivacky unsigned DefIdx = 1; 919199989Srdivacky // Remember to adjust the index. First operand is asm string, then there 920199989Srdivacky // is a flag for each. 921199989Srdivacky while (DefNo) { 922199989Srdivacky const MachineOperand &FMO = getOperand(DefIdx); 923199989Srdivacky assert(FMO.isImm()); 924263508Sdim // Skip over this def. 925199989Srdivacky DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1; 926199989Srdivacky --DefNo; 927199989Srdivacky } 928199989Srdivacky *DefOpIdx = DefIdx + UseOpIdx - FlagIdx; 929199989Srdivacky return true; 930199989Srdivacky } 931199989Srdivacky return false; 932199989Srdivacky } 933199989Srdivacky 934199989Srdivacky const TargetInstrDesc &TID = getDesc(); 935199989Srdivacky if (UseOpIdx >= TID.getNumOperands()) 936199989Srdivacky return false; 937199989Srdivacky const MachineOperand &MO = getOperand(UseOpIdx); 938199989Srdivacky if (!MO.isReg() || !MO.isUse()) 939199989Srdivacky return false; 940199989Srdivacky int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO); 941199989Srdivacky if (DefIdx == -1) 942199989Srdivacky return false; 943199989Srdivacky if (DefOpIdx) 944199989Srdivacky *DefOpIdx = (unsigned)DefIdx; 945199989Srdivacky return true; 946199989Srdivacky} 947199989Srdivacky 948199989Srdivacky/// copyKillDeadInfo - Copies kill / dead operand properties from MI. 949199989Srdivacky/// 950199989Srdivackyvoid MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 951199989Srdivacky for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 952199989Srdivacky const MachineOperand &MO = MI->getOperand(i); 953199989Srdivacky if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) 954263508Sdim continue; 955199989Srdivacky for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 956199989Srdivacky MachineOperand &MOp = getOperand(j); 957199989Srdivacky if (!MOp.isIdenticalTo(MO)) 958199989Srdivacky continue; 959199989Srdivacky if (MO.isKill()) 960199989Srdivacky MOp.setIsKill(); 961199989Srdivacky else 962207618Srdivacky MOp.setIsDead(); 963207618Srdivacky break; 964207618Srdivacky } 965207618Srdivacky } 966207618Srdivacky} 967263508Sdim 968207618Srdivacky/// copyPredicates - Copies predicate operand(s) from MI. 969263508Sdimvoid MachineInstr::copyPredicates(const MachineInstr *MI) { 970263508Sdim const TargetInstrDesc &TID = MI->getDesc(); 971199989Srdivacky if (!TID.isPredicable()) 972207618Srdivacky return; 973207618Srdivacky for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 974207618Srdivacky if (TID.OpInfo[i].isPredicate()) { 975207618Srdivacky // Predicated operands must be last operands. 976263508Sdim addOperand(MI->getOperand(i)); 977199989Srdivacky } 978199989Srdivacky } 979207618Srdivacky} 980207618Srdivacky 981207618Srdivacky/// isSafeToMove - Return true if it is safe to move this instruction. If 982207618Srdivacky/// SawStore is set to true, it means that there is a store (or call) between 983207618Srdivacky/// the instruction's location and its intended destination. 984199989Srdivackybool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, 985199989Srdivacky AliasAnalysis *AA, 986199989Srdivacky bool &SawStore) const { 987199989Srdivacky // Ignore stuff that we obviously can't move. 988199989Srdivacky if (TID->mayStore() || TID->isCall()) { 989199989Srdivacky SawStore = true; 990239462Sdim return false; 991249423Sdim } 992199989Srdivacky if (TID->isTerminator() || TID->hasUnmodeledSideEffects()) 993199989Srdivacky return false; 994199989Srdivacky 995212904Sdim // See if this instruction does a load. If so, we have to guarantee that the 996212904Sdim // loaded value doesn't change between the load and the its intended 997212904Sdim // destination. The check for isInvariantLoad gives the targe the chance to 998212904Sdim // classify the load as always returning a constant, e.g. a constant pool 999212904Sdim // load. 1000212904Sdim if (TID->mayLoad() && !isInvariantLoad(AA)) 1001212904Sdim // Otherwise, this is a real load. If there is a store between the load and 1002212904Sdim // end of block, or if the load is volatile, we can't move it. 1003212904Sdim return !SawStore && !hasVolatileMemoryRef(); 1004212904Sdim 1005212904Sdim return true; 1006212904Sdim} 1007212904Sdim 1008212904Sdim/// isSafeToReMat - Return true if it's safe to rematerialize the specified 1009212904Sdim/// instruction which defined the specified register instead of copying it. 1010212904Sdimbool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, 1011212904Sdim AliasAnalysis *AA, 1012212904Sdim unsigned DstReg) const { 1013219077Sdim bool SawStore = false; 1014263508Sdim if (!TII->isTriviallyReMaterializable(this, AA) || 1015212904Sdim !isSafeToMove(TII, AA, SawStore)) 1016212904Sdim return false; 1017212904Sdim for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1018212904Sdim const MachineOperand &MO = getOperand(i); 1019226633Sdim if (!MO.isReg()) 1020199989Srdivacky continue; 1021210299Sed // FIXME: For now, do not remat any instruction with register operands. 1022210299Sed // Later on, we can loosen the restriction is the register operands have 1023210299Sed // not been modified between the def and use. Note, this is different from 1024199989Srdivacky // MachineSink because the code is no longer in two-address form (at least 1025199989Srdivacky // partially). 1026199989Srdivacky if (MO.isUse()) 1027210299Sed return false; 1028210299Sed else if (!MO.isDead() && MO.getReg() != DstReg) 1029210299Sed return false; 1030210299Sed } 1031210299Sed return true; 1032263508Sdim} 1033263508Sdim 1034210299Sed/// hasVolatileMemoryRef - Return true if this instruction may have a 1035263508Sdim/// volatile memory reference, or if the information describing the 1036218893Sdim/// memory reference is not available. Return false if it is known to 1037218893Sdim/// have no volatile memory references. 1038210299Sedbool MachineInstr::hasVolatileMemoryRef() const { 1039210299Sed // An instruction known never to access memory won't have a volatile access. 1040210299Sed if (!TID->mayStore() && 1041210299Sed !TID->mayLoad() && 1042210299Sed !TID->isCall() && 1043212904Sdim !TID->hasUnmodeledSideEffects()) 1044210299Sed return false; 1045210299Sed 1046210299Sed // Otherwise, if the instruction has no memory reference information, 1047210299Sed // conservatively assume it wasn't preserved. 1048210299Sed if (memoperands_empty()) 1049210299Sed return true; 1050210299Sed 1051210299Sed // Check the memory reference information for volatile references. 1052210299Sed for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I) 1053210299Sed if ((*I)->isVolatile()) 1054210299Sed return true; 1055210299Sed 1056210299Sed return false; 1057212904Sdim} 1058210299Sed 1059210299Sed/// isInvariantLoad - Return true if this instruction is loading from a 1060210299Sed/// location whose value is invariant across the function. For example, 1061212904Sdim/// loading a value from the constant pool or from the argument area 1062210299Sed/// of a function if it does not change. This should only return true of 1063210299Sed/// *all* loads the instruction does are invariant (if it does multiple loads). 1064263508Sdimbool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const { 1065263508Sdim // If the instruction doesn't load at all, it isn't an invariant load. 1066207618Srdivacky if (!TID->mayLoad()) 1067263508Sdim return false; 1068199989Srdivacky 1069207618Srdivacky // If the instruction has lost its memoperands, conservatively assume that 1070210299Sed // it may not be an invariant load. 1071199989Srdivacky if (memoperands_empty()) 1072207618Srdivacky return false; 1073263508Sdim 1074199989Srdivacky const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo(); 1075263508Sdim 1076263508Sdim for (mmo_iterator I = memoperands_begin(), 1077263508Sdim E = memoperands_end(); I != E; ++I) { 1078263508Sdim if ((*I)->isVolatile()) return false; 1079199989Srdivacky if ((*I)->isStore()) return false; 1080207618Srdivacky 1081210299Sed if (const Value *V = (*I)->getValue()) { 1082199989Srdivacky // A load from a constant PseudoSourceValue is invariant. 1083199989Srdivacky if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) 1084210299Sed if (PSV->isConstant(MFI)) 1085199989Srdivacky continue; 1086207618Srdivacky // If we have an AliasAnalysis, ask it whether the memory is constant. 1087199989Srdivacky if (AA && AA->pointsToConstantMemory(V)) 1088199989Srdivacky continue; 1089207618Srdivacky } 1090199989Srdivacky 1091199989Srdivacky // Otherwise assume conservatively. 1092199989Srdivacky return false; 1093199989Srdivacky } 1094199989Srdivacky 1095199989Srdivacky // Everything checks out. 1096199989Srdivacky return true; 1097199989Srdivacky} 1098199989Srdivacky 1099199989Srdivacky/// isConstantValuePHI - If the specified instruction is a PHI that always 1100199989Srdivacky/// merges together the same virtual register, return the register, otherwise 1101199989Srdivacky/// return 0. 1102199989Srdivackyunsigned MachineInstr::isConstantValuePHI() const { 1103199989Srdivacky if (!isPHI()) 1104199989Srdivacky return 0; 1105201360Srdivacky assert(getNumOperands() >= 3 && 1106203954Srdivacky "It's illegal to have a PHI without source operands"); 1107263508Sdim 1108199989Srdivacky unsigned Reg = getOperand(1).getReg(); 1109263508Sdim for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) 1110234353Sdim if (getOperand(i).getReg() != Reg) 1111234353Sdim return 0; 1112234353Sdim return Reg; 1113234353Sdim} 1114234353Sdim 1115234353Sdimvoid MachineInstr::dump() const { 1116234353Sdim dbgs() << " " << *this; 1117234353Sdim} 1118234353Sdim 1119234353Sdimvoid MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { 1120199989Srdivacky // We can be a bit tidier if we know the TargetMachine and/or MachineFunction. 1121234353Sdim const MachineFunction *MF = 0; 1122263508Sdim if (const MachineBasicBlock *MBB = getParent()) { 1123263508Sdim MF = MBB->getParent(); 1124234353Sdim if (!TM && MF) 1125234353Sdim TM = &MF->getTarget(); 1126234353Sdim } 1127204642Srdivacky 1128199989Srdivacky // Print explicitly defined operands on the left of an assignment syntax. 1129199989Srdivacky unsigned StartOp = 0, e = getNumOperands(); 1130199989Srdivacky for (; StartOp < e && getOperand(StartOp).isReg() && 1131199989Srdivacky getOperand(StartOp).isDef() && 1132263508Sdim !getOperand(StartOp).isImplicit(); 1133199989Srdivacky ++StartOp) { 1134199989Srdivacky if (StartOp != 0) OS << ", "; 1135199989Srdivacky getOperand(StartOp).print(OS, TM); 1136199989Srdivacky } 1137199989Srdivacky 1138199989Srdivacky if (StartOp != 0) 1139199989Srdivacky OS << " = "; 1140199989Srdivacky 1141199989Srdivacky // Print the opcode name. 1142199989Srdivacky OS << getDesc().getName(); 1143199989Srdivacky 1144199989Srdivacky // Print the rest of the operands. 1145199989Srdivacky bool OmittedAnyCallClobbers = false; 1146201360Srdivacky bool FirstOp = true; 1147203954Srdivacky for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 1148263508Sdim const MachineOperand &MO = getOperand(i); 1149199989Srdivacky 1150199989Srdivacky // Omit call-clobbered registers which aren't used anywhere. This makes 1151207618Srdivacky // call instructions much less noisy on targets where calls clobber lots 1152199989Srdivacky // of registers. Don't rely on MO.isDead() because we may be called before 1153199989Srdivacky // LiveVariables is run, or we may be looking at a non-allocatable reg. 1154226633Sdim if (MF && getDesc().isCall() && 1155199989Srdivacky MO.isReg() && MO.isImplicit() && MO.isDef()) { 1156199989Srdivacky unsigned Reg = MO.getReg(); 1157199989Srdivacky if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) { 1158199989Srdivacky const MachineRegisterInfo &MRI = MF->getRegInfo(); 1159199989Srdivacky if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) { 1160234353Sdim bool HasAliasLive = false; 1161199989Srdivacky for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg); 1162234353Sdim unsigned AliasReg = *Alias; ++Alias) 1163199989Srdivacky if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) { 1164199989Srdivacky HasAliasLive = true; 1165263508Sdim break; 1166199989Srdivacky } 1167199989Srdivacky if (!HasAliasLive) { 1168199989Srdivacky OmittedAnyCallClobbers = true; 1169199989Srdivacky continue; 1170199989Srdivacky } 1171199989Srdivacky } 1172199989Srdivacky } 1173199989Srdivacky } 1174199989Srdivacky 1175199989Srdivacky if (FirstOp) FirstOp = false; else OS << ","; 1176263508Sdim OS << " "; 1177203954Srdivacky if (i < getDesc().NumOperands) { 1178199989Srdivacky const TargetOperandInfo &TOI = getDesc().OpInfo[i]; 1179199989Srdivacky if (TOI.isPredicate()) 1180199989Srdivacky OS << "pred:"; 1181199989Srdivacky if (TOI.isOptionalDef()) 1182199989Srdivacky OS << "opt:"; 1183199989Srdivacky } 1184199989Srdivacky MO.print(OS, TM); 1185199989Srdivacky } 1186263508Sdim 1187199989Srdivacky // Briefly indicate whether any call clobbers were omitted. 1188199989Srdivacky if (OmittedAnyCallClobbers) { 1189210299Sed if (!FirstOp) OS << ","; 1190210299Sed OS << " ..."; 1191210299Sed } 1192263508Sdim 1193210299Sed bool HaveSemi = false; 1194263508Sdim if (!memoperands_empty()) { 1195210299Sed if (!HaveSemi) OS << ";"; HaveSemi = true; 1196199989Srdivacky 1197210299Sed OS << " mem:"; 1198199989Srdivacky for (mmo_iterator i = memoperands_begin(), e = memoperands_end(); 1199199989Srdivacky i != e; ++i) { 1200207618Srdivacky OS << **i; 1201263508Sdim if (next(i) != e) 1202199989Srdivacky OS << " "; 1203199989Srdivacky } 1204210299Sed } 1205201360Srdivacky 1206210299Sed if (!debugLoc.isUnknown() && MF) { 1207210299Sed if (!HaveSemi) OS << ";"; 1208199989Srdivacky 1209199989Srdivacky // TODO: print InlinedAtLoc information 1210199989Srdivacky 1211199989Srdivacky DILocation DLT = MF->getDILocation(debugLoc); 1212199989Srdivacky DIScope Scope = DLT.getScope(); 1213199989Srdivacky OS << " dbg:"; 1214263508Sdim // Omit the directory, since it's usually long and uninteresting. 1215199989Srdivacky if (!Scope.isNull()) 1216199989Srdivacky OS << Scope.getFilename(); 1217199989Srdivacky else 1218199989Srdivacky OS << "<unknown>"; 1219201360Srdivacky OS << ':' << DLT.getLineNumber(); 1220199989Srdivacky if (DLT.getColumnNumber() != 0) 1221199989Srdivacky OS << ':' << DLT.getColumnNumber(); 1222263508Sdim } 1223199989Srdivacky 1224199989Srdivacky OS << "\n"; 1225199989Srdivacky} 1226201360Srdivacky 1227263508Sdimbool MachineInstr::addRegisterKilled(unsigned IncomingReg, 1228212904Sdim const TargetRegisterInfo *RegInfo, 1229212904Sdim bool AddIfNotFound) { 1230201360Srdivacky bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1231263508Sdim bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 1232201360Srdivacky bool Found = false; 1233218893Sdim SmallVector<unsigned,4> DeadOps; 1234218893Sdim for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1235201360Srdivacky MachineOperand &MO = getOperand(i); 1236201360Srdivacky if (!MO.isReg() || !MO.isUse() || MO.isUndef()) 1237263508Sdim continue; 1238199989Srdivacky unsigned Reg = MO.getReg(); 1239204642Srdivacky if (!Reg) 1240204642Srdivacky continue; 1241263508Sdim 1242204642Srdivacky if (Reg == IncomingReg) { 1243204642Srdivacky if (!Found) { 1244204642Srdivacky if (MO.isKill()) 1245199989Srdivacky // The register is already marked kill. 1246199989Srdivacky return true; 1247199989Srdivacky if (isPhysReg && isRegTiedToDefOperand(i)) 1248199989Srdivacky // Two-address uses of physregs must not be marked kill. 1249199989Srdivacky return true; 1250199989Srdivacky MO.setIsKill(); 1251249423Sdim Found = true; 1252249423Sdim } 1253199989Srdivacky } else if (hasAliases && MO.isKill() && 1254249423Sdim TargetRegisterInfo::isPhysicalRegister(Reg)) { 1255249423Sdim // A super-register kill already exists. 1256199989Srdivacky if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1257199989Srdivacky return true; 1258221345Sdim if (RegInfo->isSubRegister(IncomingReg, Reg)) 1259263508Sdim DeadOps.push_back(i); 1260199989Srdivacky } 1261263508Sdim } 1262263508Sdim 1263199989Srdivacky // Trim unneeded kill operands. 1264263508Sdim while (!DeadOps.empty()) { 1265199989Srdivacky unsigned OpIdx = DeadOps.back(); 1266243830Sdim if (getOperand(OpIdx).isImplicit()) 1267199989Srdivacky RemoveOperand(OpIdx); 1268199989Srdivacky else 1269199989Srdivacky getOperand(OpIdx).setIsKill(false); 1270249423Sdim DeadOps.pop_back(); 1271249423Sdim } 1272199989Srdivacky 1273199989Srdivacky // If not found, this means an alias of one of the operands is killed. Add a 1274199989Srdivacky // new implicit operand if required. 1275221345Sdim if (!Found && AddIfNotFound) { 1276199989Srdivacky addOperand(MachineOperand::CreateReg(IncomingReg, 1277221345Sdim false /*IsDef*/, 1278199989Srdivacky true /*IsImp*/, 1279199989Srdivacky true /*IsKill*/)); 1280210299Sed return true; 1281210299Sed } 1282263508Sdim return Found; 1283210299Sed} 1284210299Sed 1285199989Srdivackybool MachineInstr::addRegisterDead(unsigned IncomingReg, 1286199989Srdivacky const TargetRegisterInfo *RegInfo, 1287199989Srdivacky bool AddIfNotFound) { 1288199989Srdivacky bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1289199989Srdivacky bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 1290199989Srdivacky bool Found = false; 1291199989Srdivacky SmallVector<unsigned,4> DeadOps; 1292263508Sdim for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1293263508Sdim MachineOperand &MO = getOperand(i); 1294263508Sdim if (!MO.isReg() || !MO.isDef()) 1295199989Srdivacky continue; 1296199989Srdivacky unsigned Reg = MO.getReg(); 1297199989Srdivacky if (!Reg) 1298199989Srdivacky continue; 1299199989Srdivacky 1300199989Srdivacky if (Reg == IncomingReg) { 1301199989Srdivacky if (!Found) { 1302199989Srdivacky if (MO.isDead()) 1303199989Srdivacky // The register is already marked dead. 1304199989Srdivacky return true; 1305199989Srdivacky MO.setIsDead(); 1306199989Srdivacky Found = true; 1307207618Srdivacky } 1308223017Sdim } else if (hasAliases && MO.isDead() && 1309223017Sdim TargetRegisterInfo::isPhysicalRegister(Reg)) { 1310223017Sdim // There exists a super-register that's marked dead. 1311223017Sdim if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1312207618Srdivacky return true; 1313207618Srdivacky if (RegInfo->getSubRegisters(IncomingReg) && 1314207618Srdivacky RegInfo->getSuperRegisters(Reg) && 1315207618Srdivacky RegInfo->isSubRegister(IncomingReg, Reg)) 1316199989Srdivacky DeadOps.push_back(i); 1317199989Srdivacky } 1318199989Srdivacky } 1319199989Srdivacky 1320199989Srdivacky // Trim unneeded dead operands. 1321199989Srdivacky while (!DeadOps.empty()) { 1322207618Srdivacky unsigned OpIdx = DeadOps.back(); 1323199989Srdivacky if (getOperand(OpIdx).isImplicit()) 1324199989Srdivacky RemoveOperand(OpIdx); 1325199989Srdivacky else 1326199989Srdivacky getOperand(OpIdx).setIsDead(false); 1327199989Srdivacky DeadOps.pop_back(); 1328199989Srdivacky } 1329199989Srdivacky 1330199989Srdivacky // If not found, this means an alias of one of the operands is dead. Add a 1331199989Srdivacky // new implicit operand if required. 1332199989Srdivacky if (Found || !AddIfNotFound) 1333207618Srdivacky return Found; 1334199989Srdivacky 1335199989Srdivacky addOperand(MachineOperand::CreateReg(IncomingReg, 1336199989Srdivacky true /*IsDef*/, 1337207618Srdivacky true /*IsImp*/, 1338199989Srdivacky false /*IsKill*/, 1339199989Srdivacky true /*IsDead*/)); 1340199989Srdivacky return true; 1341199989Srdivacky} 1342199989Srdivacky 1343199989Srdivackyvoid MachineInstr::addRegisterDefined(unsigned IncomingReg, 1344199989Srdivacky const TargetRegisterInfo *RegInfo) { 1345199989Srdivacky MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo); 1346199989Srdivacky if (!MO || MO->getSubReg()) 1347199989Srdivacky addOperand(MachineOperand::CreateReg(IncomingReg, 1348199989Srdivacky true /*IsDef*/, 1349199989Srdivacky true /*IsImp*/)); 1350199989Srdivacky} 1351199989Srdivacky