MachineInstr.cpp revision 203954
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Methods common to all machine instructions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineInstr.h" 15#include "llvm/Constants.h" 16#include "llvm/Function.h" 17#include "llvm/InlineAsm.h" 18#include "llvm/Type.h" 19#include "llvm/Value.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CodeGen/MachineFunction.h" 22#include "llvm/CodeGen/MachineMemOperand.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/CodeGen/PseudoSourceValue.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetInstrInfo.h" 27#include "llvm/Target/TargetInstrDesc.h" 28#include "llvm/Target/TargetRegisterInfo.h" 29#include "llvm/Analysis/AliasAnalysis.h" 30#include "llvm/Analysis/DebugInfo.h" 31#include "llvm/Support/Debug.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/LeakDetector.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/ADT/FoldingSet.h" 37#include "llvm/Metadata.h" 38using namespace llvm; 39 40//===----------------------------------------------------------------------===// 41// MachineOperand Implementation 42//===----------------------------------------------------------------------===// 43 44/// AddRegOperandToRegInfo - Add this register operand to the specified 45/// MachineRegisterInfo. If it is null, then the next/prev fields should be 46/// explicitly nulled out. 47void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { 48 assert(isReg() && "Can only add reg operand to use lists"); 49 50 // If the reginfo pointer is null, just explicitly null out or next/prev 51 // pointers, to ensure they are not garbage. 52 if (RegInfo == 0) { 53 Contents.Reg.Prev = 0; 54 Contents.Reg.Next = 0; 55 return; 56 } 57 58 // Otherwise, add this operand to the head of the registers use/def list. 59 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg()); 60 61 // For SSA values, we prefer to keep the definition at the start of the list. 62 // we do this by skipping over the definition if it is at the head of the 63 // list. 64 if (*Head && (*Head)->isDef()) 65 Head = &(*Head)->Contents.Reg.Next; 66 67 Contents.Reg.Next = *Head; 68 if (Contents.Reg.Next) { 69 assert(getReg() == Contents.Reg.Next->getReg() && 70 "Different regs on the same list!"); 71 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next; 72 } 73 74 Contents.Reg.Prev = Head; 75 *Head = this; 76} 77 78/// RemoveRegOperandFromRegInfo - Remove this register operand from the 79/// MachineRegisterInfo it is linked with. 80void MachineOperand::RemoveRegOperandFromRegInfo() { 81 assert(isOnRegUseList() && "Reg operand is not on a use list"); 82 // Unlink this from the doubly linked list of operands. 83 MachineOperand *NextOp = Contents.Reg.Next; 84 *Contents.Reg.Prev = NextOp; 85 if (NextOp) { 86 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!"); 87 NextOp->Contents.Reg.Prev = Contents.Reg.Prev; 88 } 89 Contents.Reg.Prev = 0; 90 Contents.Reg.Next = 0; 91} 92 93void MachineOperand::setReg(unsigned Reg) { 94 if (getReg() == Reg) return; // No change. 95 96 // Otherwise, we have to change the register. If this operand is embedded 97 // into a machine function, we need to update the old and new register's 98 // use/def lists. 99 if (MachineInstr *MI = getParent()) 100 if (MachineBasicBlock *MBB = MI->getParent()) 101 if (MachineFunction *MF = MBB->getParent()) { 102 RemoveRegOperandFromRegInfo(); 103 Contents.Reg.RegNo = Reg; 104 AddRegOperandToRegInfo(&MF->getRegInfo()); 105 return; 106 } 107 108 // Otherwise, just change the register, no problem. :) 109 Contents.Reg.RegNo = Reg; 110} 111 112/// ChangeToImmediate - Replace this operand with a new immediate operand of 113/// the specified value. If an operand is known to be an immediate already, 114/// the setImm method should be used. 115void MachineOperand::ChangeToImmediate(int64_t ImmVal) { 116 // If this operand is currently a register operand, and if this is in a 117 // function, deregister the operand from the register's use/def list. 118 if (isReg() && getParent() && getParent()->getParent() && 119 getParent()->getParent()->getParent()) 120 RemoveRegOperandFromRegInfo(); 121 122 OpKind = MO_Immediate; 123 Contents.ImmVal = ImmVal; 124} 125 126/// ChangeToRegister - Replace this operand with a new register operand of 127/// the specified value. If an operand is known to be an register already, 128/// the setReg method should be used. 129void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 130 bool isKill, bool isDead, bool isUndef, 131 bool isDebug) { 132 // If this operand is already a register operand, use setReg to update the 133 // register's use/def lists. 134 if (isReg()) { 135 assert(!isEarlyClobber()); 136 setReg(Reg); 137 } else { 138 // Otherwise, change this to a register and set the reg#. 139 OpKind = MO_Register; 140 Contents.Reg.RegNo = Reg; 141 142 // If this operand is embedded in a function, add the operand to the 143 // register's use/def list. 144 if (MachineInstr *MI = getParent()) 145 if (MachineBasicBlock *MBB = MI->getParent()) 146 if (MachineFunction *MF = MBB->getParent()) 147 AddRegOperandToRegInfo(&MF->getRegInfo()); 148 } 149 150 IsDef = isDef; 151 IsImp = isImp; 152 IsKill = isKill; 153 IsDead = isDead; 154 IsUndef = isUndef; 155 IsEarlyClobber = false; 156 IsDebug = isDebug; 157 SubReg = 0; 158} 159 160/// isIdenticalTo - Return true if this operand is identical to the specified 161/// operand. 162bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 163 if (getType() != Other.getType() || 164 getTargetFlags() != Other.getTargetFlags()) 165 return false; 166 167 switch (getType()) { 168 default: llvm_unreachable("Unrecognized operand type"); 169 case MachineOperand::MO_Register: 170 return getReg() == Other.getReg() && isDef() == Other.isDef() && 171 getSubReg() == Other.getSubReg(); 172 case MachineOperand::MO_Immediate: 173 return getImm() == Other.getImm(); 174 case MachineOperand::MO_FPImmediate: 175 return getFPImm() == Other.getFPImm(); 176 case MachineOperand::MO_MachineBasicBlock: 177 return getMBB() == Other.getMBB(); 178 case MachineOperand::MO_FrameIndex: 179 return getIndex() == Other.getIndex(); 180 case MachineOperand::MO_ConstantPoolIndex: 181 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 182 case MachineOperand::MO_JumpTableIndex: 183 return getIndex() == Other.getIndex(); 184 case MachineOperand::MO_GlobalAddress: 185 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 186 case MachineOperand::MO_ExternalSymbol: 187 return !strcmp(getSymbolName(), Other.getSymbolName()) && 188 getOffset() == Other.getOffset(); 189 case MachineOperand::MO_BlockAddress: 190 return getBlockAddress() == Other.getBlockAddress(); 191 } 192} 193 194/// print - Print the specified machine operand. 195/// 196void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 197 // If the instruction is embedded into a basic block, we can find the 198 // target info for the instruction. 199 if (!TM) 200 if (const MachineInstr *MI = getParent()) 201 if (const MachineBasicBlock *MBB = MI->getParent()) 202 if (const MachineFunction *MF = MBB->getParent()) 203 TM = &MF->getTarget(); 204 205 switch (getType()) { 206 case MachineOperand::MO_Register: 207 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) { 208 OS << "%reg" << getReg(); 209 } else { 210 if (TM) 211 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name; 212 else 213 OS << "%physreg" << getReg(); 214 } 215 216 if (getSubReg() != 0) 217 OS << ':' << getSubReg(); 218 219 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || 220 isEarlyClobber()) { 221 OS << '<'; 222 bool NeedComma = false; 223 if (isDef()) { 224 if (NeedComma) OS << ','; 225 if (isEarlyClobber()) 226 OS << "earlyclobber,"; 227 if (isImplicit()) 228 OS << "imp-"; 229 OS << "def"; 230 NeedComma = true; 231 } else if (isImplicit()) { 232 OS << "imp-use"; 233 NeedComma = true; 234 } 235 236 if (isKill() || isDead() || isUndef()) { 237 if (NeedComma) OS << ','; 238 if (isKill()) OS << "kill"; 239 if (isDead()) OS << "dead"; 240 if (isUndef()) { 241 if (isKill() || isDead()) 242 OS << ','; 243 OS << "undef"; 244 } 245 } 246 OS << '>'; 247 } 248 break; 249 case MachineOperand::MO_Immediate: 250 OS << getImm(); 251 break; 252 case MachineOperand::MO_FPImmediate: 253 if (getFPImm()->getType()->isFloatTy()) 254 OS << getFPImm()->getValueAPF().convertToFloat(); 255 else 256 OS << getFPImm()->getValueAPF().convertToDouble(); 257 break; 258 case MachineOperand::MO_MachineBasicBlock: 259 OS << "<BB#" << getMBB()->getNumber() << ">"; 260 break; 261 case MachineOperand::MO_FrameIndex: 262 OS << "<fi#" << getIndex() << '>'; 263 break; 264 case MachineOperand::MO_ConstantPoolIndex: 265 OS << "<cp#" << getIndex(); 266 if (getOffset()) OS << "+" << getOffset(); 267 OS << '>'; 268 break; 269 case MachineOperand::MO_JumpTableIndex: 270 OS << "<jt#" << getIndex() << '>'; 271 break; 272 case MachineOperand::MO_GlobalAddress: 273 OS << "<ga:"; 274 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false); 275 if (getOffset()) OS << "+" << getOffset(); 276 OS << '>'; 277 break; 278 case MachineOperand::MO_ExternalSymbol: 279 OS << "<es:" << getSymbolName(); 280 if (getOffset()) OS << "+" << getOffset(); 281 OS << '>'; 282 break; 283 case MachineOperand::MO_BlockAddress: 284 OS << '<'; 285 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false); 286 OS << '>'; 287 break; 288 case MachineOperand::MO_Metadata: 289 OS << '<'; 290 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false); 291 OS << '>'; 292 break; 293 default: 294 llvm_unreachable("Unrecognized operand type"); 295 } 296 297 if (unsigned TF = getTargetFlags()) 298 OS << "[TF=" << TF << ']'; 299} 300 301//===----------------------------------------------------------------------===// 302// MachineMemOperand Implementation 303//===----------------------------------------------------------------------===// 304 305MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f, 306 int64_t o, uint64_t s, unsigned int a) 307 : Offset(o), Size(s), V(v), 308 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)) { 309 assert(getBaseAlignment() == a && "Alignment is not a power of 2!"); 310 assert((isLoad() || isStore()) && "Not a load/store!"); 311} 312 313/// Profile - Gather unique data for the object. 314/// 315void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 316 ID.AddInteger(Offset); 317 ID.AddInteger(Size); 318 ID.AddPointer(V); 319 ID.AddInteger(Flags); 320} 321 322void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { 323 // The Value and Offset may differ due to CSE. But the flags and size 324 // should be the same. 325 assert(MMO->getFlags() == getFlags() && "Flags mismatch!"); 326 assert(MMO->getSize() == getSize() && "Size mismatch!"); 327 328 if (MMO->getBaseAlignment() >= getBaseAlignment()) { 329 // Update the alignment value. 330 Flags = (Flags & ((1 << MOMaxBits) - 1)) | 331 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits); 332 // Also update the base and offset, because the new alignment may 333 // not be applicable with the old ones. 334 V = MMO->getValue(); 335 Offset = MMO->getOffset(); 336 } 337} 338 339/// getAlignment - Return the minimum known alignment in bytes of the 340/// actual memory reference. 341uint64_t MachineMemOperand::getAlignment() const { 342 return MinAlign(getBaseAlignment(), getOffset()); 343} 344 345raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) { 346 assert((MMO.isLoad() || MMO.isStore()) && 347 "SV has to be a load, store or both."); 348 349 if (MMO.isVolatile()) 350 OS << "Volatile "; 351 352 if (MMO.isLoad()) 353 OS << "LD"; 354 if (MMO.isStore()) 355 OS << "ST"; 356 OS << MMO.getSize(); 357 358 // Print the address information. 359 OS << "["; 360 if (!MMO.getValue()) 361 OS << "<unknown>"; 362 else 363 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false); 364 365 // If the alignment of the memory reference itself differs from the alignment 366 // of the base pointer, print the base alignment explicitly, next to the base 367 // pointer. 368 if (MMO.getBaseAlignment() != MMO.getAlignment()) 369 OS << "(align=" << MMO.getBaseAlignment() << ")"; 370 371 if (MMO.getOffset() != 0) 372 OS << "+" << MMO.getOffset(); 373 OS << "]"; 374 375 // Print the alignment of the reference. 376 if (MMO.getBaseAlignment() != MMO.getAlignment() || 377 MMO.getBaseAlignment() != MMO.getSize()) 378 OS << "(align=" << MMO.getAlignment() << ")"; 379 380 return OS; 381} 382 383//===----------------------------------------------------------------------===// 384// MachineInstr Implementation 385//===----------------------------------------------------------------------===// 386 387/// MachineInstr ctor - This constructor creates a dummy MachineInstr with 388/// TID NULL and no operands. 389MachineInstr::MachineInstr() 390 : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), 391 Parent(0), debugLoc(DebugLoc::getUnknownLoc()) { 392 // Make sure that we get added to a machine basicblock 393 LeakDetector::addGarbageObject(this); 394} 395 396void MachineInstr::addImplicitDefUseOperands() { 397 if (TID->ImplicitDefs) 398 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) 399 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 400 if (TID->ImplicitUses) 401 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) 402 addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 403} 404 405/// MachineInstr ctor - This constructor create a MachineInstr and add the 406/// implicit operands. It reserves space for number of operands specified by 407/// TargetInstrDesc or the numOperands if it is not zero. (for 408/// instructions with variable number of operands). 409MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) 410 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), 411 MemRefs(0), MemRefsEnd(0), Parent(0), 412 debugLoc(DebugLoc::getUnknownLoc()) { 413 if (!NoImp && TID->getImplicitDefs()) 414 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 415 NumImplicitOps++; 416 if (!NoImp && TID->getImplicitUses()) 417 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 418 NumImplicitOps++; 419 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 420 if (!NoImp) 421 addImplicitDefUseOperands(); 422 // Make sure that we get added to a machine basicblock 423 LeakDetector::addGarbageObject(this); 424} 425 426/// MachineInstr ctor - As above, but with a DebugLoc. 427MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl, 428 bool NoImp) 429 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), 430 Parent(0), debugLoc(dl) { 431 if (!NoImp && TID->getImplicitDefs()) 432 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 433 NumImplicitOps++; 434 if (!NoImp && TID->getImplicitUses()) 435 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 436 NumImplicitOps++; 437 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 438 if (!NoImp) 439 addImplicitDefUseOperands(); 440 // Make sure that we get added to a machine basicblock 441 LeakDetector::addGarbageObject(this); 442} 443 444/// MachineInstr ctor - Work exactly the same as the ctor two above, except 445/// that the MachineInstr is created and added to the end of the specified 446/// basic block. 447/// 448MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid) 449 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), 450 MemRefs(0), MemRefsEnd(0), Parent(0), 451 debugLoc(DebugLoc::getUnknownLoc()) { 452 assert(MBB && "Cannot use inserting ctor with null basic block!"); 453 if (TID->ImplicitDefs) 454 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 455 NumImplicitOps++; 456 if (TID->ImplicitUses) 457 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 458 NumImplicitOps++; 459 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 460 addImplicitDefUseOperands(); 461 // Make sure that we get added to a machine basicblock 462 LeakDetector::addGarbageObject(this); 463 MBB->push_back(this); // Add instruction to end of basic block! 464} 465 466/// MachineInstr ctor - As above, but with a DebugLoc. 467/// 468MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, 469 const TargetInstrDesc &tid) 470 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), 471 Parent(0), debugLoc(dl) { 472 assert(MBB && "Cannot use inserting ctor with null basic block!"); 473 if (TID->ImplicitDefs) 474 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 475 NumImplicitOps++; 476 if (TID->ImplicitUses) 477 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 478 NumImplicitOps++; 479 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 480 addImplicitDefUseOperands(); 481 // Make sure that we get added to a machine basicblock 482 LeakDetector::addGarbageObject(this); 483 MBB->push_back(this); // Add instruction to end of basic block! 484} 485 486/// MachineInstr ctor - Copies MachineInstr arg exactly 487/// 488MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 489 : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0), 490 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd), 491 Parent(0), debugLoc(MI.getDebugLoc()) { 492 Operands.reserve(MI.getNumOperands()); 493 494 // Add operands 495 for (unsigned i = 0; i != MI.getNumOperands(); ++i) 496 addOperand(MI.getOperand(i)); 497 NumImplicitOps = MI.NumImplicitOps; 498 499 // Set parent to null. 500 Parent = 0; 501 502 LeakDetector::addGarbageObject(this); 503} 504 505MachineInstr::~MachineInstr() { 506 LeakDetector::removeGarbageObject(this); 507#ifndef NDEBUG 508 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 509 assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 510 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 511 "Reg operand def/use list corrupted"); 512 } 513#endif 514} 515 516/// getRegInfo - If this instruction is embedded into a MachineFunction, 517/// return the MachineRegisterInfo object for the current function, otherwise 518/// return null. 519MachineRegisterInfo *MachineInstr::getRegInfo() { 520 if (MachineBasicBlock *MBB = getParent()) 521 return &MBB->getParent()->getRegInfo(); 522 return 0; 523} 524 525/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 526/// this instruction from their respective use lists. This requires that the 527/// operands already be on their use lists. 528void MachineInstr::RemoveRegOperandsFromUseLists() { 529 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 530 if (Operands[i].isReg()) 531 Operands[i].RemoveRegOperandFromRegInfo(); 532 } 533} 534 535/// AddRegOperandsToUseLists - Add all of the register operands in 536/// this instruction from their respective use lists. This requires that the 537/// operands not be on their use lists yet. 538void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { 539 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 540 if (Operands[i].isReg()) 541 Operands[i].AddRegOperandToRegInfo(&RegInfo); 542 } 543} 544 545 546/// addOperand - Add the specified operand to the instruction. If it is an 547/// implicit operand, it is added to the end of the operand list. If it is 548/// an explicit operand it is added at the end of the explicit operand list 549/// (before the first implicit operand). 550void MachineInstr::addOperand(const MachineOperand &Op) { 551 bool isImpReg = Op.isReg() && Op.isImplicit(); 552 assert((isImpReg || !OperandsComplete()) && 553 "Trying to add an operand to a machine instr that is already done!"); 554 555 MachineRegisterInfo *RegInfo = getRegInfo(); 556 557 // If we are adding the operand to the end of the list, our job is simpler. 558 // This is true most of the time, so this is a reasonable optimization. 559 if (isImpReg || NumImplicitOps == 0) { 560 // We can only do this optimization if we know that the operand list won't 561 // reallocate. 562 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) { 563 Operands.push_back(Op); 564 565 // Set the parent of the operand. 566 Operands.back().ParentMI = this; 567 568 // If the operand is a register, update the operand's use list. 569 if (Op.isReg()) { 570 Operands.back().AddRegOperandToRegInfo(RegInfo); 571 // If the register operand is flagged as early, mark the operand as such 572 unsigned OpNo = Operands.size() - 1; 573 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 574 Operands[OpNo].setIsEarlyClobber(true); 575 } 576 return; 577 } 578 } 579 580 // Otherwise, we have to insert a real operand before any implicit ones. 581 unsigned OpNo = Operands.size()-NumImplicitOps; 582 583 // If this instruction isn't embedded into a function, then we don't need to 584 // update any operand lists. 585 if (RegInfo == 0) { 586 // Simple insertion, no reginfo update needed for other register operands. 587 Operands.insert(Operands.begin()+OpNo, Op); 588 Operands[OpNo].ParentMI = this; 589 590 // Do explicitly set the reginfo for this operand though, to ensure the 591 // next/prev fields are properly nulled out. 592 if (Operands[OpNo].isReg()) { 593 Operands[OpNo].AddRegOperandToRegInfo(0); 594 // If the register operand is flagged as early, mark the operand as such 595 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 596 Operands[OpNo].setIsEarlyClobber(true); 597 } 598 599 } else if (Operands.size()+1 <= Operands.capacity()) { 600 // Otherwise, we have to remove register operands from their register use 601 // list, add the operand, then add the register operands back to their use 602 // list. This also must handle the case when the operand list reallocates 603 // to somewhere else. 604 605 // If insertion of this operand won't cause reallocation of the operand 606 // list, just remove the implicit operands, add the operand, then re-add all 607 // the rest of the operands. 608 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 609 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 610 Operands[i].RemoveRegOperandFromRegInfo(); 611 } 612 613 // Add the operand. If it is a register, add it to the reg list. 614 Operands.insert(Operands.begin()+OpNo, Op); 615 Operands[OpNo].ParentMI = this; 616 617 if (Operands[OpNo].isReg()) { 618 Operands[OpNo].AddRegOperandToRegInfo(RegInfo); 619 // If the register operand is flagged as early, mark the operand as such 620 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 621 Operands[OpNo].setIsEarlyClobber(true); 622 } 623 624 // Re-add all the implicit ops. 625 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) { 626 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 627 Operands[i].AddRegOperandToRegInfo(RegInfo); 628 } 629 } else { 630 // Otherwise, we will be reallocating the operand list. Remove all reg 631 // operands from their list, then readd them after the operand list is 632 // reallocated. 633 RemoveRegOperandsFromUseLists(); 634 635 Operands.insert(Operands.begin()+OpNo, Op); 636 Operands[OpNo].ParentMI = this; 637 638 // Re-add all the operands. 639 AddRegOperandsToUseLists(*RegInfo); 640 641 // If the register operand is flagged as early, mark the operand as such 642 if (Operands[OpNo].isReg() 643 && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 644 Operands[OpNo].setIsEarlyClobber(true); 645 } 646} 647 648/// RemoveOperand - Erase an operand from an instruction, leaving it with one 649/// fewer operand than it started with. 650/// 651void MachineInstr::RemoveOperand(unsigned OpNo) { 652 assert(OpNo < Operands.size() && "Invalid operand number"); 653 654 // Special case removing the last one. 655 if (OpNo == Operands.size()-1) { 656 // If needed, remove from the reg def/use list. 657 if (Operands.back().isReg() && Operands.back().isOnRegUseList()) 658 Operands.back().RemoveRegOperandFromRegInfo(); 659 660 Operands.pop_back(); 661 return; 662 } 663 664 // Otherwise, we are removing an interior operand. If we have reginfo to 665 // update, remove all operands that will be shifted down from their reg lists, 666 // move everything down, then re-add them. 667 MachineRegisterInfo *RegInfo = getRegInfo(); 668 if (RegInfo) { 669 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 670 if (Operands[i].isReg()) 671 Operands[i].RemoveRegOperandFromRegInfo(); 672 } 673 } 674 675 Operands.erase(Operands.begin()+OpNo); 676 677 if (RegInfo) { 678 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 679 if (Operands[i].isReg()) 680 Operands[i].AddRegOperandToRegInfo(RegInfo); 681 } 682 } 683} 684 685/// addMemOperand - Add a MachineMemOperand to the machine instruction. 686/// This function should be used only occasionally. The setMemRefs function 687/// is the primary method for setting up a MachineInstr's MemRefs list. 688void MachineInstr::addMemOperand(MachineFunction &MF, 689 MachineMemOperand *MO) { 690 mmo_iterator OldMemRefs = MemRefs; 691 mmo_iterator OldMemRefsEnd = MemRefsEnd; 692 693 size_t NewNum = (MemRefsEnd - MemRefs) + 1; 694 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum); 695 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum; 696 697 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs); 698 NewMemRefs[NewNum - 1] = MO; 699 700 MemRefs = NewMemRefs; 701 MemRefsEnd = NewMemRefsEnd; 702} 703 704/// removeFromParent - This method unlinks 'this' from the containing basic 705/// block, and returns it, but does not delete it. 706MachineInstr *MachineInstr::removeFromParent() { 707 assert(getParent() && "Not embedded in a basic block!"); 708 getParent()->remove(this); 709 return this; 710} 711 712 713/// eraseFromParent - This method unlinks 'this' from the containing basic 714/// block, and deletes it. 715void MachineInstr::eraseFromParent() { 716 assert(getParent() && "Not embedded in a basic block!"); 717 getParent()->erase(this); 718} 719 720 721/// OperandComplete - Return true if it's illegal to add a new operand 722/// 723bool MachineInstr::OperandsComplete() const { 724 unsigned short NumOperands = TID->getNumOperands(); 725 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands) 726 return true; // Broken: we have all the operands of this instruction! 727 return false; 728} 729 730/// getNumExplicitOperands - Returns the number of non-implicit operands. 731/// 732unsigned MachineInstr::getNumExplicitOperands() const { 733 unsigned NumOperands = TID->getNumOperands(); 734 if (!TID->isVariadic()) 735 return NumOperands; 736 737 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) { 738 const MachineOperand &MO = getOperand(i); 739 if (!MO.isReg() || !MO.isImplicit()) 740 NumOperands++; 741 } 742 return NumOperands; 743} 744 745 746/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 747/// the specific register or -1 if it is not found. It further tightens 748/// the search criteria to a use that kills the register if isKill is true. 749int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 750 const TargetRegisterInfo *TRI) const { 751 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 752 const MachineOperand &MO = getOperand(i); 753 if (!MO.isReg() || !MO.isUse()) 754 continue; 755 unsigned MOReg = MO.getReg(); 756 if (!MOReg) 757 continue; 758 if (MOReg == Reg || 759 (TRI && 760 TargetRegisterInfo::isPhysicalRegister(MOReg) && 761 TargetRegisterInfo::isPhysicalRegister(Reg) && 762 TRI->isSubRegister(MOReg, Reg))) 763 if (!isKill || MO.isKill()) 764 return i; 765 } 766 return -1; 767} 768 769/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 770/// the specified register or -1 if it is not found. If isDead is true, defs 771/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 772/// also checks if there is a def of a super-register. 773int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, 774 const TargetRegisterInfo *TRI) const { 775 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 776 const MachineOperand &MO = getOperand(i); 777 if (!MO.isReg() || !MO.isDef()) 778 continue; 779 unsigned MOReg = MO.getReg(); 780 if (MOReg == Reg || 781 (TRI && 782 TargetRegisterInfo::isPhysicalRegister(MOReg) && 783 TargetRegisterInfo::isPhysicalRegister(Reg) && 784 TRI->isSubRegister(MOReg, Reg))) 785 if (!isDead || MO.isDead()) 786 return i; 787 } 788 return -1; 789} 790 791/// findFirstPredOperandIdx() - Find the index of the first operand in the 792/// operand list that is used to represent the predicate. It returns -1 if 793/// none is found. 794int MachineInstr::findFirstPredOperandIdx() const { 795 const TargetInstrDesc &TID = getDesc(); 796 if (TID.isPredicable()) { 797 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 798 if (TID.OpInfo[i].isPredicate()) 799 return i; 800 } 801 802 return -1; 803} 804 805/// isRegTiedToUseOperand - Given the index of a register def operand, 806/// check if the register def is tied to a source operand, due to either 807/// two-address elimination or inline assembly constraints. Returns the 808/// first tied use operand index by reference is UseOpIdx is not null. 809bool MachineInstr:: 810isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const { 811 if (isInlineAsm()) { 812 assert(DefOpIdx >= 2); 813 const MachineOperand &MO = getOperand(DefOpIdx); 814 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0) 815 return false; 816 // Determine the actual operand index that corresponds to this index. 817 unsigned DefNo = 0; 818 unsigned DefPart = 0; 819 for (unsigned i = 1, e = getNumOperands(); i < e; ) { 820 const MachineOperand &FMO = getOperand(i); 821 // After the normal asm operands there may be additional imp-def regs. 822 if (!FMO.isImm()) 823 return false; 824 // Skip over this def. 825 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm()); 826 unsigned PrevDef = i + 1; 827 i = PrevDef + NumOps; 828 if (i > DefOpIdx) { 829 DefPart = DefOpIdx - PrevDef; 830 break; 831 } 832 ++DefNo; 833 } 834 for (unsigned i = 1, e = getNumOperands(); i != e; ++i) { 835 const MachineOperand &FMO = getOperand(i); 836 if (!FMO.isImm()) 837 continue; 838 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse()) 839 continue; 840 unsigned Idx; 841 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) && 842 Idx == DefNo) { 843 if (UseOpIdx) 844 *UseOpIdx = (unsigned)i + 1 + DefPart; 845 return true; 846 } 847 } 848 return false; 849 } 850 851 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!"); 852 const TargetInstrDesc &TID = getDesc(); 853 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { 854 const MachineOperand &MO = getOperand(i); 855 if (MO.isReg() && MO.isUse() && 856 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) { 857 if (UseOpIdx) 858 *UseOpIdx = (unsigned)i; 859 return true; 860 } 861 } 862 return false; 863} 864 865/// isRegTiedToDefOperand - Return true if the operand of the specified index 866/// is a register use and it is tied to an def operand. It also returns the def 867/// operand index by reference. 868bool MachineInstr:: 869isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const { 870 if (isInlineAsm()) { 871 const MachineOperand &MO = getOperand(UseOpIdx); 872 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0) 873 return false; 874 875 // Find the flag operand corresponding to UseOpIdx 876 unsigned FlagIdx, NumOps=0; 877 for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) { 878 const MachineOperand &UFMO = getOperand(FlagIdx); 879 // After the normal asm operands there may be additional imp-def regs. 880 if (!UFMO.isImm()) 881 return false; 882 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm()); 883 assert(NumOps < getNumOperands() && "Invalid inline asm flag"); 884 if (UseOpIdx < FlagIdx+NumOps+1) 885 break; 886 } 887 if (FlagIdx >= UseOpIdx) 888 return false; 889 const MachineOperand &UFMO = getOperand(FlagIdx); 890 unsigned DefNo; 891 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) { 892 if (!DefOpIdx) 893 return true; 894 895 unsigned DefIdx = 1; 896 // Remember to adjust the index. First operand is asm string, then there 897 // is a flag for each. 898 while (DefNo) { 899 const MachineOperand &FMO = getOperand(DefIdx); 900 assert(FMO.isImm()); 901 // Skip over this def. 902 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1; 903 --DefNo; 904 } 905 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx; 906 return true; 907 } 908 return false; 909 } 910 911 const TargetInstrDesc &TID = getDesc(); 912 if (UseOpIdx >= TID.getNumOperands()) 913 return false; 914 const MachineOperand &MO = getOperand(UseOpIdx); 915 if (!MO.isReg() || !MO.isUse()) 916 return false; 917 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO); 918 if (DefIdx == -1) 919 return false; 920 if (DefOpIdx) 921 *DefOpIdx = (unsigned)DefIdx; 922 return true; 923} 924 925/// copyKillDeadInfo - Copies kill / dead operand properties from MI. 926/// 927void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 928 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 929 const MachineOperand &MO = MI->getOperand(i); 930 if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) 931 continue; 932 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 933 MachineOperand &MOp = getOperand(j); 934 if (!MOp.isIdenticalTo(MO)) 935 continue; 936 if (MO.isKill()) 937 MOp.setIsKill(); 938 else 939 MOp.setIsDead(); 940 break; 941 } 942 } 943} 944 945/// copyPredicates - Copies predicate operand(s) from MI. 946void MachineInstr::copyPredicates(const MachineInstr *MI) { 947 const TargetInstrDesc &TID = MI->getDesc(); 948 if (!TID.isPredicable()) 949 return; 950 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 951 if (TID.OpInfo[i].isPredicate()) { 952 // Predicated operands must be last operands. 953 addOperand(MI->getOperand(i)); 954 } 955 } 956} 957 958/// isSafeToMove - Return true if it is safe to move this instruction. If 959/// SawStore is set to true, it means that there is a store (or call) between 960/// the instruction's location and its intended destination. 961bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, 962 bool &SawStore, 963 AliasAnalysis *AA) const { 964 // Ignore stuff that we obviously can't move. 965 if (TID->mayStore() || TID->isCall()) { 966 SawStore = true; 967 return false; 968 } 969 if (TID->isTerminator() || TID->hasUnmodeledSideEffects()) 970 return false; 971 972 // See if this instruction does a load. If so, we have to guarantee that the 973 // loaded value doesn't change between the load and the its intended 974 // destination. The check for isInvariantLoad gives the targe the chance to 975 // classify the load as always returning a constant, e.g. a constant pool 976 // load. 977 if (TID->mayLoad() && !isInvariantLoad(AA)) 978 // Otherwise, this is a real load. If there is a store between the load and 979 // end of block, or if the load is volatile, we can't move it. 980 return !SawStore && !hasVolatileMemoryRef(); 981 982 return true; 983} 984 985/// isSafeToReMat - Return true if it's safe to rematerialize the specified 986/// instruction which defined the specified register instead of copying it. 987bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, 988 unsigned DstReg, 989 AliasAnalysis *AA) const { 990 bool SawStore = false; 991 if (!TII->isTriviallyReMaterializable(this, AA) || 992 !isSafeToMove(TII, SawStore, AA)) 993 return false; 994 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 995 const MachineOperand &MO = getOperand(i); 996 if (!MO.isReg()) 997 continue; 998 // FIXME: For now, do not remat any instruction with register operands. 999 // Later on, we can loosen the restriction is the register operands have 1000 // not been modified between the def and use. Note, this is different from 1001 // MachineSink because the code is no longer in two-address form (at least 1002 // partially). 1003 if (MO.isUse()) 1004 return false; 1005 else if (!MO.isDead() && MO.getReg() != DstReg) 1006 return false; 1007 } 1008 return true; 1009} 1010 1011/// hasVolatileMemoryRef - Return true if this instruction may have a 1012/// volatile memory reference, or if the information describing the 1013/// memory reference is not available. Return false if it is known to 1014/// have no volatile memory references. 1015bool MachineInstr::hasVolatileMemoryRef() const { 1016 // An instruction known never to access memory won't have a volatile access. 1017 if (!TID->mayStore() && 1018 !TID->mayLoad() && 1019 !TID->isCall() && 1020 !TID->hasUnmodeledSideEffects()) 1021 return false; 1022 1023 // Otherwise, if the instruction has no memory reference information, 1024 // conservatively assume it wasn't preserved. 1025 if (memoperands_empty()) 1026 return true; 1027 1028 // Check the memory reference information for volatile references. 1029 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I) 1030 if ((*I)->isVolatile()) 1031 return true; 1032 1033 return false; 1034} 1035 1036/// isInvariantLoad - Return true if this instruction is loading from a 1037/// location whose value is invariant across the function. For example, 1038/// loading a value from the constant pool or from the argument area 1039/// of a function if it does not change. This should only return true of 1040/// *all* loads the instruction does are invariant (if it does multiple loads). 1041bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const { 1042 // If the instruction doesn't load at all, it isn't an invariant load. 1043 if (!TID->mayLoad()) 1044 return false; 1045 1046 // If the instruction has lost its memoperands, conservatively assume that 1047 // it may not be an invariant load. 1048 if (memoperands_empty()) 1049 return false; 1050 1051 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo(); 1052 1053 for (mmo_iterator I = memoperands_begin(), 1054 E = memoperands_end(); I != E; ++I) { 1055 if ((*I)->isVolatile()) return false; 1056 if ((*I)->isStore()) return false; 1057 1058 if (const Value *V = (*I)->getValue()) { 1059 // A load from a constant PseudoSourceValue is invariant. 1060 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) 1061 if (PSV->isConstant(MFI)) 1062 continue; 1063 // If we have an AliasAnalysis, ask it whether the memory is constant. 1064 if (AA && AA->pointsToConstantMemory(V)) 1065 continue; 1066 } 1067 1068 // Otherwise assume conservatively. 1069 return false; 1070 } 1071 1072 // Everything checks out. 1073 return true; 1074} 1075 1076/// isConstantValuePHI - If the specified instruction is a PHI that always 1077/// merges together the same virtual register, return the register, otherwise 1078/// return 0. 1079unsigned MachineInstr::isConstantValuePHI() const { 1080 if (!isPHI()) 1081 return 0; 1082 assert(getNumOperands() >= 3 && 1083 "It's illegal to have a PHI without source operands"); 1084 1085 unsigned Reg = getOperand(1).getReg(); 1086 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) 1087 if (getOperand(i).getReg() != Reg) 1088 return 0; 1089 return Reg; 1090} 1091 1092void MachineInstr::dump() const { 1093 dbgs() << " " << *this; 1094} 1095 1096void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { 1097 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction. 1098 const MachineFunction *MF = 0; 1099 if (const MachineBasicBlock *MBB = getParent()) { 1100 MF = MBB->getParent(); 1101 if (!TM && MF) 1102 TM = &MF->getTarget(); 1103 } 1104 1105 // Print explicitly defined operands on the left of an assignment syntax. 1106 unsigned StartOp = 0, e = getNumOperands(); 1107 for (; StartOp < e && getOperand(StartOp).isReg() && 1108 getOperand(StartOp).isDef() && 1109 !getOperand(StartOp).isImplicit(); 1110 ++StartOp) { 1111 if (StartOp != 0) OS << ", "; 1112 getOperand(StartOp).print(OS, TM); 1113 } 1114 1115 if (StartOp != 0) 1116 OS << " = "; 1117 1118 // Print the opcode name. 1119 OS << getDesc().getName(); 1120 1121 // Print the rest of the operands. 1122 bool OmittedAnyCallClobbers = false; 1123 bool FirstOp = true; 1124 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 1125 const MachineOperand &MO = getOperand(i); 1126 1127 // Omit call-clobbered registers which aren't used anywhere. This makes 1128 // call instructions much less noisy on targets where calls clobber lots 1129 // of registers. Don't rely on MO.isDead() because we may be called before 1130 // LiveVariables is run, or we may be looking at a non-allocatable reg. 1131 if (MF && getDesc().isCall() && 1132 MO.isReg() && MO.isImplicit() && MO.isDef()) { 1133 unsigned Reg = MO.getReg(); 1134 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) { 1135 const MachineRegisterInfo &MRI = MF->getRegInfo(); 1136 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) { 1137 bool HasAliasLive = false; 1138 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg); 1139 unsigned AliasReg = *Alias; ++Alias) 1140 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) { 1141 HasAliasLive = true; 1142 break; 1143 } 1144 if (!HasAliasLive) { 1145 OmittedAnyCallClobbers = true; 1146 continue; 1147 } 1148 } 1149 } 1150 } 1151 1152 if (FirstOp) FirstOp = false; else OS << ","; 1153 OS << " "; 1154 if (i < getDesc().NumOperands) { 1155 const TargetOperandInfo &TOI = getDesc().OpInfo[i]; 1156 if (TOI.isPredicate()) 1157 OS << "pred:"; 1158 if (TOI.isOptionalDef()) 1159 OS << "opt:"; 1160 } 1161 MO.print(OS, TM); 1162 } 1163 1164 // Briefly indicate whether any call clobbers were omitted. 1165 if (OmittedAnyCallClobbers) { 1166 if (!FirstOp) OS << ","; 1167 OS << " ..."; 1168 } 1169 1170 bool HaveSemi = false; 1171 if (!memoperands_empty()) { 1172 if (!HaveSemi) OS << ";"; HaveSemi = true; 1173 1174 OS << " mem:"; 1175 for (mmo_iterator i = memoperands_begin(), e = memoperands_end(); 1176 i != e; ++i) { 1177 OS << **i; 1178 if (next(i) != e) 1179 OS << " "; 1180 } 1181 } 1182 1183 if (!debugLoc.isUnknown() && MF) { 1184 if (!HaveSemi) OS << ";"; 1185 1186 // TODO: print InlinedAtLoc information 1187 1188 DILocation DLT = MF->getDILocation(debugLoc); 1189 DIScope Scope = DLT.getScope(); 1190 OS << " dbg:"; 1191 // Omit the directory, since it's usually long and uninteresting. 1192 if (!Scope.isNull()) 1193 OS << Scope.getFilename(); 1194 else 1195 OS << "<unknown>"; 1196 OS << ':' << DLT.getLineNumber(); 1197 if (DLT.getColumnNumber() != 0) 1198 OS << ':' << DLT.getColumnNumber(); 1199 } 1200 1201 OS << "\n"; 1202} 1203 1204bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 1205 const TargetRegisterInfo *RegInfo, 1206 bool AddIfNotFound) { 1207 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1208 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 1209 bool Found = false; 1210 SmallVector<unsigned,4> DeadOps; 1211 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1212 MachineOperand &MO = getOperand(i); 1213 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) 1214 continue; 1215 unsigned Reg = MO.getReg(); 1216 if (!Reg) 1217 continue; 1218 1219 if (Reg == IncomingReg) { 1220 if (!Found) { 1221 if (MO.isKill()) 1222 // The register is already marked kill. 1223 return true; 1224 if (isPhysReg && isRegTiedToDefOperand(i)) 1225 // Two-address uses of physregs must not be marked kill. 1226 return true; 1227 MO.setIsKill(); 1228 Found = true; 1229 } 1230 } else if (hasAliases && MO.isKill() && 1231 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1232 // A super-register kill already exists. 1233 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1234 return true; 1235 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1236 DeadOps.push_back(i); 1237 } 1238 } 1239 1240 // Trim unneeded kill operands. 1241 while (!DeadOps.empty()) { 1242 unsigned OpIdx = DeadOps.back(); 1243 if (getOperand(OpIdx).isImplicit()) 1244 RemoveOperand(OpIdx); 1245 else 1246 getOperand(OpIdx).setIsKill(false); 1247 DeadOps.pop_back(); 1248 } 1249 1250 // If not found, this means an alias of one of the operands is killed. Add a 1251 // new implicit operand if required. 1252 if (!Found && AddIfNotFound) { 1253 addOperand(MachineOperand::CreateReg(IncomingReg, 1254 false /*IsDef*/, 1255 true /*IsImp*/, 1256 true /*IsKill*/)); 1257 return true; 1258 } 1259 return Found; 1260} 1261 1262bool MachineInstr::addRegisterDead(unsigned IncomingReg, 1263 const TargetRegisterInfo *RegInfo, 1264 bool AddIfNotFound) { 1265 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1266 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 1267 bool Found = false; 1268 SmallVector<unsigned,4> DeadOps; 1269 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1270 MachineOperand &MO = getOperand(i); 1271 if (!MO.isReg() || !MO.isDef()) 1272 continue; 1273 unsigned Reg = MO.getReg(); 1274 if (!Reg) 1275 continue; 1276 1277 if (Reg == IncomingReg) { 1278 if (!Found) { 1279 if (MO.isDead()) 1280 // The register is already marked dead. 1281 return true; 1282 MO.setIsDead(); 1283 Found = true; 1284 } 1285 } else if (hasAliases && MO.isDead() && 1286 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1287 // There exists a super-register that's marked dead. 1288 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1289 return true; 1290 if (RegInfo->getSubRegisters(IncomingReg) && 1291 RegInfo->getSuperRegisters(Reg) && 1292 RegInfo->isSubRegister(IncomingReg, Reg)) 1293 DeadOps.push_back(i); 1294 } 1295 } 1296 1297 // Trim unneeded dead operands. 1298 while (!DeadOps.empty()) { 1299 unsigned OpIdx = DeadOps.back(); 1300 if (getOperand(OpIdx).isImplicit()) 1301 RemoveOperand(OpIdx); 1302 else 1303 getOperand(OpIdx).setIsDead(false); 1304 DeadOps.pop_back(); 1305 } 1306 1307 // If not found, this means an alias of one of the operands is dead. Add a 1308 // new implicit operand if required. 1309 if (Found || !AddIfNotFound) 1310 return Found; 1311 1312 addOperand(MachineOperand::CreateReg(IncomingReg, 1313 true /*IsDef*/, 1314 true /*IsImp*/, 1315 false /*IsKill*/, 1316 true /*IsDead*/)); 1317 return true; 1318} 1319 1320void MachineInstr::addRegisterDefined(unsigned IncomingReg, 1321 const TargetRegisterInfo *RegInfo) { 1322 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo); 1323 if (!MO || MO->getSubReg()) 1324 addOperand(MachineOperand::CreateReg(IncomingReg, 1325 true /*IsDef*/, 1326 true /*IsImp*/)); 1327} 1328