MachineInstr.cpp revision 202878
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Methods common to all machine instructions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineInstr.h" 15#include "llvm/Constants.h" 16#include "llvm/Function.h" 17#include "llvm/InlineAsm.h" 18#include "llvm/Type.h" 19#include "llvm/Value.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CodeGen/MachineFunction.h" 22#include "llvm/CodeGen/MachineMemOperand.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/CodeGen/PseudoSourceValue.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetInstrInfo.h" 27#include "llvm/Target/TargetInstrDesc.h" 28#include "llvm/Target/TargetRegisterInfo.h" 29#include "llvm/Analysis/AliasAnalysis.h" 30#include "llvm/Analysis/DebugInfo.h" 31#include "llvm/Support/Debug.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/LeakDetector.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/ADT/FoldingSet.h" 37#include "llvm/Metadata.h" 38using namespace llvm; 39 40//===----------------------------------------------------------------------===// 41// MachineOperand Implementation 42//===----------------------------------------------------------------------===// 43 44/// AddRegOperandToRegInfo - Add this register operand to the specified 45/// MachineRegisterInfo. If it is null, then the next/prev fields should be 46/// explicitly nulled out. 47void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { 48 assert(isReg() && "Can only add reg operand to use lists"); 49 50 // If the reginfo pointer is null, just explicitly null out or next/prev 51 // pointers, to ensure they are not garbage. 52 if (RegInfo == 0) { 53 Contents.Reg.Prev = 0; 54 Contents.Reg.Next = 0; 55 return; 56 } 57 58 // Otherwise, add this operand to the head of the registers use/def list. 59 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg()); 60 61 // For SSA values, we prefer to keep the definition at the start of the list. 62 // we do this by skipping over the definition if it is at the head of the 63 // list. 64 if (*Head && (*Head)->isDef()) 65 Head = &(*Head)->Contents.Reg.Next; 66 67 Contents.Reg.Next = *Head; 68 if (Contents.Reg.Next) { 69 assert(getReg() == Contents.Reg.Next->getReg() && 70 "Different regs on the same list!"); 71 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next; 72 } 73 74 Contents.Reg.Prev = Head; 75 *Head = this; 76} 77 78/// RemoveRegOperandFromRegInfo - Remove this register operand from the 79/// MachineRegisterInfo it is linked with. 80void MachineOperand::RemoveRegOperandFromRegInfo() { 81 assert(isOnRegUseList() && "Reg operand is not on a use list"); 82 // Unlink this from the doubly linked list of operands. 83 MachineOperand *NextOp = Contents.Reg.Next; 84 *Contents.Reg.Prev = NextOp; 85 if (NextOp) { 86 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!"); 87 NextOp->Contents.Reg.Prev = Contents.Reg.Prev; 88 } 89 Contents.Reg.Prev = 0; 90 Contents.Reg.Next = 0; 91} 92 93void MachineOperand::setReg(unsigned Reg) { 94 if (getReg() == Reg) return; // No change. 95 96 // Otherwise, we have to change the register. If this operand is embedded 97 // into a machine function, we need to update the old and new register's 98 // use/def lists. 99 if (MachineInstr *MI = getParent()) 100 if (MachineBasicBlock *MBB = MI->getParent()) 101 if (MachineFunction *MF = MBB->getParent()) { 102 RemoveRegOperandFromRegInfo(); 103 Contents.Reg.RegNo = Reg; 104 AddRegOperandToRegInfo(&MF->getRegInfo()); 105 return; 106 } 107 108 // Otherwise, just change the register, no problem. :) 109 Contents.Reg.RegNo = Reg; 110} 111 112/// ChangeToImmediate - Replace this operand with a new immediate operand of 113/// the specified value. If an operand is known to be an immediate already, 114/// the setImm method should be used. 115void MachineOperand::ChangeToImmediate(int64_t ImmVal) { 116 // If this operand is currently a register operand, and if this is in a 117 // function, deregister the operand from the register's use/def list. 118 if (isReg() && getParent() && getParent()->getParent() && 119 getParent()->getParent()->getParent()) 120 RemoveRegOperandFromRegInfo(); 121 122 OpKind = MO_Immediate; 123 Contents.ImmVal = ImmVal; 124} 125 126/// ChangeToRegister - Replace this operand with a new register operand of 127/// the specified value. If an operand is known to be an register already, 128/// the setReg method should be used. 129void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 130 bool isKill, bool isDead, bool isUndef) { 131 // If this operand is already a register operand, use setReg to update the 132 // register's use/def lists. 133 if (isReg()) { 134 assert(!isEarlyClobber()); 135 setReg(Reg); 136 } else { 137 // Otherwise, change this to a register and set the reg#. 138 OpKind = MO_Register; 139 Contents.Reg.RegNo = Reg; 140 141 // If this operand is embedded in a function, add the operand to the 142 // register's use/def list. 143 if (MachineInstr *MI = getParent()) 144 if (MachineBasicBlock *MBB = MI->getParent()) 145 if (MachineFunction *MF = MBB->getParent()) 146 AddRegOperandToRegInfo(&MF->getRegInfo()); 147 } 148 149 IsDef = isDef; 150 IsImp = isImp; 151 IsKill = isKill; 152 IsDead = isDead; 153 IsUndef = isUndef; 154 IsEarlyClobber = false; 155 SubReg = 0; 156} 157 158/// isIdenticalTo - Return true if this operand is identical to the specified 159/// operand. 160bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 161 if (getType() != Other.getType() || 162 getTargetFlags() != Other.getTargetFlags()) 163 return false; 164 165 switch (getType()) { 166 default: llvm_unreachable("Unrecognized operand type"); 167 case MachineOperand::MO_Register: 168 return getReg() == Other.getReg() && isDef() == Other.isDef() && 169 getSubReg() == Other.getSubReg(); 170 case MachineOperand::MO_Immediate: 171 return getImm() == Other.getImm(); 172 case MachineOperand::MO_FPImmediate: 173 return getFPImm() == Other.getFPImm(); 174 case MachineOperand::MO_MachineBasicBlock: 175 return getMBB() == Other.getMBB(); 176 case MachineOperand::MO_FrameIndex: 177 return getIndex() == Other.getIndex(); 178 case MachineOperand::MO_ConstantPoolIndex: 179 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 180 case MachineOperand::MO_JumpTableIndex: 181 return getIndex() == Other.getIndex(); 182 case MachineOperand::MO_GlobalAddress: 183 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 184 case MachineOperand::MO_ExternalSymbol: 185 return !strcmp(getSymbolName(), Other.getSymbolName()) && 186 getOffset() == Other.getOffset(); 187 case MachineOperand::MO_BlockAddress: 188 return getBlockAddress() == Other.getBlockAddress(); 189 } 190} 191 192/// print - Print the specified machine operand. 193/// 194void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 195 // If the instruction is embedded into a basic block, we can find the 196 // target info for the instruction. 197 if (!TM) 198 if (const MachineInstr *MI = getParent()) 199 if (const MachineBasicBlock *MBB = MI->getParent()) 200 if (const MachineFunction *MF = MBB->getParent()) 201 TM = &MF->getTarget(); 202 203 switch (getType()) { 204 case MachineOperand::MO_Register: 205 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) { 206 OS << "%reg" << getReg(); 207 } else { 208 if (TM) 209 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name; 210 else 211 OS << "%physreg" << getReg(); 212 } 213 214 if (getSubReg() != 0) 215 OS << ':' << getSubReg(); 216 217 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || 218 isEarlyClobber()) { 219 OS << '<'; 220 bool NeedComma = false; 221 if (isDef()) { 222 if (NeedComma) OS << ','; 223 if (isEarlyClobber()) 224 OS << "earlyclobber,"; 225 if (isImplicit()) 226 OS << "imp-"; 227 OS << "def"; 228 NeedComma = true; 229 } else if (isImplicit()) { 230 OS << "imp-use"; 231 NeedComma = true; 232 } 233 234 if (isKill() || isDead() || isUndef()) { 235 if (NeedComma) OS << ','; 236 if (isKill()) OS << "kill"; 237 if (isDead()) OS << "dead"; 238 if (isUndef()) { 239 if (isKill() || isDead()) 240 OS << ','; 241 OS << "undef"; 242 } 243 } 244 OS << '>'; 245 } 246 break; 247 case MachineOperand::MO_Immediate: 248 OS << getImm(); 249 break; 250 case MachineOperand::MO_FPImmediate: 251 if (getFPImm()->getType()->isFloatTy()) 252 OS << getFPImm()->getValueAPF().convertToFloat(); 253 else 254 OS << getFPImm()->getValueAPF().convertToDouble(); 255 break; 256 case MachineOperand::MO_MachineBasicBlock: 257 OS << "<BB#" << getMBB()->getNumber() << ">"; 258 break; 259 case MachineOperand::MO_FrameIndex: 260 OS << "<fi#" << getIndex() << '>'; 261 break; 262 case MachineOperand::MO_ConstantPoolIndex: 263 OS << "<cp#" << getIndex(); 264 if (getOffset()) OS << "+" << getOffset(); 265 OS << '>'; 266 break; 267 case MachineOperand::MO_JumpTableIndex: 268 OS << "<jt#" << getIndex() << '>'; 269 break; 270 case MachineOperand::MO_GlobalAddress: 271 OS << "<ga:"; 272 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false); 273 if (getOffset()) OS << "+" << getOffset(); 274 OS << '>'; 275 break; 276 case MachineOperand::MO_ExternalSymbol: 277 OS << "<es:" << getSymbolName(); 278 if (getOffset()) OS << "+" << getOffset(); 279 OS << '>'; 280 break; 281 case MachineOperand::MO_BlockAddress: 282 OS << '<'; 283 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false); 284 OS << '>'; 285 break; 286 case MachineOperand::MO_Metadata: 287 OS << '<'; 288 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false); 289 OS << '>'; 290 break; 291 default: 292 llvm_unreachable("Unrecognized operand type"); 293 } 294 295 if (unsigned TF = getTargetFlags()) 296 OS << "[TF=" << TF << ']'; 297} 298 299//===----------------------------------------------------------------------===// 300// MachineMemOperand Implementation 301//===----------------------------------------------------------------------===// 302 303MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f, 304 int64_t o, uint64_t s, unsigned int a) 305 : Offset(o), Size(s), V(v), 306 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) { 307 assert(getBaseAlignment() == a && "Alignment is not a power of 2!"); 308 assert((isLoad() || isStore()) && "Not a load/store!"); 309} 310 311/// Profile - Gather unique data for the object. 312/// 313void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 314 ID.AddInteger(Offset); 315 ID.AddInteger(Size); 316 ID.AddPointer(V); 317 ID.AddInteger(Flags); 318} 319 320void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { 321 // The Value and Offset may differ due to CSE. But the flags and size 322 // should be the same. 323 assert(MMO->getFlags() == getFlags() && "Flags mismatch!"); 324 assert(MMO->getSize() == getSize() && "Size mismatch!"); 325 326 if (MMO->getBaseAlignment() >= getBaseAlignment()) { 327 // Update the alignment value. 328 Flags = (Flags & 7) | ((Log2_32(MMO->getBaseAlignment()) + 1) << 3); 329 // Also update the base and offset, because the new alignment may 330 // not be applicable with the old ones. 331 V = MMO->getValue(); 332 Offset = MMO->getOffset(); 333 } 334} 335 336/// getAlignment - Return the minimum known alignment in bytes of the 337/// actual memory reference. 338uint64_t MachineMemOperand::getAlignment() const { 339 return MinAlign(getBaseAlignment(), getOffset()); 340} 341 342raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) { 343 assert((MMO.isLoad() || MMO.isStore()) && 344 "SV has to be a load, store or both."); 345 346 if (MMO.isVolatile()) 347 OS << "Volatile "; 348 349 if (MMO.isLoad()) 350 OS << "LD"; 351 if (MMO.isStore()) 352 OS << "ST"; 353 OS << MMO.getSize(); 354 355 // Print the address information. 356 OS << "["; 357 if (!MMO.getValue()) 358 OS << "<unknown>"; 359 else 360 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false); 361 362 // If the alignment of the memory reference itself differs from the alignment 363 // of the base pointer, print the base alignment explicitly, next to the base 364 // pointer. 365 if (MMO.getBaseAlignment() != MMO.getAlignment()) 366 OS << "(align=" << MMO.getBaseAlignment() << ")"; 367 368 if (MMO.getOffset() != 0) 369 OS << "+" << MMO.getOffset(); 370 OS << "]"; 371 372 // Print the alignment of the reference. 373 if (MMO.getBaseAlignment() != MMO.getAlignment() || 374 MMO.getBaseAlignment() != MMO.getSize()) 375 OS << "(align=" << MMO.getAlignment() << ")"; 376 377 return OS; 378} 379 380//===----------------------------------------------------------------------===// 381// MachineInstr Implementation 382//===----------------------------------------------------------------------===// 383 384/// MachineInstr ctor - This constructor creates a dummy MachineInstr with 385/// TID NULL and no operands. 386MachineInstr::MachineInstr() 387 : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), 388 Parent(0), debugLoc(DebugLoc::getUnknownLoc()) { 389 // Make sure that we get added to a machine basicblock 390 LeakDetector::addGarbageObject(this); 391} 392 393void MachineInstr::addImplicitDefUseOperands() { 394 if (TID->ImplicitDefs) 395 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) 396 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 397 if (TID->ImplicitUses) 398 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) 399 addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 400} 401 402/// MachineInstr ctor - This constructor create a MachineInstr and add the 403/// implicit operands. It reserves space for number of operands specified by 404/// TargetInstrDesc or the numOperands if it is not zero. (for 405/// instructions with variable number of operands). 406MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) 407 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), 408 MemRefs(0), MemRefsEnd(0), Parent(0), 409 debugLoc(DebugLoc::getUnknownLoc()) { 410 if (!NoImp && TID->getImplicitDefs()) 411 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 412 NumImplicitOps++; 413 if (!NoImp && TID->getImplicitUses()) 414 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 415 NumImplicitOps++; 416 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 417 if (!NoImp) 418 addImplicitDefUseOperands(); 419 // Make sure that we get added to a machine basicblock 420 LeakDetector::addGarbageObject(this); 421} 422 423/// MachineInstr ctor - As above, but with a DebugLoc. 424MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl, 425 bool NoImp) 426 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), 427 Parent(0), debugLoc(dl) { 428 if (!NoImp && TID->getImplicitDefs()) 429 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 430 NumImplicitOps++; 431 if (!NoImp && TID->getImplicitUses()) 432 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 433 NumImplicitOps++; 434 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 435 if (!NoImp) 436 addImplicitDefUseOperands(); 437 // Make sure that we get added to a machine basicblock 438 LeakDetector::addGarbageObject(this); 439} 440 441/// MachineInstr ctor - Work exactly the same as the ctor two above, except 442/// that the MachineInstr is created and added to the end of the specified 443/// basic block. 444/// 445MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid) 446 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), 447 MemRefs(0), MemRefsEnd(0), Parent(0), 448 debugLoc(DebugLoc::getUnknownLoc()) { 449 assert(MBB && "Cannot use inserting ctor with null basic block!"); 450 if (TID->ImplicitDefs) 451 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 452 NumImplicitOps++; 453 if (TID->ImplicitUses) 454 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 455 NumImplicitOps++; 456 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 457 addImplicitDefUseOperands(); 458 // Make sure that we get added to a machine basicblock 459 LeakDetector::addGarbageObject(this); 460 MBB->push_back(this); // Add instruction to end of basic block! 461} 462 463/// MachineInstr ctor - As above, but with a DebugLoc. 464/// 465MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, 466 const TargetInstrDesc &tid) 467 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), 468 Parent(0), debugLoc(dl) { 469 assert(MBB && "Cannot use inserting ctor with null basic block!"); 470 if (TID->ImplicitDefs) 471 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 472 NumImplicitOps++; 473 if (TID->ImplicitUses) 474 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 475 NumImplicitOps++; 476 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 477 addImplicitDefUseOperands(); 478 // Make sure that we get added to a machine basicblock 479 LeakDetector::addGarbageObject(this); 480 MBB->push_back(this); // Add instruction to end of basic block! 481} 482 483/// MachineInstr ctor - Copies MachineInstr arg exactly 484/// 485MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 486 : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0), 487 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd), 488 Parent(0), debugLoc(MI.getDebugLoc()) { 489 Operands.reserve(MI.getNumOperands()); 490 491 // Add operands 492 for (unsigned i = 0; i != MI.getNumOperands(); ++i) 493 addOperand(MI.getOperand(i)); 494 NumImplicitOps = MI.NumImplicitOps; 495 496 // Set parent to null. 497 Parent = 0; 498 499 LeakDetector::addGarbageObject(this); 500} 501 502MachineInstr::~MachineInstr() { 503 LeakDetector::removeGarbageObject(this); 504#ifndef NDEBUG 505 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 506 assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 507 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 508 "Reg operand def/use list corrupted"); 509 } 510#endif 511} 512 513/// getRegInfo - If this instruction is embedded into a MachineFunction, 514/// return the MachineRegisterInfo object for the current function, otherwise 515/// return null. 516MachineRegisterInfo *MachineInstr::getRegInfo() { 517 if (MachineBasicBlock *MBB = getParent()) 518 return &MBB->getParent()->getRegInfo(); 519 return 0; 520} 521 522/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 523/// this instruction from their respective use lists. This requires that the 524/// operands already be on their use lists. 525void MachineInstr::RemoveRegOperandsFromUseLists() { 526 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 527 if (Operands[i].isReg()) 528 Operands[i].RemoveRegOperandFromRegInfo(); 529 } 530} 531 532/// AddRegOperandsToUseLists - Add all of the register operands in 533/// this instruction from their respective use lists. This requires that the 534/// operands not be on their use lists yet. 535void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { 536 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 537 if (Operands[i].isReg()) 538 Operands[i].AddRegOperandToRegInfo(&RegInfo); 539 } 540} 541 542 543/// addOperand - Add the specified operand to the instruction. If it is an 544/// implicit operand, it is added to the end of the operand list. If it is 545/// an explicit operand it is added at the end of the explicit operand list 546/// (before the first implicit operand). 547void MachineInstr::addOperand(const MachineOperand &Op) { 548 bool isImpReg = Op.isReg() && Op.isImplicit(); 549 assert((isImpReg || !OperandsComplete()) && 550 "Trying to add an operand to a machine instr that is already done!"); 551 552 MachineRegisterInfo *RegInfo = getRegInfo(); 553 554 // If we are adding the operand to the end of the list, our job is simpler. 555 // This is true most of the time, so this is a reasonable optimization. 556 if (isImpReg || NumImplicitOps == 0) { 557 // We can only do this optimization if we know that the operand list won't 558 // reallocate. 559 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) { 560 Operands.push_back(Op); 561 562 // Set the parent of the operand. 563 Operands.back().ParentMI = this; 564 565 // If the operand is a register, update the operand's use list. 566 if (Op.isReg()) { 567 Operands.back().AddRegOperandToRegInfo(RegInfo); 568 // If the register operand is flagged as early, mark the operand as such 569 unsigned OpNo = Operands.size() - 1; 570 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 571 Operands[OpNo].setIsEarlyClobber(true); 572 } 573 return; 574 } 575 } 576 577 // Otherwise, we have to insert a real operand before any implicit ones. 578 unsigned OpNo = Operands.size()-NumImplicitOps; 579 580 // If this instruction isn't embedded into a function, then we don't need to 581 // update any operand lists. 582 if (RegInfo == 0) { 583 // Simple insertion, no reginfo update needed for other register operands. 584 Operands.insert(Operands.begin()+OpNo, Op); 585 Operands[OpNo].ParentMI = this; 586 587 // Do explicitly set the reginfo for this operand though, to ensure the 588 // next/prev fields are properly nulled out. 589 if (Operands[OpNo].isReg()) { 590 Operands[OpNo].AddRegOperandToRegInfo(0); 591 // If the register operand is flagged as early, mark the operand as such 592 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 593 Operands[OpNo].setIsEarlyClobber(true); 594 } 595 596 } else if (Operands.size()+1 <= Operands.capacity()) { 597 // Otherwise, we have to remove register operands from their register use 598 // list, add the operand, then add the register operands back to their use 599 // list. This also must handle the case when the operand list reallocates 600 // to somewhere else. 601 602 // If insertion of this operand won't cause reallocation of the operand 603 // list, just remove the implicit operands, add the operand, then re-add all 604 // the rest of the operands. 605 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 606 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 607 Operands[i].RemoveRegOperandFromRegInfo(); 608 } 609 610 // Add the operand. If it is a register, add it to the reg list. 611 Operands.insert(Operands.begin()+OpNo, Op); 612 Operands[OpNo].ParentMI = this; 613 614 if (Operands[OpNo].isReg()) { 615 Operands[OpNo].AddRegOperandToRegInfo(RegInfo); 616 // If the register operand is flagged as early, mark the operand as such 617 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 618 Operands[OpNo].setIsEarlyClobber(true); 619 } 620 621 // Re-add all the implicit ops. 622 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) { 623 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 624 Operands[i].AddRegOperandToRegInfo(RegInfo); 625 } 626 } else { 627 // Otherwise, we will be reallocating the operand list. Remove all reg 628 // operands from their list, then readd them after the operand list is 629 // reallocated. 630 RemoveRegOperandsFromUseLists(); 631 632 Operands.insert(Operands.begin()+OpNo, Op); 633 Operands[OpNo].ParentMI = this; 634 635 // Re-add all the operands. 636 AddRegOperandsToUseLists(*RegInfo); 637 638 // If the register operand is flagged as early, mark the operand as such 639 if (Operands[OpNo].isReg() 640 && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) 641 Operands[OpNo].setIsEarlyClobber(true); 642 } 643} 644 645/// RemoveOperand - Erase an operand from an instruction, leaving it with one 646/// fewer operand than it started with. 647/// 648void MachineInstr::RemoveOperand(unsigned OpNo) { 649 assert(OpNo < Operands.size() && "Invalid operand number"); 650 651 // Special case removing the last one. 652 if (OpNo == Operands.size()-1) { 653 // If needed, remove from the reg def/use list. 654 if (Operands.back().isReg() && Operands.back().isOnRegUseList()) 655 Operands.back().RemoveRegOperandFromRegInfo(); 656 657 Operands.pop_back(); 658 return; 659 } 660 661 // Otherwise, we are removing an interior operand. If we have reginfo to 662 // update, remove all operands that will be shifted down from their reg lists, 663 // move everything down, then re-add them. 664 MachineRegisterInfo *RegInfo = getRegInfo(); 665 if (RegInfo) { 666 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 667 if (Operands[i].isReg()) 668 Operands[i].RemoveRegOperandFromRegInfo(); 669 } 670 } 671 672 Operands.erase(Operands.begin()+OpNo); 673 674 if (RegInfo) { 675 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 676 if (Operands[i].isReg()) 677 Operands[i].AddRegOperandToRegInfo(RegInfo); 678 } 679 } 680} 681 682/// addMemOperand - Add a MachineMemOperand to the machine instruction. 683/// This function should be used only occasionally. The setMemRefs function 684/// is the primary method for setting up a MachineInstr's MemRefs list. 685void MachineInstr::addMemOperand(MachineFunction &MF, 686 MachineMemOperand *MO) { 687 mmo_iterator OldMemRefs = MemRefs; 688 mmo_iterator OldMemRefsEnd = MemRefsEnd; 689 690 size_t NewNum = (MemRefsEnd - MemRefs) + 1; 691 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum); 692 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum; 693 694 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs); 695 NewMemRefs[NewNum - 1] = MO; 696 697 MemRefs = NewMemRefs; 698 MemRefsEnd = NewMemRefsEnd; 699} 700 701/// removeFromParent - This method unlinks 'this' from the containing basic 702/// block, and returns it, but does not delete it. 703MachineInstr *MachineInstr::removeFromParent() { 704 assert(getParent() && "Not embedded in a basic block!"); 705 getParent()->remove(this); 706 return this; 707} 708 709 710/// eraseFromParent - This method unlinks 'this' from the containing basic 711/// block, and deletes it. 712void MachineInstr::eraseFromParent() { 713 assert(getParent() && "Not embedded in a basic block!"); 714 getParent()->erase(this); 715} 716 717 718/// OperandComplete - Return true if it's illegal to add a new operand 719/// 720bool MachineInstr::OperandsComplete() const { 721 unsigned short NumOperands = TID->getNumOperands(); 722 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands) 723 return true; // Broken: we have all the operands of this instruction! 724 return false; 725} 726 727/// getNumExplicitOperands - Returns the number of non-implicit operands. 728/// 729unsigned MachineInstr::getNumExplicitOperands() const { 730 unsigned NumOperands = TID->getNumOperands(); 731 if (!TID->isVariadic()) 732 return NumOperands; 733 734 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) { 735 const MachineOperand &MO = getOperand(i); 736 if (!MO.isReg() || !MO.isImplicit()) 737 NumOperands++; 738 } 739 return NumOperands; 740} 741 742 743/// isLabel - Returns true if the MachineInstr represents a label. 744/// 745bool MachineInstr::isLabel() const { 746 return getOpcode() == TargetInstrInfo::DBG_LABEL || 747 getOpcode() == TargetInstrInfo::EH_LABEL || 748 getOpcode() == TargetInstrInfo::GC_LABEL; 749} 750 751/// isDebugLabel - Returns true if the MachineInstr represents a debug label. 752/// 753bool MachineInstr::isDebugLabel() const { 754 return getOpcode() == TargetInstrInfo::DBG_LABEL; 755} 756 757/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 758/// the specific register or -1 if it is not found. It further tightens 759/// the search criteria to a use that kills the register if isKill is true. 760int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 761 const TargetRegisterInfo *TRI) const { 762 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 763 const MachineOperand &MO = getOperand(i); 764 if (!MO.isReg() || !MO.isUse()) 765 continue; 766 unsigned MOReg = MO.getReg(); 767 if (!MOReg) 768 continue; 769 if (MOReg == Reg || 770 (TRI && 771 TargetRegisterInfo::isPhysicalRegister(MOReg) && 772 TargetRegisterInfo::isPhysicalRegister(Reg) && 773 TRI->isSubRegister(MOReg, Reg))) 774 if (!isKill || MO.isKill()) 775 return i; 776 } 777 return -1; 778} 779 780/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 781/// the specified register or -1 if it is not found. If isDead is true, defs 782/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 783/// also checks if there is a def of a super-register. 784int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, 785 const TargetRegisterInfo *TRI) const { 786 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 787 const MachineOperand &MO = getOperand(i); 788 if (!MO.isReg() || !MO.isDef()) 789 continue; 790 unsigned MOReg = MO.getReg(); 791 if (MOReg == Reg || 792 (TRI && 793 TargetRegisterInfo::isPhysicalRegister(MOReg) && 794 TargetRegisterInfo::isPhysicalRegister(Reg) && 795 TRI->isSubRegister(MOReg, Reg))) 796 if (!isDead || MO.isDead()) 797 return i; 798 } 799 return -1; 800} 801 802/// findFirstPredOperandIdx() - Find the index of the first operand in the 803/// operand list that is used to represent the predicate. It returns -1 if 804/// none is found. 805int MachineInstr::findFirstPredOperandIdx() const { 806 const TargetInstrDesc &TID = getDesc(); 807 if (TID.isPredicable()) { 808 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 809 if (TID.OpInfo[i].isPredicate()) 810 return i; 811 } 812 813 return -1; 814} 815 816/// isRegTiedToUseOperand - Given the index of a register def operand, 817/// check if the register def is tied to a source operand, due to either 818/// two-address elimination or inline assembly constraints. Returns the 819/// first tied use operand index by reference is UseOpIdx is not null. 820bool MachineInstr:: 821isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const { 822 if (getOpcode() == TargetInstrInfo::INLINEASM) { 823 assert(DefOpIdx >= 2); 824 const MachineOperand &MO = getOperand(DefOpIdx); 825 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0) 826 return false; 827 // Determine the actual operand index that corresponds to this index. 828 unsigned DefNo = 0; 829 unsigned DefPart = 0; 830 for (unsigned i = 1, e = getNumOperands(); i < e; ) { 831 const MachineOperand &FMO = getOperand(i); 832 // After the normal asm operands there may be additional imp-def regs. 833 if (!FMO.isImm()) 834 return false; 835 // Skip over this def. 836 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm()); 837 unsigned PrevDef = i + 1; 838 i = PrevDef + NumOps; 839 if (i > DefOpIdx) { 840 DefPart = DefOpIdx - PrevDef; 841 break; 842 } 843 ++DefNo; 844 } 845 for (unsigned i = 1, e = getNumOperands(); i != e; ++i) { 846 const MachineOperand &FMO = getOperand(i); 847 if (!FMO.isImm()) 848 continue; 849 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse()) 850 continue; 851 unsigned Idx; 852 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) && 853 Idx == DefNo) { 854 if (UseOpIdx) 855 *UseOpIdx = (unsigned)i + 1 + DefPart; 856 return true; 857 } 858 } 859 return false; 860 } 861 862 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!"); 863 const TargetInstrDesc &TID = getDesc(); 864 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { 865 const MachineOperand &MO = getOperand(i); 866 if (MO.isReg() && MO.isUse() && 867 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) { 868 if (UseOpIdx) 869 *UseOpIdx = (unsigned)i; 870 return true; 871 } 872 } 873 return false; 874} 875 876/// isRegTiedToDefOperand - Return true if the operand of the specified index 877/// is a register use and it is tied to an def operand. It also returns the def 878/// operand index by reference. 879bool MachineInstr:: 880isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const { 881 if (getOpcode() == TargetInstrInfo::INLINEASM) { 882 const MachineOperand &MO = getOperand(UseOpIdx); 883 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0) 884 return false; 885 886 // Find the flag operand corresponding to UseOpIdx 887 unsigned FlagIdx, NumOps=0; 888 for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) { 889 const MachineOperand &UFMO = getOperand(FlagIdx); 890 // After the normal asm operands there may be additional imp-def regs. 891 if (!UFMO.isImm()) 892 return false; 893 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm()); 894 assert(NumOps < getNumOperands() && "Invalid inline asm flag"); 895 if (UseOpIdx < FlagIdx+NumOps+1) 896 break; 897 } 898 if (FlagIdx >= UseOpIdx) 899 return false; 900 const MachineOperand &UFMO = getOperand(FlagIdx); 901 unsigned DefNo; 902 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) { 903 if (!DefOpIdx) 904 return true; 905 906 unsigned DefIdx = 1; 907 // Remember to adjust the index. First operand is asm string, then there 908 // is a flag for each. 909 while (DefNo) { 910 const MachineOperand &FMO = getOperand(DefIdx); 911 assert(FMO.isImm()); 912 // Skip over this def. 913 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1; 914 --DefNo; 915 } 916 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx; 917 return true; 918 } 919 return false; 920 } 921 922 const TargetInstrDesc &TID = getDesc(); 923 if (UseOpIdx >= TID.getNumOperands()) 924 return false; 925 const MachineOperand &MO = getOperand(UseOpIdx); 926 if (!MO.isReg() || !MO.isUse()) 927 return false; 928 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO); 929 if (DefIdx == -1) 930 return false; 931 if (DefOpIdx) 932 *DefOpIdx = (unsigned)DefIdx; 933 return true; 934} 935 936/// copyKillDeadInfo - Copies kill / dead operand properties from MI. 937/// 938void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 939 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 940 const MachineOperand &MO = MI->getOperand(i); 941 if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) 942 continue; 943 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 944 MachineOperand &MOp = getOperand(j); 945 if (!MOp.isIdenticalTo(MO)) 946 continue; 947 if (MO.isKill()) 948 MOp.setIsKill(); 949 else 950 MOp.setIsDead(); 951 break; 952 } 953 } 954} 955 956/// copyPredicates - Copies predicate operand(s) from MI. 957void MachineInstr::copyPredicates(const MachineInstr *MI) { 958 const TargetInstrDesc &TID = MI->getDesc(); 959 if (!TID.isPredicable()) 960 return; 961 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 962 if (TID.OpInfo[i].isPredicate()) { 963 // Predicated operands must be last operands. 964 addOperand(MI->getOperand(i)); 965 } 966 } 967} 968 969/// isSafeToMove - Return true if it is safe to move this instruction. If 970/// SawStore is set to true, it means that there is a store (or call) between 971/// the instruction's location and its intended destination. 972bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, 973 bool &SawStore, 974 AliasAnalysis *AA) const { 975 // Ignore stuff that we obviously can't move. 976 if (TID->mayStore() || TID->isCall()) { 977 SawStore = true; 978 return false; 979 } 980 if (TID->isTerminator() || TID->hasUnmodeledSideEffects()) 981 return false; 982 983 // See if this instruction does a load. If so, we have to guarantee that the 984 // loaded value doesn't change between the load and the its intended 985 // destination. The check for isInvariantLoad gives the targe the chance to 986 // classify the load as always returning a constant, e.g. a constant pool 987 // load. 988 if (TID->mayLoad() && !isInvariantLoad(AA)) 989 // Otherwise, this is a real load. If there is a store between the load and 990 // end of block, or if the load is volatile, we can't move it. 991 return !SawStore && !hasVolatileMemoryRef(); 992 993 return true; 994} 995 996/// isSafeToReMat - Return true if it's safe to rematerialize the specified 997/// instruction which defined the specified register instead of copying it. 998bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, 999 unsigned DstReg, 1000 AliasAnalysis *AA) const { 1001 bool SawStore = false; 1002 if (!TII->isTriviallyReMaterializable(this, AA) || 1003 !isSafeToMove(TII, SawStore, AA)) 1004 return false; 1005 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1006 const MachineOperand &MO = getOperand(i); 1007 if (!MO.isReg()) 1008 continue; 1009 // FIXME: For now, do not remat any instruction with register operands. 1010 // Later on, we can loosen the restriction is the register operands have 1011 // not been modified between the def and use. Note, this is different from 1012 // MachineSink because the code is no longer in two-address form (at least 1013 // partially). 1014 if (MO.isUse()) 1015 return false; 1016 else if (!MO.isDead() && MO.getReg() != DstReg) 1017 return false; 1018 } 1019 return true; 1020} 1021 1022/// hasVolatileMemoryRef - Return true if this instruction may have a 1023/// volatile memory reference, or if the information describing the 1024/// memory reference is not available. Return false if it is known to 1025/// have no volatile memory references. 1026bool MachineInstr::hasVolatileMemoryRef() const { 1027 // An instruction known never to access memory won't have a volatile access. 1028 if (!TID->mayStore() && 1029 !TID->mayLoad() && 1030 !TID->isCall() && 1031 !TID->hasUnmodeledSideEffects()) 1032 return false; 1033 1034 // Otherwise, if the instruction has no memory reference information, 1035 // conservatively assume it wasn't preserved. 1036 if (memoperands_empty()) 1037 return true; 1038 1039 // Check the memory reference information for volatile references. 1040 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I) 1041 if ((*I)->isVolatile()) 1042 return true; 1043 1044 return false; 1045} 1046 1047/// isInvariantLoad - Return true if this instruction is loading from a 1048/// location whose value is invariant across the function. For example, 1049/// loading a value from the constant pool or from from the argument area 1050/// of a function if it does not change. This should only return true of 1051/// *all* loads the instruction does are invariant (if it does multiple loads). 1052bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const { 1053 // If the instruction doesn't load at all, it isn't an invariant load. 1054 if (!TID->mayLoad()) 1055 return false; 1056 1057 // If the instruction has lost its memoperands, conservatively assume that 1058 // it may not be an invariant load. 1059 if (memoperands_empty()) 1060 return false; 1061 1062 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo(); 1063 1064 for (mmo_iterator I = memoperands_begin(), 1065 E = memoperands_end(); I != E; ++I) { 1066 if ((*I)->isVolatile()) return false; 1067 if ((*I)->isStore()) return false; 1068 1069 if (const Value *V = (*I)->getValue()) { 1070 // A load from a constant PseudoSourceValue is invariant. 1071 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) 1072 if (PSV->isConstant(MFI)) 1073 continue; 1074 // If we have an AliasAnalysis, ask it whether the memory is constant. 1075 if (AA && AA->pointsToConstantMemory(V)) 1076 continue; 1077 } 1078 1079 // Otherwise assume conservatively. 1080 return false; 1081 } 1082 1083 // Everything checks out. 1084 return true; 1085} 1086 1087/// isConstantValuePHI - If the specified instruction is a PHI that always 1088/// merges together the same virtual register, return the register, otherwise 1089/// return 0. 1090unsigned MachineInstr::isConstantValuePHI() const { 1091 if (getOpcode() != TargetInstrInfo::PHI) 1092 return 0; 1093 assert(getNumOperands() >= 3 && 1094 "It's illegal to have a PHI without source operands"); 1095 1096 unsigned Reg = getOperand(1).getReg(); 1097 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) 1098 if (getOperand(i).getReg() != Reg) 1099 return 0; 1100 return Reg; 1101} 1102 1103void MachineInstr::dump() const { 1104 dbgs() << " " << *this; 1105} 1106 1107void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { 1108 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction. 1109 const MachineFunction *MF = 0; 1110 if (const MachineBasicBlock *MBB = getParent()) { 1111 MF = MBB->getParent(); 1112 if (!TM && MF) 1113 TM = &MF->getTarget(); 1114 } 1115 1116 // Print explicitly defined operands on the left of an assignment syntax. 1117 unsigned StartOp = 0, e = getNumOperands(); 1118 for (; StartOp < e && getOperand(StartOp).isReg() && 1119 getOperand(StartOp).isDef() && 1120 !getOperand(StartOp).isImplicit(); 1121 ++StartOp) { 1122 if (StartOp != 0) OS << ", "; 1123 getOperand(StartOp).print(OS, TM); 1124 } 1125 1126 if (StartOp != 0) 1127 OS << " = "; 1128 1129 // Print the opcode name. 1130 OS << getDesc().getName(); 1131 1132 // Print the rest of the operands. 1133 bool OmittedAnyCallClobbers = false; 1134 bool FirstOp = true; 1135 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 1136 const MachineOperand &MO = getOperand(i); 1137 1138 // Omit call-clobbered registers which aren't used anywhere. This makes 1139 // call instructions much less noisy on targets where calls clobber lots 1140 // of registers. Don't rely on MO.isDead() because we may be called before 1141 // LiveVariables is run, or we may be looking at a non-allocatable reg. 1142 if (MF && getDesc().isCall() && 1143 MO.isReg() && MO.isImplicit() && MO.isDef()) { 1144 unsigned Reg = MO.getReg(); 1145 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) { 1146 const MachineRegisterInfo &MRI = MF->getRegInfo(); 1147 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) { 1148 bool HasAliasLive = false; 1149 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg); 1150 unsigned AliasReg = *Alias; ++Alias) 1151 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) { 1152 HasAliasLive = true; 1153 break; 1154 } 1155 if (!HasAliasLive) { 1156 OmittedAnyCallClobbers = true; 1157 continue; 1158 } 1159 } 1160 } 1161 } 1162 1163 if (FirstOp) FirstOp = false; else OS << ","; 1164 OS << " "; 1165 if (i < getDesc().NumOperands) { 1166 const TargetOperandInfo &TOI = getDesc().OpInfo[i]; 1167 if (TOI.isPredicate()) 1168 OS << "pred:"; 1169 if (TOI.isOptionalDef()) 1170 OS << "opt:"; 1171 } 1172 MO.print(OS, TM); 1173 } 1174 1175 // Briefly indicate whether any call clobbers were omitted. 1176 if (OmittedAnyCallClobbers) { 1177 if (!FirstOp) OS << ","; 1178 OS << " ..."; 1179 } 1180 1181 bool HaveSemi = false; 1182 if (!memoperands_empty()) { 1183 if (!HaveSemi) OS << ";"; HaveSemi = true; 1184 1185 OS << " mem:"; 1186 for (mmo_iterator i = memoperands_begin(), e = memoperands_end(); 1187 i != e; ++i) { 1188 OS << **i; 1189 if (next(i) != e) 1190 OS << " "; 1191 } 1192 } 1193 1194 if (!debugLoc.isUnknown() && MF) { 1195 if (!HaveSemi) OS << ";"; 1196 1197 // TODO: print InlinedAtLoc information 1198 1199 DILocation DLT = MF->getDILocation(debugLoc); 1200 DIScope Scope = DLT.getScope(); 1201 OS << " dbg:"; 1202 // Omit the directory, since it's usually long and uninteresting. 1203 if (!Scope.isNull()) 1204 OS << Scope.getFilename(); 1205 else 1206 OS << "<unknown>"; 1207 OS << ':' << DLT.getLineNumber(); 1208 if (DLT.getColumnNumber() != 0) 1209 OS << ':' << DLT.getColumnNumber(); 1210 } 1211 1212 OS << "\n"; 1213} 1214 1215bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 1216 const TargetRegisterInfo *RegInfo, 1217 bool AddIfNotFound) { 1218 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1219 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 1220 bool Found = false; 1221 SmallVector<unsigned,4> DeadOps; 1222 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1223 MachineOperand &MO = getOperand(i); 1224 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) 1225 continue; 1226 unsigned Reg = MO.getReg(); 1227 if (!Reg) 1228 continue; 1229 1230 if (Reg == IncomingReg) { 1231 if (!Found) { 1232 if (MO.isKill()) 1233 // The register is already marked kill. 1234 return true; 1235 if (isPhysReg && isRegTiedToDefOperand(i)) 1236 // Two-address uses of physregs must not be marked kill. 1237 return true; 1238 MO.setIsKill(); 1239 Found = true; 1240 } 1241 } else if (hasAliases && MO.isKill() && 1242 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1243 // A super-register kill already exists. 1244 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1245 return true; 1246 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1247 DeadOps.push_back(i); 1248 } 1249 } 1250 1251 // Trim unneeded kill operands. 1252 while (!DeadOps.empty()) { 1253 unsigned OpIdx = DeadOps.back(); 1254 if (getOperand(OpIdx).isImplicit()) 1255 RemoveOperand(OpIdx); 1256 else 1257 getOperand(OpIdx).setIsKill(false); 1258 DeadOps.pop_back(); 1259 } 1260 1261 // If not found, this means an alias of one of the operands is killed. Add a 1262 // new implicit operand if required. 1263 if (!Found && AddIfNotFound) { 1264 addOperand(MachineOperand::CreateReg(IncomingReg, 1265 false /*IsDef*/, 1266 true /*IsImp*/, 1267 true /*IsKill*/)); 1268 return true; 1269 } 1270 return Found; 1271} 1272 1273bool MachineInstr::addRegisterDead(unsigned IncomingReg, 1274 const TargetRegisterInfo *RegInfo, 1275 bool AddIfNotFound) { 1276 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1277 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 1278 bool Found = false; 1279 SmallVector<unsigned,4> DeadOps; 1280 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1281 MachineOperand &MO = getOperand(i); 1282 if (!MO.isReg() || !MO.isDef()) 1283 continue; 1284 unsigned Reg = MO.getReg(); 1285 if (!Reg) 1286 continue; 1287 1288 if (Reg == IncomingReg) { 1289 if (!Found) { 1290 if (MO.isDead()) 1291 // The register is already marked dead. 1292 return true; 1293 MO.setIsDead(); 1294 Found = true; 1295 } 1296 } else if (hasAliases && MO.isDead() && 1297 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1298 // There exists a super-register that's marked dead. 1299 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1300 return true; 1301 if (RegInfo->getSubRegisters(IncomingReg) && 1302 RegInfo->getSuperRegisters(Reg) && 1303 RegInfo->isSubRegister(IncomingReg, Reg)) 1304 DeadOps.push_back(i); 1305 } 1306 } 1307 1308 // Trim unneeded dead operands. 1309 while (!DeadOps.empty()) { 1310 unsigned OpIdx = DeadOps.back(); 1311 if (getOperand(OpIdx).isImplicit()) 1312 RemoveOperand(OpIdx); 1313 else 1314 getOperand(OpIdx).setIsDead(false); 1315 DeadOps.pop_back(); 1316 } 1317 1318 // If not found, this means an alias of one of the operands is dead. Add a 1319 // new implicit operand if required. 1320 if (Found || !AddIfNotFound) 1321 return Found; 1322 1323 addOperand(MachineOperand::CreateReg(IncomingReg, 1324 true /*IsDef*/, 1325 true /*IsImp*/, 1326 false /*IsKill*/, 1327 true /*IsDead*/)); 1328 return true; 1329} 1330 1331void MachineInstr::addRegisterDefined(unsigned IncomingReg, 1332 const TargetRegisterInfo *RegInfo) { 1333 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo); 1334 if (!MO || MO->getSubReg()) 1335 addOperand(MachineOperand::CreateReg(IncomingReg, 1336 true /*IsDef*/, 1337 true /*IsImp*/)); 1338} 1339