MachineInstr.cpp revision 198892
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Methods common to all machine instructions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineInstr.h" 15#include "llvm/Constants.h" 16#include "llvm/Function.h" 17#include "llvm/InlineAsm.h" 18#include "llvm/Value.h" 19#include "llvm/Assembly/Writer.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineMemOperand.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/PseudoSourceValue.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetInstrInfo.h" 26#include "llvm/Target/TargetInstrDesc.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Analysis/AliasAnalysis.h" 29#include "llvm/Analysis/DebugInfo.h" 30#include "llvm/Support/ErrorHandling.h" 31#include "llvm/Support/LeakDetector.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Support/raw_ostream.h" 34#include "llvm/ADT/FoldingSet.h" 35using namespace llvm; 36 37//===----------------------------------------------------------------------===// 38// MachineOperand Implementation 39//===----------------------------------------------------------------------===// 40 41/// AddRegOperandToRegInfo - Add this register operand to the specified 42/// MachineRegisterInfo. If it is null, then the next/prev fields should be 43/// explicitly nulled out. 44void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { 45 assert(isReg() && "Can only add reg operand to use lists"); 46 47 // If the reginfo pointer is null, just explicitly null out or next/prev 48 // pointers, to ensure they are not garbage. 49 if (RegInfo == 0) { 50 Contents.Reg.Prev = 0; 51 Contents.Reg.Next = 0; 52 return; 53 } 54 55 // Otherwise, add this operand to the head of the registers use/def list. 56 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg()); 57 58 // For SSA values, we prefer to keep the definition at the start of the list. 59 // we do this by skipping over the definition if it is at the head of the 60 // list. 61 if (*Head && (*Head)->isDef()) 62 Head = &(*Head)->Contents.Reg.Next; 63 64 Contents.Reg.Next = *Head; 65 if (Contents.Reg.Next) { 66 assert(getReg() == Contents.Reg.Next->getReg() && 67 "Different regs on the same list!"); 68 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next; 69 } 70 71 Contents.Reg.Prev = Head; 72 *Head = this; 73} 74 75/// RemoveRegOperandFromRegInfo - Remove this register operand from the 76/// MachineRegisterInfo it is linked with. 77void MachineOperand::RemoveRegOperandFromRegInfo() { 78 assert(isOnRegUseList() && "Reg operand is not on a use list"); 79 // Unlink this from the doubly linked list of operands. 80 MachineOperand *NextOp = Contents.Reg.Next; 81 *Contents.Reg.Prev = NextOp; 82 if (NextOp) { 83 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!"); 84 NextOp->Contents.Reg.Prev = Contents.Reg.Prev; 85 } 86 Contents.Reg.Prev = 0; 87 Contents.Reg.Next = 0; 88} 89 90void MachineOperand::setReg(unsigned Reg) { 91 if (getReg() == Reg) return; // No change. 92 93 // Otherwise, we have to change the register. If this operand is embedded 94 // into a machine function, we need to update the old and new register's 95 // use/def lists. 96 if (MachineInstr *MI = getParent()) 97 if (MachineBasicBlock *MBB = MI->getParent()) 98 if (MachineFunction *MF = MBB->getParent()) { 99 RemoveRegOperandFromRegInfo(); 100 Contents.Reg.RegNo = Reg; 101 AddRegOperandToRegInfo(&MF->getRegInfo()); 102 return; 103 } 104 105 // Otherwise, just change the register, no problem. :) 106 Contents.Reg.RegNo = Reg; 107} 108 109/// ChangeToImmediate - Replace this operand with a new immediate operand of 110/// the specified value. If an operand is known to be an immediate already, 111/// the setImm method should be used. 112void MachineOperand::ChangeToImmediate(int64_t ImmVal) { 113 // If this operand is currently a register operand, and if this is in a 114 // function, deregister the operand from the register's use/def list. 115 if (isReg() && getParent() && getParent()->getParent() && 116 getParent()->getParent()->getParent()) 117 RemoveRegOperandFromRegInfo(); 118 119 OpKind = MO_Immediate; 120 Contents.ImmVal = ImmVal; 121} 122 123/// ChangeToRegister - Replace this operand with a new register operand of 124/// the specified value. If an operand is known to be an register already, 125/// the setReg method should be used. 126void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 127 bool isKill, bool isDead, bool isUndef) { 128 // If this operand is already a register operand, use setReg to update the 129 // register's use/def lists. 130 if (isReg()) { 131 assert(!isEarlyClobber()); 132 setReg(Reg); 133 } else { 134 // Otherwise, change this to a register and set the reg#. 135 OpKind = MO_Register; 136 Contents.Reg.RegNo = Reg; 137 138 // If this operand is embedded in a function, add the operand to the 139 // register's use/def list. 140 if (MachineInstr *MI = getParent()) 141 if (MachineBasicBlock *MBB = MI->getParent()) 142 if (MachineFunction *MF = MBB->getParent()) 143 AddRegOperandToRegInfo(&MF->getRegInfo()); 144 } 145 146 IsDef = isDef; 147 IsImp = isImp; 148 IsKill = isKill; 149 IsDead = isDead; 150 IsUndef = isUndef; 151 IsEarlyClobber = false; 152 SubReg = 0; 153} 154 155/// isIdenticalTo - Return true if this operand is identical to the specified 156/// operand. 157bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 158 if (getType() != Other.getType() || 159 getTargetFlags() != Other.getTargetFlags()) 160 return false; 161 162 switch (getType()) { 163 default: llvm_unreachable("Unrecognized operand type"); 164 case MachineOperand::MO_Register: 165 return getReg() == Other.getReg() && isDef() == Other.isDef() && 166 getSubReg() == Other.getSubReg(); 167 case MachineOperand::MO_Immediate: 168 return getImm() == Other.getImm(); 169 case MachineOperand::MO_FPImmediate: 170 return getFPImm() == Other.getFPImm(); 171 case MachineOperand::MO_MachineBasicBlock: 172 return getMBB() == Other.getMBB(); 173 case MachineOperand::MO_FrameIndex: 174 return getIndex() == Other.getIndex(); 175 case MachineOperand::MO_ConstantPoolIndex: 176 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 177 case MachineOperand::MO_JumpTableIndex: 178 return getIndex() == Other.getIndex(); 179 case MachineOperand::MO_GlobalAddress: 180 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 181 case MachineOperand::MO_ExternalSymbol: 182 return !strcmp(getSymbolName(), Other.getSymbolName()) && 183 getOffset() == Other.getOffset(); 184 case MachineOperand::MO_BlockAddress: 185 return getBlockAddress() == Other.getBlockAddress(); 186 } 187} 188 189/// print - Print the specified machine operand. 190/// 191void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 192 switch (getType()) { 193 case MachineOperand::MO_Register: 194 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) { 195 OS << "%reg" << getReg(); 196 } else { 197 // If the instruction is embedded into a basic block, we can find the 198 // target info for the instruction. 199 if (TM == 0) 200 if (const MachineInstr *MI = getParent()) 201 if (const MachineBasicBlock *MBB = MI->getParent()) 202 if (const MachineFunction *MF = MBB->getParent()) 203 TM = &MF->getTarget(); 204 205 if (TM) 206 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name; 207 else 208 OS << "%physreg" << getReg(); 209 } 210 211 if (getSubReg() != 0) 212 OS << ':' << getSubReg(); 213 214 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || 215 isEarlyClobber()) { 216 OS << '<'; 217 bool NeedComma = false; 218 if (isDef()) { 219 if (NeedComma) OS << ','; 220 if (isEarlyClobber()) 221 OS << "earlyclobber,"; 222 if (isImplicit()) 223 OS << "imp-"; 224 OS << "def"; 225 NeedComma = true; 226 } else if (isImplicit()) { 227 OS << "imp-use"; 228 NeedComma = true; 229 } 230 231 if (isKill() || isDead() || isUndef()) { 232 if (NeedComma) OS << ','; 233 if (isKill()) OS << "kill"; 234 if (isDead()) OS << "dead"; 235 if (isUndef()) { 236 if (isKill() || isDead()) 237 OS << ','; 238 OS << "undef"; 239 } 240 } 241 OS << '>'; 242 } 243 break; 244 case MachineOperand::MO_Immediate: 245 OS << getImm(); 246 break; 247 case MachineOperand::MO_FPImmediate: 248 if (getFPImm()->getType()->isFloatTy()) 249 OS << getFPImm()->getValueAPF().convertToFloat(); 250 else 251 OS << getFPImm()->getValueAPF().convertToDouble(); 252 break; 253 case MachineOperand::MO_MachineBasicBlock: 254 OS << "<BB#" << getMBB()->getNumber() << ">"; 255 break; 256 case MachineOperand::MO_FrameIndex: 257 OS << "<fi#" << getIndex() << '>'; 258 break; 259 case MachineOperand::MO_ConstantPoolIndex: 260 OS << "<cp#" << getIndex(); 261 if (getOffset()) OS << "+" << getOffset(); 262 OS << '>'; 263 break; 264 case MachineOperand::MO_JumpTableIndex: 265 OS << "<jt#" << getIndex() << '>'; 266 break; 267 case MachineOperand::MO_GlobalAddress: 268 OS << "<ga:" << ((Value*)getGlobal())->getName(); 269 if (getOffset()) OS << "+" << getOffset(); 270 OS << '>'; 271 break; 272 case MachineOperand::MO_ExternalSymbol: 273 OS << "<es:" << getSymbolName(); 274 if (getOffset()) OS << "+" << getOffset(); 275 OS << '>'; 276 break; 277 case MachineOperand::MO_BlockAddress: 278 OS << "<"; 279 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false); 280 OS << '>'; 281 break; 282 default: 283 llvm_unreachable("Unrecognized operand type"); 284 } 285 286 if (unsigned TF = getTargetFlags()) 287 OS << "[TF=" << TF << ']'; 288} 289 290//===----------------------------------------------------------------------===// 291// MachineMemOperand Implementation 292//===----------------------------------------------------------------------===// 293 294MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f, 295 int64_t o, uint64_t s, unsigned int a) 296 : Offset(o), Size(s), V(v), 297 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) { 298 assert(getBaseAlignment() == a && "Alignment is not a power of 2!"); 299 assert((isLoad() || isStore()) && "Not a load/store!"); 300} 301 302/// Profile - Gather unique data for the object. 303/// 304void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 305 ID.AddInteger(Offset); 306 ID.AddInteger(Size); 307 ID.AddPointer(V); 308 ID.AddInteger(Flags); 309} 310 311void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { 312 // The Value and Offset may differ due to CSE. But the flags and size 313 // should be the same. 314 assert(MMO->getFlags() == getFlags() && "Flags mismatch!"); 315 assert(MMO->getSize() == getSize() && "Size mismatch!"); 316 317 if (MMO->getBaseAlignment() >= getBaseAlignment()) { 318 // Update the alignment value. 319 Flags = (Flags & 7) | ((Log2_32(MMO->getBaseAlignment()) + 1) << 3); 320 // Also update the base and offset, because the new alignment may 321 // not be applicable with the old ones. 322 V = MMO->getValue(); 323 Offset = MMO->getOffset(); 324 } 325} 326 327/// getAlignment - Return the minimum known alignment in bytes of the 328/// actual memory reference. 329uint64_t MachineMemOperand::getAlignment() const { 330 return MinAlign(getBaseAlignment(), getOffset()); 331} 332 333raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) { 334 assert((MMO.isLoad() || MMO.isStore()) && 335 "SV has to be a load, store or both."); 336 337 if (MMO.isVolatile()) 338 OS << "Volatile "; 339 340 if (MMO.isLoad()) 341 OS << "LD"; 342 if (MMO.isStore()) 343 OS << "ST"; 344 OS << MMO.getSize(); 345 346 // Print the address information. 347 OS << "["; 348 if (!MMO.getValue()) 349 OS << "<unknown>"; 350 else 351 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false); 352 353 // If the alignment of the memory reference itself differs from the alignment 354 // of the base pointer, print the base alignment explicitly, next to the base 355 // pointer. 356 if (MMO.getBaseAlignment() != MMO.getAlignment()) 357 OS << "(align=" << MMO.getBaseAlignment() << ")"; 358 359 if (MMO.getOffset() != 0) 360 OS << "+" << MMO.getOffset(); 361 OS << "]"; 362 363 // Print the alignment of the reference. 364 if (MMO.getBaseAlignment() != MMO.getAlignment() || 365 MMO.getBaseAlignment() != MMO.getSize()) 366 OS << "(align=" << MMO.getAlignment() << ")"; 367 368 return OS; 369} 370 371//===----------------------------------------------------------------------===// 372// MachineInstr Implementation 373//===----------------------------------------------------------------------===// 374 375/// MachineInstr ctor - This constructor creates a dummy MachineInstr with 376/// TID NULL and no operands. 377MachineInstr::MachineInstr() 378 : TID(0), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0), 379 Parent(0), debugLoc(DebugLoc::getUnknownLoc()) { 380 // Make sure that we get added to a machine basicblock 381 LeakDetector::addGarbageObject(this); 382} 383 384void MachineInstr::addImplicitDefUseOperands() { 385 if (TID->ImplicitDefs) 386 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) 387 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 388 if (TID->ImplicitUses) 389 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) 390 addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 391} 392 393/// MachineInstr ctor - This constructor create a MachineInstr and add the 394/// implicit operands. It reserves space for number of operands specified by 395/// TargetInstrDesc or the numOperands if it is not zero. (for 396/// instructions with variable number of operands). 397MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) 398 : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0), Parent(0), 399 debugLoc(DebugLoc::getUnknownLoc()) { 400 if (!NoImp && TID->getImplicitDefs()) 401 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 402 NumImplicitOps++; 403 if (!NoImp && TID->getImplicitUses()) 404 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 405 NumImplicitOps++; 406 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 407 if (!NoImp) 408 addImplicitDefUseOperands(); 409 // Make sure that we get added to a machine basicblock 410 LeakDetector::addGarbageObject(this); 411} 412 413/// MachineInstr ctor - As above, but with a DebugLoc. 414MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl, 415 bool NoImp) 416 : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0), 417 Parent(0), debugLoc(dl) { 418 if (!NoImp && TID->getImplicitDefs()) 419 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 420 NumImplicitOps++; 421 if (!NoImp && TID->getImplicitUses()) 422 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 423 NumImplicitOps++; 424 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 425 if (!NoImp) 426 addImplicitDefUseOperands(); 427 // Make sure that we get added to a machine basicblock 428 LeakDetector::addGarbageObject(this); 429} 430 431/// MachineInstr ctor - Work exactly the same as the ctor two above, except 432/// that the MachineInstr is created and added to the end of the specified 433/// basic block. 434/// 435MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid) 436 : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0), Parent(0), 437 debugLoc(DebugLoc::getUnknownLoc()) { 438 assert(MBB && "Cannot use inserting ctor with null basic block!"); 439 if (TID->ImplicitDefs) 440 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 441 NumImplicitOps++; 442 if (TID->ImplicitUses) 443 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 444 NumImplicitOps++; 445 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 446 addImplicitDefUseOperands(); 447 // Make sure that we get added to a machine basicblock 448 LeakDetector::addGarbageObject(this); 449 MBB->push_back(this); // Add instruction to end of basic block! 450} 451 452/// MachineInstr ctor - As above, but with a DebugLoc. 453/// 454MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, 455 const TargetInstrDesc &tid) 456 : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0), 457 Parent(0), debugLoc(dl) { 458 assert(MBB && "Cannot use inserting ctor with null basic block!"); 459 if (TID->ImplicitDefs) 460 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 461 NumImplicitOps++; 462 if (TID->ImplicitUses) 463 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 464 NumImplicitOps++; 465 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 466 addImplicitDefUseOperands(); 467 // Make sure that we get added to a machine basicblock 468 LeakDetector::addGarbageObject(this); 469 MBB->push_back(this); // Add instruction to end of basic block! 470} 471 472/// MachineInstr ctor - Copies MachineInstr arg exactly 473/// 474MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 475 : TID(&MI.getDesc()), NumImplicitOps(0), 476 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd), 477 Parent(0), debugLoc(MI.getDebugLoc()) { 478 Operands.reserve(MI.getNumOperands()); 479 480 // Add operands 481 for (unsigned i = 0; i != MI.getNumOperands(); ++i) 482 addOperand(MI.getOperand(i)); 483 NumImplicitOps = MI.NumImplicitOps; 484 485 // Set parent to null. 486 Parent = 0; 487 488 LeakDetector::addGarbageObject(this); 489} 490 491MachineInstr::~MachineInstr() { 492 LeakDetector::removeGarbageObject(this); 493#ifndef NDEBUG 494 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 495 assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 496 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 497 "Reg operand def/use list corrupted"); 498 } 499#endif 500} 501 502/// getRegInfo - If this instruction is embedded into a MachineFunction, 503/// return the MachineRegisterInfo object for the current function, otherwise 504/// return null. 505MachineRegisterInfo *MachineInstr::getRegInfo() { 506 if (MachineBasicBlock *MBB = getParent()) 507 return &MBB->getParent()->getRegInfo(); 508 return 0; 509} 510 511/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 512/// this instruction from their respective use lists. This requires that the 513/// operands already be on their use lists. 514void MachineInstr::RemoveRegOperandsFromUseLists() { 515 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 516 if (Operands[i].isReg()) 517 Operands[i].RemoveRegOperandFromRegInfo(); 518 } 519} 520 521/// AddRegOperandsToUseLists - Add all of the register operands in 522/// this instruction from their respective use lists. This requires that the 523/// operands not be on their use lists yet. 524void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { 525 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 526 if (Operands[i].isReg()) 527 Operands[i].AddRegOperandToRegInfo(&RegInfo); 528 } 529} 530 531 532/// addOperand - Add the specified operand to the instruction. If it is an 533/// implicit operand, it is added to the end of the operand list. If it is 534/// an explicit operand it is added at the end of the explicit operand list 535/// (before the first implicit operand). 536void MachineInstr::addOperand(const MachineOperand &Op) { 537 bool isImpReg = Op.isReg() && Op.isImplicit(); 538 assert((isImpReg || !OperandsComplete()) && 539 "Trying to add an operand to a machine instr that is already done!"); 540 541 MachineRegisterInfo *RegInfo = getRegInfo(); 542 543 // If we are adding the operand to the end of the list, our job is simpler. 544 // This is true most of the time, so this is a reasonable optimization. 545 if (isImpReg || NumImplicitOps == 0) { 546 // We can only do this optimization if we know that the operand list won't 547 // reallocate. 548 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) { 549 Operands.push_back(Op); 550 551 // Set the parent of the operand. 552 Operands.back().ParentMI = this; 553 554 // If the operand is a register, update the operand's use list. 555 if (Op.isReg()) 556 Operands.back().AddRegOperandToRegInfo(RegInfo); 557 return; 558 } 559 } 560 561 // Otherwise, we have to insert a real operand before any implicit ones. 562 unsigned OpNo = Operands.size()-NumImplicitOps; 563 564 // If this instruction isn't embedded into a function, then we don't need to 565 // update any operand lists. 566 if (RegInfo == 0) { 567 // Simple insertion, no reginfo update needed for other register operands. 568 Operands.insert(Operands.begin()+OpNo, Op); 569 Operands[OpNo].ParentMI = this; 570 571 // Do explicitly set the reginfo for this operand though, to ensure the 572 // next/prev fields are properly nulled out. 573 if (Operands[OpNo].isReg()) 574 Operands[OpNo].AddRegOperandToRegInfo(0); 575 576 } else if (Operands.size()+1 <= Operands.capacity()) { 577 // Otherwise, we have to remove register operands from their register use 578 // list, add the operand, then add the register operands back to their use 579 // list. This also must handle the case when the operand list reallocates 580 // to somewhere else. 581 582 // If insertion of this operand won't cause reallocation of the operand 583 // list, just remove the implicit operands, add the operand, then re-add all 584 // the rest of the operands. 585 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 586 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 587 Operands[i].RemoveRegOperandFromRegInfo(); 588 } 589 590 // Add the operand. If it is a register, add it to the reg list. 591 Operands.insert(Operands.begin()+OpNo, Op); 592 Operands[OpNo].ParentMI = this; 593 594 if (Operands[OpNo].isReg()) 595 Operands[OpNo].AddRegOperandToRegInfo(RegInfo); 596 597 // Re-add all the implicit ops. 598 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) { 599 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 600 Operands[i].AddRegOperandToRegInfo(RegInfo); 601 } 602 } else { 603 // Otherwise, we will be reallocating the operand list. Remove all reg 604 // operands from their list, then readd them after the operand list is 605 // reallocated. 606 RemoveRegOperandsFromUseLists(); 607 608 Operands.insert(Operands.begin()+OpNo, Op); 609 Operands[OpNo].ParentMI = this; 610 611 // Re-add all the operands. 612 AddRegOperandsToUseLists(*RegInfo); 613 } 614} 615 616/// RemoveOperand - Erase an operand from an instruction, leaving it with one 617/// fewer operand than it started with. 618/// 619void MachineInstr::RemoveOperand(unsigned OpNo) { 620 assert(OpNo < Operands.size() && "Invalid operand number"); 621 622 // Special case removing the last one. 623 if (OpNo == Operands.size()-1) { 624 // If needed, remove from the reg def/use list. 625 if (Operands.back().isReg() && Operands.back().isOnRegUseList()) 626 Operands.back().RemoveRegOperandFromRegInfo(); 627 628 Operands.pop_back(); 629 return; 630 } 631 632 // Otherwise, we are removing an interior operand. If we have reginfo to 633 // update, remove all operands that will be shifted down from their reg lists, 634 // move everything down, then re-add them. 635 MachineRegisterInfo *RegInfo = getRegInfo(); 636 if (RegInfo) { 637 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 638 if (Operands[i].isReg()) 639 Operands[i].RemoveRegOperandFromRegInfo(); 640 } 641 } 642 643 Operands.erase(Operands.begin()+OpNo); 644 645 if (RegInfo) { 646 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 647 if (Operands[i].isReg()) 648 Operands[i].AddRegOperandToRegInfo(RegInfo); 649 } 650 } 651} 652 653/// addMemOperand - Add a MachineMemOperand to the machine instruction. 654/// This function should be used only occasionally. The setMemRefs function 655/// is the primary method for setting up a MachineInstr's MemRefs list. 656void MachineInstr::addMemOperand(MachineFunction &MF, 657 MachineMemOperand *MO) { 658 mmo_iterator OldMemRefs = MemRefs; 659 mmo_iterator OldMemRefsEnd = MemRefsEnd; 660 661 size_t NewNum = (MemRefsEnd - MemRefs) + 1; 662 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum); 663 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum; 664 665 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs); 666 NewMemRefs[NewNum - 1] = MO; 667 668 MemRefs = NewMemRefs; 669 MemRefsEnd = NewMemRefsEnd; 670} 671 672/// removeFromParent - This method unlinks 'this' from the containing basic 673/// block, and returns it, but does not delete it. 674MachineInstr *MachineInstr::removeFromParent() { 675 assert(getParent() && "Not embedded in a basic block!"); 676 getParent()->remove(this); 677 return this; 678} 679 680 681/// eraseFromParent - This method unlinks 'this' from the containing basic 682/// block, and deletes it. 683void MachineInstr::eraseFromParent() { 684 assert(getParent() && "Not embedded in a basic block!"); 685 getParent()->erase(this); 686} 687 688 689/// OperandComplete - Return true if it's illegal to add a new operand 690/// 691bool MachineInstr::OperandsComplete() const { 692 unsigned short NumOperands = TID->getNumOperands(); 693 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands) 694 return true; // Broken: we have all the operands of this instruction! 695 return false; 696} 697 698/// getNumExplicitOperands - Returns the number of non-implicit operands. 699/// 700unsigned MachineInstr::getNumExplicitOperands() const { 701 unsigned NumOperands = TID->getNumOperands(); 702 if (!TID->isVariadic()) 703 return NumOperands; 704 705 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) { 706 const MachineOperand &MO = getOperand(i); 707 if (!MO.isReg() || !MO.isImplicit()) 708 NumOperands++; 709 } 710 return NumOperands; 711} 712 713 714/// isLabel - Returns true if the MachineInstr represents a label. 715/// 716bool MachineInstr::isLabel() const { 717 return getOpcode() == TargetInstrInfo::DBG_LABEL || 718 getOpcode() == TargetInstrInfo::EH_LABEL || 719 getOpcode() == TargetInstrInfo::GC_LABEL; 720} 721 722/// isDebugLabel - Returns true if the MachineInstr represents a debug label. 723/// 724bool MachineInstr::isDebugLabel() const { 725 return getOpcode() == TargetInstrInfo::DBG_LABEL; 726} 727 728/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 729/// the specific register or -1 if it is not found. It further tightens 730/// the search criteria to a use that kills the register if isKill is true. 731int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 732 const TargetRegisterInfo *TRI) const { 733 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 734 const MachineOperand &MO = getOperand(i); 735 if (!MO.isReg() || !MO.isUse()) 736 continue; 737 unsigned MOReg = MO.getReg(); 738 if (!MOReg) 739 continue; 740 if (MOReg == Reg || 741 (TRI && 742 TargetRegisterInfo::isPhysicalRegister(MOReg) && 743 TargetRegisterInfo::isPhysicalRegister(Reg) && 744 TRI->isSubRegister(MOReg, Reg))) 745 if (!isKill || MO.isKill()) 746 return i; 747 } 748 return -1; 749} 750 751/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 752/// the specified register or -1 if it is not found. If isDead is true, defs 753/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 754/// also checks if there is a def of a super-register. 755int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, 756 const TargetRegisterInfo *TRI) const { 757 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 758 const MachineOperand &MO = getOperand(i); 759 if (!MO.isReg() || !MO.isDef()) 760 continue; 761 unsigned MOReg = MO.getReg(); 762 if (MOReg == Reg || 763 (TRI && 764 TargetRegisterInfo::isPhysicalRegister(MOReg) && 765 TargetRegisterInfo::isPhysicalRegister(Reg) && 766 TRI->isSubRegister(MOReg, Reg))) 767 if (!isDead || MO.isDead()) 768 return i; 769 } 770 return -1; 771} 772 773/// findFirstPredOperandIdx() - Find the index of the first operand in the 774/// operand list that is used to represent the predicate. It returns -1 if 775/// none is found. 776int MachineInstr::findFirstPredOperandIdx() const { 777 const TargetInstrDesc &TID = getDesc(); 778 if (TID.isPredicable()) { 779 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 780 if (TID.OpInfo[i].isPredicate()) 781 return i; 782 } 783 784 return -1; 785} 786 787/// isRegTiedToUseOperand - Given the index of a register def operand, 788/// check if the register def is tied to a source operand, due to either 789/// two-address elimination or inline assembly constraints. Returns the 790/// first tied use operand index by reference is UseOpIdx is not null. 791bool MachineInstr:: 792isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const { 793 if (getOpcode() == TargetInstrInfo::INLINEASM) { 794 assert(DefOpIdx >= 2); 795 const MachineOperand &MO = getOperand(DefOpIdx); 796 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0) 797 return false; 798 // Determine the actual operand index that corresponds to this index. 799 unsigned DefNo = 0; 800 unsigned DefPart = 0; 801 for (unsigned i = 1, e = getNumOperands(); i < e; ) { 802 const MachineOperand &FMO = getOperand(i); 803 // After the normal asm operands there may be additional imp-def regs. 804 if (!FMO.isImm()) 805 return false; 806 // Skip over this def. 807 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm()); 808 unsigned PrevDef = i + 1; 809 i = PrevDef + NumOps; 810 if (i > DefOpIdx) { 811 DefPart = DefOpIdx - PrevDef; 812 break; 813 } 814 ++DefNo; 815 } 816 for (unsigned i = 1, e = getNumOperands(); i != e; ++i) { 817 const MachineOperand &FMO = getOperand(i); 818 if (!FMO.isImm()) 819 continue; 820 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse()) 821 continue; 822 unsigned Idx; 823 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) && 824 Idx == DefNo) { 825 if (UseOpIdx) 826 *UseOpIdx = (unsigned)i + 1 + DefPart; 827 return true; 828 } 829 } 830 return false; 831 } 832 833 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!"); 834 const TargetInstrDesc &TID = getDesc(); 835 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { 836 const MachineOperand &MO = getOperand(i); 837 if (MO.isReg() && MO.isUse() && 838 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) { 839 if (UseOpIdx) 840 *UseOpIdx = (unsigned)i; 841 return true; 842 } 843 } 844 return false; 845} 846 847/// isRegTiedToDefOperand - Return true if the operand of the specified index 848/// is a register use and it is tied to an def operand. It also returns the def 849/// operand index by reference. 850bool MachineInstr:: 851isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const { 852 if (getOpcode() == TargetInstrInfo::INLINEASM) { 853 const MachineOperand &MO = getOperand(UseOpIdx); 854 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0) 855 return false; 856 857 // Find the flag operand corresponding to UseOpIdx 858 unsigned FlagIdx, NumOps=0; 859 for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) { 860 const MachineOperand &UFMO = getOperand(FlagIdx); 861 // After the normal asm operands there may be additional imp-def regs. 862 if (!UFMO.isImm()) 863 return false; 864 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm()); 865 assert(NumOps < getNumOperands() && "Invalid inline asm flag"); 866 if (UseOpIdx < FlagIdx+NumOps+1) 867 break; 868 } 869 if (FlagIdx >= UseOpIdx) 870 return false; 871 const MachineOperand &UFMO = getOperand(FlagIdx); 872 unsigned DefNo; 873 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) { 874 if (!DefOpIdx) 875 return true; 876 877 unsigned DefIdx = 1; 878 // Remember to adjust the index. First operand is asm string, then there 879 // is a flag for each. 880 while (DefNo) { 881 const MachineOperand &FMO = getOperand(DefIdx); 882 assert(FMO.isImm()); 883 // Skip over this def. 884 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1; 885 --DefNo; 886 } 887 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx; 888 return true; 889 } 890 return false; 891 } 892 893 const TargetInstrDesc &TID = getDesc(); 894 if (UseOpIdx >= TID.getNumOperands()) 895 return false; 896 const MachineOperand &MO = getOperand(UseOpIdx); 897 if (!MO.isReg() || !MO.isUse()) 898 return false; 899 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO); 900 if (DefIdx == -1) 901 return false; 902 if (DefOpIdx) 903 *DefOpIdx = (unsigned)DefIdx; 904 return true; 905} 906 907/// copyKillDeadInfo - Copies kill / dead operand properties from MI. 908/// 909void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 910 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 911 const MachineOperand &MO = MI->getOperand(i); 912 if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) 913 continue; 914 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 915 MachineOperand &MOp = getOperand(j); 916 if (!MOp.isIdenticalTo(MO)) 917 continue; 918 if (MO.isKill()) 919 MOp.setIsKill(); 920 else 921 MOp.setIsDead(); 922 break; 923 } 924 } 925} 926 927/// copyPredicates - Copies predicate operand(s) from MI. 928void MachineInstr::copyPredicates(const MachineInstr *MI) { 929 const TargetInstrDesc &TID = MI->getDesc(); 930 if (!TID.isPredicable()) 931 return; 932 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 933 if (TID.OpInfo[i].isPredicate()) { 934 // Predicated operands must be last operands. 935 addOperand(MI->getOperand(i)); 936 } 937 } 938} 939 940/// isSafeToMove - Return true if it is safe to move this instruction. If 941/// SawStore is set to true, it means that there is a store (or call) between 942/// the instruction's location and its intended destination. 943bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, 944 bool &SawStore, 945 AliasAnalysis *AA) const { 946 // Ignore stuff that we obviously can't move. 947 if (TID->mayStore() || TID->isCall()) { 948 SawStore = true; 949 return false; 950 } 951 if (TID->isTerminator() || TID->hasUnmodeledSideEffects()) 952 return false; 953 954 // See if this instruction does a load. If so, we have to guarantee that the 955 // loaded value doesn't change between the load and the its intended 956 // destination. The check for isInvariantLoad gives the targe the chance to 957 // classify the load as always returning a constant, e.g. a constant pool 958 // load. 959 if (TID->mayLoad() && !isInvariantLoad(AA)) 960 // Otherwise, this is a real load. If there is a store between the load and 961 // end of block, or if the load is volatile, we can't move it. 962 return !SawStore && !hasVolatileMemoryRef(); 963 964 return true; 965} 966 967/// isSafeToReMat - Return true if it's safe to rematerialize the specified 968/// instruction which defined the specified register instead of copying it. 969bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, 970 unsigned DstReg, 971 AliasAnalysis *AA) const { 972 bool SawStore = false; 973 if (!TII->isTriviallyReMaterializable(this, AA) || 974 !isSafeToMove(TII, SawStore, AA)) 975 return false; 976 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 977 const MachineOperand &MO = getOperand(i); 978 if (!MO.isReg()) 979 continue; 980 // FIXME: For now, do not remat any instruction with register operands. 981 // Later on, we can loosen the restriction is the register operands have 982 // not been modified between the def and use. Note, this is different from 983 // MachineSink because the code is no longer in two-address form (at least 984 // partially). 985 if (MO.isUse()) 986 return false; 987 else if (!MO.isDead() && MO.getReg() != DstReg) 988 return false; 989 } 990 return true; 991} 992 993/// hasVolatileMemoryRef - Return true if this instruction may have a 994/// volatile memory reference, or if the information describing the 995/// memory reference is not available. Return false if it is known to 996/// have no volatile memory references. 997bool MachineInstr::hasVolatileMemoryRef() const { 998 // An instruction known never to access memory won't have a volatile access. 999 if (!TID->mayStore() && 1000 !TID->mayLoad() && 1001 !TID->isCall() && 1002 !TID->hasUnmodeledSideEffects()) 1003 return false; 1004 1005 // Otherwise, if the instruction has no memory reference information, 1006 // conservatively assume it wasn't preserved. 1007 if (memoperands_empty()) 1008 return true; 1009 1010 // Check the memory reference information for volatile references. 1011 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I) 1012 if ((*I)->isVolatile()) 1013 return true; 1014 1015 return false; 1016} 1017 1018/// isInvariantLoad - Return true if this instruction is loading from a 1019/// location whose value is invariant across the function. For example, 1020/// loading a value from the constant pool or from from the argument area 1021/// of a function if it does not change. This should only return true of 1022/// *all* loads the instruction does are invariant (if it does multiple loads). 1023bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const { 1024 // If the instruction doesn't load at all, it isn't an invariant load. 1025 if (!TID->mayLoad()) 1026 return false; 1027 1028 // If the instruction has lost its memoperands, conservatively assume that 1029 // it may not be an invariant load. 1030 if (memoperands_empty()) 1031 return false; 1032 1033 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo(); 1034 1035 for (mmo_iterator I = memoperands_begin(), 1036 E = memoperands_end(); I != E; ++I) { 1037 if ((*I)->isVolatile()) return false; 1038 if ((*I)->isStore()) return false; 1039 1040 if (const Value *V = (*I)->getValue()) { 1041 // A load from a constant PseudoSourceValue is invariant. 1042 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) 1043 if (PSV->isConstant(MFI)) 1044 continue; 1045 // If we have an AliasAnalysis, ask it whether the memory is constant. 1046 if (AA && AA->pointsToConstantMemory(V)) 1047 continue; 1048 } 1049 1050 // Otherwise assume conservatively. 1051 return false; 1052 } 1053 1054 // Everything checks out. 1055 return true; 1056} 1057 1058void MachineInstr::dump() const { 1059 errs() << " " << *this; 1060} 1061 1062void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { 1063 unsigned StartOp = 0, e = getNumOperands(); 1064 1065 // Print explicitly defined operands on the left of an assignment syntax. 1066 for (; StartOp < e && getOperand(StartOp).isReg() && 1067 getOperand(StartOp).isDef() && 1068 !getOperand(StartOp).isImplicit(); 1069 ++StartOp) { 1070 if (StartOp != 0) OS << ", "; 1071 getOperand(StartOp).print(OS, TM); 1072 } 1073 1074 if (StartOp != 0) 1075 OS << " = "; 1076 1077 // Print the opcode name. 1078 OS << getDesc().getName(); 1079 1080 // Print the rest of the operands. 1081 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 1082 if (i != StartOp) 1083 OS << ","; 1084 OS << " "; 1085 getOperand(i).print(OS, TM); 1086 } 1087 1088 bool HaveSemi = false; 1089 if (!memoperands_empty()) { 1090 if (!HaveSemi) OS << ";"; HaveSemi = true; 1091 1092 OS << " mem:"; 1093 for (mmo_iterator i = memoperands_begin(), e = memoperands_end(); 1094 i != e; ++i) { 1095 OS << **i; 1096 if (next(i) != e) 1097 OS << " "; 1098 } 1099 } 1100 1101 if (!debugLoc.isUnknown()) { 1102 if (!HaveSemi) OS << ";"; HaveSemi = true; 1103 1104 // TODO: print InlinedAtLoc information 1105 1106 const MachineFunction *MF = getParent()->getParent(); 1107 DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc); 1108 DICompileUnit CU(DLT.Scope); 1109 if (!CU.isNull()) 1110 OS << " dbg:" << CU.getDirectory() << '/' << CU.getFilename() << ":" 1111 << DLT.Line << ":" << DLT.Col; 1112 } 1113 1114 OS << "\n"; 1115} 1116 1117bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 1118 const TargetRegisterInfo *RegInfo, 1119 bool AddIfNotFound) { 1120 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1121 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 1122 bool Found = false; 1123 SmallVector<unsigned,4> DeadOps; 1124 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1125 MachineOperand &MO = getOperand(i); 1126 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) 1127 continue; 1128 unsigned Reg = MO.getReg(); 1129 if (!Reg) 1130 continue; 1131 1132 if (Reg == IncomingReg) { 1133 if (!Found) { 1134 if (MO.isKill()) 1135 // The register is already marked kill. 1136 return true; 1137 if (isPhysReg && isRegTiedToDefOperand(i)) 1138 // Two-address uses of physregs must not be marked kill. 1139 return true; 1140 MO.setIsKill(); 1141 Found = true; 1142 } 1143 } else if (hasAliases && MO.isKill() && 1144 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1145 // A super-register kill already exists. 1146 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1147 return true; 1148 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1149 DeadOps.push_back(i); 1150 } 1151 } 1152 1153 // Trim unneeded kill operands. 1154 while (!DeadOps.empty()) { 1155 unsigned OpIdx = DeadOps.back(); 1156 if (getOperand(OpIdx).isImplicit()) 1157 RemoveOperand(OpIdx); 1158 else 1159 getOperand(OpIdx).setIsKill(false); 1160 DeadOps.pop_back(); 1161 } 1162 1163 // If not found, this means an alias of one of the operands is killed. Add a 1164 // new implicit operand if required. 1165 if (!Found && AddIfNotFound) { 1166 addOperand(MachineOperand::CreateReg(IncomingReg, 1167 false /*IsDef*/, 1168 true /*IsImp*/, 1169 true /*IsKill*/)); 1170 return true; 1171 } 1172 return Found; 1173} 1174 1175bool MachineInstr::addRegisterDead(unsigned IncomingReg, 1176 const TargetRegisterInfo *RegInfo, 1177 bool AddIfNotFound) { 1178 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1179 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 1180 bool Found = false; 1181 SmallVector<unsigned,4> DeadOps; 1182 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1183 MachineOperand &MO = getOperand(i); 1184 if (!MO.isReg() || !MO.isDef()) 1185 continue; 1186 unsigned Reg = MO.getReg(); 1187 if (!Reg) 1188 continue; 1189 1190 if (Reg == IncomingReg) { 1191 if (!Found) { 1192 if (MO.isDead()) 1193 // The register is already marked dead. 1194 return true; 1195 MO.setIsDead(); 1196 Found = true; 1197 } 1198 } else if (hasAliases && MO.isDead() && 1199 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1200 // There exists a super-register that's marked dead. 1201 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1202 return true; 1203 if (RegInfo->getSubRegisters(IncomingReg) && 1204 RegInfo->getSuperRegisters(Reg) && 1205 RegInfo->isSubRegister(IncomingReg, Reg)) 1206 DeadOps.push_back(i); 1207 } 1208 } 1209 1210 // Trim unneeded dead operands. 1211 while (!DeadOps.empty()) { 1212 unsigned OpIdx = DeadOps.back(); 1213 if (getOperand(OpIdx).isImplicit()) 1214 RemoveOperand(OpIdx); 1215 else 1216 getOperand(OpIdx).setIsDead(false); 1217 DeadOps.pop_back(); 1218 } 1219 1220 // If not found, this means an alias of one of the operands is dead. Add a 1221 // new implicit operand if required. 1222 if (Found || !AddIfNotFound) 1223 return Found; 1224 1225 addOperand(MachineOperand::CreateReg(IncomingReg, 1226 true /*IsDef*/, 1227 true /*IsImp*/, 1228 false /*IsKill*/, 1229 true /*IsDead*/)); 1230 return true; 1231} 1232