reload1.c revision 146895
1/* Reload pseudo regs into hard regs for insns that require hard regs. 2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify it under 8the terms of the GNU General Public License as published by the Free 9Software Foundation; either version 2, or (at your option) any later 10version. 11 12GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13WARRANTY; without even the implied warranty of MERCHANTABILITY or 14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING. If not, write to the Free 19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 2002111-1307, USA. */ 21 22#include "config.h" 23#include "system.h" 24#include "coretypes.h" 25#include "tm.h" 26 27#include "machmode.h" 28#include "hard-reg-set.h" 29#include "rtl.h" 30#include "tm_p.h" 31#include "obstack.h" 32#include "insn-config.h" 33#include "flags.h" 34#include "function.h" 35#include "expr.h" 36#include "optabs.h" 37#include "regs.h" 38#include "basic-block.h" 39#include "reload.h" 40#include "recog.h" 41#include "output.h" 42#include "real.h" 43#include "toplev.h" 44#include "except.h" 45#include "tree.h" 46 47/* This file contains the reload pass of the compiler, which is 48 run after register allocation has been done. It checks that 49 each insn is valid (operands required to be in registers really 50 are in registers of the proper class) and fixes up invalid ones 51 by copying values temporarily into registers for the insns 52 that need them. 53 54 The results of register allocation are described by the vector 55 reg_renumber; the insns still contain pseudo regs, but reg_renumber 56 can be used to find which hard reg, if any, a pseudo reg is in. 57 58 The technique we always use is to free up a few hard regs that are 59 called ``reload regs'', and for each place where a pseudo reg 60 must be in a hard reg, copy it temporarily into one of the reload regs. 61 62 Reload regs are allocated locally for every instruction that needs 63 reloads. When there are pseudos which are allocated to a register that 64 has been chosen as a reload reg, such pseudos must be ``spilled''. 65 This means that they go to other hard regs, or to stack slots if no other 66 available hard regs can be found. Spilling can invalidate more 67 insns, requiring additional need for reloads, so we must keep checking 68 until the process stabilizes. 69 70 For machines with different classes of registers, we must keep track 71 of the register class needed for each reload, and make sure that 72 we allocate enough reload registers of each class. 73 74 The file reload.c contains the code that checks one insn for 75 validity and reports the reloads that it needs. This file 76 is in charge of scanning the entire rtl code, accumulating the 77 reload needs, spilling, assigning reload registers to use for 78 fixing up each insn, and generating the new insns to copy values 79 into the reload registers. */ 80 81/* During reload_as_needed, element N contains a REG rtx for the hard reg 82 into which reg N has been reloaded (perhaps for a previous insn). */ 83static rtx *reg_last_reload_reg; 84 85/* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn 86 for an output reload that stores into reg N. */ 87static char *reg_has_output_reload; 88 89/* Indicates which hard regs are reload-registers for an output reload 90 in the current insn. */ 91static HARD_REG_SET reg_is_output_reload; 92 93/* Element N is the constant value to which pseudo reg N is equivalent, 94 or zero if pseudo reg N is not equivalent to a constant. 95 find_reloads looks at this in order to replace pseudo reg N 96 with the constant it stands for. */ 97rtx *reg_equiv_constant; 98 99/* Element N is a memory location to which pseudo reg N is equivalent, 100 prior to any register elimination (such as frame pointer to stack 101 pointer). Depending on whether or not it is a valid address, this value 102 is transferred to either reg_equiv_address or reg_equiv_mem. */ 103rtx *reg_equiv_memory_loc; 104 105/* Element N is the address of stack slot to which pseudo reg N is equivalent. 106 This is used when the address is not valid as a memory address 107 (because its displacement is too big for the machine.) */ 108rtx *reg_equiv_address; 109 110/* Element N is the memory slot to which pseudo reg N is equivalent, 111 or zero if pseudo reg N is not equivalent to a memory slot. */ 112rtx *reg_equiv_mem; 113 114/* Widest width in which each pseudo reg is referred to (via subreg). */ 115static unsigned int *reg_max_ref_width; 116 117/* Element N is the list of insns that initialized reg N from its equivalent 118 constant or memory slot. */ 119static rtx *reg_equiv_init; 120 121/* Vector to remember old contents of reg_renumber before spilling. */ 122static short *reg_old_renumber; 123 124/* During reload_as_needed, element N contains the last pseudo regno reloaded 125 into hard register N. If that pseudo reg occupied more than one register, 126 reg_reloaded_contents points to that pseudo for each spill register in 127 use; all of these must remain set for an inheritance to occur. */ 128static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; 129 130/* During reload_as_needed, element N contains the insn for which 131 hard register N was last used. Its contents are significant only 132 when reg_reloaded_valid is set for this register. */ 133static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; 134 135/* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */ 136static HARD_REG_SET reg_reloaded_valid; 137/* Indicate if the register was dead at the end of the reload. 138 This is only valid if reg_reloaded_contents is set and valid. */ 139static HARD_REG_SET reg_reloaded_dead; 140 141/* Indicate whether the register's current value is one that is not 142 safe to retain across a call, even for registers that are normally 143 call-saved. */ 144static HARD_REG_SET reg_reloaded_call_part_clobbered; 145 146/* Number of spill-regs so far; number of valid elements of spill_regs. */ 147static int n_spills; 148 149/* In parallel with spill_regs, contains REG rtx's for those regs. 150 Holds the last rtx used for any given reg, or 0 if it has never 151 been used for spilling yet. This rtx is reused, provided it has 152 the proper mode. */ 153static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; 154 155/* In parallel with spill_regs, contains nonzero for a spill reg 156 that was stored after the last time it was used. 157 The precise value is the insn generated to do the store. */ 158static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; 159 160/* This is the register that was stored with spill_reg_store. This is a 161 copy of reload_out / reload_out_reg when the value was stored; if 162 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */ 163static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; 164 165/* This table is the inverse mapping of spill_regs: 166 indexed by hard reg number, 167 it contains the position of that reg in spill_regs, 168 or -1 for something that is not in spill_regs. 169 170 ?!? This is no longer accurate. */ 171static short spill_reg_order[FIRST_PSEUDO_REGISTER]; 172 173/* This reg set indicates registers that can't be used as spill registers for 174 the currently processed insn. These are the hard registers which are live 175 during the insn, but not allocated to pseudos, as well as fixed 176 registers. */ 177static HARD_REG_SET bad_spill_regs; 178 179/* These are the hard registers that can't be used as spill register for any 180 insn. This includes registers used for user variables and registers that 181 we can't eliminate. A register that appears in this set also can't be used 182 to retry register allocation. */ 183static HARD_REG_SET bad_spill_regs_global; 184 185/* Describes order of use of registers for reloading 186 of spilled pseudo-registers. `n_spills' is the number of 187 elements that are actually valid; new ones are added at the end. 188 189 Both spill_regs and spill_reg_order are used on two occasions: 190 once during find_reload_regs, where they keep track of the spill registers 191 for a single insn, but also during reload_as_needed where they show all 192 the registers ever used by reload. For the latter case, the information 193 is calculated during finish_spills. */ 194static short spill_regs[FIRST_PSEUDO_REGISTER]; 195 196/* This vector of reg sets indicates, for each pseudo, which hard registers 197 may not be used for retrying global allocation because the register was 198 formerly spilled from one of them. If we allowed reallocating a pseudo to 199 a register that it was already allocated to, reload might not 200 terminate. */ 201static HARD_REG_SET *pseudo_previous_regs; 202 203/* This vector of reg sets indicates, for each pseudo, which hard 204 registers may not be used for retrying global allocation because they 205 are used as spill registers during one of the insns in which the 206 pseudo is live. */ 207static HARD_REG_SET *pseudo_forbidden_regs; 208 209/* All hard regs that have been used as spill registers for any insn are 210 marked in this set. */ 211static HARD_REG_SET used_spill_regs; 212 213/* Index of last register assigned as a spill register. We allocate in 214 a round-robin fashion. */ 215static int last_spill_reg; 216 217/* Nonzero if indirect addressing is supported on the machine; this means 218 that spilling (REG n) does not require reloading it into a register in 219 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The 220 value indicates the level of indirect addressing supported, e.g., two 221 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get 222 a hard register. */ 223static char spill_indirect_levels; 224 225/* Nonzero if indirect addressing is supported when the innermost MEM is 226 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to 227 which these are valid is the same as spill_indirect_levels, above. */ 228char indirect_symref_ok; 229 230/* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ 231char double_reg_address_ok; 232 233/* Record the stack slot for each spilled hard register. */ 234static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; 235 236/* Width allocated so far for that stack slot. */ 237static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; 238 239/* Record which pseudos needed to be spilled. */ 240static regset_head spilled_pseudos; 241 242/* Used for communication between order_regs_for_reload and count_pseudo. 243 Used to avoid counting one pseudo twice. */ 244static regset_head pseudos_counted; 245 246/* First uid used by insns created by reload in this function. 247 Used in find_equiv_reg. */ 248int reload_first_uid; 249 250/* Flag set by local-alloc or global-alloc if anything is live in 251 a call-clobbered reg across calls. */ 252int caller_save_needed; 253 254/* Set to 1 while reload_as_needed is operating. 255 Required by some machines to handle any generated moves differently. */ 256int reload_in_progress = 0; 257 258/* These arrays record the insn_code of insns that may be needed to 259 perform input and output reloads of special objects. They provide a 260 place to pass a scratch register. */ 261enum insn_code reload_in_optab[NUM_MACHINE_MODES]; 262enum insn_code reload_out_optab[NUM_MACHINE_MODES]; 263 264/* This obstack is used for allocation of rtl during register elimination. 265 The allocated storage can be freed once find_reloads has processed the 266 insn. */ 267struct obstack reload_obstack; 268 269/* Points to the beginning of the reload_obstack. All insn_chain structures 270 are allocated first. */ 271char *reload_startobj; 272 273/* The point after all insn_chain structures. Used to quickly deallocate 274 memory allocated in copy_reloads during calculate_needs_all_insns. */ 275char *reload_firstobj; 276 277/* This points before all local rtl generated by register elimination. 278 Used to quickly free all memory after processing one insn. */ 279static char *reload_insn_firstobj; 280 281/* List of insn_chain instructions, one for every insn that reload needs to 282 examine. */ 283struct insn_chain *reload_insn_chain; 284 285/* List of all insns needing reloads. */ 286static struct insn_chain *insns_need_reload; 287 288/* This structure is used to record information about register eliminations. 289 Each array entry describes one possible way of eliminating a register 290 in favor of another. If there is more than one way of eliminating a 291 particular register, the most preferred should be specified first. */ 292 293struct elim_table 294{ 295 int from; /* Register number to be eliminated. */ 296 int to; /* Register number used as replacement. */ 297 HOST_WIDE_INT initial_offset; /* Initial difference between values. */ 298 int can_eliminate; /* Nonzero if this elimination can be done. */ 299 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over 300 insns made by reload. */ 301 HOST_WIDE_INT offset; /* Current offset between the two regs. */ 302 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */ 303 int ref_outside_mem; /* "to" has been referenced outside a MEM. */ 304 rtx from_rtx; /* REG rtx for the register to be eliminated. 305 We cannot simply compare the number since 306 we might then spuriously replace a hard 307 register corresponding to a pseudo 308 assigned to the reg to be eliminated. */ 309 rtx to_rtx; /* REG rtx for the replacement. */ 310}; 311 312static struct elim_table *reg_eliminate = 0; 313 314/* This is an intermediate structure to initialize the table. It has 315 exactly the members provided by ELIMINABLE_REGS. */ 316static const struct elim_table_1 317{ 318 const int from; 319 const int to; 320} reg_eliminate_1[] = 321 322/* If a set of eliminable registers was specified, define the table from it. 323 Otherwise, default to the normal case of the frame pointer being 324 replaced by the stack pointer. */ 325 326#ifdef ELIMINABLE_REGS 327 ELIMINABLE_REGS; 328#else 329 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; 330#endif 331 332#define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1) 333 334/* Record the number of pending eliminations that have an offset not equal 335 to their initial offset. If nonzero, we use a new copy of each 336 replacement result in any insns encountered. */ 337int num_not_at_initial_offset; 338 339/* Count the number of registers that we may be able to eliminate. */ 340static int num_eliminable; 341/* And the number of registers that are equivalent to a constant that 342 can be eliminated to frame_pointer / arg_pointer + constant. */ 343static int num_eliminable_invariants; 344 345/* For each label, we record the offset of each elimination. If we reach 346 a label by more than one path and an offset differs, we cannot do the 347 elimination. This information is indexed by the difference of the 348 number of the label and the first label number. We can't offset the 349 pointer itself as this can cause problems on machines with segmented 350 memory. The first table is an array of flags that records whether we 351 have yet encountered a label and the second table is an array of arrays, 352 one entry in the latter array for each elimination. */ 353 354static int first_label_num; 355static char *offsets_known_at; 356static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS]; 357 358/* Number of labels in the current function. */ 359 360static int num_labels; 361 362static void replace_pseudos_in (rtx *, enum machine_mode, rtx); 363static void maybe_fix_stack_asms (void); 364static void copy_reloads (struct insn_chain *); 365static void calculate_needs_all_insns (int); 366static int find_reg (struct insn_chain *, int); 367static void find_reload_regs (struct insn_chain *); 368static void select_reload_regs (void); 369static void delete_caller_save_insns (void); 370 371static void spill_failure (rtx, enum reg_class); 372static void count_spilled_pseudo (int, int, int); 373static void delete_dead_insn (rtx); 374static void alter_reg (int, int); 375static void set_label_offsets (rtx, rtx, int); 376static void check_eliminable_occurrences (rtx); 377static void elimination_effects (rtx, enum machine_mode); 378static int eliminate_regs_in_insn (rtx, int); 379static void update_eliminable_offsets (void); 380static void mark_not_eliminable (rtx, rtx, void *); 381static void set_initial_elim_offsets (void); 382static void verify_initial_elim_offsets (void); 383static void set_initial_label_offsets (void); 384static void set_offsets_for_label (rtx); 385static void init_elim_table (void); 386static void update_eliminables (HARD_REG_SET *); 387static void spill_hard_reg (unsigned int, int); 388static int finish_spills (int); 389static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *); 390static void scan_paradoxical_subregs (rtx); 391static void count_pseudo (int); 392static void order_regs_for_reload (struct insn_chain *); 393static void reload_as_needed (int); 394static void forget_old_reloads_1 (rtx, rtx, void *); 395static int reload_reg_class_lower (const void *, const void *); 396static void mark_reload_reg_in_use (unsigned int, int, enum reload_type, 397 enum machine_mode); 398static void clear_reload_reg_in_use (unsigned int, int, enum reload_type, 399 enum machine_mode); 400static int reload_reg_free_p (unsigned int, int, enum reload_type); 401static int reload_reg_free_for_value_p (int, int, int, enum reload_type, 402 rtx, rtx, int, int); 403static int free_for_value_p (int, enum machine_mode, int, enum reload_type, 404 rtx, rtx, int, int); 405static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type); 406static int allocate_reload_reg (struct insn_chain *, int, int); 407static int conflicts_with_override (rtx); 408static void failed_reload (rtx, int); 409static int set_reload_reg (int, int); 410static void choose_reload_regs_init (struct insn_chain *, rtx *); 411static void choose_reload_regs (struct insn_chain *); 412static void merge_assigned_reloads (rtx); 413static void emit_input_reload_insns (struct insn_chain *, struct reload *, 414 rtx, int); 415static void emit_output_reload_insns (struct insn_chain *, struct reload *, 416 int); 417static void do_input_reload (struct insn_chain *, struct reload *, int); 418static void do_output_reload (struct insn_chain *, struct reload *, int); 419static void emit_reload_insns (struct insn_chain *); 420static void delete_output_reload (rtx, int, int); 421static void delete_address_reloads (rtx, rtx); 422static void delete_address_reloads_1 (rtx, rtx, rtx); 423static rtx inc_for_reload (rtx, rtx, rtx, int); 424#ifdef AUTO_INC_DEC 425static void add_auto_inc_notes (rtx, rtx); 426#endif 427static void copy_eh_notes (rtx, rtx); 428 429/* Initialize the reload pass once per compilation. */ 430 431void 432init_reload (void) 433{ 434 int i; 435 436 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. 437 Set spill_indirect_levels to the number of levels such addressing is 438 permitted, zero if it is not permitted at all. */ 439 440 rtx tem 441 = gen_rtx_MEM (Pmode, 442 gen_rtx_PLUS (Pmode, 443 gen_rtx_REG (Pmode, 444 LAST_VIRTUAL_REGISTER + 1), 445 GEN_INT (4))); 446 spill_indirect_levels = 0; 447 448 while (memory_address_p (QImode, tem)) 449 { 450 spill_indirect_levels++; 451 tem = gen_rtx_MEM (Pmode, tem); 452 } 453 454 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ 455 456 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); 457 indirect_symref_ok = memory_address_p (QImode, tem); 458 459 /* See if reg+reg is a valid (and offsettable) address. */ 460 461 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 462 { 463 tem = gen_rtx_PLUS (Pmode, 464 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), 465 gen_rtx_REG (Pmode, i)); 466 467 /* This way, we make sure that reg+reg is an offsettable address. */ 468 tem = plus_constant (tem, 4); 469 470 if (memory_address_p (QImode, tem)) 471 { 472 double_reg_address_ok = 1; 473 break; 474 } 475 } 476 477 /* Initialize obstack for our rtl allocation. */ 478 gcc_obstack_init (&reload_obstack); 479 reload_startobj = obstack_alloc (&reload_obstack, 0); 480 481 INIT_REG_SET (&spilled_pseudos); 482 INIT_REG_SET (&pseudos_counted); 483} 484 485/* List of insn chains that are currently unused. */ 486static struct insn_chain *unused_insn_chains = 0; 487 488/* Allocate an empty insn_chain structure. */ 489struct insn_chain * 490new_insn_chain (void) 491{ 492 struct insn_chain *c; 493 494 if (unused_insn_chains == 0) 495 { 496 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain)); 497 INIT_REG_SET (&c->live_throughout); 498 INIT_REG_SET (&c->dead_or_set); 499 } 500 else 501 { 502 c = unused_insn_chains; 503 unused_insn_chains = c->next; 504 } 505 c->is_caller_save_insn = 0; 506 c->need_operand_change = 0; 507 c->need_reload = 0; 508 c->need_elim = 0; 509 return c; 510} 511 512/* Small utility function to set all regs in hard reg set TO which are 513 allocated to pseudos in regset FROM. */ 514 515void 516compute_use_by_pseudos (HARD_REG_SET *to, regset from) 517{ 518 unsigned int regno; 519 520 EXECUTE_IF_SET_IN_REG_SET 521 (from, FIRST_PSEUDO_REGISTER, regno, 522 { 523 int r = reg_renumber[regno]; 524 int nregs; 525 526 if (r < 0) 527 { 528 /* reload_combine uses the information from 529 BASIC_BLOCK->global_live_at_start, which might still 530 contain registers that have not actually been allocated 531 since they have an equivalence. */ 532 if (! reload_completed) 533 abort (); 534 } 535 else 536 { 537 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno)); 538 while (nregs-- > 0) 539 SET_HARD_REG_BIT (*to, r + nregs); 540 } 541 }); 542} 543 544/* Replace all pseudos found in LOC with their corresponding 545 equivalences. */ 546 547static void 548replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage) 549{ 550 rtx x = *loc; 551 enum rtx_code code; 552 const char *fmt; 553 int i, j; 554 555 if (! x) 556 return; 557 558 code = GET_CODE (x); 559 if (code == REG) 560 { 561 unsigned int regno = REGNO (x); 562 563 if (regno < FIRST_PSEUDO_REGISTER) 564 return; 565 566 x = eliminate_regs (x, mem_mode, usage); 567 if (x != *loc) 568 { 569 *loc = x; 570 replace_pseudos_in (loc, mem_mode, usage); 571 return; 572 } 573 574 if (reg_equiv_constant[regno]) 575 *loc = reg_equiv_constant[regno]; 576 else if (reg_equiv_mem[regno]) 577 *loc = reg_equiv_mem[regno]; 578 else if (reg_equiv_address[regno]) 579 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]); 580 else if (GET_CODE (regno_reg_rtx[regno]) != REG 581 || REGNO (regno_reg_rtx[regno]) != regno) 582 *loc = regno_reg_rtx[regno]; 583 else 584 abort (); 585 586 return; 587 } 588 else if (code == MEM) 589 { 590 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage); 591 return; 592 } 593 594 /* Process each of our operands recursively. */ 595 fmt = GET_RTX_FORMAT (code); 596 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) 597 if (*fmt == 'e') 598 replace_pseudos_in (&XEXP (x, i), mem_mode, usage); 599 else if (*fmt == 'E') 600 for (j = 0; j < XVECLEN (x, i); j++) 601 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage); 602} 603 604 605/* Global variables used by reload and its subroutines. */ 606 607/* Set during calculate_needs if an insn needs register elimination. */ 608static int something_needs_elimination; 609/* Set during calculate_needs if an insn needs an operand changed. */ 610int something_needs_operands_changed; 611 612/* Nonzero means we couldn't get enough spill regs. */ 613static int failure; 614 615/* Main entry point for the reload pass. 616 617 FIRST is the first insn of the function being compiled. 618 619 GLOBAL nonzero means we were called from global_alloc 620 and should attempt to reallocate any pseudoregs that we 621 displace from hard regs we will use for reloads. 622 If GLOBAL is zero, we do not have enough information to do that, 623 so any pseudo reg that is spilled must go to the stack. 624 625 Return value is nonzero if reload failed 626 and we must not do any more for this function. */ 627 628int 629reload (rtx first, int global) 630{ 631 int i; 632 rtx insn; 633 struct elim_table *ep; 634 basic_block bb; 635 636 /* Make sure even insns with volatile mem refs are recognizable. */ 637 init_recog (); 638 639 failure = 0; 640 641 reload_firstobj = obstack_alloc (&reload_obstack, 0); 642 643 /* Make sure that the last insn in the chain 644 is not something that needs reloading. */ 645 emit_note (NOTE_INSN_DELETED); 646 647 /* Enable find_equiv_reg to distinguish insns made by reload. */ 648 reload_first_uid = get_max_uid (); 649 650#ifdef SECONDARY_MEMORY_NEEDED 651 /* Initialize the secondary memory table. */ 652 clear_secondary_mem (); 653#endif 654 655 /* We don't have a stack slot for any spill reg yet. */ 656 memset (spill_stack_slot, 0, sizeof spill_stack_slot); 657 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width); 658 659 /* Initialize the save area information for caller-save, in case some 660 are needed. */ 661 init_save_areas (); 662 663 /* Compute which hard registers are now in use 664 as homes for pseudo registers. 665 This is done here rather than (eg) in global_alloc 666 because this point is reached even if not optimizing. */ 667 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 668 mark_home_live (i); 669 670 /* A function that receives a nonlocal goto must save all call-saved 671 registers. */ 672 if (current_function_has_nonlocal_label) 673 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 674 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) 675 regs_ever_live[i] = 1; 676 677#ifdef NON_SAVING_SETJMP 678 /* A function that calls setjmp should save and restore all the 679 call-saved registers on a system where longjmp clobbers them. */ 680 if (NON_SAVING_SETJMP && current_function_calls_setjmp) 681 { 682 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 683 if (! call_used_regs[i]) 684 regs_ever_live[i] = 1; 685 } 686#endif 687 688 /* Find all the pseudo registers that didn't get hard regs 689 but do have known equivalent constants or memory slots. 690 These include parameters (known equivalent to parameter slots) 691 and cse'd or loop-moved constant memory addresses. 692 693 Record constant equivalents in reg_equiv_constant 694 so they will be substituted by find_reloads. 695 Record memory equivalents in reg_mem_equiv so they can 696 be substituted eventually by altering the REG-rtx's. */ 697 698 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx)); 699 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx)); 700 reg_equiv_init = xcalloc (max_regno, sizeof (rtx)); 701 reg_equiv_address = xcalloc (max_regno, sizeof (rtx)); 702 reg_max_ref_width = xcalloc (max_regno, sizeof (int)); 703 reg_old_renumber = xcalloc (max_regno, sizeof (short)); 704 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); 705 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET)); 706 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET)); 707 708 CLEAR_HARD_REG_SET (bad_spill_regs_global); 709 710 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to. 711 Also find all paradoxical subregs and find largest such for each pseudo. 712 On machines with small register classes, record hard registers that 713 are used for user variables. These can never be used for spills. */ 714 715 num_eliminable_invariants = 0; 716 for (insn = first; insn; insn = NEXT_INSN (insn)) 717 { 718 rtx set = single_set (insn); 719 720 /* We may introduce USEs that we want to remove at the end, so 721 we'll mark them with QImode. Make sure there are no 722 previously-marked insns left by say regmove. */ 723 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE 724 && GET_MODE (insn) != VOIDmode) 725 PUT_MODE (insn, VOIDmode); 726 727 if (set != 0 && GET_CODE (SET_DEST (set)) == REG) 728 { 729 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); 730 if (note 731#ifdef LEGITIMATE_PIC_OPERAND_P 732 && (! function_invariant_p (XEXP (note, 0)) 733 || ! flag_pic 734 /* A function invariant is often CONSTANT_P but may 735 include a register. We promise to only pass 736 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ 737 || (CONSTANT_P (XEXP (note, 0)) 738 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))) 739#endif 740 ) 741 { 742 rtx x = XEXP (note, 0); 743 i = REGNO (SET_DEST (set)); 744 if (i > LAST_VIRTUAL_REGISTER) 745 { 746 /* It can happen that a REG_EQUIV note contains a MEM 747 that is not a legitimate memory operand. As later 748 stages of reload assume that all addresses found 749 in the reg_equiv_* arrays were originally legitimate, 750 we ignore such REG_EQUIV notes. 751 752 It also can happen that a REG_EQUIV note contains a MEM 753 that carries the /u flag, for example when GCSE turns 754 the load of a constant into a move from a pseudo that 755 already contains the constant and attaches a REG_EQUAL 756 note to the insn, which is later promoted to REQ_EQUIV 757 by local-alloc. If the destination pseudo happens not 758 to be assigned to a hard reg, it will be replaced by 759 the MEM as the destination of the move, thus generating 760 a store to a possibly read-only memory location. */ 761 if (memory_operand (x, VOIDmode) && ! RTX_UNCHANGING_P (x)) 762 { 763 /* Always unshare the equivalence, so we can 764 substitute into this insn without touching the 765 equivalence. */ 766 reg_equiv_memory_loc[i] = copy_rtx (x); 767 } 768 else if (function_invariant_p (x)) 769 { 770 if (GET_CODE (x) == PLUS) 771 { 772 /* This is PLUS of frame pointer and a constant, 773 and might be shared. Unshare it. */ 774 reg_equiv_constant[i] = copy_rtx (x); 775 num_eliminable_invariants++; 776 } 777 else if (x == frame_pointer_rtx 778 || x == arg_pointer_rtx) 779 { 780 reg_equiv_constant[i] = x; 781 num_eliminable_invariants++; 782 } 783 else if (LEGITIMATE_CONSTANT_P (x)) 784 reg_equiv_constant[i] = x; 785 else 786 { 787 reg_equiv_memory_loc[i] 788 = force_const_mem (GET_MODE (SET_DEST (set)), x); 789 if (!reg_equiv_memory_loc[i]) 790 continue; 791 } 792 } 793 else 794 continue; 795 796 /* If this register is being made equivalent to a MEM 797 and the MEM is not SET_SRC, the equivalencing insn 798 is one with the MEM as a SET_DEST and it occurs later. 799 So don't mark this insn now. */ 800 if (GET_CODE (x) != MEM 801 || rtx_equal_p (SET_SRC (set), x)) 802 reg_equiv_init[i] 803 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]); 804 } 805 } 806 } 807 808 /* If this insn is setting a MEM from a register equivalent to it, 809 this is the equivalencing insn. */ 810 else if (set && GET_CODE (SET_DEST (set)) == MEM 811 && GET_CODE (SET_SRC (set)) == REG 812 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] 813 && rtx_equal_p (SET_DEST (set), 814 reg_equiv_memory_loc[REGNO (SET_SRC (set))])) 815 reg_equiv_init[REGNO (SET_SRC (set))] 816 = gen_rtx_INSN_LIST (VOIDmode, insn, 817 reg_equiv_init[REGNO (SET_SRC (set))]); 818 819 if (INSN_P (insn)) 820 scan_paradoxical_subregs (PATTERN (insn)); 821 } 822 823 init_elim_table (); 824 825 first_label_num = get_first_label_num (); 826 num_labels = max_label_num () - first_label_num; 827 828 /* Allocate the tables used to store offset information at labels. */ 829 /* We used to use alloca here, but the size of what it would try to 830 allocate would occasionally cause it to exceed the stack limit and 831 cause a core dump. */ 832 offsets_known_at = xmalloc (num_labels); 833 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT)); 834 835 /* Alter each pseudo-reg rtx to contain its hard reg number. 836 Assign stack slots to the pseudos that lack hard regs or equivalents. 837 Do not touch virtual registers. */ 838 839 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) 840 alter_reg (i, -1); 841 842 /* If we have some registers we think can be eliminated, scan all insns to 843 see if there is an insn that sets one of these registers to something 844 other than itself plus a constant. If so, the register cannot be 845 eliminated. Doing this scan here eliminates an extra pass through the 846 main reload loop in the most common case where register elimination 847 cannot be done. */ 848 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) 849 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN 850 || GET_CODE (insn) == CALL_INSN) 851 note_stores (PATTERN (insn), mark_not_eliminable, NULL); 852 853 maybe_fix_stack_asms (); 854 855 insns_need_reload = 0; 856 something_needs_elimination = 0; 857 858 /* Initialize to -1, which means take the first spill register. */ 859 last_spill_reg = -1; 860 861 /* Spill any hard regs that we know we can't eliminate. */ 862 CLEAR_HARD_REG_SET (used_spill_regs); 863 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 864 if (! ep->can_eliminate) 865 spill_hard_reg (ep->from, 1); 866 867#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 868 if (frame_pointer_needed) 869 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1); 870#endif 871 finish_spills (global); 872 873 /* From now on, we may need to generate moves differently. We may also 874 allow modifications of insns which cause them to not be recognized. 875 Any such modifications will be cleaned up during reload itself. */ 876 reload_in_progress = 1; 877 878 /* This loop scans the entire function each go-round 879 and repeats until one repetition spills no additional hard regs. */ 880 for (;;) 881 { 882 int something_changed; 883 int did_spill; 884 885 HOST_WIDE_INT starting_frame_size; 886 887 /* Round size of stack frame to stack_alignment_needed. This must be done 888 here because the stack size may be a part of the offset computation 889 for register elimination, and there might have been new stack slots 890 created in the last iteration of this loop. */ 891 if (cfun->stack_alignment_needed) 892 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed); 893 894 starting_frame_size = get_frame_size (); 895 896 set_initial_elim_offsets (); 897 set_initial_label_offsets (); 898 899 /* For each pseudo register that has an equivalent location defined, 900 try to eliminate any eliminable registers (such as the frame pointer) 901 assuming initial offsets for the replacement register, which 902 is the normal case. 903 904 If the resulting location is directly addressable, substitute 905 the MEM we just got directly for the old REG. 906 907 If it is not addressable but is a constant or the sum of a hard reg 908 and constant, it is probably not addressable because the constant is 909 out of range, in that case record the address; we will generate 910 hairy code to compute the address in a register each time it is 911 needed. Similarly if it is a hard register, but one that is not 912 valid as an address register. 913 914 If the location is not addressable, but does not have one of the 915 above forms, assign a stack slot. We have to do this to avoid the 916 potential of producing lots of reloads if, e.g., a location involves 917 a pseudo that didn't get a hard register and has an equivalent memory 918 location that also involves a pseudo that didn't get a hard register. 919 920 Perhaps at some point we will improve reload_when_needed handling 921 so this problem goes away. But that's very hairy. */ 922 923 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 924 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) 925 { 926 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); 927 928 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), 929 XEXP (x, 0))) 930 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; 931 else if (CONSTANT_P (XEXP (x, 0)) 932 || (GET_CODE (XEXP (x, 0)) == REG 933 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) 934 || (GET_CODE (XEXP (x, 0)) == PLUS 935 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG 936 && (REGNO (XEXP (XEXP (x, 0), 0)) 937 < FIRST_PSEUDO_REGISTER) 938 && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) 939 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; 940 else 941 { 942 /* Make a new stack slot. Then indicate that something 943 changed so we go back and recompute offsets for 944 eliminable registers because the allocation of memory 945 below might change some offset. reg_equiv_{mem,address} 946 will be set up for this pseudo on the next pass around 947 the loop. */ 948 reg_equiv_memory_loc[i] = 0; 949 reg_equiv_init[i] = 0; 950 alter_reg (i, -1); 951 } 952 } 953 954 if (caller_save_needed) 955 setup_save_areas (); 956 957 /* If we allocated another stack slot, redo elimination bookkeeping. */ 958 if (starting_frame_size != get_frame_size ()) 959 continue; 960 961 if (caller_save_needed) 962 { 963 save_call_clobbered_regs (); 964 /* That might have allocated new insn_chain structures. */ 965 reload_firstobj = obstack_alloc (&reload_obstack, 0); 966 } 967 968 calculate_needs_all_insns (global); 969 970 CLEAR_REG_SET (&spilled_pseudos); 971 did_spill = 0; 972 973 something_changed = 0; 974 975 /* If we allocated any new memory locations, make another pass 976 since it might have changed elimination offsets. */ 977 if (starting_frame_size != get_frame_size ()) 978 something_changed = 1; 979 980 { 981 HARD_REG_SET to_spill; 982 CLEAR_HARD_REG_SET (to_spill); 983 update_eliminables (&to_spill); 984 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 985 if (TEST_HARD_REG_BIT (to_spill, i)) 986 { 987 spill_hard_reg (i, 1); 988 did_spill = 1; 989 990 /* Regardless of the state of spills, if we previously had 991 a register that we thought we could eliminate, but now can 992 not eliminate, we must run another pass. 993 994 Consider pseudos which have an entry in reg_equiv_* which 995 reference an eliminable register. We must make another pass 996 to update reg_equiv_* so that we do not substitute in the 997 old value from when we thought the elimination could be 998 performed. */ 999 something_changed = 1; 1000 } 1001 } 1002 1003 select_reload_regs (); 1004 if (failure) 1005 goto failed; 1006 1007 if (insns_need_reload != 0 || did_spill) 1008 something_changed |= finish_spills (global); 1009 1010 if (! something_changed) 1011 break; 1012 1013 if (caller_save_needed) 1014 delete_caller_save_insns (); 1015 1016 obstack_free (&reload_obstack, reload_firstobj); 1017 } 1018 1019 /* If global-alloc was run, notify it of any register eliminations we have 1020 done. */ 1021 if (global) 1022 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 1023 if (ep->can_eliminate) 1024 mark_elimination (ep->from, ep->to); 1025 1026 /* If a pseudo has no hard reg, delete the insns that made the equivalence. 1027 If that insn didn't set the register (i.e., it copied the register to 1028 memory), just delete that insn instead of the equivalencing insn plus 1029 anything now dead. If we call delete_dead_insn on that insn, we may 1030 delete the insn that actually sets the register if the register dies 1031 there and that is incorrect. */ 1032 1033 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 1034 { 1035 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0) 1036 { 1037 rtx list; 1038 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1)) 1039 { 1040 rtx equiv_insn = XEXP (list, 0); 1041 1042 /* If we already deleted the insn or if it may trap, we can't 1043 delete it. The latter case shouldn't happen, but can 1044 if an insn has a variable address, gets a REG_EH_REGION 1045 note added to it, and then gets converted into an load 1046 from a constant address. */ 1047 if (GET_CODE (equiv_insn) == NOTE 1048 || can_throw_internal (equiv_insn)) 1049 ; 1050 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn))) 1051 delete_dead_insn (equiv_insn); 1052 else 1053 { 1054 PUT_CODE (equiv_insn, NOTE); 1055 NOTE_SOURCE_FILE (equiv_insn) = 0; 1056 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; 1057 } 1058 } 1059 } 1060 } 1061 1062 /* Use the reload registers where necessary 1063 by generating move instructions to move the must-be-register 1064 values into or out of the reload registers. */ 1065 1066 if (insns_need_reload != 0 || something_needs_elimination 1067 || something_needs_operands_changed) 1068 { 1069 HOST_WIDE_INT old_frame_size = get_frame_size (); 1070 1071 reload_as_needed (global); 1072 1073 if (old_frame_size != get_frame_size ()) 1074 abort (); 1075 1076 if (num_eliminable) 1077 verify_initial_elim_offsets (); 1078 } 1079 1080 /* If we were able to eliminate the frame pointer, show that it is no 1081 longer live at the start of any basic block. If it ls live by 1082 virtue of being in a pseudo, that pseudo will be marked live 1083 and hence the frame pointer will be known to be live via that 1084 pseudo. */ 1085 1086 if (! frame_pointer_needed) 1087 FOR_EACH_BB (bb) 1088 CLEAR_REGNO_REG_SET (bb->global_live_at_start, 1089 HARD_FRAME_POINTER_REGNUM); 1090 1091 /* Come here (with failure set nonzero) if we can't get enough spill regs 1092 and we decide not to abort about it. */ 1093 failed: 1094 1095 CLEAR_REG_SET (&spilled_pseudos); 1096 reload_in_progress = 0; 1097 1098 /* Now eliminate all pseudo regs by modifying them into 1099 their equivalent memory references. 1100 The REG-rtx's for the pseudos are modified in place, 1101 so all insns that used to refer to them now refer to memory. 1102 1103 For a reg that has a reg_equiv_address, all those insns 1104 were changed by reloading so that no insns refer to it any longer; 1105 but the DECL_RTL of a variable decl may refer to it, 1106 and if so this causes the debugging info to mention the variable. */ 1107 1108 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 1109 { 1110 rtx addr = 0; 1111 1112 if (reg_equiv_mem[i]) 1113 addr = XEXP (reg_equiv_mem[i], 0); 1114 1115 if (reg_equiv_address[i]) 1116 addr = reg_equiv_address[i]; 1117 1118 if (addr) 1119 { 1120 if (reg_renumber[i] < 0) 1121 { 1122 rtx reg = regno_reg_rtx[i]; 1123 1124 REG_USERVAR_P (reg) = 0; 1125 PUT_CODE (reg, MEM); 1126 XEXP (reg, 0) = addr; 1127 if (reg_equiv_memory_loc[i]) 1128 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]); 1129 else 1130 { 1131 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg) 1132 = MEM_SCALAR_P (reg) = 0; 1133 MEM_ATTRS (reg) = 0; 1134 } 1135 } 1136 else if (reg_equiv_mem[i]) 1137 XEXP (reg_equiv_mem[i], 0) = addr; 1138 } 1139 } 1140 1141 /* We must set reload_completed now since the cleanup_subreg_operands call 1142 below will re-recognize each insn and reload may have generated insns 1143 which are only valid during and after reload. */ 1144 reload_completed = 1; 1145 1146 /* Make a pass over all the insns and delete all USEs which we inserted 1147 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED 1148 notes. Delete all CLOBBER insns, except those that refer to the return 1149 value and the special mem:BLK CLOBBERs added to prevent the scheduler 1150 from misarranging variable-array code, and simplify (subreg (reg)) 1151 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they 1152 are no longer useful or accurate. Strip and regenerate REG_INC notes 1153 that may have been moved around. */ 1154 1155 for (insn = first; insn; insn = NEXT_INSN (insn)) 1156 if (INSN_P (insn)) 1157 { 1158 rtx *pnote; 1159 1160 if (GET_CODE (insn) == CALL_INSN) 1161 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn), 1162 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn)); 1163 1164 if ((GET_CODE (PATTERN (insn)) == USE 1165 /* We mark with QImode USEs introduced by reload itself. */ 1166 && (GET_MODE (insn) == QImode 1167 || find_reg_note (insn, REG_EQUAL, NULL_RTX))) 1168 || (GET_CODE (PATTERN (insn)) == CLOBBER 1169 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM 1170 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode 1171 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH 1172 && XEXP (XEXP (PATTERN (insn), 0), 0) 1173 != stack_pointer_rtx)) 1174 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG 1175 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))))) 1176 { 1177 delete_insn (insn); 1178 continue; 1179 } 1180 1181 /* Some CLOBBERs may survive until here and still reference unassigned 1182 pseudos with const equivalent, which may in turn cause ICE in later 1183 passes if the reference remains in place. */ 1184 if (GET_CODE (PATTERN (insn)) == CLOBBER) 1185 replace_pseudos_in (& XEXP (PATTERN (insn), 0), 1186 VOIDmode, PATTERN (insn)); 1187 1188 pnote = ®_NOTES (insn); 1189 while (*pnote != 0) 1190 { 1191 if (REG_NOTE_KIND (*pnote) == REG_DEAD 1192 || REG_NOTE_KIND (*pnote) == REG_UNUSED 1193 || REG_NOTE_KIND (*pnote) == REG_INC 1194 || REG_NOTE_KIND (*pnote) == REG_RETVAL 1195 || REG_NOTE_KIND (*pnote) == REG_LIBCALL) 1196 *pnote = XEXP (*pnote, 1); 1197 else 1198 pnote = &XEXP (*pnote, 1); 1199 } 1200 1201#ifdef AUTO_INC_DEC 1202 add_auto_inc_notes (insn, PATTERN (insn)); 1203#endif 1204 1205 /* And simplify (subreg (reg)) if it appears as an operand. */ 1206 cleanup_subreg_operands (insn); 1207 } 1208 1209 /* If we are doing stack checking, give a warning if this function's 1210 frame size is larger than we expect. */ 1211 if (flag_stack_check && ! STACK_CHECK_BUILTIN) 1212 { 1213 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; 1214 static int verbose_warned = 0; 1215 1216 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1217 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i]) 1218 size += UNITS_PER_WORD; 1219 1220 if (size > STACK_CHECK_MAX_FRAME_SIZE) 1221 { 1222 warning ("frame size too large for reliable stack checking"); 1223 if (! verbose_warned) 1224 { 1225 warning ("try reducing the number of local variables"); 1226 verbose_warned = 1; 1227 } 1228 } 1229 } 1230 1231 /* Indicate that we no longer have known memory locations or constants. */ 1232 if (reg_equiv_constant) 1233 free (reg_equiv_constant); 1234 reg_equiv_constant = 0; 1235 if (reg_equiv_memory_loc) 1236 free (reg_equiv_memory_loc); 1237 reg_equiv_memory_loc = 0; 1238 1239 if (offsets_known_at) 1240 free (offsets_known_at); 1241 if (offsets_at) 1242 free (offsets_at); 1243 1244 free (reg_equiv_mem); 1245 free (reg_equiv_init); 1246 free (reg_equiv_address); 1247 free (reg_max_ref_width); 1248 free (reg_old_renumber); 1249 free (pseudo_previous_regs); 1250 free (pseudo_forbidden_regs); 1251 1252 CLEAR_HARD_REG_SET (used_spill_regs); 1253 for (i = 0; i < n_spills; i++) 1254 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); 1255 1256 /* Free all the insn_chain structures at once. */ 1257 obstack_free (&reload_obstack, reload_startobj); 1258 unused_insn_chains = 0; 1259 fixup_abnormal_edges (); 1260 1261 /* Replacing pseudos with their memory equivalents might have 1262 created shared rtx. Subsequent passes would get confused 1263 by this, so unshare everything here. */ 1264 unshare_all_rtl_again (first); 1265 1266#ifdef STACK_BOUNDARY 1267 /* init_emit has set the alignment of the hard frame pointer 1268 to STACK_BOUNDARY. It is very likely no longer valid if 1269 the hard frame pointer was used for register allocation. */ 1270 if (!frame_pointer_needed) 1271 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; 1272#endif 1273 1274 return failure; 1275} 1276 1277/* Yet another special case. Unfortunately, reg-stack forces people to 1278 write incorrect clobbers in asm statements. These clobbers must not 1279 cause the register to appear in bad_spill_regs, otherwise we'll call 1280 fatal_insn later. We clear the corresponding regnos in the live 1281 register sets to avoid this. 1282 The whole thing is rather sick, I'm afraid. */ 1283 1284static void 1285maybe_fix_stack_asms (void) 1286{ 1287#ifdef STACK_REGS 1288 const char *constraints[MAX_RECOG_OPERANDS]; 1289 enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; 1290 struct insn_chain *chain; 1291 1292 for (chain = reload_insn_chain; chain != 0; chain = chain->next) 1293 { 1294 int i, noperands; 1295 HARD_REG_SET clobbered, allowed; 1296 rtx pat; 1297 1298 if (! INSN_P (chain->insn) 1299 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0) 1300 continue; 1301 pat = PATTERN (chain->insn); 1302 if (GET_CODE (pat) != PARALLEL) 1303 continue; 1304 1305 CLEAR_HARD_REG_SET (clobbered); 1306 CLEAR_HARD_REG_SET (allowed); 1307 1308 /* First, make a mask of all stack regs that are clobbered. */ 1309 for (i = 0; i < XVECLEN (pat, 0); i++) 1310 { 1311 rtx t = XVECEXP (pat, 0, i); 1312 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) 1313 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); 1314 } 1315 1316 /* Get the operand values and constraints out of the insn. */ 1317 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc, 1318 constraints, operand_mode); 1319 1320 /* For every operand, see what registers are allowed. */ 1321 for (i = 0; i < noperands; i++) 1322 { 1323 const char *p = constraints[i]; 1324 /* For every alternative, we compute the class of registers allowed 1325 for reloading in CLS, and merge its contents into the reg set 1326 ALLOWED. */ 1327 int cls = (int) NO_REGS; 1328 1329 for (;;) 1330 { 1331 char c = *p; 1332 1333 if (c == '\0' || c == ',' || c == '#') 1334 { 1335 /* End of one alternative - mark the regs in the current 1336 class, and reset the class. */ 1337 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]); 1338 cls = NO_REGS; 1339 p++; 1340 if (c == '#') 1341 do { 1342 c = *p++; 1343 } while (c != '\0' && c != ','); 1344 if (c == '\0') 1345 break; 1346 continue; 1347 } 1348 1349 switch (c) 1350 { 1351 case '=': case '+': case '*': case '%': case '?': case '!': 1352 case '0': case '1': case '2': case '3': case '4': case 'm': 1353 case '<': case '>': case 'V': case 'o': case '&': case 'E': 1354 case 'F': case 's': case 'i': case 'n': case 'X': case 'I': 1355 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O': 1356 case 'P': 1357 break; 1358 1359 case 'p': 1360 cls = (int) reg_class_subunion[cls] 1361 [(int) MODE_BASE_REG_CLASS (VOIDmode)]; 1362 break; 1363 1364 case 'g': 1365 case 'r': 1366 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS]; 1367 break; 1368 1369 default: 1370 if (EXTRA_ADDRESS_CONSTRAINT (c, p)) 1371 cls = (int) reg_class_subunion[cls] 1372 [(int) MODE_BASE_REG_CLASS (VOIDmode)]; 1373 else 1374 cls = (int) reg_class_subunion[cls] 1375 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]; 1376 } 1377 p += CONSTRAINT_LEN (c, p); 1378 } 1379 } 1380 /* Those of the registers which are clobbered, but allowed by the 1381 constraints, must be usable as reload registers. So clear them 1382 out of the life information. */ 1383 AND_HARD_REG_SET (allowed, clobbered); 1384 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1385 if (TEST_HARD_REG_BIT (allowed, i)) 1386 { 1387 CLEAR_REGNO_REG_SET (&chain->live_throughout, i); 1388 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i); 1389 } 1390 } 1391 1392#endif 1393} 1394 1395/* Copy the global variables n_reloads and rld into the corresponding elts 1396 of CHAIN. */ 1397static void 1398copy_reloads (struct insn_chain *chain) 1399{ 1400 chain->n_reloads = n_reloads; 1401 chain->rld = obstack_alloc (&reload_obstack, 1402 n_reloads * sizeof (struct reload)); 1403 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); 1404 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0); 1405} 1406 1407/* Walk the chain of insns, and determine for each whether it needs reloads 1408 and/or eliminations. Build the corresponding insns_need_reload list, and 1409 set something_needs_elimination as appropriate. */ 1410static void 1411calculate_needs_all_insns (int global) 1412{ 1413 struct insn_chain **pprev_reload = &insns_need_reload; 1414 struct insn_chain *chain, *next = 0; 1415 1416 something_needs_elimination = 0; 1417 1418 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0); 1419 for (chain = reload_insn_chain; chain != 0; chain = next) 1420 { 1421 rtx insn = chain->insn; 1422 1423 next = chain->next; 1424 1425 /* Clear out the shortcuts. */ 1426 chain->n_reloads = 0; 1427 chain->need_elim = 0; 1428 chain->need_reload = 0; 1429 chain->need_operand_change = 0; 1430 1431 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might 1432 include REG_LABEL), we need to see what effects this has on the 1433 known offsets at labels. */ 1434 1435 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN 1436 || (INSN_P (insn) && REG_NOTES (insn) != 0)) 1437 set_label_offsets (insn, insn, 0); 1438 1439 if (INSN_P (insn)) 1440 { 1441 rtx old_body = PATTERN (insn); 1442 int old_code = INSN_CODE (insn); 1443 rtx old_notes = REG_NOTES (insn); 1444 int did_elimination = 0; 1445 int operands_changed = 0; 1446 rtx set = single_set (insn); 1447 1448 /* Skip insns that only set an equivalence. */ 1449 if (set && GET_CODE (SET_DEST (set)) == REG 1450 && reg_renumber[REGNO (SET_DEST (set))] < 0 1451 && reg_equiv_constant[REGNO (SET_DEST (set))]) 1452 continue; 1453 1454 /* If needed, eliminate any eliminable registers. */ 1455 if (num_eliminable || num_eliminable_invariants) 1456 did_elimination = eliminate_regs_in_insn (insn, 0); 1457 1458 /* Analyze the instruction. */ 1459 operands_changed = find_reloads (insn, 0, spill_indirect_levels, 1460 global, spill_reg_order); 1461 1462 /* If a no-op set needs more than one reload, this is likely 1463 to be something that needs input address reloads. We 1464 can't get rid of this cleanly later, and it is of no use 1465 anyway, so discard it now. 1466 We only do this when expensive_optimizations is enabled, 1467 since this complements reload inheritance / output 1468 reload deletion, and it can make debugging harder. */ 1469 if (flag_expensive_optimizations && n_reloads > 1) 1470 { 1471 rtx set = single_set (insn); 1472 if (set 1473 && SET_SRC (set) == SET_DEST (set) 1474 && GET_CODE (SET_SRC (set)) == REG 1475 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) 1476 { 1477 delete_insn (insn); 1478 /* Delete it from the reload chain. */ 1479 if (chain->prev) 1480 chain->prev->next = next; 1481 else 1482 reload_insn_chain = next; 1483 if (next) 1484 next->prev = chain->prev; 1485 chain->next = unused_insn_chains; 1486 unused_insn_chains = chain; 1487 continue; 1488 } 1489 } 1490 if (num_eliminable) 1491 update_eliminable_offsets (); 1492 1493 /* Remember for later shortcuts which insns had any reloads or 1494 register eliminations. */ 1495 chain->need_elim = did_elimination; 1496 chain->need_reload = n_reloads > 0; 1497 chain->need_operand_change = operands_changed; 1498 1499 /* Discard any register replacements done. */ 1500 if (did_elimination) 1501 { 1502 obstack_free (&reload_obstack, reload_insn_firstobj); 1503 PATTERN (insn) = old_body; 1504 INSN_CODE (insn) = old_code; 1505 REG_NOTES (insn) = old_notes; 1506 something_needs_elimination = 1; 1507 } 1508 1509 something_needs_operands_changed |= operands_changed; 1510 1511 if (n_reloads != 0) 1512 { 1513 copy_reloads (chain); 1514 *pprev_reload = chain; 1515 pprev_reload = &chain->next_need_reload; 1516 } 1517 } 1518 } 1519 *pprev_reload = 0; 1520} 1521 1522/* Comparison function for qsort to decide which of two reloads 1523 should be handled first. *P1 and *P2 are the reload numbers. */ 1524 1525static int 1526reload_reg_class_lower (const void *r1p, const void *r2p) 1527{ 1528 int r1 = *(const short *) r1p, r2 = *(const short *) r2p; 1529 int t; 1530 1531 /* Consider required reloads before optional ones. */ 1532 t = rld[r1].optional - rld[r2].optional; 1533 if (t != 0) 1534 return t; 1535 1536 /* Count all solitary classes before non-solitary ones. */ 1537 t = ((reg_class_size[(int) rld[r2].class] == 1) 1538 - (reg_class_size[(int) rld[r1].class] == 1)); 1539 if (t != 0) 1540 return t; 1541 1542 /* Aside from solitaires, consider all multi-reg groups first. */ 1543 t = rld[r2].nregs - rld[r1].nregs; 1544 if (t != 0) 1545 return t; 1546 1547 /* Consider reloads in order of increasing reg-class number. */ 1548 t = (int) rld[r1].class - (int) rld[r2].class; 1549 if (t != 0) 1550 return t; 1551 1552 /* If reloads are equally urgent, sort by reload number, 1553 so that the results of qsort leave nothing to chance. */ 1554 return r1 - r2; 1555} 1556 1557/* The cost of spilling each hard reg. */ 1558static int spill_cost[FIRST_PSEUDO_REGISTER]; 1559 1560/* When spilling multiple hard registers, we use SPILL_COST for the first 1561 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST 1562 only the first hard reg for a multi-reg pseudo. */ 1563static int spill_add_cost[FIRST_PSEUDO_REGISTER]; 1564 1565/* Update the spill cost arrays, considering that pseudo REG is live. */ 1566 1567static void 1568count_pseudo (int reg) 1569{ 1570 int freq = REG_FREQ (reg); 1571 int r = reg_renumber[reg]; 1572 int nregs; 1573 1574 if (REGNO_REG_SET_P (&pseudos_counted, reg) 1575 || REGNO_REG_SET_P (&spilled_pseudos, reg)) 1576 return; 1577 1578 SET_REGNO_REG_SET (&pseudos_counted, reg); 1579 1580 if (r < 0) 1581 abort (); 1582 1583 spill_add_cost[r] += freq; 1584 1585 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); 1586 while (nregs-- > 0) 1587 spill_cost[r + nregs] += freq; 1588} 1589 1590/* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the 1591 contents of BAD_SPILL_REGS for the insn described by CHAIN. */ 1592 1593static void 1594order_regs_for_reload (struct insn_chain *chain) 1595{ 1596 int i; 1597 HARD_REG_SET used_by_pseudos; 1598 HARD_REG_SET used_by_pseudos2; 1599 1600 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set); 1601 1602 memset (spill_cost, 0, sizeof spill_cost); 1603 memset (spill_add_cost, 0, sizeof spill_add_cost); 1604 1605 /* Count number of uses of each hard reg by pseudo regs allocated to it 1606 and then order them by decreasing use. First exclude hard registers 1607 that are live in or across this insn. */ 1608 1609 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); 1610 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); 1611 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos); 1612 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2); 1613 1614 /* Now find out which pseudos are allocated to it, and update 1615 hard_reg_n_uses. */ 1616 CLEAR_REG_SET (&pseudos_counted); 1617 1618 EXECUTE_IF_SET_IN_REG_SET 1619 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, 1620 { 1621 count_pseudo (i); 1622 }); 1623 EXECUTE_IF_SET_IN_REG_SET 1624 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, 1625 { 1626 count_pseudo (i); 1627 }); 1628 CLEAR_REG_SET (&pseudos_counted); 1629} 1630 1631/* Vector of reload-numbers showing the order in which the reloads should 1632 be processed. */ 1633static short reload_order[MAX_RELOADS]; 1634 1635/* This is used to keep track of the spill regs used in one insn. */ 1636static HARD_REG_SET used_spill_regs_local; 1637 1638/* We decided to spill hard register SPILLED, which has a size of 1639 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn, 1640 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will 1641 update SPILL_COST/SPILL_ADD_COST. */ 1642 1643static void 1644count_spilled_pseudo (int spilled, int spilled_nregs, int reg) 1645{ 1646 int r = reg_renumber[reg]; 1647 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); 1648 1649 if (REGNO_REG_SET_P (&spilled_pseudos, reg) 1650 || spilled + spilled_nregs <= r || r + nregs <= spilled) 1651 return; 1652 1653 SET_REGNO_REG_SET (&spilled_pseudos, reg); 1654 1655 spill_add_cost[r] -= REG_FREQ (reg); 1656 while (nregs-- > 0) 1657 spill_cost[r + nregs] -= REG_FREQ (reg); 1658} 1659 1660/* Find reload register to use for reload number ORDER. */ 1661 1662static int 1663find_reg (struct insn_chain *chain, int order) 1664{ 1665 int rnum = reload_order[order]; 1666 struct reload *rl = rld + rnum; 1667 int best_cost = INT_MAX; 1668 int best_reg = -1; 1669 unsigned int i, j; 1670 int k; 1671 HARD_REG_SET not_usable; 1672 HARD_REG_SET used_by_other_reload; 1673 1674 COPY_HARD_REG_SET (not_usable, bad_spill_regs); 1675 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global); 1676 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]); 1677 1678 CLEAR_HARD_REG_SET (used_by_other_reload); 1679 for (k = 0; k < order; k++) 1680 { 1681 int other = reload_order[k]; 1682 1683 if (rld[other].regno >= 0 && reloads_conflict (other, rnum)) 1684 for (j = 0; j < rld[other].nregs; j++) 1685 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j); 1686 } 1687 1688 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1689 { 1690 unsigned int regno = i; 1691 1692 if (! TEST_HARD_REG_BIT (not_usable, regno) 1693 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno) 1694 && HARD_REGNO_MODE_OK (regno, rl->mode)) 1695 { 1696 int this_cost = spill_cost[regno]; 1697 int ok = 1; 1698 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode); 1699 1700 for (j = 1; j < this_nregs; j++) 1701 { 1702 this_cost += spill_add_cost[regno + j]; 1703 if ((TEST_HARD_REG_BIT (not_usable, regno + j)) 1704 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j)) 1705 ok = 0; 1706 } 1707 if (! ok) 1708 continue; 1709 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno) 1710 this_cost--; 1711 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno) 1712 this_cost--; 1713 if (this_cost < best_cost 1714 /* Among registers with equal cost, prefer caller-saved ones, or 1715 use REG_ALLOC_ORDER if it is defined. */ 1716 || (this_cost == best_cost 1717#ifdef REG_ALLOC_ORDER 1718 && (inv_reg_alloc_order[regno] 1719 < inv_reg_alloc_order[best_reg]) 1720#else 1721 && call_used_regs[regno] 1722 && ! call_used_regs[best_reg] 1723#endif 1724 )) 1725 { 1726 best_reg = regno; 1727 best_cost = this_cost; 1728 } 1729 } 1730 } 1731 if (best_reg == -1) 1732 return 0; 1733 1734 if (rtl_dump_file) 1735 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum); 1736 1737 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode); 1738 rl->regno = best_reg; 1739 1740 EXECUTE_IF_SET_IN_REG_SET 1741 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, 1742 { 1743 count_spilled_pseudo (best_reg, rl->nregs, j); 1744 }); 1745 1746 EXECUTE_IF_SET_IN_REG_SET 1747 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, 1748 { 1749 count_spilled_pseudo (best_reg, rl->nregs, j); 1750 }); 1751 1752 for (i = 0; i < rl->nregs; i++) 1753 { 1754 if (spill_cost[best_reg + i] != 0 1755 || spill_add_cost[best_reg + i] != 0) 1756 abort (); 1757 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i); 1758 } 1759 return 1; 1760} 1761 1762/* Find more reload regs to satisfy the remaining need of an insn, which 1763 is given by CHAIN. 1764 Do it by ascending class number, since otherwise a reg 1765 might be spilled for a big class and might fail to count 1766 for a smaller class even though it belongs to that class. */ 1767 1768static void 1769find_reload_regs (struct insn_chain *chain) 1770{ 1771 int i; 1772 1773 /* In order to be certain of getting the registers we need, 1774 we must sort the reloads into order of increasing register class. 1775 Then our grabbing of reload registers will parallel the process 1776 that provided the reload registers. */ 1777 for (i = 0; i < chain->n_reloads; i++) 1778 { 1779 /* Show whether this reload already has a hard reg. */ 1780 if (chain->rld[i].reg_rtx) 1781 { 1782 int regno = REGNO (chain->rld[i].reg_rtx); 1783 chain->rld[i].regno = regno; 1784 chain->rld[i].nregs 1785 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx)); 1786 } 1787 else 1788 chain->rld[i].regno = -1; 1789 reload_order[i] = i; 1790 } 1791 1792 n_reloads = chain->n_reloads; 1793 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload)); 1794 1795 CLEAR_HARD_REG_SET (used_spill_regs_local); 1796 1797 if (rtl_dump_file) 1798 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn)); 1799 1800 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); 1801 1802 /* Compute the order of preference for hard registers to spill. */ 1803 1804 order_regs_for_reload (chain); 1805 1806 for (i = 0; i < n_reloads; i++) 1807 { 1808 int r = reload_order[i]; 1809 1810 /* Ignore reloads that got marked inoperative. */ 1811 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p) 1812 && ! rld[r].optional 1813 && rld[r].regno == -1) 1814 if (! find_reg (chain, i)) 1815 { 1816 spill_failure (chain->insn, rld[r].class); 1817 failure = 1; 1818 return; 1819 } 1820 } 1821 1822 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local); 1823 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local); 1824 1825 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); 1826} 1827 1828static void 1829select_reload_regs (void) 1830{ 1831 struct insn_chain *chain; 1832 1833 /* Try to satisfy the needs for each insn. */ 1834 for (chain = insns_need_reload; chain != 0; 1835 chain = chain->next_need_reload) 1836 find_reload_regs (chain); 1837} 1838 1839/* Delete all insns that were inserted by emit_caller_save_insns during 1840 this iteration. */ 1841static void 1842delete_caller_save_insns (void) 1843{ 1844 struct insn_chain *c = reload_insn_chain; 1845 1846 while (c != 0) 1847 { 1848 while (c != 0 && c->is_caller_save_insn) 1849 { 1850 struct insn_chain *next = c->next; 1851 rtx insn = c->insn; 1852 1853 if (c == reload_insn_chain) 1854 reload_insn_chain = next; 1855 delete_insn (insn); 1856 1857 if (next) 1858 next->prev = c->prev; 1859 if (c->prev) 1860 c->prev->next = next; 1861 c->next = unused_insn_chains; 1862 unused_insn_chains = c; 1863 c = next; 1864 } 1865 if (c != 0) 1866 c = c->next; 1867 } 1868} 1869 1870/* Handle the failure to find a register to spill. 1871 INSN should be one of the insns which needed this particular spill reg. */ 1872 1873static void 1874spill_failure (rtx insn, enum reg_class class) 1875{ 1876 static const char *const reg_class_names[] = REG_CLASS_NAMES; 1877 if (asm_noperands (PATTERN (insn)) >= 0) 1878 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'", 1879 reg_class_names[class]); 1880 else 1881 { 1882 error ("unable to find a register to spill in class `%s'", 1883 reg_class_names[class]); 1884 fatal_insn ("this is the insn:", insn); 1885 } 1886} 1887 1888/* Delete an unneeded INSN and any previous insns who sole purpose is loading 1889 data that is dead in INSN. */ 1890 1891static void 1892delete_dead_insn (rtx insn) 1893{ 1894 rtx prev = prev_real_insn (insn); 1895 rtx prev_dest; 1896 1897 /* If the previous insn sets a register that dies in our insn, delete it 1898 too. */ 1899 if (prev && GET_CODE (PATTERN (prev)) == SET 1900 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG) 1901 && reg_mentioned_p (prev_dest, PATTERN (insn)) 1902 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) 1903 && ! side_effects_p (SET_SRC (PATTERN (prev)))) 1904 delete_dead_insn (prev); 1905 1906 PUT_CODE (insn, NOTE); 1907 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 1908 NOTE_SOURCE_FILE (insn) = 0; 1909} 1910 1911/* Modify the home of pseudo-reg I. 1912 The new home is present in reg_renumber[I]. 1913 1914 FROM_REG may be the hard reg that the pseudo-reg is being spilled from; 1915 or it may be -1, meaning there is none or it is not relevant. 1916 This is used so that all pseudos spilled from a given hard reg 1917 can share one stack slot. */ 1918 1919static void 1920alter_reg (int i, int from_reg) 1921{ 1922 /* When outputting an inline function, this can happen 1923 for a reg that isn't actually used. */ 1924 if (regno_reg_rtx[i] == 0) 1925 return; 1926 1927 /* If the reg got changed to a MEM at rtl-generation time, 1928 ignore it. */ 1929 if (GET_CODE (regno_reg_rtx[i]) != REG) 1930 return; 1931 1932 /* Modify the reg-rtx to contain the new hard reg 1933 number or else to contain its pseudo reg number. */ 1934 REGNO (regno_reg_rtx[i]) 1935 = reg_renumber[i] >= 0 ? reg_renumber[i] : i; 1936 1937 /* If we have a pseudo that is needed but has no hard reg or equivalent, 1938 allocate a stack slot for it. */ 1939 1940 if (reg_renumber[i] < 0 1941 && REG_N_REFS (i) > 0 1942 && reg_equiv_constant[i] == 0 1943 && reg_equiv_memory_loc[i] == 0) 1944 { 1945 rtx x; 1946 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i); 1947 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]); 1948 int adjust = 0; 1949 1950 /* Each pseudo reg has an inherent size which comes from its own mode, 1951 and a total size which provides room for paradoxical subregs 1952 which refer to the pseudo reg in wider modes. 1953 1954 We can use a slot already allocated if it provides both 1955 enough inherent space and enough total space. 1956 Otherwise, we allocate a new slot, making sure that it has no less 1957 inherent space, and no less total space, then the previous slot. */ 1958 if (from_reg == -1) 1959 { 1960 /* No known place to spill from => no slot to reuse. */ 1961 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, 1962 inherent_size == total_size ? 0 : -1); 1963 if (BYTES_BIG_ENDIAN) 1964 /* Cancel the big-endian correction done in assign_stack_local. 1965 Get the address of the beginning of the slot. 1966 This is so we can do a big-endian correction unconditionally 1967 below. */ 1968 adjust = inherent_size - total_size; 1969 1970 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); 1971 1972 /* Nothing can alias this slot except this pseudo. */ 1973 set_mem_alias_set (x, new_alias_set ()); 1974 } 1975 1976 /* Reuse a stack slot if possible. */ 1977 else if (spill_stack_slot[from_reg] != 0 1978 && spill_stack_slot_width[from_reg] >= total_size 1979 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) 1980 >= inherent_size)) 1981 x = spill_stack_slot[from_reg]; 1982 1983 /* Allocate a bigger slot. */ 1984 else 1985 { 1986 /* Compute maximum size needed, both for inherent size 1987 and for total size. */ 1988 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); 1989 rtx stack_slot; 1990 1991 if (spill_stack_slot[from_reg]) 1992 { 1993 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) 1994 > inherent_size) 1995 mode = GET_MODE (spill_stack_slot[from_reg]); 1996 if (spill_stack_slot_width[from_reg] > total_size) 1997 total_size = spill_stack_slot_width[from_reg]; 1998 } 1999 2000 /* Make a slot with that size. */ 2001 x = assign_stack_local (mode, total_size, 2002 inherent_size == total_size ? 0 : -1); 2003 stack_slot = x; 2004 2005 /* All pseudos mapped to this slot can alias each other. */ 2006 if (spill_stack_slot[from_reg]) 2007 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg])); 2008 else 2009 set_mem_alias_set (x, new_alias_set ()); 2010 2011 if (BYTES_BIG_ENDIAN) 2012 { 2013 /* Cancel the big-endian correction done in assign_stack_local. 2014 Get the address of the beginning of the slot. 2015 This is so we can do a big-endian correction unconditionally 2016 below. */ 2017 adjust = GET_MODE_SIZE (mode) - total_size; 2018 if (adjust) 2019 stack_slot 2020 = adjust_address_nv (x, mode_for_size (total_size 2021 * BITS_PER_UNIT, 2022 MODE_INT, 1), 2023 adjust); 2024 } 2025 2026 spill_stack_slot[from_reg] = stack_slot; 2027 spill_stack_slot_width[from_reg] = total_size; 2028 } 2029 2030 /* On a big endian machine, the "address" of the slot 2031 is the address of the low part that fits its inherent mode. */ 2032 if (BYTES_BIG_ENDIAN && inherent_size < total_size) 2033 adjust += (total_size - inherent_size); 2034 2035 /* If we have any adjustment to make, or if the stack slot is the 2036 wrong mode, make a new stack slot. */ 2037 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust); 2038 2039 /* If we have a decl for the original register, set it for the 2040 memory. If this is a shared MEM, make a copy. */ 2041 if (REG_EXPR (regno_reg_rtx[i]) 2042 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd') 2043 { 2044 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i])); 2045 2046 /* We can do this only for the DECLs home pseudo, not for 2047 any copies of it, since otherwise when the stack slot 2048 is reused, nonoverlapping_memrefs_p might think they 2049 cannot overlap. */ 2050 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i) 2051 { 2052 if (from_reg != -1 && spill_stack_slot[from_reg] == x) 2053 x = copy_rtx (x); 2054 2055 set_mem_attrs_from_reg (x, regno_reg_rtx[i]); 2056 } 2057 } 2058 2059 /* Save the stack slot for later. */ 2060 reg_equiv_memory_loc[i] = x; 2061 } 2062} 2063 2064/* Mark the slots in regs_ever_live for the hard regs 2065 used by pseudo-reg number REGNO. */ 2066 2067void 2068mark_home_live (int regno) 2069{ 2070 int i, lim; 2071 2072 i = reg_renumber[regno]; 2073 if (i < 0) 2074 return; 2075 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno)); 2076 while (i < lim) 2077 regs_ever_live[i++] = 1; 2078} 2079 2080/* This function handles the tracking of elimination offsets around branches. 2081 2082 X is a piece of RTL being scanned. 2083 2084 INSN is the insn that it came from, if any. 2085 2086 INITIAL_P is nonzero if we are to set the offset to be the initial 2087 offset and zero if we are setting the offset of the label to be the 2088 current offset. */ 2089 2090static void 2091set_label_offsets (rtx x, rtx insn, int initial_p) 2092{ 2093 enum rtx_code code = GET_CODE (x); 2094 rtx tem; 2095 unsigned int i; 2096 struct elim_table *p; 2097 2098 switch (code) 2099 { 2100 case LABEL_REF: 2101 if (LABEL_REF_NONLOCAL_P (x)) 2102 return; 2103 2104 x = XEXP (x, 0); 2105 2106 /* ... fall through ... */ 2107 2108 case CODE_LABEL: 2109 /* If we know nothing about this label, set the desired offsets. Note 2110 that this sets the offset at a label to be the offset before a label 2111 if we don't know anything about the label. This is not correct for 2112 the label after a BARRIER, but is the best guess we can make. If 2113 we guessed wrong, we will suppress an elimination that might have 2114 been possible had we been able to guess correctly. */ 2115 2116 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num]) 2117 { 2118 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 2119 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i] 2120 = (initial_p ? reg_eliminate[i].initial_offset 2121 : reg_eliminate[i].offset); 2122 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1; 2123 } 2124 2125 /* Otherwise, if this is the definition of a label and it is 2126 preceded by a BARRIER, set our offsets to the known offset of 2127 that label. */ 2128 2129 else if (x == insn 2130 && (tem = prev_nonnote_insn (insn)) != 0 2131 && GET_CODE (tem) == BARRIER) 2132 set_offsets_for_label (insn); 2133 else 2134 /* If neither of the above cases is true, compare each offset 2135 with those previously recorded and suppress any eliminations 2136 where the offsets disagree. */ 2137 2138 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 2139 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i] 2140 != (initial_p ? reg_eliminate[i].initial_offset 2141 : reg_eliminate[i].offset)) 2142 reg_eliminate[i].can_eliminate = 0; 2143 2144 return; 2145 2146 case JUMP_INSN: 2147 set_label_offsets (PATTERN (insn), insn, initial_p); 2148 2149 /* ... fall through ... */ 2150 2151 case INSN: 2152 case CALL_INSN: 2153 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly 2154 and hence must have all eliminations at their initial offsets. */ 2155 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) 2156 if (REG_NOTE_KIND (tem) == REG_LABEL) 2157 set_label_offsets (XEXP (tem, 0), insn, 1); 2158 return; 2159 2160 case PARALLEL: 2161 case ADDR_VEC: 2162 case ADDR_DIFF_VEC: 2163 /* Each of the labels in the parallel or address vector must be 2164 at their initial offsets. We want the first field for PARALLEL 2165 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */ 2166 2167 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++) 2168 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), 2169 insn, initial_p); 2170 return; 2171 2172 case SET: 2173 /* We only care about setting PC. If the source is not RETURN, 2174 IF_THEN_ELSE, or a label, disable any eliminations not at 2175 their initial offsets. Similarly if any arm of the IF_THEN_ELSE 2176 isn't one of those possibilities. For branches to a label, 2177 call ourselves recursively. 2178 2179 Note that this can disable elimination unnecessarily when we have 2180 a non-local goto since it will look like a non-constant jump to 2181 someplace in the current function. This isn't a significant 2182 problem since such jumps will normally be when all elimination 2183 pairs are back to their initial offsets. */ 2184 2185 if (SET_DEST (x) != pc_rtx) 2186 return; 2187 2188 switch (GET_CODE (SET_SRC (x))) 2189 { 2190 case PC: 2191 case RETURN: 2192 return; 2193 2194 case LABEL_REF: 2195 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p); 2196 return; 2197 2198 case IF_THEN_ELSE: 2199 tem = XEXP (SET_SRC (x), 1); 2200 if (GET_CODE (tem) == LABEL_REF) 2201 set_label_offsets (XEXP (tem, 0), insn, initial_p); 2202 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) 2203 break; 2204 2205 tem = XEXP (SET_SRC (x), 2); 2206 if (GET_CODE (tem) == LABEL_REF) 2207 set_label_offsets (XEXP (tem, 0), insn, initial_p); 2208 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) 2209 break; 2210 return; 2211 2212 default: 2213 break; 2214 } 2215 2216 /* If we reach here, all eliminations must be at their initial 2217 offset because we are doing a jump to a variable address. */ 2218 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) 2219 if (p->offset != p->initial_offset) 2220 p->can_eliminate = 0; 2221 break; 2222 2223 default: 2224 break; 2225 } 2226} 2227 2228/* Scan X and replace any eliminable registers (such as fp) with a 2229 replacement (such as sp), plus an offset. 2230 2231 MEM_MODE is the mode of an enclosing MEM. We need this to know how 2232 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a 2233 MEM, we are allowed to replace a sum of a register and the constant zero 2234 with the register, which we cannot do outside a MEM. In addition, we need 2235 to record the fact that a register is referenced outside a MEM. 2236 2237 If INSN is an insn, it is the insn containing X. If we replace a REG 2238 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a 2239 CLOBBER of the pseudo after INSN so find_equiv_regs will know that 2240 the REG is being modified. 2241 2242 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). 2243 That's used when we eliminate in expressions stored in notes. 2244 This means, do not set ref_outside_mem even if the reference 2245 is outside of MEMs. 2246 2247 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had 2248 replacements done assuming all offsets are at their initial values. If 2249 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we 2250 encounter, return the actual location so that find_reloads will do 2251 the proper thing. */ 2252 2253rtx 2254eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn) 2255{ 2256 enum rtx_code code = GET_CODE (x); 2257 struct elim_table *ep; 2258 int regno; 2259 rtx new; 2260 int i, j; 2261 const char *fmt; 2262 int copied = 0; 2263 2264 if (! current_function_decl) 2265 return x; 2266 2267 switch (code) 2268 { 2269 case CONST_INT: 2270 case CONST_DOUBLE: 2271 case CONST_VECTOR: 2272 case CONST: 2273 case SYMBOL_REF: 2274 case CODE_LABEL: 2275 case PC: 2276 case CC0: 2277 case ASM_INPUT: 2278 case ADDR_VEC: 2279 case ADDR_DIFF_VEC: 2280 case RETURN: 2281 return x; 2282 2283 case ADDRESSOF: 2284 /* This is only for the benefit of the debugging backends, which call 2285 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are 2286 removed after CSE. */ 2287 new = eliminate_regs (XEXP (x, 0), 0, insn); 2288 if (GET_CODE (new) == MEM) 2289 return XEXP (new, 0); 2290 return x; 2291 2292 case REG: 2293 regno = REGNO (x); 2294 2295 /* First handle the case where we encounter a bare register that 2296 is eliminable. Replace it with a PLUS. */ 2297 if (regno < FIRST_PSEUDO_REGISTER) 2298 { 2299 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2300 ep++) 2301 if (ep->from_rtx == x && ep->can_eliminate) 2302 return plus_constant (ep->to_rtx, ep->previous_offset); 2303 2304 } 2305 else if (reg_renumber && reg_renumber[regno] < 0 2306 && reg_equiv_constant && reg_equiv_constant[regno] 2307 && ! CONSTANT_P (reg_equiv_constant[regno])) 2308 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]), 2309 mem_mode, insn); 2310 return x; 2311 2312 /* You might think handling MINUS in a manner similar to PLUS is a 2313 good idea. It is not. It has been tried multiple times and every 2314 time the change has had to have been reverted. 2315 2316 Other parts of reload know a PLUS is special (gen_reload for example) 2317 and require special code to handle code a reloaded PLUS operand. 2318 2319 Also consider backends where the flags register is clobbered by a 2320 MINUS, but we can emit a PLUS that does not clobber flags (ia32, 2321 lea instruction comes to mind). If we try to reload a MINUS, we 2322 may kill the flags register that was holding a useful value. 2323 2324 So, please before trying to handle MINUS, consider reload as a 2325 whole instead of this little section as well as the backend issues. */ 2326 case PLUS: 2327 /* If this is the sum of an eliminable register and a constant, rework 2328 the sum. */ 2329 if (GET_CODE (XEXP (x, 0)) == REG 2330 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER 2331 && CONSTANT_P (XEXP (x, 1))) 2332 { 2333 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2334 ep++) 2335 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) 2336 { 2337 /* The only time we want to replace a PLUS with a REG (this 2338 occurs when the constant operand of the PLUS is the negative 2339 of the offset) is when we are inside a MEM. We won't want 2340 to do so at other times because that would change the 2341 structure of the insn in a way that reload can't handle. 2342 We special-case the commonest situation in 2343 eliminate_regs_in_insn, so just replace a PLUS with a 2344 PLUS here, unless inside a MEM. */ 2345 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT 2346 && INTVAL (XEXP (x, 1)) == - ep->previous_offset) 2347 return ep->to_rtx; 2348 else 2349 return gen_rtx_PLUS (Pmode, ep->to_rtx, 2350 plus_constant (XEXP (x, 1), 2351 ep->previous_offset)); 2352 } 2353 2354 /* If the register is not eliminable, we are done since the other 2355 operand is a constant. */ 2356 return x; 2357 } 2358 2359 /* If this is part of an address, we want to bring any constant to the 2360 outermost PLUS. We will do this by doing register replacement in 2361 our operands and seeing if a constant shows up in one of them. 2362 2363 Note that there is no risk of modifying the structure of the insn, 2364 since we only get called for its operands, thus we are either 2365 modifying the address inside a MEM, or something like an address 2366 operand of a load-address insn. */ 2367 2368 { 2369 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); 2370 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn); 2371 2372 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))) 2373 { 2374 /* If one side is a PLUS and the other side is a pseudo that 2375 didn't get a hard register but has a reg_equiv_constant, 2376 we must replace the constant here since it may no longer 2377 be in the position of any operand. */ 2378 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG 2379 && REGNO (new1) >= FIRST_PSEUDO_REGISTER 2380 && reg_renumber[REGNO (new1)] < 0 2381 && reg_equiv_constant != 0 2382 && reg_equiv_constant[REGNO (new1)] != 0) 2383 new1 = reg_equiv_constant[REGNO (new1)]; 2384 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG 2385 && REGNO (new0) >= FIRST_PSEUDO_REGISTER 2386 && reg_renumber[REGNO (new0)] < 0 2387 && reg_equiv_constant[REGNO (new0)] != 0) 2388 new0 = reg_equiv_constant[REGNO (new0)]; 2389 2390 new = form_sum (new0, new1); 2391 2392 /* As above, if we are not inside a MEM we do not want to 2393 turn a PLUS into something else. We might try to do so here 2394 for an addition of 0 if we aren't optimizing. */ 2395 if (! mem_mode && GET_CODE (new) != PLUS) 2396 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx); 2397 else 2398 return new; 2399 } 2400 } 2401 return x; 2402 2403 case MULT: 2404 /* If this is the product of an eliminable register and a 2405 constant, apply the distribute law and move the constant out 2406 so that we have (plus (mult ..) ..). This is needed in order 2407 to keep load-address insns valid. This case is pathological. 2408 We ignore the possibility of overflow here. */ 2409 if (GET_CODE (XEXP (x, 0)) == REG 2410 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER 2411 && GET_CODE (XEXP (x, 1)) == CONST_INT) 2412 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2413 ep++) 2414 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) 2415 { 2416 if (! mem_mode 2417 /* Refs inside notes don't count for this purpose. */ 2418 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST 2419 || GET_CODE (insn) == INSN_LIST))) 2420 ep->ref_outside_mem = 1; 2421 2422 return 2423 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), 2424 ep->previous_offset * INTVAL (XEXP (x, 1))); 2425 } 2426 2427 /* ... fall through ... */ 2428 2429 case CALL: 2430 case COMPARE: 2431 /* See comments before PLUS about handling MINUS. */ 2432 case MINUS: 2433 case DIV: case UDIV: 2434 case MOD: case UMOD: 2435 case AND: case IOR: case XOR: 2436 case ROTATERT: case ROTATE: 2437 case ASHIFTRT: case LSHIFTRT: case ASHIFT: 2438 case NE: case EQ: 2439 case GE: case GT: case GEU: case GTU: 2440 case LE: case LT: case LEU: case LTU: 2441 { 2442 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); 2443 rtx new1 2444 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0; 2445 2446 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) 2447 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); 2448 } 2449 return x; 2450 2451 case EXPR_LIST: 2452 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ 2453 if (XEXP (x, 0)) 2454 { 2455 new = eliminate_regs (XEXP (x, 0), mem_mode, insn); 2456 if (new != XEXP (x, 0)) 2457 { 2458 /* If this is a REG_DEAD note, it is not valid anymore. 2459 Using the eliminated version could result in creating a 2460 REG_DEAD note for the stack or frame pointer. */ 2461 if (GET_MODE (x) == REG_DEAD) 2462 return (XEXP (x, 1) 2463 ? eliminate_regs (XEXP (x, 1), mem_mode, insn) 2464 : NULL_RTX); 2465 2466 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1)); 2467 } 2468 } 2469 2470 /* ... fall through ... */ 2471 2472 case INSN_LIST: 2473 /* Now do eliminations in the rest of the chain. If this was 2474 an EXPR_LIST, this might result in allocating more memory than is 2475 strictly needed, but it simplifies the code. */ 2476 if (XEXP (x, 1)) 2477 { 2478 new = eliminate_regs (XEXP (x, 1), mem_mode, insn); 2479 if (new != XEXP (x, 1)) 2480 return 2481 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new); 2482 } 2483 return x; 2484 2485 case PRE_INC: 2486 case POST_INC: 2487 case PRE_DEC: 2488 case POST_DEC: 2489 case STRICT_LOW_PART: 2490 case NEG: case NOT: 2491 case SIGN_EXTEND: case ZERO_EXTEND: 2492 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: 2493 case FLOAT: case FIX: 2494 case UNSIGNED_FIX: case UNSIGNED_FLOAT: 2495 case ABS: 2496 case SQRT: 2497 case FFS: 2498 case CLZ: 2499 case CTZ: 2500 case POPCOUNT: 2501 case PARITY: 2502 new = eliminate_regs (XEXP (x, 0), mem_mode, insn); 2503 if (new != XEXP (x, 0)) 2504 return gen_rtx_fmt_e (code, GET_MODE (x), new); 2505 return x; 2506 2507 case SUBREG: 2508 /* Similar to above processing, but preserve SUBREG_BYTE. 2509 Convert (subreg (mem)) to (mem) if not paradoxical. 2510 Also, if we have a non-paradoxical (subreg (pseudo)) and the 2511 pseudo didn't get a hard reg, we must replace this with the 2512 eliminated version of the memory location because push_reload 2513 may do the replacement in certain circumstances. */ 2514 if (GET_CODE (SUBREG_REG (x)) == REG 2515 && (GET_MODE_SIZE (GET_MODE (x)) 2516 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 2517 && reg_equiv_memory_loc != 0 2518 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) 2519 { 2520 new = SUBREG_REG (x); 2521 } 2522 else 2523 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn); 2524 2525 if (new != SUBREG_REG (x)) 2526 { 2527 int x_size = GET_MODE_SIZE (GET_MODE (x)); 2528 int new_size = GET_MODE_SIZE (GET_MODE (new)); 2529 2530 if (GET_CODE (new) == MEM 2531 && ((x_size < new_size 2532#ifdef WORD_REGISTER_OPERATIONS 2533 /* On these machines, combine can create rtl of the form 2534 (set (subreg:m1 (reg:m2 R) 0) ...) 2535 where m1 < m2, and expects something interesting to 2536 happen to the entire word. Moreover, it will use the 2537 (reg:m2 R) later, expecting all bits to be preserved. 2538 So if the number of words is the same, preserve the 2539 subreg so that push_reload can see it. */ 2540 && ! ((x_size - 1) / UNITS_PER_WORD 2541 == (new_size -1 ) / UNITS_PER_WORD) 2542#endif 2543 ) 2544 || x_size == new_size) 2545 ) 2546 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x)); 2547 else 2548 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x)); 2549 } 2550 2551 return x; 2552 2553 case MEM: 2554 /* This is only for the benefit of the debugging backends, which call 2555 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are 2556 removed after CSE. */ 2557 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) 2558 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn); 2559 2560 /* Our only special processing is to pass the mode of the MEM to our 2561 recursive call and copy the flags. While we are here, handle this 2562 case more efficiently. */ 2563 return 2564 replace_equiv_address_nv (x, 2565 eliminate_regs (XEXP (x, 0), 2566 GET_MODE (x), insn)); 2567 2568 case USE: 2569 /* Handle insn_list USE that a call to a pure function may generate. */ 2570 new = eliminate_regs (XEXP (x, 0), 0, insn); 2571 if (new != XEXP (x, 0)) 2572 return gen_rtx_USE (GET_MODE (x), new); 2573 return x; 2574 2575 case CLOBBER: 2576 case ASM_OPERANDS: 2577 case SET: 2578 abort (); 2579 2580 default: 2581 break; 2582 } 2583 2584 /* Process each of our operands recursively. If any have changed, make a 2585 copy of the rtx. */ 2586 fmt = GET_RTX_FORMAT (code); 2587 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) 2588 { 2589 if (*fmt == 'e') 2590 { 2591 new = eliminate_regs (XEXP (x, i), mem_mode, insn); 2592 if (new != XEXP (x, i) && ! copied) 2593 { 2594 rtx new_x = rtx_alloc (code); 2595 memcpy (new_x, x, RTX_SIZE (code)); 2596 x = new_x; 2597 copied = 1; 2598 } 2599 XEXP (x, i) = new; 2600 } 2601 else if (*fmt == 'E') 2602 { 2603 int copied_vec = 0; 2604 for (j = 0; j < XVECLEN (x, i); j++) 2605 { 2606 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn); 2607 if (new != XVECEXP (x, i, j) && ! copied_vec) 2608 { 2609 rtvec new_v = gen_rtvec_v (XVECLEN (x, i), 2610 XVEC (x, i)->elem); 2611 if (! copied) 2612 { 2613 rtx new_x = rtx_alloc (code); 2614 memcpy (new_x, x, RTX_SIZE (code)); 2615 x = new_x; 2616 copied = 1; 2617 } 2618 XVEC (x, i) = new_v; 2619 copied_vec = 1; 2620 } 2621 XVECEXP (x, i, j) = new; 2622 } 2623 } 2624 } 2625 2626 return x; 2627} 2628 2629/* Scan rtx X for modifications of elimination target registers. Update 2630 the table of eliminables to reflect the changed state. MEM_MODE is 2631 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */ 2632 2633static void 2634elimination_effects (rtx x, enum machine_mode mem_mode) 2635{ 2636 enum rtx_code code = GET_CODE (x); 2637 struct elim_table *ep; 2638 int regno; 2639 int i, j; 2640 const char *fmt; 2641 2642 switch (code) 2643 { 2644 case CONST_INT: 2645 case CONST_DOUBLE: 2646 case CONST_VECTOR: 2647 case CONST: 2648 case SYMBOL_REF: 2649 case CODE_LABEL: 2650 case PC: 2651 case CC0: 2652 case ASM_INPUT: 2653 case ADDR_VEC: 2654 case ADDR_DIFF_VEC: 2655 case RETURN: 2656 return; 2657 2658 case ADDRESSOF: 2659 abort (); 2660 2661 case REG: 2662 regno = REGNO (x); 2663 2664 /* First handle the case where we encounter a bare register that 2665 is eliminable. Replace it with a PLUS. */ 2666 if (regno < FIRST_PSEUDO_REGISTER) 2667 { 2668 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2669 ep++) 2670 if (ep->from_rtx == x && ep->can_eliminate) 2671 { 2672 if (! mem_mode) 2673 ep->ref_outside_mem = 1; 2674 return; 2675 } 2676 2677 } 2678 else if (reg_renumber[regno] < 0 && reg_equiv_constant 2679 && reg_equiv_constant[regno] 2680 && ! function_invariant_p (reg_equiv_constant[regno])) 2681 elimination_effects (reg_equiv_constant[regno], mem_mode); 2682 return; 2683 2684 case PRE_INC: 2685 case POST_INC: 2686 case PRE_DEC: 2687 case POST_DEC: 2688 case POST_MODIFY: 2689 case PRE_MODIFY: 2690 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 2691 if (ep->to_rtx == XEXP (x, 0)) 2692 { 2693 int size = GET_MODE_SIZE (mem_mode); 2694 2695 /* If more bytes than MEM_MODE are pushed, account for them. */ 2696#ifdef PUSH_ROUNDING 2697 if (ep->to_rtx == stack_pointer_rtx) 2698 size = PUSH_ROUNDING (size); 2699#endif 2700 if (code == PRE_DEC || code == POST_DEC) 2701 ep->offset += size; 2702 else if (code == PRE_INC || code == POST_INC) 2703 ep->offset -= size; 2704 else if ((code == PRE_MODIFY || code == POST_MODIFY) 2705 && GET_CODE (XEXP (x, 1)) == PLUS 2706 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0) 2707 && CONSTANT_P (XEXP (XEXP (x, 1), 1))) 2708 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1)); 2709 } 2710 2711 /* These two aren't unary operators. */ 2712 if (code == POST_MODIFY || code == PRE_MODIFY) 2713 break; 2714 2715 /* Fall through to generic unary operation case. */ 2716 case STRICT_LOW_PART: 2717 case NEG: case NOT: 2718 case SIGN_EXTEND: case ZERO_EXTEND: 2719 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: 2720 case FLOAT: case FIX: 2721 case UNSIGNED_FIX: case UNSIGNED_FLOAT: 2722 case ABS: 2723 case SQRT: 2724 case FFS: 2725 case CLZ: 2726 case CTZ: 2727 case POPCOUNT: 2728 case PARITY: 2729 elimination_effects (XEXP (x, 0), mem_mode); 2730 return; 2731 2732 case SUBREG: 2733 if (GET_CODE (SUBREG_REG (x)) == REG 2734 && (GET_MODE_SIZE (GET_MODE (x)) 2735 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 2736 && reg_equiv_memory_loc != 0 2737 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) 2738 return; 2739 2740 elimination_effects (SUBREG_REG (x), mem_mode); 2741 return; 2742 2743 case USE: 2744 /* If using a register that is the source of an eliminate we still 2745 think can be performed, note it cannot be performed since we don't 2746 know how this register is used. */ 2747 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 2748 if (ep->from_rtx == XEXP (x, 0)) 2749 ep->can_eliminate = 0; 2750 2751 elimination_effects (XEXP (x, 0), mem_mode); 2752 return; 2753 2754 case CLOBBER: 2755 /* If clobbering a register that is the replacement register for an 2756 elimination we still think can be performed, note that it cannot 2757 be performed. Otherwise, we need not be concerned about it. */ 2758 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 2759 if (ep->to_rtx == XEXP (x, 0)) 2760 ep->can_eliminate = 0; 2761 2762 elimination_effects (XEXP (x, 0), mem_mode); 2763 return; 2764 2765 case SET: 2766 /* Check for setting a register that we know about. */ 2767 if (GET_CODE (SET_DEST (x)) == REG) 2768 { 2769 /* See if this is setting the replacement register for an 2770 elimination. 2771 2772 If DEST is the hard frame pointer, we do nothing because we 2773 assume that all assignments to the frame pointer are for 2774 non-local gotos and are being done at a time when they are valid 2775 and do not disturb anything else. Some machines want to 2776 eliminate a fake argument pointer (or even a fake frame pointer) 2777 with either the real frame or the stack pointer. Assignments to 2778 the hard frame pointer must not prevent this elimination. */ 2779 2780 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2781 ep++) 2782 if (ep->to_rtx == SET_DEST (x) 2783 && SET_DEST (x) != hard_frame_pointer_rtx) 2784 { 2785 /* If it is being incremented, adjust the offset. Otherwise, 2786 this elimination can't be done. */ 2787 rtx src = SET_SRC (x); 2788 2789 if (GET_CODE (src) == PLUS 2790 && XEXP (src, 0) == SET_DEST (x) 2791 && GET_CODE (XEXP (src, 1)) == CONST_INT) 2792 ep->offset -= INTVAL (XEXP (src, 1)); 2793 else 2794 ep->can_eliminate = 0; 2795 } 2796 } 2797 2798 elimination_effects (SET_DEST (x), 0); 2799 elimination_effects (SET_SRC (x), 0); 2800 return; 2801 2802 case MEM: 2803 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) 2804 abort (); 2805 2806 /* Our only special processing is to pass the mode of the MEM to our 2807 recursive call. */ 2808 elimination_effects (XEXP (x, 0), GET_MODE (x)); 2809 return; 2810 2811 default: 2812 break; 2813 } 2814 2815 fmt = GET_RTX_FORMAT (code); 2816 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) 2817 { 2818 if (*fmt == 'e') 2819 elimination_effects (XEXP (x, i), mem_mode); 2820 else if (*fmt == 'E') 2821 for (j = 0; j < XVECLEN (x, i); j++) 2822 elimination_effects (XVECEXP (x, i, j), mem_mode); 2823 } 2824} 2825 2826/* Descend through rtx X and verify that no references to eliminable registers 2827 remain. If any do remain, mark the involved register as not 2828 eliminable. */ 2829 2830static void 2831check_eliminable_occurrences (rtx x) 2832{ 2833 const char *fmt; 2834 int i; 2835 enum rtx_code code; 2836 2837 if (x == 0) 2838 return; 2839 2840 code = GET_CODE (x); 2841 2842 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) 2843 { 2844 struct elim_table *ep; 2845 2846 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 2847 if (ep->from_rtx == x && ep->can_eliminate) 2848 ep->can_eliminate = 0; 2849 return; 2850 } 2851 2852 fmt = GET_RTX_FORMAT (code); 2853 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) 2854 { 2855 if (*fmt == 'e') 2856 check_eliminable_occurrences (XEXP (x, i)); 2857 else if (*fmt == 'E') 2858 { 2859 int j; 2860 for (j = 0; j < XVECLEN (x, i); j++) 2861 check_eliminable_occurrences (XVECEXP (x, i, j)); 2862 } 2863 } 2864} 2865 2866/* Scan INSN and eliminate all eliminable registers in it. 2867 2868 If REPLACE is nonzero, do the replacement destructively. Also 2869 delete the insn as dead it if it is setting an eliminable register. 2870 2871 If REPLACE is zero, do all our allocations in reload_obstack. 2872 2873 If no eliminations were done and this insn doesn't require any elimination 2874 processing (these are not identical conditions: it might be updating sp, 2875 but not referencing fp; this needs to be seen during reload_as_needed so 2876 that the offset between fp and sp can be taken into consideration), zero 2877 is returned. Otherwise, 1 is returned. */ 2878 2879static int 2880eliminate_regs_in_insn (rtx insn, int replace) 2881{ 2882 int icode = recog_memoized (insn); 2883 rtx old_body = PATTERN (insn); 2884 int insn_is_asm = asm_noperands (old_body) >= 0; 2885 rtx old_set = single_set (insn); 2886 rtx new_body; 2887 int val = 0; 2888 int i; 2889 rtx substed_operand[MAX_RECOG_OPERANDS]; 2890 rtx orig_operand[MAX_RECOG_OPERANDS]; 2891 struct elim_table *ep; 2892 2893 if (! insn_is_asm && icode < 0) 2894 { 2895 if (GET_CODE (PATTERN (insn)) == USE 2896 || GET_CODE (PATTERN (insn)) == CLOBBER 2897 || GET_CODE (PATTERN (insn)) == ADDR_VEC 2898 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC 2899 || GET_CODE (PATTERN (insn)) == ASM_INPUT) 2900 return 0; 2901 abort (); 2902 } 2903 2904 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG 2905 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) 2906 { 2907 /* Check for setting an eliminable register. */ 2908 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 2909 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) 2910 { 2911#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 2912 /* If this is setting the frame pointer register to the 2913 hardware frame pointer register and this is an elimination 2914 that will be done (tested above), this insn is really 2915 adjusting the frame pointer downward to compensate for 2916 the adjustment done before a nonlocal goto. */ 2917 if (ep->from == FRAME_POINTER_REGNUM 2918 && ep->to == HARD_FRAME_POINTER_REGNUM) 2919 { 2920 rtx base = SET_SRC (old_set); 2921 rtx base_insn = insn; 2922 HOST_WIDE_INT offset = 0; 2923 2924 while (base != ep->to_rtx) 2925 { 2926 rtx prev_insn, prev_set; 2927 2928 if (GET_CODE (base) == PLUS 2929 && GET_CODE (XEXP (base, 1)) == CONST_INT) 2930 { 2931 offset += INTVAL (XEXP (base, 1)); 2932 base = XEXP (base, 0); 2933 } 2934 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0 2935 && (prev_set = single_set (prev_insn)) != 0 2936 && rtx_equal_p (SET_DEST (prev_set), base)) 2937 { 2938 base = SET_SRC (prev_set); 2939 base_insn = prev_insn; 2940 } 2941 else 2942 break; 2943 } 2944 2945 if (base == ep->to_rtx) 2946 { 2947 rtx src 2948 = plus_constant (ep->to_rtx, offset - ep->offset); 2949 2950 new_body = old_body; 2951 if (! replace) 2952 { 2953 new_body = copy_insn (old_body); 2954 if (REG_NOTES (insn)) 2955 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); 2956 } 2957 PATTERN (insn) = new_body; 2958 old_set = single_set (insn); 2959 2960 /* First see if this insn remains valid when we 2961 make the change. If not, keep the INSN_CODE 2962 the same and let reload fit it up. */ 2963 validate_change (insn, &SET_SRC (old_set), src, 1); 2964 validate_change (insn, &SET_DEST (old_set), 2965 ep->to_rtx, 1); 2966 if (! apply_change_group ()) 2967 { 2968 SET_SRC (old_set) = src; 2969 SET_DEST (old_set) = ep->to_rtx; 2970 } 2971 2972 val = 1; 2973 goto done; 2974 } 2975 } 2976#endif 2977 2978 /* In this case this insn isn't serving a useful purpose. We 2979 will delete it in reload_as_needed once we know that this 2980 elimination is, in fact, being done. 2981 2982 If REPLACE isn't set, we can't delete this insn, but needn't 2983 process it since it won't be used unless something changes. */ 2984 if (replace) 2985 { 2986 delete_dead_insn (insn); 2987 return 1; 2988 } 2989 val = 1; 2990 goto done; 2991 } 2992 } 2993 2994 /* We allow one special case which happens to work on all machines we 2995 currently support: a single set with the source being a PLUS of an 2996 eliminable register and a constant. */ 2997 if (old_set 2998 && GET_CODE (SET_DEST (old_set)) == REG 2999 && GET_CODE (SET_SRC (old_set)) == PLUS 3000 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG 3001 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT 3002 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER) 3003 { 3004 rtx reg = XEXP (SET_SRC (old_set), 0); 3005 HOST_WIDE_INT offset = INTVAL (XEXP (SET_SRC (old_set), 1)); 3006 3007 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3008 if (ep->from_rtx == reg && ep->can_eliminate) 3009 { 3010 offset += ep->offset; 3011 3012 if (offset == 0) 3013 { 3014 int num_clobbers; 3015 /* We assume here that if we need a PARALLEL with 3016 CLOBBERs for this assignment, we can do with the 3017 MATCH_SCRATCHes that add_clobbers allocates. 3018 There's not much we can do if that doesn't work. */ 3019 PATTERN (insn) = gen_rtx_SET (VOIDmode, 3020 SET_DEST (old_set), 3021 ep->to_rtx); 3022 num_clobbers = 0; 3023 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers); 3024 if (num_clobbers) 3025 { 3026 rtvec vec = rtvec_alloc (num_clobbers + 1); 3027 3028 vec->elem[0] = PATTERN (insn); 3029 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec); 3030 add_clobbers (PATTERN (insn), INSN_CODE (insn)); 3031 } 3032 if (INSN_CODE (insn) < 0) 3033 abort (); 3034 } 3035 else 3036 { 3037 new_body = old_body; 3038 if (! replace) 3039 { 3040 new_body = copy_insn (old_body); 3041 if (REG_NOTES (insn)) 3042 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); 3043 } 3044 PATTERN (insn) = new_body; 3045 old_set = single_set (insn); 3046 3047 XEXP (SET_SRC (old_set), 0) = ep->to_rtx; 3048 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset); 3049 } 3050 val = 1; 3051 /* This can't have an effect on elimination offsets, so skip right 3052 to the end. */ 3053 goto done; 3054 } 3055 } 3056 3057 /* Determine the effects of this insn on elimination offsets. */ 3058 elimination_effects (old_body, 0); 3059 3060 /* Eliminate all eliminable registers occurring in operands that 3061 can be handled by reload. */ 3062 extract_insn (insn); 3063 for (i = 0; i < recog_data.n_operands; i++) 3064 { 3065 orig_operand[i] = recog_data.operand[i]; 3066 substed_operand[i] = recog_data.operand[i]; 3067 3068 /* For an asm statement, every operand is eliminable. */ 3069 if (insn_is_asm || insn_data[icode].operand[i].eliminable) 3070 { 3071 /* Check for setting a register that we know about. */ 3072 if (recog_data.operand_type[i] != OP_IN 3073 && GET_CODE (orig_operand[i]) == REG) 3074 { 3075 /* If we are assigning to a register that can be eliminated, it 3076 must be as part of a PARALLEL, since the code above handles 3077 single SETs. We must indicate that we can no longer 3078 eliminate this reg. */ 3079 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 3080 ep++) 3081 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate) 3082 ep->can_eliminate = 0; 3083 } 3084 3085 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0, 3086 replace ? insn : NULL_RTX); 3087 if (substed_operand[i] != orig_operand[i]) 3088 val = 1; 3089 /* Terminate the search in check_eliminable_occurrences at 3090 this point. */ 3091 *recog_data.operand_loc[i] = 0; 3092 3093 /* If an output operand changed from a REG to a MEM and INSN is an 3094 insn, write a CLOBBER insn. */ 3095 if (recog_data.operand_type[i] != OP_IN 3096 && GET_CODE (orig_operand[i]) == REG 3097 && GET_CODE (substed_operand[i]) == MEM 3098 && replace) 3099 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]), 3100 insn); 3101 } 3102 } 3103 3104 for (i = 0; i < recog_data.n_dups; i++) 3105 *recog_data.dup_loc[i] 3106 = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; 3107 3108 /* If any eliminable remain, they aren't eliminable anymore. */ 3109 check_eliminable_occurrences (old_body); 3110 3111 /* Substitute the operands; the new values are in the substed_operand 3112 array. */ 3113 for (i = 0; i < recog_data.n_operands; i++) 3114 *recog_data.operand_loc[i] = substed_operand[i]; 3115 for (i = 0; i < recog_data.n_dups; i++) 3116 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]]; 3117 3118 /* If we are replacing a body that was a (set X (plus Y Z)), try to 3119 re-recognize the insn. We do this in case we had a simple addition 3120 but now can do this as a load-address. This saves an insn in this 3121 common case. 3122 If re-recognition fails, the old insn code number will still be used, 3123 and some register operands may have changed into PLUS expressions. 3124 These will be handled by find_reloads by loading them into a register 3125 again. */ 3126 3127 if (val) 3128 { 3129 /* If we aren't replacing things permanently and we changed something, 3130 make another copy to ensure that all the RTL is new. Otherwise 3131 things can go wrong if find_reload swaps commutative operands 3132 and one is inside RTL that has been copied while the other is not. */ 3133 new_body = old_body; 3134 if (! replace) 3135 { 3136 new_body = copy_insn (old_body); 3137 if (REG_NOTES (insn)) 3138 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); 3139 } 3140 PATTERN (insn) = new_body; 3141 3142 /* If we had a move insn but now we don't, rerecognize it. This will 3143 cause spurious re-recognition if the old move had a PARALLEL since 3144 the new one still will, but we can't call single_set without 3145 having put NEW_BODY into the insn and the re-recognition won't 3146 hurt in this rare case. */ 3147 /* ??? Why this huge if statement - why don't we just rerecognize the 3148 thing always? */ 3149 if (! insn_is_asm 3150 && old_set != 0 3151 && ((GET_CODE (SET_SRC (old_set)) == REG 3152 && (GET_CODE (new_body) != SET 3153 || GET_CODE (SET_SRC (new_body)) != REG)) 3154 /* If this was a load from or store to memory, compare 3155 the MEM in recog_data.operand to the one in the insn. 3156 If they are not equal, then rerecognize the insn. */ 3157 || (old_set != 0 3158 && ((GET_CODE (SET_SRC (old_set)) == MEM 3159 && SET_SRC (old_set) != recog_data.operand[1]) 3160 || (GET_CODE (SET_DEST (old_set)) == MEM 3161 && SET_DEST (old_set) != recog_data.operand[0]))) 3162 /* If this was an add insn before, rerecognize. */ 3163 || GET_CODE (SET_SRC (old_set)) == PLUS)) 3164 { 3165 int new_icode = recog (PATTERN (insn), insn, 0); 3166 if (new_icode < 0) 3167 INSN_CODE (insn) = icode; 3168 } 3169 } 3170 3171 /* Restore the old body. If there were any changes to it, we made a copy 3172 of it while the changes were still in place, so we'll correctly return 3173 a modified insn below. */ 3174 if (! replace) 3175 { 3176 /* Restore the old body. */ 3177 for (i = 0; i < recog_data.n_operands; i++) 3178 *recog_data.operand_loc[i] = orig_operand[i]; 3179 for (i = 0; i < recog_data.n_dups; i++) 3180 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]]; 3181 } 3182 3183 /* Update all elimination pairs to reflect the status after the current 3184 insn. The changes we make were determined by the earlier call to 3185 elimination_effects. 3186 3187 We also detect cases where register elimination cannot be done, 3188 namely, if a register would be both changed and referenced outside a MEM 3189 in the resulting insn since such an insn is often undefined and, even if 3190 not, we cannot know what meaning will be given to it. Note that it is 3191 valid to have a register used in an address in an insn that changes it 3192 (presumably with a pre- or post-increment or decrement). 3193 3194 If anything changes, return nonzero. */ 3195 3196 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3197 { 3198 if (ep->previous_offset != ep->offset && ep->ref_outside_mem) 3199 ep->can_eliminate = 0; 3200 3201 ep->ref_outside_mem = 0; 3202 3203 if (ep->previous_offset != ep->offset) 3204 val = 1; 3205 } 3206 3207 done: 3208 /* If we changed something, perform elimination in REG_NOTES. This is 3209 needed even when REPLACE is zero because a REG_DEAD note might refer 3210 to a register that we eliminate and could cause a different number 3211 of spill registers to be needed in the final reload pass than in 3212 the pre-passes. */ 3213 if (val && REG_NOTES (insn) != 0) 3214 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn)); 3215 3216 return val; 3217} 3218 3219/* Loop through all elimination pairs. 3220 Recalculate the number not at initial offset. 3221 3222 Compute the maximum offset (minimum offset if the stack does not 3223 grow downward) for each elimination pair. */ 3224 3225static void 3226update_eliminable_offsets (void) 3227{ 3228 struct elim_table *ep; 3229 3230 num_not_at_initial_offset = 0; 3231 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3232 { 3233 ep->previous_offset = ep->offset; 3234 if (ep->can_eliminate && ep->offset != ep->initial_offset) 3235 num_not_at_initial_offset++; 3236 } 3237} 3238 3239/* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register 3240 replacement we currently believe is valid, mark it as not eliminable if X 3241 modifies DEST in any way other than by adding a constant integer to it. 3242 3243 If DEST is the frame pointer, we do nothing because we assume that 3244 all assignments to the hard frame pointer are nonlocal gotos and are being 3245 done at a time when they are valid and do not disturb anything else. 3246 Some machines want to eliminate a fake argument pointer with either the 3247 frame or stack pointer. Assignments to the hard frame pointer must not 3248 prevent this elimination. 3249 3250 Called via note_stores from reload before starting its passes to scan 3251 the insns of the function. */ 3252 3253static void 3254mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED) 3255{ 3256 unsigned int i; 3257 3258 /* A SUBREG of a hard register here is just changing its mode. We should 3259 not see a SUBREG of an eliminable hard register, but check just in 3260 case. */ 3261 if (GET_CODE (dest) == SUBREG) 3262 dest = SUBREG_REG (dest); 3263 3264 if (dest == hard_frame_pointer_rtx) 3265 return; 3266 3267 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 3268 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx 3269 && (GET_CODE (x) != SET 3270 || GET_CODE (SET_SRC (x)) != PLUS 3271 || XEXP (SET_SRC (x), 0) != dest 3272 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) 3273 { 3274 reg_eliminate[i].can_eliminate_previous 3275 = reg_eliminate[i].can_eliminate = 0; 3276 num_eliminable--; 3277 } 3278} 3279 3280/* Verify that the initial elimination offsets did not change since the 3281 last call to set_initial_elim_offsets. This is used to catch cases 3282 where something illegal happened during reload_as_needed that could 3283 cause incorrect code to be generated if we did not check for it. */ 3284 3285static void 3286verify_initial_elim_offsets (void) 3287{ 3288 HOST_WIDE_INT t; 3289 3290#ifdef ELIMINABLE_REGS 3291 struct elim_table *ep; 3292 3293 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3294 { 3295 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t); 3296 if (t != ep->initial_offset) 3297 abort (); 3298 } 3299#else 3300 INITIAL_FRAME_POINTER_OFFSET (t); 3301 if (t != reg_eliminate[0].initial_offset) 3302 abort (); 3303#endif 3304} 3305 3306/* Reset all offsets on eliminable registers to their initial values. */ 3307 3308static void 3309set_initial_elim_offsets (void) 3310{ 3311 struct elim_table *ep = reg_eliminate; 3312 3313#ifdef ELIMINABLE_REGS 3314 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3315 { 3316 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); 3317 ep->previous_offset = ep->offset = ep->initial_offset; 3318 } 3319#else 3320 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset); 3321 ep->previous_offset = ep->offset = ep->initial_offset; 3322#endif 3323 3324 num_not_at_initial_offset = 0; 3325} 3326 3327/* Subroutine of set_initial_label_offsets called via for_each_eh_label. */ 3328 3329static void 3330set_initial_eh_label_offset (rtx label) 3331{ 3332 set_label_offsets (label, NULL_RTX, 1); 3333} 3334 3335/* Initialize the known label offsets. 3336 Set a known offset for each forced label to be at the initial offset 3337 of each elimination. We do this because we assume that all 3338 computed jumps occur from a location where each elimination is 3339 at its initial offset. 3340 For all other labels, show that we don't know the offsets. */ 3341 3342static void 3343set_initial_label_offsets (void) 3344{ 3345 rtx x; 3346 memset (offsets_known_at, 0, num_labels); 3347 3348 for (x = forced_labels; x; x = XEXP (x, 1)) 3349 if (XEXP (x, 0)) 3350 set_label_offsets (XEXP (x, 0), NULL_RTX, 1); 3351 3352 for_each_eh_label (set_initial_eh_label_offset); 3353} 3354 3355/* Set all elimination offsets to the known values for the code label given 3356 by INSN. */ 3357 3358static void 3359set_offsets_for_label (rtx insn) 3360{ 3361 unsigned int i; 3362 int label_nr = CODE_LABEL_NUMBER (insn); 3363 struct elim_table *ep; 3364 3365 num_not_at_initial_offset = 0; 3366 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++) 3367 { 3368 ep->offset = ep->previous_offset 3369 = offsets_at[label_nr - first_label_num][i]; 3370 if (ep->can_eliminate && ep->offset != ep->initial_offset) 3371 num_not_at_initial_offset++; 3372 } 3373} 3374 3375/* See if anything that happened changes which eliminations are valid. 3376 For example, on the SPARC, whether or not the frame pointer can 3377 be eliminated can depend on what registers have been used. We need 3378 not check some conditions again (such as flag_omit_frame_pointer) 3379 since they can't have changed. */ 3380 3381static void 3382update_eliminables (HARD_REG_SET *pset) 3383{ 3384 int previous_frame_pointer_needed = frame_pointer_needed; 3385 struct elim_table *ep; 3386 3387 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3388 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) 3389#ifdef ELIMINABLE_REGS 3390 || ! CAN_ELIMINATE (ep->from, ep->to) 3391#endif 3392 ) 3393 ep->can_eliminate = 0; 3394 3395 /* Look for the case where we have discovered that we can't replace 3396 register A with register B and that means that we will now be 3397 trying to replace register A with register C. This means we can 3398 no longer replace register C with register B and we need to disable 3399 such an elimination, if it exists. This occurs often with A == ap, 3400 B == sp, and C == fp. */ 3401 3402 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3403 { 3404 struct elim_table *op; 3405 int new_to = -1; 3406 3407 if (! ep->can_eliminate && ep->can_eliminate_previous) 3408 { 3409 /* Find the current elimination for ep->from, if there is a 3410 new one. */ 3411 for (op = reg_eliminate; 3412 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) 3413 if (op->from == ep->from && op->can_eliminate) 3414 { 3415 new_to = op->to; 3416 break; 3417 } 3418 3419 /* See if there is an elimination of NEW_TO -> EP->TO. If so, 3420 disable it. */ 3421 for (op = reg_eliminate; 3422 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) 3423 if (op->from == new_to && op->to == ep->to) 3424 op->can_eliminate = 0; 3425 } 3426 } 3427 3428 /* See if any registers that we thought we could eliminate the previous 3429 time are no longer eliminable. If so, something has changed and we 3430 must spill the register. Also, recompute the number of eliminable 3431 registers and see if the frame pointer is needed; it is if there is 3432 no elimination of the frame pointer that we can perform. */ 3433 3434 frame_pointer_needed = 1; 3435 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3436 { 3437 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM 3438 && ep->to != HARD_FRAME_POINTER_REGNUM) 3439 frame_pointer_needed = 0; 3440 3441 if (! ep->can_eliminate && ep->can_eliminate_previous) 3442 { 3443 ep->can_eliminate_previous = 0; 3444 SET_HARD_REG_BIT (*pset, ep->from); 3445 num_eliminable--; 3446 } 3447 } 3448 3449 /* If we didn't need a frame pointer last time, but we do now, spill 3450 the hard frame pointer. */ 3451 if (frame_pointer_needed && ! previous_frame_pointer_needed) 3452 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM); 3453} 3454 3455/* Initialize the table of registers to eliminate. */ 3456 3457static void 3458init_elim_table (void) 3459{ 3460 struct elim_table *ep; 3461#ifdef ELIMINABLE_REGS 3462 const struct elim_table_1 *ep1; 3463#endif 3464 3465 if (!reg_eliminate) 3466 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS); 3467 3468 /* Does this function require a frame pointer? */ 3469 3470 frame_pointer_needed = (! flag_omit_frame_pointer 3471 /* ?? If EXIT_IGNORE_STACK is set, we will not save 3472 and restore sp for alloca. So we can't eliminate 3473 the frame pointer in that case. At some point, 3474 we should improve this by emitting the 3475 sp-adjusting insns for this case. */ 3476 || (current_function_calls_alloca 3477 && EXIT_IGNORE_STACK) 3478 || FRAME_POINTER_REQUIRED); 3479 3480 num_eliminable = 0; 3481 3482#ifdef ELIMINABLE_REGS 3483 for (ep = reg_eliminate, ep1 = reg_eliminate_1; 3484 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) 3485 { 3486 ep->from = ep1->from; 3487 ep->to = ep1->to; 3488 ep->can_eliminate = ep->can_eliminate_previous 3489 = (CAN_ELIMINATE (ep->from, ep->to) 3490 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed)); 3491 } 3492#else 3493 reg_eliminate[0].from = reg_eliminate_1[0].from; 3494 reg_eliminate[0].to = reg_eliminate_1[0].to; 3495 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous 3496 = ! frame_pointer_needed; 3497#endif 3498 3499 /* Count the number of eliminable registers and build the FROM and TO 3500 REG rtx's. Note that code in gen_rtx will cause, e.g., 3501 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. 3502 We depend on this. */ 3503 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3504 { 3505 num_eliminable += ep->can_eliminate; 3506 ep->from_rtx = gen_rtx_REG (Pmode, ep->from); 3507 ep->to_rtx = gen_rtx_REG (Pmode, ep->to); 3508 } 3509} 3510 3511/* Kick all pseudos out of hard register REGNO. 3512 3513 If CANT_ELIMINATE is nonzero, it means that we are doing this spill 3514 because we found we can't eliminate some register. In the case, no pseudos 3515 are allowed to be in the register, even if they are only in a block that 3516 doesn't require spill registers, unlike the case when we are spilling this 3517 hard reg to produce another spill register. 3518 3519 Return nonzero if any pseudos needed to be kicked out. */ 3520 3521static void 3522spill_hard_reg (unsigned int regno, int cant_eliminate) 3523{ 3524 int i; 3525 3526 if (cant_eliminate) 3527 { 3528 SET_HARD_REG_BIT (bad_spill_regs_global, regno); 3529 regs_ever_live[regno] = 1; 3530 } 3531 3532 /* Spill every pseudo reg that was allocated to this reg 3533 or to something that overlaps this reg. */ 3534 3535 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 3536 if (reg_renumber[i] >= 0 3537 && (unsigned int) reg_renumber[i] <= regno 3538 && ((unsigned int) reg_renumber[i] 3539 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i], 3540 PSEUDO_REGNO_MODE (i)) 3541 > regno)) 3542 SET_REGNO_REG_SET (&spilled_pseudos, i); 3543} 3544 3545/* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET 3546 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */ 3547 3548static void 3549ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2) 3550{ 3551 IOR_HARD_REG_SET (*set1, *set2); 3552} 3553 3554/* After find_reload_regs has been run for all insn that need reloads, 3555 and/or spill_hard_regs was called, this function is used to actually 3556 spill pseudo registers and try to reallocate them. It also sets up the 3557 spill_regs array for use by choose_reload_regs. */ 3558 3559static int 3560finish_spills (int global) 3561{ 3562 struct insn_chain *chain; 3563 int something_changed = 0; 3564 int i; 3565 3566 /* Build the spill_regs array for the function. */ 3567 /* If there are some registers still to eliminate and one of the spill regs 3568 wasn't ever used before, additional stack space may have to be 3569 allocated to store this register. Thus, we may have changed the offset 3570 between the stack and frame pointers, so mark that something has changed. 3571 3572 One might think that we need only set VAL to 1 if this is a call-used 3573 register. However, the set of registers that must be saved by the 3574 prologue is not identical to the call-used set. For example, the 3575 register used by the call insn for the return PC is a call-used register, 3576 but must be saved by the prologue. */ 3577 3578 n_spills = 0; 3579 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3580 if (TEST_HARD_REG_BIT (used_spill_regs, i)) 3581 { 3582 spill_reg_order[i] = n_spills; 3583 spill_regs[n_spills++] = i; 3584 if (num_eliminable && ! regs_ever_live[i]) 3585 something_changed = 1; 3586 regs_ever_live[i] = 1; 3587 } 3588 else 3589 spill_reg_order[i] = -1; 3590 3591 EXECUTE_IF_SET_IN_REG_SET 3592 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, 3593 { 3594 /* Record the current hard register the pseudo is allocated to in 3595 pseudo_previous_regs so we avoid reallocating it to the same 3596 hard reg in a later pass. */ 3597 if (reg_renumber[i] < 0) 3598 abort (); 3599 3600 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]); 3601 /* Mark it as no longer having a hard register home. */ 3602 reg_renumber[i] = -1; 3603 /* We will need to scan everything again. */ 3604 something_changed = 1; 3605 }); 3606 3607 /* Retry global register allocation if possible. */ 3608 if (global) 3609 { 3610 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET)); 3611 /* For every insn that needs reloads, set the registers used as spill 3612 regs in pseudo_forbidden_regs for every pseudo live across the 3613 insn. */ 3614 for (chain = insns_need_reload; chain; chain = chain->next_need_reload) 3615 { 3616 EXECUTE_IF_SET_IN_REG_SET 3617 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, 3618 { 3619 ior_hard_reg_set (pseudo_forbidden_regs + i, 3620 &chain->used_spill_regs); 3621 }); 3622 EXECUTE_IF_SET_IN_REG_SET 3623 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, 3624 { 3625 ior_hard_reg_set (pseudo_forbidden_regs + i, 3626 &chain->used_spill_regs); 3627 }); 3628 } 3629 3630 /* Retry allocating the spilled pseudos. For each reg, merge the 3631 various reg sets that indicate which hard regs can't be used, 3632 and call retry_global_alloc. 3633 We change spill_pseudos here to only contain pseudos that did not 3634 get a new hard register. */ 3635 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 3636 if (reg_old_renumber[i] != reg_renumber[i]) 3637 { 3638 HARD_REG_SET forbidden; 3639 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global); 3640 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]); 3641 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]); 3642 retry_global_alloc (i, forbidden); 3643 if (reg_renumber[i] >= 0) 3644 CLEAR_REGNO_REG_SET (&spilled_pseudos, i); 3645 } 3646 } 3647 3648 /* Fix up the register information in the insn chain. 3649 This involves deleting those of the spilled pseudos which did not get 3650 a new hard register home from the live_{before,after} sets. */ 3651 for (chain = reload_insn_chain; chain; chain = chain->next) 3652 { 3653 HARD_REG_SET used_by_pseudos; 3654 HARD_REG_SET used_by_pseudos2; 3655 3656 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos); 3657 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos); 3658 3659 /* Mark any unallocated hard regs as available for spills. That 3660 makes inheritance work somewhat better. */ 3661 if (chain->need_reload) 3662 { 3663 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); 3664 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); 3665 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2); 3666 3667 /* Save the old value for the sanity test below. */ 3668 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs); 3669 3670 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout); 3671 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set); 3672 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos); 3673 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs); 3674 3675 /* Make sure we only enlarge the set. */ 3676 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok); 3677 abort (); 3678 ok:; 3679 } 3680 } 3681 3682 /* Let alter_reg modify the reg rtx's for the modified pseudos. */ 3683 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 3684 { 3685 int regno = reg_renumber[i]; 3686 if (reg_old_renumber[i] == regno) 3687 continue; 3688 3689 alter_reg (i, reg_old_renumber[i]); 3690 reg_old_renumber[i] = regno; 3691 if (rtl_dump_file) 3692 { 3693 if (regno == -1) 3694 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i); 3695 else 3696 fprintf (rtl_dump_file, " Register %d now in %d.\n\n", 3697 i, reg_renumber[i]); 3698 } 3699 } 3700 3701 return something_changed; 3702} 3703 3704/* Find all paradoxical subregs within X and update reg_max_ref_width. 3705 Also mark any hard registers used to store user variables as 3706 forbidden from being used for spill registers. */ 3707 3708static void 3709scan_paradoxical_subregs (rtx x) 3710{ 3711 int i; 3712 const char *fmt; 3713 enum rtx_code code = GET_CODE (x); 3714 3715 switch (code) 3716 { 3717 case REG: 3718#if 0 3719 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER 3720 && REG_USERVAR_P (x)) 3721 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x)); 3722#endif 3723 return; 3724 3725 case CONST_INT: 3726 case CONST: 3727 case SYMBOL_REF: 3728 case LABEL_REF: 3729 case CONST_DOUBLE: 3730 case CONST_VECTOR: /* shouldn't happen, but just in case. */ 3731 case CC0: 3732 case PC: 3733 case USE: 3734 case CLOBBER: 3735 return; 3736 3737 case SUBREG: 3738 if (GET_CODE (SUBREG_REG (x)) == REG 3739 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 3740 reg_max_ref_width[REGNO (SUBREG_REG (x))] 3741 = GET_MODE_SIZE (GET_MODE (x)); 3742 return; 3743 3744 default: 3745 break; 3746 } 3747 3748 fmt = GET_RTX_FORMAT (code); 3749 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 3750 { 3751 if (fmt[i] == 'e') 3752 scan_paradoxical_subregs (XEXP (x, i)); 3753 else if (fmt[i] == 'E') 3754 { 3755 int j; 3756 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3757 scan_paradoxical_subregs (XVECEXP (x, i, j)); 3758 } 3759 } 3760} 3761 3762/* Reload pseudo-registers into hard regs around each insn as needed. 3763 Additional register load insns are output before the insn that needs it 3764 and perhaps store insns after insns that modify the reloaded pseudo reg. 3765 3766 reg_last_reload_reg and reg_reloaded_contents keep track of 3767 which registers are already available in reload registers. 3768 We update these for the reloads that we perform, 3769 as the insns are scanned. */ 3770 3771static void 3772reload_as_needed (int live_known) 3773{ 3774 struct insn_chain *chain; 3775#if defined (AUTO_INC_DEC) 3776 int i; 3777#endif 3778 rtx x; 3779 3780 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx); 3781 memset (spill_reg_store, 0, sizeof spill_reg_store); 3782 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx)); 3783 reg_has_output_reload = xmalloc (max_regno); 3784 CLEAR_HARD_REG_SET (reg_reloaded_valid); 3785 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered); 3786 3787 set_initial_elim_offsets (); 3788 3789 for (chain = reload_insn_chain; chain; chain = chain->next) 3790 { 3791 rtx prev = 0; 3792 rtx insn = chain->insn; 3793 rtx old_next = NEXT_INSN (insn); 3794 3795 /* If we pass a label, copy the offsets from the label information 3796 into the current offsets of each elimination. */ 3797 if (GET_CODE (insn) == CODE_LABEL) 3798 set_offsets_for_label (insn); 3799 3800 else if (INSN_P (insn)) 3801 { 3802 rtx oldpat = copy_rtx (PATTERN (insn)); 3803 3804 /* If this is a USE and CLOBBER of a MEM, ensure that any 3805 references to eliminable registers have been removed. */ 3806 3807 if ((GET_CODE (PATTERN (insn)) == USE 3808 || GET_CODE (PATTERN (insn)) == CLOBBER) 3809 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM) 3810 XEXP (XEXP (PATTERN (insn), 0), 0) 3811 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), 3812 GET_MODE (XEXP (PATTERN (insn), 0)), 3813 NULL_RTX); 3814 3815 /* If we need to do register elimination processing, do so. 3816 This might delete the insn, in which case we are done. */ 3817 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim) 3818 { 3819 eliminate_regs_in_insn (insn, 1); 3820 if (GET_CODE (insn) == NOTE) 3821 { 3822 update_eliminable_offsets (); 3823 continue; 3824 } 3825 } 3826 3827 /* If need_elim is nonzero but need_reload is zero, one might think 3828 that we could simply set n_reloads to 0. However, find_reloads 3829 could have done some manipulation of the insn (such as swapping 3830 commutative operands), and these manipulations are lost during 3831 the first pass for every insn that needs register elimination. 3832 So the actions of find_reloads must be redone here. */ 3833 3834 if (! chain->need_elim && ! chain->need_reload 3835 && ! chain->need_operand_change) 3836 n_reloads = 0; 3837 /* First find the pseudo regs that must be reloaded for this insn. 3838 This info is returned in the tables reload_... (see reload.h). 3839 Also modify the body of INSN by substituting RELOAD 3840 rtx's for those pseudo regs. */ 3841 else 3842 { 3843 memset (reg_has_output_reload, 0, max_regno); 3844 CLEAR_HARD_REG_SET (reg_is_output_reload); 3845 3846 find_reloads (insn, 1, spill_indirect_levels, live_known, 3847 spill_reg_order); 3848 } 3849 3850 if (n_reloads > 0) 3851 { 3852 rtx next = NEXT_INSN (insn); 3853 rtx p; 3854 3855 prev = PREV_INSN (insn); 3856 3857 /* Now compute which reload regs to reload them into. Perhaps 3858 reusing reload regs from previous insns, or else output 3859 load insns to reload them. Maybe output store insns too. 3860 Record the choices of reload reg in reload_reg_rtx. */ 3861 choose_reload_regs (chain); 3862 3863 /* Merge any reloads that we didn't combine for fear of 3864 increasing the number of spill registers needed but now 3865 discover can be safely merged. */ 3866 if (SMALL_REGISTER_CLASSES) 3867 merge_assigned_reloads (insn); 3868 3869 /* Generate the insns to reload operands into or out of 3870 their reload regs. */ 3871 emit_reload_insns (chain); 3872 3873 /* Substitute the chosen reload regs from reload_reg_rtx 3874 into the insn's body (or perhaps into the bodies of other 3875 load and store insn that we just made for reloading 3876 and that we moved the structure into). */ 3877 subst_reloads (insn); 3878 3879 /* If this was an ASM, make sure that all the reload insns 3880 we have generated are valid. If not, give an error 3881 and delete them. */ 3882 3883 if (asm_noperands (PATTERN (insn)) >= 0) 3884 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) 3885 if (p != insn && INSN_P (p) 3886 && GET_CODE (PATTERN (p)) != USE 3887 && (recog_memoized (p) < 0 3888 || (extract_insn (p), ! constrain_operands (1)))) 3889 { 3890 error_for_asm (insn, 3891 "`asm' operand requires impossible reload"); 3892 delete_insn (p); 3893 } 3894 } 3895 3896 if (num_eliminable && chain->need_elim) 3897 update_eliminable_offsets (); 3898 3899 /* Any previously reloaded spilled pseudo reg, stored in this insn, 3900 is no longer validly lying around to save a future reload. 3901 Note that this does not detect pseudos that were reloaded 3902 for this insn in order to be stored in 3903 (obeying register constraints). That is correct; such reload 3904 registers ARE still valid. */ 3905 note_stores (oldpat, forget_old_reloads_1, NULL); 3906 3907 /* There may have been CLOBBER insns placed after INSN. So scan 3908 between INSN and NEXT and use them to forget old reloads. */ 3909 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x)) 3910 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER) 3911 note_stores (PATTERN (x), forget_old_reloads_1, NULL); 3912 3913#ifdef AUTO_INC_DEC 3914 /* Likewise for regs altered by auto-increment in this insn. 3915 REG_INC notes have been changed by reloading: 3916 find_reloads_address_1 records substitutions for them, 3917 which have been performed by subst_reloads above. */ 3918 for (i = n_reloads - 1; i >= 0; i--) 3919 { 3920 rtx in_reg = rld[i].in_reg; 3921 if (in_reg) 3922 { 3923 enum rtx_code code = GET_CODE (in_reg); 3924 /* PRE_INC / PRE_DEC will have the reload register ending up 3925 with the same value as the stack slot, but that doesn't 3926 hold true for POST_INC / POST_DEC. Either we have to 3927 convert the memory access to a true POST_INC / POST_DEC, 3928 or we can't use the reload register for inheritance. */ 3929 if ((code == POST_INC || code == POST_DEC) 3930 && TEST_HARD_REG_BIT (reg_reloaded_valid, 3931 REGNO (rld[i].reg_rtx)) 3932 /* Make sure it is the inc/dec pseudo, and not 3933 some other (e.g. output operand) pseudo. */ 3934 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)] 3935 == REGNO (XEXP (in_reg, 0)))) 3936 3937 { 3938 rtx reload_reg = rld[i].reg_rtx; 3939 enum machine_mode mode = GET_MODE (reload_reg); 3940 int n = 0; 3941 rtx p; 3942 3943 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p)) 3944 { 3945 /* We really want to ignore REG_INC notes here, so 3946 use PATTERN (p) as argument to reg_set_p . */ 3947 if (reg_set_p (reload_reg, PATTERN (p))) 3948 break; 3949 n = count_occurrences (PATTERN (p), reload_reg, 0); 3950 if (! n) 3951 continue; 3952 if (n == 1) 3953 { 3954 n = validate_replace_rtx (reload_reg, 3955 gen_rtx (code, mode, 3956 reload_reg), 3957 p); 3958 3959 /* We must also verify that the constraints 3960 are met after the replacement. */ 3961 extract_insn (p); 3962 if (n) 3963 n = constrain_operands (1); 3964 else 3965 break; 3966 3967 /* If the constraints were not met, then 3968 undo the replacement. */ 3969 if (!n) 3970 { 3971 validate_replace_rtx (gen_rtx (code, mode, 3972 reload_reg), 3973 reload_reg, p); 3974 break; 3975 } 3976 3977 } 3978 break; 3979 } 3980 if (n == 1) 3981 { 3982 REG_NOTES (p) 3983 = gen_rtx_EXPR_LIST (REG_INC, reload_reg, 3984 REG_NOTES (p)); 3985 /* Mark this as having an output reload so that the 3986 REG_INC processing code below won't invalidate 3987 the reload for inheritance. */ 3988 SET_HARD_REG_BIT (reg_is_output_reload, 3989 REGNO (reload_reg)); 3990 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; 3991 } 3992 else 3993 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX, 3994 NULL); 3995 } 3996 else if ((code == PRE_INC || code == PRE_DEC) 3997 && TEST_HARD_REG_BIT (reg_reloaded_valid, 3998 REGNO (rld[i].reg_rtx)) 3999 /* Make sure it is the inc/dec pseudo, and not 4000 some other (e.g. output operand) pseudo. */ 4001 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)] 4002 == REGNO (XEXP (in_reg, 0)))) 4003 { 4004 SET_HARD_REG_BIT (reg_is_output_reload, 4005 REGNO (rld[i].reg_rtx)); 4006 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; 4007 } 4008 } 4009 } 4010 /* If a pseudo that got a hard register is auto-incremented, 4011 we must purge records of copying it into pseudos without 4012 hard registers. */ 4013 for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) 4014 if (REG_NOTE_KIND (x) == REG_INC) 4015 { 4016 /* See if this pseudo reg was reloaded in this insn. 4017 If so, its last-reload info is still valid 4018 because it is based on this insn's reload. */ 4019 for (i = 0; i < n_reloads; i++) 4020 if (rld[i].out == XEXP (x, 0)) 4021 break; 4022 4023 if (i == n_reloads) 4024 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL); 4025 } 4026#endif 4027 } 4028 /* A reload reg's contents are unknown after a label. */ 4029 if (GET_CODE (insn) == CODE_LABEL) 4030 CLEAR_HARD_REG_SET (reg_reloaded_valid); 4031 4032 /* Don't assume a reload reg is still good after a call insn 4033 if it is a call-used reg, or if it contains a value that will 4034 be partially clobbered by the call. */ 4035 else if (GET_CODE (insn) == CALL_INSN) 4036 { 4037 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set); 4038 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered); 4039 } 4040 } 4041 4042 /* Clean up. */ 4043 free (reg_last_reload_reg); 4044 free (reg_has_output_reload); 4045} 4046 4047/* Discard all record of any value reloaded from X, 4048 or reloaded in X from someplace else; 4049 unless X is an output reload reg of the current insn. 4050 4051 X may be a hard reg (the reload reg) 4052 or it may be a pseudo reg that was reloaded from. */ 4053 4054static void 4055forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED, 4056 void *data ATTRIBUTE_UNUSED) 4057{ 4058 unsigned int regno; 4059 unsigned int nr; 4060 4061 /* note_stores does give us subregs of hard regs, 4062 subreg_regno_offset will abort if it is not a hard reg. */ 4063 while (GET_CODE (x) == SUBREG) 4064 { 4065 /* We ignore the subreg offset when calculating the regno, 4066 because we are using the entire underlying hard register 4067 below. */ 4068 x = SUBREG_REG (x); 4069 } 4070 4071 if (GET_CODE (x) != REG) 4072 return; 4073 4074 regno = REGNO (x); 4075 4076 if (regno >= FIRST_PSEUDO_REGISTER) 4077 nr = 1; 4078 else 4079 { 4080 unsigned int i; 4081 4082 nr = HARD_REGNO_NREGS (regno, GET_MODE (x)); 4083 /* Storing into a spilled-reg invalidates its contents. 4084 This can happen if a block-local pseudo is allocated to that reg 4085 and it wasn't spilled because this block's total need is 0. 4086 Then some insn might have an optional reload and use this reg. */ 4087 for (i = 0; i < nr; i++) 4088 /* But don't do this if the reg actually serves as an output 4089 reload reg in the current instruction. */ 4090 if (n_reloads == 0 4091 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) 4092 { 4093 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); 4094 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i); 4095 spill_reg_store[regno + i] = 0; 4096 } 4097 } 4098 4099 /* Since value of X has changed, 4100 forget any value previously copied from it. */ 4101 4102 while (nr-- > 0) 4103 /* But don't forget a copy if this is the output reload 4104 that establishes the copy's validity. */ 4105 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0) 4106 reg_last_reload_reg[regno + nr] = 0; 4107} 4108 4109/* The following HARD_REG_SETs indicate when each hard register is 4110 used for a reload of various parts of the current insn. */ 4111 4112/* If reg is unavailable for all reloads. */ 4113static HARD_REG_SET reload_reg_unavailable; 4114/* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ 4115static HARD_REG_SET reload_reg_used; 4116/* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ 4117static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; 4118/* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ 4119static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; 4120/* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ 4121static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; 4122/* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ 4123static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; 4124/* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ 4125static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; 4126/* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ 4127static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; 4128/* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ 4129static HARD_REG_SET reload_reg_used_in_op_addr; 4130/* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ 4131static HARD_REG_SET reload_reg_used_in_op_addr_reload; 4132/* If reg is in use for a RELOAD_FOR_INSN reload. */ 4133static HARD_REG_SET reload_reg_used_in_insn; 4134/* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ 4135static HARD_REG_SET reload_reg_used_in_other_addr; 4136 4137/* If reg is in use as a reload reg for any sort of reload. */ 4138static HARD_REG_SET reload_reg_used_at_all; 4139 4140/* If reg is use as an inherited reload. We just mark the first register 4141 in the group. */ 4142static HARD_REG_SET reload_reg_used_for_inherit; 4143 4144/* Records which hard regs are used in any way, either as explicit use or 4145 by being allocated to a pseudo during any point of the current insn. */ 4146static HARD_REG_SET reg_used_in_insn; 4147 4148/* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and 4149 TYPE. MODE is used to indicate how many consecutive regs are 4150 actually used. */ 4151 4152static void 4153mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type, 4154 enum machine_mode mode) 4155{ 4156 unsigned int nregs = HARD_REGNO_NREGS (regno, mode); 4157 unsigned int i; 4158 4159 for (i = regno; i < nregs + regno; i++) 4160 { 4161 switch (type) 4162 { 4163 case RELOAD_OTHER: 4164 SET_HARD_REG_BIT (reload_reg_used, i); 4165 break; 4166 4167 case RELOAD_FOR_INPUT_ADDRESS: 4168 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); 4169 break; 4170 4171 case RELOAD_FOR_INPADDR_ADDRESS: 4172 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); 4173 break; 4174 4175 case RELOAD_FOR_OUTPUT_ADDRESS: 4176 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); 4177 break; 4178 4179 case RELOAD_FOR_OUTADDR_ADDRESS: 4180 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); 4181 break; 4182 4183 case RELOAD_FOR_OPERAND_ADDRESS: 4184 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); 4185 break; 4186 4187 case RELOAD_FOR_OPADDR_ADDR: 4188 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); 4189 break; 4190 4191 case RELOAD_FOR_OTHER_ADDRESS: 4192 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); 4193 break; 4194 4195 case RELOAD_FOR_INPUT: 4196 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); 4197 break; 4198 4199 case RELOAD_FOR_OUTPUT: 4200 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); 4201 break; 4202 4203 case RELOAD_FOR_INSN: 4204 SET_HARD_REG_BIT (reload_reg_used_in_insn, i); 4205 break; 4206 } 4207 4208 SET_HARD_REG_BIT (reload_reg_used_at_all, i); 4209 } 4210} 4211 4212/* Similarly, but show REGNO is no longer in use for a reload. */ 4213 4214static void 4215clear_reload_reg_in_use (unsigned int regno, int opnum, 4216 enum reload_type type, enum machine_mode mode) 4217{ 4218 unsigned int nregs = HARD_REGNO_NREGS (regno, mode); 4219 unsigned int start_regno, end_regno, r; 4220 int i; 4221 /* A complication is that for some reload types, inheritance might 4222 allow multiple reloads of the same types to share a reload register. 4223 We set check_opnum if we have to check only reloads with the same 4224 operand number, and check_any if we have to check all reloads. */ 4225 int check_opnum = 0; 4226 int check_any = 0; 4227 HARD_REG_SET *used_in_set; 4228 4229 switch (type) 4230 { 4231 case RELOAD_OTHER: 4232 used_in_set = &reload_reg_used; 4233 break; 4234 4235 case RELOAD_FOR_INPUT_ADDRESS: 4236 used_in_set = &reload_reg_used_in_input_addr[opnum]; 4237 break; 4238 4239 case RELOAD_FOR_INPADDR_ADDRESS: 4240 check_opnum = 1; 4241 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum]; 4242 break; 4243 4244 case RELOAD_FOR_OUTPUT_ADDRESS: 4245 used_in_set = &reload_reg_used_in_output_addr[opnum]; 4246 break; 4247 4248 case RELOAD_FOR_OUTADDR_ADDRESS: 4249 check_opnum = 1; 4250 used_in_set = &reload_reg_used_in_outaddr_addr[opnum]; 4251 break; 4252 4253 case RELOAD_FOR_OPERAND_ADDRESS: 4254 used_in_set = &reload_reg_used_in_op_addr; 4255 break; 4256 4257 case RELOAD_FOR_OPADDR_ADDR: 4258 check_any = 1; 4259 used_in_set = &reload_reg_used_in_op_addr_reload; 4260 break; 4261 4262 case RELOAD_FOR_OTHER_ADDRESS: 4263 used_in_set = &reload_reg_used_in_other_addr; 4264 check_any = 1; 4265 break; 4266 4267 case RELOAD_FOR_INPUT: 4268 used_in_set = &reload_reg_used_in_input[opnum]; 4269 break; 4270 4271 case RELOAD_FOR_OUTPUT: 4272 used_in_set = &reload_reg_used_in_output[opnum]; 4273 break; 4274 4275 case RELOAD_FOR_INSN: 4276 used_in_set = &reload_reg_used_in_insn; 4277 break; 4278 default: 4279 abort (); 4280 } 4281 /* We resolve conflicts with remaining reloads of the same type by 4282 excluding the intervals of reload registers by them from the 4283 interval of freed reload registers. Since we only keep track of 4284 one set of interval bounds, we might have to exclude somewhat 4285 more than what would be necessary if we used a HARD_REG_SET here. 4286 But this should only happen very infrequently, so there should 4287 be no reason to worry about it. */ 4288 4289 start_regno = regno; 4290 end_regno = regno + nregs; 4291 if (check_opnum || check_any) 4292 { 4293 for (i = n_reloads - 1; i >= 0; i--) 4294 { 4295 if (rld[i].when_needed == type 4296 && (check_any || rld[i].opnum == opnum) 4297 && rld[i].reg_rtx) 4298 { 4299 unsigned int conflict_start = true_regnum (rld[i].reg_rtx); 4300 unsigned int conflict_end 4301 = (conflict_start 4302 + HARD_REGNO_NREGS (conflict_start, rld[i].mode)); 4303 4304 /* If there is an overlap with the first to-be-freed register, 4305 adjust the interval start. */ 4306 if (conflict_start <= start_regno && conflict_end > start_regno) 4307 start_regno = conflict_end; 4308 /* Otherwise, if there is a conflict with one of the other 4309 to-be-freed registers, adjust the interval end. */ 4310 if (conflict_start > start_regno && conflict_start < end_regno) 4311 end_regno = conflict_start; 4312 } 4313 } 4314 } 4315 4316 for (r = start_regno; r < end_regno; r++) 4317 CLEAR_HARD_REG_BIT (*used_in_set, r); 4318} 4319 4320/* 1 if reg REGNO is free as a reload reg for a reload of the sort 4321 specified by OPNUM and TYPE. */ 4322 4323static int 4324reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type) 4325{ 4326 int i; 4327 4328 /* In use for a RELOAD_OTHER means it's not available for anything. */ 4329 if (TEST_HARD_REG_BIT (reload_reg_used, regno) 4330 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) 4331 return 0; 4332 4333 switch (type) 4334 { 4335 case RELOAD_OTHER: 4336 /* In use for anything means we can't use it for RELOAD_OTHER. */ 4337 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) 4338 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 4339 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno) 4340 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) 4341 return 0; 4342 4343 for (i = 0; i < reload_n_operands; i++) 4344 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4345 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 4346 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4347 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4348 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) 4349 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4350 return 0; 4351 4352 return 1; 4353 4354 case RELOAD_FOR_INPUT: 4355 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4356 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) 4357 return 0; 4358 4359 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) 4360 return 0; 4361 4362 /* If it is used for some other input, can't use it. */ 4363 for (i = 0; i < reload_n_operands; i++) 4364 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4365 return 0; 4366 4367 /* If it is used in a later operand's address, can't use it. */ 4368 for (i = opnum + 1; i < reload_n_operands; i++) 4369 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4370 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) 4371 return 0; 4372 4373 return 1; 4374 4375 case RELOAD_FOR_INPUT_ADDRESS: 4376 /* Can't use a register if it is used for an input address for this 4377 operand or used as an input in an earlier one. */ 4378 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) 4379 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) 4380 return 0; 4381 4382 for (i = 0; i < opnum; i++) 4383 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4384 return 0; 4385 4386 return 1; 4387 4388 case RELOAD_FOR_INPADDR_ADDRESS: 4389 /* Can't use a register if it is used for an input address 4390 for this operand or used as an input in an earlier 4391 one. */ 4392 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) 4393 return 0; 4394 4395 for (i = 0; i < opnum; i++) 4396 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4397 return 0; 4398 4399 return 1; 4400 4401 case RELOAD_FOR_OUTPUT_ADDRESS: 4402 /* Can't use a register if it is used for an output address for this 4403 operand or used as an output in this or a later operand. Note 4404 that multiple output operands are emitted in reverse order, so 4405 the conflicting ones are those with lower indices. */ 4406 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) 4407 return 0; 4408 4409 for (i = 0; i <= opnum; i++) 4410 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4411 return 0; 4412 4413 return 1; 4414 4415 case RELOAD_FOR_OUTADDR_ADDRESS: 4416 /* Can't use a register if it is used for an output address 4417 for this operand or used as an output in this or a 4418 later operand. Note that multiple output operands are 4419 emitted in reverse order, so the conflicting ones are 4420 those with lower indices. */ 4421 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) 4422 return 0; 4423 4424 for (i = 0; i <= opnum; i++) 4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4426 return 0; 4427 4428 return 1; 4429 4430 case RELOAD_FOR_OPERAND_ADDRESS: 4431 for (i = 0; i < reload_n_operands; i++) 4432 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4433 return 0; 4434 4435 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4436 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); 4437 4438 case RELOAD_FOR_OPADDR_ADDR: 4439 for (i = 0; i < reload_n_operands; i++) 4440 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4441 return 0; 4442 4443 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); 4444 4445 case RELOAD_FOR_OUTPUT: 4446 /* This cannot share a register with RELOAD_FOR_INSN reloads, other 4447 outputs, or an operand address for this or an earlier output. 4448 Note that multiple output operands are emitted in reverse order, 4449 so the conflicting ones are those with higher indices. */ 4450 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) 4451 return 0; 4452 4453 for (i = 0; i < reload_n_operands; i++) 4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4455 return 0; 4456 4457 for (i = opnum; i < reload_n_operands; i++) 4458 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4459 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) 4460 return 0; 4461 4462 return 1; 4463 4464 case RELOAD_FOR_INSN: 4465 for (i = 0; i < reload_n_operands; i++) 4466 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) 4467 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4468 return 0; 4469 4470 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4471 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); 4472 4473 case RELOAD_FOR_OTHER_ADDRESS: 4474 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); 4475 } 4476 abort (); 4477} 4478 4479/* Return 1 if the value in reload reg REGNO, as used by a reload 4480 needed for the part of the insn specified by OPNUM and TYPE, 4481 is still available in REGNO at the end of the insn. 4482 4483 We can assume that the reload reg was already tested for availability 4484 at the time it is needed, and we should not check this again, 4485 in case the reg has already been marked in use. */ 4486 4487static int 4488reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type) 4489{ 4490 int i; 4491 4492 switch (type) 4493 { 4494 case RELOAD_OTHER: 4495 /* Since a RELOAD_OTHER reload claims the reg for the entire insn, 4496 its value must reach the end. */ 4497 return 1; 4498 4499 /* If this use is for part of the insn, 4500 its value reaches if no subsequent part uses the same register. 4501 Just like the above function, don't try to do this with lots 4502 of fallthroughs. */ 4503 4504 case RELOAD_FOR_OTHER_ADDRESS: 4505 /* Here we check for everything else, since these don't conflict 4506 with anything else and everything comes later. */ 4507 4508 for (i = 0; i < reload_n_operands; i++) 4509 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4510 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4511 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) 4512 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4513 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 4514 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4515 return 0; 4516 4517 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 4518 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno) 4519 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4520 && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); 4521 4522 case RELOAD_FOR_INPUT_ADDRESS: 4523 case RELOAD_FOR_INPADDR_ADDRESS: 4524 /* Similar, except that we check only for this and subsequent inputs 4525 and the address of only subsequent inputs and we do not need 4526 to check for RELOAD_OTHER objects since they are known not to 4527 conflict. */ 4528 4529 for (i = opnum; i < reload_n_operands; i++) 4530 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4531 return 0; 4532 4533 for (i = opnum + 1; i < reload_n_operands; i++) 4534 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4535 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) 4536 return 0; 4537 4538 for (i = 0; i < reload_n_operands; i++) 4539 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4540 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4541 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4542 return 0; 4543 4544 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) 4545 return 0; 4546 4547 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 4548 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4549 && !TEST_HARD_REG_BIT (reload_reg_used, regno)); 4550 4551 case RELOAD_FOR_INPUT: 4552 /* Similar to input address, except we start at the next operand for 4553 both input and input address and we do not check for 4554 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these 4555 would conflict. */ 4556 4557 for (i = opnum + 1; i < reload_n_operands; i++) 4558 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4559 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 4560 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4561 return 0; 4562 4563 /* ... fall through ... */ 4564 4565 case RELOAD_FOR_OPERAND_ADDRESS: 4566 /* Check outputs and their addresses. */ 4567 4568 for (i = 0; i < reload_n_operands; i++) 4569 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4570 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4571 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4572 return 0; 4573 4574 return (!TEST_HARD_REG_BIT (reload_reg_used, regno)); 4575 4576 case RELOAD_FOR_OPADDR_ADDR: 4577 for (i = 0; i < reload_n_operands; i++) 4578 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4579 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4580 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4581 return 0; 4582 4583 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 4584 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4585 && !TEST_HARD_REG_BIT (reload_reg_used, regno)); 4586 4587 case RELOAD_FOR_INSN: 4588 /* These conflict with other outputs with RELOAD_OTHER. So 4589 we need only check for output addresses. */ 4590 4591 opnum = reload_n_operands; 4592 4593 /* ... fall through ... */ 4594 4595 case RELOAD_FOR_OUTPUT: 4596 case RELOAD_FOR_OUTPUT_ADDRESS: 4597 case RELOAD_FOR_OUTADDR_ADDRESS: 4598 /* We already know these can't conflict with a later output. So the 4599 only thing to check are later output addresses. 4600 Note that multiple output operands are emitted in reverse order, 4601 so the conflicting ones are those with lower indices. */ 4602 for (i = 0; i < opnum; i++) 4603 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4604 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) 4605 return 0; 4606 4607 return 1; 4608 } 4609 4610 abort (); 4611} 4612 4613/* Return 1 if the reloads denoted by R1 and R2 cannot share a register. 4614 Return 0 otherwise. 4615 4616 This function uses the same algorithm as reload_reg_free_p above. */ 4617 4618int 4619reloads_conflict (int r1, int r2) 4620{ 4621 enum reload_type r1_type = rld[r1].when_needed; 4622 enum reload_type r2_type = rld[r2].when_needed; 4623 int r1_opnum = rld[r1].opnum; 4624 int r2_opnum = rld[r2].opnum; 4625 4626 /* RELOAD_OTHER conflicts with everything. */ 4627 if (r2_type == RELOAD_OTHER) 4628 return 1; 4629 4630 /* Otherwise, check conflicts differently for each type. */ 4631 4632 switch (r1_type) 4633 { 4634 case RELOAD_FOR_INPUT: 4635 return (r2_type == RELOAD_FOR_INSN 4636 || r2_type == RELOAD_FOR_OPERAND_ADDRESS 4637 || r2_type == RELOAD_FOR_OPADDR_ADDR 4638 || r2_type == RELOAD_FOR_INPUT 4639 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS 4640 || r2_type == RELOAD_FOR_INPADDR_ADDRESS) 4641 && r2_opnum > r1_opnum)); 4642 4643 case RELOAD_FOR_INPUT_ADDRESS: 4644 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) 4645 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); 4646 4647 case RELOAD_FOR_INPADDR_ADDRESS: 4648 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) 4649 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); 4650 4651 case RELOAD_FOR_OUTPUT_ADDRESS: 4652 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) 4653 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); 4654 4655 case RELOAD_FOR_OUTADDR_ADDRESS: 4656 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) 4657 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); 4658 4659 case RELOAD_FOR_OPERAND_ADDRESS: 4660 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN 4661 || r2_type == RELOAD_FOR_OPERAND_ADDRESS); 4662 4663 case RELOAD_FOR_OPADDR_ADDR: 4664 return (r2_type == RELOAD_FOR_INPUT 4665 || r2_type == RELOAD_FOR_OPADDR_ADDR); 4666 4667 case RELOAD_FOR_OUTPUT: 4668 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT 4669 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS 4670 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) 4671 && r2_opnum >= r1_opnum)); 4672 4673 case RELOAD_FOR_INSN: 4674 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT 4675 || r2_type == RELOAD_FOR_INSN 4676 || r2_type == RELOAD_FOR_OPERAND_ADDRESS); 4677 4678 case RELOAD_FOR_OTHER_ADDRESS: 4679 return r2_type == RELOAD_FOR_OTHER_ADDRESS; 4680 4681 case RELOAD_OTHER: 4682 return 1; 4683 4684 default: 4685 abort (); 4686 } 4687} 4688 4689/* Indexed by reload number, 1 if incoming value 4690 inherited from previous insns. */ 4691char reload_inherited[MAX_RELOADS]; 4692 4693/* For an inherited reload, this is the insn the reload was inherited from, 4694 if we know it. Otherwise, this is 0. */ 4695rtx reload_inheritance_insn[MAX_RELOADS]; 4696 4697/* If nonzero, this is a place to get the value of the reload, 4698 rather than using reload_in. */ 4699rtx reload_override_in[MAX_RELOADS]; 4700 4701/* For each reload, the hard register number of the register used, 4702 or -1 if we did not need a register for this reload. */ 4703int reload_spill_index[MAX_RELOADS]; 4704 4705/* Subroutine of free_for_value_p, used to check a single register. 4706 START_REGNO is the starting regno of the full reload register 4707 (possibly comprising multiple hard registers) that we are considering. */ 4708 4709static int 4710reload_reg_free_for_value_p (int start_regno, int regno, int opnum, 4711 enum reload_type type, rtx value, rtx out, 4712 int reloadnum, int ignore_address_reloads) 4713{ 4714 int time1; 4715 /* Set if we see an input reload that must not share its reload register 4716 with any new earlyclobber, but might otherwise share the reload 4717 register with an output or input-output reload. */ 4718 int check_earlyclobber = 0; 4719 int i; 4720 int copy = 0; 4721 4722 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) 4723 return 0; 4724 4725 if (out == const0_rtx) 4726 { 4727 copy = 1; 4728 out = NULL_RTX; 4729 } 4730 4731 /* We use some pseudo 'time' value to check if the lifetimes of the 4732 new register use would overlap with the one of a previous reload 4733 that is not read-only or uses a different value. 4734 The 'time' used doesn't have to be linear in any shape or form, just 4735 monotonic. 4736 Some reload types use different 'buckets' for each operand. 4737 So there are MAX_RECOG_OPERANDS different time values for each 4738 such reload type. 4739 We compute TIME1 as the time when the register for the prospective 4740 new reload ceases to be live, and TIME2 for each existing 4741 reload as the time when that the reload register of that reload 4742 becomes live. 4743 Where there is little to be gained by exact lifetime calculations, 4744 we just make conservative assumptions, i.e. a longer lifetime; 4745 this is done in the 'default:' cases. */ 4746 switch (type) 4747 { 4748 case RELOAD_FOR_OTHER_ADDRESS: 4749 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */ 4750 time1 = copy ? 0 : 1; 4751 break; 4752 case RELOAD_OTHER: 4753 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5; 4754 break; 4755 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS, 4756 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , 4757 respectively, to the time values for these, we get distinct time 4758 values. To get distinct time values for each operand, we have to 4759 multiply opnum by at least three. We round that up to four because 4760 multiply by four is often cheaper. */ 4761 case RELOAD_FOR_INPADDR_ADDRESS: 4762 time1 = opnum * 4 + 2; 4763 break; 4764 case RELOAD_FOR_INPUT_ADDRESS: 4765 time1 = opnum * 4 + 3; 4766 break; 4767 case RELOAD_FOR_INPUT: 4768 /* All RELOAD_FOR_INPUT reloads remain live till the instruction 4769 executes (inclusive). */ 4770 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3; 4771 break; 4772 case RELOAD_FOR_OPADDR_ADDR: 4773 /* opnum * 4 + 4 4774 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ 4775 time1 = MAX_RECOG_OPERANDS * 4 + 1; 4776 break; 4777 case RELOAD_FOR_OPERAND_ADDRESS: 4778 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn 4779 is executed. */ 4780 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3; 4781 break; 4782 case RELOAD_FOR_OUTADDR_ADDRESS: 4783 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum; 4784 break; 4785 case RELOAD_FOR_OUTPUT_ADDRESS: 4786 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum; 4787 break; 4788 default: 4789 time1 = MAX_RECOG_OPERANDS * 5 + 5; 4790 } 4791 4792 for (i = 0; i < n_reloads; i++) 4793 { 4794 rtx reg = rld[i].reg_rtx; 4795 if (reg && GET_CODE (reg) == REG 4796 && ((unsigned) regno - true_regnum (reg) 4797 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1) 4798 && i != reloadnum) 4799 { 4800 rtx other_input = rld[i].in; 4801 4802 /* If the other reload loads the same input value, that 4803 will not cause a conflict only if it's loading it into 4804 the same register. */ 4805 if (true_regnum (reg) != start_regno) 4806 other_input = NULL_RTX; 4807 if (! other_input || ! rtx_equal_p (other_input, value) 4808 || rld[i].out || out) 4809 { 4810 int time2; 4811 switch (rld[i].when_needed) 4812 { 4813 case RELOAD_FOR_OTHER_ADDRESS: 4814 time2 = 0; 4815 break; 4816 case RELOAD_FOR_INPADDR_ADDRESS: 4817 /* find_reloads makes sure that a 4818 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used 4819 by at most one - the first - 4820 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the 4821 address reload is inherited, the address address reload 4822 goes away, so we can ignore this conflict. */ 4823 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1 4824 && ignore_address_reloads 4825 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression. 4826 Then the address address is still needed to store 4827 back the new address. */ 4828 && ! rld[reloadnum].out) 4829 continue; 4830 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its 4831 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS 4832 reloads go away. */ 4833 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum 4834 && ignore_address_reloads 4835 /* Unless we are reloading an auto_inc expression. */ 4836 && ! rld[reloadnum].out) 4837 continue; 4838 time2 = rld[i].opnum * 4 + 2; 4839 break; 4840 case RELOAD_FOR_INPUT_ADDRESS: 4841 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum 4842 && ignore_address_reloads 4843 && ! rld[reloadnum].out) 4844 continue; 4845 time2 = rld[i].opnum * 4 + 3; 4846 break; 4847 case RELOAD_FOR_INPUT: 4848 time2 = rld[i].opnum * 4 + 4; 4849 check_earlyclobber = 1; 4850 break; 4851 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4 4852 == MAX_RECOG_OPERAND * 4 */ 4853 case RELOAD_FOR_OPADDR_ADDR: 4854 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1 4855 && ignore_address_reloads 4856 && ! rld[reloadnum].out) 4857 continue; 4858 time2 = MAX_RECOG_OPERANDS * 4 + 1; 4859 break; 4860 case RELOAD_FOR_OPERAND_ADDRESS: 4861 time2 = MAX_RECOG_OPERANDS * 4 + 2; 4862 check_earlyclobber = 1; 4863 break; 4864 case RELOAD_FOR_INSN: 4865 time2 = MAX_RECOG_OPERANDS * 4 + 3; 4866 break; 4867 case RELOAD_FOR_OUTPUT: 4868 /* All RELOAD_FOR_OUTPUT reloads become live just after the 4869 instruction is executed. */ 4870 time2 = MAX_RECOG_OPERANDS * 4 + 4; 4871 break; 4872 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with 4873 the RELOAD_FOR_OUTPUT reloads, so assign it the same time 4874 value. */ 4875 case RELOAD_FOR_OUTADDR_ADDRESS: 4876 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1 4877 && ignore_address_reloads 4878 && ! rld[reloadnum].out) 4879 continue; 4880 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum; 4881 break; 4882 case RELOAD_FOR_OUTPUT_ADDRESS: 4883 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum; 4884 break; 4885 case RELOAD_OTHER: 4886 /* If there is no conflict in the input part, handle this 4887 like an output reload. */ 4888 if (! rld[i].in || rtx_equal_p (other_input, value)) 4889 { 4890 time2 = MAX_RECOG_OPERANDS * 4 + 4; 4891 /* Earlyclobbered outputs must conflict with inputs. */ 4892 if (earlyclobber_operand_p (rld[i].out)) 4893 time2 = MAX_RECOG_OPERANDS * 4 + 3; 4894 4895 break; 4896 } 4897 time2 = 1; 4898 /* RELOAD_OTHER might be live beyond instruction execution, 4899 but this is not obvious when we set time2 = 1. So check 4900 here if there might be a problem with the new reload 4901 clobbering the register used by the RELOAD_OTHER. */ 4902 if (out) 4903 return 0; 4904 break; 4905 default: 4906 return 0; 4907 } 4908 if ((time1 >= time2 4909 && (! rld[i].in || rld[i].out 4910 || ! rtx_equal_p (other_input, value))) 4911 || (out && rld[reloadnum].out_reg 4912 && time2 >= MAX_RECOG_OPERANDS * 4 + 3)) 4913 return 0; 4914 } 4915 } 4916 } 4917 4918 /* Earlyclobbered outputs must conflict with inputs. */ 4919 if (check_earlyclobber && out && earlyclobber_operand_p (out)) 4920 return 0; 4921 4922 return 1; 4923} 4924 4925/* Return 1 if the value in reload reg REGNO, as used by a reload 4926 needed for the part of the insn specified by OPNUM and TYPE, 4927 may be used to load VALUE into it. 4928 4929 MODE is the mode in which the register is used, this is needed to 4930 determine how many hard regs to test. 4931 4932 Other read-only reloads with the same value do not conflict 4933 unless OUT is nonzero and these other reloads have to live while 4934 output reloads live. 4935 If OUT is CONST0_RTX, this is a special case: it means that the 4936 test should not be for using register REGNO as reload register, but 4937 for copying from register REGNO into the reload register. 4938 4939 RELOADNUM is the number of the reload we want to load this value for; 4940 a reload does not conflict with itself. 4941 4942 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with 4943 reloads that load an address for the very reload we are considering. 4944 4945 The caller has to make sure that there is no conflict with the return 4946 register. */ 4947 4948static int 4949free_for_value_p (int regno, enum machine_mode mode, int opnum, 4950 enum reload_type type, rtx value, rtx out, int reloadnum, 4951 int ignore_address_reloads) 4952{ 4953 int nregs = HARD_REGNO_NREGS (regno, mode); 4954 while (nregs-- > 0) 4955 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type, 4956 value, out, reloadnum, 4957 ignore_address_reloads)) 4958 return 0; 4959 return 1; 4960} 4961 4962/* Determine whether the reload reg X overlaps any rtx'es used for 4963 overriding inheritance. Return nonzero if so. */ 4964 4965static int 4966conflicts_with_override (rtx x) 4967{ 4968 int i; 4969 for (i = 0; i < n_reloads; i++) 4970 if (reload_override_in[i] 4971 && reg_overlap_mentioned_p (x, reload_override_in[i])) 4972 return 1; 4973 return 0; 4974} 4975 4976/* Give an error message saying we failed to find a reload for INSN, 4977 and clear out reload R. */ 4978static void 4979failed_reload (rtx insn, int r) 4980{ 4981 if (asm_noperands (PATTERN (insn)) < 0) 4982 /* It's the compiler's fault. */ 4983 fatal_insn ("could not find a spill register", insn); 4984 4985 /* It's the user's fault; the operand's mode and constraint 4986 don't match. Disable this reload so we don't crash in final. */ 4987 error_for_asm (insn, 4988 "`asm' operand constraint incompatible with operand size"); 4989 rld[r].in = 0; 4990 rld[r].out = 0; 4991 rld[r].reg_rtx = 0; 4992 rld[r].optional = 1; 4993 rld[r].secondary_p = 1; 4994} 4995 4996/* I is the index in SPILL_REG_RTX of the reload register we are to allocate 4997 for reload R. If it's valid, get an rtx for it. Return nonzero if 4998 successful. */ 4999static int 5000set_reload_reg (int i, int r) 5001{ 5002 int regno; 5003 rtx reg = spill_reg_rtx[i]; 5004 5005 if (reg == 0 || GET_MODE (reg) != rld[r].mode) 5006 spill_reg_rtx[i] = reg 5007 = gen_rtx_REG (rld[r].mode, spill_regs[i]); 5008 5009 regno = true_regnum (reg); 5010 5011 /* Detect when the reload reg can't hold the reload mode. 5012 This used to be one `if', but Sequent compiler can't handle that. */ 5013 if (HARD_REGNO_MODE_OK (regno, rld[r].mode)) 5014 { 5015 enum machine_mode test_mode = VOIDmode; 5016 if (rld[r].in) 5017 test_mode = GET_MODE (rld[r].in); 5018 /* If rld[r].in has VOIDmode, it means we will load it 5019 in whatever mode the reload reg has: to wit, rld[r].mode. 5020 We have already tested that for validity. */ 5021 /* Aside from that, we need to test that the expressions 5022 to reload from or into have modes which are valid for this 5023 reload register. Otherwise the reload insns would be invalid. */ 5024 if (! (rld[r].in != 0 && test_mode != VOIDmode 5025 && ! HARD_REGNO_MODE_OK (regno, test_mode))) 5026 if (! (rld[r].out != 0 5027 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out)))) 5028 { 5029 /* The reg is OK. */ 5030 last_spill_reg = i; 5031 5032 /* Mark as in use for this insn the reload regs we use 5033 for this. */ 5034 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum, 5035 rld[r].when_needed, rld[r].mode); 5036 5037 rld[r].reg_rtx = reg; 5038 reload_spill_index[r] = spill_regs[i]; 5039 return 1; 5040 } 5041 } 5042 return 0; 5043} 5044 5045/* Find a spill register to use as a reload register for reload R. 5046 LAST_RELOAD is nonzero if this is the last reload for the insn being 5047 processed. 5048 5049 Set rld[R].reg_rtx to the register allocated. 5050 5051 We return 1 if successful, or 0 if we couldn't find a spill reg and 5052 we didn't change anything. */ 5053 5054static int 5055allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r, 5056 int last_reload) 5057{ 5058 int i, pass, count; 5059 5060 /* If we put this reload ahead, thinking it is a group, 5061 then insist on finding a group. Otherwise we can grab a 5062 reg that some other reload needs. 5063 (That can happen when we have a 68000 DATA_OR_FP_REG 5064 which is a group of data regs or one fp reg.) 5065 We need not be so restrictive if there are no more reloads 5066 for this insn. 5067 5068 ??? Really it would be nicer to have smarter handling 5069 for that kind of reg class, where a problem like this is normal. 5070 Perhaps those classes should be avoided for reloading 5071 by use of more alternatives. */ 5072 5073 int force_group = rld[r].nregs > 1 && ! last_reload; 5074 5075 /* If we want a single register and haven't yet found one, 5076 take any reg in the right class and not in use. 5077 If we want a consecutive group, here is where we look for it. 5078 5079 We use two passes so we can first look for reload regs to 5080 reuse, which are already in use for other reloads in this insn, 5081 and only then use additional registers. 5082 I think that maximizing reuse is needed to make sure we don't 5083 run out of reload regs. Suppose we have three reloads, and 5084 reloads A and B can share regs. These need two regs. 5085 Suppose A and B are given different regs. 5086 That leaves none for C. */ 5087 for (pass = 0; pass < 2; pass++) 5088 { 5089 /* I is the index in spill_regs. 5090 We advance it round-robin between insns to use all spill regs 5091 equally, so that inherited reloads have a chance 5092 of leapfrogging each other. */ 5093 5094 i = last_spill_reg; 5095 5096 for (count = 0; count < n_spills; count++) 5097 { 5098 int class = (int) rld[r].class; 5099 int regnum; 5100 5101 i++; 5102 if (i >= n_spills) 5103 i -= n_spills; 5104 regnum = spill_regs[i]; 5105 5106 if ((reload_reg_free_p (regnum, rld[r].opnum, 5107 rld[r].when_needed) 5108 || (rld[r].in 5109 /* We check reload_reg_used to make sure we 5110 don't clobber the return register. */ 5111 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum) 5112 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum, 5113 rld[r].when_needed, rld[r].in, 5114 rld[r].out, r, 1))) 5115 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum) 5116 && HARD_REGNO_MODE_OK (regnum, rld[r].mode) 5117 /* Look first for regs to share, then for unshared. But 5118 don't share regs used for inherited reloads; they are 5119 the ones we want to preserve. */ 5120 && (pass 5121 || (TEST_HARD_REG_BIT (reload_reg_used_at_all, 5122 regnum) 5123 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, 5124 regnum)))) 5125 { 5126 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode); 5127 /* Avoid the problem where spilling a GENERAL_OR_FP_REG 5128 (on 68000) got us two FP regs. If NR is 1, 5129 we would reject both of them. */ 5130 if (force_group) 5131 nr = rld[r].nregs; 5132 /* If we need only one reg, we have already won. */ 5133 if (nr == 1) 5134 { 5135 /* But reject a single reg if we demand a group. */ 5136 if (force_group) 5137 continue; 5138 break; 5139 } 5140 /* Otherwise check that as many consecutive regs as we need 5141 are available here. */ 5142 while (nr > 1) 5143 { 5144 int regno = regnum + nr - 1; 5145 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) 5146 && spill_reg_order[regno] >= 0 5147 && reload_reg_free_p (regno, rld[r].opnum, 5148 rld[r].when_needed))) 5149 break; 5150 nr--; 5151 } 5152 if (nr == 1) 5153 break; 5154 } 5155 } 5156 5157 /* If we found something on pass 1, omit pass 2. */ 5158 if (count < n_spills) 5159 break; 5160 } 5161 5162 /* We should have found a spill register by now. */ 5163 if (count >= n_spills) 5164 return 0; 5165 5166 /* I is the index in SPILL_REG_RTX of the reload register we are to 5167 allocate. Get an rtx for it and find its register number. */ 5168 5169 return set_reload_reg (i, r); 5170} 5171 5172/* Initialize all the tables needed to allocate reload registers. 5173 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX 5174 is the array we use to restore the reg_rtx field for every reload. */ 5175 5176static void 5177choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx) 5178{ 5179 int i; 5180 5181 for (i = 0; i < n_reloads; i++) 5182 rld[i].reg_rtx = save_reload_reg_rtx[i]; 5183 5184 memset (reload_inherited, 0, MAX_RELOADS); 5185 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx)); 5186 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx)); 5187 5188 CLEAR_HARD_REG_SET (reload_reg_used); 5189 CLEAR_HARD_REG_SET (reload_reg_used_at_all); 5190 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); 5191 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); 5192 CLEAR_HARD_REG_SET (reload_reg_used_in_insn); 5193 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); 5194 5195 CLEAR_HARD_REG_SET (reg_used_in_insn); 5196 { 5197 HARD_REG_SET tmp; 5198 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout); 5199 IOR_HARD_REG_SET (reg_used_in_insn, tmp); 5200 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set); 5201 IOR_HARD_REG_SET (reg_used_in_insn, tmp); 5202 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout); 5203 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set); 5204 } 5205 5206 for (i = 0; i < reload_n_operands; i++) 5207 { 5208 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); 5209 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); 5210 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); 5211 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); 5212 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); 5213 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); 5214 } 5215 5216 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs); 5217 5218 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); 5219 5220 for (i = 0; i < n_reloads; i++) 5221 /* If we have already decided to use a certain register, 5222 don't use it in another way. */ 5223 if (rld[i].reg_rtx) 5224 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum, 5225 rld[i].when_needed, rld[i].mode); 5226} 5227 5228/* Assign hard reg targets for the pseudo-registers we must reload 5229 into hard regs for this insn. 5230 Also output the instructions to copy them in and out of the hard regs. 5231 5232 For machines with register classes, we are responsible for 5233 finding a reload reg in the proper class. */ 5234 5235static void 5236choose_reload_regs (struct insn_chain *chain) 5237{ 5238 rtx insn = chain->insn; 5239 int i, j; 5240 unsigned int max_group_size = 1; 5241 enum reg_class group_class = NO_REGS; 5242 int pass, win, inheritance; 5243 5244 rtx save_reload_reg_rtx[MAX_RELOADS]; 5245 5246 /* In order to be certain of getting the registers we need, 5247 we must sort the reloads into order of increasing register class. 5248 Then our grabbing of reload registers will parallel the process 5249 that provided the reload registers. 5250 5251 Also note whether any of the reloads wants a consecutive group of regs. 5252 If so, record the maximum size of the group desired and what 5253 register class contains all the groups needed by this insn. */ 5254 5255 for (j = 0; j < n_reloads; j++) 5256 { 5257 reload_order[j] = j; 5258 reload_spill_index[j] = -1; 5259 5260 if (rld[j].nregs > 1) 5261 { 5262 max_group_size = MAX (rld[j].nregs, max_group_size); 5263 group_class 5264 = reg_class_superunion[(int) rld[j].class][(int) group_class]; 5265 } 5266 5267 save_reload_reg_rtx[j] = rld[j].reg_rtx; 5268 } 5269 5270 if (n_reloads > 1) 5271 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); 5272 5273 /* If -O, try first with inheritance, then turning it off. 5274 If not -O, don't do inheritance. 5275 Using inheritance when not optimizing leads to paradoxes 5276 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves 5277 because one side of the comparison might be inherited. */ 5278 win = 0; 5279 for (inheritance = optimize > 0; inheritance >= 0; inheritance--) 5280 { 5281 choose_reload_regs_init (chain, save_reload_reg_rtx); 5282 5283 /* Process the reloads in order of preference just found. 5284 Beyond this point, subregs can be found in reload_reg_rtx. 5285 5286 This used to look for an existing reloaded home for all of the 5287 reloads, and only then perform any new reloads. But that could lose 5288 if the reloads were done out of reg-class order because a later 5289 reload with a looser constraint might have an old home in a register 5290 needed by an earlier reload with a tighter constraint. 5291 5292 To solve this, we make two passes over the reloads, in the order 5293 described above. In the first pass we try to inherit a reload 5294 from a previous insn. If there is a later reload that needs a 5295 class that is a proper subset of the class being processed, we must 5296 also allocate a spill register during the first pass. 5297 5298 Then make a second pass over the reloads to allocate any reloads 5299 that haven't been given registers yet. */ 5300 5301 for (j = 0; j < n_reloads; j++) 5302 { 5303 int r = reload_order[j]; 5304 rtx search_equiv = NULL_RTX; 5305 5306 /* Ignore reloads that got marked inoperative. */ 5307 if (rld[r].out == 0 && rld[r].in == 0 5308 && ! rld[r].secondary_p) 5309 continue; 5310 5311 /* If find_reloads chose to use reload_in or reload_out as a reload 5312 register, we don't need to chose one. Otherwise, try even if it 5313 found one since we might save an insn if we find the value lying 5314 around. 5315 Try also when reload_in is a pseudo without a hard reg. */ 5316 if (rld[r].in != 0 && rld[r].reg_rtx != 0 5317 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx) 5318 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx) 5319 && GET_CODE (rld[r].in) != MEM 5320 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER))) 5321 continue; 5322 5323#if 0 /* No longer needed for correct operation. 5324 It might give better code, or might not; worth an experiment? */ 5325 /* If this is an optional reload, we can't inherit from earlier insns 5326 until we are sure that any non-optional reloads have been allocated. 5327 The following code takes advantage of the fact that optional reloads 5328 are at the end of reload_order. */ 5329 if (rld[r].optional != 0) 5330 for (i = 0; i < j; i++) 5331 if ((rld[reload_order[i]].out != 0 5332 || rld[reload_order[i]].in != 0 5333 || rld[reload_order[i]].secondary_p) 5334 && ! rld[reload_order[i]].optional 5335 && rld[reload_order[i]].reg_rtx == 0) 5336 allocate_reload_reg (chain, reload_order[i], 0); 5337#endif 5338 5339 /* First see if this pseudo is already available as reloaded 5340 for a previous insn. We cannot try to inherit for reloads 5341 that are smaller than the maximum number of registers needed 5342 for groups unless the register we would allocate cannot be used 5343 for the groups. 5344 5345 We could check here to see if this is a secondary reload for 5346 an object that is already in a register of the desired class. 5347 This would avoid the need for the secondary reload register. 5348 But this is complex because we can't easily determine what 5349 objects might want to be loaded via this reload. So let a 5350 register be allocated here. In `emit_reload_insns' we suppress 5351 one of the loads in the case described above. */ 5352 5353 if (inheritance) 5354 { 5355 int byte = 0; 5356 int regno = -1; 5357 enum machine_mode mode = VOIDmode; 5358 5359 if (rld[r].in == 0) 5360 ; 5361 else if (GET_CODE (rld[r].in) == REG) 5362 { 5363 regno = REGNO (rld[r].in); 5364 mode = GET_MODE (rld[r].in); 5365 } 5366 else if (GET_CODE (rld[r].in_reg) == REG) 5367 { 5368 regno = REGNO (rld[r].in_reg); 5369 mode = GET_MODE (rld[r].in_reg); 5370 } 5371 else if (GET_CODE (rld[r].in_reg) == SUBREG 5372 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG) 5373 { 5374 byte = SUBREG_BYTE (rld[r].in_reg); 5375 regno = REGNO (SUBREG_REG (rld[r].in_reg)); 5376 if (regno < FIRST_PSEUDO_REGISTER) 5377 regno = subreg_regno (rld[r].in_reg); 5378 mode = GET_MODE (rld[r].in_reg); 5379 } 5380#ifdef AUTO_INC_DEC 5381 else if ((GET_CODE (rld[r].in_reg) == PRE_INC 5382 || GET_CODE (rld[r].in_reg) == PRE_DEC 5383 || GET_CODE (rld[r].in_reg) == POST_INC 5384 || GET_CODE (rld[r].in_reg) == POST_DEC) 5385 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG) 5386 { 5387 regno = REGNO (XEXP (rld[r].in_reg, 0)); 5388 mode = GET_MODE (XEXP (rld[r].in_reg, 0)); 5389 rld[r].out = rld[r].in; 5390 } 5391#endif 5392#if 0 5393 /* This won't work, since REGNO can be a pseudo reg number. 5394 Also, it takes much more hair to keep track of all the things 5395 that can invalidate an inherited reload of part of a pseudoreg. */ 5396 else if (GET_CODE (rld[r].in) == SUBREG 5397 && GET_CODE (SUBREG_REG (rld[r].in)) == REG) 5398 regno = subreg_regno (rld[r].in); 5399#endif 5400 5401 if (regno >= 0 && reg_last_reload_reg[regno] != 0) 5402 { 5403 enum reg_class class = rld[r].class, last_class; 5404 rtx last_reg = reg_last_reload_reg[regno]; 5405 enum machine_mode need_mode; 5406 5407 i = REGNO (last_reg); 5408 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode); 5409 last_class = REGNO_REG_CLASS (i); 5410 5411 if (byte == 0) 5412 need_mode = mode; 5413 else 5414 need_mode 5415 = smallest_mode_for_size (GET_MODE_BITSIZE (mode) 5416 + byte * BITS_PER_UNIT, 5417 GET_MODE_CLASS (mode)); 5418 5419 if ((GET_MODE_SIZE (GET_MODE (last_reg)) 5420 >= GET_MODE_SIZE (need_mode)) 5421#ifdef CANNOT_CHANGE_MODE_CLASS 5422 /* Verify that the register in "i" can be obtained 5423 from LAST_REG. */ 5424 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg), 5425 GET_MODE (last_reg), 5426 mode) 5427#endif 5428 && reg_reloaded_contents[i] == regno 5429 && TEST_HARD_REG_BIT (reg_reloaded_valid, i) 5430 && HARD_REGNO_MODE_OK (i, rld[r].mode) 5431 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i) 5432 /* Even if we can't use this register as a reload 5433 register, we might use it for reload_override_in, 5434 if copying it to the desired class is cheap 5435 enough. */ 5436 || ((REGISTER_MOVE_COST (mode, last_class, class) 5437 < MEMORY_MOVE_COST (mode, class, 1)) 5438#ifdef SECONDARY_INPUT_RELOAD_CLASS 5439 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode, 5440 last_reg) 5441 == NO_REGS) 5442#endif 5443#ifdef SECONDARY_MEMORY_NEEDED 5444 && ! SECONDARY_MEMORY_NEEDED (last_class, class, 5445 mode) 5446#endif 5447 )) 5448 5449 && (rld[r].nregs == max_group_size 5450 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], 5451 i)) 5452 && free_for_value_p (i, rld[r].mode, rld[r].opnum, 5453 rld[r].when_needed, rld[r].in, 5454 const0_rtx, r, 1)) 5455 { 5456 /* If a group is needed, verify that all the subsequent 5457 registers still have their values intact. */ 5458 int nr = HARD_REGNO_NREGS (i, rld[r].mode); 5459 int k; 5460 5461 for (k = 1; k < nr; k++) 5462 if (reg_reloaded_contents[i + k] != regno 5463 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) 5464 break; 5465 5466 if (k == nr) 5467 { 5468 int i1; 5469 int bad_for_class; 5470 5471 last_reg = (GET_MODE (last_reg) == mode 5472 ? last_reg : gen_rtx_REG (mode, i)); 5473 5474 bad_for_class = 0; 5475 for (k = 0; k < nr; k++) 5476 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], 5477 i+k); 5478 5479 /* We found a register that contains the 5480 value we need. If this register is the 5481 same as an `earlyclobber' operand of the 5482 current insn, just mark it as a place to 5483 reload from since we can't use it as the 5484 reload register itself. */ 5485 5486 for (i1 = 0; i1 < n_earlyclobbers; i1++) 5487 if (reg_overlap_mentioned_for_reload_p 5488 (reg_last_reload_reg[regno], 5489 reload_earlyclobbers[i1])) 5490 break; 5491 5492 if (i1 != n_earlyclobbers 5493 || ! (free_for_value_p (i, rld[r].mode, 5494 rld[r].opnum, 5495 rld[r].when_needed, rld[r].in, 5496 rld[r].out, r, 1)) 5497 /* Don't use it if we'd clobber a pseudo reg. */ 5498 || (TEST_HARD_REG_BIT (reg_used_in_insn, i) 5499 && rld[r].out 5500 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) 5501 /* Don't clobber the frame pointer. */ 5502 || (i == HARD_FRAME_POINTER_REGNUM 5503 && frame_pointer_needed 5504 && rld[r].out) 5505 /* Don't really use the inherited spill reg 5506 if we need it wider than we've got it. */ 5507 || (GET_MODE_SIZE (rld[r].mode) 5508 > GET_MODE_SIZE (mode)) 5509 || bad_for_class 5510 5511 /* If find_reloads chose reload_out as reload 5512 register, stay with it - that leaves the 5513 inherited register for subsequent reloads. */ 5514 || (rld[r].out && rld[r].reg_rtx 5515 && rtx_equal_p (rld[r].out, rld[r].reg_rtx))) 5516 { 5517 if (! rld[r].optional) 5518 { 5519 reload_override_in[r] = last_reg; 5520 reload_inheritance_insn[r] 5521 = reg_reloaded_insn[i]; 5522 } 5523 } 5524 else 5525 { 5526 int k; 5527 /* We can use this as a reload reg. */ 5528 /* Mark the register as in use for this part of 5529 the insn. */ 5530 mark_reload_reg_in_use (i, 5531 rld[r].opnum, 5532 rld[r].when_needed, 5533 rld[r].mode); 5534 rld[r].reg_rtx = last_reg; 5535 reload_inherited[r] = 1; 5536 reload_inheritance_insn[r] 5537 = reg_reloaded_insn[i]; 5538 reload_spill_index[r] = i; 5539 for (k = 0; k < nr; k++) 5540 SET_HARD_REG_BIT (reload_reg_used_for_inherit, 5541 i + k); 5542 } 5543 } 5544 } 5545 } 5546 } 5547 5548 /* Here's another way to see if the value is already lying around. */ 5549 if (inheritance 5550 && rld[r].in != 0 5551 && ! reload_inherited[r] 5552 && rld[r].out == 0 5553 && (CONSTANT_P (rld[r].in) 5554 || GET_CODE (rld[r].in) == PLUS 5555 || GET_CODE (rld[r].in) == REG 5556 || GET_CODE (rld[r].in) == MEM) 5557 && (rld[r].nregs == max_group_size 5558 || ! reg_classes_intersect_p (rld[r].class, group_class))) 5559 search_equiv = rld[r].in; 5560 /* If this is an output reload from a simple move insn, look 5561 if an equivalence for the input is available. */ 5562 else if (inheritance && rld[r].in == 0 && rld[r].out != 0) 5563 { 5564 rtx set = single_set (insn); 5565 5566 if (set 5567 && rtx_equal_p (rld[r].out, SET_DEST (set)) 5568 && CONSTANT_P (SET_SRC (set))) 5569 search_equiv = SET_SRC (set); 5570 } 5571 5572 if (search_equiv) 5573 { 5574 rtx equiv 5575 = find_equiv_reg (search_equiv, insn, rld[r].class, 5576 -1, NULL, 0, rld[r].mode); 5577 int regno = 0; 5578 5579 if (equiv != 0) 5580 { 5581 if (GET_CODE (equiv) == REG) 5582 regno = REGNO (equiv); 5583 else if (GET_CODE (equiv) == SUBREG) 5584 { 5585 /* This must be a SUBREG of a hard register. 5586 Make a new REG since this might be used in an 5587 address and not all machines support SUBREGs 5588 there. */ 5589 regno = subreg_regno (equiv); 5590 equiv = gen_rtx_REG (rld[r].mode, regno); 5591 } 5592 else 5593 abort (); 5594 } 5595 5596 /* If we found a spill reg, reject it unless it is free 5597 and of the desired class. */ 5598 if (equiv != 0) 5599 { 5600 int regs_used = 0; 5601 int bad_for_class = 0; 5602 int max_regno = regno + rld[r].nregs; 5603 5604 for (i = regno; i < max_regno; i++) 5605 { 5606 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all, 5607 i); 5608 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], 5609 i); 5610 } 5611 5612 if ((regs_used 5613 && ! free_for_value_p (regno, rld[r].mode, 5614 rld[r].opnum, rld[r].when_needed, 5615 rld[r].in, rld[r].out, r, 1)) 5616 || bad_for_class) 5617 equiv = 0; 5618 } 5619 5620 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode)) 5621 equiv = 0; 5622 5623 /* We found a register that contains the value we need. 5624 If this register is the same as an `earlyclobber' operand 5625 of the current insn, just mark it as a place to reload from 5626 since we can't use it as the reload register itself. */ 5627 5628 if (equiv != 0) 5629 for (i = 0; i < n_earlyclobbers; i++) 5630 if (reg_overlap_mentioned_for_reload_p (equiv, 5631 reload_earlyclobbers[i])) 5632 { 5633 if (! rld[r].optional) 5634 reload_override_in[r] = equiv; 5635 equiv = 0; 5636 break; 5637 } 5638 5639 /* If the equiv register we have found is explicitly clobbered 5640 in the current insn, it depends on the reload type if we 5641 can use it, use it for reload_override_in, or not at all. 5642 In particular, we then can't use EQUIV for a 5643 RELOAD_FOR_OUTPUT_ADDRESS reload. */ 5644 5645 if (equiv != 0) 5646 { 5647 if (regno_clobbered_p (regno, insn, rld[r].mode, 0)) 5648 switch (rld[r].when_needed) 5649 { 5650 case RELOAD_FOR_OTHER_ADDRESS: 5651 case RELOAD_FOR_INPADDR_ADDRESS: 5652 case RELOAD_FOR_INPUT_ADDRESS: 5653 case RELOAD_FOR_OPADDR_ADDR: 5654 break; 5655 case RELOAD_OTHER: 5656 case RELOAD_FOR_INPUT: 5657 case RELOAD_FOR_OPERAND_ADDRESS: 5658 if (! rld[r].optional) 5659 reload_override_in[r] = equiv; 5660 /* Fall through. */ 5661 default: 5662 equiv = 0; 5663 break; 5664 } 5665 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1)) 5666 switch (rld[r].when_needed) 5667 { 5668 case RELOAD_FOR_OTHER_ADDRESS: 5669 case RELOAD_FOR_INPADDR_ADDRESS: 5670 case RELOAD_FOR_INPUT_ADDRESS: 5671 case RELOAD_FOR_OPADDR_ADDR: 5672 case RELOAD_FOR_OPERAND_ADDRESS: 5673 case RELOAD_FOR_INPUT: 5674 break; 5675 case RELOAD_OTHER: 5676 if (! rld[r].optional) 5677 reload_override_in[r] = equiv; 5678 /* Fall through. */ 5679 default: 5680 equiv = 0; 5681 break; 5682 } 5683 } 5684 5685 /* If we found an equivalent reg, say no code need be generated 5686 to load it, and use it as our reload reg. */ 5687 if (equiv != 0 5688 && (regno != HARD_FRAME_POINTER_REGNUM 5689 || !frame_pointer_needed)) 5690 { 5691 int nr = HARD_REGNO_NREGS (regno, rld[r].mode); 5692 int k; 5693 rld[r].reg_rtx = equiv; 5694 reload_inherited[r] = 1; 5695 5696 /* If reg_reloaded_valid is not set for this register, 5697 there might be a stale spill_reg_store lying around. 5698 We must clear it, since otherwise emit_reload_insns 5699 might delete the store. */ 5700 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) 5701 spill_reg_store[regno] = NULL_RTX; 5702 /* If any of the hard registers in EQUIV are spill 5703 registers, mark them as in use for this insn. */ 5704 for (k = 0; k < nr; k++) 5705 { 5706 i = spill_reg_order[regno + k]; 5707 if (i >= 0) 5708 { 5709 mark_reload_reg_in_use (regno, rld[r].opnum, 5710 rld[r].when_needed, 5711 rld[r].mode); 5712 SET_HARD_REG_BIT (reload_reg_used_for_inherit, 5713 regno + k); 5714 } 5715 } 5716 } 5717 } 5718 5719 /* If we found a register to use already, or if this is an optional 5720 reload, we are done. */ 5721 if (rld[r].reg_rtx != 0 || rld[r].optional != 0) 5722 continue; 5723 5724#if 0 5725 /* No longer needed for correct operation. Might or might 5726 not give better code on the average. Want to experiment? */ 5727 5728 /* See if there is a later reload that has a class different from our 5729 class that intersects our class or that requires less register 5730 than our reload. If so, we must allocate a register to this 5731 reload now, since that reload might inherit a previous reload 5732 and take the only available register in our class. Don't do this 5733 for optional reloads since they will force all previous reloads 5734 to be allocated. Also don't do this for reloads that have been 5735 turned off. */ 5736 5737 for (i = j + 1; i < n_reloads; i++) 5738 { 5739 int s = reload_order[i]; 5740 5741 if ((rld[s].in == 0 && rld[s].out == 0 5742 && ! rld[s].secondary_p) 5743 || rld[s].optional) 5744 continue; 5745 5746 if ((rld[s].class != rld[r].class 5747 && reg_classes_intersect_p (rld[r].class, 5748 rld[s].class)) 5749 || rld[s].nregs < rld[r].nregs) 5750 break; 5751 } 5752 5753 if (i == n_reloads) 5754 continue; 5755 5756 allocate_reload_reg (chain, r, j == n_reloads - 1); 5757#endif 5758 } 5759 5760 /* Now allocate reload registers for anything non-optional that 5761 didn't get one yet. */ 5762 for (j = 0; j < n_reloads; j++) 5763 { 5764 int r = reload_order[j]; 5765 5766 /* Ignore reloads that got marked inoperative. */ 5767 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p) 5768 continue; 5769 5770 /* Skip reloads that already have a register allocated or are 5771 optional. */ 5772 if (rld[r].reg_rtx != 0 || rld[r].optional) 5773 continue; 5774 5775 if (! allocate_reload_reg (chain, r, j == n_reloads - 1)) 5776 break; 5777 } 5778 5779 /* If that loop got all the way, we have won. */ 5780 if (j == n_reloads) 5781 { 5782 win = 1; 5783 break; 5784 } 5785 5786 /* Loop around and try without any inheritance. */ 5787 } 5788 5789 if (! win) 5790 { 5791 /* First undo everything done by the failed attempt 5792 to allocate with inheritance. */ 5793 choose_reload_regs_init (chain, save_reload_reg_rtx); 5794 5795 /* Some sanity tests to verify that the reloads found in the first 5796 pass are identical to the ones we have now. */ 5797 if (chain->n_reloads != n_reloads) 5798 abort (); 5799 5800 for (i = 0; i < n_reloads; i++) 5801 { 5802 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0) 5803 continue; 5804 if (chain->rld[i].when_needed != rld[i].when_needed) 5805 abort (); 5806 for (j = 0; j < n_spills; j++) 5807 if (spill_regs[j] == chain->rld[i].regno) 5808 if (! set_reload_reg (j, i)) 5809 failed_reload (chain->insn, i); 5810 } 5811 } 5812 5813 /* If we thought we could inherit a reload, because it seemed that 5814 nothing else wanted the same reload register earlier in the insn, 5815 verify that assumption, now that all reloads have been assigned. 5816 Likewise for reloads where reload_override_in has been set. */ 5817 5818 /* If doing expensive optimizations, do one preliminary pass that doesn't 5819 cancel any inheritance, but removes reloads that have been needed only 5820 for reloads that we know can be inherited. */ 5821 for (pass = flag_expensive_optimizations; pass >= 0; pass--) 5822 { 5823 for (j = 0; j < n_reloads; j++) 5824 { 5825 int r = reload_order[j]; 5826 rtx check_reg; 5827 if (reload_inherited[r] && rld[r].reg_rtx) 5828 check_reg = rld[r].reg_rtx; 5829 else if (reload_override_in[r] 5830 && (GET_CODE (reload_override_in[r]) == REG 5831 || GET_CODE (reload_override_in[r]) == SUBREG)) 5832 check_reg = reload_override_in[r]; 5833 else 5834 continue; 5835 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode, 5836 rld[r].opnum, rld[r].when_needed, rld[r].in, 5837 (reload_inherited[r] 5838 ? rld[r].out : const0_rtx), 5839 r, 1)) 5840 { 5841 if (pass) 5842 continue; 5843 reload_inherited[r] = 0; 5844 reload_override_in[r] = 0; 5845 } 5846 /* If we can inherit a RELOAD_FOR_INPUT, or can use a 5847 reload_override_in, then we do not need its related 5848 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads; 5849 likewise for other reload types. 5850 We handle this by removing a reload when its only replacement 5851 is mentioned in reload_in of the reload we are going to inherit. 5852 A special case are auto_inc expressions; even if the input is 5853 inherited, we still need the address for the output. We can 5854 recognize them because they have RELOAD_OUT set to RELOAD_IN. 5855 If we succeeded removing some reload and we are doing a preliminary 5856 pass just to remove such reloads, make another pass, since the 5857 removal of one reload might allow us to inherit another one. */ 5858 else if (rld[r].in 5859 && rld[r].out != rld[r].in 5860 && remove_address_replacements (rld[r].in) && pass) 5861 pass = 2; 5862 } 5863 } 5864 5865 /* Now that reload_override_in is known valid, 5866 actually override reload_in. */ 5867 for (j = 0; j < n_reloads; j++) 5868 if (reload_override_in[j]) 5869 rld[j].in = reload_override_in[j]; 5870 5871 /* If this reload won't be done because it has been canceled or is 5872 optional and not inherited, clear reload_reg_rtx so other 5873 routines (such as subst_reloads) don't get confused. */ 5874 for (j = 0; j < n_reloads; j++) 5875 if (rld[j].reg_rtx != 0 5876 && ((rld[j].optional && ! reload_inherited[j]) 5877 || (rld[j].in == 0 && rld[j].out == 0 5878 && ! rld[j].secondary_p))) 5879 { 5880 int regno = true_regnum (rld[j].reg_rtx); 5881 5882 if (spill_reg_order[regno] >= 0) 5883 clear_reload_reg_in_use (regno, rld[j].opnum, 5884 rld[j].when_needed, rld[j].mode); 5885 rld[j].reg_rtx = 0; 5886 reload_spill_index[j] = -1; 5887 } 5888 5889 /* Record which pseudos and which spill regs have output reloads. */ 5890 for (j = 0; j < n_reloads; j++) 5891 { 5892 int r = reload_order[j]; 5893 5894 i = reload_spill_index[r]; 5895 5896 /* I is nonneg if this reload uses a register. 5897 If rld[r].reg_rtx is 0, this is an optional reload 5898 that we opted to ignore. */ 5899 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG 5900 && rld[r].reg_rtx != 0) 5901 { 5902 int nregno = REGNO (rld[r].out_reg); 5903 int nr = 1; 5904 5905 if (nregno < FIRST_PSEUDO_REGISTER) 5906 nr = HARD_REGNO_NREGS (nregno, rld[r].mode); 5907 5908 while (--nr >= 0) 5909 reg_has_output_reload[nregno + nr] = 1; 5910 5911 if (i >= 0) 5912 { 5913 nr = HARD_REGNO_NREGS (i, rld[r].mode); 5914 while (--nr >= 0) 5915 SET_HARD_REG_BIT (reg_is_output_reload, i + nr); 5916 } 5917 5918 if (rld[r].when_needed != RELOAD_OTHER 5919 && rld[r].when_needed != RELOAD_FOR_OUTPUT 5920 && rld[r].when_needed != RELOAD_FOR_INSN) 5921 abort (); 5922 } 5923 } 5924} 5925 5926/* Deallocate the reload register for reload R. This is called from 5927 remove_address_replacements. */ 5928 5929void 5930deallocate_reload_reg (int r) 5931{ 5932 int regno; 5933 5934 if (! rld[r].reg_rtx) 5935 return; 5936 regno = true_regnum (rld[r].reg_rtx); 5937 rld[r].reg_rtx = 0; 5938 if (spill_reg_order[regno] >= 0) 5939 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed, 5940 rld[r].mode); 5941 reload_spill_index[r] = -1; 5942} 5943 5944/* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two 5945 reloads of the same item for fear that we might not have enough reload 5946 registers. However, normally they will get the same reload register 5947 and hence actually need not be loaded twice. 5948 5949 Here we check for the most common case of this phenomenon: when we have 5950 a number of reloads for the same object, each of which were allocated 5951 the same reload_reg_rtx, that reload_reg_rtx is not used for any other 5952 reload, and is not modified in the insn itself. If we find such, 5953 merge all the reloads and set the resulting reload to RELOAD_OTHER. 5954 This will not increase the number of spill registers needed and will 5955 prevent redundant code. */ 5956 5957static void 5958merge_assigned_reloads (rtx insn) 5959{ 5960 int i, j; 5961 5962 /* Scan all the reloads looking for ones that only load values and 5963 are not already RELOAD_OTHER and ones whose reload_reg_rtx are 5964 assigned and not modified by INSN. */ 5965 5966 for (i = 0; i < n_reloads; i++) 5967 { 5968 int conflicting_input = 0; 5969 int max_input_address_opnum = -1; 5970 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS; 5971 5972 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER 5973 || rld[i].out != 0 || rld[i].reg_rtx == 0 5974 || reg_set_p (rld[i].reg_rtx, insn)) 5975 continue; 5976 5977 /* Look at all other reloads. Ensure that the only use of this 5978 reload_reg_rtx is in a reload that just loads the same value 5979 as we do. Note that any secondary reloads must be of the identical 5980 class since the values, modes, and result registers are the 5981 same, so we need not do anything with any secondary reloads. */ 5982 5983 for (j = 0; j < n_reloads; j++) 5984 { 5985 if (i == j || rld[j].reg_rtx == 0 5986 || ! reg_overlap_mentioned_p (rld[j].reg_rtx, 5987 rld[i].reg_rtx)) 5988 continue; 5989 5990 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS 5991 && rld[j].opnum > max_input_address_opnum) 5992 max_input_address_opnum = rld[j].opnum; 5993 5994 /* If the reload regs aren't exactly the same (e.g, different modes) 5995 or if the values are different, we can't merge this reload. 5996 But if it is an input reload, we might still merge 5997 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */ 5998 5999 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) 6000 || rld[j].out != 0 || rld[j].in == 0 6001 || ! rtx_equal_p (rld[i].in, rld[j].in)) 6002 { 6003 if (rld[j].when_needed != RELOAD_FOR_INPUT 6004 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS 6005 || rld[i].opnum > rld[j].opnum) 6006 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS)) 6007 break; 6008 conflicting_input = 1; 6009 if (min_conflicting_input_opnum > rld[j].opnum) 6010 min_conflicting_input_opnum = rld[j].opnum; 6011 } 6012 } 6013 6014 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if 6015 we, in fact, found any matching reloads. */ 6016 6017 if (j == n_reloads 6018 && max_input_address_opnum <= min_conflicting_input_opnum) 6019 { 6020 for (j = 0; j < n_reloads; j++) 6021 if (i != j && rld[j].reg_rtx != 0 6022 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) 6023 && (! conflicting_input 6024 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS 6025 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS)) 6026 { 6027 rld[i].when_needed = RELOAD_OTHER; 6028 rld[j].in = 0; 6029 reload_spill_index[j] = -1; 6030 transfer_replacements (i, j); 6031 } 6032 6033 /* If this is now RELOAD_OTHER, look for any reloads that load 6034 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS 6035 if they were for inputs, RELOAD_OTHER for outputs. Note that 6036 this test is equivalent to looking for reloads for this operand 6037 number. */ 6038 /* We must take special care when there are two or more reloads to 6039 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the 6040 same value or a part of it; we must not change its type if there 6041 is a conflicting input. */ 6042 6043 if (rld[i].when_needed == RELOAD_OTHER) 6044 for (j = 0; j < n_reloads; j++) 6045 if (rld[j].in != 0 6046 && rld[j].when_needed != RELOAD_OTHER 6047 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS 6048 && (! conflicting_input 6049 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS 6050 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) 6051 && reg_overlap_mentioned_for_reload_p (rld[j].in, 6052 rld[i].in)) 6053 { 6054 int k; 6055 6056 rld[j].when_needed 6057 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS 6058 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) 6059 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER); 6060 6061 /* Check to see if we accidentally converted two reloads 6062 that use the same reload register with different inputs 6063 to the same type. If so, the resulting code won't work, 6064 so abort. */ 6065 if (rld[j].reg_rtx) 6066 for (k = 0; k < j; k++) 6067 if (rld[k].in != 0 && rld[k].reg_rtx != 0 6068 && rld[k].when_needed == rld[j].when_needed 6069 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx) 6070 && ! rtx_equal_p (rld[k].in, rld[j].in)) 6071 abort (); 6072 } 6073 } 6074 } 6075} 6076 6077/* These arrays are filled by emit_reload_insns and its subroutines. */ 6078static rtx input_reload_insns[MAX_RECOG_OPERANDS]; 6079static rtx other_input_address_reload_insns = 0; 6080static rtx other_input_reload_insns = 0; 6081static rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; 6082static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; 6083static rtx output_reload_insns[MAX_RECOG_OPERANDS]; 6084static rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; 6085static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; 6086static rtx operand_reload_insns = 0; 6087static rtx other_operand_reload_insns = 0; 6088static rtx other_output_reload_insns[MAX_RECOG_OPERANDS]; 6089 6090/* Values to be put in spill_reg_store are put here first. */ 6091static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; 6092static HARD_REG_SET reg_reloaded_died; 6093 6094/* Generate insns to perform reload RL, which is for the insn in CHAIN and 6095 has the number J. OLD contains the value to be used as input. */ 6096 6097static void 6098emit_input_reload_insns (struct insn_chain *chain, struct reload *rl, 6099 rtx old, int j) 6100{ 6101 rtx insn = chain->insn; 6102 rtx reloadreg = rl->reg_rtx; 6103 rtx oldequiv_reg = 0; 6104 rtx oldequiv = 0; 6105 int special = 0; 6106 enum machine_mode mode; 6107 rtx *where; 6108 6109 /* Determine the mode to reload in. 6110 This is very tricky because we have three to choose from. 6111 There is the mode the insn operand wants (rl->inmode). 6112 There is the mode of the reload register RELOADREG. 6113 There is the intrinsic mode of the operand, which we could find 6114 by stripping some SUBREGs. 6115 It turns out that RELOADREG's mode is irrelevant: 6116 we can change that arbitrarily. 6117 6118 Consider (SUBREG:SI foo:QI) as an operand that must be SImode; 6119 then the reload reg may not support QImode moves, so use SImode. 6120 If foo is in memory due to spilling a pseudo reg, this is safe, 6121 because the QImode value is in the least significant part of a 6122 slot big enough for a SImode. If foo is some other sort of 6123 memory reference, then it is impossible to reload this case, 6124 so previous passes had better make sure this never happens. 6125 6126 Then consider a one-word union which has SImode and one of its 6127 members is a float, being fetched as (SUBREG:SF union:SI). 6128 We must fetch that as SFmode because we could be loading into 6129 a float-only register. In this case OLD's mode is correct. 6130 6131 Consider an immediate integer: it has VOIDmode. Here we need 6132 to get a mode from something else. 6133 6134 In some cases, there is a fourth mode, the operand's 6135 containing mode. If the insn specifies a containing mode for 6136 this operand, it overrides all others. 6137 6138 I am not sure whether the algorithm here is always right, 6139 but it does the right things in those cases. */ 6140 6141 mode = GET_MODE (old); 6142 if (mode == VOIDmode) 6143 mode = rl->inmode; 6144 6145#ifdef SECONDARY_INPUT_RELOAD_CLASS 6146 /* If we need a secondary register for this operation, see if 6147 the value is already in a register in that class. Don't 6148 do this if the secondary register will be used as a scratch 6149 register. */ 6150 6151 if (rl->secondary_in_reload >= 0 6152 && rl->secondary_in_icode == CODE_FOR_nothing 6153 && optimize) 6154 oldequiv 6155 = find_equiv_reg (old, insn, 6156 rld[rl->secondary_in_reload].class, 6157 -1, NULL, 0, mode); 6158#endif 6159 6160 /* If reloading from memory, see if there is a register 6161 that already holds the same value. If so, reload from there. 6162 We can pass 0 as the reload_reg_p argument because 6163 any other reload has either already been emitted, 6164 in which case find_equiv_reg will see the reload-insn, 6165 or has yet to be emitted, in which case it doesn't matter 6166 because we will use this equiv reg right away. */ 6167 6168 if (oldequiv == 0 && optimize 6169 && (GET_CODE (old) == MEM 6170 || (GET_CODE (old) == REG 6171 && REGNO (old) >= FIRST_PSEUDO_REGISTER 6172 && reg_renumber[REGNO (old)] < 0))) 6173 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode); 6174 6175 if (oldequiv) 6176 { 6177 unsigned int regno = true_regnum (oldequiv); 6178 6179 /* Don't use OLDEQUIV if any other reload changes it at an 6180 earlier stage of this insn or at this stage. */ 6181 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed, 6182 rl->in, const0_rtx, j, 0)) 6183 oldequiv = 0; 6184 6185 /* If it is no cheaper to copy from OLDEQUIV into the 6186 reload register than it would be to move from memory, 6187 don't use it. Likewise, if we need a secondary register 6188 or memory. */ 6189 6190 if (oldequiv != 0 6191 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class 6192 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno), 6193 rl->class) 6194 >= MEMORY_MOVE_COST (mode, rl->class, 1))) 6195#ifdef SECONDARY_INPUT_RELOAD_CLASS 6196 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class, 6197 mode, oldequiv) 6198 != NO_REGS) 6199#endif 6200#ifdef SECONDARY_MEMORY_NEEDED 6201 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno), 6202 rl->class, 6203 mode) 6204#endif 6205 )) 6206 oldequiv = 0; 6207 } 6208 6209 /* delete_output_reload is only invoked properly if old contains 6210 the original pseudo register. Since this is replaced with a 6211 hard reg when RELOAD_OVERRIDE_IN is set, see if we can 6212 find the pseudo in RELOAD_IN_REG. */ 6213 if (oldequiv == 0 6214 && reload_override_in[j] 6215 && GET_CODE (rl->in_reg) == REG) 6216 { 6217 oldequiv = old; 6218 old = rl->in_reg; 6219 } 6220 if (oldequiv == 0) 6221 oldequiv = old; 6222 else if (GET_CODE (oldequiv) == REG) 6223 oldequiv_reg = oldequiv; 6224 else if (GET_CODE (oldequiv) == SUBREG) 6225 oldequiv_reg = SUBREG_REG (oldequiv); 6226 6227 /* If we are reloading from a register that was recently stored in 6228 with an output-reload, see if we can prove there was 6229 actually no need to store the old value in it. */ 6230 6231 if (optimize && GET_CODE (oldequiv) == REG 6232 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER 6233 && spill_reg_store[REGNO (oldequiv)] 6234 && GET_CODE (old) == REG 6235 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) 6236 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], 6237 rl->out_reg))) 6238 delete_output_reload (insn, j, REGNO (oldequiv)); 6239 6240 /* Encapsulate both RELOADREG and OLDEQUIV into that mode, 6241 then load RELOADREG from OLDEQUIV. Note that we cannot use 6242 gen_lowpart_common since it can do the wrong thing when 6243 RELOADREG has a multi-word mode. Note that RELOADREG 6244 must always be a REG here. */ 6245 6246 if (GET_MODE (reloadreg) != mode) 6247 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode); 6248 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) 6249 oldequiv = SUBREG_REG (oldequiv); 6250 if (GET_MODE (oldequiv) != VOIDmode 6251 && mode != GET_MODE (oldequiv)) 6252 oldequiv = gen_lowpart_SUBREG (mode, oldequiv); 6253 6254 /* Switch to the right place to emit the reload insns. */ 6255 switch (rl->when_needed) 6256 { 6257 case RELOAD_OTHER: 6258 where = &other_input_reload_insns; 6259 break; 6260 case RELOAD_FOR_INPUT: 6261 where = &input_reload_insns[rl->opnum]; 6262 break; 6263 case RELOAD_FOR_INPUT_ADDRESS: 6264 where = &input_address_reload_insns[rl->opnum]; 6265 break; 6266 case RELOAD_FOR_INPADDR_ADDRESS: 6267 where = &inpaddr_address_reload_insns[rl->opnum]; 6268 break; 6269 case RELOAD_FOR_OUTPUT_ADDRESS: 6270 where = &output_address_reload_insns[rl->opnum]; 6271 break; 6272 case RELOAD_FOR_OUTADDR_ADDRESS: 6273 where = &outaddr_address_reload_insns[rl->opnum]; 6274 break; 6275 case RELOAD_FOR_OPERAND_ADDRESS: 6276 where = &operand_reload_insns; 6277 break; 6278 case RELOAD_FOR_OPADDR_ADDR: 6279 where = &other_operand_reload_insns; 6280 break; 6281 case RELOAD_FOR_OTHER_ADDRESS: 6282 where = &other_input_address_reload_insns; 6283 break; 6284 default: 6285 abort (); 6286 } 6287 6288 push_to_sequence (*where); 6289 6290 /* Auto-increment addresses must be reloaded in a special way. */ 6291 if (rl->out && ! rl->out_reg) 6292 { 6293 /* We are not going to bother supporting the case where a 6294 incremented register can't be copied directly from 6295 OLDEQUIV since this seems highly unlikely. */ 6296 if (rl->secondary_in_reload >= 0) 6297 abort (); 6298 6299 if (reload_inherited[j]) 6300 oldequiv = reloadreg; 6301 6302 old = XEXP (rl->in_reg, 0); 6303 6304 if (optimize && GET_CODE (oldequiv) == REG 6305 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER 6306 && spill_reg_store[REGNO (oldequiv)] 6307 && GET_CODE (old) == REG 6308 && (dead_or_set_p (insn, 6309 spill_reg_stored_to[REGNO (oldequiv)]) 6310 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], 6311 old))) 6312 delete_output_reload (insn, j, REGNO (oldequiv)); 6313 6314 /* Prevent normal processing of this reload. */ 6315 special = 1; 6316 /* Output a special code sequence for this case. */ 6317 new_spill_reg_store[REGNO (reloadreg)] 6318 = inc_for_reload (reloadreg, oldequiv, rl->out, 6319 rl->inc); 6320 } 6321 6322 /* If we are reloading a pseudo-register that was set by the previous 6323 insn, see if we can get rid of that pseudo-register entirely 6324 by redirecting the previous insn into our reload register. */ 6325 6326 else if (optimize && GET_CODE (old) == REG 6327 && REGNO (old) >= FIRST_PSEUDO_REGISTER 6328 && dead_or_set_p (insn, old) 6329 /* This is unsafe if some other reload 6330 uses the same reg first. */ 6331 && ! conflicts_with_override (reloadreg) 6332 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum, 6333 rl->when_needed, old, rl->out, j, 0)) 6334 { 6335 rtx temp = PREV_INSN (insn); 6336 while (temp && GET_CODE (temp) == NOTE) 6337 temp = PREV_INSN (temp); 6338 if (temp 6339 && GET_CODE (temp) == INSN 6340 && GET_CODE (PATTERN (temp)) == SET 6341 && SET_DEST (PATTERN (temp)) == old 6342 /* Make sure we can access insn_operand_constraint. */ 6343 && asm_noperands (PATTERN (temp)) < 0 6344 /* This is unsafe if operand occurs more than once in current 6345 insn. Perhaps some occurrences aren't reloaded. */ 6346 && count_occurrences (PATTERN (insn), old, 0) == 1) 6347 { 6348 rtx old = SET_DEST (PATTERN (temp)); 6349 /* Store into the reload register instead of the pseudo. */ 6350 SET_DEST (PATTERN (temp)) = reloadreg; 6351 6352 /* Verify that resulting insn is valid. */ 6353 extract_insn (temp); 6354 if (constrain_operands (1)) 6355 { 6356 /* If the previous insn is an output reload, the source is 6357 a reload register, and its spill_reg_store entry will 6358 contain the previous destination. This is now 6359 invalid. */ 6360 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG 6361 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER) 6362 { 6363 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0; 6364 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; 6365 } 6366 6367 /* If these are the only uses of the pseudo reg, 6368 pretend for GDB it lives in the reload reg we used. */ 6369 if (REG_N_DEATHS (REGNO (old)) == 1 6370 && REG_N_SETS (REGNO (old)) == 1) 6371 { 6372 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx); 6373 alter_reg (REGNO (old), -1); 6374 } 6375 special = 1; 6376 } 6377 else 6378 { 6379 SET_DEST (PATTERN (temp)) = old; 6380 } 6381 } 6382 } 6383 6384 /* We can't do that, so output an insn to load RELOADREG. */ 6385 6386#ifdef SECONDARY_INPUT_RELOAD_CLASS 6387 /* If we have a secondary reload, pick up the secondary register 6388 and icode, if any. If OLDEQUIV and OLD are different or 6389 if this is an in-out reload, recompute whether or not we 6390 still need a secondary register and what the icode should 6391 be. If we still need a secondary register and the class or 6392 icode is different, go back to reloading from OLD if using 6393 OLDEQUIV means that we got the wrong type of register. We 6394 cannot have different class or icode due to an in-out reload 6395 because we don't make such reloads when both the input and 6396 output need secondary reload registers. */ 6397 6398 if (! special && rl->secondary_in_reload >= 0) 6399 { 6400 rtx second_reload_reg = 0; 6401 int secondary_reload = rl->secondary_in_reload; 6402 rtx real_oldequiv = oldequiv; 6403 rtx real_old = old; 6404 rtx tmp; 6405 enum insn_code icode; 6406 6407 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM 6408 and similarly for OLD. 6409 See comments in get_secondary_reload in reload.c. */ 6410 /* If it is a pseudo that cannot be replaced with its 6411 equivalent MEM, we must fall back to reload_in, which 6412 will have all the necessary substitutions registered. 6413 Likewise for a pseudo that can't be replaced with its 6414 equivalent constant. 6415 6416 Take extra care for subregs of such pseudos. Note that 6417 we cannot use reg_equiv_mem in this case because it is 6418 not in the right mode. */ 6419 6420 tmp = oldequiv; 6421 if (GET_CODE (tmp) == SUBREG) 6422 tmp = SUBREG_REG (tmp); 6423 if (GET_CODE (tmp) == REG 6424 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER 6425 && (reg_equiv_memory_loc[REGNO (tmp)] != 0 6426 || reg_equiv_constant[REGNO (tmp)] != 0)) 6427 { 6428 if (! reg_equiv_mem[REGNO (tmp)] 6429 || num_not_at_initial_offset 6430 || GET_CODE (oldequiv) == SUBREG) 6431 real_oldequiv = rl->in; 6432 else 6433 real_oldequiv = reg_equiv_mem[REGNO (tmp)]; 6434 } 6435 6436 tmp = old; 6437 if (GET_CODE (tmp) == SUBREG) 6438 tmp = SUBREG_REG (tmp); 6439 if (GET_CODE (tmp) == REG 6440 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER 6441 && (reg_equiv_memory_loc[REGNO (tmp)] != 0 6442 || reg_equiv_constant[REGNO (tmp)] != 0)) 6443 { 6444 if (! reg_equiv_mem[REGNO (tmp)] 6445 || num_not_at_initial_offset 6446 || GET_CODE (old) == SUBREG) 6447 real_old = rl->in; 6448 else 6449 real_old = reg_equiv_mem[REGNO (tmp)]; 6450 } 6451 6452 second_reload_reg = rld[secondary_reload].reg_rtx; 6453 icode = rl->secondary_in_icode; 6454 6455 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) 6456 || (rl->in != 0 && rl->out != 0)) 6457 { 6458 enum reg_class new_class 6459 = SECONDARY_INPUT_RELOAD_CLASS (rl->class, 6460 mode, real_oldequiv); 6461 6462 if (new_class == NO_REGS) 6463 second_reload_reg = 0; 6464 else 6465 { 6466 enum insn_code new_icode; 6467 enum machine_mode new_mode; 6468 6469 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], 6470 REGNO (second_reload_reg))) 6471 oldequiv = old, real_oldequiv = real_old; 6472 else 6473 { 6474 new_icode = reload_in_optab[(int) mode]; 6475 if (new_icode != CODE_FOR_nothing 6476 && ((insn_data[(int) new_icode].operand[0].predicate 6477 && ! ((*insn_data[(int) new_icode].operand[0].predicate) 6478 (reloadreg, mode))) 6479 || (insn_data[(int) new_icode].operand[1].predicate 6480 && ! ((*insn_data[(int) new_icode].operand[1].predicate) 6481 (real_oldequiv, mode))))) 6482 new_icode = CODE_FOR_nothing; 6483 6484 if (new_icode == CODE_FOR_nothing) 6485 new_mode = mode; 6486 else 6487 new_mode = insn_data[(int) new_icode].operand[2].mode; 6488 6489 if (GET_MODE (second_reload_reg) != new_mode) 6490 { 6491 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg), 6492 new_mode)) 6493 oldequiv = old, real_oldequiv = real_old; 6494 else 6495 second_reload_reg 6496 = reload_adjust_reg_for_mode (second_reload_reg, 6497 new_mode); 6498 } 6499 } 6500 } 6501 } 6502 6503 /* If we still need a secondary reload register, check 6504 to see if it is being used as a scratch or intermediate 6505 register and generate code appropriately. If we need 6506 a scratch register, use REAL_OLDEQUIV since the form of 6507 the insn may depend on the actual address if it is 6508 a MEM. */ 6509 6510 if (second_reload_reg) 6511 { 6512 if (icode != CODE_FOR_nothing) 6513 { 6514 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, 6515 second_reload_reg)); 6516 special = 1; 6517 } 6518 else 6519 { 6520 /* See if we need a scratch register to load the 6521 intermediate register (a tertiary reload). */ 6522 enum insn_code tertiary_icode 6523 = rld[secondary_reload].secondary_in_icode; 6524 6525 if (tertiary_icode != CODE_FOR_nothing) 6526 { 6527 rtx third_reload_reg 6528 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx; 6529 6530 emit_insn ((GEN_FCN (tertiary_icode) 6531 (second_reload_reg, real_oldequiv, 6532 third_reload_reg))); 6533 } 6534 else 6535 gen_reload (second_reload_reg, real_oldequiv, 6536 rl->opnum, 6537 rl->when_needed); 6538 6539 oldequiv = second_reload_reg; 6540 } 6541 } 6542 } 6543#endif 6544 6545 if (! special && ! rtx_equal_p (reloadreg, oldequiv)) 6546 { 6547 rtx real_oldequiv = oldequiv; 6548 6549 if ((GET_CODE (oldequiv) == REG 6550 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER 6551 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0 6552 || reg_equiv_constant[REGNO (oldequiv)] != 0)) 6553 || (GET_CODE (oldequiv) == SUBREG 6554 && GET_CODE (SUBREG_REG (oldequiv)) == REG 6555 && (REGNO (SUBREG_REG (oldequiv)) 6556 >= FIRST_PSEUDO_REGISTER) 6557 && ((reg_equiv_memory_loc 6558 [REGNO (SUBREG_REG (oldequiv))] != 0) 6559 || (reg_equiv_constant 6560 [REGNO (SUBREG_REG (oldequiv))] != 0))) 6561 || (CONSTANT_P (oldequiv) 6562 && (PREFERRED_RELOAD_CLASS (oldequiv, 6563 REGNO_REG_CLASS (REGNO (reloadreg))) 6564 == NO_REGS))) 6565 real_oldequiv = rl->in; 6566 gen_reload (reloadreg, real_oldequiv, rl->opnum, 6567 rl->when_needed); 6568 } 6569 6570 if (flag_non_call_exceptions) 6571 copy_eh_notes (insn, get_insns ()); 6572 6573 /* End this sequence. */ 6574 *where = get_insns (); 6575 end_sequence (); 6576 6577 /* Update reload_override_in so that delete_address_reloads_1 6578 can see the actual register usage. */ 6579 if (oldequiv_reg) 6580 reload_override_in[j] = oldequiv; 6581} 6582 6583/* Generate insns to for the output reload RL, which is for the insn described 6584 by CHAIN and has the number J. */ 6585static void 6586emit_output_reload_insns (struct insn_chain *chain, struct reload *rl, 6587 int j) 6588{ 6589 rtx reloadreg = rl->reg_rtx; 6590 rtx insn = chain->insn; 6591 int special = 0; 6592 rtx old = rl->out; 6593 enum machine_mode mode = GET_MODE (old); 6594 rtx p; 6595 6596 if (rl->when_needed == RELOAD_OTHER) 6597 start_sequence (); 6598 else 6599 push_to_sequence (output_reload_insns[rl->opnum]); 6600 6601 /* Determine the mode to reload in. 6602 See comments above (for input reloading). */ 6603 6604 if (mode == VOIDmode) 6605 { 6606 /* VOIDmode should never happen for an output. */ 6607 if (asm_noperands (PATTERN (insn)) < 0) 6608 /* It's the compiler's fault. */ 6609 fatal_insn ("VOIDmode on an output", insn); 6610 error_for_asm (insn, "output operand is constant in `asm'"); 6611 /* Prevent crash--use something we know is valid. */ 6612 mode = word_mode; 6613 old = gen_rtx_REG (mode, REGNO (reloadreg)); 6614 } 6615 6616 if (GET_MODE (reloadreg) != mode) 6617 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode); 6618 6619#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 6620 6621 /* If we need two reload regs, set RELOADREG to the intermediate 6622 one, since it will be stored into OLD. We might need a secondary 6623 register only for an input reload, so check again here. */ 6624 6625 if (rl->secondary_out_reload >= 0) 6626 { 6627 rtx real_old = old; 6628 6629 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER 6630 && reg_equiv_mem[REGNO (old)] != 0) 6631 real_old = reg_equiv_mem[REGNO (old)]; 6632 6633 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class, 6634 mode, real_old) 6635 != NO_REGS)) 6636 { 6637 rtx second_reloadreg = reloadreg; 6638 reloadreg = rld[rl->secondary_out_reload].reg_rtx; 6639 6640 /* See if RELOADREG is to be used as a scratch register 6641 or as an intermediate register. */ 6642 if (rl->secondary_out_icode != CODE_FOR_nothing) 6643 { 6644 emit_insn ((GEN_FCN (rl->secondary_out_icode) 6645 (real_old, second_reloadreg, reloadreg))); 6646 special = 1; 6647 } 6648 else 6649 { 6650 /* See if we need both a scratch and intermediate reload 6651 register. */ 6652 6653 int secondary_reload = rl->secondary_out_reload; 6654 enum insn_code tertiary_icode 6655 = rld[secondary_reload].secondary_out_icode; 6656 6657 if (GET_MODE (reloadreg) != mode) 6658 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode); 6659 6660 if (tertiary_icode != CODE_FOR_nothing) 6661 { 6662 rtx third_reloadreg 6663 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx; 6664 rtx tem; 6665 6666 /* Copy primary reload reg to secondary reload reg. 6667 (Note that these have been swapped above, then 6668 secondary reload reg to OLD using our insn.) */ 6669 6670 /* If REAL_OLD is a paradoxical SUBREG, remove it 6671 and try to put the opposite SUBREG on 6672 RELOADREG. */ 6673 if (GET_CODE (real_old) == SUBREG 6674 && (GET_MODE_SIZE (GET_MODE (real_old)) 6675 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old)))) 6676 && 0 != (tem = gen_lowpart_common 6677 (GET_MODE (SUBREG_REG (real_old)), 6678 reloadreg))) 6679 real_old = SUBREG_REG (real_old), reloadreg = tem; 6680 6681 gen_reload (reloadreg, second_reloadreg, 6682 rl->opnum, rl->when_needed); 6683 emit_insn ((GEN_FCN (tertiary_icode) 6684 (real_old, reloadreg, third_reloadreg))); 6685 special = 1; 6686 } 6687 6688 else 6689 /* Copy between the reload regs here and then to 6690 OUT later. */ 6691 6692 gen_reload (reloadreg, second_reloadreg, 6693 rl->opnum, rl->when_needed); 6694 } 6695 } 6696 } 6697#endif 6698 6699 /* Output the last reload insn. */ 6700 if (! special) 6701 { 6702 rtx set; 6703 6704 /* Don't output the last reload if OLD is not the dest of 6705 INSN and is in the src and is clobbered by INSN. */ 6706 if (! flag_expensive_optimizations 6707 || GET_CODE (old) != REG 6708 || !(set = single_set (insn)) 6709 || rtx_equal_p (old, SET_DEST (set)) 6710 || !reg_mentioned_p (old, SET_SRC (set)) 6711 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0)) 6712 gen_reload (old, reloadreg, rl->opnum, 6713 rl->when_needed); 6714 } 6715 6716 /* Look at all insns we emitted, just to be safe. */ 6717 for (p = get_insns (); p; p = NEXT_INSN (p)) 6718 if (INSN_P (p)) 6719 { 6720 rtx pat = PATTERN (p); 6721 6722 /* If this output reload doesn't come from a spill reg, 6723 clear any memory of reloaded copies of the pseudo reg. 6724 If this output reload comes from a spill reg, 6725 reg_has_output_reload will make this do nothing. */ 6726 note_stores (pat, forget_old_reloads_1, NULL); 6727 6728 if (reg_mentioned_p (rl->reg_rtx, pat)) 6729 { 6730 rtx set = single_set (insn); 6731 if (reload_spill_index[j] < 0 6732 && set 6733 && SET_SRC (set) == rl->reg_rtx) 6734 { 6735 int src = REGNO (SET_SRC (set)); 6736 6737 reload_spill_index[j] = src; 6738 SET_HARD_REG_BIT (reg_is_output_reload, src); 6739 if (find_regno_note (insn, REG_DEAD, src)) 6740 SET_HARD_REG_BIT (reg_reloaded_died, src); 6741 } 6742 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER) 6743 { 6744 int s = rl->secondary_out_reload; 6745 set = single_set (p); 6746 /* If this reload copies only to the secondary reload 6747 register, the secondary reload does the actual 6748 store. */ 6749 if (s >= 0 && set == NULL_RTX) 6750 /* We can't tell what function the secondary reload 6751 has and where the actual store to the pseudo is 6752 made; leave new_spill_reg_store alone. */ 6753 ; 6754 else if (s >= 0 6755 && SET_SRC (set) == rl->reg_rtx 6756 && SET_DEST (set) == rld[s].reg_rtx) 6757 { 6758 /* Usually the next instruction will be the 6759 secondary reload insn; if we can confirm 6760 that it is, setting new_spill_reg_store to 6761 that insn will allow an extra optimization. */ 6762 rtx s_reg = rld[s].reg_rtx; 6763 rtx next = NEXT_INSN (p); 6764 rld[s].out = rl->out; 6765 rld[s].out_reg = rl->out_reg; 6766 set = single_set (next); 6767 if (set && SET_SRC (set) == s_reg 6768 && ! new_spill_reg_store[REGNO (s_reg)]) 6769 { 6770 SET_HARD_REG_BIT (reg_is_output_reload, 6771 REGNO (s_reg)); 6772 new_spill_reg_store[REGNO (s_reg)] = next; 6773 } 6774 } 6775 else 6776 new_spill_reg_store[REGNO (rl->reg_rtx)] = p; 6777 } 6778 } 6779 } 6780 6781 if (rl->when_needed == RELOAD_OTHER) 6782 { 6783 emit_insn (other_output_reload_insns[rl->opnum]); 6784 other_output_reload_insns[rl->opnum] = get_insns (); 6785 } 6786 else 6787 output_reload_insns[rl->opnum] = get_insns (); 6788 6789 if (flag_non_call_exceptions) 6790 copy_eh_notes (insn, get_insns ()); 6791 6792 end_sequence (); 6793} 6794 6795/* Do input reloading for reload RL, which is for the insn described by CHAIN 6796 and has the number J. */ 6797static void 6798do_input_reload (struct insn_chain *chain, struct reload *rl, int j) 6799{ 6800 rtx insn = chain->insn; 6801 rtx old = (rl->in && GET_CODE (rl->in) == MEM 6802 ? rl->in_reg : rl->in); 6803 6804 if (old != 0 6805 /* AUTO_INC reloads need to be handled even if inherited. We got an 6806 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */ 6807 && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) 6808 && ! rtx_equal_p (rl->reg_rtx, old) 6809 && rl->reg_rtx != 0) 6810 emit_input_reload_insns (chain, rld + j, old, j); 6811 6812 /* When inheriting a wider reload, we have a MEM in rl->in, 6813 e.g. inheriting a SImode output reload for 6814 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ 6815 if (optimize && reload_inherited[j] && rl->in 6816 && GET_CODE (rl->in) == MEM 6817 && GET_CODE (rl->in_reg) == MEM 6818 && reload_spill_index[j] >= 0 6819 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) 6820 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; 6821 6822 /* If we are reloading a register that was recently stored in with an 6823 output-reload, see if we can prove there was 6824 actually no need to store the old value in it. */ 6825 6826 if (optimize 6827 /* Only attempt this for input reloads; for RELOAD_OTHER we miss 6828 that there may be multiple uses of the previous output reload. 6829 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */ 6830 && rl->when_needed == RELOAD_FOR_INPUT 6831 && (reload_inherited[j] || reload_override_in[j]) 6832 && rl->reg_rtx 6833 && GET_CODE (rl->reg_rtx) == REG 6834 && spill_reg_store[REGNO (rl->reg_rtx)] != 0 6835#if 0 6836 /* There doesn't seem to be any reason to restrict this to pseudos 6837 and doing so loses in the case where we are copying from a 6838 register of the wrong class. */ 6839 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)]) 6840 >= FIRST_PSEUDO_REGISTER) 6841#endif 6842 /* The insn might have already some references to stackslots 6843 replaced by MEMs, while reload_out_reg still names the 6844 original pseudo. */ 6845 && (dead_or_set_p (insn, 6846 spill_reg_stored_to[REGNO (rl->reg_rtx)]) 6847 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)], 6848 rl->out_reg))) 6849 delete_output_reload (insn, j, REGNO (rl->reg_rtx)); 6850} 6851 6852/* Do output reloading for reload RL, which is for the insn described by 6853 CHAIN and has the number J. 6854 ??? At some point we need to support handling output reloads of 6855 JUMP_INSNs or insns that set cc0. */ 6856static void 6857do_output_reload (struct insn_chain *chain, struct reload *rl, int j) 6858{ 6859 rtx note, old; 6860 rtx insn = chain->insn; 6861 /* If this is an output reload that stores something that is 6862 not loaded in this same reload, see if we can eliminate a previous 6863 store. */ 6864 rtx pseudo = rl->out_reg; 6865 6866 if (pseudo 6867 && optimize 6868 && GET_CODE (pseudo) == REG 6869 && ! rtx_equal_p (rl->in_reg, pseudo) 6870 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER 6871 && reg_last_reload_reg[REGNO (pseudo)]) 6872 { 6873 int pseudo_no = REGNO (pseudo); 6874 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]); 6875 6876 /* We don't need to test full validity of last_regno for 6877 inherit here; we only want to know if the store actually 6878 matches the pseudo. */ 6879 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno) 6880 && reg_reloaded_contents[last_regno] == pseudo_no 6881 && spill_reg_store[last_regno] 6882 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) 6883 delete_output_reload (insn, j, last_regno); 6884 } 6885 6886 old = rl->out_reg; 6887 if (old == 0 6888 || rl->reg_rtx == old 6889 || rl->reg_rtx == 0) 6890 return; 6891 6892 /* An output operand that dies right away does need a reload, 6893 but need not be copied from it. Show the new location in the 6894 REG_UNUSED note. */ 6895 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH) 6896 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) 6897 { 6898 XEXP (note, 0) = rl->reg_rtx; 6899 return; 6900 } 6901 /* Likewise for a SUBREG of an operand that dies. */ 6902 else if (GET_CODE (old) == SUBREG 6903 && GET_CODE (SUBREG_REG (old)) == REG 6904 && 0 != (note = find_reg_note (insn, REG_UNUSED, 6905 SUBREG_REG (old)))) 6906 { 6907 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), 6908 rl->reg_rtx); 6909 return; 6910 } 6911 else if (GET_CODE (old) == SCRATCH) 6912 /* If we aren't optimizing, there won't be a REG_UNUSED note, 6913 but we don't want to make an output reload. */ 6914 return; 6915 6916 /* If is a JUMP_INSN, we can't support output reloads yet. */ 6917 if (GET_CODE (insn) == JUMP_INSN) 6918 abort (); 6919 6920 emit_output_reload_insns (chain, rld + j, j); 6921} 6922 6923/* Output insns to reload values in and out of the chosen reload regs. */ 6924 6925static void 6926emit_reload_insns (struct insn_chain *chain) 6927{ 6928 rtx insn = chain->insn; 6929 6930 int j; 6931 6932 CLEAR_HARD_REG_SET (reg_reloaded_died); 6933 6934 for (j = 0; j < reload_n_operands; j++) 6935 input_reload_insns[j] = input_address_reload_insns[j] 6936 = inpaddr_address_reload_insns[j] 6937 = output_reload_insns[j] = output_address_reload_insns[j] 6938 = outaddr_address_reload_insns[j] 6939 = other_output_reload_insns[j] = 0; 6940 other_input_address_reload_insns = 0; 6941 other_input_reload_insns = 0; 6942 operand_reload_insns = 0; 6943 other_operand_reload_insns = 0; 6944 6945 /* Dump reloads into the dump file. */ 6946 if (rtl_dump_file) 6947 { 6948 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); 6949 debug_reload_to_stream (rtl_dump_file); 6950 } 6951 6952 /* Now output the instructions to copy the data into and out of the 6953 reload registers. Do these in the order that the reloads were reported, 6954 since reloads of base and index registers precede reloads of operands 6955 and the operands may need the base and index registers reloaded. */ 6956 6957 for (j = 0; j < n_reloads; j++) 6958 { 6959 if (rld[j].reg_rtx 6960 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER) 6961 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0; 6962 6963 do_input_reload (chain, rld + j, j); 6964 do_output_reload (chain, rld + j, j); 6965 } 6966 6967 /* Now write all the insns we made for reloads in the order expected by 6968 the allocation functions. Prior to the insn being reloaded, we write 6969 the following reloads: 6970 6971 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. 6972 6973 RELOAD_OTHER reloads. 6974 6975 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed 6976 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the 6977 RELOAD_FOR_INPUT reload for the operand. 6978 6979 RELOAD_FOR_OPADDR_ADDRS reloads. 6980 6981 RELOAD_FOR_OPERAND_ADDRESS reloads. 6982 6983 After the insn being reloaded, we write the following: 6984 6985 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed 6986 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the 6987 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output 6988 reloads for the operand. The RELOAD_OTHER output reloads are 6989 output in descending order by reload number. */ 6990 6991 emit_insn_before (other_input_address_reload_insns, insn); 6992 emit_insn_before (other_input_reload_insns, insn); 6993 6994 for (j = 0; j < reload_n_operands; j++) 6995 { 6996 emit_insn_before (inpaddr_address_reload_insns[j], insn); 6997 emit_insn_before (input_address_reload_insns[j], insn); 6998 emit_insn_before (input_reload_insns[j], insn); 6999 } 7000 7001 emit_insn_before (other_operand_reload_insns, insn); 7002 emit_insn_before (operand_reload_insns, insn); 7003 7004 for (j = 0; j < reload_n_operands; j++) 7005 { 7006 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn); 7007 x = emit_insn_after (output_address_reload_insns[j], x); 7008 x = emit_insn_after (output_reload_insns[j], x); 7009 emit_insn_after (other_output_reload_insns[j], x); 7010 } 7011 7012 /* For all the spill regs newly reloaded in this instruction, 7013 record what they were reloaded from, so subsequent instructions 7014 can inherit the reloads. 7015 7016 Update spill_reg_store for the reloads of this insn. 7017 Copy the elements that were updated in the loop above. */ 7018 7019 for (j = 0; j < n_reloads; j++) 7020 { 7021 int r = reload_order[j]; 7022 int i = reload_spill_index[r]; 7023 7024 /* If this is a non-inherited input reload from a pseudo, we must 7025 clear any memory of a previous store to the same pseudo. Only do 7026 something if there will not be an output reload for the pseudo 7027 being reloaded. */ 7028 if (rld[r].in_reg != 0 7029 && ! (reload_inherited[r] || reload_override_in[r])) 7030 { 7031 rtx reg = rld[r].in_reg; 7032 7033 if (GET_CODE (reg) == SUBREG) 7034 reg = SUBREG_REG (reg); 7035 7036 if (GET_CODE (reg) == REG 7037 && REGNO (reg) >= FIRST_PSEUDO_REGISTER 7038 && ! reg_has_output_reload[REGNO (reg)]) 7039 { 7040 int nregno = REGNO (reg); 7041 7042 if (reg_last_reload_reg[nregno]) 7043 { 7044 int last_regno = REGNO (reg_last_reload_reg[nregno]); 7045 7046 if (reg_reloaded_contents[last_regno] == nregno) 7047 spill_reg_store[last_regno] = 0; 7048 } 7049 } 7050 } 7051 7052 /* I is nonneg if this reload used a register. 7053 If rld[r].reg_rtx is 0, this is an optional reload 7054 that we opted to ignore. */ 7055 7056 if (i >= 0 && rld[r].reg_rtx != 0) 7057 { 7058 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx)); 7059 int k; 7060 int part_reaches_end = 0; 7061 int all_reaches_end = 1; 7062 7063 /* For a multi register reload, we need to check if all or part 7064 of the value lives to the end. */ 7065 for (k = 0; k < nr; k++) 7066 { 7067 if (reload_reg_reaches_end_p (i + k, rld[r].opnum, 7068 rld[r].when_needed)) 7069 part_reaches_end = 1; 7070 else 7071 all_reaches_end = 0; 7072 } 7073 7074 /* Ignore reloads that don't reach the end of the insn in 7075 entirety. */ 7076 if (all_reaches_end) 7077 { 7078 /* First, clear out memory of what used to be in this spill reg. 7079 If consecutive registers are used, clear them all. */ 7080 7081 for (k = 0; k < nr; k++) 7082 { 7083 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); 7084 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k); 7085 } 7086 7087 /* Maybe the spill reg contains a copy of reload_out. */ 7088 if (rld[r].out != 0 7089 && (GET_CODE (rld[r].out) == REG 7090#ifdef AUTO_INC_DEC 7091 || ! rld[r].out_reg 7092#endif 7093 || GET_CODE (rld[r].out_reg) == REG)) 7094 { 7095 rtx out = (GET_CODE (rld[r].out) == REG 7096 ? rld[r].out 7097 : rld[r].out_reg 7098 ? rld[r].out_reg 7099/* AUTO_INC */ : XEXP (rld[r].in_reg, 0)); 7100 int nregno = REGNO (out); 7101 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 7102 : HARD_REGNO_NREGS (nregno, 7103 GET_MODE (rld[r].reg_rtx))); 7104 7105 spill_reg_store[i] = new_spill_reg_store[i]; 7106 spill_reg_stored_to[i] = out; 7107 reg_last_reload_reg[nregno] = rld[r].reg_rtx; 7108 7109 /* If NREGNO is a hard register, it may occupy more than 7110 one register. If it does, say what is in the 7111 rest of the registers assuming that both registers 7112 agree on how many words the object takes. If not, 7113 invalidate the subsequent registers. */ 7114 7115 if (nregno < FIRST_PSEUDO_REGISTER) 7116 for (k = 1; k < nnr; k++) 7117 reg_last_reload_reg[nregno + k] 7118 = (nr == nnr 7119 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k] 7120 : 0); 7121 7122 /* Now do the inverse operation. */ 7123 for (k = 0; k < nr; k++) 7124 { 7125 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); 7126 reg_reloaded_contents[i + k] 7127 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr 7128 ? nregno 7129 : nregno + k); 7130 reg_reloaded_insn[i + k] = insn; 7131 SET_HARD_REG_BIT (reg_reloaded_valid, i + k); 7132 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out))) 7133 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k); 7134 } 7135 } 7136 7137 /* Maybe the spill reg contains a copy of reload_in. Only do 7138 something if there will not be an output reload for 7139 the register being reloaded. */ 7140 else if (rld[r].out_reg == 0 7141 && rld[r].in != 0 7142 && ((GET_CODE (rld[r].in) == REG 7143 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER 7144 && ! reg_has_output_reload[REGNO (rld[r].in)]) 7145 || (GET_CODE (rld[r].in_reg) == REG 7146 && ! reg_has_output_reload[REGNO (rld[r].in_reg)])) 7147 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn))) 7148 { 7149 int nregno; 7150 int nnr; 7151 rtx in; 7152 7153 if (GET_CODE (rld[r].in) == REG 7154 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER) 7155 in = rld[r].in; 7156 else if (GET_CODE (rld[r].in_reg) == REG) 7157 in = rld[r].in_reg; 7158 else 7159 in = XEXP (rld[r].in_reg, 0); 7160 nregno = REGNO (in); 7161 7162 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 7163 : HARD_REGNO_NREGS (nregno, 7164 GET_MODE (rld[r].reg_rtx))); 7165 7166 reg_last_reload_reg[nregno] = rld[r].reg_rtx; 7167 7168 if (nregno < FIRST_PSEUDO_REGISTER) 7169 for (k = 1; k < nnr; k++) 7170 reg_last_reload_reg[nregno + k] 7171 = (nr == nnr 7172 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k] 7173 : 0); 7174 7175 /* Unless we inherited this reload, show we haven't 7176 recently done a store. 7177 Previous stores of inherited auto_inc expressions 7178 also have to be discarded. */ 7179 if (! reload_inherited[r] 7180 || (rld[r].out && ! rld[r].out_reg)) 7181 spill_reg_store[i] = 0; 7182 7183 for (k = 0; k < nr; k++) 7184 { 7185 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); 7186 reg_reloaded_contents[i + k] 7187 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr 7188 ? nregno 7189 : nregno + k); 7190 reg_reloaded_insn[i + k] = insn; 7191 SET_HARD_REG_BIT (reg_reloaded_valid, i + k); 7192 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in))) 7193 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k); 7194 } 7195 } 7196 } 7197 7198 /* However, if part of the reload reaches the end, then we must 7199 invalidate the old info for the part that survives to the end. */ 7200 else if (part_reaches_end) 7201 { 7202 for (k = 0; k < nr; k++) 7203 if (reload_reg_reaches_end_p (i + k, 7204 rld[r].opnum, 7205 rld[r].when_needed)) 7206 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); 7207 } 7208 } 7209 7210 /* The following if-statement was #if 0'd in 1.34 (or before...). 7211 It's reenabled in 1.35 because supposedly nothing else 7212 deals with this problem. */ 7213 7214 /* If a register gets output-reloaded from a non-spill register, 7215 that invalidates any previous reloaded copy of it. 7216 But forget_old_reloads_1 won't get to see it, because 7217 it thinks only about the original insn. So invalidate it here. */ 7218 if (i < 0 && rld[r].out != 0 7219 && (GET_CODE (rld[r].out) == REG 7220 || (GET_CODE (rld[r].out) == MEM 7221 && GET_CODE (rld[r].out_reg) == REG))) 7222 { 7223 rtx out = (GET_CODE (rld[r].out) == REG 7224 ? rld[r].out : rld[r].out_reg); 7225 int nregno = REGNO (out); 7226 if (nregno >= FIRST_PSEUDO_REGISTER) 7227 { 7228 rtx src_reg, store_insn = NULL_RTX; 7229 7230 reg_last_reload_reg[nregno] = 0; 7231 7232 /* If we can find a hard register that is stored, record 7233 the storing insn so that we may delete this insn with 7234 delete_output_reload. */ 7235 src_reg = rld[r].reg_rtx; 7236 7237 /* If this is an optional reload, try to find the source reg 7238 from an input reload. */ 7239 if (! src_reg) 7240 { 7241 rtx set = single_set (insn); 7242 if (set && SET_DEST (set) == rld[r].out) 7243 { 7244 int k; 7245 7246 src_reg = SET_SRC (set); 7247 store_insn = insn; 7248 for (k = 0; k < n_reloads; k++) 7249 { 7250 if (rld[k].in == src_reg) 7251 { 7252 src_reg = rld[k].reg_rtx; 7253 break; 7254 } 7255 } 7256 } 7257 } 7258 else 7259 store_insn = new_spill_reg_store[REGNO (src_reg)]; 7260 if (src_reg && GET_CODE (src_reg) == REG 7261 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER) 7262 { 7263 int src_regno = REGNO (src_reg); 7264 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode); 7265 /* The place where to find a death note varies with 7266 PRESERVE_DEATH_INFO_REGNO_P . The condition is not 7267 necessarily checked exactly in the code that moves 7268 notes, so just check both locations. */ 7269 rtx note = find_regno_note (insn, REG_DEAD, src_regno); 7270 if (! note && store_insn) 7271 note = find_regno_note (store_insn, REG_DEAD, src_regno); 7272 while (nr-- > 0) 7273 { 7274 spill_reg_store[src_regno + nr] = store_insn; 7275 spill_reg_stored_to[src_regno + nr] = out; 7276 reg_reloaded_contents[src_regno + nr] = nregno; 7277 reg_reloaded_insn[src_regno + nr] = store_insn; 7278 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr); 7279 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr); 7280 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr, 7281 GET_MODE (src_reg))) 7282 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, 7283 src_regno + nr); 7284 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr); 7285 if (note) 7286 SET_HARD_REG_BIT (reg_reloaded_died, src_regno); 7287 else 7288 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno); 7289 } 7290 reg_last_reload_reg[nregno] = src_reg; 7291 /* We have to set reg_has_output_reload here, or else 7292 forget_old_reloads_1 will clear reg_last_reload_reg 7293 right away. */ 7294 reg_has_output_reload[nregno] = 1; 7295 } 7296 } 7297 else 7298 { 7299 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out)); 7300 7301 while (num_regs-- > 0) 7302 reg_last_reload_reg[nregno + num_regs] = 0; 7303 } 7304 } 7305 } 7306 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died); 7307} 7308 7309/* Emit code to perform a reload from IN (which may be a reload register) to 7310 OUT (which may also be a reload register). IN or OUT is from operand 7311 OPNUM with reload type TYPE. 7312 7313 Returns first insn emitted. */ 7314 7315rtx 7316gen_reload (rtx out, rtx in, int opnum, enum reload_type type) 7317{ 7318 rtx last = get_last_insn (); 7319 rtx tem; 7320 7321 /* If IN is a paradoxical SUBREG, remove it and try to put the 7322 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ 7323 if (GET_CODE (in) == SUBREG 7324 && (GET_MODE_SIZE (GET_MODE (in)) 7325 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) 7326 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) 7327 in = SUBREG_REG (in), out = tem; 7328 else if (GET_CODE (out) == SUBREG 7329 && (GET_MODE_SIZE (GET_MODE (out)) 7330 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) 7331 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0) 7332 out = SUBREG_REG (out), in = tem; 7333 7334 /* How to do this reload can get quite tricky. Normally, we are being 7335 asked to reload a simple operand, such as a MEM, a constant, or a pseudo 7336 register that didn't get a hard register. In that case we can just 7337 call emit_move_insn. 7338 7339 We can also be asked to reload a PLUS that adds a register or a MEM to 7340 another register, constant or MEM. This can occur during frame pointer 7341 elimination and while reloading addresses. This case is handled by 7342 trying to emit a single insn to perform the add. If it is not valid, 7343 we use a two insn sequence. 7344 7345 Finally, we could be called to handle an 'o' constraint by putting 7346 an address into a register. In that case, we first try to do this 7347 with a named pattern of "reload_load_address". If no such pattern 7348 exists, we just emit a SET insn and hope for the best (it will normally 7349 be valid on machines that use 'o'). 7350 7351 This entire process is made complex because reload will never 7352 process the insns we generate here and so we must ensure that 7353 they will fit their constraints and also by the fact that parts of 7354 IN might be being reloaded separately and replaced with spill registers. 7355 Because of this, we are, in some sense, just guessing the right approach 7356 here. The one listed above seems to work. 7357 7358 ??? At some point, this whole thing needs to be rethought. */ 7359 7360 if (GET_CODE (in) == PLUS 7361 && (GET_CODE (XEXP (in, 0)) == REG 7362 || GET_CODE (XEXP (in, 0)) == SUBREG 7363 || GET_CODE (XEXP (in, 0)) == MEM) 7364 && (GET_CODE (XEXP (in, 1)) == REG 7365 || GET_CODE (XEXP (in, 1)) == SUBREG 7366 || CONSTANT_P (XEXP (in, 1)) 7367 || GET_CODE (XEXP (in, 1)) == MEM)) 7368 { 7369 /* We need to compute the sum of a register or a MEM and another 7370 register, constant, or MEM, and put it into the reload 7371 register. The best possible way of doing this is if the machine 7372 has a three-operand ADD insn that accepts the required operands. 7373 7374 The simplest approach is to try to generate such an insn and see if it 7375 is recognized and matches its constraints. If so, it can be used. 7376 7377 It might be better not to actually emit the insn unless it is valid, 7378 but we need to pass the insn as an operand to `recog' and 7379 `extract_insn' and it is simpler to emit and then delete the insn if 7380 not valid than to dummy things up. */ 7381 7382 rtx op0, op1, tem, insn; 7383 int code; 7384 7385 op0 = find_replacement (&XEXP (in, 0)); 7386 op1 = find_replacement (&XEXP (in, 1)); 7387 7388 /* Since constraint checking is strict, commutativity won't be 7389 checked, so we need to do that here to avoid spurious failure 7390 if the add instruction is two-address and the second operand 7391 of the add is the same as the reload reg, which is frequently 7392 the case. If the insn would be A = B + A, rearrange it so 7393 it will be A = A + B as constrain_operands expects. */ 7394 7395 if (GET_CODE (XEXP (in, 1)) == REG 7396 && REGNO (out) == REGNO (XEXP (in, 1))) 7397 tem = op0, op0 = op1, op1 = tem; 7398 7399 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) 7400 in = gen_rtx_PLUS (GET_MODE (in), op0, op1); 7401 7402 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in)); 7403 code = recog_memoized (insn); 7404 7405 if (code >= 0) 7406 { 7407 extract_insn (insn); 7408 /* We want constrain operands to treat this insn strictly in 7409 its validity determination, i.e., the way it would after reload 7410 has completed. */ 7411 if (constrain_operands (1)) 7412 return insn; 7413 } 7414 7415 delete_insns_since (last); 7416 7417 /* If that failed, we must use a conservative two-insn sequence. 7418 7419 Use a move to copy one operand into the reload register. Prefer 7420 to reload a constant, MEM or pseudo since the move patterns can 7421 handle an arbitrary operand. If OP1 is not a constant, MEM or 7422 pseudo and OP1 is not a valid operand for an add instruction, then 7423 reload OP1. 7424 7425 After reloading one of the operands into the reload register, add 7426 the reload register to the output register. 7427 7428 If there is another way to do this for a specific machine, a 7429 DEFINE_PEEPHOLE should be specified that recognizes the sequence 7430 we emit below. */ 7431 7432 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code; 7433 7434 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG 7435 || (GET_CODE (op1) == REG 7436 && REGNO (op1) >= FIRST_PSEUDO_REGISTER) 7437 || (code != CODE_FOR_nothing 7438 && ! ((*insn_data[code].operand[2].predicate) 7439 (op1, insn_data[code].operand[2].mode)))) 7440 tem = op0, op0 = op1, op1 = tem; 7441 7442 gen_reload (out, op0, opnum, type); 7443 7444 /* If OP0 and OP1 are the same, we can use OUT for OP1. 7445 This fixes a problem on the 32K where the stack pointer cannot 7446 be used as an operand of an add insn. */ 7447 7448 if (rtx_equal_p (op0, op1)) 7449 op1 = out; 7450 7451 insn = emit_insn (gen_add2_insn (out, op1)); 7452 7453 /* If that failed, copy the address register to the reload register. 7454 Then add the constant to the reload register. */ 7455 7456 code = recog_memoized (insn); 7457 7458 if (code >= 0) 7459 { 7460 extract_insn (insn); 7461 /* We want constrain operands to treat this insn strictly in 7462 its validity determination, i.e., the way it would after reload 7463 has completed. */ 7464 if (constrain_operands (1)) 7465 { 7466 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ 7467 REG_NOTES (insn) 7468 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); 7469 return insn; 7470 } 7471 } 7472 7473 delete_insns_since (last); 7474 7475 gen_reload (out, op1, opnum, type); 7476 insn = emit_insn (gen_add2_insn (out, op0)); 7477 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); 7478 } 7479 7480#ifdef SECONDARY_MEMORY_NEEDED 7481 /* If we need a memory location to do the move, do it that way. */ 7482 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG) 7483 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER 7484 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG) 7485 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER 7486 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)), 7487 REGNO_REG_CLASS (reg_or_subregno (out)), 7488 GET_MODE (out))) 7489 { 7490 /* Get the memory to use and rewrite both registers to its mode. */ 7491 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); 7492 7493 if (GET_MODE (loc) != GET_MODE (out)) 7494 out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); 7495 7496 if (GET_MODE (loc) != GET_MODE (in)) 7497 in = gen_rtx_REG (GET_MODE (loc), REGNO (in)); 7498 7499 gen_reload (loc, in, opnum, type); 7500 gen_reload (out, loc, opnum, type); 7501 } 7502#endif 7503 7504 /* If IN is a simple operand, use gen_move_insn. */ 7505 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG) 7506 emit_insn (gen_move_insn (out, in)); 7507 7508#ifdef HAVE_reload_load_address 7509 else if (HAVE_reload_load_address) 7510 emit_insn (gen_reload_load_address (out, in)); 7511#endif 7512 7513 /* Otherwise, just write (set OUT IN) and hope for the best. */ 7514 else 7515 emit_insn (gen_rtx_SET (VOIDmode, out, in)); 7516 7517 /* Return the first insn emitted. 7518 We can not just return get_last_insn, because there may have 7519 been multiple instructions emitted. Also note that gen_move_insn may 7520 emit more than one insn itself, so we can not assume that there is one 7521 insn emitted per emit_insn_before call. */ 7522 7523 return last ? NEXT_INSN (last) : get_insns (); 7524} 7525 7526/* Delete a previously made output-reload whose result we now believe 7527 is not needed. First we double-check. 7528 7529 INSN is the insn now being processed. 7530 LAST_RELOAD_REG is the hard register number for which we want to delete 7531 the last output reload. 7532 J is the reload-number that originally used REG. The caller has made 7533 certain that reload J doesn't use REG any longer for input. */ 7534 7535static void 7536delete_output_reload (rtx insn, int j, int last_reload_reg) 7537{ 7538 rtx output_reload_insn = spill_reg_store[last_reload_reg]; 7539 rtx reg = spill_reg_stored_to[last_reload_reg]; 7540 int k; 7541 int n_occurrences; 7542 int n_inherited = 0; 7543 rtx i1; 7544 rtx substed; 7545 7546 /* It is possible that this reload has been only used to set another reload 7547 we eliminated earlier and thus deleted this instruction too. */ 7548 if (INSN_DELETED_P (output_reload_insn)) 7549 return; 7550 7551 /* Get the raw pseudo-register referred to. */ 7552 7553 while (GET_CODE (reg) == SUBREG) 7554 reg = SUBREG_REG (reg); 7555 substed = reg_equiv_memory_loc[REGNO (reg)]; 7556 7557 /* This is unsafe if the operand occurs more often in the current 7558 insn than it is inherited. */ 7559 for (k = n_reloads - 1; k >= 0; k--) 7560 { 7561 rtx reg2 = rld[k].in; 7562 if (! reg2) 7563 continue; 7564 if (GET_CODE (reg2) == MEM || reload_override_in[k]) 7565 reg2 = rld[k].in_reg; 7566#ifdef AUTO_INC_DEC 7567 if (rld[k].out && ! rld[k].out_reg) 7568 reg2 = XEXP (rld[k].in_reg, 0); 7569#endif 7570 while (GET_CODE (reg2) == SUBREG) 7571 reg2 = SUBREG_REG (reg2); 7572 if (rtx_equal_p (reg2, reg)) 7573 { 7574 if (reload_inherited[k] || reload_override_in[k] || k == j) 7575 { 7576 n_inherited++; 7577 reg2 = rld[k].out_reg; 7578 if (! reg2) 7579 continue; 7580 while (GET_CODE (reg2) == SUBREG) 7581 reg2 = XEXP (reg2, 0); 7582 if (rtx_equal_p (reg2, reg)) 7583 n_inherited++; 7584 } 7585 else 7586 return; 7587 } 7588 } 7589 n_occurrences = count_occurrences (PATTERN (insn), reg, 0); 7590 if (substed) 7591 n_occurrences += count_occurrences (PATTERN (insn), 7592 eliminate_regs (substed, 0, 7593 NULL_RTX), 0); 7594 if (n_occurrences > n_inherited) 7595 return; 7596 7597 /* If the pseudo-reg we are reloading is no longer referenced 7598 anywhere between the store into it and here, 7599 and no jumps or labels intervene, then the value can get 7600 here through the reload reg alone. 7601 Otherwise, give up--return. */ 7602 for (i1 = NEXT_INSN (output_reload_insn); 7603 i1 != insn; i1 = NEXT_INSN (i1)) 7604 { 7605 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN) 7606 return; 7607 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN) 7608 && reg_mentioned_p (reg, PATTERN (i1))) 7609 { 7610 /* If this is USE in front of INSN, we only have to check that 7611 there are no more references than accounted for by inheritance. */ 7612 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE) 7613 { 7614 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; 7615 i1 = NEXT_INSN (i1); 7616 } 7617 if (n_occurrences <= n_inherited && i1 == insn) 7618 break; 7619 return; 7620 } 7621 } 7622 7623 /* We will be deleting the insn. Remove the spill reg information. */ 7624 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; ) 7625 { 7626 spill_reg_store[last_reload_reg + k] = 0; 7627 spill_reg_stored_to[last_reload_reg + k] = 0; 7628 } 7629 7630 /* The caller has already checked that REG dies or is set in INSN. 7631 It has also checked that we are optimizing, and thus some 7632 inaccuracies in the debugging information are acceptable. 7633 So we could just delete output_reload_insn. But in some cases 7634 we can improve the debugging information without sacrificing 7635 optimization - maybe even improving the code: See if the pseudo 7636 reg has been completely replaced with reload regs. If so, delete 7637 the store insn and forget we had a stack slot for the pseudo. */ 7638 if (rld[j].out != rld[j].in 7639 && REG_N_DEATHS (REGNO (reg)) == 1 7640 && REG_N_SETS (REGNO (reg)) == 1 7641 && REG_BASIC_BLOCK (REGNO (reg)) >= 0 7642 && find_regno_note (insn, REG_DEAD, REGNO (reg))) 7643 { 7644 rtx i2; 7645 7646 /* We know that it was used only between here and the beginning of 7647 the current basic block. (We also know that the last use before 7648 INSN was the output reload we are thinking of deleting, but never 7649 mind that.) Search that range; see if any ref remains. */ 7650 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) 7651 { 7652 rtx set = single_set (i2); 7653 7654 /* Uses which just store in the pseudo don't count, 7655 since if they are the only uses, they are dead. */ 7656 if (set != 0 && SET_DEST (set) == reg) 7657 continue; 7658 if (GET_CODE (i2) == CODE_LABEL 7659 || GET_CODE (i2) == JUMP_INSN) 7660 break; 7661 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN) 7662 && reg_mentioned_p (reg, PATTERN (i2))) 7663 { 7664 /* Some other ref remains; just delete the output reload we 7665 know to be dead. */ 7666 delete_address_reloads (output_reload_insn, insn); 7667 delete_insn (output_reload_insn); 7668 return; 7669 } 7670 } 7671 7672 /* Delete the now-dead stores into this pseudo. Note that this 7673 loop also takes care of deleting output_reload_insn. */ 7674 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) 7675 { 7676 rtx set = single_set (i2); 7677 7678 if (set != 0 && SET_DEST (set) == reg) 7679 { 7680 delete_address_reloads (i2, insn); 7681 delete_insn (i2); 7682 } 7683 if (GET_CODE (i2) == CODE_LABEL 7684 || GET_CODE (i2) == JUMP_INSN) 7685 break; 7686 } 7687 7688 /* For the debugging info, say the pseudo lives in this reload reg. */ 7689 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx); 7690 alter_reg (REGNO (reg), -1); 7691 } 7692 else 7693 { 7694 delete_address_reloads (output_reload_insn, insn); 7695 delete_insn (output_reload_insn); 7696 } 7697} 7698 7699/* We are going to delete DEAD_INSN. Recursively delete loads of 7700 reload registers used in DEAD_INSN that are not used till CURRENT_INSN. 7701 CURRENT_INSN is being reloaded, so we have to check its reloads too. */ 7702static void 7703delete_address_reloads (rtx dead_insn, rtx current_insn) 7704{ 7705 rtx set = single_set (dead_insn); 7706 rtx set2, dst, prev, next; 7707 if (set) 7708 { 7709 rtx dst = SET_DEST (set); 7710 if (GET_CODE (dst) == MEM) 7711 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn); 7712 } 7713 /* If we deleted the store from a reloaded post_{in,de}c expression, 7714 we can delete the matching adds. */ 7715 prev = PREV_INSN (dead_insn); 7716 next = NEXT_INSN (dead_insn); 7717 if (! prev || ! next) 7718 return; 7719 set = single_set (next); 7720 set2 = single_set (prev); 7721 if (! set || ! set2 7722 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS 7723 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT 7724 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT) 7725 return; 7726 dst = SET_DEST (set); 7727 if (! rtx_equal_p (dst, SET_DEST (set2)) 7728 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0)) 7729 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0)) 7730 || (INTVAL (XEXP (SET_SRC (set), 1)) 7731 != -INTVAL (XEXP (SET_SRC (set2), 1)))) 7732 return; 7733 delete_related_insns (prev); 7734 delete_related_insns (next); 7735} 7736 7737/* Subfunction of delete_address_reloads: process registers found in X. */ 7738static void 7739delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn) 7740{ 7741 rtx prev, set, dst, i2; 7742 int i, j; 7743 enum rtx_code code = GET_CODE (x); 7744 7745 if (code != REG) 7746 { 7747 const char *fmt = GET_RTX_FORMAT (code); 7748 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 7749 { 7750 if (fmt[i] == 'e') 7751 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn); 7752 else if (fmt[i] == 'E') 7753 { 7754 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 7755 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j), 7756 current_insn); 7757 } 7758 } 7759 return; 7760 } 7761 7762 if (spill_reg_order[REGNO (x)] < 0) 7763 return; 7764 7765 /* Scan backwards for the insn that sets x. This might be a way back due 7766 to inheritance. */ 7767 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev)) 7768 { 7769 code = GET_CODE (prev); 7770 if (code == CODE_LABEL || code == JUMP_INSN) 7771 return; 7772 if (GET_RTX_CLASS (code) != 'i') 7773 continue; 7774 if (reg_set_p (x, PATTERN (prev))) 7775 break; 7776 if (reg_referenced_p (x, PATTERN (prev))) 7777 return; 7778 } 7779 if (! prev || INSN_UID (prev) < reload_first_uid) 7780 return; 7781 /* Check that PREV only sets the reload register. */ 7782 set = single_set (prev); 7783 if (! set) 7784 return; 7785 dst = SET_DEST (set); 7786 if (GET_CODE (dst) != REG 7787 || ! rtx_equal_p (dst, x)) 7788 return; 7789 if (! reg_set_p (dst, PATTERN (dead_insn))) 7790 { 7791 /* Check if DST was used in a later insn - 7792 it might have been inherited. */ 7793 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2)) 7794 { 7795 if (GET_CODE (i2) == CODE_LABEL) 7796 break; 7797 if (! INSN_P (i2)) 7798 continue; 7799 if (reg_referenced_p (dst, PATTERN (i2))) 7800 { 7801 /* If there is a reference to the register in the current insn, 7802 it might be loaded in a non-inherited reload. If no other 7803 reload uses it, that means the register is set before 7804 referenced. */ 7805 if (i2 == current_insn) 7806 { 7807 for (j = n_reloads - 1; j >= 0; j--) 7808 if ((rld[j].reg_rtx == dst && reload_inherited[j]) 7809 || reload_override_in[j] == dst) 7810 return; 7811 for (j = n_reloads - 1; j >= 0; j--) 7812 if (rld[j].in && rld[j].reg_rtx == dst) 7813 break; 7814 if (j >= 0) 7815 break; 7816 } 7817 return; 7818 } 7819 if (GET_CODE (i2) == JUMP_INSN) 7820 break; 7821 /* If DST is still live at CURRENT_INSN, check if it is used for 7822 any reload. Note that even if CURRENT_INSN sets DST, we still 7823 have to check the reloads. */ 7824 if (i2 == current_insn) 7825 { 7826 for (j = n_reloads - 1; j >= 0; j--) 7827 if ((rld[j].reg_rtx == dst && reload_inherited[j]) 7828 || reload_override_in[j] == dst) 7829 return; 7830 /* ??? We can't finish the loop here, because dst might be 7831 allocated to a pseudo in this block if no reload in this 7832 block needs any of the classes containing DST - see 7833 spill_hard_reg. There is no easy way to tell this, so we 7834 have to scan till the end of the basic block. */ 7835 } 7836 if (reg_set_p (dst, PATTERN (i2))) 7837 break; 7838 } 7839 } 7840 delete_address_reloads_1 (prev, SET_SRC (set), current_insn); 7841 reg_reloaded_contents[REGNO (dst)] = -1; 7842 delete_insn (prev); 7843} 7844 7845/* Output reload-insns to reload VALUE into RELOADREG. 7846 VALUE is an autoincrement or autodecrement RTX whose operand 7847 is a register or memory location; 7848 so reloading involves incrementing that location. 7849 IN is either identical to VALUE, or some cheaper place to reload from. 7850 7851 INC_AMOUNT is the number to increment or decrement by (always positive). 7852 This cannot be deduced from VALUE. 7853 7854 Return the instruction that stores into RELOADREG. */ 7855 7856static rtx 7857inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount) 7858{ 7859 /* REG or MEM to be copied and incremented. */ 7860 rtx incloc = XEXP (value, 0); 7861 /* Nonzero if increment after copying. */ 7862 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC); 7863 rtx last; 7864 rtx inc; 7865 rtx add_insn; 7866 int code; 7867 rtx store; 7868 rtx real_in = in == value ? XEXP (in, 0) : in; 7869 7870 /* No hard register is equivalent to this register after 7871 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero, 7872 we could inc/dec that register as well (maybe even using it for 7873 the source), but I'm not sure it's worth worrying about. */ 7874 if (GET_CODE (incloc) == REG) 7875 reg_last_reload_reg[REGNO (incloc)] = 0; 7876 7877 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) 7878 inc_amount = -inc_amount; 7879 7880 inc = GEN_INT (inc_amount); 7881 7882 /* If this is post-increment, first copy the location to the reload reg. */ 7883 if (post && real_in != reloadreg) 7884 emit_insn (gen_move_insn (reloadreg, real_in)); 7885 7886 if (in == value) 7887 { 7888 /* See if we can directly increment INCLOC. Use a method similar to 7889 that in gen_reload. */ 7890 7891 last = get_last_insn (); 7892 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc, 7893 gen_rtx_PLUS (GET_MODE (incloc), 7894 incloc, inc))); 7895 7896 code = recog_memoized (add_insn); 7897 if (code >= 0) 7898 { 7899 extract_insn (add_insn); 7900 if (constrain_operands (1)) 7901 { 7902 /* If this is a pre-increment and we have incremented the value 7903 where it lives, copy the incremented value to RELOADREG to 7904 be used as an address. */ 7905 7906 if (! post) 7907 emit_insn (gen_move_insn (reloadreg, incloc)); 7908 7909 return add_insn; 7910 } 7911 } 7912 delete_insns_since (last); 7913 } 7914 7915 /* If couldn't do the increment directly, must increment in RELOADREG. 7916 The way we do this depends on whether this is pre- or post-increment. 7917 For pre-increment, copy INCLOC to the reload register, increment it 7918 there, then save back. */ 7919 7920 if (! post) 7921 { 7922 if (in != reloadreg) 7923 emit_insn (gen_move_insn (reloadreg, real_in)); 7924 emit_insn (gen_add2_insn (reloadreg, inc)); 7925 store = emit_insn (gen_move_insn (incloc, reloadreg)); 7926 } 7927 else 7928 { 7929 /* Postincrement. 7930 Because this might be a jump insn or a compare, and because RELOADREG 7931 may not be available after the insn in an input reload, we must do 7932 the incrementation before the insn being reloaded for. 7933 7934 We have already copied IN to RELOADREG. Increment the copy in 7935 RELOADREG, save that back, then decrement RELOADREG so it has 7936 the original value. */ 7937 7938 emit_insn (gen_add2_insn (reloadreg, inc)); 7939 store = emit_insn (gen_move_insn (incloc, reloadreg)); 7940 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount))); 7941 } 7942 7943 return store; 7944} 7945 7946#ifdef AUTO_INC_DEC 7947static void 7948add_auto_inc_notes (rtx insn, rtx x) 7949{ 7950 enum rtx_code code = GET_CODE (x); 7951 const char *fmt; 7952 int i, j; 7953 7954 if (code == MEM && auto_inc_p (XEXP (x, 0))) 7955 { 7956 REG_NOTES (insn) 7957 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn)); 7958 return; 7959 } 7960 7961 /* Scan all the operand sub-expressions. */ 7962 fmt = GET_RTX_FORMAT (code); 7963 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 7964 { 7965 if (fmt[i] == 'e') 7966 add_auto_inc_notes (insn, XEXP (x, i)); 7967 else if (fmt[i] == 'E') 7968 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 7969 add_auto_inc_notes (insn, XVECEXP (x, i, j)); 7970 } 7971} 7972#endif 7973 7974/* Copy EH notes from an insn to its reloads. */ 7975static void 7976copy_eh_notes (rtx insn, rtx x) 7977{ 7978 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); 7979 if (eh_note) 7980 { 7981 for (; x != 0; x = NEXT_INSN (x)) 7982 { 7983 if (may_trap_p (PATTERN (x))) 7984 REG_NOTES (x) 7985 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0), 7986 REG_NOTES (x)); 7987 } 7988 } 7989} 7990 7991/* This is used by reload pass, that does emit some instructions after 7992 abnormal calls moving basic block end, but in fact it wants to emit 7993 them on the edge. Looks for abnormal call edges, find backward the 7994 proper call and fix the damage. 7995 7996 Similar handle instructions throwing exceptions internally. */ 7997void 7998fixup_abnormal_edges (void) 7999{ 8000 bool inserted = false; 8001 basic_block bb; 8002 8003 FOR_EACH_BB (bb) 8004 { 8005 edge e; 8006 8007 /* Look for cases we are interested in - calls or instructions causing 8008 exceptions. */ 8009 for (e = bb->succ; e; e = e->succ_next) 8010 { 8011 if (e->flags & EDGE_ABNORMAL_CALL) 8012 break; 8013 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH)) 8014 == (EDGE_ABNORMAL | EDGE_EH)) 8015 break; 8016 } 8017 if (e && GET_CODE (BB_END (bb)) != CALL_INSN 8018 && !can_throw_internal (BB_END (bb))) 8019 { 8020 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb)); 8021 rtx next; 8022 for (e = bb->succ; e; e = e->succ_next) 8023 if (e->flags & EDGE_FALLTHRU) 8024 break; 8025 /* Get past the new insns generated. Allow notes, as the insns may 8026 be already deleted. */ 8027 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE) 8028 && !can_throw_internal (insn) 8029 && insn != BB_HEAD (bb)) 8030 insn = PREV_INSN (insn); 8031 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn)) 8032 abort (); 8033 BB_END (bb) = insn; 8034 inserted = true; 8035 insn = NEXT_INSN (insn); 8036 while (insn && insn != stop) 8037 { 8038 next = NEXT_INSN (insn); 8039 if (INSN_P (insn)) 8040 { 8041 delete_insn (insn); 8042 8043 /* Sometimes there's still the return value USE. 8044 If it's placed after a trapping call (i.e. that 8045 call is the last insn anyway), we have no fallthru 8046 edge. Simply delete this use and don't try to insert 8047 on the non-existent edge. */ 8048 if (GET_CODE (PATTERN (insn)) != USE) 8049 { 8050 /* We're not deleting it, we're moving it. */ 8051 INSN_DELETED_P (insn) = 0; 8052 PREV_INSN (insn) = NULL_RTX; 8053 NEXT_INSN (insn) = NULL_RTX; 8054 8055 insert_insn_on_edge (insn, e); 8056 } 8057 } 8058 insn = next; 8059 } 8060 } 8061 } 8062 /* We've possibly turned single trapping insn into multiple ones. */ 8063 if (flag_non_call_exceptions) 8064 { 8065 sbitmap blocks; 8066 blocks = sbitmap_alloc (last_basic_block); 8067 sbitmap_ones (blocks); 8068 find_many_sub_basic_blocks (blocks); 8069 } 8070 if (inserted) 8071 commit_edge_insertions (); 8072} 8073