regclass.c revision 90075
1/* Compute register class preferences for pseudo-registers. 2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996 3 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify it under 8the terms of the GNU General Public License as published by the Free 9Software Foundation; either version 2, or (at your option) any later 10version. 11 12GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13WARRANTY; without even the implied warranty of MERCHANTABILITY or 14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING. If not, write to the Free 19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 2002111-1307, USA. */ 21 22 23/* This file contains two passes of the compiler: reg_scan and reg_class. 24 It also defines some tables of information about the hardware registers 25 and a function init_reg_sets to initialize the tables. */ 26 27#include "config.h" 28#include "system.h" 29#include "rtl.h" 30#include "expr.h" 31#include "tm_p.h" 32#include "hard-reg-set.h" 33#include "flags.h" 34#include "basic-block.h" 35#include "regs.h" 36#include "function.h" 37#include "insn-config.h" 38#include "recog.h" 39#include "reload.h" 40#include "real.h" 41#include "toplev.h" 42#include "output.h" 43#include "ggc.h" 44 45#ifndef REGISTER_MOVE_COST 46#define REGISTER_MOVE_COST(m, x, y) 2 47#endif 48 49static void init_reg_sets_1 PARAMS ((void)); 50static void init_reg_modes PARAMS ((void)); 51 52/* If we have auto-increment or auto-decrement and we can have secondary 53 reloads, we are not allowed to use classes requiring secondary 54 reloads for pseudos auto-incremented since reload can't handle it. */ 55 56#ifdef AUTO_INC_DEC 57#if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) 58#define FORBIDDEN_INC_DEC_CLASSES 59#endif 60#endif 61 62/* Register tables used by many passes. */ 63 64/* Indexed by hard register number, contains 1 for registers 65 that are fixed use (stack pointer, pc, frame pointer, etc.). 66 These are the registers that cannot be used to allocate 67 a pseudo reg for general use. */ 68 69char fixed_regs[FIRST_PSEUDO_REGISTER]; 70 71/* Same info as a HARD_REG_SET. */ 72 73HARD_REG_SET fixed_reg_set; 74 75/* Data for initializing the above. */ 76 77static const char initial_fixed_regs[] = FIXED_REGISTERS; 78 79/* Indexed by hard register number, contains 1 for registers 80 that are fixed use or are clobbered by function calls. 81 These are the registers that cannot be used to allocate 82 a pseudo reg whose life crosses calls unless we are able 83 to save/restore them across the calls. */ 84 85char call_used_regs[FIRST_PSEUDO_REGISTER]; 86 87/* Same info as a HARD_REG_SET. */ 88 89HARD_REG_SET call_used_reg_set; 90 91/* HARD_REG_SET of registers we want to avoid caller saving. */ 92HARD_REG_SET losing_caller_save_reg_set; 93 94/* Data for initializing the above. */ 95 96static const char initial_call_used_regs[] = CALL_USED_REGISTERS; 97 98/* This is much like call_used_regs, except it doesn't have to 99 be a superset of FIXED_REGISTERS. This vector indicates 100 what is really call clobbered, and is used when defining 101 regs_invalidated_by_call. */ 102 103#ifdef CALL_REALLY_USED_REGISTERS 104char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; 105#endif 106 107/* Indexed by hard register number, contains 1 for registers that are 108 fixed use or call used registers that cannot hold quantities across 109 calls even if we are willing to save and restore them. call fixed 110 registers are a subset of call used registers. */ 111 112char call_fixed_regs[FIRST_PSEUDO_REGISTER]; 113 114/* The same info as a HARD_REG_SET. */ 115 116HARD_REG_SET call_fixed_reg_set; 117 118/* Number of non-fixed registers. */ 119 120int n_non_fixed_regs; 121 122/* Indexed by hard register number, contains 1 for registers 123 that are being used for global register decls. 124 These must be exempt from ordinary flow analysis 125 and are also considered fixed. */ 126 127char global_regs[FIRST_PSEUDO_REGISTER]; 128 129/* Contains 1 for registers that are set or clobbered by calls. */ 130/* ??? Ideally, this would be just call_used_regs plus global_regs, but 131 for someone's bright idea to have call_used_regs strictly include 132 fixed_regs. Which leaves us guessing as to the set of fixed_regs 133 that are actually preserved. We know for sure that those associated 134 with the local stack frame are safe, but scant others. */ 135 136HARD_REG_SET regs_invalidated_by_call; 137 138/* Table of register numbers in the order in which to try to use them. */ 139#ifdef REG_ALLOC_ORDER 140int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; 141 142/* The inverse of reg_alloc_order. */ 143int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER]; 144#endif 145 146/* For each reg class, a HARD_REG_SET saying which registers are in it. */ 147 148HARD_REG_SET reg_class_contents[N_REG_CLASSES]; 149 150/* The same information, but as an array of unsigned ints. We copy from 151 these unsigned ints to the table above. We do this so the tm.h files 152 do not have to be aware of the wordsize for machines with <= 64 regs. 153 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ 154 155#define N_REG_INTS \ 156 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32) 157 158static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] 159 = REG_CLASS_CONTENTS; 160 161/* For each reg class, number of regs it contains. */ 162 163unsigned int reg_class_size[N_REG_CLASSES]; 164 165/* For each reg class, table listing all the containing classes. */ 166 167enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; 168 169/* For each reg class, table listing all the classes contained in it. */ 170 171enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; 172 173/* For each pair of reg classes, 174 a largest reg class contained in their union. */ 175 176enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; 177 178/* For each pair of reg classes, 179 the smallest reg class containing their union. */ 180 181enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; 182 183/* Array containing all of the register names. Unless 184 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */ 185 186#ifdef DEBUG_REGISTER_NAMES 187const char * reg_names[] = REGISTER_NAMES; 188#endif 189 190/* For each hard register, the widest mode object that it can contain. 191 This will be a MODE_INT mode if the register can hold integers. Otherwise 192 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the 193 register. */ 194 195enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; 196 197/* 1 if class does contain register of given mode. */ 198 199static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE]; 200 201/* Maximum cost of moving from a register in one class to a register in 202 another class. Based on REGISTER_MOVE_COST. */ 203 204static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; 205 206/* Similar, but here we don't have to move if the first index is a subset 207 of the second so in that case the cost is zero. */ 208 209static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; 210 211/* Similar, but here we don't have to move if the first index is a superset 212 of the second so in that case the cost is zero. */ 213 214static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; 215 216#ifdef FORBIDDEN_INC_DEC_CLASSES 217 218/* These are the classes that regs which are auto-incremented or decremented 219 cannot be put in. */ 220 221static int forbidden_inc_dec_class[N_REG_CLASSES]; 222 223/* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec 224 context. */ 225 226static char *in_inc_dec; 227 228#endif /* FORBIDDEN_INC_DEC_CLASSES */ 229 230#ifdef CLASS_CANNOT_CHANGE_MODE 231 232/* These are the classes containing only registers that can be used in 233 a SUBREG expression that changes the mode of the register in some 234 way that is illegal. */ 235 236static int class_can_change_mode[N_REG_CLASSES]; 237 238/* Registers, including pseudos, which change modes in some way that 239 is illegal. */ 240 241static regset reg_changes_mode; 242 243#endif /* CLASS_CANNOT_CHANGE_MODE */ 244 245#ifdef HAVE_SECONDARY_RELOADS 246 247/* Sample MEM values for use by memory_move_secondary_cost. */ 248 249static rtx top_of_stack[MAX_MACHINE_MODE]; 250 251#endif /* HAVE_SECONDARY_RELOADS */ 252 253/* Linked list of reg_info structures allocated for reg_n_info array. 254 Grouping all of the allocated structures together in one lump 255 means only one call to bzero to clear them, rather than n smaller 256 calls. */ 257struct reg_info_data { 258 struct reg_info_data *next; /* next set of reg_info structures */ 259 size_t min_index; /* minimum index # */ 260 size_t max_index; /* maximum index # */ 261 char used_p; /* non-zero if this has been used previously */ 262 reg_info data[1]; /* beginning of the reg_info data */ 263}; 264 265static struct reg_info_data *reg_info_head; 266 267/* No more global register variables may be declared; true once 268 regclass has been initialized. */ 269 270static int no_global_reg_vars = 0; 271 272 273/* Function called only once to initialize the above data on reg usage. 274 Once this is done, various switches may override. */ 275 276void 277init_reg_sets () 278{ 279 int i, j; 280 281 /* First copy the register information from the initial int form into 282 the regsets. */ 283 284 for (i = 0; i < N_REG_CLASSES; i++) 285 { 286 CLEAR_HARD_REG_SET (reg_class_contents[i]); 287 288 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ 289 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 290 if (int_reg_class_contents[i][j / 32] 291 & ((unsigned) 1 << (j % 32))) 292 SET_HARD_REG_BIT (reg_class_contents[i], j); 293 } 294 295 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); 296 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); 297 memset (global_regs, 0, sizeof global_regs); 298 299 /* Do any additional initialization regsets may need */ 300 INIT_ONCE_REG_SET (); 301 302#ifdef REG_ALLOC_ORDER 303 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 304 inv_reg_alloc_order[reg_alloc_order[i]] = i; 305#endif 306} 307 308/* After switches have been processed, which perhaps alter 309 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ 310 311static void 312init_reg_sets_1 () 313{ 314 unsigned int i, j; 315 unsigned int /* enum machine_mode */ m; 316 char allocatable_regs_of_mode [MAX_MACHINE_MODE]; 317 318 /* This macro allows the fixed or call-used registers 319 and the register classes to depend on target flags. */ 320 321#ifdef CONDITIONAL_REGISTER_USAGE 322 CONDITIONAL_REGISTER_USAGE; 323#endif 324 325 /* Compute number of hard regs in each class. */ 326 327 memset ((char *) reg_class_size, 0, sizeof reg_class_size); 328 for (i = 0; i < N_REG_CLASSES; i++) 329 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 330 if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 331 reg_class_size[i]++; 332 333 /* Initialize the table of subunions. 334 reg_class_subunion[I][J] gets the largest-numbered reg-class 335 that is contained in the union of classes I and J. */ 336 337 for (i = 0; i < N_REG_CLASSES; i++) 338 { 339 for (j = 0; j < N_REG_CLASSES; j++) 340 { 341#ifdef HARD_REG_SET 342 register /* Declare it register if it's a scalar. */ 343#endif 344 HARD_REG_SET c; 345 int k; 346 347 COPY_HARD_REG_SET (c, reg_class_contents[i]); 348 IOR_HARD_REG_SET (c, reg_class_contents[j]); 349 for (k = 0; k < N_REG_CLASSES; k++) 350 { 351 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, 352 subclass1); 353 continue; 354 355 subclass1: 356 /* keep the largest subclass */ /* SPEE 900308 */ 357 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], 358 reg_class_contents[(int) reg_class_subunion[i][j]], 359 subclass2); 360 reg_class_subunion[i][j] = (enum reg_class) k; 361 subclass2: 362 ; 363 } 364 } 365 } 366 367 /* Initialize the table of superunions. 368 reg_class_superunion[I][J] gets the smallest-numbered reg-class 369 containing the union of classes I and J. */ 370 371 for (i = 0; i < N_REG_CLASSES; i++) 372 { 373 for (j = 0; j < N_REG_CLASSES; j++) 374 { 375#ifdef HARD_REG_SET 376 register /* Declare it register if it's a scalar. */ 377#endif 378 HARD_REG_SET c; 379 int k; 380 381 COPY_HARD_REG_SET (c, reg_class_contents[i]); 382 IOR_HARD_REG_SET (c, reg_class_contents[j]); 383 for (k = 0; k < N_REG_CLASSES; k++) 384 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); 385 386 superclass: 387 reg_class_superunion[i][j] = (enum reg_class) k; 388 } 389 } 390 391 /* Initialize the tables of subclasses and superclasses of each reg class. 392 First clear the whole table, then add the elements as they are found. */ 393 394 for (i = 0; i < N_REG_CLASSES; i++) 395 { 396 for (j = 0; j < N_REG_CLASSES; j++) 397 { 398 reg_class_superclasses[i][j] = LIM_REG_CLASSES; 399 reg_class_subclasses[i][j] = LIM_REG_CLASSES; 400 } 401 } 402 403 for (i = 0; i < N_REG_CLASSES; i++) 404 { 405 if (i == (int) NO_REGS) 406 continue; 407 408 for (j = i + 1; j < N_REG_CLASSES; j++) 409 { 410 enum reg_class *p; 411 412 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], 413 subclass); 414 continue; 415 subclass: 416 /* Reg class I is a subclass of J. 417 Add J to the table of superclasses of I. */ 418 p = ®_class_superclasses[i][0]; 419 while (*p != LIM_REG_CLASSES) p++; 420 *p = (enum reg_class) j; 421 /* Add I to the table of superclasses of J. */ 422 p = ®_class_subclasses[j][0]; 423 while (*p != LIM_REG_CLASSES) p++; 424 *p = (enum reg_class) i; 425 } 426 } 427 428 /* Initialize "constant" tables. */ 429 430 CLEAR_HARD_REG_SET (fixed_reg_set); 431 CLEAR_HARD_REG_SET (call_used_reg_set); 432 CLEAR_HARD_REG_SET (call_fixed_reg_set); 433 CLEAR_HARD_REG_SET (regs_invalidated_by_call); 434 435 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs); 436 437 n_non_fixed_regs = 0; 438 439 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 440 { 441 if (fixed_regs[i]) 442 SET_HARD_REG_BIT (fixed_reg_set, i); 443 else 444 n_non_fixed_regs++; 445 446 if (call_used_regs[i]) 447 SET_HARD_REG_BIT (call_used_reg_set, i); 448 if (call_fixed_regs[i]) 449 SET_HARD_REG_BIT (call_fixed_reg_set, i); 450 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) 451 SET_HARD_REG_BIT (losing_caller_save_reg_set, i); 452 453 /* There are a couple of fixed registers that we know are safe to 454 exclude from being clobbered by calls: 455 456 The frame pointer is always preserved across calls. The arg pointer 457 is if it is fixed. The stack pointer usually is, unless 458 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present. 459 If we are generating PIC code, the PIC offset table register is 460 preserved across calls, though the target can override that. */ 461 462 if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM) 463 ; 464#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 465 else if (i == HARD_FRAME_POINTER_REGNUM) 466 ; 467#endif 468#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM 469 else if (i == ARG_POINTER_REGNUM && fixed_regs[i]) 470 ; 471#endif 472#ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 473 else if (i == PIC_OFFSET_TABLE_REGNUM && fixed_regs[i]) 474 ; 475#endif 476 else if (0 477#ifdef CALL_REALLY_USED_REGISTERS 478 || call_really_used_regs[i] 479#else 480 || call_used_regs[i] 481#endif 482 || global_regs[i]) 483 SET_HARD_REG_BIT (regs_invalidated_by_call, i); 484 } 485 486 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode)); 487 memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode)); 488 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) 489 for (i = 0; i < N_REG_CLASSES; i++) 490 if (CLASS_MAX_NREGS (i, m) <= reg_class_size[i]) 491 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 492 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j) 493 && HARD_REGNO_MODE_OK (j, m)) 494 { 495 contains_reg_of_mode [i][m] = 1; 496 allocatable_regs_of_mode [m] = 1; 497 break; 498 } 499 500 /* Initialize the move cost table. Find every subset of each class 501 and take the maximum cost of moving any subset to any other. */ 502 503 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) 504 if (allocatable_regs_of_mode [m]) 505 { 506 for (i = 0; i < N_REG_CLASSES; i++) 507 if (contains_reg_of_mode [i][m]) 508 for (j = 0; j < N_REG_CLASSES; j++) 509 { 510 int cost; 511 enum reg_class *p1, *p2; 512 513 if (!contains_reg_of_mode [j][m]) 514 { 515 move_cost[m][i][j] = 65536; 516 may_move_in_cost[m][i][j] = 65536; 517 may_move_out_cost[m][i][j] = 65536; 518 } 519 else 520 { 521 cost = REGISTER_MOVE_COST (m, i, j); 522 523 for (p2 = ®_class_subclasses[j][0]; 524 *p2 != LIM_REG_CLASSES; 525 p2++) 526 if (*p2 != i && contains_reg_of_mode [*p2][m]) 527 cost = MAX (cost, move_cost [m][i][*p2]); 528 529 for (p1 = ®_class_subclasses[i][0]; 530 *p1 != LIM_REG_CLASSES; 531 p1++) 532 if (*p1 != j && contains_reg_of_mode [*p1][m]) 533 cost = MAX (cost, move_cost [m][*p1][j]); 534 535 move_cost[m][i][j] = cost; 536 537 if (reg_class_subset_p (i, j)) 538 may_move_in_cost[m][i][j] = 0; 539 else 540 may_move_in_cost[m][i][j] = cost; 541 542 if (reg_class_subset_p (j, i)) 543 may_move_out_cost[m][i][j] = 0; 544 else 545 may_move_out_cost[m][i][j] = cost; 546 } 547 } 548 else 549 for (j = 0; j < N_REG_CLASSES; j++) 550 { 551 move_cost[m][i][j] = 65536; 552 may_move_in_cost[m][i][j] = 65536; 553 may_move_out_cost[m][i][j] = 65536; 554 } 555 } 556 557#ifdef CLASS_CANNOT_CHANGE_MODE 558 { 559 HARD_REG_SET c; 560 COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]); 561 562 for (i = 0; i < N_REG_CLASSES; i++) 563 { 564 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class); 565 class_can_change_mode [i] = 0; 566 continue; 567 ok_class: 568 class_can_change_mode [i] = 1; 569 } 570 } 571#endif /* CLASS_CANNOT_CHANGE_MODE */ 572} 573 574/* Compute the table of register modes. 575 These values are used to record death information for individual registers 576 (as opposed to a multi-register mode). */ 577 578static void 579init_reg_modes () 580{ 581 int i; 582 583 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 584 { 585 reg_raw_mode[i] = choose_hard_reg_mode (i, 1); 586 587 /* If we couldn't find a valid mode, just use the previous mode. 588 ??? One situation in which we need to do this is on the mips where 589 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like 590 to use DF mode for the even registers and VOIDmode for the odd 591 (for the cpu models where the odd ones are inaccessible). */ 592 if (reg_raw_mode[i] == VOIDmode) 593 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; 594 } 595} 596 597/* Finish initializing the register sets and 598 initialize the register modes. */ 599 600void 601init_regs () 602{ 603 /* This finishes what was started by init_reg_sets, but couldn't be done 604 until after register usage was specified. */ 605 init_reg_sets_1 (); 606 607 init_reg_modes (); 608 609#ifdef HAVE_SECONDARY_RELOADS 610 { 611 /* Make some fake stack-frame MEM references for use in 612 memory_move_secondary_cost. */ 613 int i; 614 615 for (i = 0; i < MAX_MACHINE_MODE; i++) 616 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); 617 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE); 618 } 619#endif 620} 621 622#ifdef HAVE_SECONDARY_RELOADS 623 624/* Compute extra cost of moving registers to/from memory due to reloads. 625 Only needed if secondary reloads are required for memory moves. */ 626 627int 628memory_move_secondary_cost (mode, class, in) 629 enum machine_mode mode; 630 enum reg_class class; 631 int in; 632{ 633 enum reg_class altclass; 634 int partial_cost = 0; 635 /* We need a memory reference to feed to SECONDARY... macros. */ 636 /* mem may be unused even if the SECONDARY_ macros are defined. */ 637 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; 638 639 640 if (in) 641 { 642#ifdef SECONDARY_INPUT_RELOAD_CLASS 643 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); 644#else 645 altclass = NO_REGS; 646#endif 647 } 648 else 649 { 650#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 651 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); 652#else 653 altclass = NO_REGS; 654#endif 655 } 656 657 if (altclass == NO_REGS) 658 return 0; 659 660 if (in) 661 partial_cost = REGISTER_MOVE_COST (mode, altclass, class); 662 else 663 partial_cost = REGISTER_MOVE_COST (mode, class, altclass); 664 665 if (class == altclass) 666 /* This isn't simply a copy-to-temporary situation. Can't guess 667 what it is, so MEMORY_MOVE_COST really ought not to be calling 668 here in that case. 669 670 I'm tempted to put in an abort here, but returning this will 671 probably only give poor estimates, which is what we would've 672 had before this code anyways. */ 673 return partial_cost; 674 675 /* Check if the secondary reload register will also need a 676 secondary reload. */ 677 return memory_move_secondary_cost (mode, altclass, in) + partial_cost; 678} 679#endif 680 681/* Return a machine mode that is legitimate for hard reg REGNO and large 682 enough to save nregs. If we can't find one, return VOIDmode. */ 683 684enum machine_mode 685choose_hard_reg_mode (regno, nregs) 686 unsigned int regno ATTRIBUTE_UNUSED; 687 unsigned int nregs; 688{ 689 unsigned int /* enum machine_mode */ m; 690 enum machine_mode found_mode = VOIDmode, mode; 691 692 /* We first look for the largest integer mode that can be validly 693 held in REGNO. If none, we look for the largest floating-point mode. 694 If we still didn't find a valid mode, try CCmode. */ 695 696 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); 697 mode != VOIDmode; 698 mode = GET_MODE_WIDER_MODE (mode)) 699 if (HARD_REGNO_NREGS (regno, mode) == nregs 700 && HARD_REGNO_MODE_OK (regno, mode)) 701 found_mode = mode; 702 703 if (found_mode != VOIDmode) 704 return found_mode; 705 706 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); 707 mode != VOIDmode; 708 mode = GET_MODE_WIDER_MODE (mode)) 709 if (HARD_REGNO_NREGS (regno, mode) == nregs 710 && HARD_REGNO_MODE_OK (regno, mode)) 711 found_mode = mode; 712 713 if (found_mode != VOIDmode) 714 return found_mode; 715 716 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); 717 mode != VOIDmode; 718 mode = GET_MODE_WIDER_MODE (mode)) 719 if (HARD_REGNO_NREGS (regno, mode) == nregs 720 && HARD_REGNO_MODE_OK (regno, mode)) 721 found_mode = mode; 722 723 if (found_mode != VOIDmode) 724 return found_mode; 725 726 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); 727 mode != VOIDmode; 728 mode = GET_MODE_WIDER_MODE (mode)) 729 if (HARD_REGNO_NREGS (regno, mode) == nregs 730 && HARD_REGNO_MODE_OK (regno, mode)) 731 found_mode = mode; 732 733 if (found_mode != VOIDmode) 734 return found_mode; 735 736 /* Iterate over all of the CCmodes. */ 737 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m) 738 { 739 mode = (enum machine_mode) m; 740 if (HARD_REGNO_NREGS (regno, mode) == nregs 741 && HARD_REGNO_MODE_OK (regno, mode)) 742 return mode; 743 } 744 745 /* We can't find a mode valid for this register. */ 746 return VOIDmode; 747} 748 749/* Specify the usage characteristics of the register named NAME. 750 It should be a fixed register if FIXED and a 751 call-used register if CALL_USED. */ 752 753void 754fix_register (name, fixed, call_used) 755 const char *name; 756 int fixed, call_used; 757{ 758 int i; 759 760 /* Decode the name and update the primary form of 761 the register info. */ 762 763 if ((i = decode_reg_name (name)) >= 0) 764 { 765 if ((i == STACK_POINTER_REGNUM 766#ifdef HARD_FRAME_POINTER_REGNUM 767 || i == HARD_FRAME_POINTER_REGNUM 768#else 769 || i == FRAME_POINTER_REGNUM 770#endif 771 ) 772 && (fixed == 0 || call_used == 0)) 773 { 774 static const char * const what_option[2][2] = { 775 { "call-saved", "call-used" }, 776 { "no-such-option", "fixed" }}; 777 778 error ("can't use '%s' as a %s register", name, 779 what_option[fixed][call_used]); 780 } 781 else 782 { 783 fixed_regs[i] = fixed; 784 call_used_regs[i] = call_used; 785#ifdef CALL_REALLY_USED_REGISTERS 786 if (fixed == 0) 787 call_really_used_regs[i] = call_used; 788#endif 789 } 790 } 791 else 792 { 793 warning ("unknown register name: %s", name); 794 } 795} 796 797/* Mark register number I as global. */ 798 799void 800globalize_reg (i) 801 int i; 802{ 803 if (fixed_regs[i] == 0 && no_global_reg_vars) 804 error ("global register variable follows a function definition"); 805 806 if (global_regs[i]) 807 { 808 warning ("register used for two global register variables"); 809 return; 810 } 811 812 if (call_used_regs[i] && ! fixed_regs[i]) 813 warning ("call-clobbered register used for global register variable"); 814 815 global_regs[i] = 1; 816 817 /* If already fixed, nothing else to do. */ 818 if (fixed_regs[i]) 819 return; 820 821 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; 822 n_non_fixed_regs--; 823 824 SET_HARD_REG_BIT (fixed_reg_set, i); 825 SET_HARD_REG_BIT (call_used_reg_set, i); 826 SET_HARD_REG_BIT (call_fixed_reg_set, i); 827} 828 829/* Now the data and code for the `regclass' pass, which happens 830 just before local-alloc. */ 831 832/* The `costs' struct records the cost of using a hard register of each class 833 and of using memory for each pseudo. We use this data to set up 834 register class preferences. */ 835 836struct costs 837{ 838 int cost[N_REG_CLASSES]; 839 int mem_cost; 840}; 841 842/* Structure used to record preferrences of given pseudo. */ 843struct reg_pref 844{ 845 /* (enum reg_class) prefclass is the preferred class. */ 846 char prefclass; 847 848 /* altclass is a register class that we should use for allocating 849 pseudo if no register in the preferred class is available. 850 If no register in this class is available, memory is preferred. 851 852 It might appear to be more general to have a bitmask of classes here, 853 but since it is recommended that there be a class corresponding to the 854 union of most major pair of classes, that generality is not required. */ 855 char altclass; 856}; 857 858/* Record the cost of each class for each pseudo. */ 859 860static struct costs *costs; 861 862/* Initialized once, and used to initialize cost values for each insn. */ 863 864static struct costs init_cost; 865 866/* Record preferrences of each pseudo. 867 This is available after `regclass' is run. */ 868 869static struct reg_pref *reg_pref; 870 871/* Allocated buffers for reg_pref. */ 872 873static struct reg_pref *reg_pref_buffer; 874 875/* Frequency of executions of current insn. */ 876 877static int frequency; 878 879static rtx scan_one_insn PARAMS ((rtx, int)); 880static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *)); 881static void dump_regclass PARAMS ((FILE *)); 882static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *, 883 const char **, rtx, 884 struct costs *, struct reg_pref *)); 885static int copy_cost PARAMS ((rtx, enum machine_mode, 886 enum reg_class, int)); 887static void record_address_regs PARAMS ((rtx, enum reg_class, int)); 888#ifdef FORBIDDEN_INC_DEC_CLASSES 889static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode)); 890#endif 891static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int)); 892 893/* Return the reg_class in which pseudo reg number REGNO is best allocated. 894 This function is sometimes called before the info has been computed. 895 When that happens, just return GENERAL_REGS, which is innocuous. */ 896 897enum reg_class 898reg_preferred_class (regno) 899 int regno; 900{ 901 if (reg_pref == 0) 902 return GENERAL_REGS; 903 return (enum reg_class) reg_pref[regno].prefclass; 904} 905 906enum reg_class 907reg_alternate_class (regno) 908 int regno; 909{ 910 if (reg_pref == 0) 911 return ALL_REGS; 912 913 return (enum reg_class) reg_pref[regno].altclass; 914} 915 916/* Initialize some global data for this pass. */ 917 918void 919regclass_init () 920{ 921 int i; 922 923 init_cost.mem_cost = 10000; 924 for (i = 0; i < N_REG_CLASSES; i++) 925 init_cost.cost[i] = 10000; 926 927 /* This prevents dump_flow_info from losing if called 928 before regclass is run. */ 929 reg_pref = NULL; 930 931 /* No more global register variables may be declared. */ 932 no_global_reg_vars = 1; 933} 934 935/* Dump register costs. */ 936static void 937dump_regclass (dump) 938 FILE *dump; 939{ 940 static const char *const reg_class_names[] = REG_CLASS_NAMES; 941 int i; 942 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 943 { 944 int /* enum reg_class */ class; 945 if (REG_N_REFS (i)) 946 { 947 fprintf (dump, " Register %i costs:", i); 948 for (class = 0; class < (int) N_REG_CLASSES; class++) 949 if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)] 950#ifdef FORBIDDEN_INC_DEC_CLASSES 951 && (!in_inc_dec[i] 952 || !forbidden_inc_dec_class[(enum reg_class) class]) 953#endif 954#ifdef CLASS_CANNOT_CHANGE_MODE 955 && (!REGNO_REG_SET_P (reg_changes_mode, i) 956 || class_can_change_mode [(enum reg_class) class]) 957#endif 958 ) 959 fprintf (dump, " %s:%i", reg_class_names[class], 960 costs[i].cost[(enum reg_class) class]); 961 fprintf (dump, " MEM:%i\n", costs[i].mem_cost); 962 } 963 } 964} 965 966 967/* Calculate the costs of insn operands. */ 968 969static void 970record_operand_costs (insn, op_costs, reg_pref) 971 rtx insn; 972 struct costs *op_costs; 973 struct reg_pref *reg_pref; 974{ 975 const char *constraints[MAX_RECOG_OPERANDS]; 976 enum machine_mode modes[MAX_RECOG_OPERANDS]; 977 int i; 978 979 for (i = 0; i < recog_data.n_operands; i++) 980 { 981 constraints[i] = recog_data.constraints[i]; 982 modes[i] = recog_data.operand_mode[i]; 983 } 984 985 /* If we get here, we are set up to record the costs of all the 986 operands for this insn. Start by initializing the costs. 987 Then handle any address registers. Finally record the desired 988 classes for any pseudos, doing it twice if some pair of 989 operands are commutative. */ 990 991 for (i = 0; i < recog_data.n_operands; i++) 992 { 993 op_costs[i] = init_cost; 994 995 if (GET_CODE (recog_data.operand[i]) == SUBREG) 996 { 997 rtx inner = SUBREG_REG (recog_data.operand[i]); 998#ifdef CLASS_CANNOT_CHANGE_MODE 999 if (GET_CODE (inner) == REG 1000 && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner))) 1001 SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner)); 1002#endif 1003 recog_data.operand[i] = inner; 1004 } 1005 1006 if (GET_CODE (recog_data.operand[i]) == MEM) 1007 record_address_regs (XEXP (recog_data.operand[i], 0), 1008 MODE_BASE_REG_CLASS (modes[i]), frequency * 2); 1009 else if (constraints[i][0] == 'p') 1010 record_address_regs (recog_data.operand[i], 1011 MODE_BASE_REG_CLASS (modes[i]), frequency * 2); 1012 } 1013 1014 /* Check for commutative in a separate loop so everything will 1015 have been initialized. We must do this even if one operand 1016 is a constant--see addsi3 in m68k.md. */ 1017 1018 for (i = 0; i < (int) recog_data.n_operands - 1; i++) 1019 if (constraints[i][0] == '%') 1020 { 1021 const char *xconstraints[MAX_RECOG_OPERANDS]; 1022 int j; 1023 1024 /* Handle commutative operands by swapping the constraints. 1025 We assume the modes are the same. */ 1026 1027 for (j = 0; j < recog_data.n_operands; j++) 1028 xconstraints[j] = constraints[j]; 1029 1030 xconstraints[i] = constraints[i+1]; 1031 xconstraints[i+1] = constraints[i]; 1032 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, 1033 recog_data.operand, modes, 1034 xconstraints, insn, op_costs, reg_pref); 1035 } 1036 1037 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, 1038 recog_data.operand, modes, 1039 constraints, insn, op_costs, reg_pref); 1040} 1041 1042/* Subroutine of regclass, processes one insn INSN. Scan it and record each 1043 time it would save code to put a certain register in a certain class. 1044 PASS, when nonzero, inhibits some optimizations which need only be done 1045 once. 1046 Return the last insn processed, so that the scan can be continued from 1047 there. */ 1048 1049static rtx 1050scan_one_insn (insn, pass) 1051 rtx insn; 1052 int pass; 1053{ 1054 enum rtx_code code = GET_CODE (insn); 1055 enum rtx_code pat_code; 1056 rtx set, note; 1057 int i, j; 1058 struct costs op_costs[MAX_RECOG_OPERANDS]; 1059 1060 if (GET_RTX_CLASS (code) != 'i') 1061 return insn; 1062 1063 pat_code = GET_CODE (PATTERN (insn)); 1064 if (pat_code == USE 1065 || pat_code == CLOBBER 1066 || pat_code == ASM_INPUT 1067 || pat_code == ADDR_VEC 1068 || pat_code == ADDR_DIFF_VEC) 1069 return insn; 1070 1071 set = single_set (insn); 1072 extract_insn (insn); 1073 1074 /* If this insn loads a parameter from its stack slot, then 1075 it represents a savings, rather than a cost, if the 1076 parameter is stored in memory. Record this fact. */ 1077 1078 if (set != 0 && GET_CODE (SET_DEST (set)) == REG 1079 && GET_CODE (SET_SRC (set)) == MEM 1080 && (note = find_reg_note (insn, REG_EQUIV, 1081 NULL_RTX)) != 0 1082 && GET_CODE (XEXP (note, 0)) == MEM) 1083 { 1084 costs[REGNO (SET_DEST (set))].mem_cost 1085 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), 1086 GENERAL_REGS, 1) 1087 * frequency); 1088 record_address_regs (XEXP (SET_SRC (set), 0), 1089 MODE_BASE_REG_CLASS (VOIDmode), frequency * 2); 1090 return insn; 1091 } 1092 1093 /* Improve handling of two-address insns such as 1094 (set X (ashift CONST Y)) where CONST must be made to 1095 match X. Change it into two insns: (set X CONST) 1096 (set X (ashift X Y)). If we left this for reloading, it 1097 would probably get three insns because X and Y might go 1098 in the same place. This prevents X and Y from receiving 1099 the same hard reg. 1100 1101 We can only do this if the modes of operands 0 and 1 1102 (which might not be the same) are tieable and we only need 1103 do this during our first pass. */ 1104 1105 if (pass == 0 && optimize 1106 && recog_data.n_operands >= 3 1107 && recog_data.constraints[1][0] == '0' 1108 && recog_data.constraints[1][1] == 0 1109 && CONSTANT_P (recog_data.operand[1]) 1110 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1]) 1111 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2]) 1112 && GET_CODE (recog_data.operand[0]) == REG 1113 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]), 1114 recog_data.operand_mode[1])) 1115 { 1116 rtx previnsn = prev_real_insn (insn); 1117 rtx dest 1118 = gen_lowpart (recog_data.operand_mode[1], 1119 recog_data.operand[0]); 1120 rtx newinsn 1121 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn); 1122 1123 /* If this insn was the start of a basic block, 1124 include the new insn in that block. 1125 We need not check for code_label here; 1126 while a basic block can start with a code_label, 1127 INSN could not be at the beginning of that block. */ 1128 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) 1129 { 1130 int b; 1131 for (b = 0; b < n_basic_blocks; b++) 1132 if (insn == BLOCK_HEAD (b)) 1133 BLOCK_HEAD (b) = newinsn; 1134 } 1135 1136 /* This makes one more setting of new insns's dest. */ 1137 REG_N_SETS (REGNO (recog_data.operand[0]))++; 1138 REG_N_REFS (REGNO (recog_data.operand[0]))++; 1139 REG_FREQ (REGNO (recog_data.operand[0])) += frequency; 1140 1141 *recog_data.operand_loc[1] = recog_data.operand[0]; 1142 REG_N_REFS (REGNO (recog_data.operand[0]))++; 1143 REG_FREQ (REGNO (recog_data.operand[0])) += frequency; 1144 for (i = recog_data.n_dups - 1; i >= 0; i--) 1145 if (recog_data.dup_num[i] == 1) 1146 { 1147 *recog_data.dup_loc[i] = recog_data.operand[0]; 1148 REG_N_REFS (REGNO (recog_data.operand[0]))++; 1149 REG_FREQ (REGNO (recog_data.operand[0])) += frequency; 1150 } 1151 1152 return PREV_INSN (newinsn); 1153 } 1154 1155 record_operand_costs (insn, op_costs, reg_pref); 1156 1157 /* Now add the cost for each operand to the total costs for 1158 its register. */ 1159 1160 for (i = 0; i < recog_data.n_operands; i++) 1161 if (GET_CODE (recog_data.operand[i]) == REG 1162 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) 1163 { 1164 int regno = REGNO (recog_data.operand[i]); 1165 struct costs *p = &costs[regno], *q = &op_costs[i]; 1166 1167 p->mem_cost += q->mem_cost * frequency; 1168 for (j = 0; j < N_REG_CLASSES; j++) 1169 p->cost[j] += q->cost[j] * frequency; 1170 } 1171 1172 return insn; 1173} 1174 1175/* This is a pass of the compiler that scans all instructions 1176 and calculates the preferred class for each pseudo-register. 1177 This information can be accessed later by calling `reg_preferred_class'. 1178 This pass comes just before local register allocation. */ 1179 1180void 1181regclass (f, nregs, dump) 1182 rtx f; 1183 int nregs; 1184 FILE *dump; 1185{ 1186 rtx insn; 1187 int i; 1188 int pass; 1189 1190 init_recog (); 1191 1192 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs)); 1193 1194#ifdef CLASS_CANNOT_CHANGE_MODE 1195 reg_changes_mode = BITMAP_XMALLOC (); 1196#endif 1197 1198#ifdef FORBIDDEN_INC_DEC_CLASSES 1199 1200 in_inc_dec = (char *) xmalloc (nregs); 1201 1202 /* Initialize information about which register classes can be used for 1203 pseudos that are auto-incremented or auto-decremented. It would 1204 seem better to put this in init_reg_sets, but we need to be able 1205 to allocate rtx, which we can't do that early. */ 1206 1207 for (i = 0; i < N_REG_CLASSES; i++) 1208 { 1209 rtx r = gen_rtx_REG (VOIDmode, 0); 1210 enum machine_mode m; 1211 int j; 1212 1213 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 1214 if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 1215 { 1216 REGNO (r) = j; 1217 1218 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; 1219 m = (enum machine_mode) ((int) m + 1)) 1220 if (HARD_REGNO_MODE_OK (j, m)) 1221 { 1222 PUT_MODE (r, m); 1223 1224 /* If a register is not directly suitable for an 1225 auto-increment or decrement addressing mode and 1226 requires secondary reloads, disallow its class from 1227 being used in such addresses. */ 1228 1229 if ((0 1230#ifdef SECONDARY_RELOAD_CLASS 1231 || (SECONDARY_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) 1232 != NO_REGS) 1233#else 1234#ifdef SECONDARY_INPUT_RELOAD_CLASS 1235 || (SECONDARY_INPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) 1236 != NO_REGS) 1237#endif 1238#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1239 || (SECONDARY_OUTPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) 1240 != NO_REGS) 1241#endif 1242#endif 1243 ) 1244 && ! auto_inc_dec_reg_p (r, m)) 1245 forbidden_inc_dec_class[i] = 1; 1246 } 1247 } 1248 } 1249#endif /* FORBIDDEN_INC_DEC_CLASSES */ 1250 1251 /* Normally we scan the insns once and determine the best class to use for 1252 each register. However, if -fexpensive_optimizations are on, we do so 1253 twice, the second time using the tentative best classes to guide the 1254 selection. */ 1255 1256 for (pass = 0; pass <= flag_expensive_optimizations; pass++) 1257 { 1258 int index; 1259 1260 if (dump) 1261 fprintf (dump, "\n\nPass %i\n\n",pass); 1262 /* Zero out our accumulation of the cost of each class for each reg. */ 1263 1264 memset ((char *) costs, 0, nregs * sizeof (struct costs)); 1265 1266#ifdef FORBIDDEN_INC_DEC_CLASSES 1267 memset (in_inc_dec, 0, nregs); 1268#endif 1269 1270 /* Scan the instructions and record each time it would 1271 save code to put a certain register in a certain class. */ 1272 1273 if (!optimize) 1274 { 1275 frequency = REG_FREQ_MAX; 1276 for (insn = f; insn; insn = NEXT_INSN (insn)) 1277 insn = scan_one_insn (insn, pass); 1278 } 1279 else 1280 for (index = 0; index < n_basic_blocks; index++) 1281 { 1282 basic_block bb = BASIC_BLOCK (index); 1283 1284 /* Show that an insn inside a loop is likely to be executed three 1285 times more than insns outside a loop. This is much more 1286 aggressive than the assumptions made elsewhere and is being 1287 tried as an experiment. */ 1288 frequency = REG_FREQ_FROM_BB (bb); 1289 for (insn = bb->head; ; insn = NEXT_INSN (insn)) 1290 { 1291 insn = scan_one_insn (insn, pass); 1292 if (insn == bb->end) 1293 break; 1294 } 1295 } 1296 1297 /* Now for each register look at how desirable each class is 1298 and find which class is preferred. Store that in 1299 `prefclass'. Record in `altclass' the largest register 1300 class any of whose registers is better than memory. */ 1301 1302 if (pass == 0) 1303 reg_pref = reg_pref_buffer; 1304 1305 if (dump) 1306 { 1307 dump_regclass (dump); 1308 fprintf (dump,"\n"); 1309 } 1310 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) 1311 { 1312 int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; 1313 enum reg_class best = ALL_REGS, alt = NO_REGS; 1314 /* This is an enum reg_class, but we call it an int 1315 to save lots of casts. */ 1316 int class; 1317 struct costs *p = &costs[i]; 1318 1319 /* In non-optimizing compilation REG_N_REFS is not initialized 1320 yet. */ 1321 if (optimize && !REG_N_REFS (i)) 1322 continue; 1323 1324 for (class = (int) ALL_REGS - 1; class > 0; class--) 1325 { 1326 /* Ignore classes that are too small for this operand or 1327 invalid for an operand that was auto-incremented. */ 1328 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)] 1329#ifdef FORBIDDEN_INC_DEC_CLASSES 1330 || (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1331#endif 1332#ifdef CLASS_CANNOT_CHANGE_MODE 1333 || (REGNO_REG_SET_P (reg_changes_mode, i) 1334 && ! class_can_change_mode [class]) 1335#endif 1336 ) 1337 ; 1338 else if (p->cost[class] < best_cost) 1339 { 1340 best_cost = p->cost[class]; 1341 best = (enum reg_class) class; 1342 } 1343 else if (p->cost[class] == best_cost) 1344 best = reg_class_subunion[(int) best][class]; 1345 } 1346 1347 /* Record the alternate register class; i.e., a class for which 1348 every register in it is better than using memory. If adding a 1349 class would make a smaller class (i.e., no union of just those 1350 classes exists), skip that class. The major unions of classes 1351 should be provided as a register class. Don't do this if we 1352 will be doing it again later. */ 1353 1354 if ((pass == 1 || dump) || ! flag_expensive_optimizations) 1355 for (class = 0; class < N_REG_CLASSES; class++) 1356 if (p->cost[class] < p->mem_cost 1357 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] 1358 > reg_class_size[(int) alt]) 1359#ifdef FORBIDDEN_INC_DEC_CLASSES 1360 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1361#endif 1362#ifdef CLASS_CANNOT_CHANGE_MODE 1363 && ! (REGNO_REG_SET_P (reg_changes_mode, i) 1364 && ! class_can_change_mode [class]) 1365#endif 1366 ) 1367 alt = reg_class_subunion[(int) alt][class]; 1368 1369 /* If we don't add any classes, nothing to try. */ 1370 if (alt == best) 1371 alt = NO_REGS; 1372 1373 if (dump 1374 && (reg_pref[i].prefclass != (int) best 1375 || reg_pref[i].altclass != (int) alt)) 1376 { 1377 static const char *const reg_class_names[] = REG_CLASS_NAMES; 1378 fprintf (dump, " Register %i", i); 1379 if (alt == ALL_REGS || best == ALL_REGS) 1380 fprintf (dump, " pref %s\n", reg_class_names[(int) best]); 1381 else if (alt == NO_REGS) 1382 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]); 1383 else 1384 fprintf (dump, " pref %s, else %s\n", 1385 reg_class_names[(int) best], 1386 reg_class_names[(int) alt]); 1387 } 1388 1389 /* We cast to (int) because (char) hits bugs in some compilers. */ 1390 reg_pref[i].prefclass = (int) best; 1391 reg_pref[i].altclass = (int) alt; 1392 } 1393 } 1394 1395#ifdef FORBIDDEN_INC_DEC_CLASSES 1396 free (in_inc_dec); 1397#endif 1398#ifdef CLASS_CANNOT_CHANGE_MODE 1399 BITMAP_XFREE (reg_changes_mode); 1400#endif 1401 free (costs); 1402} 1403 1404/* Record the cost of using memory or registers of various classes for 1405 the operands in INSN. 1406 1407 N_ALTS is the number of alternatives. 1408 1409 N_OPS is the number of operands. 1410 1411 OPS is an array of the operands. 1412 1413 MODES are the modes of the operands, in case any are VOIDmode. 1414 1415 CONSTRAINTS are the constraints to use for the operands. This array 1416 is modified by this procedure. 1417 1418 This procedure works alternative by alternative. For each alternative 1419 we assume that we will be able to allocate all pseudos to their ideal 1420 register class and calculate the cost of using that alternative. Then 1421 we compute for each operand that is a pseudo-register, the cost of 1422 having the pseudo allocated to each register class and using it in that 1423 alternative. To this cost is added the cost of the alternative. 1424 1425 The cost of each class for this insn is its lowest cost among all the 1426 alternatives. */ 1427 1428static void 1429record_reg_classes (n_alts, n_ops, ops, modes, 1430 constraints, insn, op_costs, reg_pref) 1431 int n_alts; 1432 int n_ops; 1433 rtx *ops; 1434 enum machine_mode *modes; 1435 const char **constraints; 1436 rtx insn; 1437 struct costs *op_costs; 1438 struct reg_pref *reg_pref; 1439{ 1440 int alt; 1441 int i, j; 1442 rtx set; 1443 1444 /* Process each alternative, each time minimizing an operand's cost with 1445 the cost for each operand in that alternative. */ 1446 1447 for (alt = 0; alt < n_alts; alt++) 1448 { 1449 struct costs this_op_costs[MAX_RECOG_OPERANDS]; 1450 int alt_fail = 0; 1451 int alt_cost = 0; 1452 enum reg_class classes[MAX_RECOG_OPERANDS]; 1453 int allows_mem[MAX_RECOG_OPERANDS]; 1454 int class; 1455 1456 for (i = 0; i < n_ops; i++) 1457 { 1458 const char *p = constraints[i]; 1459 rtx op = ops[i]; 1460 enum machine_mode mode = modes[i]; 1461 int allows_addr = 0; 1462 int win = 0; 1463 unsigned char c; 1464 1465 /* Initially show we know nothing about the register class. */ 1466 classes[i] = NO_REGS; 1467 allows_mem[i] = 0; 1468 1469 /* If this operand has no constraints at all, we can conclude 1470 nothing about it since anything is valid. */ 1471 1472 if (*p == 0) 1473 { 1474 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1475 memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]); 1476 1477 continue; 1478 } 1479 1480 /* If this alternative is only relevant when this operand 1481 matches a previous operand, we do different things depending 1482 on whether this operand is a pseudo-reg or not. We must process 1483 any modifiers for the operand before we can make this test. */ 1484 1485 while (*p == '%' || *p == '=' || *p == '+' || *p == '&') 1486 p++; 1487 1488 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) 1489 { 1490 /* Copy class and whether memory is allowed from the matching 1491 alternative. Then perform any needed cost computations 1492 and/or adjustments. */ 1493 j = p[0] - '0'; 1494 classes[i] = classes[j]; 1495 allows_mem[i] = allows_mem[j]; 1496 1497 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) 1498 { 1499 /* If this matches the other operand, we have no added 1500 cost and we win. */ 1501 if (rtx_equal_p (ops[j], op)) 1502 win = 1; 1503 1504 /* If we can put the other operand into a register, add to 1505 the cost of this alternative the cost to copy this 1506 operand to the register used for the other operand. */ 1507 1508 else if (classes[j] != NO_REGS) 1509 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; 1510 } 1511 else if (GET_CODE (ops[j]) != REG 1512 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) 1513 { 1514 /* This op is a pseudo but the one it matches is not. */ 1515 1516 /* If we can't put the other operand into a register, this 1517 alternative can't be used. */ 1518 1519 if (classes[j] == NO_REGS) 1520 alt_fail = 1; 1521 1522 /* Otherwise, add to the cost of this alternative the cost 1523 to copy the other operand to the register used for this 1524 operand. */ 1525 1526 else 1527 alt_cost += copy_cost (ops[j], mode, classes[j], 1); 1528 } 1529 else 1530 { 1531 /* The costs of this operand are not the same as the other 1532 operand since move costs are not symmetric. Moreover, 1533 if we cannot tie them, this alternative needs to do a 1534 copy, which is one instruction. */ 1535 1536 struct costs *pp = &this_op_costs[i]; 1537 1538 for (class = 0; class < N_REG_CLASSES; class++) 1539 pp->cost[class] 1540 = ((recog_data.operand_type[i] != OP_OUT 1541 ? may_move_in_cost[mode][class][(int) classes[i]] 1542 : 0) 1543 + (recog_data.operand_type[i] != OP_IN 1544 ? may_move_out_cost[mode][(int) classes[i]][class] 1545 : 0)); 1546 1547 /* If the alternative actually allows memory, make things 1548 a bit cheaper since we won't need an extra insn to 1549 load it. */ 1550 1551 pp->mem_cost 1552 = ((recog_data.operand_type[i] != OP_IN 1553 ? MEMORY_MOVE_COST (mode, classes[i], 0) 1554 : 0) 1555 + (recog_data.operand_type[i] != OP_OUT 1556 ? MEMORY_MOVE_COST (mode, classes[i], 1) 1557 : 0) - allows_mem[i]); 1558 1559 /* If we have assigned a class to this register in our 1560 first pass, add a cost to this alternative corresponding 1561 to what we would add if this register were not in the 1562 appropriate class. */ 1563 1564 if (reg_pref) 1565 alt_cost 1566 += (may_move_in_cost[mode] 1567 [(unsigned char) reg_pref[REGNO (op)].prefclass] 1568 [(int) classes[i]]); 1569 1570 if (REGNO (ops[i]) != REGNO (ops[j]) 1571 && ! find_reg_note (insn, REG_DEAD, op)) 1572 alt_cost += 2; 1573 1574 /* This is in place of ordinary cost computation 1575 for this operand, so skip to the end of the 1576 alternative (should be just one character). */ 1577 while (*p && *p++ != ',') 1578 ; 1579 1580 constraints[i] = p; 1581 continue; 1582 } 1583 } 1584 1585 /* Scan all the constraint letters. See if the operand matches 1586 any of the constraints. Collect the valid register classes 1587 and see if this operand accepts memory. */ 1588 1589 while (*p && (c = *p++) != ',') 1590 switch (c) 1591 { 1592 case '*': 1593 /* Ignore the next letter for this pass. */ 1594 p++; 1595 break; 1596 1597 case '?': 1598 alt_cost += 2; 1599 case '!': case '#': case '&': 1600 case '0': case '1': case '2': case '3': case '4': 1601 case '5': case '6': case '7': case '8': case '9': 1602 break; 1603 1604 case 'p': 1605 allows_addr = 1; 1606 win = address_operand (op, GET_MODE (op)); 1607 /* We know this operand is an address, so we want it to be 1608 allocated to a register that can be the base of an 1609 address, ie BASE_REG_CLASS. */ 1610 classes[i] 1611 = reg_class_subunion[(int) classes[i]] 1612 [(int) MODE_BASE_REG_CLASS (VOIDmode)]; 1613 break; 1614 1615 case 'm': case 'o': case 'V': 1616 /* It doesn't seem worth distinguishing between offsettable 1617 and non-offsettable addresses here. */ 1618 allows_mem[i] = 1; 1619 if (GET_CODE (op) == MEM) 1620 win = 1; 1621 break; 1622 1623 case '<': 1624 if (GET_CODE (op) == MEM 1625 && (GET_CODE (XEXP (op, 0)) == PRE_DEC 1626 || GET_CODE (XEXP (op, 0)) == POST_DEC)) 1627 win = 1; 1628 break; 1629 1630 case '>': 1631 if (GET_CODE (op) == MEM 1632 && (GET_CODE (XEXP (op, 0)) == PRE_INC 1633 || GET_CODE (XEXP (op, 0)) == POST_INC)) 1634 win = 1; 1635 break; 1636 1637 case 'E': 1638#ifndef REAL_ARITHMETIC 1639 /* Match any floating double constant, but only if 1640 we can examine the bits of it reliably. */ 1641 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT 1642 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) 1643 && GET_MODE (op) != VOIDmode && ! flag_pretend_float) 1644 break; 1645#endif 1646 if (GET_CODE (op) == CONST_DOUBLE) 1647 win = 1; 1648 break; 1649 1650 case 'F': 1651 if (GET_CODE (op) == CONST_DOUBLE) 1652 win = 1; 1653 break; 1654 1655 case 'G': 1656 case 'H': 1657 if (GET_CODE (op) == CONST_DOUBLE 1658 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) 1659 win = 1; 1660 break; 1661 1662 case 's': 1663 if (GET_CODE (op) == CONST_INT 1664 || (GET_CODE (op) == CONST_DOUBLE 1665 && GET_MODE (op) == VOIDmode)) 1666 break; 1667 case 'i': 1668 if (CONSTANT_P (op) 1669#ifdef LEGITIMATE_PIC_OPERAND_P 1670 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1671#endif 1672 ) 1673 win = 1; 1674 break; 1675 1676 case 'n': 1677 if (GET_CODE (op) == CONST_INT 1678 || (GET_CODE (op) == CONST_DOUBLE 1679 && GET_MODE (op) == VOIDmode)) 1680 win = 1; 1681 break; 1682 1683 case 'I': 1684 case 'J': 1685 case 'K': 1686 case 'L': 1687 case 'M': 1688 case 'N': 1689 case 'O': 1690 case 'P': 1691 if (GET_CODE (op) == CONST_INT 1692 && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) 1693 win = 1; 1694 break; 1695 1696 case 'X': 1697 win = 1; 1698 break; 1699 1700 case 'g': 1701 if (GET_CODE (op) == MEM 1702 || (CONSTANT_P (op) 1703#ifdef LEGITIMATE_PIC_OPERAND_P 1704 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1705#endif 1706 )) 1707 win = 1; 1708 allows_mem[i] = 1; 1709 case 'r': 1710 classes[i] 1711 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; 1712 break; 1713 1714 default: 1715 if (REG_CLASS_FROM_LETTER (c) != NO_REGS) 1716 classes[i] 1717 = reg_class_subunion[(int) classes[i]] 1718 [(int) REG_CLASS_FROM_LETTER (c)]; 1719#ifdef EXTRA_CONSTRAINT 1720 else if (EXTRA_CONSTRAINT (op, c)) 1721 win = 1; 1722#endif 1723 break; 1724 } 1725 1726 constraints[i] = p; 1727 1728 /* How we account for this operand now depends on whether it is a 1729 pseudo register or not. If it is, we first check if any 1730 register classes are valid. If not, we ignore this alternative, 1731 since we want to assume that all pseudos get allocated for 1732 register preferencing. If some register class is valid, compute 1733 the costs of moving the pseudo into that class. */ 1734 1735 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1736 { 1737 if (classes[i] == NO_REGS) 1738 { 1739 /* We must always fail if the operand is a REG, but 1740 we did not find a suitable class. 1741 1742 Otherwise we may perform an uninitialized read 1743 from this_op_costs after the `continue' statement 1744 below. */ 1745 alt_fail = 1; 1746 } 1747 else 1748 { 1749 struct costs *pp = &this_op_costs[i]; 1750 1751 for (class = 0; class < N_REG_CLASSES; class++) 1752 pp->cost[class] 1753 = ((recog_data.operand_type[i] != OP_OUT 1754 ? may_move_in_cost[mode][class][(int) classes[i]] 1755 : 0) 1756 + (recog_data.operand_type[i] != OP_IN 1757 ? may_move_out_cost[mode][(int) classes[i]][class] 1758 : 0)); 1759 1760 /* If the alternative actually allows memory, make things 1761 a bit cheaper since we won't need an extra insn to 1762 load it. */ 1763 1764 pp->mem_cost 1765 = ((recog_data.operand_type[i] != OP_IN 1766 ? MEMORY_MOVE_COST (mode, classes[i], 0) 1767 : 0) 1768 + (recog_data.operand_type[i] != OP_OUT 1769 ? MEMORY_MOVE_COST (mode, classes[i], 1) 1770 : 0) - allows_mem[i]); 1771 1772 /* If we have assigned a class to this register in our 1773 first pass, add a cost to this alternative corresponding 1774 to what we would add if this register were not in the 1775 appropriate class. */ 1776 1777 if (reg_pref) 1778 alt_cost 1779 += (may_move_in_cost[mode] 1780 [(unsigned char) reg_pref[REGNO (op)].prefclass] 1781 [(int) classes[i]]); 1782 } 1783 } 1784 1785 /* Otherwise, if this alternative wins, either because we 1786 have already determined that or if we have a hard register of 1787 the proper class, there is no cost for this alternative. */ 1788 1789 else if (win 1790 || (GET_CODE (op) == REG 1791 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) 1792 ; 1793 1794 /* If registers are valid, the cost of this alternative includes 1795 copying the object to and/or from a register. */ 1796 1797 else if (classes[i] != NO_REGS) 1798 { 1799 if (recog_data.operand_type[i] != OP_OUT) 1800 alt_cost += copy_cost (op, mode, classes[i], 1); 1801 1802 if (recog_data.operand_type[i] != OP_IN) 1803 alt_cost += copy_cost (op, mode, classes[i], 0); 1804 } 1805 1806 /* The only other way this alternative can be used is if this is a 1807 constant that could be placed into memory. */ 1808 1809 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) 1810 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); 1811 else 1812 alt_fail = 1; 1813 } 1814 1815 if (alt_fail) 1816 continue; 1817 1818 /* Finally, update the costs with the information we've calculated 1819 about this alternative. */ 1820 1821 for (i = 0; i < n_ops; i++) 1822 if (GET_CODE (ops[i]) == REG 1823 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1824 { 1825 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; 1826 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); 1827 1828 pp->mem_cost = MIN (pp->mem_cost, 1829 (qq->mem_cost + alt_cost) * scale); 1830 1831 for (class = 0; class < N_REG_CLASSES; class++) 1832 pp->cost[class] = MIN (pp->cost[class], 1833 (qq->cost[class] + alt_cost) * scale); 1834 } 1835 } 1836 1837 /* If this insn is a single set copying operand 1 to operand 0 1838 and one operand is a pseudo with the other a hard reg or a pseudo 1839 that prefers a register that is in its own register class then 1840 we may want to adjust the cost of that register class to -1. 1841 1842 Avoid the adjustment if the source does not die to avoid stressing of 1843 register allocator by preferrencing two coliding registers into single 1844 class. 1845 1846 Also avoid the adjustment if a copy between registers of the class 1847 is expensive (ten times the cost of a default copy is considered 1848 arbitrarily expensive). This avoids losing when the preferred class 1849 is very expensive as the source of a copy instruction. */ 1850 1851 if ((set = single_set (insn)) != 0 1852 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) 1853 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG 1854 && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) 1855 for (i = 0; i <= 1; i++) 1856 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1857 { 1858 unsigned int regno = REGNO (ops[!i]); 1859 enum machine_mode mode = GET_MODE (ops[!i]); 1860 int class; 1861 unsigned int nr; 1862 1863 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0) 1864 { 1865 enum reg_class pref = reg_pref[regno].prefclass; 1866 1867 if ((reg_class_size[(unsigned char) pref] 1868 == CLASS_MAX_NREGS (pref, mode)) 1869 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2) 1870 op_costs[i].cost[(unsigned char) pref] = -1; 1871 } 1872 else if (regno < FIRST_PSEUDO_REGISTER) 1873 for (class = 0; class < N_REG_CLASSES; class++) 1874 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) 1875 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) 1876 { 1877 if (reg_class_size[class] == 1) 1878 op_costs[i].cost[class] = -1; 1879 else 1880 { 1881 for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++) 1882 { 1883 if (! TEST_HARD_REG_BIT (reg_class_contents[class], 1884 regno + nr)) 1885 break; 1886 } 1887 1888 if (nr == HARD_REGNO_NREGS (regno,mode)) 1889 op_costs[i].cost[class] = -1; 1890 } 1891 } 1892 } 1893} 1894 1895/* Compute the cost of loading X into (if TO_P is non-zero) or from (if 1896 TO_P is zero) a register of class CLASS in mode MODE. 1897 1898 X must not be a pseudo. */ 1899 1900static int 1901copy_cost (x, mode, class, to_p) 1902 rtx x; 1903 enum machine_mode mode ATTRIBUTE_UNUSED; 1904 enum reg_class class; 1905 int to_p ATTRIBUTE_UNUSED; 1906{ 1907#ifdef HAVE_SECONDARY_RELOADS 1908 enum reg_class secondary_class = NO_REGS; 1909#endif 1910 1911 /* If X is a SCRATCH, there is actually nothing to move since we are 1912 assuming optimal allocation. */ 1913 1914 if (GET_CODE (x) == SCRATCH) 1915 return 0; 1916 1917 /* Get the class we will actually use for a reload. */ 1918 class = PREFERRED_RELOAD_CLASS (x, class); 1919 1920#ifdef HAVE_SECONDARY_RELOADS 1921 /* If we need a secondary reload (we assume here that we are using 1922 the secondary reload as an intermediate, not a scratch register), the 1923 cost is that to load the input into the intermediate register, then 1924 to copy them. We use a special value of TO_P to avoid recursion. */ 1925 1926#ifdef SECONDARY_INPUT_RELOAD_CLASS 1927 if (to_p == 1) 1928 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); 1929#endif 1930 1931#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1932 if (! to_p) 1933 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); 1934#endif 1935 1936 if (secondary_class != NO_REGS) 1937 return (move_cost[mode][(int) secondary_class][(int) class] 1938 + copy_cost (x, mode, secondary_class, 2)); 1939#endif /* HAVE_SECONDARY_RELOADS */ 1940 1941 /* For memory, use the memory move cost, for (hard) registers, use the 1942 cost to move between the register classes, and use 2 for everything 1943 else (constants). */ 1944 1945 if (GET_CODE (x) == MEM || class == NO_REGS) 1946 return MEMORY_MOVE_COST (mode, class, to_p); 1947 1948 else if (GET_CODE (x) == REG) 1949 return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; 1950 1951 else 1952 /* If this is a constant, we may eventually want to call rtx_cost here. */ 1953 return COSTS_N_INSNS (1); 1954} 1955 1956/* Record the pseudo registers we must reload into hard registers 1957 in a subexpression of a memory address, X. 1958 1959 CLASS is the class that the register needs to be in and is either 1960 BASE_REG_CLASS or INDEX_REG_CLASS. 1961 1962 SCALE is twice the amount to multiply the cost by (it is twice so we 1963 can represent half-cost adjustments). */ 1964 1965static void 1966record_address_regs (x, class, scale) 1967 rtx x; 1968 enum reg_class class; 1969 int scale; 1970{ 1971 enum rtx_code code = GET_CODE (x); 1972 1973 switch (code) 1974 { 1975 case CONST_INT: 1976 case CONST: 1977 case CC0: 1978 case PC: 1979 case SYMBOL_REF: 1980 case LABEL_REF: 1981 return; 1982 1983 case PLUS: 1984 /* When we have an address that is a sum, 1985 we must determine whether registers are "base" or "index" regs. 1986 If there is a sum of two registers, we must choose one to be 1987 the "base". Luckily, we can use the REG_POINTER to make a good 1988 choice most of the time. We only need to do this on machines 1989 that can have two registers in an address and where the base 1990 and index register classes are different. 1991 1992 ??? This code used to set REGNO_POINTER_FLAG in some cases, but 1993 that seems bogus since it should only be set when we are sure 1994 the register is being used as a pointer. */ 1995 1996 { 1997 rtx arg0 = XEXP (x, 0); 1998 rtx arg1 = XEXP (x, 1); 1999 enum rtx_code code0 = GET_CODE (arg0); 2000 enum rtx_code code1 = GET_CODE (arg1); 2001 2002 /* Look inside subregs. */ 2003 if (code0 == SUBREG) 2004 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); 2005 if (code1 == SUBREG) 2006 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); 2007 2008 /* If this machine only allows one register per address, it must 2009 be in the first operand. */ 2010 2011 if (MAX_REGS_PER_ADDRESS == 1) 2012 record_address_regs (arg0, class, scale); 2013 2014 /* If index and base registers are the same on this machine, just 2015 record registers in any non-constant operands. We assume here, 2016 as well as in the tests below, that all addresses are in 2017 canonical form. */ 2018 2019 else if (INDEX_REG_CLASS == MODE_BASE_REG_CLASS (VOIDmode)) 2020 { 2021 record_address_regs (arg0, class, scale); 2022 if (! CONSTANT_P (arg1)) 2023 record_address_regs (arg1, class, scale); 2024 } 2025 2026 /* If the second operand is a constant integer, it doesn't change 2027 what class the first operand must be. */ 2028 2029 else if (code1 == CONST_INT || code1 == CONST_DOUBLE) 2030 record_address_regs (arg0, class, scale); 2031 2032 /* If the second operand is a symbolic constant, the first operand 2033 must be an index register. */ 2034 2035 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) 2036 record_address_regs (arg0, INDEX_REG_CLASS, scale); 2037 2038 /* If both operands are registers but one is already a hard register 2039 of index or base class, give the other the class that the hard 2040 register is not. */ 2041 2042#ifdef REG_OK_FOR_BASE_P 2043 else if (code0 == REG && code1 == REG 2044 && REGNO (arg0) < FIRST_PSEUDO_REGISTER 2045 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) 2046 record_address_regs (arg1, 2047 REG_OK_FOR_BASE_P (arg0) 2048 ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), 2049 scale); 2050 else if (code0 == REG && code1 == REG 2051 && REGNO (arg1) < FIRST_PSEUDO_REGISTER 2052 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) 2053 record_address_regs (arg0, 2054 REG_OK_FOR_BASE_P (arg1) 2055 ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), 2056 scale); 2057#endif 2058 2059 /* If one operand is known to be a pointer, it must be the base 2060 with the other operand the index. Likewise if the other operand 2061 is a MULT. */ 2062 2063 else if ((code0 == REG && REG_POINTER (arg0)) 2064 || code1 == MULT) 2065 { 2066 record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), scale); 2067 record_address_regs (arg1, INDEX_REG_CLASS, scale); 2068 } 2069 else if ((code1 == REG && REG_POINTER (arg1)) 2070 || code0 == MULT) 2071 { 2072 record_address_regs (arg0, INDEX_REG_CLASS, scale); 2073 record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), scale); 2074 } 2075 2076 /* Otherwise, count equal chances that each might be a base 2077 or index register. This case should be rare. */ 2078 2079 else 2080 { 2081 record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), 2082 scale / 2); 2083 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); 2084 record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), 2085 scale / 2); 2086 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); 2087 } 2088 } 2089 break; 2090 2091 /* Double the importance of a pseudo register that is incremented 2092 or decremented, since it would take two extra insns 2093 if it ends up in the wrong place. */ 2094 case POST_MODIFY: 2095 case PRE_MODIFY: 2096 record_address_regs (XEXP (x, 0), MODE_BASE_REG_CLASS (VOIDmode), 2097 2 * scale); 2098 if (REG_P (XEXP (XEXP (x, 1), 1))) 2099 record_address_regs (XEXP (XEXP (x, 1), 1), 2100 INDEX_REG_CLASS, 2 * scale); 2101 break; 2102 2103 case POST_INC: 2104 case PRE_INC: 2105 case POST_DEC: 2106 case PRE_DEC: 2107 /* Double the importance of a pseudo register that is incremented 2108 or decremented, since it would take two extra insns 2109 if it ends up in the wrong place. If the operand is a pseudo, 2110 show it is being used in an INC_DEC context. */ 2111 2112#ifdef FORBIDDEN_INC_DEC_CLASSES 2113 if (GET_CODE (XEXP (x, 0)) == REG 2114 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) 2115 in_inc_dec[REGNO (XEXP (x, 0))] = 1; 2116#endif 2117 2118 record_address_regs (XEXP (x, 0), class, 2 * scale); 2119 break; 2120 2121 case REG: 2122 { 2123 struct costs *pp = &costs[REGNO (x)]; 2124 int i; 2125 2126 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; 2127 2128 for (i = 0; i < N_REG_CLASSES; i++) 2129 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2; 2130 } 2131 break; 2132 2133 default: 2134 { 2135 const char *fmt = GET_RTX_FORMAT (code); 2136 int i; 2137 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2138 if (fmt[i] == 'e') 2139 record_address_regs (XEXP (x, i), class, scale); 2140 } 2141 } 2142} 2143 2144#ifdef FORBIDDEN_INC_DEC_CLASSES 2145 2146/* Return 1 if REG is valid as an auto-increment memory reference 2147 to an object of MODE. */ 2148 2149static int 2150auto_inc_dec_reg_p (reg, mode) 2151 rtx reg; 2152 enum machine_mode mode; 2153{ 2154 if (HAVE_POST_INCREMENT 2155 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) 2156 return 1; 2157 2158 if (HAVE_POST_DECREMENT 2159 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) 2160 return 1; 2161 2162 if (HAVE_PRE_INCREMENT 2163 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) 2164 return 1; 2165 2166 if (HAVE_PRE_DECREMENT 2167 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) 2168 return 1; 2169 2170 return 0; 2171} 2172#endif 2173 2174static short *renumber; 2175static size_t regno_allocated; 2176static unsigned int reg_n_max; 2177 2178/* Allocate enough space to hold NUM_REGS registers for the tables used for 2179 reg_scan and flow_analysis that are indexed by the register number. If 2180 NEW_P is non zero, initialize all of the registers, otherwise only 2181 initialize the new registers allocated. The same table is kept from 2182 function to function, only reallocating it when we need more room. If 2183 RENUMBER_P is non zero, allocate the reg_renumber array also. */ 2184 2185void 2186allocate_reg_info (num_regs, new_p, renumber_p) 2187 size_t num_regs; 2188 int new_p; 2189 int renumber_p; 2190{ 2191 size_t size_info; 2192 size_t size_renumber; 2193 size_t min = (new_p) ? 0 : reg_n_max; 2194 struct reg_info_data *reg_data; 2195 2196 if (num_regs > regno_allocated) 2197 { 2198 size_t old_allocated = regno_allocated; 2199 2200 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ 2201 size_renumber = regno_allocated * sizeof (short); 2202 2203 if (!reg_n_info) 2204 { 2205 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); 2206 renumber = (short *) xmalloc (size_renumber); 2207 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated 2208 * sizeof (struct reg_pref)); 2209 } 2210 2211 else 2212 { 2213 VARRAY_GROW (reg_n_info, regno_allocated); 2214 2215 if (new_p) /* if we're zapping everything, no need to realloc */ 2216 { 2217 free ((char *) renumber); 2218 free ((char *) reg_pref); 2219 renumber = (short *) xmalloc (size_renumber); 2220 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated 2221 * sizeof (struct reg_pref)); 2222 } 2223 2224 else 2225 { 2226 renumber = (short *) xrealloc ((char *) renumber, size_renumber); 2227 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *) reg_pref_buffer, 2228 regno_allocated 2229 * sizeof (struct reg_pref)); 2230 } 2231 } 2232 2233 size_info = (regno_allocated - old_allocated) * sizeof (reg_info) 2234 + sizeof (struct reg_info_data) - sizeof (reg_info); 2235 reg_data = (struct reg_info_data *) xcalloc (size_info, 1); 2236 reg_data->min_index = old_allocated; 2237 reg_data->max_index = regno_allocated - 1; 2238 reg_data->next = reg_info_head; 2239 reg_info_head = reg_data; 2240 } 2241 2242 reg_n_max = num_regs; 2243 if (min < num_regs) 2244 { 2245 /* Loop through each of the segments allocated for the actual 2246 reg_info pages, and set up the pointers, zero the pages, etc. */ 2247 for (reg_data = reg_info_head; 2248 reg_data && reg_data->max_index >= min; 2249 reg_data = reg_data->next) 2250 { 2251 size_t min_index = reg_data->min_index; 2252 size_t max_index = reg_data->max_index; 2253 size_t max = MIN (max_index, num_regs); 2254 size_t local_min = min - min_index; 2255 size_t i; 2256 2257 if (reg_data->min_index > num_regs) 2258 continue; 2259 2260 if (min < min_index) 2261 local_min = 0; 2262 if (!reg_data->used_p) /* page just allocated with calloc */ 2263 reg_data->used_p = 1; /* no need to zero */ 2264 else 2265 memset ((char *) ®_data->data[local_min], 0, 2266 sizeof (reg_info) * (max - min_index - local_min + 1)); 2267 2268 for (i = min_index+local_min; i <= max; i++) 2269 { 2270 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; 2271 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; 2272 renumber[i] = -1; 2273 reg_pref_buffer[i].prefclass = (char) NO_REGS; 2274 reg_pref_buffer[i].altclass = (char) NO_REGS; 2275 } 2276 } 2277 } 2278 2279 /* If {pref,alt}class have already been allocated, update the pointers to 2280 the newly realloced ones. */ 2281 if (reg_pref) 2282 reg_pref = reg_pref_buffer; 2283 2284 if (renumber_p) 2285 reg_renumber = renumber; 2286 2287 /* Tell the regset code about the new number of registers */ 2288 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); 2289} 2290 2291/* Free up the space allocated by allocate_reg_info. */ 2292void 2293free_reg_info () 2294{ 2295 if (reg_n_info) 2296 { 2297 struct reg_info_data *reg_data; 2298 struct reg_info_data *reg_next; 2299 2300 VARRAY_FREE (reg_n_info); 2301 for (reg_data = reg_info_head; reg_data; reg_data = reg_next) 2302 { 2303 reg_next = reg_data->next; 2304 free ((char *) reg_data); 2305 } 2306 2307 free (reg_pref_buffer); 2308 reg_pref_buffer = (struct reg_pref *) 0; 2309 reg_info_head = (struct reg_info_data *) 0; 2310 renumber = (short *) 0; 2311 } 2312 regno_allocated = 0; 2313 reg_n_max = 0; 2314} 2315 2316/* This is the `regscan' pass of the compiler, run just before cse 2317 and again just before loop. 2318 2319 It finds the first and last use of each pseudo-register 2320 and records them in the vectors regno_first_uid, regno_last_uid 2321 and counts the number of sets in the vector reg_n_sets. 2322 2323 REPEAT is nonzero the second time this is called. */ 2324 2325/* Maximum number of parallel sets and clobbers in any insn in this fn. 2326 Always at least 3, since the combiner could put that many together 2327 and we want this to remain correct for all the remaining passes. 2328 This corresponds to the maximum number of times note_stores will call 2329 a function for any insn. */ 2330 2331int max_parallel; 2332 2333/* Used as a temporary to record the largest number of registers in 2334 PARALLEL in a SET_DEST. This is added to max_parallel. */ 2335 2336static int max_set_parallel; 2337 2338void 2339reg_scan (f, nregs, repeat) 2340 rtx f; 2341 unsigned int nregs; 2342 int repeat ATTRIBUTE_UNUSED; 2343{ 2344 rtx insn; 2345 2346 allocate_reg_info (nregs, TRUE, FALSE); 2347 max_parallel = 3; 2348 max_set_parallel = 0; 2349 2350 for (insn = f; insn; insn = NEXT_INSN (insn)) 2351 if (GET_CODE (insn) == INSN 2352 || GET_CODE (insn) == CALL_INSN 2353 || GET_CODE (insn) == JUMP_INSN) 2354 { 2355 if (GET_CODE (PATTERN (insn)) == PARALLEL 2356 && XVECLEN (PATTERN (insn), 0) > max_parallel) 2357 max_parallel = XVECLEN (PATTERN (insn), 0); 2358 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0); 2359 2360 if (REG_NOTES (insn)) 2361 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); 2362 } 2363 2364 max_parallel += max_set_parallel; 2365} 2366 2367/* Update 'regscan' information by looking at the insns 2368 from FIRST to LAST. Some new REGs have been created, 2369 and any REG with number greater than OLD_MAX_REGNO is 2370 such a REG. We only update information for those. */ 2371 2372void 2373reg_scan_update (first, last, old_max_regno) 2374 rtx first; 2375 rtx last; 2376 unsigned int old_max_regno; 2377{ 2378 rtx insn; 2379 2380 allocate_reg_info (max_reg_num (), FALSE, FALSE); 2381 2382 for (insn = first; insn != last; insn = NEXT_INSN (insn)) 2383 if (GET_CODE (insn) == INSN 2384 || GET_CODE (insn) == CALL_INSN 2385 || GET_CODE (insn) == JUMP_INSN) 2386 { 2387 if (GET_CODE (PATTERN (insn)) == PARALLEL 2388 && XVECLEN (PATTERN (insn), 0) > max_parallel) 2389 max_parallel = XVECLEN (PATTERN (insn), 0); 2390 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno); 2391 2392 if (REG_NOTES (insn)) 2393 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); 2394 } 2395} 2396 2397/* X is the expression to scan. INSN is the insn it appears in. 2398 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. 2399 We should only record information for REGs with numbers 2400 greater than or equal to MIN_REGNO. */ 2401 2402static void 2403reg_scan_mark_refs (x, insn, note_flag, min_regno) 2404 rtx x; 2405 rtx insn; 2406 int note_flag; 2407 unsigned int min_regno; 2408{ 2409 enum rtx_code code; 2410 rtx dest; 2411 rtx note; 2412 2413 code = GET_CODE (x); 2414 switch (code) 2415 { 2416 case CONST: 2417 case CONST_INT: 2418 case CONST_DOUBLE: 2419 case CC0: 2420 case PC: 2421 case SYMBOL_REF: 2422 case LABEL_REF: 2423 case ADDR_VEC: 2424 case ADDR_DIFF_VEC: 2425 return; 2426 2427 case REG: 2428 { 2429 unsigned int regno = REGNO (x); 2430 2431 if (regno >= min_regno) 2432 { 2433 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); 2434 if (!note_flag) 2435 REGNO_LAST_UID (regno) = INSN_UID (insn); 2436 if (REGNO_FIRST_UID (regno) == 0) 2437 REGNO_FIRST_UID (regno) = INSN_UID (insn); 2438 } 2439 } 2440 break; 2441 2442 case EXPR_LIST: 2443 if (XEXP (x, 0)) 2444 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); 2445 if (XEXP (x, 1)) 2446 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); 2447 break; 2448 2449 case INSN_LIST: 2450 if (XEXP (x, 1)) 2451 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); 2452 break; 2453 2454 case SET: 2455 /* Count a set of the destination if it is a register. */ 2456 for (dest = SET_DEST (x); 2457 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART 2458 || GET_CODE (dest) == ZERO_EXTEND; 2459 dest = XEXP (dest, 0)) 2460 ; 2461 2462 /* For a PARALLEL, record the number of things (less the usual one for a 2463 SET) that are set. */ 2464 if (GET_CODE (dest) == PARALLEL) 2465 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1); 2466 2467 if (GET_CODE (dest) == REG 2468 && REGNO (dest) >= min_regno) 2469 { 2470 REG_N_SETS (REGNO (dest))++; 2471 REG_N_REFS (REGNO (dest))++; 2472 } 2473 2474 /* If this is setting a pseudo from another pseudo or the sum of a 2475 pseudo and a constant integer and the other pseudo is known to be 2476 a pointer, set the destination to be a pointer as well. 2477 2478 Likewise if it is setting the destination from an address or from a 2479 value equivalent to an address or to the sum of an address and 2480 something else. 2481 2482 But don't do any of this if the pseudo corresponds to a user 2483 variable since it should have already been set as a pointer based 2484 on the type. */ 2485 2486 if (GET_CODE (SET_DEST (x)) == REG 2487 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER 2488 && REGNO (SET_DEST (x)) >= min_regno 2489 /* If the destination pseudo is set more than once, then other 2490 sets might not be to a pointer value (consider access to a 2491 union in two threads of control in the presense of global 2492 optimizations). So only set REG_POINTER on the destination 2493 pseudo if this is the only set of that pseudo. */ 2494 && REG_N_SETS (REGNO (SET_DEST (x))) == 1 2495 && ! REG_USERVAR_P (SET_DEST (x)) 2496 && ! REG_POINTER (SET_DEST (x)) 2497 && ((GET_CODE (SET_SRC (x)) == REG 2498 && REG_POINTER (SET_SRC (x))) 2499 || ((GET_CODE (SET_SRC (x)) == PLUS 2500 || GET_CODE (SET_SRC (x)) == LO_SUM) 2501 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 2502 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG 2503 && REG_POINTER (XEXP (SET_SRC (x), 0))) 2504 || GET_CODE (SET_SRC (x)) == CONST 2505 || GET_CODE (SET_SRC (x)) == SYMBOL_REF 2506 || GET_CODE (SET_SRC (x)) == LABEL_REF 2507 || (GET_CODE (SET_SRC (x)) == HIGH 2508 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST 2509 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF 2510 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) 2511 || ((GET_CODE (SET_SRC (x)) == PLUS 2512 || GET_CODE (SET_SRC (x)) == LO_SUM) 2513 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST 2514 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF 2515 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) 2516 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 2517 && (GET_CODE (XEXP (note, 0)) == CONST 2518 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF 2519 || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) 2520 REG_POINTER (SET_DEST (x)) = 1; 2521 2522 /* If this is setting a register from a register or from a simple 2523 conversion of a register, propagate REG_DECL. */ 2524 if (GET_CODE (dest) == REG) 2525 { 2526 rtx src = SET_SRC (x); 2527 2528 while (GET_CODE (src) == SIGN_EXTEND 2529 || GET_CODE (src) == ZERO_EXTEND 2530 || GET_CODE (src) == TRUNCATE 2531 || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src))) 2532 src = XEXP (src, 0); 2533 2534 if (GET_CODE (src) == REG && REGNO_DECL (REGNO (src)) == 0) 2535 REGNO_DECL (REGNO (src)) = REGNO_DECL (REGNO (dest)); 2536 else if (GET_CODE (src) == REG && REGNO_DECL (REGNO (dest)) == 0) 2537 REGNO_DECL (REGNO (dest)) = REGNO_DECL (REGNO (src)); 2538 } 2539 2540 /* ... fall through ... */ 2541 2542 default: 2543 { 2544 const char *fmt = GET_RTX_FORMAT (code); 2545 int i; 2546 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2547 { 2548 if (fmt[i] == 'e') 2549 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); 2550 else if (fmt[i] == 'E' && XVEC (x, i) != 0) 2551 { 2552 int j; 2553 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 2554 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); 2555 } 2556 } 2557 } 2558 } 2559} 2560 2561/* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 2562 is also in C2. */ 2563 2564int 2565reg_class_subset_p (c1, c2) 2566 enum reg_class c1; 2567 enum reg_class c2; 2568{ 2569 if (c1 == c2) return 1; 2570 2571 if (c2 == ALL_REGS) 2572 win: 2573 return 1; 2574 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) c1], 2575 reg_class_contents[(int) c2], 2576 win); 2577 return 0; 2578} 2579 2580/* Return nonzero if there is a register that is in both C1 and C2. */ 2581 2582int 2583reg_classes_intersect_p (c1, c2) 2584 enum reg_class c1; 2585 enum reg_class c2; 2586{ 2587#ifdef HARD_REG_SET 2588 register 2589#endif 2590 HARD_REG_SET c; 2591 2592 if (c1 == c2) return 1; 2593 2594 if (c1 == ALL_REGS || c2 == ALL_REGS) 2595 return 1; 2596 2597 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); 2598 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); 2599 2600 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); 2601 return 1; 2602 2603 lose: 2604 return 0; 2605} 2606 2607/* Release any memory allocated by register sets. */ 2608 2609void 2610regset_release_memory () 2611{ 2612 bitmap_release_memory (); 2613} 2614