regclass.c revision 52284
1/* Compute register class preferences for pseudo-registers. 2 Copyright (C) 1987, 88, 91-98, 1999 Free Software Foundation, Inc. 3 4This file is part of GNU CC. 5 6GNU CC is free software; you can redistribute it and/or modify 7it under the terms of the GNU General Public License as published by 8the Free Software Foundation; either version 2, or (at your option) 9any later version. 10 11GNU CC is distributed in the hope that it will be useful, 12but WITHOUT ANY WARRANTY; without even the implied warranty of 13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14GNU General Public License for more details. 15 16You should have received a copy of the GNU General Public License 17along with GNU CC; see the file COPYING. If not, write to 18the Free Software Foundation, 59 Temple Place - Suite 330, 19Boston, MA 02111-1307, USA. */ 20 21 22/* This file contains two passes of the compiler: reg_scan and reg_class. 23 It also defines some tables of information about the hardware registers 24 and a function init_reg_sets to initialize the tables. */ 25 26#include "config.h" 27#include "system.h" 28#include "rtl.h" 29#include "hard-reg-set.h" 30#include "flags.h" 31#include "basic-block.h" 32#include "regs.h" 33#include "insn-config.h" 34#include "recog.h" 35#include "reload.h" 36#include "real.h" 37#include "toplev.h" 38#include "output.h" 39 40#ifndef REGISTER_MOVE_COST 41#define REGISTER_MOVE_COST(x, y) 2 42#endif 43 44static void init_reg_sets_1 PROTO((void)); 45static void init_reg_modes PROTO((void)); 46 47/* If we have auto-increment or auto-decrement and we can have secondary 48 reloads, we are not allowed to use classes requiring secondary 49 reloads for pseudos auto-incremented since reload can't handle it. */ 50 51#ifdef AUTO_INC_DEC 52#if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) 53#define FORBIDDEN_INC_DEC_CLASSES 54#endif 55#endif 56 57/* Register tables used by many passes. */ 58 59/* Indexed by hard register number, contains 1 for registers 60 that are fixed use (stack pointer, pc, frame pointer, etc.). 61 These are the registers that cannot be used to allocate 62 a pseudo reg for general use. */ 63 64char fixed_regs[FIRST_PSEUDO_REGISTER]; 65 66/* Same info as a HARD_REG_SET. */ 67 68HARD_REG_SET fixed_reg_set; 69 70/* Data for initializing the above. */ 71 72static char initial_fixed_regs[] = FIXED_REGISTERS; 73 74/* Indexed by hard register number, contains 1 for registers 75 that are fixed use or are clobbered by function calls. 76 These are the registers that cannot be used to allocate 77 a pseudo reg whose life crosses calls unless we are able 78 to save/restore them across the calls. */ 79 80char call_used_regs[FIRST_PSEUDO_REGISTER]; 81 82/* Same info as a HARD_REG_SET. */ 83 84HARD_REG_SET call_used_reg_set; 85 86/* HARD_REG_SET of registers we want to avoid caller saving. */ 87HARD_REG_SET losing_caller_save_reg_set; 88 89/* Data for initializing the above. */ 90 91static char initial_call_used_regs[] = CALL_USED_REGISTERS; 92 93/* Indexed by hard register number, contains 1 for registers that are 94 fixed use or call used registers that cannot hold quantities across 95 calls even if we are willing to save and restore them. call fixed 96 registers are a subset of call used registers. */ 97 98char call_fixed_regs[FIRST_PSEUDO_REGISTER]; 99 100/* The same info as a HARD_REG_SET. */ 101 102HARD_REG_SET call_fixed_reg_set; 103 104/* Number of non-fixed registers. */ 105 106int n_non_fixed_regs; 107 108/* Indexed by hard register number, contains 1 for registers 109 that are being used for global register decls. 110 These must be exempt from ordinary flow analysis 111 and are also considered fixed. */ 112 113char global_regs[FIRST_PSEUDO_REGISTER]; 114 115/* Table of register numbers in the order in which to try to use them. */ 116#ifdef REG_ALLOC_ORDER 117int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; 118#endif 119 120/* For each reg class, a HARD_REG_SET saying which registers are in it. */ 121 122HARD_REG_SET reg_class_contents[N_REG_CLASSES]; 123 124/* The same information, but as an array of unsigned ints. We copy from 125 these unsigned ints to the table above. We do this so the tm.h files 126 do not have to be aware of the wordsize for machines with <= 64 regs. */ 127 128#define N_REG_INTS \ 129 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT) 130 131static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] 132 = REG_CLASS_CONTENTS; 133 134/* For each reg class, number of regs it contains. */ 135 136int reg_class_size[N_REG_CLASSES]; 137 138/* For each reg class, table listing all the containing classes. */ 139 140enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; 141 142/* For each reg class, table listing all the classes contained in it. */ 143 144enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; 145 146/* For each pair of reg classes, 147 a largest reg class contained in their union. */ 148 149enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; 150 151/* For each pair of reg classes, 152 the smallest reg class containing their union. */ 153 154enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; 155 156/* Array containing all of the register names */ 157 158char *reg_names[] = REGISTER_NAMES; 159 160/* For each hard register, the widest mode object that it can contain. 161 This will be a MODE_INT mode if the register can hold integers. Otherwise 162 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the 163 register. */ 164 165enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; 166 167/* Maximum cost of moving from a register in one class to a register in 168 another class. Based on REGISTER_MOVE_COST. */ 169 170static int move_cost[N_REG_CLASSES][N_REG_CLASSES]; 171 172/* Similar, but here we don't have to move if the first index is a subset 173 of the second so in that case the cost is zero. */ 174 175static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES]; 176 177#ifdef FORBIDDEN_INC_DEC_CLASSES 178 179/* These are the classes that regs which are auto-incremented or decremented 180 cannot be put in. */ 181 182static int forbidden_inc_dec_class[N_REG_CLASSES]; 183 184/* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec 185 context. */ 186 187static char *in_inc_dec; 188 189#endif /* FORBIDDEN_INC_DEC_CLASSES */ 190 191#ifdef HAVE_SECONDARY_RELOADS 192 193/* Sample MEM values for use by memory_move_secondary_cost. */ 194 195static rtx top_of_stack[MAX_MACHINE_MODE]; 196 197#endif /* HAVE_SECONDARY_RELOADS */ 198 199/* Linked list of reg_info structures allocated for reg_n_info array. 200 Grouping all of the allocated structures together in one lump 201 means only one call to bzero to clear them, rather than n smaller 202 calls. */ 203struct reg_info_data { 204 struct reg_info_data *next; /* next set of reg_info structures */ 205 size_t min_index; /* minimum index # */ 206 size_t max_index; /* maximum index # */ 207 char used_p; /* non-zero if this has been used previously */ 208 reg_info data[1]; /* beginning of the reg_info data */ 209}; 210 211static struct reg_info_data *reg_info_head; 212 213 214/* Function called only once to initialize the above data on reg usage. 215 Once this is done, various switches may override. */ 216 217void 218init_reg_sets () 219{ 220 register int i, j; 221 222 /* First copy the register information from the initial int form into 223 the regsets. */ 224 225 for (i = 0; i < N_REG_CLASSES; i++) 226 { 227 CLEAR_HARD_REG_SET (reg_class_contents[i]); 228 229 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 230 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT] 231 & ((unsigned) 1 << (j % HOST_BITS_PER_INT))) 232 SET_HARD_REG_BIT (reg_class_contents[i], j); 233 } 234 235 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); 236 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); 237 bzero (global_regs, sizeof global_regs); 238 239 /* Do any additional initialization regsets may need */ 240 INIT_ONCE_REG_SET (); 241} 242 243/* After switches have been processed, which perhaps alter 244 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ 245 246static void 247init_reg_sets_1 () 248{ 249 register unsigned int i, j; 250 251 /* This macro allows the fixed or call-used registers 252 and the register classes to depend on target flags. */ 253 254#ifdef CONDITIONAL_REGISTER_USAGE 255 CONDITIONAL_REGISTER_USAGE; 256#endif 257 258 /* Compute number of hard regs in each class. */ 259 260 bzero ((char *) reg_class_size, sizeof reg_class_size); 261 for (i = 0; i < N_REG_CLASSES; i++) 262 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 263 if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 264 reg_class_size[i]++; 265 266 /* Initialize the table of subunions. 267 reg_class_subunion[I][J] gets the largest-numbered reg-class 268 that is contained in the union of classes I and J. */ 269 270 for (i = 0; i < N_REG_CLASSES; i++) 271 { 272 for (j = 0; j < N_REG_CLASSES; j++) 273 { 274#ifdef HARD_REG_SET 275 register /* Declare it register if it's a scalar. */ 276#endif 277 HARD_REG_SET c; 278 register int k; 279 280 COPY_HARD_REG_SET (c, reg_class_contents[i]); 281 IOR_HARD_REG_SET (c, reg_class_contents[j]); 282 for (k = 0; k < N_REG_CLASSES; k++) 283 { 284 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, 285 subclass1); 286 continue; 287 288 subclass1: 289 /* keep the largest subclass */ /* SPEE 900308 */ 290 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], 291 reg_class_contents[(int) reg_class_subunion[i][j]], 292 subclass2); 293 reg_class_subunion[i][j] = (enum reg_class) k; 294 subclass2: 295 ; 296 } 297 } 298 } 299 300 /* Initialize the table of superunions. 301 reg_class_superunion[I][J] gets the smallest-numbered reg-class 302 containing the union of classes I and J. */ 303 304 for (i = 0; i < N_REG_CLASSES; i++) 305 { 306 for (j = 0; j < N_REG_CLASSES; j++) 307 { 308#ifdef HARD_REG_SET 309 register /* Declare it register if it's a scalar. */ 310#endif 311 HARD_REG_SET c; 312 register int k; 313 314 COPY_HARD_REG_SET (c, reg_class_contents[i]); 315 IOR_HARD_REG_SET (c, reg_class_contents[j]); 316 for (k = 0; k < N_REG_CLASSES; k++) 317 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); 318 319 superclass: 320 reg_class_superunion[i][j] = (enum reg_class) k; 321 } 322 } 323 324 /* Initialize the tables of subclasses and superclasses of each reg class. 325 First clear the whole table, then add the elements as they are found. */ 326 327 for (i = 0; i < N_REG_CLASSES; i++) 328 { 329 for (j = 0; j < N_REG_CLASSES; j++) 330 { 331 reg_class_superclasses[i][j] = LIM_REG_CLASSES; 332 reg_class_subclasses[i][j] = LIM_REG_CLASSES; 333 } 334 } 335 336 for (i = 0; i < N_REG_CLASSES; i++) 337 { 338 if (i == (int) NO_REGS) 339 continue; 340 341 for (j = i + 1; j < N_REG_CLASSES; j++) 342 { 343 enum reg_class *p; 344 345 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], 346 subclass); 347 continue; 348 subclass: 349 /* Reg class I is a subclass of J. 350 Add J to the table of superclasses of I. */ 351 p = ®_class_superclasses[i][0]; 352 while (*p != LIM_REG_CLASSES) p++; 353 *p = (enum reg_class) j; 354 /* Add I to the table of superclasses of J. */ 355 p = ®_class_subclasses[j][0]; 356 while (*p != LIM_REG_CLASSES) p++; 357 *p = (enum reg_class) i; 358 } 359 } 360 361 /* Initialize "constant" tables. */ 362 363 CLEAR_HARD_REG_SET (fixed_reg_set); 364 CLEAR_HARD_REG_SET (call_used_reg_set); 365 CLEAR_HARD_REG_SET (call_fixed_reg_set); 366 367 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); 368 369 n_non_fixed_regs = 0; 370 371 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 372 { 373 if (fixed_regs[i]) 374 SET_HARD_REG_BIT (fixed_reg_set, i); 375 else 376 n_non_fixed_regs++; 377 378 if (call_used_regs[i]) 379 SET_HARD_REG_BIT (call_used_reg_set, i); 380 if (call_fixed_regs[i]) 381 SET_HARD_REG_BIT (call_fixed_reg_set, i); 382 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) 383 SET_HARD_REG_BIT (losing_caller_save_reg_set, i); 384 } 385 386 /* Initialize the move cost table. Find every subset of each class 387 and take the maximum cost of moving any subset to any other. */ 388 389 for (i = 0; i < N_REG_CLASSES; i++) 390 for (j = 0; j < N_REG_CLASSES; j++) 391 { 392 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j); 393 enum reg_class *p1, *p2; 394 395 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) 396 if (*p2 != i) 397 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2)); 398 399 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) 400 { 401 if (*p1 != j) 402 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j)); 403 404 for (p2 = ®_class_subclasses[j][0]; 405 *p2 != LIM_REG_CLASSES; p2++) 406 if (*p1 != *p2) 407 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2)); 408 } 409 410 move_cost[i][j] = cost; 411 412 if (reg_class_subset_p (i, j)) 413 cost = 0; 414 415 may_move_cost[i][j] = cost; 416 } 417} 418 419/* Compute the table of register modes. 420 These values are used to record death information for individual registers 421 (as opposed to a multi-register mode). */ 422 423static void 424init_reg_modes () 425{ 426 register int i; 427 428 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 429 { 430 reg_raw_mode[i] = choose_hard_reg_mode (i, 1); 431 432 /* If we couldn't find a valid mode, just use the previous mode. 433 ??? One situation in which we need to do this is on the mips where 434 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like 435 to use DF mode for the even registers and VOIDmode for the odd 436 (for the cpu models where the odd ones are inaccessible). */ 437 if (reg_raw_mode[i] == VOIDmode) 438 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; 439 } 440} 441 442/* Finish initializing the register sets and 443 initialize the register modes. */ 444 445void 446init_regs () 447{ 448 /* This finishes what was started by init_reg_sets, but couldn't be done 449 until after register usage was specified. */ 450 init_reg_sets_1 (); 451 452 init_reg_modes (); 453 454#ifdef HAVE_SECONDARY_RELOADS 455 { 456 /* Make some fake stack-frame MEM references for use in 457 memory_move_secondary_cost. */ 458 int i; 459 for (i = 0; i < MAX_MACHINE_MODE; i++) 460 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); 461 } 462#endif 463} 464 465#ifdef HAVE_SECONDARY_RELOADS 466 467/* Compute extra cost of moving registers to/from memory due to reloads. 468 Only needed if secondary reloads are required for memory moves. */ 469 470int 471memory_move_secondary_cost (mode, class, in) 472 enum machine_mode mode; 473 enum reg_class class; 474 int in; 475{ 476 enum reg_class altclass; 477 int partial_cost = 0; 478 /* We need a memory reference to feed to SECONDARY... macros. */ 479 rtx mem = top_of_stack[(int) mode]; 480 481 if (in) 482 { 483#ifdef SECONDARY_INPUT_RELOAD_CLASS 484 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); 485#else 486 altclass = NO_REGS; 487#endif 488 } 489 else 490 { 491#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 492 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); 493#else 494 altclass = NO_REGS; 495#endif 496 } 497 498 if (altclass == NO_REGS) 499 return 0; 500 501 if (in) 502 partial_cost = REGISTER_MOVE_COST (altclass, class); 503 else 504 partial_cost = REGISTER_MOVE_COST (class, altclass); 505 506 if (class == altclass) 507 /* This isn't simply a copy-to-temporary situation. Can't guess 508 what it is, so MEMORY_MOVE_COST really ought not to be calling 509 here in that case. 510 511 I'm tempted to put in an abort here, but returning this will 512 probably only give poor estimates, which is what we would've 513 had before this code anyways. */ 514 return partial_cost; 515 516 /* Check if the secondary reload register will also need a 517 secondary reload. */ 518 return memory_move_secondary_cost (mode, altclass, in) + partial_cost; 519} 520#endif 521 522/* Return a machine mode that is legitimate for hard reg REGNO and large 523 enough to save nregs. If we can't find one, return VOIDmode. */ 524 525enum machine_mode 526choose_hard_reg_mode (regno, nregs) 527 int regno; 528 int nregs; 529{ 530 enum machine_mode found_mode = VOIDmode, mode; 531 532 /* We first look for the largest integer mode that can be validly 533 held in REGNO. If none, we look for the largest floating-point mode. 534 If we still didn't find a valid mode, try CCmode. */ 535 536 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); 537 mode != VOIDmode; 538 mode = GET_MODE_WIDER_MODE (mode)) 539 if (HARD_REGNO_NREGS (regno, mode) == nregs 540 && HARD_REGNO_MODE_OK (regno, mode)) 541 found_mode = mode; 542 543 if (found_mode != VOIDmode) 544 return found_mode; 545 546 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); 547 mode != VOIDmode; 548 mode = GET_MODE_WIDER_MODE (mode)) 549 if (HARD_REGNO_NREGS (regno, mode) == nregs 550 && HARD_REGNO_MODE_OK (regno, mode)) 551 found_mode = mode; 552 553 if (found_mode != VOIDmode) 554 return found_mode; 555 556 if (HARD_REGNO_NREGS (regno, CCmode) == nregs 557 && HARD_REGNO_MODE_OK (regno, CCmode)) 558 return CCmode; 559 560 /* We can't find a mode valid for this register. */ 561 return VOIDmode; 562} 563 564/* Specify the usage characteristics of the register named NAME. 565 It should be a fixed register if FIXED and a 566 call-used register if CALL_USED. */ 567 568void 569fix_register (name, fixed, call_used) 570 char *name; 571 int fixed, call_used; 572{ 573 int i; 574 575 /* Decode the name and update the primary form of 576 the register info. */ 577 578 if ((i = decode_reg_name (name)) >= 0) 579 { 580 if ((i == STACK_POINTER_REGNUM 581#ifdef HARD_FRAME_POINTER_REGNUM 582 || i == HARD_FRAME_POINTER_REGNUM 583#else 584 || i == FRAME_POINTER_REGNUM 585#endif 586 ) 587 && (fixed == 0 || call_used == 0)) 588 { 589 static char* what_option[2][2] = { 590 { "call-saved", "call-used" }, 591 { "no-such-option", "fixed" }}; 592 593 error ("can't use '%s' as a %s register", name, 594 what_option[fixed][call_used]); 595 } 596 else 597 { 598 fixed_regs[i] = fixed; 599 call_used_regs[i] = call_used; 600 } 601 } 602 else 603 { 604 warning ("unknown register name: %s", name); 605 } 606} 607 608/* Mark register number I as global. */ 609 610void 611globalize_reg (i) 612 int i; 613{ 614 if (global_regs[i]) 615 { 616 warning ("register used for two global register variables"); 617 return; 618 } 619 620 if (call_used_regs[i] && ! fixed_regs[i]) 621 warning ("call-clobbered register used for global register variable"); 622 623 global_regs[i] = 1; 624 625 /* If already fixed, nothing else to do. */ 626 if (fixed_regs[i]) 627 return; 628 629 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; 630 n_non_fixed_regs--; 631 632 SET_HARD_REG_BIT (fixed_reg_set, i); 633 SET_HARD_REG_BIT (call_used_reg_set, i); 634 SET_HARD_REG_BIT (call_fixed_reg_set, i); 635} 636 637/* Now the data and code for the `regclass' pass, which happens 638 just before local-alloc. */ 639 640/* The `costs' struct records the cost of using a hard register of each class 641 and of using memory for each pseudo. We use this data to set up 642 register class preferences. */ 643 644struct costs 645{ 646 int cost[N_REG_CLASSES]; 647 int mem_cost; 648}; 649 650/* Record the cost of each class for each pseudo. */ 651 652static struct costs *costs; 653 654/* Initialized once, and used to initialize cost values for each insn. */ 655 656static struct costs init_cost; 657 658/* Record the same data by operand number, accumulated for each alternative 659 in an insn. The contribution to a pseudo is that of the minimum-cost 660 alternative. */ 661 662static struct costs op_costs[MAX_RECOG_OPERANDS]; 663 664/* (enum reg_class) prefclass[R] is the preferred class for pseudo number R. 665 This is available after `regclass' is run. */ 666 667static char *prefclass; 668 669/* altclass[R] is a register class that we should use for allocating 670 pseudo number R if no register in the preferred class is available. 671 If no register in this class is available, memory is preferred. 672 673 It might appear to be more general to have a bitmask of classes here, 674 but since it is recommended that there be a class corresponding to the 675 union of most major pair of classes, that generality is not required. 676 677 This is available after `regclass' is run. */ 678 679static char *altclass; 680 681/* Allocated buffers for prefclass and altclass. */ 682static char *prefclass_buffer; 683static char *altclass_buffer; 684 685/* Record the depth of loops that we are in. */ 686 687static int loop_depth; 688 689/* Account for the fact that insns within a loop are executed very commonly, 690 but don't keep doing this as loops go too deep. */ 691 692static int loop_cost; 693 694static rtx scan_one_insn PROTO((rtx, int)); 695static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *, 696 char *, const char **, rtx)); 697static int copy_cost PROTO((rtx, enum machine_mode, 698 enum reg_class, int)); 699static void record_address_regs PROTO((rtx, enum reg_class, int)); 700#ifdef FORBIDDEN_INC_DEC_CLASSES 701static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode)); 702#endif 703static void reg_scan_mark_refs PROTO((rtx, rtx, int, int)); 704 705/* Return the reg_class in which pseudo reg number REGNO is best allocated. 706 This function is sometimes called before the info has been computed. 707 When that happens, just return GENERAL_REGS, which is innocuous. */ 708 709enum reg_class 710reg_preferred_class (regno) 711 int regno; 712{ 713 if (prefclass == 0) 714 return GENERAL_REGS; 715 return (enum reg_class) prefclass[regno]; 716} 717 718enum reg_class 719reg_alternate_class (regno) 720 int regno; 721{ 722 if (prefclass == 0) 723 return ALL_REGS; 724 725 return (enum reg_class) altclass[regno]; 726} 727 728/* Initialize some global data for this pass. */ 729 730void 731regclass_init () 732{ 733 int i; 734 735 init_cost.mem_cost = 10000; 736 for (i = 0; i < N_REG_CLASSES; i++) 737 init_cost.cost[i] = 10000; 738 739 /* This prevents dump_flow_info from losing if called 740 before regclass is run. */ 741 prefclass = 0; 742} 743 744/* Subroutine of regclass, processes one insn INSN. Scan it and record each 745 time it would save code to put a certain register in a certain class. 746 PASS, when nonzero, inhibits some optimizations which need only be done 747 once. 748 Return the last insn processed, so that the scan can be continued from 749 there. */ 750 751static rtx 752scan_one_insn (insn, pass) 753 rtx insn; 754 int pass; 755{ 756 enum rtx_code code = GET_CODE (insn); 757 enum rtx_code pat_code; 758 const char *constraints[MAX_RECOG_OPERANDS]; 759 enum machine_mode modes[MAX_RECOG_OPERANDS]; 760 char subreg_changes_size[MAX_RECOG_OPERANDS]; 761 rtx set, note; 762 int i, j; 763 764 /* Show that an insn inside a loop is likely to be executed three 765 times more than insns outside a loop. This is much more aggressive 766 than the assumptions made elsewhere and is being tried as an 767 experiment. */ 768 769 if (code == NOTE) 770 { 771 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) 772 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5)); 773 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) 774 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5)); 775 776 return insn; 777 } 778 779 if (GET_RTX_CLASS (code) != 'i') 780 return insn; 781 782 pat_code = GET_CODE (PATTERN (insn)); 783 if (pat_code == USE 784 || pat_code == CLOBBER 785 || pat_code == ASM_INPUT 786 || pat_code == ADDR_VEC 787 || pat_code == ADDR_DIFF_VEC) 788 return insn; 789 790 set = single_set (insn); 791 extract_insn (insn); 792 793 for (i = 0; i < recog_n_operands; i++) 794 { 795 constraints[i] = recog_constraints[i]; 796 modes[i] = recog_operand_mode[i]; 797 } 798 memset (subreg_changes_size, 0, sizeof (subreg_changes_size)); 799 800 /* If this insn loads a parameter from its stack slot, then 801 it represents a savings, rather than a cost, if the 802 parameter is stored in memory. Record this fact. */ 803 804 if (set != 0 && GET_CODE (SET_DEST (set)) == REG 805 && GET_CODE (SET_SRC (set)) == MEM 806 && (note = find_reg_note (insn, REG_EQUIV, 807 NULL_RTX)) != 0 808 && GET_CODE (XEXP (note, 0)) == MEM) 809 { 810 costs[REGNO (SET_DEST (set))].mem_cost 811 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), 812 GENERAL_REGS, 1) 813 * loop_cost); 814 record_address_regs (XEXP (SET_SRC (set), 0), 815 BASE_REG_CLASS, loop_cost * 2); 816 return insn; 817 } 818 819 /* Improve handling of two-address insns such as 820 (set X (ashift CONST Y)) where CONST must be made to 821 match X. Change it into two insns: (set X CONST) 822 (set X (ashift X Y)). If we left this for reloading, it 823 would probably get three insns because X and Y might go 824 in the same place. This prevents X and Y from receiving 825 the same hard reg. 826 827 We can only do this if the modes of operands 0 and 1 828 (which might not be the same) are tieable and we only need 829 do this during our first pass. */ 830 831 if (pass == 0 && optimize 832 && recog_n_operands >= 3 833 && recog_constraints[1][0] == '0' 834 && recog_constraints[1][1] == 0 835 && CONSTANT_P (recog_operand[1]) 836 && ! rtx_equal_p (recog_operand[0], recog_operand[1]) 837 && ! rtx_equal_p (recog_operand[0], recog_operand[2]) 838 && GET_CODE (recog_operand[0]) == REG 839 && MODES_TIEABLE_P (GET_MODE (recog_operand[0]), 840 recog_operand_mode[1])) 841 { 842 rtx previnsn = prev_real_insn (insn); 843 rtx dest 844 = gen_lowpart (recog_operand_mode[1], 845 recog_operand[0]); 846 rtx newinsn 847 = emit_insn_before (gen_move_insn (dest, 848 recog_operand[1]), 849 insn); 850 851 /* If this insn was the start of a basic block, 852 include the new insn in that block. 853 We need not check for code_label here; 854 while a basic block can start with a code_label, 855 INSN could not be at the beginning of that block. */ 856 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) 857 { 858 int b; 859 for (b = 0; b < n_basic_blocks; b++) 860 if (insn == BLOCK_HEAD (b)) 861 BLOCK_HEAD (b) = newinsn; 862 } 863 864 /* This makes one more setting of new insns's dest. */ 865 REG_N_SETS (REGNO (recog_operand[0]))++; 866 867 *recog_operand_loc[1] = recog_operand[0]; 868 for (i = recog_n_dups - 1; i >= 0; i--) 869 if (recog_dup_num[i] == 1) 870 *recog_dup_loc[i] = recog_operand[0]; 871 872 return PREV_INSN (newinsn); 873 } 874 875 /* If we get here, we are set up to record the costs of all the 876 operands for this insn. Start by initializing the costs. 877 Then handle any address registers. Finally record the desired 878 classes for any pseudos, doing it twice if some pair of 879 operands are commutative. */ 880 881 for (i = 0; i < recog_n_operands; i++) 882 { 883 op_costs[i] = init_cost; 884 885 if (GET_CODE (recog_operand[i]) == SUBREG) 886 { 887 rtx inner = SUBREG_REG (recog_operand[i]); 888 if (GET_MODE_SIZE (modes[i]) != GET_MODE_SIZE (GET_MODE (inner))) 889 subreg_changes_size[i] = 1; 890 recog_operand[i] = inner; 891 } 892 893 if (GET_CODE (recog_operand[i]) == MEM) 894 record_address_regs (XEXP (recog_operand[i], 0), 895 BASE_REG_CLASS, loop_cost * 2); 896 else if (constraints[i][0] == 'p') 897 record_address_regs (recog_operand[i], 898 BASE_REG_CLASS, loop_cost * 2); 899 } 900 901 /* Check for commutative in a separate loop so everything will 902 have been initialized. We must do this even if one operand 903 is a constant--see addsi3 in m68k.md. */ 904 905 for (i = 0; i < recog_n_operands - 1; i++) 906 if (constraints[i][0] == '%') 907 { 908 const char *xconstraints[MAX_RECOG_OPERANDS]; 909 int j; 910 911 /* Handle commutative operands by swapping the constraints. 912 We assume the modes are the same. */ 913 914 for (j = 0; j < recog_n_operands; j++) 915 xconstraints[j] = constraints[j]; 916 917 xconstraints[i] = constraints[i+1]; 918 xconstraints[i+1] = constraints[i]; 919 record_reg_classes (recog_n_alternatives, recog_n_operands, 920 recog_operand, modes, subreg_changes_size, 921 xconstraints, insn); 922 } 923 924 record_reg_classes (recog_n_alternatives, recog_n_operands, recog_operand, 925 modes, subreg_changes_size, constraints, insn); 926 927 /* Now add the cost for each operand to the total costs for 928 its register. */ 929 930 for (i = 0; i < recog_n_operands; i++) 931 if (GET_CODE (recog_operand[i]) == REG 932 && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) 933 { 934 int regno = REGNO (recog_operand[i]); 935 struct costs *p = &costs[regno], *q = &op_costs[i]; 936 937 p->mem_cost += q->mem_cost * loop_cost; 938 for (j = 0; j < N_REG_CLASSES; j++) 939 p->cost[j] += q->cost[j] * loop_cost; 940 } 941 942 return insn; 943} 944 945/* This is a pass of the compiler that scans all instructions 946 and calculates the preferred class for each pseudo-register. 947 This information can be accessed later by calling `reg_preferred_class'. 948 This pass comes just before local register allocation. */ 949 950void 951regclass (f, nregs) 952 rtx f; 953 int nregs; 954{ 955#ifdef REGISTER_CONSTRAINTS 956 register rtx insn; 957 register int i; 958 int pass; 959 960 init_recog (); 961 962 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs)); 963 964#ifdef FORBIDDEN_INC_DEC_CLASSES 965 966 in_inc_dec = (char *) alloca (nregs); 967 968 /* Initialize information about which register classes can be used for 969 pseudos that are auto-incremented or auto-decremented. It would 970 seem better to put this in init_reg_sets, but we need to be able 971 to allocate rtx, which we can't do that early. */ 972 973 for (i = 0; i < N_REG_CLASSES; i++) 974 { 975 rtx r = gen_rtx_REG (VOIDmode, 0); 976 enum machine_mode m; 977 register int j; 978 979 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 980 if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 981 { 982 REGNO (r) = j; 983 984 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; 985 m = (enum machine_mode) ((int) m + 1)) 986 if (HARD_REGNO_MODE_OK (j, m)) 987 { 988 PUT_MODE (r, m); 989 990 /* If a register is not directly suitable for an 991 auto-increment or decrement addressing mode and 992 requires secondary reloads, disallow its class from 993 being used in such addresses. */ 994 995 if ((0 996#ifdef SECONDARY_RELOAD_CLASS 997 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r) 998 != NO_REGS) 999#else 1000#ifdef SECONDARY_INPUT_RELOAD_CLASS 1001 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) 1002 != NO_REGS) 1003#endif 1004#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1005 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) 1006 != NO_REGS) 1007#endif 1008#endif 1009 ) 1010 && ! auto_inc_dec_reg_p (r, m)) 1011 forbidden_inc_dec_class[i] = 1; 1012 } 1013 } 1014 } 1015#endif /* FORBIDDEN_INC_DEC_CLASSES */ 1016 1017 /* Normally we scan the insns once and determine the best class to use for 1018 each register. However, if -fexpensive_optimizations are on, we do so 1019 twice, the second time using the tentative best classes to guide the 1020 selection. */ 1021 1022 for (pass = 0; pass <= flag_expensive_optimizations; pass++) 1023 { 1024 /* Zero out our accumulation of the cost of each class for each reg. */ 1025 1026 bzero ((char *) costs, nregs * sizeof (struct costs)); 1027 1028#ifdef FORBIDDEN_INC_DEC_CLASSES 1029 bzero (in_inc_dec, nregs); 1030#endif 1031 1032 loop_depth = 0, loop_cost = 1; 1033 1034 /* Scan the instructions and record each time it would 1035 save code to put a certain register in a certain class. */ 1036 1037 for (insn = f; insn; insn = NEXT_INSN (insn)) 1038 { 1039 insn = scan_one_insn (insn, pass); 1040 } 1041 1042 /* Now for each register look at how desirable each class is 1043 and find which class is preferred. Store that in 1044 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register 1045 class any of whose registers is better than memory. */ 1046 1047 if (pass == 0) 1048 { 1049 prefclass = prefclass_buffer; 1050 altclass = altclass_buffer; 1051 } 1052 1053 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) 1054 { 1055 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; 1056 enum reg_class best = ALL_REGS, alt = NO_REGS; 1057 /* This is an enum reg_class, but we call it an int 1058 to save lots of casts. */ 1059 register int class; 1060 register struct costs *p = &costs[i]; 1061 1062 for (class = (int) ALL_REGS - 1; class > 0; class--) 1063 { 1064 /* Ignore classes that are too small for this operand or 1065 invalid for a operand that was auto-incremented. */ 1066 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) 1067 > reg_class_size[class] 1068#ifdef FORBIDDEN_INC_DEC_CLASSES 1069 || (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1070#endif 1071 ) 1072 ; 1073 else if (p->cost[class] < best_cost) 1074 { 1075 best_cost = p->cost[class]; 1076 best = (enum reg_class) class; 1077 } 1078 else if (p->cost[class] == best_cost) 1079 best = reg_class_subunion[(int)best][class]; 1080 } 1081 1082 /* Record the alternate register class; i.e., a class for which 1083 every register in it is better than using memory. If adding a 1084 class would make a smaller class (i.e., no union of just those 1085 classes exists), skip that class. The major unions of classes 1086 should be provided as a register class. Don't do this if we 1087 will be doing it again later. */ 1088 1089 if (pass == 1 || ! flag_expensive_optimizations) 1090 for (class = 0; class < N_REG_CLASSES; class++) 1091 if (p->cost[class] < p->mem_cost 1092 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] 1093 > reg_class_size[(int) alt]) 1094#ifdef FORBIDDEN_INC_DEC_CLASSES 1095 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1096#endif 1097 ) 1098 alt = reg_class_subunion[(int) alt][class]; 1099 1100 /* If we don't add any classes, nothing to try. */ 1101 if (alt == best) 1102 alt = NO_REGS; 1103 1104 /* We cast to (int) because (char) hits bugs in some compilers. */ 1105 prefclass[i] = (int) best; 1106 altclass[i] = (int) alt; 1107 } 1108 } 1109#endif /* REGISTER_CONSTRAINTS */ 1110 1111 free (costs); 1112} 1113 1114#ifdef REGISTER_CONSTRAINTS 1115 1116/* Record the cost of using memory or registers of various classes for 1117 the operands in INSN. 1118 1119 N_ALTS is the number of alternatives. 1120 1121 N_OPS is the number of operands. 1122 1123 OPS is an array of the operands. 1124 1125 MODES are the modes of the operands, in case any are VOIDmode. 1126 1127 CONSTRAINTS are the constraints to use for the operands. This array 1128 is modified by this procedure. 1129 1130 This procedure works alternative by alternative. For each alternative 1131 we assume that we will be able to allocate all pseudos to their ideal 1132 register class and calculate the cost of using that alternative. Then 1133 we compute for each operand that is a pseudo-register, the cost of 1134 having the pseudo allocated to each register class and using it in that 1135 alternative. To this cost is added the cost of the alternative. 1136 1137 The cost of each class for this insn is its lowest cost among all the 1138 alternatives. */ 1139 1140static void 1141record_reg_classes (n_alts, n_ops, ops, modes, subreg_changes_size, 1142 constraints, insn) 1143 int n_alts; 1144 int n_ops; 1145 rtx *ops; 1146 enum machine_mode *modes; 1147 char *subreg_changes_size; 1148 const char **constraints; 1149 rtx insn; 1150{ 1151 int alt; 1152 int i, j; 1153 rtx set; 1154 1155 /* Process each alternative, each time minimizing an operand's cost with 1156 the cost for each operand in that alternative. */ 1157 1158 for (alt = 0; alt < n_alts; alt++) 1159 { 1160 struct costs this_op_costs[MAX_RECOG_OPERANDS]; 1161 int alt_fail = 0; 1162 int alt_cost = 0; 1163 enum reg_class classes[MAX_RECOG_OPERANDS]; 1164 int class; 1165 1166 for (i = 0; i < n_ops; i++) 1167 { 1168 const char *p = constraints[i]; 1169 rtx op = ops[i]; 1170 enum machine_mode mode = modes[i]; 1171 int allows_addr = 0; 1172 int allows_mem = 0; 1173 int win = 0; 1174 unsigned char c; 1175 1176 /* Initially show we know nothing about the register class. */ 1177 classes[i] = NO_REGS; 1178 1179 /* If this operand has no constraints at all, we can conclude 1180 nothing about it since anything is valid. */ 1181 1182 if (*p == 0) 1183 { 1184 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1185 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]); 1186 1187 continue; 1188 } 1189 1190 /* If this alternative is only relevant when this operand 1191 matches a previous operand, we do different things depending 1192 on whether this operand is a pseudo-reg or not. We must process 1193 any modifiers for the operand before we can make this test. */ 1194 1195 while (*p == '%' || *p == '=' || *p == '+' || *p == '&') 1196 p++; 1197 1198 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) 1199 { 1200 j = p[0] - '0'; 1201 classes[i] = classes[j]; 1202 1203 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) 1204 { 1205 /* If this matches the other operand, we have no added 1206 cost and we win. */ 1207 if (rtx_equal_p (ops[j], op)) 1208 win = 1; 1209 1210 /* If we can put the other operand into a register, add to 1211 the cost of this alternative the cost to copy this 1212 operand to the register used for the other operand. */ 1213 1214 else if (classes[j] != NO_REGS) 1215 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; 1216 } 1217 else if (GET_CODE (ops[j]) != REG 1218 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) 1219 { 1220 /* This op is a pseudo but the one it matches is not. */ 1221 1222 /* If we can't put the other operand into a register, this 1223 alternative can't be used. */ 1224 1225 if (classes[j] == NO_REGS) 1226 alt_fail = 1; 1227 1228 /* Otherwise, add to the cost of this alternative the cost 1229 to copy the other operand to the register used for this 1230 operand. */ 1231 1232 else 1233 alt_cost += copy_cost (ops[j], mode, classes[j], 1); 1234 } 1235 else 1236 { 1237 /* The costs of this operand are the same as that of the 1238 other operand. However, if we cannot tie them, this 1239 alternative needs to do a copy, which is one 1240 instruction. */ 1241 1242 this_op_costs[i] = this_op_costs[j]; 1243 if (REGNO (ops[i]) != REGNO (ops[j]) 1244 && ! find_reg_note (insn, REG_DEAD, op)) 1245 alt_cost += 2; 1246 1247 /* This is in place of ordinary cost computation 1248 for this operand, so skip to the end of the 1249 alternative (should be just one character). */ 1250 while (*p && *p++ != ',') 1251 ; 1252 1253 constraints[i] = p; 1254 continue; 1255 } 1256 } 1257 1258 /* Scan all the constraint letters. See if the operand matches 1259 any of the constraints. Collect the valid register classes 1260 and see if this operand accepts memory. */ 1261 1262 while (*p && (c = *p++) != ',') 1263 switch (c) 1264 { 1265 case '*': 1266 /* Ignore the next letter for this pass. */ 1267 p++; 1268 break; 1269 1270 case '?': 1271 alt_cost += 2; 1272 case '!': case '#': case '&': 1273 case '0': case '1': case '2': case '3': case '4': 1274 case '5': case '6': case '7': case '8': case '9': 1275 break; 1276 1277 case 'p': 1278 allows_addr = 1; 1279 win = address_operand (op, GET_MODE (op)); 1280 /* We know this operand is an address, so we want it to be 1281 allocated to a register that can be the base of an 1282 address, ie BASE_REG_CLASS. */ 1283 classes[i] 1284 = reg_class_subunion[(int) classes[i]] 1285 [(int) BASE_REG_CLASS]; 1286 break; 1287 1288 case 'm': case 'o': case 'V': 1289 /* It doesn't seem worth distinguishing between offsettable 1290 and non-offsettable addresses here. */ 1291 allows_mem = 1; 1292 if (GET_CODE (op) == MEM) 1293 win = 1; 1294 break; 1295 1296 case '<': 1297 if (GET_CODE (op) == MEM 1298 && (GET_CODE (XEXP (op, 0)) == PRE_DEC 1299 || GET_CODE (XEXP (op, 0)) == POST_DEC)) 1300 win = 1; 1301 break; 1302 1303 case '>': 1304 if (GET_CODE (op) == MEM 1305 && (GET_CODE (XEXP (op, 0)) == PRE_INC 1306 || GET_CODE (XEXP (op, 0)) == POST_INC)) 1307 win = 1; 1308 break; 1309 1310 case 'E': 1311#ifndef REAL_ARITHMETIC 1312 /* Match any floating double constant, but only if 1313 we can examine the bits of it reliably. */ 1314 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT 1315 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) 1316 && GET_MODE (op) != VOIDmode && ! flag_pretend_float) 1317 break; 1318#endif 1319 if (GET_CODE (op) == CONST_DOUBLE) 1320 win = 1; 1321 break; 1322 1323 case 'F': 1324 if (GET_CODE (op) == CONST_DOUBLE) 1325 win = 1; 1326 break; 1327 1328 case 'G': 1329 case 'H': 1330 if (GET_CODE (op) == CONST_DOUBLE 1331 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) 1332 win = 1; 1333 break; 1334 1335 case 's': 1336 if (GET_CODE (op) == CONST_INT 1337 || (GET_CODE (op) == CONST_DOUBLE 1338 && GET_MODE (op) == VOIDmode)) 1339 break; 1340 case 'i': 1341 if (CONSTANT_P (op) 1342#ifdef LEGITIMATE_PIC_OPERAND_P 1343 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1344#endif 1345 ) 1346 win = 1; 1347 break; 1348 1349 case 'n': 1350 if (GET_CODE (op) == CONST_INT 1351 || (GET_CODE (op) == CONST_DOUBLE 1352 && GET_MODE (op) == VOIDmode)) 1353 win = 1; 1354 break; 1355 1356 case 'I': 1357 case 'J': 1358 case 'K': 1359 case 'L': 1360 case 'M': 1361 case 'N': 1362 case 'O': 1363 case 'P': 1364 if (GET_CODE (op) == CONST_INT 1365 && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) 1366 win = 1; 1367 break; 1368 1369 case 'X': 1370 win = 1; 1371 break; 1372 1373#ifdef EXTRA_CONSTRAINT 1374 case 'Q': 1375 case 'R': 1376 case 'S': 1377 case 'T': 1378 case 'U': 1379 if (EXTRA_CONSTRAINT (op, c)) 1380 win = 1; 1381 break; 1382#endif 1383 1384 case 'g': 1385 if (GET_CODE (op) == MEM 1386 || (CONSTANT_P (op) 1387#ifdef LEGITIMATE_PIC_OPERAND_P 1388 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1389#endif 1390 )) 1391 win = 1; 1392 allows_mem = 1; 1393 case 'r': 1394 classes[i] 1395 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; 1396 break; 1397 1398 default: 1399 classes[i] 1400 = reg_class_subunion[(int) classes[i]] 1401 [(int) REG_CLASS_FROM_LETTER (c)]; 1402 } 1403 1404 constraints[i] = p; 1405 1406#ifdef CLASS_CANNOT_CHANGE_SIZE 1407 /* If we noted a subreg earlier, and the selected class is a 1408 subclass of CLASS_CANNOT_CHANGE_SIZE, zap it. */ 1409 if (subreg_changes_size[i] 1410 && (reg_class_subunion[(int) CLASS_CANNOT_CHANGE_SIZE] 1411 [(int) classes[i]] 1412 == CLASS_CANNOT_CHANGE_SIZE)) 1413 classes[i] = NO_REGS; 1414#endif 1415 1416 /* How we account for this operand now depends on whether it is a 1417 pseudo register or not. If it is, we first check if any 1418 register classes are valid. If not, we ignore this alternative, 1419 since we want to assume that all pseudos get allocated for 1420 register preferencing. If some register class is valid, compute 1421 the costs of moving the pseudo into that class. */ 1422 1423 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1424 { 1425 if (classes[i] == NO_REGS) 1426 { 1427 /* We must always fail if the operand is a REG, but 1428 we did not find a suitable class. 1429 1430 Otherwise we may perform an uninitialized read 1431 from this_op_costs after the `continue' statement 1432 below. */ 1433 alt_fail = 1; 1434 } 1435 else 1436 { 1437 struct costs *pp = &this_op_costs[i]; 1438 1439 for (class = 0; class < N_REG_CLASSES; class++) 1440 pp->cost[class] = may_move_cost[class][(int) classes[i]]; 1441 1442 /* If the alternative actually allows memory, make things 1443 a bit cheaper since we won't need an extra insn to 1444 load it. */ 1445 1446 pp->mem_cost = (MEMORY_MOVE_COST (mode, classes[i], 1) 1447 - allows_mem); 1448 1449 /* If we have assigned a class to this register in our 1450 first pass, add a cost to this alternative corresponding 1451 to what we would add if this register were not in the 1452 appropriate class. */ 1453 1454 if (prefclass) 1455 alt_cost 1456 += may_move_cost[(unsigned char)prefclass[REGNO (op)]][(int) classes[i]]; 1457 } 1458 } 1459 1460 /* Otherwise, if this alternative wins, either because we 1461 have already determined that or if we have a hard register of 1462 the proper class, there is no cost for this alternative. */ 1463 1464 else if (win 1465 || (GET_CODE (op) == REG 1466 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) 1467 ; 1468 1469 /* If registers are valid, the cost of this alternative includes 1470 copying the object to and/or from a register. */ 1471 1472 else if (classes[i] != NO_REGS) 1473 { 1474 if (recog_op_type[i] != OP_OUT) 1475 alt_cost += copy_cost (op, mode, classes[i], 1); 1476 1477 if (recog_op_type[i] != OP_IN) 1478 alt_cost += copy_cost (op, mode, classes[i], 0); 1479 } 1480 1481 /* The only other way this alternative can be used is if this is a 1482 constant that could be placed into memory. */ 1483 1484 else if (CONSTANT_P (op) && (allows_addr || allows_mem)) 1485 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); 1486 else 1487 alt_fail = 1; 1488 } 1489 1490 if (alt_fail) 1491 continue; 1492 1493 /* Finally, update the costs with the information we've calculated 1494 about this alternative. */ 1495 1496 for (i = 0; i < n_ops; i++) 1497 if (GET_CODE (ops[i]) == REG 1498 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1499 { 1500 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; 1501 int scale = 1 + (recog_op_type[i] == OP_INOUT); 1502 1503 pp->mem_cost = MIN (pp->mem_cost, 1504 (qq->mem_cost + alt_cost) * scale); 1505 1506 for (class = 0; class < N_REG_CLASSES; class++) 1507 pp->cost[class] = MIN (pp->cost[class], 1508 (qq->cost[class] + alt_cost) * scale); 1509 } 1510 } 1511 1512 /* If this insn is a single set copying operand 1 to operand 0 1513 and one is a pseudo with the other a hard reg that is in its 1514 own register class, set the cost of that register class to -1. */ 1515 1516 if ((set = single_set (insn)) != 0 1517 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) 1518 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG) 1519 for (i = 0; i <= 1; i++) 1520 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1521 { 1522 int regno = REGNO (ops[!i]); 1523 enum machine_mode mode = GET_MODE (ops[!i]); 1524 int class; 1525 int nr; 1526 1527 if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0 1528 && (reg_class_size[(unsigned char)prefclass[regno]] 1529 == CLASS_MAX_NREGS (prefclass[regno], mode))) 1530 op_costs[i].cost[(unsigned char)prefclass[regno]] = -1; 1531 else if (regno < FIRST_PSEUDO_REGISTER) 1532 for (class = 0; class < N_REG_CLASSES; class++) 1533 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) 1534 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) 1535 { 1536 if (reg_class_size[class] == 1) 1537 op_costs[i].cost[class] = -1; 1538 else 1539 { 1540 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++) 1541 { 1542 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr)) 1543 break; 1544 } 1545 1546 if (nr == HARD_REGNO_NREGS(regno,mode)) 1547 op_costs[i].cost[class] = -1; 1548 } 1549 } 1550 } 1551} 1552 1553/* Compute the cost of loading X into (if TO_P is non-zero) or from (if 1554 TO_P is zero) a register of class CLASS in mode MODE. 1555 1556 X must not be a pseudo. */ 1557 1558static int 1559copy_cost (x, mode, class, to_p) 1560 rtx x; 1561 enum machine_mode mode; 1562 enum reg_class class; 1563 int to_p; 1564{ 1565#ifdef HAVE_SECONDARY_RELOADS 1566 enum reg_class secondary_class = NO_REGS; 1567#endif 1568 1569 /* If X is a SCRATCH, there is actually nothing to move since we are 1570 assuming optimal allocation. */ 1571 1572 if (GET_CODE (x) == SCRATCH) 1573 return 0; 1574 1575 /* Get the class we will actually use for a reload. */ 1576 class = PREFERRED_RELOAD_CLASS (x, class); 1577 1578#ifdef HAVE_SECONDARY_RELOADS 1579 /* If we need a secondary reload (we assume here that we are using 1580 the secondary reload as an intermediate, not a scratch register), the 1581 cost is that to load the input into the intermediate register, then 1582 to copy them. We use a special value of TO_P to avoid recursion. */ 1583 1584#ifdef SECONDARY_INPUT_RELOAD_CLASS 1585 if (to_p == 1) 1586 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); 1587#endif 1588 1589#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1590 if (! to_p) 1591 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); 1592#endif 1593 1594 if (secondary_class != NO_REGS) 1595 return (move_cost[(int) secondary_class][(int) class] 1596 + copy_cost (x, mode, secondary_class, 2)); 1597#endif /* HAVE_SECONDARY_RELOADS */ 1598 1599 /* For memory, use the memory move cost, for (hard) registers, use the 1600 cost to move between the register classes, and use 2 for everything 1601 else (constants). */ 1602 1603 if (GET_CODE (x) == MEM || class == NO_REGS) 1604 return MEMORY_MOVE_COST (mode, class, to_p); 1605 1606 else if (GET_CODE (x) == REG) 1607 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; 1608 1609 else 1610 /* If this is a constant, we may eventually want to call rtx_cost here. */ 1611 return 2; 1612} 1613 1614/* Record the pseudo registers we must reload into hard registers 1615 in a subexpression of a memory address, X. 1616 1617 CLASS is the class that the register needs to be in and is either 1618 BASE_REG_CLASS or INDEX_REG_CLASS. 1619 1620 SCALE is twice the amount to multiply the cost by (it is twice so we 1621 can represent half-cost adjustments). */ 1622 1623static void 1624record_address_regs (x, class, scale) 1625 rtx x; 1626 enum reg_class class; 1627 int scale; 1628{ 1629 register enum rtx_code code = GET_CODE (x); 1630 1631 switch (code) 1632 { 1633 case CONST_INT: 1634 case CONST: 1635 case CC0: 1636 case PC: 1637 case SYMBOL_REF: 1638 case LABEL_REF: 1639 return; 1640 1641 case PLUS: 1642 /* When we have an address that is a sum, 1643 we must determine whether registers are "base" or "index" regs. 1644 If there is a sum of two registers, we must choose one to be 1645 the "base". Luckily, we can use the REGNO_POINTER_FLAG 1646 to make a good choice most of the time. We only need to do this 1647 on machines that can have two registers in an address and where 1648 the base and index register classes are different. 1649 1650 ??? This code used to set REGNO_POINTER_FLAG in some cases, but 1651 that seems bogus since it should only be set when we are sure 1652 the register is being used as a pointer. */ 1653 1654 { 1655 rtx arg0 = XEXP (x, 0); 1656 rtx arg1 = XEXP (x, 1); 1657 register enum rtx_code code0 = GET_CODE (arg0); 1658 register enum rtx_code code1 = GET_CODE (arg1); 1659 1660 /* Look inside subregs. */ 1661 if (code0 == SUBREG) 1662 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); 1663 if (code1 == SUBREG) 1664 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); 1665 1666 /* If this machine only allows one register per address, it must 1667 be in the first operand. */ 1668 1669 if (MAX_REGS_PER_ADDRESS == 1) 1670 record_address_regs (arg0, class, scale); 1671 1672 /* If index and base registers are the same on this machine, just 1673 record registers in any non-constant operands. We assume here, 1674 as well as in the tests below, that all addresses are in 1675 canonical form. */ 1676 1677 else if (INDEX_REG_CLASS == BASE_REG_CLASS) 1678 { 1679 record_address_regs (arg0, class, scale); 1680 if (! CONSTANT_P (arg1)) 1681 record_address_regs (arg1, class, scale); 1682 } 1683 1684 /* If the second operand is a constant integer, it doesn't change 1685 what class the first operand must be. */ 1686 1687 else if (code1 == CONST_INT || code1 == CONST_DOUBLE) 1688 record_address_regs (arg0, class, scale); 1689 1690 /* If the second operand is a symbolic constant, the first operand 1691 must be an index register. */ 1692 1693 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) 1694 record_address_regs (arg0, INDEX_REG_CLASS, scale); 1695 1696 /* If both operands are registers but one is already a hard register 1697 of index or base class, give the other the class that the hard 1698 register is not. */ 1699 1700#ifdef REG_OK_FOR_BASE_P 1701 else if (code0 == REG && code1 == REG 1702 && REGNO (arg0) < FIRST_PSEUDO_REGISTER 1703 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) 1704 record_address_regs (arg1, 1705 REG_OK_FOR_BASE_P (arg0) 1706 ? INDEX_REG_CLASS : BASE_REG_CLASS, 1707 scale); 1708 else if (code0 == REG && code1 == REG 1709 && REGNO (arg1) < FIRST_PSEUDO_REGISTER 1710 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) 1711 record_address_regs (arg0, 1712 REG_OK_FOR_BASE_P (arg1) 1713 ? INDEX_REG_CLASS : BASE_REG_CLASS, 1714 scale); 1715#endif 1716 1717 /* If one operand is known to be a pointer, it must be the base 1718 with the other operand the index. Likewise if the other operand 1719 is a MULT. */ 1720 1721 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0))) 1722 || code1 == MULT) 1723 { 1724 record_address_regs (arg0, BASE_REG_CLASS, scale); 1725 record_address_regs (arg1, INDEX_REG_CLASS, scale); 1726 } 1727 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1))) 1728 || code0 == MULT) 1729 { 1730 record_address_regs (arg0, INDEX_REG_CLASS, scale); 1731 record_address_regs (arg1, BASE_REG_CLASS, scale); 1732 } 1733 1734 /* Otherwise, count equal chances that each might be a base 1735 or index register. This case should be rare. */ 1736 1737 else 1738 { 1739 record_address_regs (arg0, BASE_REG_CLASS, scale / 2); 1740 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); 1741 record_address_regs (arg1, BASE_REG_CLASS, scale / 2); 1742 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); 1743 } 1744 } 1745 break; 1746 1747 case POST_INC: 1748 case PRE_INC: 1749 case POST_DEC: 1750 case PRE_DEC: 1751 /* Double the importance of a pseudo register that is incremented 1752 or decremented, since it would take two extra insns 1753 if it ends up in the wrong place. If the operand is a pseudo, 1754 show it is being used in an INC_DEC context. */ 1755 1756#ifdef FORBIDDEN_INC_DEC_CLASSES 1757 if (GET_CODE (XEXP (x, 0)) == REG 1758 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) 1759 in_inc_dec[REGNO (XEXP (x, 0))] = 1; 1760#endif 1761 1762 record_address_regs (XEXP (x, 0), class, 2 * scale); 1763 break; 1764 1765 case REG: 1766 { 1767 register struct costs *pp = &costs[REGNO (x)]; 1768 register int i; 1769 1770 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; 1771 1772 for (i = 0; i < N_REG_CLASSES; i++) 1773 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2; 1774 } 1775 break; 1776 1777 default: 1778 { 1779 register char *fmt = GET_RTX_FORMAT (code); 1780 register int i; 1781 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1782 if (fmt[i] == 'e') 1783 record_address_regs (XEXP (x, i), class, scale); 1784 } 1785 } 1786} 1787 1788#ifdef FORBIDDEN_INC_DEC_CLASSES 1789 1790/* Return 1 if REG is valid as an auto-increment memory reference 1791 to an object of MODE. */ 1792 1793static int 1794auto_inc_dec_reg_p (reg, mode) 1795 rtx reg; 1796 enum machine_mode mode; 1797{ 1798 if (HAVE_POST_INCREMENT 1799 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) 1800 return 1; 1801 1802 if (HAVE_POST_DECREMENT 1803 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) 1804 return 1; 1805 1806 if (HAVE_PRE_INCREMENT 1807 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) 1808 return 1; 1809 1810 if (HAVE_PRE_DECREMENT 1811 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) 1812 return 1; 1813 1814 return 0; 1815} 1816#endif 1817 1818#endif /* REGISTER_CONSTRAINTS */ 1819 1820static short *renumber = (short *)0; 1821static size_t regno_allocated = 0; 1822 1823/* Allocate enough space to hold NUM_REGS registers for the tables used for 1824 reg_scan and flow_analysis that are indexed by the register number. If 1825 NEW_P is non zero, initialize all of the registers, otherwise only 1826 initialize the new registers allocated. The same table is kept from 1827 function to function, only reallocating it when we need more room. If 1828 RENUMBER_P is non zero, allocate the reg_renumber array also. */ 1829 1830void 1831allocate_reg_info (num_regs, new_p, renumber_p) 1832 size_t num_regs; 1833 int new_p; 1834 int renumber_p; 1835{ 1836 size_t size_info; 1837 size_t size_renumber; 1838 size_t min = (new_p) ? 0 : reg_n_max; 1839 struct reg_info_data *reg_data; 1840 struct reg_info_data *reg_next; 1841 1842 if (num_regs > regno_allocated) 1843 { 1844 size_t old_allocated = regno_allocated; 1845 1846 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ 1847 size_renumber = regno_allocated * sizeof (short); 1848 1849 if (!reg_n_info) 1850 { 1851 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); 1852 renumber = (short *) xmalloc (size_renumber); 1853 prefclass_buffer = (char *) xmalloc (regno_allocated); 1854 altclass_buffer = (char *) xmalloc (regno_allocated); 1855 } 1856 1857 else 1858 { 1859 VARRAY_GROW (reg_n_info, regno_allocated); 1860 1861 if (new_p) /* if we're zapping everything, no need to realloc */ 1862 { 1863 free ((char *)renumber); 1864 free ((char *)prefclass_buffer); 1865 free ((char *)altclass_buffer); 1866 renumber = (short *) xmalloc (size_renumber); 1867 prefclass_buffer = (char *) xmalloc (regno_allocated); 1868 altclass_buffer = (char *) xmalloc (regno_allocated); 1869 } 1870 1871 else 1872 { 1873 renumber = (short *) xrealloc ((char *)renumber, size_renumber); 1874 prefclass_buffer = (char *) xrealloc ((char *)prefclass_buffer, 1875 regno_allocated); 1876 1877 altclass_buffer = (char *) xrealloc ((char *)altclass_buffer, 1878 regno_allocated); 1879 } 1880 } 1881 1882 size_info = (regno_allocated - old_allocated) * sizeof (reg_info) 1883 + sizeof (struct reg_info_data) - sizeof (reg_info); 1884 reg_data = (struct reg_info_data *) xcalloc (size_info, 1); 1885 reg_data->min_index = old_allocated; 1886 reg_data->max_index = regno_allocated - 1; 1887 reg_data->next = reg_info_head; 1888 reg_info_head = reg_data; 1889 } 1890 1891 reg_n_max = num_regs; 1892 if (min < num_regs) 1893 { 1894 /* Loop through each of the segments allocated for the actual 1895 reg_info pages, and set up the pointers, zero the pages, etc. */ 1896 for (reg_data = reg_info_head; reg_data; reg_data = reg_next) 1897 { 1898 size_t min_index = reg_data->min_index; 1899 size_t max_index = reg_data->max_index; 1900 1901 reg_next = reg_data->next; 1902 if (min <= max_index) 1903 { 1904 size_t max = max_index; 1905 size_t local_min = min - min_index; 1906 size_t i; 1907 1908 if (min < min_index) 1909 local_min = 0; 1910 if (!reg_data->used_p) /* page just allocated with calloc */ 1911 reg_data->used_p = 1; /* no need to zero */ 1912 else 1913 bzero ((char *) ®_data->data[local_min], 1914 sizeof (reg_info) * (max - min_index - local_min + 1)); 1915 1916 for (i = min_index+local_min; i <= max; i++) 1917 { 1918 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; 1919 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; 1920 renumber[i] = -1; 1921 prefclass_buffer[i] = (char) NO_REGS; 1922 altclass_buffer[i] = (char) NO_REGS; 1923 } 1924 } 1925 } 1926 } 1927 1928 /* If {pref,alt}class have already been allocated, update the pointers to 1929 the newly realloced ones. */ 1930 if (prefclass) 1931 { 1932 prefclass = prefclass_buffer; 1933 altclass = altclass_buffer; 1934 } 1935 1936 if (renumber_p) 1937 reg_renumber = renumber; 1938 1939 /* Tell the regset code about the new number of registers */ 1940 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); 1941} 1942 1943/* Free up the space allocated by allocate_reg_info. */ 1944void 1945free_reg_info () 1946{ 1947 if (reg_n_info) 1948 { 1949 struct reg_info_data *reg_data; 1950 struct reg_info_data *reg_next; 1951 1952 VARRAY_FREE (reg_n_info); 1953 for (reg_data = reg_info_head; reg_data; reg_data = reg_next) 1954 { 1955 reg_next = reg_data->next; 1956 free ((char *)reg_data); 1957 } 1958 1959 free (prefclass_buffer); 1960 free (altclass_buffer); 1961 prefclass_buffer = (char *)0; 1962 altclass_buffer = (char *)0; 1963 reg_info_head = (struct reg_info_data *)0; 1964 renumber = (short *)0; 1965 } 1966 regno_allocated = 0; 1967 reg_n_max = 0; 1968} 1969 1970/* This is the `regscan' pass of the compiler, run just before cse 1971 and again just before loop. 1972 1973 It finds the first and last use of each pseudo-register 1974 and records them in the vectors regno_first_uid, regno_last_uid 1975 and counts the number of sets in the vector reg_n_sets. 1976 1977 REPEAT is nonzero the second time this is called. */ 1978 1979/* Maximum number of parallel sets and clobbers in any insn in this fn. 1980 Always at least 3, since the combiner could put that many together 1981 and we want this to remain correct for all the remaining passes. */ 1982 1983int max_parallel; 1984 1985void 1986reg_scan (f, nregs, repeat) 1987 rtx f; 1988 int nregs; 1989 int repeat; 1990{ 1991 register rtx insn; 1992 1993 allocate_reg_info (nregs, TRUE, FALSE); 1994 max_parallel = 3; 1995 1996 for (insn = f; insn; insn = NEXT_INSN (insn)) 1997 if (GET_CODE (insn) == INSN 1998 || GET_CODE (insn) == CALL_INSN 1999 || GET_CODE (insn) == JUMP_INSN) 2000 { 2001 if (GET_CODE (PATTERN (insn)) == PARALLEL 2002 && XVECLEN (PATTERN (insn), 0) > max_parallel) 2003 max_parallel = XVECLEN (PATTERN (insn), 0); 2004 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0); 2005 2006 if (REG_NOTES (insn)) 2007 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); 2008 } 2009} 2010 2011/* Update 'regscan' information by looking at the insns 2012 from FIRST to LAST. Some new REGs have been created, 2013 and any REG with number greater than OLD_MAX_REGNO is 2014 such a REG. We only update information for those. */ 2015 2016void 2017reg_scan_update(first, last, old_max_regno) 2018 rtx first; 2019 rtx last; 2020 int old_max_regno; 2021{ 2022 register rtx insn; 2023 2024 allocate_reg_info (max_reg_num (), FALSE, FALSE); 2025 2026 for (insn = first; insn != last; insn = NEXT_INSN (insn)) 2027 if (GET_CODE (insn) == INSN 2028 || GET_CODE (insn) == CALL_INSN 2029 || GET_CODE (insn) == JUMP_INSN) 2030 { 2031 if (GET_CODE (PATTERN (insn)) == PARALLEL 2032 && XVECLEN (PATTERN (insn), 0) > max_parallel) 2033 max_parallel = XVECLEN (PATTERN (insn), 0); 2034 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno); 2035 2036 if (REG_NOTES (insn)) 2037 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); 2038 } 2039} 2040 2041/* X is the expression to scan. INSN is the insn it appears in. 2042 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. 2043 We should only record information for REGs with numbers 2044 greater than or equal to MIN_REGNO. */ 2045 2046static void 2047reg_scan_mark_refs (x, insn, note_flag, min_regno) 2048 rtx x; 2049 rtx insn; 2050 int note_flag; 2051 int min_regno; 2052{ 2053 register enum rtx_code code; 2054 register rtx dest; 2055 register rtx note; 2056 2057 code = GET_CODE (x); 2058 switch (code) 2059 { 2060 case CONST: 2061 case CONST_INT: 2062 case CONST_DOUBLE: 2063 case CC0: 2064 case PC: 2065 case SYMBOL_REF: 2066 case LABEL_REF: 2067 case ADDR_VEC: 2068 case ADDR_DIFF_VEC: 2069 return; 2070 2071 case REG: 2072 { 2073 register int regno = REGNO (x); 2074 2075 if (regno >= min_regno) 2076 { 2077 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); 2078 if (!note_flag) 2079 REGNO_LAST_UID (regno) = INSN_UID (insn); 2080 if (REGNO_FIRST_UID (regno) == 0) 2081 REGNO_FIRST_UID (regno) = INSN_UID (insn); 2082 } 2083 } 2084 break; 2085 2086 case EXPR_LIST: 2087 if (XEXP (x, 0)) 2088 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); 2089 if (XEXP (x, 1)) 2090 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); 2091 break; 2092 2093 case INSN_LIST: 2094 if (XEXP (x, 1)) 2095 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); 2096 break; 2097 2098 case SET: 2099 /* Count a set of the destination if it is a register. */ 2100 for (dest = SET_DEST (x); 2101 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART 2102 || GET_CODE (dest) == ZERO_EXTEND; 2103 dest = XEXP (dest, 0)) 2104 ; 2105 2106 if (GET_CODE (dest) == REG 2107 && REGNO (dest) >= min_regno) 2108 REG_N_SETS (REGNO (dest))++; 2109 2110 /* If this is setting a pseudo from another pseudo or the sum of a 2111 pseudo and a constant integer and the other pseudo is known to be 2112 a pointer, set the destination to be a pointer as well. 2113 2114 Likewise if it is setting the destination from an address or from a 2115 value equivalent to an address or to the sum of an address and 2116 something else. 2117 2118 But don't do any of this if the pseudo corresponds to a user 2119 variable since it should have already been set as a pointer based 2120 on the type. */ 2121 2122 if (GET_CODE (SET_DEST (x)) == REG 2123 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER 2124 && REGNO (SET_DEST (x)) >= min_regno 2125 /* If the destination pseudo is set more than once, then other 2126 sets might not be to a pointer value (consider access to a 2127 union in two threads of control in the presense of global 2128 optimizations). So only set REGNO_POINTER_FLAG on the destination 2129 pseudo if this is the only set of that pseudo. */ 2130 && REG_N_SETS (REGNO (SET_DEST (x))) == 1 2131 && ! REG_USERVAR_P (SET_DEST (x)) 2132 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) 2133 && ((GET_CODE (SET_SRC (x)) == REG 2134 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x)))) 2135 || ((GET_CODE (SET_SRC (x)) == PLUS 2136 || GET_CODE (SET_SRC (x)) == LO_SUM) 2137 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 2138 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG 2139 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0)))) 2140 || GET_CODE (SET_SRC (x)) == CONST 2141 || GET_CODE (SET_SRC (x)) == SYMBOL_REF 2142 || GET_CODE (SET_SRC (x)) == LABEL_REF 2143 || (GET_CODE (SET_SRC (x)) == HIGH 2144 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST 2145 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF 2146 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) 2147 || ((GET_CODE (SET_SRC (x)) == PLUS 2148 || GET_CODE (SET_SRC (x)) == LO_SUM) 2149 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST 2150 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF 2151 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) 2152 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 2153 && (GET_CODE (XEXP (note, 0)) == CONST 2154 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF 2155 || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) 2156 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1; 2157 2158 /* ... fall through ... */ 2159 2160 default: 2161 { 2162 register char *fmt = GET_RTX_FORMAT (code); 2163 register int i; 2164 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2165 { 2166 if (fmt[i] == 'e') 2167 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); 2168 else if (fmt[i] == 'E' && XVEC (x, i) != 0) 2169 { 2170 register int j; 2171 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 2172 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); 2173 } 2174 } 2175 } 2176 } 2177} 2178 2179/* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 2180 is also in C2. */ 2181 2182int 2183reg_class_subset_p (c1, c2) 2184 register enum reg_class c1; 2185 register enum reg_class c2; 2186{ 2187 if (c1 == c2) return 1; 2188 2189 if (c2 == ALL_REGS) 2190 win: 2191 return 1; 2192 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], 2193 reg_class_contents[(int)c2], 2194 win); 2195 return 0; 2196} 2197 2198/* Return nonzero if there is a register that is in both C1 and C2. */ 2199 2200int 2201reg_classes_intersect_p (c1, c2) 2202 register enum reg_class c1; 2203 register enum reg_class c2; 2204{ 2205#ifdef HARD_REG_SET 2206 register 2207#endif 2208 HARD_REG_SET c; 2209 2210 if (c1 == c2) return 1; 2211 2212 if (c1 == ALL_REGS || c2 == ALL_REGS) 2213 return 1; 2214 2215 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); 2216 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); 2217 2218 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); 2219 return 1; 2220 2221 lose: 2222 return 0; 2223} 2224 2225/* Release any memory allocated by register sets. */ 2226 2227void 2228regset_release_memory () 2229{ 2230 bitmap_release_memory (); 2231} 2232