regclass.c revision 50397
1/* Compute register class preferences for pseudo-registers. 2 Copyright (C) 1987, 88, 91-97, 1998 Free Software Foundation, Inc. 3 4This file is part of GNU CC. 5 6GNU CC is free software; you can redistribute it and/or modify 7it under the terms of the GNU General Public License as published by 8the Free Software Foundation; either version 2, or (at your option) 9any later version. 10 11GNU CC is distributed in the hope that it will be useful, 12but WITHOUT ANY WARRANTY; without even the implied warranty of 13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14GNU General Public License for more details. 15 16You should have received a copy of the GNU General Public License 17along with GNU CC; see the file COPYING. If not, write to 18the Free Software Foundation, 59 Temple Place - Suite 330, 19Boston, MA 02111-1307, USA. */ 20 21 22/* This file contains two passes of the compiler: reg_scan and reg_class. 23 It also defines some tables of information about the hardware registers 24 and a function init_reg_sets to initialize the tables. */ 25 26#include "config.h" 27#include "system.h" 28#include "rtl.h" 29#include "hard-reg-set.h" 30#include "flags.h" 31#include "basic-block.h" 32#include "regs.h" 33#include "insn-config.h" 34#include "recog.h" 35#include "reload.h" 36#include "real.h" 37#include "toplev.h" 38#include "output.h" 39 40#ifndef REGISTER_MOVE_COST 41#define REGISTER_MOVE_COST(x, y) 2 42#endif 43 44/* If we have auto-increment or auto-decrement and we can have secondary 45 reloads, we are not allowed to use classes requiring secondary 46 reloads for pseudos auto-incremented since reload can't handle it. */ 47 48#ifdef AUTO_INC_DEC 49#if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) 50#define FORBIDDEN_INC_DEC_CLASSES 51#endif 52#endif 53 54/* Register tables used by many passes. */ 55 56/* Indexed by hard register number, contains 1 for registers 57 that are fixed use (stack pointer, pc, frame pointer, etc.). 58 These are the registers that cannot be used to allocate 59 a pseudo reg whose life does not cross calls. */ 60 61char fixed_regs[FIRST_PSEUDO_REGISTER]; 62 63/* Same info as a HARD_REG_SET. */ 64 65HARD_REG_SET fixed_reg_set; 66 67/* Data for initializing the above. */ 68 69static char initial_fixed_regs[] = FIXED_REGISTERS; 70 71/* Indexed by hard register number, contains 1 for registers 72 that are fixed use or are clobbered by function calls. 73 These are the registers that cannot be used to allocate 74 a pseudo reg whose life crosses calls. */ 75 76char call_used_regs[FIRST_PSEUDO_REGISTER]; 77 78/* Same info as a HARD_REG_SET. */ 79 80HARD_REG_SET call_used_reg_set; 81 82/* HARD_REG_SET of registers we want to avoid caller saving. */ 83HARD_REG_SET losing_caller_save_reg_set; 84 85/* Data for initializing the above. */ 86 87static char initial_call_used_regs[] = CALL_USED_REGISTERS; 88 89/* Indexed by hard register number, contains 1 for registers that are 90 fixed use -- i.e. in fixed_regs -- or a function value return register 91 or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the 92 registers that cannot hold quantities across calls even if we are 93 willing to save and restore them. */ 94 95char call_fixed_regs[FIRST_PSEUDO_REGISTER]; 96 97/* The same info as a HARD_REG_SET. */ 98 99HARD_REG_SET call_fixed_reg_set; 100 101/* Number of non-fixed registers. */ 102 103int n_non_fixed_regs; 104 105/* Indexed by hard register number, contains 1 for registers 106 that are being used for global register decls. 107 These must be exempt from ordinary flow analysis 108 and are also considered fixed. */ 109 110char global_regs[FIRST_PSEUDO_REGISTER]; 111 112/* Table of register numbers in the order in which to try to use them. */ 113#ifdef REG_ALLOC_ORDER 114int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; 115#endif 116 117/* For each reg class, a HARD_REG_SET saying which registers are in it. */ 118 119HARD_REG_SET reg_class_contents[N_REG_CLASSES]; 120 121/* The same information, but as an array of unsigned ints. We copy from 122 these unsigned ints to the table above. We do this so the tm.h files 123 do not have to be aware of the wordsize for machines with <= 64 regs. */ 124 125#define N_REG_INTS \ 126 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT) 127 128static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] 129 = REG_CLASS_CONTENTS; 130 131/* For each reg class, number of regs it contains. */ 132 133int reg_class_size[N_REG_CLASSES]; 134 135/* For each reg class, table listing all the containing classes. */ 136 137enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; 138 139/* For each reg class, table listing all the classes contained in it. */ 140 141enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; 142 143/* For each pair of reg classes, 144 a largest reg class contained in their union. */ 145 146enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; 147 148/* For each pair of reg classes, 149 the smallest reg class containing their union. */ 150 151enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; 152 153/* Array containing all of the register names */ 154 155char *reg_names[] = REGISTER_NAMES; 156 157/* For each hard register, the widest mode object that it can contain. 158 This will be a MODE_INT mode if the register can hold integers. Otherwise 159 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the 160 register. */ 161 162enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; 163 164/* Maximum cost of moving from a register in one class to a register in 165 another class. Based on REGISTER_MOVE_COST. */ 166 167static int move_cost[N_REG_CLASSES][N_REG_CLASSES]; 168 169/* Similar, but here we don't have to move if the first index is a subset 170 of the second so in that case the cost is zero. */ 171 172static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES]; 173 174#ifdef FORBIDDEN_INC_DEC_CLASSES 175 176/* These are the classes that regs which are auto-incremented or decremented 177 cannot be put in. */ 178 179static int forbidden_inc_dec_class[N_REG_CLASSES]; 180 181/* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec 182 context. */ 183 184static char *in_inc_dec; 185 186#endif /* FORBIDDEN_INC_DEC_CLASSES */ 187 188#ifdef HAVE_SECONDARY_RELOADS 189 190/* Sample MEM values for use by memory_move_secondary_cost. */ 191 192static rtx top_of_stack[MAX_MACHINE_MODE]; 193 194#endif /* HAVE_SECONDARY_RELOADS */ 195 196/* Linked list of reg_info structures allocated for reg_n_info array. 197 Grouping all of the allocated structures together in one lump 198 means only one call to bzero to clear them, rather than n smaller 199 calls. */ 200struct reg_info_data { 201 struct reg_info_data *next; /* next set of reg_info structures */ 202 size_t min_index; /* minimum index # */ 203 size_t max_index; /* maximum index # */ 204 char used_p; /* non-zero if this has been used previously */ 205 reg_info data[1]; /* beginning of the reg_info data */ 206}; 207 208static struct reg_info_data *reg_info_head; 209 210 211/* Function called only once to initialize the above data on reg usage. 212 Once this is done, various switches may override. */ 213 214void 215init_reg_sets () 216{ 217 register int i, j; 218 219 /* First copy the register information from the initial int form into 220 the regsets. */ 221 222 for (i = 0; i < N_REG_CLASSES; i++) 223 { 224 CLEAR_HARD_REG_SET (reg_class_contents[i]); 225 226 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 227 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT] 228 & ((unsigned) 1 << (j % HOST_BITS_PER_INT))) 229 SET_HARD_REG_BIT (reg_class_contents[i], j); 230 } 231 232 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); 233 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); 234 bzero (global_regs, sizeof global_regs); 235 236 /* Compute number of hard regs in each class. */ 237 238 bzero ((char *) reg_class_size, sizeof reg_class_size); 239 for (i = 0; i < N_REG_CLASSES; i++) 240 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 241 if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 242 reg_class_size[i]++; 243 244 /* Initialize the table of subunions. 245 reg_class_subunion[I][J] gets the largest-numbered reg-class 246 that is contained in the union of classes I and J. */ 247 248 for (i = 0; i < N_REG_CLASSES; i++) 249 { 250 for (j = 0; j < N_REG_CLASSES; j++) 251 { 252#ifdef HARD_REG_SET 253 register /* Declare it register if it's a scalar. */ 254#endif 255 HARD_REG_SET c; 256 register int k; 257 258 COPY_HARD_REG_SET (c, reg_class_contents[i]); 259 IOR_HARD_REG_SET (c, reg_class_contents[j]); 260 for (k = 0; k < N_REG_CLASSES; k++) 261 { 262 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, 263 subclass1); 264 continue; 265 266 subclass1: 267 /* keep the largest subclass */ /* SPEE 900308 */ 268 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], 269 reg_class_contents[(int) reg_class_subunion[i][j]], 270 subclass2); 271 reg_class_subunion[i][j] = (enum reg_class) k; 272 subclass2: 273 ; 274 } 275 } 276 } 277 278 /* Initialize the table of superunions. 279 reg_class_superunion[I][J] gets the smallest-numbered reg-class 280 containing the union of classes I and J. */ 281 282 for (i = 0; i < N_REG_CLASSES; i++) 283 { 284 for (j = 0; j < N_REG_CLASSES; j++) 285 { 286#ifdef HARD_REG_SET 287 register /* Declare it register if it's a scalar. */ 288#endif 289 HARD_REG_SET c; 290 register int k; 291 292 COPY_HARD_REG_SET (c, reg_class_contents[i]); 293 IOR_HARD_REG_SET (c, reg_class_contents[j]); 294 for (k = 0; k < N_REG_CLASSES; k++) 295 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); 296 297 superclass: 298 reg_class_superunion[i][j] = (enum reg_class) k; 299 } 300 } 301 302 /* Initialize the tables of subclasses and superclasses of each reg class. 303 First clear the whole table, then add the elements as they are found. */ 304 305 for (i = 0; i < N_REG_CLASSES; i++) 306 { 307 for (j = 0; j < N_REG_CLASSES; j++) 308 { 309 reg_class_superclasses[i][j] = LIM_REG_CLASSES; 310 reg_class_subclasses[i][j] = LIM_REG_CLASSES; 311 } 312 } 313 314 for (i = 0; i < N_REG_CLASSES; i++) 315 { 316 if (i == (int) NO_REGS) 317 continue; 318 319 for (j = i + 1; j < N_REG_CLASSES; j++) 320 { 321 enum reg_class *p; 322 323 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], 324 subclass); 325 continue; 326 subclass: 327 /* Reg class I is a subclass of J. 328 Add J to the table of superclasses of I. */ 329 p = ®_class_superclasses[i][0]; 330 while (*p != LIM_REG_CLASSES) p++; 331 *p = (enum reg_class) j; 332 /* Add I to the table of superclasses of J. */ 333 p = ®_class_subclasses[j][0]; 334 while (*p != LIM_REG_CLASSES) p++; 335 *p = (enum reg_class) i; 336 } 337 } 338 339 /* Do any additional initialization regsets may need */ 340 INIT_ONCE_REG_SET (); 341} 342 343/* After switches have been processed, which perhaps alter 344 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ 345 346static void 347init_reg_sets_1 () 348{ 349 register unsigned int i, j; 350 351 /* This macro allows the fixed or call-used registers 352 to depend on target flags. */ 353 354#ifdef CONDITIONAL_REGISTER_USAGE 355 CONDITIONAL_REGISTER_USAGE; 356#endif 357 358 /* Initialize "constant" tables. */ 359 360 CLEAR_HARD_REG_SET (fixed_reg_set); 361 CLEAR_HARD_REG_SET (call_used_reg_set); 362 CLEAR_HARD_REG_SET (call_fixed_reg_set); 363 364 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); 365 366 n_non_fixed_regs = 0; 367 368 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 369 { 370 if (fixed_regs[i]) 371 SET_HARD_REG_BIT (fixed_reg_set, i); 372 else 373 n_non_fixed_regs++; 374 375 if (call_used_regs[i]) 376 SET_HARD_REG_BIT (call_used_reg_set, i); 377 if (call_fixed_regs[i]) 378 SET_HARD_REG_BIT (call_fixed_reg_set, i); 379 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) 380 SET_HARD_REG_BIT (losing_caller_save_reg_set, i); 381 } 382 383 /* Initialize the move cost table. Find every subset of each class 384 and take the maximum cost of moving any subset to any other. */ 385 386 for (i = 0; i < N_REG_CLASSES; i++) 387 for (j = 0; j < N_REG_CLASSES; j++) 388 { 389 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j); 390 enum reg_class *p1, *p2; 391 392 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) 393 if (*p2 != i) 394 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2)); 395 396 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) 397 { 398 if (*p1 != j) 399 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j)); 400 401 for (p2 = ®_class_subclasses[j][0]; 402 *p2 != LIM_REG_CLASSES; p2++) 403 if (*p1 != *p2) 404 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2)); 405 } 406 407 move_cost[i][j] = cost; 408 409 if (reg_class_subset_p (i, j)) 410 cost = 0; 411 412 may_move_cost[i][j] = cost; 413 } 414} 415 416/* Compute the table of register modes. 417 These values are used to record death information for individual registers 418 (as opposed to a multi-register mode). */ 419 420static void 421init_reg_modes () 422{ 423 register int i; 424 425 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 426 { 427 reg_raw_mode[i] = choose_hard_reg_mode (i, 1); 428 429 /* If we couldn't find a valid mode, just use the previous mode. 430 ??? One situation in which we need to do this is on the mips where 431 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like 432 to use DF mode for the even registers and VOIDmode for the odd 433 (for the cpu models where the odd ones are inaccessible). */ 434 if (reg_raw_mode[i] == VOIDmode) 435 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; 436 } 437} 438 439/* Finish initializing the register sets and 440 initialize the register modes. */ 441 442void 443init_regs () 444{ 445 /* This finishes what was started by init_reg_sets, but couldn't be done 446 until after register usage was specified. */ 447 init_reg_sets_1 (); 448 449 init_reg_modes (); 450 451#ifdef HAVE_SECONDARY_RELOADS 452 { 453 /* Make some fake stack-frame MEM references for use in 454 memory_move_secondary_cost. */ 455 int i; 456 for (i = 0; i < MAX_MACHINE_MODE; i++) 457 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); 458 } 459#endif 460} 461 462#ifdef HAVE_SECONDARY_RELOADS 463 464/* Compute extra cost of moving registers to/from memory due to reloads. 465 Only needed if secondary reloads are required for memory moves. */ 466 467int 468memory_move_secondary_cost (mode, class, in) 469 enum machine_mode mode; 470 enum reg_class class; 471 int in; 472{ 473 enum reg_class altclass; 474 int partial_cost = 0; 475 /* We need a memory reference to feed to SECONDARY... macros. */ 476 rtx mem = top_of_stack[(int) mode]; 477 478 if (in) 479 { 480#ifdef SECONDARY_INPUT_RELOAD_CLASS 481 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); 482#else 483 altclass = NO_REGS; 484#endif 485 } 486 else 487 { 488#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 489 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); 490#else 491 altclass = NO_REGS; 492#endif 493 } 494 495 if (altclass == NO_REGS) 496 return 0; 497 498 if (in) 499 partial_cost = REGISTER_MOVE_COST (altclass, class); 500 else 501 partial_cost = REGISTER_MOVE_COST (class, altclass); 502 503 if (class == altclass) 504 /* This isn't simply a copy-to-temporary situation. Can't guess 505 what it is, so MEMORY_MOVE_COST really ought not to be calling 506 here in that case. 507 508 I'm tempted to put in an abort here, but returning this will 509 probably only give poor estimates, which is what we would've 510 had before this code anyways. */ 511 return partial_cost; 512 513 /* Check if the secondary reload register will also need a 514 secondary reload. */ 515 return memory_move_secondary_cost (mode, altclass, in) + partial_cost; 516} 517#endif 518 519/* Return a machine mode that is legitimate for hard reg REGNO and large 520 enough to save nregs. If we can't find one, return VOIDmode. */ 521 522enum machine_mode 523choose_hard_reg_mode (regno, nregs) 524 int regno; 525 int nregs; 526{ 527 enum machine_mode found_mode = VOIDmode, mode; 528 529 /* We first look for the largest integer mode that can be validly 530 held in REGNO. If none, we look for the largest floating-point mode. 531 If we still didn't find a valid mode, try CCmode. */ 532 533 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); 534 mode != VOIDmode; 535 mode = GET_MODE_WIDER_MODE (mode)) 536 if (HARD_REGNO_NREGS (regno, mode) == nregs 537 && HARD_REGNO_MODE_OK (regno, mode)) 538 found_mode = mode; 539 540 if (found_mode != VOIDmode) 541 return found_mode; 542 543 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); 544 mode != VOIDmode; 545 mode = GET_MODE_WIDER_MODE (mode)) 546 if (HARD_REGNO_NREGS (regno, mode) == nregs 547 && HARD_REGNO_MODE_OK (regno, mode)) 548 found_mode = mode; 549 550 if (found_mode != VOIDmode) 551 return found_mode; 552 553 if (HARD_REGNO_NREGS (regno, CCmode) == nregs 554 && HARD_REGNO_MODE_OK (regno, CCmode)) 555 return CCmode; 556 557 /* We can't find a mode valid for this register. */ 558 return VOIDmode; 559} 560 561/* Specify the usage characteristics of the register named NAME. 562 It should be a fixed register if FIXED and a 563 call-used register if CALL_USED. */ 564 565void 566fix_register (name, fixed, call_used) 567 char *name; 568 int fixed, call_used; 569{ 570 int i; 571 572 /* Decode the name and update the primary form of 573 the register info. */ 574 575 if ((i = decode_reg_name (name)) >= 0) 576 { 577 fixed_regs[i] = fixed; 578 call_used_regs[i] = call_used; 579 } 580 else 581 { 582 warning ("unknown register name: %s", name); 583 } 584} 585 586/* Mark register number I as global. */ 587 588void 589globalize_reg (i) 590 int i; 591{ 592 if (global_regs[i]) 593 { 594 warning ("register used for two global register variables"); 595 return; 596 } 597 598 if (call_used_regs[i] && ! fixed_regs[i]) 599 warning ("call-clobbered register used for global register variable"); 600 601 global_regs[i] = 1; 602 603 /* If already fixed, nothing else to do. */ 604 if (fixed_regs[i]) 605 return; 606 607 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; 608 n_non_fixed_regs--; 609 610 SET_HARD_REG_BIT (fixed_reg_set, i); 611 SET_HARD_REG_BIT (call_used_reg_set, i); 612 SET_HARD_REG_BIT (call_fixed_reg_set, i); 613} 614 615/* Now the data and code for the `regclass' pass, which happens 616 just before local-alloc. */ 617 618/* The `costs' struct records the cost of using a hard register of each class 619 and of using memory for each pseudo. We use this data to set up 620 register class preferences. */ 621 622struct costs 623{ 624 int cost[N_REG_CLASSES]; 625 int mem_cost; 626}; 627 628/* Record the cost of each class for each pseudo. */ 629 630static struct costs *costs; 631 632/* Record the same data by operand number, accumulated for each alternative 633 in an insn. The contribution to a pseudo is that of the minimum-cost 634 alternative. */ 635 636static struct costs op_costs[MAX_RECOG_OPERANDS]; 637 638/* (enum reg_class) prefclass[R] is the preferred class for pseudo number R. 639 This is available after `regclass' is run. */ 640 641static char *prefclass; 642 643/* altclass[R] is a register class that we should use for allocating 644 pseudo number R if no register in the preferred class is available. 645 If no register in this class is available, memory is preferred. 646 647 It might appear to be more general to have a bitmask of classes here, 648 but since it is recommended that there be a class corresponding to the 649 union of most major pair of classes, that generality is not required. 650 651 This is available after `regclass' is run. */ 652 653static char *altclass; 654 655/* Allocated buffers for prefclass and altclass. */ 656static char *prefclass_buffer; 657static char *altclass_buffer; 658 659/* Record the depth of loops that we are in. */ 660 661static int loop_depth; 662 663/* Account for the fact that insns within a loop are executed very commonly, 664 but don't keep doing this as loops go too deep. */ 665 666static int loop_cost; 667 668static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *, 669 char **, rtx)); 670static int copy_cost PROTO((rtx, enum machine_mode, 671 enum reg_class, int)); 672static void record_address_regs PROTO((rtx, enum reg_class, int)); 673#ifdef FORBIDDEN_INC_DEC_CLASSES 674static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode)); 675#endif 676static void reg_scan_mark_refs PROTO((rtx, rtx, int, int)); 677 678/* Return the reg_class in which pseudo reg number REGNO is best allocated. 679 This function is sometimes called before the info has been computed. 680 When that happens, just return GENERAL_REGS, which is innocuous. */ 681 682enum reg_class 683reg_preferred_class (regno) 684 int regno; 685{ 686 if (prefclass == 0) 687 return GENERAL_REGS; 688 return (enum reg_class) prefclass[regno]; 689} 690 691enum reg_class 692reg_alternate_class (regno) 693 int regno; 694{ 695 if (prefclass == 0) 696 return ALL_REGS; 697 698 return (enum reg_class) altclass[regno]; 699} 700 701/* This prevents dump_flow_info from losing if called 702 before regclass is run. */ 703 704void 705regclass_init () 706{ 707 prefclass = 0; 708} 709 710/* This is a pass of the compiler that scans all instructions 711 and calculates the preferred class for each pseudo-register. 712 This information can be accessed later by calling `reg_preferred_class'. 713 This pass comes just before local register allocation. */ 714 715void 716regclass (f, nregs) 717 rtx f; 718 int nregs; 719{ 720#ifdef REGISTER_CONSTRAINTS 721 register rtx insn; 722 register int i, j; 723 struct costs init_cost; 724 rtx set; 725 int pass; 726 727 init_recog (); 728 729 costs = (struct costs *) alloca (nregs * sizeof (struct costs)); 730 731#ifdef FORBIDDEN_INC_DEC_CLASSES 732 733 in_inc_dec = (char *) alloca (nregs); 734 735 /* Initialize information about which register classes can be used for 736 pseudos that are auto-incremented or auto-decremented. It would 737 seem better to put this in init_reg_sets, but we need to be able 738 to allocate rtx, which we can't do that early. */ 739 740 for (i = 0; i < N_REG_CLASSES; i++) 741 { 742 rtx r = gen_rtx_REG (VOIDmode, 0); 743 enum machine_mode m; 744 745 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 746 if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 747 { 748 REGNO (r) = j; 749 750 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; 751 m = (enum machine_mode) ((int) m + 1)) 752 if (HARD_REGNO_MODE_OK (j, m)) 753 { 754 PUT_MODE (r, m); 755 756 /* If a register is not directly suitable for an 757 auto-increment or decrement addressing mode and 758 requires secondary reloads, disallow its class from 759 being used in such addresses. */ 760 761 if ((0 762#ifdef SECONDARY_RELOAD_CLASS 763 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r) 764 != NO_REGS) 765#else 766#ifdef SECONDARY_INPUT_RELOAD_CLASS 767 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) 768 != NO_REGS) 769#endif 770#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 771 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) 772 != NO_REGS) 773#endif 774#endif 775 ) 776 && ! auto_inc_dec_reg_p (r, m)) 777 forbidden_inc_dec_class[i] = 1; 778 } 779 } 780 } 781#endif /* FORBIDDEN_INC_DEC_CLASSES */ 782 783 init_cost.mem_cost = 10000; 784 for (i = 0; i < N_REG_CLASSES; i++) 785 init_cost.cost[i] = 10000; 786 787 /* Normally we scan the insns once and determine the best class to use for 788 each register. However, if -fexpensive_optimizations are on, we do so 789 twice, the second time using the tentative best classes to guide the 790 selection. */ 791 792 for (pass = 0; pass <= flag_expensive_optimizations; pass++) 793 { 794 /* Zero out our accumulation of the cost of each class for each reg. */ 795 796 bzero ((char *) costs, nregs * sizeof (struct costs)); 797 798#ifdef FORBIDDEN_INC_DEC_CLASSES 799 bzero (in_inc_dec, nregs); 800#endif 801 802 loop_depth = 0, loop_cost = 1; 803 804 /* Scan the instructions and record each time it would 805 save code to put a certain register in a certain class. */ 806 807 for (insn = f; insn; insn = NEXT_INSN (insn)) 808 { 809 char *constraints[MAX_RECOG_OPERANDS]; 810 enum machine_mode modes[MAX_RECOG_OPERANDS]; 811 int nalternatives; 812 int noperands; 813 814 /* Show that an insn inside a loop is likely to be executed three 815 times more than insns outside a loop. This is much more aggressive 816 than the assumptions made elsewhere and is being tried as an 817 experiment. */ 818 819 if (GET_CODE (insn) == NOTE 820 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) 821 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5)); 822 else if (GET_CODE (insn) == NOTE 823 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) 824 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5)); 825 826 else if ((GET_CODE (insn) == INSN 827 && GET_CODE (PATTERN (insn)) != USE 828 && GET_CODE (PATTERN (insn)) != CLOBBER 829 && GET_CODE (PATTERN (insn)) != ASM_INPUT) 830 || (GET_CODE (insn) == JUMP_INSN 831 && GET_CODE (PATTERN (insn)) != ADDR_VEC 832 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) 833 || GET_CODE (insn) == CALL_INSN) 834 { 835 if (GET_CODE (insn) == INSN 836 && (noperands = asm_noperands (PATTERN (insn))) >= 0) 837 { 838 decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR, 839 constraints, modes); 840 nalternatives = (noperands == 0 ? 0 841 : n_occurrences (',', constraints[0]) + 1); 842 } 843 else 844 { 845 int insn_code_number = recog_memoized (insn); 846 rtx note; 847 848 set = single_set (insn); 849 insn_extract (insn); 850 851 nalternatives = insn_n_alternatives[insn_code_number]; 852 noperands = insn_n_operands[insn_code_number]; 853 854 /* If this insn loads a parameter from its stack slot, then 855 it represents a savings, rather than a cost, if the 856 parameter is stored in memory. Record this fact. */ 857 858 if (set != 0 && GET_CODE (SET_DEST (set)) == REG 859 && GET_CODE (SET_SRC (set)) == MEM 860 && (note = find_reg_note (insn, REG_EQUIV, 861 NULL_RTX)) != 0 862 && GET_CODE (XEXP (note, 0)) == MEM) 863 { 864 costs[REGNO (SET_DEST (set))].mem_cost 865 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), 866 GENERAL_REGS, 1) 867 * loop_cost); 868 record_address_regs (XEXP (SET_SRC (set), 0), 869 BASE_REG_CLASS, loop_cost * 2); 870 continue; 871 } 872 873 /* Improve handling of two-address insns such as 874 (set X (ashift CONST Y)) where CONST must be made to 875 match X. Change it into two insns: (set X CONST) 876 (set X (ashift X Y)). If we left this for reloading, it 877 would probably get three insns because X and Y might go 878 in the same place. This prevents X and Y from receiving 879 the same hard reg. 880 881 We can only do this if the modes of operands 0 and 1 882 (which might not be the same) are tieable and we only need 883 do this during our first pass. */ 884 885 if (pass == 0 && optimize 886 && noperands >= 3 887 && insn_operand_constraint[insn_code_number][1][0] == '0' 888 && insn_operand_constraint[insn_code_number][1][1] == 0 889 && CONSTANT_P (recog_operand[1]) 890 && ! rtx_equal_p (recog_operand[0], recog_operand[1]) 891 && ! rtx_equal_p (recog_operand[0], recog_operand[2]) 892 && GET_CODE (recog_operand[0]) == REG 893 && MODES_TIEABLE_P (GET_MODE (recog_operand[0]), 894 insn_operand_mode[insn_code_number][1])) 895 { 896 rtx previnsn = prev_real_insn (insn); 897 rtx dest 898 = gen_lowpart (insn_operand_mode[insn_code_number][1], 899 recog_operand[0]); 900 rtx newinsn 901 = emit_insn_before (gen_move_insn (dest, 902 recog_operand[1]), 903 insn); 904 905 /* If this insn was the start of a basic block, 906 include the new insn in that block. 907 We need not check for code_label here; 908 while a basic block can start with a code_label, 909 INSN could not be at the beginning of that block. */ 910 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) 911 { 912 int b; 913 for (b = 0; b < n_basic_blocks; b++) 914 if (insn == basic_block_head[b]) 915 basic_block_head[b] = newinsn; 916 } 917 918 /* This makes one more setting of new insns's dest. */ 919 REG_N_SETS (REGNO (recog_operand[0]))++; 920 921 *recog_operand_loc[1] = recog_operand[0]; 922 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) 923 if (recog_dup_num[i] == 1) 924 *recog_dup_loc[i] = recog_operand[0]; 925 926 insn = PREV_INSN (newinsn); 927 continue; 928 } 929 930 for (i = 0; i < noperands; i++) 931 { 932 constraints[i] 933 = insn_operand_constraint[insn_code_number][i]; 934 modes[i] = insn_operand_mode[insn_code_number][i]; 935 } 936 } 937 938 /* If we get here, we are set up to record the costs of all the 939 operands for this insn. Start by initializing the costs. 940 Then handle any address registers. Finally record the desired 941 classes for any pseudos, doing it twice if some pair of 942 operands are commutative. */ 943 944 for (i = 0; i < noperands; i++) 945 { 946 op_costs[i] = init_cost; 947 948 if (GET_CODE (recog_operand[i]) == SUBREG) 949 recog_operand[i] = SUBREG_REG (recog_operand[i]); 950 951 if (GET_CODE (recog_operand[i]) == MEM) 952 record_address_regs (XEXP (recog_operand[i], 0), 953 BASE_REG_CLASS, loop_cost * 2); 954 else if (constraints[i][0] == 'p') 955 record_address_regs (recog_operand[i], 956 BASE_REG_CLASS, loop_cost * 2); 957 } 958 959 /* Check for commutative in a separate loop so everything will 960 have been initialized. We must do this even if one operand 961 is a constant--see addsi3 in m68k.md. */ 962 963 for (i = 0; i < noperands - 1; i++) 964 if (constraints[i][0] == '%') 965 { 966 char *xconstraints[MAX_RECOG_OPERANDS]; 967 int j; 968 969 /* Handle commutative operands by swapping the constraints. 970 We assume the modes are the same. */ 971 972 for (j = 0; j < noperands; j++) 973 xconstraints[j] = constraints[j]; 974 975 xconstraints[i] = constraints[i+1]; 976 xconstraints[i+1] = constraints[i]; 977 record_reg_classes (nalternatives, noperands, 978 recog_operand, modes, xconstraints, 979 insn); 980 } 981 982 record_reg_classes (nalternatives, noperands, recog_operand, 983 modes, constraints, insn); 984 985 /* Now add the cost for each operand to the total costs for 986 its register. */ 987 988 for (i = 0; i < noperands; i++) 989 if (GET_CODE (recog_operand[i]) == REG 990 && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) 991 { 992 int regno = REGNO (recog_operand[i]); 993 struct costs *p = &costs[regno], *q = &op_costs[i]; 994 995 p->mem_cost += q->mem_cost * loop_cost; 996 for (j = 0; j < N_REG_CLASSES; j++) 997 p->cost[j] += q->cost[j] * loop_cost; 998 } 999 } 1000 } 1001 1002 /* Now for each register look at how desirable each class is 1003 and find which class is preferred. Store that in 1004 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register 1005 class any of whose registers is better than memory. */ 1006 1007 if (pass == 0) 1008 { 1009 prefclass = prefclass_buffer; 1010 altclass = altclass_buffer; 1011 } 1012 1013 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) 1014 { 1015 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; 1016 enum reg_class best = ALL_REGS, alt = NO_REGS; 1017 /* This is an enum reg_class, but we call it an int 1018 to save lots of casts. */ 1019 register int class; 1020 register struct costs *p = &costs[i]; 1021 1022 for (class = (int) ALL_REGS - 1; class > 0; class--) 1023 { 1024 /* Ignore classes that are too small for this operand or 1025 invalid for a operand that was auto-incremented. */ 1026 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) 1027 > reg_class_size[class] 1028#ifdef FORBIDDEN_INC_DEC_CLASSES 1029 || (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1030#endif 1031 ) 1032 ; 1033 else if (p->cost[class] < best_cost) 1034 { 1035 best_cost = p->cost[class]; 1036 best = (enum reg_class) class; 1037 } 1038 else if (p->cost[class] == best_cost) 1039 best = reg_class_subunion[(int)best][class]; 1040 } 1041 1042 /* Record the alternate register class; i.e., a class for which 1043 every register in it is better than using memory. If adding a 1044 class would make a smaller class (i.e., no union of just those 1045 classes exists), skip that class. The major unions of classes 1046 should be provided as a register class. Don't do this if we 1047 will be doing it again later. */ 1048 1049 if (pass == 1 || ! flag_expensive_optimizations) 1050 for (class = 0; class < N_REG_CLASSES; class++) 1051 if (p->cost[class] < p->mem_cost 1052 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] 1053 > reg_class_size[(int) alt]) 1054#ifdef FORBIDDEN_INC_DEC_CLASSES 1055 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1056#endif 1057 ) 1058 alt = reg_class_subunion[(int) alt][class]; 1059 1060 /* If we don't add any classes, nothing to try. */ 1061 if (alt == best) 1062 alt = NO_REGS; 1063 1064 /* We cast to (int) because (char) hits bugs in some compilers. */ 1065 prefclass[i] = (int) best; 1066 altclass[i] = (int) alt; 1067 } 1068 } 1069#endif /* REGISTER_CONSTRAINTS */ 1070} 1071 1072#ifdef REGISTER_CONSTRAINTS 1073 1074/* Record the cost of using memory or registers of various classes for 1075 the operands in INSN. 1076 1077 N_ALTS is the number of alternatives. 1078 1079 N_OPS is the number of operands. 1080 1081 OPS is an array of the operands. 1082 1083 MODES are the modes of the operands, in case any are VOIDmode. 1084 1085 CONSTRAINTS are the constraints to use for the operands. This array 1086 is modified by this procedure. 1087 1088 This procedure works alternative by alternative. For each alternative 1089 we assume that we will be able to allocate all pseudos to their ideal 1090 register class and calculate the cost of using that alternative. Then 1091 we compute for each operand that is a pseudo-register, the cost of 1092 having the pseudo allocated to each register class and using it in that 1093 alternative. To this cost is added the cost of the alternative. 1094 1095 The cost of each class for this insn is its lowest cost among all the 1096 alternatives. */ 1097 1098static void 1099record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn) 1100 int n_alts; 1101 int n_ops; 1102 rtx *ops; 1103 enum machine_mode *modes; 1104 char **constraints; 1105 rtx insn; 1106{ 1107 int alt; 1108 enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS]; 1109 int i, j; 1110 rtx set; 1111 1112 /* By default, each operand is an input operand. */ 1113 1114 for (i = 0; i < n_ops; i++) 1115 op_types[i] = OP_READ; 1116 1117 /* Process each alternative, each time minimizing an operand's cost with 1118 the cost for each operand in that alternative. */ 1119 1120 for (alt = 0; alt < n_alts; alt++) 1121 { 1122 struct costs this_op_costs[MAX_RECOG_OPERANDS]; 1123 int alt_fail = 0; 1124 int alt_cost = 0; 1125 enum reg_class classes[MAX_RECOG_OPERANDS]; 1126 int class; 1127 1128 for (i = 0; i < n_ops; i++) 1129 { 1130 char *p = constraints[i]; 1131 rtx op = ops[i]; 1132 enum machine_mode mode = modes[i]; 1133 int allows_mem = 0; 1134 int win = 0; 1135 char c; 1136 1137 /* If this operand has no constraints at all, we can conclude 1138 nothing about it since anything is valid. */ 1139 1140 if (*p == 0) 1141 { 1142 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1143 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]); 1144 1145 continue; 1146 } 1147 1148 if (*p == '%') 1149 p++; 1150 1151 /* If this alternative is only relevant when this operand 1152 matches a previous operand, we do different things depending 1153 on whether this operand is a pseudo-reg or not. */ 1154 1155 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) 1156 { 1157 j = p[0] - '0'; 1158 classes[i] = classes[j]; 1159 1160 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) 1161 { 1162 /* If this matches the other operand, we have no added 1163 cost and we win. */ 1164 if (rtx_equal_p (ops[j], op)) 1165 win = 1; 1166 1167 /* If we can put the other operand into a register, add to 1168 the cost of this alternative the cost to copy this 1169 operand to the register used for the other operand. */ 1170 1171 else if (classes[j] != NO_REGS) 1172 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; 1173 } 1174 else if (GET_CODE (ops[j]) != REG 1175 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) 1176 { 1177 /* This op is a pseudo but the one it matches is not. */ 1178 1179 /* If we can't put the other operand into a register, this 1180 alternative can't be used. */ 1181 1182 if (classes[j] == NO_REGS) 1183 alt_fail = 1; 1184 1185 /* Otherwise, add to the cost of this alternative the cost 1186 to copy the other operand to the register used for this 1187 operand. */ 1188 1189 else 1190 alt_cost += copy_cost (ops[j], mode, classes[j], 1); 1191 } 1192 else 1193 { 1194 /* The costs of this operand are the same as that of the 1195 other operand. However, if we cannot tie them, this 1196 alternative needs to do a copy, which is one 1197 instruction. */ 1198 1199 this_op_costs[i] = this_op_costs[j]; 1200 if (REGNO (ops[i]) != REGNO (ops[j]) 1201 && ! find_reg_note (insn, REG_DEAD, op)) 1202 alt_cost += 2; 1203 1204 /* This is in place of ordinary cost computation 1205 for this operand, so skip to the end of the 1206 alternative (should be just one character). */ 1207 while (*p && *p++ != ',') 1208 ; 1209 1210 constraints[i] = p; 1211 continue; 1212 } 1213 } 1214 1215 /* Scan all the constraint letters. See if the operand matches 1216 any of the constraints. Collect the valid register classes 1217 and see if this operand accepts memory. */ 1218 1219 classes[i] = NO_REGS; 1220 while (*p && (c = *p++) != ',') 1221 switch (c) 1222 { 1223 case '=': 1224 op_types[i] = OP_WRITE; 1225 break; 1226 1227 case '+': 1228 op_types[i] = OP_READ_WRITE; 1229 break; 1230 1231 case '*': 1232 /* Ignore the next letter for this pass. */ 1233 p++; 1234 break; 1235 1236 case '?': 1237 alt_cost += 2; 1238 case '%': 1239 case '!': case '#': 1240 case '&': 1241 case '0': case '1': case '2': case '3': case '4': 1242 case 'p': 1243 break; 1244 1245 case 'm': case 'o': case 'V': 1246 /* It doesn't seem worth distinguishing between offsettable 1247 and non-offsettable addresses here. */ 1248 allows_mem = 1; 1249 if (GET_CODE (op) == MEM) 1250 win = 1; 1251 break; 1252 1253 case '<': 1254 if (GET_CODE (op) == MEM 1255 && (GET_CODE (XEXP (op, 0)) == PRE_DEC 1256 || GET_CODE (XEXP (op, 0)) == POST_DEC)) 1257 win = 1; 1258 break; 1259 1260 case '>': 1261 if (GET_CODE (op) == MEM 1262 && (GET_CODE (XEXP (op, 0)) == PRE_INC 1263 || GET_CODE (XEXP (op, 0)) == POST_INC)) 1264 win = 1; 1265 break; 1266 1267 case 'E': 1268#ifndef REAL_ARITHMETIC 1269 /* Match any floating double constant, but only if 1270 we can examine the bits of it reliably. */ 1271 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT 1272 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) 1273 && GET_MODE (op) != VOIDmode && ! flag_pretend_float) 1274 break; 1275#endif 1276 if (GET_CODE (op) == CONST_DOUBLE) 1277 win = 1; 1278 break; 1279 1280 case 'F': 1281 if (GET_CODE (op) == CONST_DOUBLE) 1282 win = 1; 1283 break; 1284 1285 case 'G': 1286 case 'H': 1287 if (GET_CODE (op) == CONST_DOUBLE 1288 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) 1289 win = 1; 1290 break; 1291 1292 case 's': 1293 if (GET_CODE (op) == CONST_INT 1294 || (GET_CODE (op) == CONST_DOUBLE 1295 && GET_MODE (op) == VOIDmode)) 1296 break; 1297 case 'i': 1298 if (CONSTANT_P (op) 1299#ifdef LEGITIMATE_PIC_OPERAND_P 1300 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1301#endif 1302 ) 1303 win = 1; 1304 break; 1305 1306 case 'n': 1307 if (GET_CODE (op) == CONST_INT 1308 || (GET_CODE (op) == CONST_DOUBLE 1309 && GET_MODE (op) == VOIDmode)) 1310 win = 1; 1311 break; 1312 1313 case 'I': 1314 case 'J': 1315 case 'K': 1316 case 'L': 1317 case 'M': 1318 case 'N': 1319 case 'O': 1320 case 'P': 1321 if (GET_CODE (op) == CONST_INT 1322 && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) 1323 win = 1; 1324 break; 1325 1326 case 'X': 1327 win = 1; 1328 break; 1329 1330#ifdef EXTRA_CONSTRAINT 1331 case 'Q': 1332 case 'R': 1333 case 'S': 1334 case 'T': 1335 case 'U': 1336 if (EXTRA_CONSTRAINT (op, c)) 1337 win = 1; 1338 break; 1339#endif 1340 1341 case 'g': 1342 if (GET_CODE (op) == MEM 1343 || (CONSTANT_P (op) 1344#ifdef LEGITIMATE_PIC_OPERAND_P 1345 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1346#endif 1347 )) 1348 win = 1; 1349 allows_mem = 1; 1350 case 'r': 1351 classes[i] 1352 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; 1353 break; 1354 1355 default: 1356 classes[i] 1357 = reg_class_subunion[(int) classes[i]] 1358 [(int) REG_CLASS_FROM_LETTER (c)]; 1359 } 1360 1361 constraints[i] = p; 1362 1363 /* How we account for this operand now depends on whether it is a 1364 pseudo register or not. If it is, we first check if any 1365 register classes are valid. If not, we ignore this alternative, 1366 since we want to assume that all pseudos get allocated for 1367 register preferencing. If some register class is valid, compute 1368 the costs of moving the pseudo into that class. */ 1369 1370 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1371 { 1372 if (classes[i] == NO_REGS) 1373 alt_fail = 1; 1374 else 1375 { 1376 struct costs *pp = &this_op_costs[i]; 1377 1378 for (class = 0; class < N_REG_CLASSES; class++) 1379 pp->cost[class] = may_move_cost[class][(int) classes[i]]; 1380 1381 /* If the alternative actually allows memory, make things 1382 a bit cheaper since we won't need an extra insn to 1383 load it. */ 1384 1385 pp->mem_cost = (MEMORY_MOVE_COST (mode, classes[i], 1) 1386 - allows_mem); 1387 1388 /* If we have assigned a class to this register in our 1389 first pass, add a cost to this alternative corresponding 1390 to what we would add if this register were not in the 1391 appropriate class. */ 1392 1393 if (prefclass) 1394 alt_cost 1395 += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]]; 1396 } 1397 } 1398 1399 /* Otherwise, if this alternative wins, either because we 1400 have already determined that or if we have a hard register of 1401 the proper class, there is no cost for this alternative. */ 1402 1403 else if (win 1404 || (GET_CODE (op) == REG 1405 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) 1406 ; 1407 1408 /* If registers are valid, the cost of this alternative includes 1409 copying the object to and/or from a register. */ 1410 1411 else if (classes[i] != NO_REGS) 1412 { 1413 if (op_types[i] != OP_WRITE) 1414 alt_cost += copy_cost (op, mode, classes[i], 1); 1415 1416 if (op_types[i] != OP_READ) 1417 alt_cost += copy_cost (op, mode, classes[i], 0); 1418 } 1419 1420 /* The only other way this alternative can be used is if this is a 1421 constant that could be placed into memory. */ 1422 1423 else if (CONSTANT_P (op) && allows_mem) 1424 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); 1425 else 1426 alt_fail = 1; 1427 } 1428 1429 if (alt_fail) 1430 continue; 1431 1432 /* Finally, update the costs with the information we've calculated 1433 about this alternative. */ 1434 1435 for (i = 0; i < n_ops; i++) 1436 if (GET_CODE (ops[i]) == REG 1437 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1438 { 1439 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; 1440 int scale = 1 + (op_types[i] == OP_READ_WRITE); 1441 1442 pp->mem_cost = MIN (pp->mem_cost, 1443 (qq->mem_cost + alt_cost) * scale); 1444 1445 for (class = 0; class < N_REG_CLASSES; class++) 1446 pp->cost[class] = MIN (pp->cost[class], 1447 (qq->cost[class] + alt_cost) * scale); 1448 } 1449 } 1450 1451 /* If this insn is a single set copying operand 1 to operand 0 1452 and one is a pseudo with the other a hard reg that is in its 1453 own register class, set the cost of that register class to -1. */ 1454 1455 if ((set = single_set (insn)) != 0 1456 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) 1457 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG) 1458 for (i = 0; i <= 1; i++) 1459 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1460 { 1461 int regno = REGNO (ops[!i]); 1462 enum machine_mode mode = GET_MODE (ops[!i]); 1463 int class; 1464 int nr; 1465 1466 if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0 1467 && (reg_class_size[prefclass[regno]] 1468 == CLASS_MAX_NREGS (prefclass[regno], mode))) 1469 op_costs[i].cost[prefclass[regno]] = -1; 1470 else if (regno < FIRST_PSEUDO_REGISTER) 1471 for (class = 0; class < N_REG_CLASSES; class++) 1472 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) 1473 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) 1474 { 1475 if (reg_class_size[class] == 1) 1476 op_costs[i].cost[class] = -1; 1477 else 1478 { 1479 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++) 1480 { 1481 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr)) 1482 break; 1483 } 1484 1485 if (nr == HARD_REGNO_NREGS(regno,mode)) 1486 op_costs[i].cost[class] = -1; 1487 } 1488 } 1489 } 1490} 1491 1492/* Compute the cost of loading X into (if TO_P is non-zero) or from (if 1493 TO_P is zero) a register of class CLASS in mode MODE. 1494 1495 X must not be a pseudo. */ 1496 1497static int 1498copy_cost (x, mode, class, to_p) 1499 rtx x; 1500 enum machine_mode mode; 1501 enum reg_class class; 1502 int to_p; 1503{ 1504#ifdef HAVE_SECONDARY_RELOADS 1505 enum reg_class secondary_class = NO_REGS; 1506#endif 1507 1508 /* If X is a SCRATCH, there is actually nothing to move since we are 1509 assuming optimal allocation. */ 1510 1511 if (GET_CODE (x) == SCRATCH) 1512 return 0; 1513 1514 /* Get the class we will actually use for a reload. */ 1515 class = PREFERRED_RELOAD_CLASS (x, class); 1516 1517#ifdef HAVE_SECONDARY_RELOADS 1518 /* If we need a secondary reload (we assume here that we are using 1519 the secondary reload as an intermediate, not a scratch register), the 1520 cost is that to load the input into the intermediate register, then 1521 to copy them. We use a special value of TO_P to avoid recursion. */ 1522 1523#ifdef SECONDARY_INPUT_RELOAD_CLASS 1524 if (to_p == 1) 1525 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); 1526#endif 1527 1528#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1529 if (! to_p) 1530 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); 1531#endif 1532 1533 if (secondary_class != NO_REGS) 1534 return (move_cost[(int) secondary_class][(int) class] 1535 + copy_cost (x, mode, secondary_class, 2)); 1536#endif /* HAVE_SECONDARY_RELOADS */ 1537 1538 /* For memory, use the memory move cost, for (hard) registers, use the 1539 cost to move between the register classes, and use 2 for everything 1540 else (constants). */ 1541 1542 if (GET_CODE (x) == MEM || class == NO_REGS) 1543 return MEMORY_MOVE_COST (mode, class, to_p); 1544 1545 else if (GET_CODE (x) == REG) 1546 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; 1547 1548 else 1549 /* If this is a constant, we may eventually want to call rtx_cost here. */ 1550 return 2; 1551} 1552 1553/* Record the pseudo registers we must reload into hard registers 1554 in a subexpression of a memory address, X. 1555 1556 CLASS is the class that the register needs to be in and is either 1557 BASE_REG_CLASS or INDEX_REG_CLASS. 1558 1559 SCALE is twice the amount to multiply the cost by (it is twice so we 1560 can represent half-cost adjustments). */ 1561 1562static void 1563record_address_regs (x, class, scale) 1564 rtx x; 1565 enum reg_class class; 1566 int scale; 1567{ 1568 register enum rtx_code code = GET_CODE (x); 1569 1570 switch (code) 1571 { 1572 case CONST_INT: 1573 case CONST: 1574 case CC0: 1575 case PC: 1576 case SYMBOL_REF: 1577 case LABEL_REF: 1578 return; 1579 1580 case PLUS: 1581 /* When we have an address that is a sum, 1582 we must determine whether registers are "base" or "index" regs. 1583 If there is a sum of two registers, we must choose one to be 1584 the "base". Luckily, we can use the REGNO_POINTER_FLAG 1585 to make a good choice most of the time. We only need to do this 1586 on machines that can have two registers in an address and where 1587 the base and index register classes are different. 1588 1589 ??? This code used to set REGNO_POINTER_FLAG in some cases, but 1590 that seems bogus since it should only be set when we are sure 1591 the register is being used as a pointer. */ 1592 1593 { 1594 rtx arg0 = XEXP (x, 0); 1595 rtx arg1 = XEXP (x, 1); 1596 register enum rtx_code code0 = GET_CODE (arg0); 1597 register enum rtx_code code1 = GET_CODE (arg1); 1598 1599 /* Look inside subregs. */ 1600 if (code0 == SUBREG) 1601 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); 1602 if (code1 == SUBREG) 1603 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); 1604 1605 /* If this machine only allows one register per address, it must 1606 be in the first operand. */ 1607 1608 if (MAX_REGS_PER_ADDRESS == 1) 1609 record_address_regs (arg0, class, scale); 1610 1611 /* If index and base registers are the same on this machine, just 1612 record registers in any non-constant operands. We assume here, 1613 as well as in the tests below, that all addresses are in 1614 canonical form. */ 1615 1616 else if (INDEX_REG_CLASS == BASE_REG_CLASS) 1617 { 1618 record_address_regs (arg0, class, scale); 1619 if (! CONSTANT_P (arg1)) 1620 record_address_regs (arg1, class, scale); 1621 } 1622 1623 /* If the second operand is a constant integer, it doesn't change 1624 what class the first operand must be. */ 1625 1626 else if (code1 == CONST_INT || code1 == CONST_DOUBLE) 1627 record_address_regs (arg0, class, scale); 1628 1629 /* If the second operand is a symbolic constant, the first operand 1630 must be an index register. */ 1631 1632 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) 1633 record_address_regs (arg0, INDEX_REG_CLASS, scale); 1634 1635 /* If both operands are registers but one is already a hard register 1636 of index or base class, give the other the class that the hard 1637 register is not. */ 1638 1639#ifdef REG_OK_FOR_BASE_P 1640 else if (code0 == REG && code1 == REG 1641 && REGNO (arg0) < FIRST_PSEUDO_REGISTER 1642 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) 1643 record_address_regs (arg1, 1644 REG_OK_FOR_BASE_P (arg0) 1645 ? INDEX_REG_CLASS : BASE_REG_CLASS, 1646 scale); 1647 else if (code0 == REG && code1 == REG 1648 && REGNO (arg1) < FIRST_PSEUDO_REGISTER 1649 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) 1650 record_address_regs (arg0, 1651 REG_OK_FOR_BASE_P (arg1) 1652 ? INDEX_REG_CLASS : BASE_REG_CLASS, 1653 scale); 1654#endif 1655 1656 /* If one operand is known to be a pointer, it must be the base 1657 with the other operand the index. Likewise if the other operand 1658 is a MULT. */ 1659 1660 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0))) 1661 || code1 == MULT) 1662 { 1663 record_address_regs (arg0, BASE_REG_CLASS, scale); 1664 record_address_regs (arg1, INDEX_REG_CLASS, scale); 1665 } 1666 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1))) 1667 || code0 == MULT) 1668 { 1669 record_address_regs (arg0, INDEX_REG_CLASS, scale); 1670 record_address_regs (arg1, BASE_REG_CLASS, scale); 1671 } 1672 1673 /* Otherwise, count equal chances that each might be a base 1674 or index register. This case should be rare. */ 1675 1676 else 1677 { 1678 record_address_regs (arg0, BASE_REG_CLASS, scale / 2); 1679 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); 1680 record_address_regs (arg1, BASE_REG_CLASS, scale / 2); 1681 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); 1682 } 1683 } 1684 break; 1685 1686 case POST_INC: 1687 case PRE_INC: 1688 case POST_DEC: 1689 case PRE_DEC: 1690 /* Double the importance of a pseudo register that is incremented 1691 or decremented, since it would take two extra insns 1692 if it ends up in the wrong place. If the operand is a pseudo, 1693 show it is being used in an INC_DEC context. */ 1694 1695#ifdef FORBIDDEN_INC_DEC_CLASSES 1696 if (GET_CODE (XEXP (x, 0)) == REG 1697 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) 1698 in_inc_dec[REGNO (XEXP (x, 0))] = 1; 1699#endif 1700 1701 record_address_regs (XEXP (x, 0), class, 2 * scale); 1702 break; 1703 1704 case REG: 1705 { 1706 register struct costs *pp = &costs[REGNO (x)]; 1707 register int i; 1708 1709 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; 1710 1711 for (i = 0; i < N_REG_CLASSES; i++) 1712 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2; 1713 } 1714 break; 1715 1716 default: 1717 { 1718 register char *fmt = GET_RTX_FORMAT (code); 1719 register int i; 1720 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1721 if (fmt[i] == 'e') 1722 record_address_regs (XEXP (x, i), class, scale); 1723 } 1724 } 1725} 1726 1727#ifdef FORBIDDEN_INC_DEC_CLASSES 1728 1729/* Return 1 if REG is valid as an auto-increment memory reference 1730 to an object of MODE. */ 1731 1732static int 1733auto_inc_dec_reg_p (reg, mode) 1734 rtx reg; 1735 enum machine_mode mode; 1736{ 1737#ifdef HAVE_POST_INCREMENT 1738 if (memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) 1739 return 1; 1740#endif 1741 1742#ifdef HAVE_POST_DECREMENT 1743 if (memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) 1744 return 1; 1745#endif 1746 1747#ifdef HAVE_PRE_INCREMENT 1748 if (memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) 1749 return 1; 1750#endif 1751 1752#ifdef HAVE_PRE_DECREMENT 1753 if (memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) 1754 return 1; 1755#endif 1756 1757 return 0; 1758} 1759#endif 1760 1761#endif /* REGISTER_CONSTRAINTS */ 1762 1763/* Allocate enough space to hold NUM_REGS registers for the tables used for 1764 reg_scan and flow_analysis that are indexed by the register number. If 1765 NEW_P is non zero, initialize all of the registers, otherwise only 1766 initialize the new registers allocated. The same table is kept from 1767 function to function, only reallocating it when we need more room. If 1768 RENUMBER_P is non zero, allocate the reg_renumber array also. */ 1769 1770void 1771allocate_reg_info (num_regs, new_p, renumber_p) 1772 size_t num_regs; 1773 int new_p; 1774 int renumber_p; 1775{ 1776 static size_t regno_allocated = 0; 1777 static short *renumber = (short *)0; 1778 int i; 1779 size_t size_info; 1780 size_t size_renumber; 1781 size_t min = (new_p) ? 0 : reg_n_max; 1782 struct reg_info_data *reg_data; 1783 struct reg_info_data *reg_next; 1784 1785 /* Free up all storage allocated */ 1786 if (num_regs < 0) 1787 { 1788 if (reg_n_info) 1789 { 1790 VARRAY_FREE (reg_n_info); 1791 for (reg_data = reg_info_head; reg_data; reg_data = reg_next) 1792 { 1793 reg_next = reg_data->next; 1794 free ((char *)reg_data); 1795 } 1796 1797 free (prefclass_buffer); 1798 free (altclass_buffer); 1799 prefclass_buffer = (char *)0; 1800 altclass_buffer = (char *)0; 1801 reg_info_head = (struct reg_info_data *)0; 1802 renumber = (short *)0; 1803 } 1804 regno_allocated = 0; 1805 reg_n_max = 0; 1806 return; 1807 } 1808 1809 if (num_regs > regno_allocated) 1810 { 1811 size_t old_allocated = regno_allocated; 1812 1813 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ 1814 size_renumber = regno_allocated * sizeof (short); 1815 1816 if (!reg_n_info) 1817 { 1818 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); 1819 renumber = (short *) xmalloc (size_renumber); 1820 prefclass_buffer = (char *) xmalloc (regno_allocated); 1821 altclass_buffer = (char *) xmalloc (regno_allocated); 1822 } 1823 1824 else 1825 { 1826 VARRAY_GROW (reg_n_info, regno_allocated); 1827 1828 if (new_p) /* if we're zapping everything, no need to realloc */ 1829 { 1830 free ((char *)renumber); 1831 free ((char *)prefclass_buffer); 1832 free ((char *)altclass_buffer); 1833 renumber = (short *) xmalloc (size_renumber); 1834 prefclass_buffer = (char *) xmalloc (regno_allocated); 1835 altclass_buffer = (char *) xmalloc (regno_allocated); 1836 } 1837 1838 else 1839 { 1840 renumber = (short *) xrealloc ((char *)renumber, size_renumber); 1841 prefclass_buffer = (char *) xrealloc ((char *)prefclass_buffer, 1842 regno_allocated); 1843 1844 altclass_buffer = (char *) xrealloc ((char *)altclass_buffer, 1845 regno_allocated); 1846 } 1847 } 1848 1849 size_info = (regno_allocated - old_allocated) * sizeof (reg_info) 1850 + sizeof (struct reg_info_data) - sizeof (reg_info); 1851 reg_data = (struct reg_info_data *) xcalloc (size_info, 1); 1852 reg_data->min_index = old_allocated; 1853 reg_data->max_index = regno_allocated - 1; 1854 reg_data->next = reg_info_head; 1855 reg_info_head = reg_data; 1856 } 1857 1858 reg_n_max = num_regs; 1859 if (min < num_regs) 1860 { 1861 /* Loop through each of the segments allocated for the actual 1862 reg_info pages, and set up the pointers, zero the pages, etc. */ 1863 for (reg_data = reg_info_head; reg_data; reg_data = reg_next) 1864 { 1865 size_t min_index = reg_data->min_index; 1866 size_t max_index = reg_data->max_index; 1867 1868 reg_next = reg_data->next; 1869 if (min <= max_index) 1870 { 1871 size_t max = max_index; 1872 size_t local_min = min - min_index; 1873 if (min < min_index) 1874 local_min = 0; 1875 if (!reg_data->used_p) /* page just allocated with calloc */ 1876 reg_data->used_p = 1; /* no need to zero */ 1877 else 1878 bzero ((char *) ®_data->data[local_min], 1879 sizeof (reg_info) * (max - min_index - local_min + 1)); 1880 1881 for (i = min_index+local_min; i <= max; i++) 1882 { 1883 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; 1884 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; 1885 renumber[i] = -1; 1886 prefclass_buffer[i] = (char) NO_REGS; 1887 altclass_buffer[i] = (char) NO_REGS; 1888 } 1889 } 1890 } 1891 } 1892 1893 /* If {pref,alt}class have already been allocated, update the pointers to 1894 the newly realloced ones. */ 1895 if (prefclass) 1896 { 1897 prefclass = prefclass_buffer; 1898 altclass = altclass_buffer; 1899 } 1900 1901 if (renumber_p) 1902 reg_renumber = renumber; 1903 1904 /* Tell the regset code about the new number of registers */ 1905 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); 1906} 1907 1908 1909/* This is the `regscan' pass of the compiler, run just before cse 1910 and again just before loop. 1911 1912 It finds the first and last use of each pseudo-register 1913 and records them in the vectors regno_first_uid, regno_last_uid 1914 and counts the number of sets in the vector reg_n_sets. 1915 1916 REPEAT is nonzero the second time this is called. */ 1917 1918/* Maximum number of parallel sets and clobbers in any insn in this fn. 1919 Always at least 3, since the combiner could put that many together 1920 and we want this to remain correct for all the remaining passes. */ 1921 1922int max_parallel; 1923 1924void 1925reg_scan (f, nregs, repeat) 1926 rtx f; 1927 int nregs; 1928 int repeat; 1929{ 1930 register rtx insn; 1931 1932 allocate_reg_info (nregs, TRUE, FALSE); 1933 max_parallel = 3; 1934 1935 for (insn = f; insn; insn = NEXT_INSN (insn)) 1936 if (GET_CODE (insn) == INSN 1937 || GET_CODE (insn) == CALL_INSN 1938 || GET_CODE (insn) == JUMP_INSN) 1939 { 1940 if (GET_CODE (PATTERN (insn)) == PARALLEL 1941 && XVECLEN (PATTERN (insn), 0) > max_parallel) 1942 max_parallel = XVECLEN (PATTERN (insn), 0); 1943 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0); 1944 1945 if (REG_NOTES (insn)) 1946 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); 1947 } 1948} 1949 1950/* Update 'regscan' information by looking at the insns 1951 from FIRST to LAST. Some new REGs have been created, 1952 and any REG with number greater than OLD_MAX_REGNO is 1953 such a REG. We only update information for those. */ 1954 1955void 1956reg_scan_update(first, last, old_max_regno) 1957 rtx first; 1958 rtx last; 1959 int old_max_regno; 1960{ 1961 register rtx insn; 1962 1963 allocate_reg_info (max_reg_num (), FALSE, FALSE); 1964 1965 for (insn = first; insn != last; insn = NEXT_INSN (insn)) 1966 if (GET_CODE (insn) == INSN 1967 || GET_CODE (insn) == CALL_INSN 1968 || GET_CODE (insn) == JUMP_INSN) 1969 { 1970 if (GET_CODE (PATTERN (insn)) == PARALLEL 1971 && XVECLEN (PATTERN (insn), 0) > max_parallel) 1972 max_parallel = XVECLEN (PATTERN (insn), 0); 1973 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno); 1974 1975 if (REG_NOTES (insn)) 1976 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); 1977 } 1978} 1979 1980/* X is the expression to scan. INSN is the insn it appears in. 1981 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. 1982 We should only record information for REGs with numbers 1983 greater than or equal to MIN_REGNO. */ 1984 1985static void 1986reg_scan_mark_refs (x, insn, note_flag, min_regno) 1987 rtx x; 1988 rtx insn; 1989 int note_flag; 1990 int min_regno; 1991{ 1992 register enum rtx_code code; 1993 register rtx dest; 1994 register rtx note; 1995 1996 /* This can happen when scanning insns referenced by certain notes. 1997 1998 It is unclear if we should be scanning such insns; until someone can 1999 say for sure this seems like the safest fix. */ 2000 if (x == NULL_RTX) 2001 return; 2002 2003 code = GET_CODE (x); 2004 switch (code) 2005 { 2006 case CONST_INT: 2007 case CONST: 2008 case CONST_DOUBLE: 2009 case CC0: 2010 case PC: 2011 case SYMBOL_REF: 2012 case LABEL_REF: 2013 case ADDR_VEC: 2014 case ADDR_DIFF_VEC: 2015 return; 2016 2017 case REG: 2018 { 2019 register int regno = REGNO (x); 2020 2021 if (regno >= min_regno) 2022 { 2023 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); 2024 if (!note_flag) 2025 REGNO_LAST_UID (regno) = INSN_UID (insn); 2026 if (REGNO_FIRST_UID (regno) == 0) 2027 REGNO_FIRST_UID (regno) = INSN_UID (insn); 2028 } 2029 } 2030 break; 2031 2032 case EXPR_LIST: 2033 if (XEXP (x, 0)) 2034 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); 2035 if (XEXP (x, 1)) 2036 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); 2037 break; 2038 2039 case INSN_LIST: 2040 if (XEXP (x, 1)) 2041 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); 2042 break; 2043 2044 case SET: 2045 /* Count a set of the destination if it is a register. */ 2046 for (dest = SET_DEST (x); 2047 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART 2048 || GET_CODE (dest) == ZERO_EXTEND; 2049 dest = XEXP (dest, 0)) 2050 ; 2051 2052 if (GET_CODE (dest) == REG 2053 && REGNO (dest) >= min_regno) 2054 REG_N_SETS (REGNO (dest))++; 2055 2056 /* If this is setting a pseudo from another pseudo or the sum of a 2057 pseudo and a constant integer and the other pseudo is known to be 2058 a pointer, set the destination to be a pointer as well. 2059 2060 Likewise if it is setting the destination from an address or from a 2061 value equivalent to an address or to the sum of an address and 2062 something else. 2063 2064 But don't do any of this if the pseudo corresponds to a user 2065 variable since it should have already been set as a pointer based 2066 on the type. */ 2067 2068 if (GET_CODE (SET_DEST (x)) == REG 2069 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER 2070 && REGNO (SET_DEST (x)) >= min_regno 2071 /* If the destination pseudo is set more than once, then other 2072 sets might not be to a pointer value (consider access to a 2073 union in two threads of control in the presense of global 2074 optimizations). So only set REGNO_POINTER_FLAG on the destination 2075 pseudo if this is the only set of that pseudo. */ 2076 && REG_N_SETS (REGNO (SET_DEST (x))) == 1 2077 && ! REG_USERVAR_P (SET_DEST (x)) 2078 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) 2079 && ((GET_CODE (SET_SRC (x)) == REG 2080 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x)))) 2081 || ((GET_CODE (SET_SRC (x)) == PLUS 2082 || GET_CODE (SET_SRC (x)) == LO_SUM) 2083 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 2084 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG 2085 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0)))) 2086 || GET_CODE (SET_SRC (x)) == CONST 2087 || GET_CODE (SET_SRC (x)) == SYMBOL_REF 2088 || GET_CODE (SET_SRC (x)) == LABEL_REF 2089 || (GET_CODE (SET_SRC (x)) == HIGH 2090 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST 2091 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF 2092 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) 2093 || ((GET_CODE (SET_SRC (x)) == PLUS 2094 || GET_CODE (SET_SRC (x)) == LO_SUM) 2095 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST 2096 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF 2097 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) 2098 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 2099 && (GET_CODE (XEXP (note, 0)) == CONST 2100 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF 2101 || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) 2102 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1; 2103 2104 /* ... fall through ... */ 2105 2106 default: 2107 { 2108 register char *fmt = GET_RTX_FORMAT (code); 2109 register int i; 2110 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2111 { 2112 if (fmt[i] == 'e') 2113 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); 2114 else if (fmt[i] == 'E' && XVEC (x, i) != 0) 2115 { 2116 register int j; 2117 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 2118 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); 2119 } 2120 } 2121 } 2122 } 2123} 2124 2125/* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 2126 is also in C2. */ 2127 2128int 2129reg_class_subset_p (c1, c2) 2130 register enum reg_class c1; 2131 register enum reg_class c2; 2132{ 2133 if (c1 == c2) return 1; 2134 2135 if (c2 == ALL_REGS) 2136 win: 2137 return 1; 2138 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], 2139 reg_class_contents[(int)c2], 2140 win); 2141 return 0; 2142} 2143 2144/* Return nonzero if there is a register that is in both C1 and C2. */ 2145 2146int 2147reg_classes_intersect_p (c1, c2) 2148 register enum reg_class c1; 2149 register enum reg_class c2; 2150{ 2151#ifdef HARD_REG_SET 2152 register 2153#endif 2154 HARD_REG_SET c; 2155 2156 if (c1 == c2) return 1; 2157 2158 if (c1 == ALL_REGS || c2 == ALL_REGS) 2159 return 1; 2160 2161 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); 2162 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); 2163 2164 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); 2165 return 1; 2166 2167 lose: 2168 return 0; 2169} 2170 2171/* Release any memory allocated by register sets. */ 2172 2173void 2174regset_release_memory () 2175{ 2176 if (basic_block_live_at_start) 2177 { 2178 free_regset_vector (basic_block_live_at_start, n_basic_blocks); 2179 basic_block_live_at_start = 0; 2180 } 2181 2182 FREE_REG_SET (regs_live_at_setjmp); 2183 bitmap_release_memory (); 2184} 2185