regclass.c revision 132718
1/* Compute register class preferences for pseudo-registers. 2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996 3 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify it under 8the terms of the GNU General Public License as published by the Free 9Software Foundation; either version 2, or (at your option) any later 10version. 11 12GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13WARRANTY; without even the implied warranty of MERCHANTABILITY or 14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING. If not, write to the Free 19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 2002111-1307, USA. */ 21 22 23/* This file contains two passes of the compiler: reg_scan and reg_class. 24 It also defines some tables of information about the hardware registers 25 and a function init_reg_sets to initialize the tables. */ 26 27#include "config.h" 28#include "system.h" 29#include "coretypes.h" 30#include "tm.h" 31#include "hard-reg-set.h" 32#include "rtl.h" 33#include "expr.h" 34#include "tm_p.h" 35#include "flags.h" 36#include "basic-block.h" 37#include "regs.h" 38#include "function.h" 39#include "insn-config.h" 40#include "recog.h" 41#include "reload.h" 42#include "real.h" 43#include "toplev.h" 44#include "output.h" 45#include "ggc.h" 46#include "timevar.h" 47 48static void init_reg_sets_1 (void); 49static void init_reg_autoinc (void); 50 51/* If we have auto-increment or auto-decrement and we can have secondary 52 reloads, we are not allowed to use classes requiring secondary 53 reloads for pseudos auto-incremented since reload can't handle it. */ 54 55#ifdef AUTO_INC_DEC 56#if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) 57#define FORBIDDEN_INC_DEC_CLASSES 58#endif 59#endif 60 61/* Register tables used by many passes. */ 62 63/* Indexed by hard register number, contains 1 for registers 64 that are fixed use (stack pointer, pc, frame pointer, etc.). 65 These are the registers that cannot be used to allocate 66 a pseudo reg for general use. */ 67 68char fixed_regs[FIRST_PSEUDO_REGISTER]; 69 70/* Same info as a HARD_REG_SET. */ 71 72HARD_REG_SET fixed_reg_set; 73 74/* Data for initializing the above. */ 75 76static const char initial_fixed_regs[] = FIXED_REGISTERS; 77 78/* Indexed by hard register number, contains 1 for registers 79 that are fixed use or are clobbered by function calls. 80 These are the registers that cannot be used to allocate 81 a pseudo reg whose life crosses calls unless we are able 82 to save/restore them across the calls. */ 83 84char call_used_regs[FIRST_PSEUDO_REGISTER]; 85 86/* Same info as a HARD_REG_SET. */ 87 88HARD_REG_SET call_used_reg_set; 89 90/* HARD_REG_SET of registers we want to avoid caller saving. */ 91HARD_REG_SET losing_caller_save_reg_set; 92 93/* Data for initializing the above. */ 94 95static const char initial_call_used_regs[] = CALL_USED_REGISTERS; 96 97/* This is much like call_used_regs, except it doesn't have to 98 be a superset of FIXED_REGISTERS. This vector indicates 99 what is really call clobbered, and is used when defining 100 regs_invalidated_by_call. */ 101 102#ifdef CALL_REALLY_USED_REGISTERS 103char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; 104#endif 105 106/* Indexed by hard register number, contains 1 for registers that are 107 fixed use or call used registers that cannot hold quantities across 108 calls even if we are willing to save and restore them. call fixed 109 registers are a subset of call used registers. */ 110 111char call_fixed_regs[FIRST_PSEUDO_REGISTER]; 112 113/* The same info as a HARD_REG_SET. */ 114 115HARD_REG_SET call_fixed_reg_set; 116 117/* Number of non-fixed registers. */ 118 119int n_non_fixed_regs; 120 121/* Indexed by hard register number, contains 1 for registers 122 that are being used for global register decls. 123 These must be exempt from ordinary flow analysis 124 and are also considered fixed. */ 125 126char global_regs[FIRST_PSEUDO_REGISTER]; 127 128/* Contains 1 for registers that are set or clobbered by calls. */ 129/* ??? Ideally, this would be just call_used_regs plus global_regs, but 130 for someone's bright idea to have call_used_regs strictly include 131 fixed_regs. Which leaves us guessing as to the set of fixed_regs 132 that are actually preserved. We know for sure that those associated 133 with the local stack frame are safe, but scant others. */ 134 135HARD_REG_SET regs_invalidated_by_call; 136 137/* Table of register numbers in the order in which to try to use them. */ 138#ifdef REG_ALLOC_ORDER 139int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; 140 141/* The inverse of reg_alloc_order. */ 142int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER]; 143#endif 144 145/* For each reg class, a HARD_REG_SET saying which registers are in it. */ 146 147HARD_REG_SET reg_class_contents[N_REG_CLASSES]; 148 149/* The same information, but as an array of unsigned ints. We copy from 150 these unsigned ints to the table above. We do this so the tm.h files 151 do not have to be aware of the wordsize for machines with <= 64 regs. 152 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ 153 154#define N_REG_INTS \ 155 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32) 156 157static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] 158 = REG_CLASS_CONTENTS; 159 160/* For each reg class, number of regs it contains. */ 161 162unsigned int reg_class_size[N_REG_CLASSES]; 163 164/* For each reg class, table listing all the containing classes. */ 165 166enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; 167 168/* For each reg class, table listing all the classes contained in it. */ 169 170enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; 171 172/* For each pair of reg classes, 173 a largest reg class contained in their union. */ 174 175enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; 176 177/* For each pair of reg classes, 178 the smallest reg class containing their union. */ 179 180enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; 181 182/* Array containing all of the register names. */ 183 184const char * reg_names[] = REGISTER_NAMES; 185 186/* For each hard register, the widest mode object that it can contain. 187 This will be a MODE_INT mode if the register can hold integers. Otherwise 188 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the 189 register. */ 190 191enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; 192 193/* 1 if class does contain register of given mode. */ 194 195static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE]; 196 197/* Maximum cost of moving from a register in one class to a register in 198 another class. Based on REGISTER_MOVE_COST. */ 199 200static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; 201 202/* Similar, but here we don't have to move if the first index is a subset 203 of the second so in that case the cost is zero. */ 204 205static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; 206 207/* Similar, but here we don't have to move if the first index is a superset 208 of the second so in that case the cost is zero. */ 209 210static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; 211 212#ifdef FORBIDDEN_INC_DEC_CLASSES 213 214/* These are the classes that regs which are auto-incremented or decremented 215 cannot be put in. */ 216 217static int forbidden_inc_dec_class[N_REG_CLASSES]; 218 219/* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec 220 context. */ 221 222static char *in_inc_dec; 223 224#endif /* FORBIDDEN_INC_DEC_CLASSES */ 225 226#ifdef CANNOT_CHANGE_MODE_CLASS 227/* All registers that have been subreged. Indexed by regno * MAX_MACHINE_MODE 228 + mode. */ 229bitmap_head subregs_of_mode; 230#endif 231 232/* Sample MEM values for use by memory_move_secondary_cost. */ 233 234static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE]; 235 236/* Linked list of reg_info structures allocated for reg_n_info array. 237 Grouping all of the allocated structures together in one lump 238 means only one call to bzero to clear them, rather than n smaller 239 calls. */ 240struct reg_info_data { 241 struct reg_info_data *next; /* next set of reg_info structures */ 242 size_t min_index; /* minimum index # */ 243 size_t max_index; /* maximum index # */ 244 char used_p; /* nonzero if this has been used previously */ 245 reg_info data[1]; /* beginning of the reg_info data */ 246}; 247 248static struct reg_info_data *reg_info_head; 249 250/* No more global register variables may be declared; true once 251 regclass has been initialized. */ 252 253static int no_global_reg_vars = 0; 254 255 256/* Function called only once to initialize the above data on reg usage. 257 Once this is done, various switches may override. */ 258 259void 260init_reg_sets (void) 261{ 262 int i, j; 263 264 /* First copy the register information from the initial int form into 265 the regsets. */ 266 267 for (i = 0; i < N_REG_CLASSES; i++) 268 { 269 CLEAR_HARD_REG_SET (reg_class_contents[i]); 270 271 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ 272 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 273 if (int_reg_class_contents[i][j / 32] 274 & ((unsigned) 1 << (j % 32))) 275 SET_HARD_REG_BIT (reg_class_contents[i], j); 276 } 277 278 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); 279 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); 280 memset (global_regs, 0, sizeof global_regs); 281 282 /* Do any additional initialization regsets may need. */ 283 INIT_ONCE_REG_SET (); 284 285#ifdef REG_ALLOC_ORDER 286 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 287 inv_reg_alloc_order[reg_alloc_order[i]] = i; 288#endif 289} 290 291/* After switches have been processed, which perhaps alter 292 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ 293 294static void 295init_reg_sets_1 (void) 296{ 297 unsigned int i, j; 298 unsigned int /* enum machine_mode */ m; 299 char allocatable_regs_of_mode [MAX_MACHINE_MODE]; 300 301 /* This macro allows the fixed or call-used registers 302 and the register classes to depend on target flags. */ 303 304#ifdef CONDITIONAL_REGISTER_USAGE 305 CONDITIONAL_REGISTER_USAGE; 306#endif 307 308 /* Compute number of hard regs in each class. */ 309 310 memset (reg_class_size, 0, sizeof reg_class_size); 311 for (i = 0; i < N_REG_CLASSES; i++) 312 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 313 if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 314 reg_class_size[i]++; 315 316 /* Initialize the table of subunions. 317 reg_class_subunion[I][J] gets the largest-numbered reg-class 318 that is contained in the union of classes I and J. */ 319 320 for (i = 0; i < N_REG_CLASSES; i++) 321 { 322 for (j = 0; j < N_REG_CLASSES; j++) 323 { 324 HARD_REG_SET c; 325 int k; 326 327 COPY_HARD_REG_SET (c, reg_class_contents[i]); 328 IOR_HARD_REG_SET (c, reg_class_contents[j]); 329 for (k = 0; k < N_REG_CLASSES; k++) 330 { 331 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, 332 subclass1); 333 continue; 334 335 subclass1: 336 /* Keep the largest subclass. */ /* SPEE 900308 */ 337 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], 338 reg_class_contents[(int) reg_class_subunion[i][j]], 339 subclass2); 340 reg_class_subunion[i][j] = (enum reg_class) k; 341 subclass2: 342 ; 343 } 344 } 345 } 346 347 /* Initialize the table of superunions. 348 reg_class_superunion[I][J] gets the smallest-numbered reg-class 349 containing the union of classes I and J. */ 350 351 for (i = 0; i < N_REG_CLASSES; i++) 352 { 353 for (j = 0; j < N_REG_CLASSES; j++) 354 { 355 HARD_REG_SET c; 356 int k; 357 358 COPY_HARD_REG_SET (c, reg_class_contents[i]); 359 IOR_HARD_REG_SET (c, reg_class_contents[j]); 360 for (k = 0; k < N_REG_CLASSES; k++) 361 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); 362 363 superclass: 364 reg_class_superunion[i][j] = (enum reg_class) k; 365 } 366 } 367 368 /* Initialize the tables of subclasses and superclasses of each reg class. 369 First clear the whole table, then add the elements as they are found. */ 370 371 for (i = 0; i < N_REG_CLASSES; i++) 372 { 373 for (j = 0; j < N_REG_CLASSES; j++) 374 { 375 reg_class_superclasses[i][j] = LIM_REG_CLASSES; 376 reg_class_subclasses[i][j] = LIM_REG_CLASSES; 377 } 378 } 379 380 for (i = 0; i < N_REG_CLASSES; i++) 381 { 382 if (i == (int) NO_REGS) 383 continue; 384 385 for (j = i + 1; j < N_REG_CLASSES; j++) 386 { 387 enum reg_class *p; 388 389 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], 390 subclass); 391 continue; 392 subclass: 393 /* Reg class I is a subclass of J. 394 Add J to the table of superclasses of I. */ 395 p = ®_class_superclasses[i][0]; 396 while (*p != LIM_REG_CLASSES) p++; 397 *p = (enum reg_class) j; 398 /* Add I to the table of superclasses of J. */ 399 p = ®_class_subclasses[j][0]; 400 while (*p != LIM_REG_CLASSES) p++; 401 *p = (enum reg_class) i; 402 } 403 } 404 405 /* Initialize "constant" tables. */ 406 407 CLEAR_HARD_REG_SET (fixed_reg_set); 408 CLEAR_HARD_REG_SET (call_used_reg_set); 409 CLEAR_HARD_REG_SET (call_fixed_reg_set); 410 CLEAR_HARD_REG_SET (regs_invalidated_by_call); 411 412 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs); 413 414 n_non_fixed_regs = 0; 415 416 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 417 { 418 if (fixed_regs[i]) 419 SET_HARD_REG_BIT (fixed_reg_set, i); 420 else 421 n_non_fixed_regs++; 422 423 if (call_used_regs[i]) 424 SET_HARD_REG_BIT (call_used_reg_set, i); 425 if (call_fixed_regs[i]) 426 SET_HARD_REG_BIT (call_fixed_reg_set, i); 427 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) 428 SET_HARD_REG_BIT (losing_caller_save_reg_set, i); 429 430 /* There are a couple of fixed registers that we know are safe to 431 exclude from being clobbered by calls: 432 433 The frame pointer is always preserved across calls. The arg pointer 434 is if it is fixed. The stack pointer usually is, unless 435 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present. 436 If we are generating PIC code, the PIC offset table register is 437 preserved across calls, though the target can override that. */ 438 439 if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM) 440 ; 441#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 442 else if (i == HARD_FRAME_POINTER_REGNUM) 443 ; 444#endif 445#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM 446 else if (i == ARG_POINTER_REGNUM && fixed_regs[i]) 447 ; 448#endif 449#ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 450 else if (i == (unsigned) PIC_OFFSET_TABLE_REGNUM && fixed_regs[i]) 451 ; 452#endif 453 else if (0 454#ifdef CALL_REALLY_USED_REGISTERS 455 || call_really_used_regs[i] 456#else 457 || call_used_regs[i] 458#endif 459 || global_regs[i]) 460 SET_HARD_REG_BIT (regs_invalidated_by_call, i); 461 } 462 463 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode)); 464 memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode)); 465 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) 466 for (i = 0; i < N_REG_CLASSES; i++) 467 if ((unsigned) CLASS_MAX_NREGS (i, m) <= reg_class_size[i]) 468 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 469 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j) 470 && HARD_REGNO_MODE_OK (j, m)) 471 { 472 contains_reg_of_mode [i][m] = 1; 473 allocatable_regs_of_mode [m] = 1; 474 break; 475 } 476 477 /* Initialize the move cost table. Find every subset of each class 478 and take the maximum cost of moving any subset to any other. */ 479 480 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) 481 if (allocatable_regs_of_mode [m]) 482 { 483 for (i = 0; i < N_REG_CLASSES; i++) 484 if (contains_reg_of_mode [i][m]) 485 for (j = 0; j < N_REG_CLASSES; j++) 486 { 487 int cost; 488 enum reg_class *p1, *p2; 489 490 if (!contains_reg_of_mode [j][m]) 491 { 492 move_cost[m][i][j] = 65536; 493 may_move_in_cost[m][i][j] = 65536; 494 may_move_out_cost[m][i][j] = 65536; 495 } 496 else 497 { 498 cost = REGISTER_MOVE_COST (m, i, j); 499 500 for (p2 = ®_class_subclasses[j][0]; 501 *p2 != LIM_REG_CLASSES; 502 p2++) 503 if (*p2 != i && contains_reg_of_mode [*p2][m]) 504 cost = MAX (cost, move_cost [m][i][*p2]); 505 506 for (p1 = ®_class_subclasses[i][0]; 507 *p1 != LIM_REG_CLASSES; 508 p1++) 509 if (*p1 != j && contains_reg_of_mode [*p1][m]) 510 cost = MAX (cost, move_cost [m][*p1][j]); 511 512 move_cost[m][i][j] = cost; 513 514 if (reg_class_subset_p (i, j)) 515 may_move_in_cost[m][i][j] = 0; 516 else 517 may_move_in_cost[m][i][j] = cost; 518 519 if (reg_class_subset_p (j, i)) 520 may_move_out_cost[m][i][j] = 0; 521 else 522 may_move_out_cost[m][i][j] = cost; 523 } 524 } 525 else 526 for (j = 0; j < N_REG_CLASSES; j++) 527 { 528 move_cost[m][i][j] = 65536; 529 may_move_in_cost[m][i][j] = 65536; 530 may_move_out_cost[m][i][j] = 65536; 531 } 532 } 533} 534 535/* Compute the table of register modes. 536 These values are used to record death information for individual registers 537 (as opposed to a multi-register mode). */ 538 539void 540init_reg_modes_once (void) 541{ 542 int i; 543 544 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 545 { 546 reg_raw_mode[i] = choose_hard_reg_mode (i, 1, false); 547 548 /* If we couldn't find a valid mode, just use the previous mode. 549 ??? One situation in which we need to do this is on the mips where 550 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like 551 to use DF mode for the even registers and VOIDmode for the odd 552 (for the cpu models where the odd ones are inaccessible). */ 553 if (reg_raw_mode[i] == VOIDmode) 554 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; 555 } 556} 557 558/* Finish initializing the register sets and 559 initialize the register modes. */ 560 561void 562init_regs (void) 563{ 564 /* This finishes what was started by init_reg_sets, but couldn't be done 565 until after register usage was specified. */ 566 init_reg_sets_1 (); 567 568 init_reg_autoinc (); 569} 570 571/* Initialize some fake stack-frame MEM references for use in 572 memory_move_secondary_cost. */ 573 574void 575init_fake_stack_mems (void) 576{ 577#ifdef HAVE_SECONDARY_RELOADS 578 { 579 int i; 580 581 for (i = 0; i < MAX_MACHINE_MODE; i++) 582 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); 583 } 584#endif 585} 586 587#ifdef HAVE_SECONDARY_RELOADS 588 589/* Compute extra cost of moving registers to/from memory due to reloads. 590 Only needed if secondary reloads are required for memory moves. */ 591 592int 593memory_move_secondary_cost (enum machine_mode mode, enum reg_class class, int in) 594{ 595 enum reg_class altclass; 596 int partial_cost = 0; 597 /* We need a memory reference to feed to SECONDARY... macros. */ 598 /* mem may be unused even if the SECONDARY_ macros are defined. */ 599 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; 600 601 602 if (in) 603 { 604#ifdef SECONDARY_INPUT_RELOAD_CLASS 605 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); 606#else 607 altclass = NO_REGS; 608#endif 609 } 610 else 611 { 612#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 613 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); 614#else 615 altclass = NO_REGS; 616#endif 617 } 618 619 if (altclass == NO_REGS) 620 return 0; 621 622 if (in) 623 partial_cost = REGISTER_MOVE_COST (mode, altclass, class); 624 else 625 partial_cost = REGISTER_MOVE_COST (mode, class, altclass); 626 627 if (class == altclass) 628 /* This isn't simply a copy-to-temporary situation. Can't guess 629 what it is, so MEMORY_MOVE_COST really ought not to be calling 630 here in that case. 631 632 I'm tempted to put in an abort here, but returning this will 633 probably only give poor estimates, which is what we would've 634 had before this code anyways. */ 635 return partial_cost; 636 637 /* Check if the secondary reload register will also need a 638 secondary reload. */ 639 return memory_move_secondary_cost (mode, altclass, in) + partial_cost; 640} 641#endif 642 643/* Return a machine mode that is legitimate for hard reg REGNO and large 644 enough to save nregs. If we can't find one, return VOIDmode. 645 If CALL_SAVED is true, only consider modes that are call saved. */ 646 647enum machine_mode 648choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED, 649 unsigned int nregs, bool call_saved) 650{ 651 unsigned int /* enum machine_mode */ m; 652 enum machine_mode found_mode = VOIDmode, mode; 653 654 /* We first look for the largest integer mode that can be validly 655 held in REGNO. If none, we look for the largest floating-point mode. 656 If we still didn't find a valid mode, try CCmode. */ 657 658 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); 659 mode != VOIDmode; 660 mode = GET_MODE_WIDER_MODE (mode)) 661 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs 662 && HARD_REGNO_MODE_OK (regno, mode) 663 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) 664 found_mode = mode; 665 666 if (found_mode != VOIDmode) 667 return found_mode; 668 669 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); 670 mode != VOIDmode; 671 mode = GET_MODE_WIDER_MODE (mode)) 672 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs 673 && HARD_REGNO_MODE_OK (regno, mode) 674 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) 675 found_mode = mode; 676 677 if (found_mode != VOIDmode) 678 return found_mode; 679 680 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); 681 mode != VOIDmode; 682 mode = GET_MODE_WIDER_MODE (mode)) 683 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs 684 && HARD_REGNO_MODE_OK (regno, mode) 685 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) 686 found_mode = mode; 687 688 if (found_mode != VOIDmode) 689 return found_mode; 690 691 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); 692 mode != VOIDmode; 693 mode = GET_MODE_WIDER_MODE (mode)) 694 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs 695 && HARD_REGNO_MODE_OK (regno, mode) 696 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) 697 found_mode = mode; 698 699 if (found_mode != VOIDmode) 700 return found_mode; 701 702 /* Iterate over all of the CCmodes. */ 703 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m) 704 { 705 mode = (enum machine_mode) m; 706 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs 707 && HARD_REGNO_MODE_OK (regno, mode) 708 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) 709 return mode; 710 } 711 712 /* We can't find a mode valid for this register. */ 713 return VOIDmode; 714} 715 716/* Specify the usage characteristics of the register named NAME. 717 It should be a fixed register if FIXED and a 718 call-used register if CALL_USED. */ 719 720void 721fix_register (const char *name, int fixed, int call_used) 722{ 723 int i; 724 725 /* Decode the name and update the primary form of 726 the register info. */ 727 728 if ((i = decode_reg_name (name)) >= 0) 729 { 730 if ((i == STACK_POINTER_REGNUM 731#ifdef HARD_FRAME_POINTER_REGNUM 732 || i == HARD_FRAME_POINTER_REGNUM 733#else 734 || i == FRAME_POINTER_REGNUM 735#endif 736 ) 737 && (fixed == 0 || call_used == 0)) 738 { 739 static const char * const what_option[2][2] = { 740 { "call-saved", "call-used" }, 741 { "no-such-option", "fixed" }}; 742 743 error ("can't use '%s' as a %s register", name, 744 what_option[fixed][call_used]); 745 } 746 else 747 { 748 fixed_regs[i] = fixed; 749 call_used_regs[i] = call_used; 750#ifdef CALL_REALLY_USED_REGISTERS 751 if (fixed == 0) 752 call_really_used_regs[i] = call_used; 753#endif 754 } 755 } 756 else 757 { 758 warning ("unknown register name: %s", name); 759 } 760} 761 762/* Mark register number I as global. */ 763 764void 765globalize_reg (int i) 766{ 767 if (fixed_regs[i] == 0 && no_global_reg_vars) 768 error ("global register variable follows a function definition"); 769 770 if (global_regs[i]) 771 { 772 warning ("register used for two global register variables"); 773 return; 774 } 775 776 if (call_used_regs[i] && ! fixed_regs[i]) 777 warning ("call-clobbered register used for global register variable"); 778 779 global_regs[i] = 1; 780 781 /* If already fixed, nothing else to do. */ 782 if (fixed_regs[i]) 783 return; 784 785 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; 786 n_non_fixed_regs--; 787 788 SET_HARD_REG_BIT (fixed_reg_set, i); 789 SET_HARD_REG_BIT (call_used_reg_set, i); 790 SET_HARD_REG_BIT (call_fixed_reg_set, i); 791 SET_HARD_REG_BIT (regs_invalidated_by_call, i); 792} 793 794/* Now the data and code for the `regclass' pass, which happens 795 just before local-alloc. */ 796 797/* The `costs' struct records the cost of using a hard register of each class 798 and of using memory for each pseudo. We use this data to set up 799 register class preferences. */ 800 801struct costs 802{ 803 int cost[N_REG_CLASSES]; 804 int mem_cost; 805}; 806 807/* Structure used to record preferences of given pseudo. */ 808struct reg_pref 809{ 810 /* (enum reg_class) prefclass is the preferred class. */ 811 char prefclass; 812 813 /* altclass is a register class that we should use for allocating 814 pseudo if no register in the preferred class is available. 815 If no register in this class is available, memory is preferred. 816 817 It might appear to be more general to have a bitmask of classes here, 818 but since it is recommended that there be a class corresponding to the 819 union of most major pair of classes, that generality is not required. */ 820 char altclass; 821}; 822 823/* Record the cost of each class for each pseudo. */ 824 825static struct costs *costs; 826 827/* Initialized once, and used to initialize cost values for each insn. */ 828 829static struct costs init_cost; 830 831/* Record preferences of each pseudo. 832 This is available after `regclass' is run. */ 833 834static struct reg_pref *reg_pref; 835 836/* Allocated buffers for reg_pref. */ 837 838static struct reg_pref *reg_pref_buffer; 839 840/* Frequency of executions of current insn. */ 841 842static int frequency; 843 844static rtx scan_one_insn (rtx, int); 845static void record_operand_costs (rtx, struct costs *, struct reg_pref *); 846static void dump_regclass (FILE *); 847static void record_reg_classes (int, int, rtx *, enum machine_mode *, 848 const char **, rtx, struct costs *, 849 struct reg_pref *); 850static int copy_cost (rtx, enum machine_mode, enum reg_class, int); 851static void record_address_regs (rtx, enum reg_class, int); 852#ifdef FORBIDDEN_INC_DEC_CLASSES 853static int auto_inc_dec_reg_p (rtx, enum machine_mode); 854#endif 855static void reg_scan_mark_refs (rtx, rtx, int, unsigned int); 856 857/* Return the reg_class in which pseudo reg number REGNO is best allocated. 858 This function is sometimes called before the info has been computed. 859 When that happens, just return GENERAL_REGS, which is innocuous. */ 860 861enum reg_class 862reg_preferred_class (int regno) 863{ 864 if (reg_pref == 0) 865 return GENERAL_REGS; 866 return (enum reg_class) reg_pref[regno].prefclass; 867} 868 869enum reg_class 870reg_alternate_class (int regno) 871{ 872 if (reg_pref == 0) 873 return ALL_REGS; 874 875 return (enum reg_class) reg_pref[regno].altclass; 876} 877 878/* Initialize some global data for this pass. */ 879 880void 881regclass_init (void) 882{ 883 int i; 884 885 init_cost.mem_cost = 10000; 886 for (i = 0; i < N_REG_CLASSES; i++) 887 init_cost.cost[i] = 10000; 888 889 /* This prevents dump_flow_info from losing if called 890 before regclass is run. */ 891 reg_pref = NULL; 892 893 /* No more global register variables may be declared. */ 894 no_global_reg_vars = 1; 895} 896 897/* Dump register costs. */ 898static void 899dump_regclass (FILE *dump) 900{ 901 static const char *const reg_class_names[] = REG_CLASS_NAMES; 902 int i; 903 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 904 { 905 int /* enum reg_class */ class; 906 if (REG_N_REFS (i)) 907 { 908 fprintf (dump, " Register %i costs:", i); 909 for (class = 0; class < (int) N_REG_CLASSES; class++) 910 if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)] 911#ifdef FORBIDDEN_INC_DEC_CLASSES 912 && (!in_inc_dec[i] 913 || !forbidden_inc_dec_class[(enum reg_class) class]) 914#endif 915#ifdef CANNOT_CHANGE_MODE_CLASS 916 && ! invalid_mode_change_p (i, (enum reg_class) class, 917 PSEUDO_REGNO_MODE (i)) 918#endif 919 ) 920 fprintf (dump, " %s:%i", reg_class_names[class], 921 costs[i].cost[(enum reg_class) class]); 922 fprintf (dump, " MEM:%i\n", costs[i].mem_cost); 923 } 924 } 925} 926 927 928/* Calculate the costs of insn operands. */ 929 930static void 931record_operand_costs (rtx insn, struct costs *op_costs, 932 struct reg_pref *reg_pref) 933{ 934 const char *constraints[MAX_RECOG_OPERANDS]; 935 enum machine_mode modes[MAX_RECOG_OPERANDS]; 936 int i; 937 938 for (i = 0; i < recog_data.n_operands; i++) 939 { 940 constraints[i] = recog_data.constraints[i]; 941 modes[i] = recog_data.operand_mode[i]; 942 } 943 944 /* If we get here, we are set up to record the costs of all the 945 operands for this insn. Start by initializing the costs. 946 Then handle any address registers. Finally record the desired 947 classes for any pseudos, doing it twice if some pair of 948 operands are commutative. */ 949 950 for (i = 0; i < recog_data.n_operands; i++) 951 { 952 op_costs[i] = init_cost; 953 954 if (GET_CODE (recog_data.operand[i]) == SUBREG) 955 recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); 956 957 if (GET_CODE (recog_data.operand[i]) == MEM) 958 record_address_regs (XEXP (recog_data.operand[i], 0), 959 MODE_BASE_REG_CLASS (modes[i]), frequency * 2); 960 else if (constraints[i][0] == 'p' 961 || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i])) 962 record_address_regs (recog_data.operand[i], 963 MODE_BASE_REG_CLASS (modes[i]), frequency * 2); 964 } 965 966 /* Check for commutative in a separate loop so everything will 967 have been initialized. We must do this even if one operand 968 is a constant--see addsi3 in m68k.md. */ 969 970 for (i = 0; i < (int) recog_data.n_operands - 1; i++) 971 if (constraints[i][0] == '%') 972 { 973 const char *xconstraints[MAX_RECOG_OPERANDS]; 974 int j; 975 976 /* Handle commutative operands by swapping the constraints. 977 We assume the modes are the same. */ 978 979 for (j = 0; j < recog_data.n_operands; j++) 980 xconstraints[j] = constraints[j]; 981 982 xconstraints[i] = constraints[i+1]; 983 xconstraints[i+1] = constraints[i]; 984 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, 985 recog_data.operand, modes, 986 xconstraints, insn, op_costs, reg_pref); 987 } 988 989 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, 990 recog_data.operand, modes, 991 constraints, insn, op_costs, reg_pref); 992} 993 994/* Subroutine of regclass, processes one insn INSN. Scan it and record each 995 time it would save code to put a certain register in a certain class. 996 PASS, when nonzero, inhibits some optimizations which need only be done 997 once. 998 Return the last insn processed, so that the scan can be continued from 999 there. */ 1000 1001static rtx 1002scan_one_insn (rtx insn, int pass) 1003{ 1004 enum rtx_code code = GET_CODE (insn); 1005 enum rtx_code pat_code; 1006 rtx set, note; 1007 int i, j; 1008 struct costs op_costs[MAX_RECOG_OPERANDS]; 1009 1010 if (GET_RTX_CLASS (code) != 'i') 1011 return insn; 1012 1013 pat_code = GET_CODE (PATTERN (insn)); 1014 if (pat_code == USE 1015 || pat_code == CLOBBER 1016 || pat_code == ASM_INPUT 1017 || pat_code == ADDR_VEC 1018 || pat_code == ADDR_DIFF_VEC) 1019 return insn; 1020 1021 set = single_set (insn); 1022 extract_insn (insn); 1023 1024 /* If this insn loads a parameter from its stack slot, then 1025 it represents a savings, rather than a cost, if the 1026 parameter is stored in memory. Record this fact. */ 1027 1028 if (set != 0 && GET_CODE (SET_DEST (set)) == REG 1029 && GET_CODE (SET_SRC (set)) == MEM 1030 && (note = find_reg_note (insn, REG_EQUIV, 1031 NULL_RTX)) != 0 1032 && GET_CODE (XEXP (note, 0)) == MEM) 1033 { 1034 costs[REGNO (SET_DEST (set))].mem_cost 1035 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), 1036 GENERAL_REGS, 1) 1037 * frequency); 1038 record_address_regs (XEXP (SET_SRC (set), 0), 1039 MODE_BASE_REG_CLASS (VOIDmode), frequency * 2); 1040 return insn; 1041 } 1042 1043 /* Improve handling of two-address insns such as 1044 (set X (ashift CONST Y)) where CONST must be made to 1045 match X. Change it into two insns: (set X CONST) 1046 (set X (ashift X Y)). If we left this for reloading, it 1047 would probably get three insns because X and Y might go 1048 in the same place. This prevents X and Y from receiving 1049 the same hard reg. 1050 1051 We can only do this if the modes of operands 0 and 1 1052 (which might not be the same) are tieable and we only need 1053 do this during our first pass. */ 1054 1055 if (pass == 0 && optimize 1056 && recog_data.n_operands >= 3 1057 && recog_data.constraints[1][0] == '0' 1058 && recog_data.constraints[1][1] == 0 1059 && CONSTANT_P (recog_data.operand[1]) 1060 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1]) 1061 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2]) 1062 && GET_CODE (recog_data.operand[0]) == REG 1063 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]), 1064 recog_data.operand_mode[1])) 1065 { 1066 rtx previnsn = prev_real_insn (insn); 1067 rtx dest 1068 = gen_lowpart (recog_data.operand_mode[1], 1069 recog_data.operand[0]); 1070 rtx newinsn 1071 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn); 1072 1073 /* If this insn was the start of a basic block, 1074 include the new insn in that block. 1075 We need not check for code_label here; 1076 while a basic block can start with a code_label, 1077 INSN could not be at the beginning of that block. */ 1078 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) 1079 { 1080 basic_block b; 1081 FOR_EACH_BB (b) 1082 if (insn == BB_HEAD (b)) 1083 BB_HEAD (b) = newinsn; 1084 } 1085 1086 /* This makes one more setting of new insns's dest. */ 1087 REG_N_SETS (REGNO (recog_data.operand[0]))++; 1088 REG_N_REFS (REGNO (recog_data.operand[0]))++; 1089 REG_FREQ (REGNO (recog_data.operand[0])) += frequency; 1090 1091 *recog_data.operand_loc[1] = recog_data.operand[0]; 1092 REG_N_REFS (REGNO (recog_data.operand[0]))++; 1093 REG_FREQ (REGNO (recog_data.operand[0])) += frequency; 1094 for (i = recog_data.n_dups - 1; i >= 0; i--) 1095 if (recog_data.dup_num[i] == 1) 1096 { 1097 *recog_data.dup_loc[i] = recog_data.operand[0]; 1098 REG_N_REFS (REGNO (recog_data.operand[0]))++; 1099 REG_FREQ (REGNO (recog_data.operand[0])) += frequency; 1100 } 1101 1102 return PREV_INSN (newinsn); 1103 } 1104 1105 record_operand_costs (insn, op_costs, reg_pref); 1106 1107 /* Now add the cost for each operand to the total costs for 1108 its register. */ 1109 1110 for (i = 0; i < recog_data.n_operands; i++) 1111 if (GET_CODE (recog_data.operand[i]) == REG 1112 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) 1113 { 1114 int regno = REGNO (recog_data.operand[i]); 1115 struct costs *p = &costs[regno], *q = &op_costs[i]; 1116 1117 p->mem_cost += q->mem_cost * frequency; 1118 for (j = 0; j < N_REG_CLASSES; j++) 1119 p->cost[j] += q->cost[j] * frequency; 1120 } 1121 1122 return insn; 1123} 1124 1125/* Initialize information about which register classes can be used for 1126 pseudos that are auto-incremented or auto-decremented. */ 1127 1128static void 1129init_reg_autoinc (void) 1130{ 1131#ifdef FORBIDDEN_INC_DEC_CLASSES 1132 int i; 1133 1134 for (i = 0; i < N_REG_CLASSES; i++) 1135 { 1136 rtx r = gen_rtx_raw_REG (VOIDmode, 0); 1137 enum machine_mode m; 1138 int j; 1139 1140 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 1141 if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 1142 { 1143 REGNO (r) = j; 1144 1145 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; 1146 m = (enum machine_mode) ((int) m + 1)) 1147 if (HARD_REGNO_MODE_OK (j, m)) 1148 { 1149 PUT_MODE (r, m); 1150 1151 /* If a register is not directly suitable for an 1152 auto-increment or decrement addressing mode and 1153 requires secondary reloads, disallow its class from 1154 being used in such addresses. */ 1155 1156 if ((0 1157#ifdef SECONDARY_RELOAD_CLASS 1158 || (SECONDARY_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) 1159 != NO_REGS) 1160#else 1161#ifdef SECONDARY_INPUT_RELOAD_CLASS 1162 || (SECONDARY_INPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) 1163 != NO_REGS) 1164#endif 1165#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1166 || (SECONDARY_OUTPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) 1167 != NO_REGS) 1168#endif 1169#endif 1170 ) 1171 && ! auto_inc_dec_reg_p (r, m)) 1172 forbidden_inc_dec_class[i] = 1; 1173 } 1174 } 1175 } 1176#endif /* FORBIDDEN_INC_DEC_CLASSES */ 1177} 1178 1179/* This is a pass of the compiler that scans all instructions 1180 and calculates the preferred class for each pseudo-register. 1181 This information can be accessed later by calling `reg_preferred_class'. 1182 This pass comes just before local register allocation. */ 1183 1184void 1185regclass (rtx f, int nregs, FILE *dump) 1186{ 1187 rtx insn; 1188 int i; 1189 int pass; 1190 1191 init_recog (); 1192 1193 costs = xmalloc (nregs * sizeof (struct costs)); 1194 1195#ifdef FORBIDDEN_INC_DEC_CLASSES 1196 1197 in_inc_dec = xmalloc (nregs); 1198 1199#endif /* FORBIDDEN_INC_DEC_CLASSES */ 1200 1201 /* Normally we scan the insns once and determine the best class to use for 1202 each register. However, if -fexpensive_optimizations are on, we do so 1203 twice, the second time using the tentative best classes to guide the 1204 selection. */ 1205 1206 for (pass = 0; pass <= flag_expensive_optimizations; pass++) 1207 { 1208 basic_block bb; 1209 1210 if (dump) 1211 fprintf (dump, "\n\nPass %i\n\n",pass); 1212 /* Zero out our accumulation of the cost of each class for each reg. */ 1213 1214 memset (costs, 0, nregs * sizeof (struct costs)); 1215 1216#ifdef FORBIDDEN_INC_DEC_CLASSES 1217 memset (in_inc_dec, 0, nregs); 1218#endif 1219 1220 /* Scan the instructions and record each time it would 1221 save code to put a certain register in a certain class. */ 1222 1223 if (!optimize) 1224 { 1225 frequency = REG_FREQ_MAX; 1226 for (insn = f; insn; insn = NEXT_INSN (insn)) 1227 insn = scan_one_insn (insn, pass); 1228 } 1229 else 1230 FOR_EACH_BB (bb) 1231 { 1232 /* Show that an insn inside a loop is likely to be executed three 1233 times more than insns outside a loop. This is much more 1234 aggressive than the assumptions made elsewhere and is being 1235 tried as an experiment. */ 1236 frequency = REG_FREQ_FROM_BB (bb); 1237 for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn)) 1238 { 1239 insn = scan_one_insn (insn, pass); 1240 if (insn == BB_END (bb)) 1241 break; 1242 } 1243 } 1244 1245 /* Now for each register look at how desirable each class is 1246 and find which class is preferred. Store that in 1247 `prefclass'. Record in `altclass' the largest register 1248 class any of whose registers is better than memory. */ 1249 1250 if (pass == 0) 1251 reg_pref = reg_pref_buffer; 1252 1253 if (dump) 1254 { 1255 dump_regclass (dump); 1256 fprintf (dump,"\n"); 1257 } 1258 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) 1259 { 1260 int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; 1261 enum reg_class best = ALL_REGS, alt = NO_REGS; 1262 /* This is an enum reg_class, but we call it an int 1263 to save lots of casts. */ 1264 int class; 1265 struct costs *p = &costs[i]; 1266 1267 /* In non-optimizing compilation REG_N_REFS is not initialized 1268 yet. */ 1269 if (optimize && !REG_N_REFS (i) && !REG_N_SETS (i)) 1270 continue; 1271 1272 for (class = (int) ALL_REGS - 1; class > 0; class--) 1273 { 1274 /* Ignore classes that are too small for this operand or 1275 invalid for an operand that was auto-incremented. */ 1276 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)] 1277#ifdef FORBIDDEN_INC_DEC_CLASSES 1278 || (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1279#endif 1280#ifdef CANNOT_CHANGE_MODE_CLASS 1281 || invalid_mode_change_p (i, (enum reg_class) class, 1282 PSEUDO_REGNO_MODE (i)) 1283#endif 1284 ) 1285 ; 1286 else if (p->cost[class] < best_cost) 1287 { 1288 best_cost = p->cost[class]; 1289 best = (enum reg_class) class; 1290 } 1291 else if (p->cost[class] == best_cost) 1292 best = reg_class_subunion[(int) best][class]; 1293 } 1294 1295 /* Record the alternate register class; i.e., a class for which 1296 every register in it is better than using memory. If adding a 1297 class would make a smaller class (i.e., no union of just those 1298 classes exists), skip that class. The major unions of classes 1299 should be provided as a register class. Don't do this if we 1300 will be doing it again later. */ 1301 1302 if ((pass == 1 || dump) || ! flag_expensive_optimizations) 1303 for (class = 0; class < N_REG_CLASSES; class++) 1304 if (p->cost[class] < p->mem_cost 1305 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] 1306 > reg_class_size[(int) alt]) 1307#ifdef FORBIDDEN_INC_DEC_CLASSES 1308 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1309#endif 1310#ifdef CANNOT_CHANGE_MODE_CLASS 1311 && ! invalid_mode_change_p (i, (enum reg_class) class, 1312 PSEUDO_REGNO_MODE (i)) 1313#endif 1314 ) 1315 alt = reg_class_subunion[(int) alt][class]; 1316 1317 /* If we don't add any classes, nothing to try. */ 1318 if (alt == best) 1319 alt = NO_REGS; 1320 1321 if (dump 1322 && (reg_pref[i].prefclass != (int) best 1323 || reg_pref[i].altclass != (int) alt)) 1324 { 1325 static const char *const reg_class_names[] = REG_CLASS_NAMES; 1326 fprintf (dump, " Register %i", i); 1327 if (alt == ALL_REGS || best == ALL_REGS) 1328 fprintf (dump, " pref %s\n", reg_class_names[(int) best]); 1329 else if (alt == NO_REGS) 1330 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]); 1331 else 1332 fprintf (dump, " pref %s, else %s\n", 1333 reg_class_names[(int) best], 1334 reg_class_names[(int) alt]); 1335 } 1336 1337 /* We cast to (int) because (char) hits bugs in some compilers. */ 1338 reg_pref[i].prefclass = (int) best; 1339 reg_pref[i].altclass = (int) alt; 1340 } 1341 } 1342 1343#ifdef FORBIDDEN_INC_DEC_CLASSES 1344 free (in_inc_dec); 1345#endif 1346 free (costs); 1347} 1348 1349/* Record the cost of using memory or registers of various classes for 1350 the operands in INSN. 1351 1352 N_ALTS is the number of alternatives. 1353 1354 N_OPS is the number of operands. 1355 1356 OPS is an array of the operands. 1357 1358 MODES are the modes of the operands, in case any are VOIDmode. 1359 1360 CONSTRAINTS are the constraints to use for the operands. This array 1361 is modified by this procedure. 1362 1363 This procedure works alternative by alternative. For each alternative 1364 we assume that we will be able to allocate all pseudos to their ideal 1365 register class and calculate the cost of using that alternative. Then 1366 we compute for each operand that is a pseudo-register, the cost of 1367 having the pseudo allocated to each register class and using it in that 1368 alternative. To this cost is added the cost of the alternative. 1369 1370 The cost of each class for this insn is its lowest cost among all the 1371 alternatives. */ 1372 1373static void 1374record_reg_classes (int n_alts, int n_ops, rtx *ops, 1375 enum machine_mode *modes, const char **constraints, 1376 rtx insn, struct costs *op_costs, 1377 struct reg_pref *reg_pref) 1378{ 1379 int alt; 1380 int i, j; 1381 rtx set; 1382 1383 /* Process each alternative, each time minimizing an operand's cost with 1384 the cost for each operand in that alternative. */ 1385 1386 for (alt = 0; alt < n_alts; alt++) 1387 { 1388 struct costs this_op_costs[MAX_RECOG_OPERANDS]; 1389 int alt_fail = 0; 1390 int alt_cost = 0; 1391 enum reg_class classes[MAX_RECOG_OPERANDS]; 1392 int allows_mem[MAX_RECOG_OPERANDS]; 1393 int class; 1394 1395 for (i = 0; i < n_ops; i++) 1396 { 1397 const char *p = constraints[i]; 1398 rtx op = ops[i]; 1399 enum machine_mode mode = modes[i]; 1400 int allows_addr = 0; 1401 int win = 0; 1402 unsigned char c; 1403 1404 /* Initially show we know nothing about the register class. */ 1405 classes[i] = NO_REGS; 1406 allows_mem[i] = 0; 1407 1408 /* If this operand has no constraints at all, we can conclude 1409 nothing about it since anything is valid. */ 1410 1411 if (*p == 0) 1412 { 1413 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1414 memset (&this_op_costs[i], 0, sizeof this_op_costs[i]); 1415 1416 continue; 1417 } 1418 1419 /* If this alternative is only relevant when this operand 1420 matches a previous operand, we do different things depending 1421 on whether this operand is a pseudo-reg or not. We must process 1422 any modifiers for the operand before we can make this test. */ 1423 1424 while (*p == '%' || *p == '=' || *p == '+' || *p == '&') 1425 p++; 1426 1427 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) 1428 { 1429 /* Copy class and whether memory is allowed from the matching 1430 alternative. Then perform any needed cost computations 1431 and/or adjustments. */ 1432 j = p[0] - '0'; 1433 classes[i] = classes[j]; 1434 allows_mem[i] = allows_mem[j]; 1435 1436 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) 1437 { 1438 /* If this matches the other operand, we have no added 1439 cost and we win. */ 1440 if (rtx_equal_p (ops[j], op)) 1441 win = 1; 1442 1443 /* If we can put the other operand into a register, add to 1444 the cost of this alternative the cost to copy this 1445 operand to the register used for the other operand. */ 1446 1447 else if (classes[j] != NO_REGS) 1448 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; 1449 } 1450 else if (GET_CODE (ops[j]) != REG 1451 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) 1452 { 1453 /* This op is a pseudo but the one it matches is not. */ 1454 1455 /* If we can't put the other operand into a register, this 1456 alternative can't be used. */ 1457 1458 if (classes[j] == NO_REGS) 1459 alt_fail = 1; 1460 1461 /* Otherwise, add to the cost of this alternative the cost 1462 to copy the other operand to the register used for this 1463 operand. */ 1464 1465 else 1466 alt_cost += copy_cost (ops[j], mode, classes[j], 1); 1467 } 1468 else 1469 { 1470 /* The costs of this operand are not the same as the other 1471 operand since move costs are not symmetric. Moreover, 1472 if we cannot tie them, this alternative needs to do a 1473 copy, which is one instruction. */ 1474 1475 struct costs *pp = &this_op_costs[i]; 1476 1477 for (class = 0; class < N_REG_CLASSES; class++) 1478 pp->cost[class] 1479 = ((recog_data.operand_type[i] != OP_OUT 1480 ? may_move_in_cost[mode][class][(int) classes[i]] 1481 : 0) 1482 + (recog_data.operand_type[i] != OP_IN 1483 ? may_move_out_cost[mode][(int) classes[i]][class] 1484 : 0)); 1485 1486 /* If the alternative actually allows memory, make things 1487 a bit cheaper since we won't need an extra insn to 1488 load it. */ 1489 1490 pp->mem_cost 1491 = ((recog_data.operand_type[i] != OP_IN 1492 ? MEMORY_MOVE_COST (mode, classes[i], 0) 1493 : 0) 1494 + (recog_data.operand_type[i] != OP_OUT 1495 ? MEMORY_MOVE_COST (mode, classes[i], 1) 1496 : 0) - allows_mem[i]); 1497 1498 /* If we have assigned a class to this register in our 1499 first pass, add a cost to this alternative corresponding 1500 to what we would add if this register were not in the 1501 appropriate class. */ 1502 1503 if (reg_pref) 1504 alt_cost 1505 += (may_move_in_cost[mode] 1506 [(unsigned char) reg_pref[REGNO (op)].prefclass] 1507 [(int) classes[i]]); 1508 1509 if (REGNO (ops[i]) != REGNO (ops[j]) 1510 && ! find_reg_note (insn, REG_DEAD, op)) 1511 alt_cost += 2; 1512 1513 /* This is in place of ordinary cost computation 1514 for this operand, so skip to the end of the 1515 alternative (should be just one character). */ 1516 while (*p && *p++ != ',') 1517 ; 1518 1519 constraints[i] = p; 1520 continue; 1521 } 1522 } 1523 1524 /* Scan all the constraint letters. See if the operand matches 1525 any of the constraints. Collect the valid register classes 1526 and see if this operand accepts memory. */ 1527 1528 while ((c = *p)) 1529 { 1530 switch (c) 1531 { 1532 case ',': 1533 break; 1534 case '*': 1535 /* Ignore the next letter for this pass. */ 1536 c = *++p; 1537 break; 1538 1539 case '?': 1540 alt_cost += 2; 1541 case '!': case '#': case '&': 1542 case '0': case '1': case '2': case '3': case '4': 1543 case '5': case '6': case '7': case '8': case '9': 1544 break; 1545 1546 case 'p': 1547 allows_addr = 1; 1548 win = address_operand (op, GET_MODE (op)); 1549 /* We know this operand is an address, so we want it to be 1550 allocated to a register that can be the base of an 1551 address, ie BASE_REG_CLASS. */ 1552 classes[i] 1553 = reg_class_subunion[(int) classes[i]] 1554 [(int) MODE_BASE_REG_CLASS (VOIDmode)]; 1555 break; 1556 1557 case 'm': case 'o': case 'V': 1558 /* It doesn't seem worth distinguishing between offsettable 1559 and non-offsettable addresses here. */ 1560 allows_mem[i] = 1; 1561 if (GET_CODE (op) == MEM) 1562 win = 1; 1563 break; 1564 1565 case '<': 1566 if (GET_CODE (op) == MEM 1567 && (GET_CODE (XEXP (op, 0)) == PRE_DEC 1568 || GET_CODE (XEXP (op, 0)) == POST_DEC)) 1569 win = 1; 1570 break; 1571 1572 case '>': 1573 if (GET_CODE (op) == MEM 1574 && (GET_CODE (XEXP (op, 0)) == PRE_INC 1575 || GET_CODE (XEXP (op, 0)) == POST_INC)) 1576 win = 1; 1577 break; 1578 1579 case 'E': 1580 case 'F': 1581 if (GET_CODE (op) == CONST_DOUBLE 1582 || (GET_CODE (op) == CONST_VECTOR 1583 && (GET_MODE_CLASS (GET_MODE (op)) 1584 == MODE_VECTOR_FLOAT))) 1585 win = 1; 1586 break; 1587 1588 case 'G': 1589 case 'H': 1590 if (GET_CODE (op) == CONST_DOUBLE 1591 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) 1592 win = 1; 1593 break; 1594 1595 case 's': 1596 if (GET_CODE (op) == CONST_INT 1597 || (GET_CODE (op) == CONST_DOUBLE 1598 && GET_MODE (op) == VOIDmode)) 1599 break; 1600 case 'i': 1601 if (CONSTANT_P (op) 1602#ifdef LEGITIMATE_PIC_OPERAND_P 1603 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1604#endif 1605 ) 1606 win = 1; 1607 break; 1608 1609 case 'n': 1610 if (GET_CODE (op) == CONST_INT 1611 || (GET_CODE (op) == CONST_DOUBLE 1612 && GET_MODE (op) == VOIDmode)) 1613 win = 1; 1614 break; 1615 1616 case 'I': 1617 case 'J': 1618 case 'K': 1619 case 'L': 1620 case 'M': 1621 case 'N': 1622 case 'O': 1623 case 'P': 1624 if (GET_CODE (op) == CONST_INT 1625 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) 1626 win = 1; 1627 break; 1628 1629 case 'X': 1630 win = 1; 1631 break; 1632 1633 case 'g': 1634 if (GET_CODE (op) == MEM 1635 || (CONSTANT_P (op) 1636#ifdef LEGITIMATE_PIC_OPERAND_P 1637 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1638#endif 1639 )) 1640 win = 1; 1641 allows_mem[i] = 1; 1642 case 'r': 1643 classes[i] 1644 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; 1645 break; 1646 1647 default: 1648 if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS) 1649 classes[i] 1650 = reg_class_subunion[(int) classes[i]] 1651 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]; 1652#ifdef EXTRA_CONSTRAINT_STR 1653 else if (EXTRA_CONSTRAINT_STR (op, c, p)) 1654 win = 1; 1655 1656 if (EXTRA_MEMORY_CONSTRAINT (c, p)) 1657 { 1658 /* Every MEM can be reloaded to fit. */ 1659 allows_mem[i] = 1; 1660 if (GET_CODE (op) == MEM) 1661 win = 1; 1662 } 1663 if (EXTRA_ADDRESS_CONSTRAINT (c, p)) 1664 { 1665 /* Every address can be reloaded to fit. */ 1666 allows_addr = 1; 1667 if (address_operand (op, GET_MODE (op))) 1668 win = 1; 1669 /* We know this operand is an address, so we want it to 1670 be allocated to a register that can be the base of an 1671 address, ie BASE_REG_CLASS. */ 1672 classes[i] 1673 = reg_class_subunion[(int) classes[i]] 1674 [(int) MODE_BASE_REG_CLASS (VOIDmode)]; 1675 } 1676#endif 1677 break; 1678 } 1679 p += CONSTRAINT_LEN (c, p); 1680 if (c == ',') 1681 break; 1682 } 1683 1684 constraints[i] = p; 1685 1686 /* How we account for this operand now depends on whether it is a 1687 pseudo register or not. If it is, we first check if any 1688 register classes are valid. If not, we ignore this alternative, 1689 since we want to assume that all pseudos get allocated for 1690 register preferencing. If some register class is valid, compute 1691 the costs of moving the pseudo into that class. */ 1692 1693 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1694 { 1695 if (classes[i] == NO_REGS) 1696 { 1697 /* We must always fail if the operand is a REG, but 1698 we did not find a suitable class. 1699 1700 Otherwise we may perform an uninitialized read 1701 from this_op_costs after the `continue' statement 1702 below. */ 1703 alt_fail = 1; 1704 } 1705 else 1706 { 1707 struct costs *pp = &this_op_costs[i]; 1708 1709 for (class = 0; class < N_REG_CLASSES; class++) 1710 pp->cost[class] 1711 = ((recog_data.operand_type[i] != OP_OUT 1712 ? may_move_in_cost[mode][class][(int) classes[i]] 1713 : 0) 1714 + (recog_data.operand_type[i] != OP_IN 1715 ? may_move_out_cost[mode][(int) classes[i]][class] 1716 : 0)); 1717 1718 /* If the alternative actually allows memory, make things 1719 a bit cheaper since we won't need an extra insn to 1720 load it. */ 1721 1722 pp->mem_cost 1723 = ((recog_data.operand_type[i] != OP_IN 1724 ? MEMORY_MOVE_COST (mode, classes[i], 0) 1725 : 0) 1726 + (recog_data.operand_type[i] != OP_OUT 1727 ? MEMORY_MOVE_COST (mode, classes[i], 1) 1728 : 0) - allows_mem[i]); 1729 1730 /* If we have assigned a class to this register in our 1731 first pass, add a cost to this alternative corresponding 1732 to what we would add if this register were not in the 1733 appropriate class. */ 1734 1735 if (reg_pref) 1736 alt_cost 1737 += (may_move_in_cost[mode] 1738 [(unsigned char) reg_pref[REGNO (op)].prefclass] 1739 [(int) classes[i]]); 1740 } 1741 } 1742 1743 /* Otherwise, if this alternative wins, either because we 1744 have already determined that or if we have a hard register of 1745 the proper class, there is no cost for this alternative. */ 1746 1747 else if (win 1748 || (GET_CODE (op) == REG 1749 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) 1750 ; 1751 1752 /* If registers are valid, the cost of this alternative includes 1753 copying the object to and/or from a register. */ 1754 1755 else if (classes[i] != NO_REGS) 1756 { 1757 if (recog_data.operand_type[i] != OP_OUT) 1758 alt_cost += copy_cost (op, mode, classes[i], 1); 1759 1760 if (recog_data.operand_type[i] != OP_IN) 1761 alt_cost += copy_cost (op, mode, classes[i], 0); 1762 } 1763 1764 /* The only other way this alternative can be used is if this is a 1765 constant that could be placed into memory. */ 1766 1767 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) 1768 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); 1769 else 1770 alt_fail = 1; 1771 } 1772 1773 if (alt_fail) 1774 continue; 1775 1776 /* Finally, update the costs with the information we've calculated 1777 about this alternative. */ 1778 1779 for (i = 0; i < n_ops; i++) 1780 if (GET_CODE (ops[i]) == REG 1781 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1782 { 1783 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; 1784 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); 1785 1786 pp->mem_cost = MIN (pp->mem_cost, 1787 (qq->mem_cost + alt_cost) * scale); 1788 1789 for (class = 0; class < N_REG_CLASSES; class++) 1790 pp->cost[class] = MIN (pp->cost[class], 1791 (qq->cost[class] + alt_cost) * scale); 1792 } 1793 } 1794 1795 /* If this insn is a single set copying operand 1 to operand 0 1796 and one operand is a pseudo with the other a hard reg or a pseudo 1797 that prefers a register that is in its own register class then 1798 we may want to adjust the cost of that register class to -1. 1799 1800 Avoid the adjustment if the source does not die to avoid stressing of 1801 register allocator by preferrencing two colliding registers into single 1802 class. 1803 1804 Also avoid the adjustment if a copy between registers of the class 1805 is expensive (ten times the cost of a default copy is considered 1806 arbitrarily expensive). This avoids losing when the preferred class 1807 is very expensive as the source of a copy instruction. */ 1808 1809 if ((set = single_set (insn)) != 0 1810 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) 1811 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG 1812 && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) 1813 for (i = 0; i <= 1; i++) 1814 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1815 { 1816 unsigned int regno = REGNO (ops[!i]); 1817 enum machine_mode mode = GET_MODE (ops[!i]); 1818 int class; 1819 unsigned int nr; 1820 1821 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0) 1822 { 1823 enum reg_class pref = reg_pref[regno].prefclass; 1824 1825 if ((reg_class_size[(unsigned char) pref] 1826 == (unsigned) CLASS_MAX_NREGS (pref, mode)) 1827 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2) 1828 op_costs[i].cost[(unsigned char) pref] = -1; 1829 } 1830 else if (regno < FIRST_PSEUDO_REGISTER) 1831 for (class = 0; class < N_REG_CLASSES; class++) 1832 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) 1833 && reg_class_size[class] == (unsigned) CLASS_MAX_NREGS (class, mode)) 1834 { 1835 if (reg_class_size[class] == 1) 1836 op_costs[i].cost[class] = -1; 1837 else 1838 { 1839 for (nr = 0; nr < (unsigned) HARD_REGNO_NREGS (regno, mode); nr++) 1840 { 1841 if (! TEST_HARD_REG_BIT (reg_class_contents[class], 1842 regno + nr)) 1843 break; 1844 } 1845 1846 if (nr == (unsigned) HARD_REGNO_NREGS (regno,mode)) 1847 op_costs[i].cost[class] = -1; 1848 } 1849 } 1850 } 1851} 1852 1853/* Compute the cost of loading X into (if TO_P is nonzero) or from (if 1854 TO_P is zero) a register of class CLASS in mode MODE. 1855 1856 X must not be a pseudo. */ 1857 1858static int 1859copy_cost (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED, 1860 enum reg_class class, int to_p ATTRIBUTE_UNUSED) 1861{ 1862#ifdef HAVE_SECONDARY_RELOADS 1863 enum reg_class secondary_class = NO_REGS; 1864#endif 1865 1866 /* If X is a SCRATCH, there is actually nothing to move since we are 1867 assuming optimal allocation. */ 1868 1869 if (GET_CODE (x) == SCRATCH) 1870 return 0; 1871 1872 /* Get the class we will actually use for a reload. */ 1873 class = PREFERRED_RELOAD_CLASS (x, class); 1874 1875#ifdef HAVE_SECONDARY_RELOADS 1876 /* If we need a secondary reload (we assume here that we are using 1877 the secondary reload as an intermediate, not a scratch register), the 1878 cost is that to load the input into the intermediate register, then 1879 to copy them. We use a special value of TO_P to avoid recursion. */ 1880 1881#ifdef SECONDARY_INPUT_RELOAD_CLASS 1882 if (to_p == 1) 1883 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); 1884#endif 1885 1886#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1887 if (! to_p) 1888 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); 1889#endif 1890 1891 if (secondary_class != NO_REGS) 1892 return (move_cost[mode][(int) secondary_class][(int) class] 1893 + copy_cost (x, mode, secondary_class, 2)); 1894#endif /* HAVE_SECONDARY_RELOADS */ 1895 1896 /* For memory, use the memory move cost, for (hard) registers, use the 1897 cost to move between the register classes, and use 2 for everything 1898 else (constants). */ 1899 1900 if (GET_CODE (x) == MEM || class == NO_REGS) 1901 return MEMORY_MOVE_COST (mode, class, to_p); 1902 1903 else if (GET_CODE (x) == REG) 1904 return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; 1905 1906 else 1907 /* If this is a constant, we may eventually want to call rtx_cost here. */ 1908 return COSTS_N_INSNS (1); 1909} 1910 1911/* Record the pseudo registers we must reload into hard registers 1912 in a subexpression of a memory address, X. 1913 1914 CLASS is the class that the register needs to be in and is either 1915 BASE_REG_CLASS or INDEX_REG_CLASS. 1916 1917 SCALE is twice the amount to multiply the cost by (it is twice so we 1918 can represent half-cost adjustments). */ 1919 1920static void 1921record_address_regs (rtx x, enum reg_class class, int scale) 1922{ 1923 enum rtx_code code = GET_CODE (x); 1924 1925 switch (code) 1926 { 1927 case CONST_INT: 1928 case CONST: 1929 case CC0: 1930 case PC: 1931 case SYMBOL_REF: 1932 case LABEL_REF: 1933 return; 1934 1935 case PLUS: 1936 /* When we have an address that is a sum, 1937 we must determine whether registers are "base" or "index" regs. 1938 If there is a sum of two registers, we must choose one to be 1939 the "base". Luckily, we can use the REG_POINTER to make a good 1940 choice most of the time. We only need to do this on machines 1941 that can have two registers in an address and where the base 1942 and index register classes are different. 1943 1944 ??? This code used to set REGNO_POINTER_FLAG in some cases, but 1945 that seems bogus since it should only be set when we are sure 1946 the register is being used as a pointer. */ 1947 1948 { 1949 rtx arg0 = XEXP (x, 0); 1950 rtx arg1 = XEXP (x, 1); 1951 enum rtx_code code0 = GET_CODE (arg0); 1952 enum rtx_code code1 = GET_CODE (arg1); 1953 1954 /* Look inside subregs. */ 1955 if (code0 == SUBREG) 1956 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); 1957 if (code1 == SUBREG) 1958 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); 1959 1960 /* If this machine only allows one register per address, it must 1961 be in the first operand. */ 1962 1963 if (MAX_REGS_PER_ADDRESS == 1) 1964 record_address_regs (arg0, class, scale); 1965 1966 /* If index and base registers are the same on this machine, just 1967 record registers in any non-constant operands. We assume here, 1968 as well as in the tests below, that all addresses are in 1969 canonical form. */ 1970 1971 else if (INDEX_REG_CLASS == MODE_BASE_REG_CLASS (VOIDmode)) 1972 { 1973 record_address_regs (arg0, class, scale); 1974 if (! CONSTANT_P (arg1)) 1975 record_address_regs (arg1, class, scale); 1976 } 1977 1978 /* If the second operand is a constant integer, it doesn't change 1979 what class the first operand must be. */ 1980 1981 else if (code1 == CONST_INT || code1 == CONST_DOUBLE) 1982 record_address_regs (arg0, class, scale); 1983 1984 /* If the second operand is a symbolic constant, the first operand 1985 must be an index register. */ 1986 1987 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) 1988 record_address_regs (arg0, INDEX_REG_CLASS, scale); 1989 1990 /* If both operands are registers but one is already a hard register 1991 of index or base class, give the other the class that the hard 1992 register is not. */ 1993 1994#ifdef REG_OK_FOR_BASE_P 1995 else if (code0 == REG && code1 == REG 1996 && REGNO (arg0) < FIRST_PSEUDO_REGISTER 1997 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) 1998 record_address_regs (arg1, 1999 REG_OK_FOR_BASE_P (arg0) 2000 ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), 2001 scale); 2002 else if (code0 == REG && code1 == REG 2003 && REGNO (arg1) < FIRST_PSEUDO_REGISTER 2004 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) 2005 record_address_regs (arg0, 2006 REG_OK_FOR_BASE_P (arg1) 2007 ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), 2008 scale); 2009#endif 2010 2011 /* If one operand is known to be a pointer, it must be the base 2012 with the other operand the index. Likewise if the other operand 2013 is a MULT. */ 2014 2015 else if ((code0 == REG && REG_POINTER (arg0)) 2016 || code1 == MULT) 2017 { 2018 record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), scale); 2019 record_address_regs (arg1, INDEX_REG_CLASS, scale); 2020 } 2021 else if ((code1 == REG && REG_POINTER (arg1)) 2022 || code0 == MULT) 2023 { 2024 record_address_regs (arg0, INDEX_REG_CLASS, scale); 2025 record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), scale); 2026 } 2027 2028 /* Otherwise, count equal chances that each might be a base 2029 or index register. This case should be rare. */ 2030 2031 else 2032 { 2033 record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), 2034 scale / 2); 2035 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); 2036 record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), 2037 scale / 2); 2038 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); 2039 } 2040 } 2041 break; 2042 2043 /* Double the importance of a pseudo register that is incremented 2044 or decremented, since it would take two extra insns 2045 if it ends up in the wrong place. */ 2046 case POST_MODIFY: 2047 case PRE_MODIFY: 2048 record_address_regs (XEXP (x, 0), MODE_BASE_REG_CLASS (VOIDmode), 2049 2 * scale); 2050 if (REG_P (XEXP (XEXP (x, 1), 1))) 2051 record_address_regs (XEXP (XEXP (x, 1), 1), 2052 INDEX_REG_CLASS, 2 * scale); 2053 break; 2054 2055 case POST_INC: 2056 case PRE_INC: 2057 case POST_DEC: 2058 case PRE_DEC: 2059 /* Double the importance of a pseudo register that is incremented 2060 or decremented, since it would take two extra insns 2061 if it ends up in the wrong place. If the operand is a pseudo, 2062 show it is being used in an INC_DEC context. */ 2063 2064#ifdef FORBIDDEN_INC_DEC_CLASSES 2065 if (GET_CODE (XEXP (x, 0)) == REG 2066 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) 2067 in_inc_dec[REGNO (XEXP (x, 0))] = 1; 2068#endif 2069 2070 record_address_regs (XEXP (x, 0), class, 2 * scale); 2071 break; 2072 2073 case REG: 2074 { 2075 struct costs *pp = &costs[REGNO (x)]; 2076 int i; 2077 2078 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; 2079 2080 for (i = 0; i < N_REG_CLASSES; i++) 2081 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2; 2082 } 2083 break; 2084 2085 default: 2086 { 2087 const char *fmt = GET_RTX_FORMAT (code); 2088 int i; 2089 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2090 if (fmt[i] == 'e') 2091 record_address_regs (XEXP (x, i), class, scale); 2092 } 2093 } 2094} 2095 2096#ifdef FORBIDDEN_INC_DEC_CLASSES 2097 2098/* Return 1 if REG is valid as an auto-increment memory reference 2099 to an object of MODE. */ 2100 2101static int 2102auto_inc_dec_reg_p (rtx reg, enum machine_mode mode) 2103{ 2104 if (HAVE_POST_INCREMENT 2105 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) 2106 return 1; 2107 2108 if (HAVE_POST_DECREMENT 2109 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) 2110 return 1; 2111 2112 if (HAVE_PRE_INCREMENT 2113 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) 2114 return 1; 2115 2116 if (HAVE_PRE_DECREMENT 2117 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) 2118 return 1; 2119 2120 return 0; 2121} 2122#endif 2123 2124static short *renumber; 2125static size_t regno_allocated; 2126static unsigned int reg_n_max; 2127 2128/* Allocate enough space to hold NUM_REGS registers for the tables used for 2129 reg_scan and flow_analysis that are indexed by the register number. If 2130 NEW_P is nonzero, initialize all of the registers, otherwise only 2131 initialize the new registers allocated. The same table is kept from 2132 function to function, only reallocating it when we need more room. If 2133 RENUMBER_P is nonzero, allocate the reg_renumber array also. */ 2134 2135void 2136allocate_reg_info (size_t num_regs, int new_p, int renumber_p) 2137{ 2138 size_t size_info; 2139 size_t size_renumber; 2140 size_t min = (new_p) ? 0 : reg_n_max; 2141 struct reg_info_data *reg_data; 2142 2143 if (num_regs > regno_allocated) 2144 { 2145 size_t old_allocated = regno_allocated; 2146 2147 regno_allocated = num_regs + (num_regs / 20); /* Add some slop space. */ 2148 size_renumber = regno_allocated * sizeof (short); 2149 2150 if (!reg_n_info) 2151 { 2152 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); 2153 renumber = xmalloc (size_renumber); 2154 reg_pref_buffer = xmalloc (regno_allocated 2155 * sizeof (struct reg_pref)); 2156 } 2157 2158 else 2159 { 2160 VARRAY_GROW (reg_n_info, regno_allocated); 2161 2162 if (new_p) /* If we're zapping everything, no need to realloc. */ 2163 { 2164 free ((char *) renumber); 2165 free ((char *) reg_pref); 2166 renumber = xmalloc (size_renumber); 2167 reg_pref_buffer = xmalloc (regno_allocated 2168 * sizeof (struct reg_pref)); 2169 } 2170 2171 else 2172 { 2173 renumber = xrealloc (renumber, size_renumber); 2174 reg_pref_buffer = xrealloc (reg_pref_buffer, 2175 regno_allocated 2176 * sizeof (struct reg_pref)); 2177 } 2178 } 2179 2180 size_info = (regno_allocated - old_allocated) * sizeof (reg_info) 2181 + sizeof (struct reg_info_data) - sizeof (reg_info); 2182 reg_data = xcalloc (size_info, 1); 2183 reg_data->min_index = old_allocated; 2184 reg_data->max_index = regno_allocated - 1; 2185 reg_data->next = reg_info_head; 2186 reg_info_head = reg_data; 2187 } 2188 2189 reg_n_max = num_regs; 2190 if (min < num_regs) 2191 { 2192 /* Loop through each of the segments allocated for the actual 2193 reg_info pages, and set up the pointers, zero the pages, etc. */ 2194 for (reg_data = reg_info_head; 2195 reg_data && reg_data->max_index >= min; 2196 reg_data = reg_data->next) 2197 { 2198 size_t min_index = reg_data->min_index; 2199 size_t max_index = reg_data->max_index; 2200 size_t max = MIN (max_index, num_regs); 2201 size_t local_min = min - min_index; 2202 size_t i; 2203 2204 if (reg_data->min_index > num_regs) 2205 continue; 2206 2207 if (min < min_index) 2208 local_min = 0; 2209 if (!reg_data->used_p) /* page just allocated with calloc */ 2210 reg_data->used_p = 1; /* no need to zero */ 2211 else 2212 memset (®_data->data[local_min], 0, 2213 sizeof (reg_info) * (max - min_index - local_min + 1)); 2214 2215 for (i = min_index+local_min; i <= max; i++) 2216 { 2217 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; 2218 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; 2219 renumber[i] = -1; 2220 reg_pref_buffer[i].prefclass = (char) NO_REGS; 2221 reg_pref_buffer[i].altclass = (char) NO_REGS; 2222 } 2223 } 2224 } 2225 2226 /* If {pref,alt}class have already been allocated, update the pointers to 2227 the newly realloced ones. */ 2228 if (reg_pref) 2229 reg_pref = reg_pref_buffer; 2230 2231 if (renumber_p) 2232 reg_renumber = renumber; 2233 2234 /* Tell the regset code about the new number of registers. */ 2235 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); 2236} 2237 2238/* Free up the space allocated by allocate_reg_info. */ 2239void 2240free_reg_info (void) 2241{ 2242 if (reg_n_info) 2243 { 2244 struct reg_info_data *reg_data; 2245 struct reg_info_data *reg_next; 2246 2247 VARRAY_FREE (reg_n_info); 2248 for (reg_data = reg_info_head; reg_data; reg_data = reg_next) 2249 { 2250 reg_next = reg_data->next; 2251 free ((char *) reg_data); 2252 } 2253 2254 free (reg_pref_buffer); 2255 reg_pref_buffer = (struct reg_pref *) 0; 2256 reg_info_head = (struct reg_info_data *) 0; 2257 renumber = (short *) 0; 2258 } 2259 regno_allocated = 0; 2260 reg_n_max = 0; 2261} 2262 2263/* This is the `regscan' pass of the compiler, run just before cse 2264 and again just before loop. 2265 2266 It finds the first and last use of each pseudo-register 2267 and records them in the vectors regno_first_uid, regno_last_uid 2268 and counts the number of sets in the vector reg_n_sets. 2269 2270 REPEAT is nonzero the second time this is called. */ 2271 2272/* Maximum number of parallel sets and clobbers in any insn in this fn. 2273 Always at least 3, since the combiner could put that many together 2274 and we want this to remain correct for all the remaining passes. 2275 This corresponds to the maximum number of times note_stores will call 2276 a function for any insn. */ 2277 2278int max_parallel; 2279 2280/* Used as a temporary to record the largest number of registers in 2281 PARALLEL in a SET_DEST. This is added to max_parallel. */ 2282 2283static int max_set_parallel; 2284 2285void 2286reg_scan (rtx f, unsigned int nregs, int repeat ATTRIBUTE_UNUSED) 2287{ 2288 rtx insn; 2289 2290 timevar_push (TV_REG_SCAN); 2291 2292 allocate_reg_info (nregs, TRUE, FALSE); 2293 max_parallel = 3; 2294 max_set_parallel = 0; 2295 2296 for (insn = f; insn; insn = NEXT_INSN (insn)) 2297 if (INSN_P (insn)) 2298 { 2299 rtx pat = PATTERN (insn); 2300 if (GET_CODE (pat) == PARALLEL 2301 && XVECLEN (pat, 0) > max_parallel) 2302 max_parallel = XVECLEN (pat, 0); 2303 reg_scan_mark_refs (pat, insn, 0, 0); 2304 2305 if (REG_NOTES (insn)) 2306 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); 2307 } 2308 2309 max_parallel += max_set_parallel; 2310 2311 timevar_pop (TV_REG_SCAN); 2312} 2313 2314/* Update 'regscan' information by looking at the insns 2315 from FIRST to LAST. Some new REGs have been created, 2316 and any REG with number greater than OLD_MAX_REGNO is 2317 such a REG. We only update information for those. */ 2318 2319void 2320reg_scan_update (rtx first, rtx last, unsigned int old_max_regno) 2321{ 2322 rtx insn; 2323 2324 allocate_reg_info (max_reg_num (), FALSE, FALSE); 2325 2326 for (insn = first; insn != last; insn = NEXT_INSN (insn)) 2327 if (INSN_P (insn)) 2328 { 2329 rtx pat = PATTERN (insn); 2330 if (GET_CODE (pat) == PARALLEL 2331 && XVECLEN (pat, 0) > max_parallel) 2332 max_parallel = XVECLEN (pat, 0); 2333 reg_scan_mark_refs (pat, insn, 0, old_max_regno); 2334 2335 if (REG_NOTES (insn)) 2336 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); 2337 } 2338} 2339 2340/* X is the expression to scan. INSN is the insn it appears in. 2341 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. 2342 We should only record information for REGs with numbers 2343 greater than or equal to MIN_REGNO. */ 2344 2345static void 2346reg_scan_mark_refs (rtx x, rtx insn, int note_flag, unsigned int min_regno) 2347{ 2348 enum rtx_code code; 2349 rtx dest; 2350 rtx note; 2351 2352 if (!x) 2353 return; 2354 code = GET_CODE (x); 2355 switch (code) 2356 { 2357 case CONST: 2358 case CONST_INT: 2359 case CONST_DOUBLE: 2360 case CONST_VECTOR: 2361 case CC0: 2362 case PC: 2363 case SYMBOL_REF: 2364 case LABEL_REF: 2365 case ADDR_VEC: 2366 case ADDR_DIFF_VEC: 2367 return; 2368 2369 case REG: 2370 { 2371 unsigned int regno = REGNO (x); 2372 2373 if (regno >= min_regno) 2374 { 2375 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); 2376 if (!note_flag) 2377 REGNO_LAST_UID (regno) = INSN_UID (insn); 2378 if (REGNO_FIRST_UID (regno) == 0) 2379 REGNO_FIRST_UID (regno) = INSN_UID (insn); 2380 /* If we are called by reg_scan_update() (indicated by min_regno 2381 being set), we also need to update the reference count. */ 2382 if (min_regno) 2383 REG_N_REFS (regno)++; 2384 } 2385 } 2386 break; 2387 2388 case EXPR_LIST: 2389 if (XEXP (x, 0)) 2390 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); 2391 if (XEXP (x, 1)) 2392 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); 2393 break; 2394 2395 case INSN_LIST: 2396 if (XEXP (x, 1)) 2397 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); 2398 break; 2399 2400 case CLOBBER: 2401 { 2402 rtx reg = XEXP (x, 0); 2403 if (REG_P (reg) 2404 && REGNO (reg) >= min_regno) 2405 { 2406 REG_N_SETS (REGNO (reg))++; 2407 REG_N_REFS (REGNO (reg))++; 2408 } 2409 else if (GET_CODE (reg) == MEM) 2410 reg_scan_mark_refs (XEXP (reg, 0), insn, note_flag, min_regno); 2411 } 2412 break; 2413 2414 case SET: 2415 /* Count a set of the destination if it is a register. */ 2416 for (dest = SET_DEST (x); 2417 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART 2418 || GET_CODE (dest) == ZERO_EXTEND; 2419 dest = XEXP (dest, 0)) 2420 ; 2421 2422 /* For a PARALLEL, record the number of things (less the usual one for a 2423 SET) that are set. */ 2424 if (GET_CODE (dest) == PARALLEL) 2425 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1); 2426 2427 if (GET_CODE (dest) == REG 2428 && REGNO (dest) >= min_regno) 2429 { 2430 REG_N_SETS (REGNO (dest))++; 2431 REG_N_REFS (REGNO (dest))++; 2432 } 2433 2434 /* If this is setting a pseudo from another pseudo or the sum of a 2435 pseudo and a constant integer and the other pseudo is known to be 2436 a pointer, set the destination to be a pointer as well. 2437 2438 Likewise if it is setting the destination from an address or from a 2439 value equivalent to an address or to the sum of an address and 2440 something else. 2441 2442 But don't do any of this if the pseudo corresponds to a user 2443 variable since it should have already been set as a pointer based 2444 on the type. */ 2445 2446 if (GET_CODE (SET_DEST (x)) == REG 2447 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER 2448 && REGNO (SET_DEST (x)) >= min_regno 2449 /* If the destination pseudo is set more than once, then other 2450 sets might not be to a pointer value (consider access to a 2451 union in two threads of control in the presence of global 2452 optimizations). So only set REG_POINTER on the destination 2453 pseudo if this is the only set of that pseudo. */ 2454 && REG_N_SETS (REGNO (SET_DEST (x))) == 1 2455 && ! REG_USERVAR_P (SET_DEST (x)) 2456 && ! REG_POINTER (SET_DEST (x)) 2457 && ((GET_CODE (SET_SRC (x)) == REG 2458 && REG_POINTER (SET_SRC (x))) 2459 || ((GET_CODE (SET_SRC (x)) == PLUS 2460 || GET_CODE (SET_SRC (x)) == LO_SUM) 2461 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 2462 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG 2463 && REG_POINTER (XEXP (SET_SRC (x), 0))) 2464 || GET_CODE (SET_SRC (x)) == CONST 2465 || GET_CODE (SET_SRC (x)) == SYMBOL_REF 2466 || GET_CODE (SET_SRC (x)) == LABEL_REF 2467 || (GET_CODE (SET_SRC (x)) == HIGH 2468 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST 2469 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF 2470 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) 2471 || ((GET_CODE (SET_SRC (x)) == PLUS 2472 || GET_CODE (SET_SRC (x)) == LO_SUM) 2473 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST 2474 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF 2475 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) 2476 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 2477 && (GET_CODE (XEXP (note, 0)) == CONST 2478 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF 2479 || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) 2480 REG_POINTER (SET_DEST (x)) = 1; 2481 2482 /* If this is setting a register from a register or from a simple 2483 conversion of a register, propagate REG_EXPR. */ 2484 if (GET_CODE (dest) == REG) 2485 { 2486 rtx src = SET_SRC (x); 2487 2488 while (GET_CODE (src) == SIGN_EXTEND 2489 || GET_CODE (src) == ZERO_EXTEND 2490 || GET_CODE (src) == TRUNCATE 2491 || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src))) 2492 src = XEXP (src, 0); 2493 2494 if (!REG_ATTRS (dest) && REG_P (src)) 2495 REG_ATTRS (dest) = REG_ATTRS (src); 2496 if (!REG_ATTRS (dest) && GET_CODE (src) == MEM) 2497 set_reg_attrs_from_mem (dest, src); 2498 } 2499 2500 /* ... fall through ... */ 2501 2502 default: 2503 { 2504 const char *fmt = GET_RTX_FORMAT (code); 2505 int i; 2506 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2507 { 2508 if (fmt[i] == 'e') 2509 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); 2510 else if (fmt[i] == 'E' && XVEC (x, i) != 0) 2511 { 2512 int j; 2513 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 2514 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); 2515 } 2516 } 2517 } 2518 } 2519} 2520 2521/* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 2522 is also in C2. */ 2523 2524int 2525reg_class_subset_p (enum reg_class c1, enum reg_class c2) 2526{ 2527 if (c1 == c2) return 1; 2528 2529 if (c2 == ALL_REGS) 2530 win: 2531 return 1; 2532 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) c1], 2533 reg_class_contents[(int) c2], 2534 win); 2535 return 0; 2536} 2537 2538/* Return nonzero if there is a register that is in both C1 and C2. */ 2539 2540int 2541reg_classes_intersect_p (enum reg_class c1, enum reg_class c2) 2542{ 2543 HARD_REG_SET c; 2544 2545 if (c1 == c2) return 1; 2546 2547 if (c1 == ALL_REGS || c2 == ALL_REGS) 2548 return 1; 2549 2550 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); 2551 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); 2552 2553 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); 2554 return 1; 2555 2556 lose: 2557 return 0; 2558} 2559 2560/* Release any memory allocated by register sets. */ 2561 2562void 2563regset_release_memory (void) 2564{ 2565 bitmap_release_memory (); 2566} 2567 2568#ifdef CANNOT_CHANGE_MODE_CLASS 2569/* Set bits in *USED which correspond to registers which can't change 2570 their mode from FROM to any mode in which REGNO was encountered. */ 2571 2572void 2573cannot_change_mode_set_regs (HARD_REG_SET *used, enum machine_mode from, 2574 unsigned int regno) 2575{ 2576 enum machine_mode to; 2577 int n, i; 2578 int start = regno * MAX_MACHINE_MODE; 2579 2580 EXECUTE_IF_SET_IN_BITMAP (&subregs_of_mode, start, n, 2581 if (n >= MAX_MACHINE_MODE + start) 2582 return; 2583 to = n - start; 2584 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 2585 if (! TEST_HARD_REG_BIT (*used, i) 2586 && REG_CANNOT_CHANGE_MODE_P (i, from, to)) 2587 SET_HARD_REG_BIT (*used, i); 2588 ); 2589} 2590 2591/* Return 1 if REGNO has had an invalid mode change in CLASS from FROM 2592 mode. */ 2593 2594bool 2595invalid_mode_change_p (unsigned int regno, enum reg_class class, 2596 enum machine_mode from_mode) 2597{ 2598 enum machine_mode to_mode; 2599 int n; 2600 int start = regno * MAX_MACHINE_MODE; 2601 2602 EXECUTE_IF_SET_IN_BITMAP (&subregs_of_mode, start, n, 2603 if (n >= MAX_MACHINE_MODE + start) 2604 return 0; 2605 to_mode = n - start; 2606 if (CANNOT_CHANGE_MODE_CLASS (from_mode, to_mode, class)) 2607 return 1; 2608 ); 2609 return 0; 2610} 2611#endif /* CANNOT_CHANGE_MODE_CLASS */ 2612 2613#include "gt-regclass.h" 2614