regclass.c revision 117395
1/* Compute register class preferences for pseudo-registers. 2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996 3 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify it under 8the terms of the GNU General Public License as published by the Free 9Software Foundation; either version 2, or (at your option) any later 10version. 11 12GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13WARRANTY; without even the implied warranty of MERCHANTABILITY or 14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING. If not, write to the Free 19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 2002111-1307, USA. */ 21 22 23/* This file contains two passes of the compiler: reg_scan and reg_class. 24 It also defines some tables of information about the hardware registers 25 and a function init_reg_sets to initialize the tables. */ 26 27#include "config.h" 28#include "system.h" 29#include "hard-reg-set.h" 30#include "rtl.h" 31#include "expr.h" 32#include "tm_p.h" 33#include "flags.h" 34#include "basic-block.h" 35#include "regs.h" 36#include "function.h" 37#include "insn-config.h" 38#include "recog.h" 39#include "reload.h" 40#include "real.h" 41#include "toplev.h" 42#include "output.h" 43#include "ggc.h" 44 45#ifndef REGISTER_MOVE_COST 46#define REGISTER_MOVE_COST(m, x, y) 2 47#endif 48 49static void init_reg_sets_1 PARAMS ((void)); 50static void init_reg_modes PARAMS ((void)); 51static void init_reg_autoinc PARAMS ((void)); 52 53/* If we have auto-increment or auto-decrement and we can have secondary 54 reloads, we are not allowed to use classes requiring secondary 55 reloads for pseudos auto-incremented since reload can't handle it. */ 56 57#ifdef AUTO_INC_DEC 58#if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) 59#define FORBIDDEN_INC_DEC_CLASSES 60#endif 61#endif 62 63/* Register tables used by many passes. */ 64 65/* Indexed by hard register number, contains 1 for registers 66 that are fixed use (stack pointer, pc, frame pointer, etc.). 67 These are the registers that cannot be used to allocate 68 a pseudo reg for general use. */ 69 70char fixed_regs[FIRST_PSEUDO_REGISTER]; 71 72/* Same info as a HARD_REG_SET. */ 73 74HARD_REG_SET fixed_reg_set; 75 76/* Data for initializing the above. */ 77 78static const char initial_fixed_regs[] = FIXED_REGISTERS; 79 80/* Indexed by hard register number, contains 1 for registers 81 that are fixed use or are clobbered by function calls. 82 These are the registers that cannot be used to allocate 83 a pseudo reg whose life crosses calls unless we are able 84 to save/restore them across the calls. */ 85 86char call_used_regs[FIRST_PSEUDO_REGISTER]; 87 88/* Same info as a HARD_REG_SET. */ 89 90HARD_REG_SET call_used_reg_set; 91 92/* HARD_REG_SET of registers we want to avoid caller saving. */ 93HARD_REG_SET losing_caller_save_reg_set; 94 95/* Data for initializing the above. */ 96 97static const char initial_call_used_regs[] = CALL_USED_REGISTERS; 98 99/* This is much like call_used_regs, except it doesn't have to 100 be a superset of FIXED_REGISTERS. This vector indicates 101 what is really call clobbered, and is used when defining 102 regs_invalidated_by_call. */ 103 104#ifdef CALL_REALLY_USED_REGISTERS 105char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; 106#endif 107 108/* Indexed by hard register number, contains 1 for registers that are 109 fixed use or call used registers that cannot hold quantities across 110 calls even if we are willing to save and restore them. call fixed 111 registers are a subset of call used registers. */ 112 113char call_fixed_regs[FIRST_PSEUDO_REGISTER]; 114 115/* The same info as a HARD_REG_SET. */ 116 117HARD_REG_SET call_fixed_reg_set; 118 119/* Number of non-fixed registers. */ 120 121int n_non_fixed_regs; 122 123/* Indexed by hard register number, contains 1 for registers 124 that are being used for global register decls. 125 These must be exempt from ordinary flow analysis 126 and are also considered fixed. */ 127 128char global_regs[FIRST_PSEUDO_REGISTER]; 129 130/* Contains 1 for registers that are set or clobbered by calls. */ 131/* ??? Ideally, this would be just call_used_regs plus global_regs, but 132 for someone's bright idea to have call_used_regs strictly include 133 fixed_regs. Which leaves us guessing as to the set of fixed_regs 134 that are actually preserved. We know for sure that those associated 135 with the local stack frame are safe, but scant others. */ 136 137HARD_REG_SET regs_invalidated_by_call; 138 139/* Table of register numbers in the order in which to try to use them. */ 140#ifdef REG_ALLOC_ORDER 141int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; 142 143/* The inverse of reg_alloc_order. */ 144int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER]; 145#endif 146 147/* For each reg class, a HARD_REG_SET saying which registers are in it. */ 148 149HARD_REG_SET reg_class_contents[N_REG_CLASSES]; 150 151/* The same information, but as an array of unsigned ints. We copy from 152 these unsigned ints to the table above. We do this so the tm.h files 153 do not have to be aware of the wordsize for machines with <= 64 regs. 154 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ 155 156#define N_REG_INTS \ 157 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32) 158 159static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] 160 = REG_CLASS_CONTENTS; 161 162/* For each reg class, number of regs it contains. */ 163 164unsigned int reg_class_size[N_REG_CLASSES]; 165 166/* For each reg class, table listing all the containing classes. */ 167 168enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; 169 170/* For each reg class, table listing all the classes contained in it. */ 171 172enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; 173 174/* For each pair of reg classes, 175 a largest reg class contained in their union. */ 176 177enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; 178 179/* For each pair of reg classes, 180 the smallest reg class containing their union. */ 181 182enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; 183 184/* Array containing all of the register names. Unless 185 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */ 186 187#ifdef DEBUG_REGISTER_NAMES 188const char * reg_names[] = REGISTER_NAMES; 189#endif 190 191/* For each hard register, the widest mode object that it can contain. 192 This will be a MODE_INT mode if the register can hold integers. Otherwise 193 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the 194 register. */ 195 196enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; 197 198/* 1 if class does contain register of given mode. */ 199 200static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE]; 201 202/* Maximum cost of moving from a register in one class to a register in 203 another class. Based on REGISTER_MOVE_COST. */ 204 205static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; 206 207/* Similar, but here we don't have to move if the first index is a subset 208 of the second so in that case the cost is zero. */ 209 210static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; 211 212/* Similar, but here we don't have to move if the first index is a superset 213 of the second so in that case the cost is zero. */ 214 215static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; 216 217#ifdef FORBIDDEN_INC_DEC_CLASSES 218 219/* These are the classes that regs which are auto-incremented or decremented 220 cannot be put in. */ 221 222static int forbidden_inc_dec_class[N_REG_CLASSES]; 223 224/* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec 225 context. */ 226 227static char *in_inc_dec; 228 229#endif /* FORBIDDEN_INC_DEC_CLASSES */ 230 231#ifdef CANNOT_CHANGE_MODE_CLASS 232/* All registers that have been subreged. Indexed by regno * MAX_MACHINE_MODE 233 + mode. */ 234bitmap_head subregs_of_mode; 235#endif 236 237/* Sample MEM values for use by memory_move_secondary_cost. */ 238 239static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE]; 240 241/* Linked list of reg_info structures allocated for reg_n_info array. 242 Grouping all of the allocated structures together in one lump 243 means only one call to bzero to clear them, rather than n smaller 244 calls. */ 245struct reg_info_data { 246 struct reg_info_data *next; /* next set of reg_info structures */ 247 size_t min_index; /* minimum index # */ 248 size_t max_index; /* maximum index # */ 249 char used_p; /* nonzero if this has been used previously */ 250 reg_info data[1]; /* beginning of the reg_info data */ 251}; 252 253static struct reg_info_data *reg_info_head; 254 255/* No more global register variables may be declared; true once 256 regclass has been initialized. */ 257 258static int no_global_reg_vars = 0; 259 260 261/* Function called only once to initialize the above data on reg usage. 262 Once this is done, various switches may override. */ 263 264void 265init_reg_sets () 266{ 267 int i, j; 268 269 /* First copy the register information from the initial int form into 270 the regsets. */ 271 272 for (i = 0; i < N_REG_CLASSES; i++) 273 { 274 CLEAR_HARD_REG_SET (reg_class_contents[i]); 275 276 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ 277 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 278 if (int_reg_class_contents[i][j / 32] 279 & ((unsigned) 1 << (j % 32))) 280 SET_HARD_REG_BIT (reg_class_contents[i], j); 281 } 282 283 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); 284 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); 285 memset (global_regs, 0, sizeof global_regs); 286 287 /* Do any additional initialization regsets may need. */ 288 INIT_ONCE_REG_SET (); 289 290#ifdef REG_ALLOC_ORDER 291 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 292 inv_reg_alloc_order[reg_alloc_order[i]] = i; 293#endif 294} 295 296/* After switches have been processed, which perhaps alter 297 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ 298 299static void 300init_reg_sets_1 () 301{ 302 unsigned int i, j; 303 unsigned int /* enum machine_mode */ m; 304 char allocatable_regs_of_mode [MAX_MACHINE_MODE]; 305 306 /* This macro allows the fixed or call-used registers 307 and the register classes to depend on target flags. */ 308 309#ifdef CONDITIONAL_REGISTER_USAGE 310 CONDITIONAL_REGISTER_USAGE; 311#endif 312 313 /* Compute number of hard regs in each class. */ 314 315 memset ((char *) reg_class_size, 0, sizeof reg_class_size); 316 for (i = 0; i < N_REG_CLASSES; i++) 317 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 318 if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 319 reg_class_size[i]++; 320 321 /* Initialize the table of subunions. 322 reg_class_subunion[I][J] gets the largest-numbered reg-class 323 that is contained in the union of classes I and J. */ 324 325 for (i = 0; i < N_REG_CLASSES; i++) 326 { 327 for (j = 0; j < N_REG_CLASSES; j++) 328 { 329#ifdef HARD_REG_SET 330 register /* Declare it register if it's a scalar. */ 331#endif 332 HARD_REG_SET c; 333 int k; 334 335 COPY_HARD_REG_SET (c, reg_class_contents[i]); 336 IOR_HARD_REG_SET (c, reg_class_contents[j]); 337 for (k = 0; k < N_REG_CLASSES; k++) 338 { 339 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, 340 subclass1); 341 continue; 342 343 subclass1: 344 /* keep the largest subclass */ /* SPEE 900308 */ 345 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], 346 reg_class_contents[(int) reg_class_subunion[i][j]], 347 subclass2); 348 reg_class_subunion[i][j] = (enum reg_class) k; 349 subclass2: 350 ; 351 } 352 } 353 } 354 355 /* Initialize the table of superunions. 356 reg_class_superunion[I][J] gets the smallest-numbered reg-class 357 containing the union of classes I and J. */ 358 359 for (i = 0; i < N_REG_CLASSES; i++) 360 { 361 for (j = 0; j < N_REG_CLASSES; j++) 362 { 363#ifdef HARD_REG_SET 364 register /* Declare it register if it's a scalar. */ 365#endif 366 HARD_REG_SET c; 367 int k; 368 369 COPY_HARD_REG_SET (c, reg_class_contents[i]); 370 IOR_HARD_REG_SET (c, reg_class_contents[j]); 371 for (k = 0; k < N_REG_CLASSES; k++) 372 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); 373 374 superclass: 375 reg_class_superunion[i][j] = (enum reg_class) k; 376 } 377 } 378 379 /* Initialize the tables of subclasses and superclasses of each reg class. 380 First clear the whole table, then add the elements as they are found. */ 381 382 for (i = 0; i < N_REG_CLASSES; i++) 383 { 384 for (j = 0; j < N_REG_CLASSES; j++) 385 { 386 reg_class_superclasses[i][j] = LIM_REG_CLASSES; 387 reg_class_subclasses[i][j] = LIM_REG_CLASSES; 388 } 389 } 390 391 for (i = 0; i < N_REG_CLASSES; i++) 392 { 393 if (i == (int) NO_REGS) 394 continue; 395 396 for (j = i + 1; j < N_REG_CLASSES; j++) 397 { 398 enum reg_class *p; 399 400 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], 401 subclass); 402 continue; 403 subclass: 404 /* Reg class I is a subclass of J. 405 Add J to the table of superclasses of I. */ 406 p = ®_class_superclasses[i][0]; 407 while (*p != LIM_REG_CLASSES) p++; 408 *p = (enum reg_class) j; 409 /* Add I to the table of superclasses of J. */ 410 p = ®_class_subclasses[j][0]; 411 while (*p != LIM_REG_CLASSES) p++; 412 *p = (enum reg_class) i; 413 } 414 } 415 416 /* Initialize "constant" tables. */ 417 418 CLEAR_HARD_REG_SET (fixed_reg_set); 419 CLEAR_HARD_REG_SET (call_used_reg_set); 420 CLEAR_HARD_REG_SET (call_fixed_reg_set); 421 CLEAR_HARD_REG_SET (regs_invalidated_by_call); 422 423 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs); 424 425 n_non_fixed_regs = 0; 426 427 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 428 { 429 if (fixed_regs[i]) 430 SET_HARD_REG_BIT (fixed_reg_set, i); 431 else 432 n_non_fixed_regs++; 433 434 if (call_used_regs[i]) 435 SET_HARD_REG_BIT (call_used_reg_set, i); 436 if (call_fixed_regs[i]) 437 SET_HARD_REG_BIT (call_fixed_reg_set, i); 438 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) 439 SET_HARD_REG_BIT (losing_caller_save_reg_set, i); 440 441 /* There are a couple of fixed registers that we know are safe to 442 exclude from being clobbered by calls: 443 444 The frame pointer is always preserved across calls. The arg pointer 445 is if it is fixed. The stack pointer usually is, unless 446 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present. 447 If we are generating PIC code, the PIC offset table register is 448 preserved across calls, though the target can override that. */ 449 450 if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM) 451 ; 452#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 453 else if (i == HARD_FRAME_POINTER_REGNUM) 454 ; 455#endif 456#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM 457 else if (i == ARG_POINTER_REGNUM && fixed_regs[i]) 458 ; 459#endif 460#ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 461 else if (i == PIC_OFFSET_TABLE_REGNUM && fixed_regs[i]) 462 ; 463#endif 464 else if (0 465#ifdef CALL_REALLY_USED_REGISTERS 466 || call_really_used_regs[i] 467#else 468 || call_used_regs[i] 469#endif 470 || global_regs[i]) 471 SET_HARD_REG_BIT (regs_invalidated_by_call, i); 472 } 473 474 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode)); 475 memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode)); 476 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) 477 for (i = 0; i < N_REG_CLASSES; i++) 478 if ((unsigned) CLASS_MAX_NREGS (i, m) <= reg_class_size[i]) 479 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 480 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j) 481 && HARD_REGNO_MODE_OK (j, m)) 482 { 483 contains_reg_of_mode [i][m] = 1; 484 allocatable_regs_of_mode [m] = 1; 485 break; 486 } 487 488 /* Initialize the move cost table. Find every subset of each class 489 and take the maximum cost of moving any subset to any other. */ 490 491 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) 492 if (allocatable_regs_of_mode [m]) 493 { 494 for (i = 0; i < N_REG_CLASSES; i++) 495 if (contains_reg_of_mode [i][m]) 496 for (j = 0; j < N_REG_CLASSES; j++) 497 { 498 int cost; 499 enum reg_class *p1, *p2; 500 501 if (!contains_reg_of_mode [j][m]) 502 { 503 move_cost[m][i][j] = 65536; 504 may_move_in_cost[m][i][j] = 65536; 505 may_move_out_cost[m][i][j] = 65536; 506 } 507 else 508 { 509 cost = REGISTER_MOVE_COST (m, i, j); 510 511 for (p2 = ®_class_subclasses[j][0]; 512 *p2 != LIM_REG_CLASSES; 513 p2++) 514 if (*p2 != i && contains_reg_of_mode [*p2][m]) 515 cost = MAX (cost, move_cost [m][i][*p2]); 516 517 for (p1 = ®_class_subclasses[i][0]; 518 *p1 != LIM_REG_CLASSES; 519 p1++) 520 if (*p1 != j && contains_reg_of_mode [*p1][m]) 521 cost = MAX (cost, move_cost [m][*p1][j]); 522 523 move_cost[m][i][j] = cost; 524 525 if (reg_class_subset_p (i, j)) 526 may_move_in_cost[m][i][j] = 0; 527 else 528 may_move_in_cost[m][i][j] = cost; 529 530 if (reg_class_subset_p (j, i)) 531 may_move_out_cost[m][i][j] = 0; 532 else 533 may_move_out_cost[m][i][j] = cost; 534 } 535 } 536 else 537 for (j = 0; j < N_REG_CLASSES; j++) 538 { 539 move_cost[m][i][j] = 65536; 540 may_move_in_cost[m][i][j] = 65536; 541 may_move_out_cost[m][i][j] = 65536; 542 } 543 } 544} 545 546/* Compute the table of register modes. 547 These values are used to record death information for individual registers 548 (as opposed to a multi-register mode). */ 549 550static void 551init_reg_modes () 552{ 553 int i; 554 555 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 556 { 557 reg_raw_mode[i] = choose_hard_reg_mode (i, 1); 558 559 /* If we couldn't find a valid mode, just use the previous mode. 560 ??? One situation in which we need to do this is on the mips where 561 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like 562 to use DF mode for the even registers and VOIDmode for the odd 563 (for the cpu models where the odd ones are inaccessible). */ 564 if (reg_raw_mode[i] == VOIDmode) 565 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; 566 } 567} 568 569/* Finish initializing the register sets and 570 initialize the register modes. */ 571 572void 573init_regs () 574{ 575 /* This finishes what was started by init_reg_sets, but couldn't be done 576 until after register usage was specified. */ 577 init_reg_sets_1 (); 578 579 init_reg_modes (); 580 581 init_reg_autoinc (); 582} 583 584/* Initialize some fake stack-frame MEM references for use in 585 memory_move_secondary_cost. */ 586 587void 588init_fake_stack_mems () 589{ 590#ifdef HAVE_SECONDARY_RELOADS 591 { 592 int i; 593 594 for (i = 0; i < MAX_MACHINE_MODE; i++) 595 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); 596 } 597#endif 598} 599 600#ifdef HAVE_SECONDARY_RELOADS 601 602/* Compute extra cost of moving registers to/from memory due to reloads. 603 Only needed if secondary reloads are required for memory moves. */ 604 605int 606memory_move_secondary_cost (mode, class, in) 607 enum machine_mode mode; 608 enum reg_class class; 609 int in; 610{ 611 enum reg_class altclass; 612 int partial_cost = 0; 613 /* We need a memory reference to feed to SECONDARY... macros. */ 614 /* mem may be unused even if the SECONDARY_ macros are defined. */ 615 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; 616 617 618 if (in) 619 { 620#ifdef SECONDARY_INPUT_RELOAD_CLASS 621 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); 622#else 623 altclass = NO_REGS; 624#endif 625 } 626 else 627 { 628#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 629 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); 630#else 631 altclass = NO_REGS; 632#endif 633 } 634 635 if (altclass == NO_REGS) 636 return 0; 637 638 if (in) 639 partial_cost = REGISTER_MOVE_COST (mode, altclass, class); 640 else 641 partial_cost = REGISTER_MOVE_COST (mode, class, altclass); 642 643 if (class == altclass) 644 /* This isn't simply a copy-to-temporary situation. Can't guess 645 what it is, so MEMORY_MOVE_COST really ought not to be calling 646 here in that case. 647 648 I'm tempted to put in an abort here, but returning this will 649 probably only give poor estimates, which is what we would've 650 had before this code anyways. */ 651 return partial_cost; 652 653 /* Check if the secondary reload register will also need a 654 secondary reload. */ 655 return memory_move_secondary_cost (mode, altclass, in) + partial_cost; 656} 657#endif 658 659/* Return a machine mode that is legitimate for hard reg REGNO and large 660 enough to save nregs. If we can't find one, return VOIDmode. */ 661 662enum machine_mode 663choose_hard_reg_mode (regno, nregs) 664 unsigned int regno ATTRIBUTE_UNUSED; 665 unsigned int nregs; 666{ 667 unsigned int /* enum machine_mode */ m; 668 enum machine_mode found_mode = VOIDmode, mode; 669 670 /* We first look for the largest integer mode that can be validly 671 held in REGNO. If none, we look for the largest floating-point mode. 672 If we still didn't find a valid mode, try CCmode. */ 673 674 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); 675 mode != VOIDmode; 676 mode = GET_MODE_WIDER_MODE (mode)) 677 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs 678 && HARD_REGNO_MODE_OK (regno, mode)) 679 found_mode = mode; 680 681 if (found_mode != VOIDmode) 682 return found_mode; 683 684 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); 685 mode != VOIDmode; 686 mode = GET_MODE_WIDER_MODE (mode)) 687 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs 688 && HARD_REGNO_MODE_OK (regno, mode)) 689 found_mode = mode; 690 691 if (found_mode != VOIDmode) 692 return found_mode; 693 694 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); 695 mode != VOIDmode; 696 mode = GET_MODE_WIDER_MODE (mode)) 697 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs 698 && HARD_REGNO_MODE_OK (regno, mode)) 699 found_mode = mode; 700 701 if (found_mode != VOIDmode) 702 return found_mode; 703 704 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); 705 mode != VOIDmode; 706 mode = GET_MODE_WIDER_MODE (mode)) 707 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs 708 && HARD_REGNO_MODE_OK (regno, mode)) 709 found_mode = mode; 710 711 if (found_mode != VOIDmode) 712 return found_mode; 713 714 /* Iterate over all of the CCmodes. */ 715 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m) 716 { 717 mode = (enum machine_mode) m; 718 if ((unsigned) HARD_REGNO_NREGS (regno, mode) == nregs 719 && HARD_REGNO_MODE_OK (regno, mode)) 720 return mode; 721 } 722 723 /* We can't find a mode valid for this register. */ 724 return VOIDmode; 725} 726 727/* Specify the usage characteristics of the register named NAME. 728 It should be a fixed register if FIXED and a 729 call-used register if CALL_USED. */ 730 731void 732fix_register (name, fixed, call_used) 733 const char *name; 734 int fixed, call_used; 735{ 736 int i; 737 738 /* Decode the name and update the primary form of 739 the register info. */ 740 741 if ((i = decode_reg_name (name)) >= 0) 742 { 743 if ((i == STACK_POINTER_REGNUM 744#ifdef HARD_FRAME_POINTER_REGNUM 745 || i == HARD_FRAME_POINTER_REGNUM 746#else 747 || i == FRAME_POINTER_REGNUM 748#endif 749 ) 750 && (fixed == 0 || call_used == 0)) 751 { 752 static const char * const what_option[2][2] = { 753 { "call-saved", "call-used" }, 754 { "no-such-option", "fixed" }}; 755 756 error ("can't use '%s' as a %s register", name, 757 what_option[fixed][call_used]); 758 } 759 else 760 { 761 fixed_regs[i] = fixed; 762 call_used_regs[i] = call_used; 763#ifdef CALL_REALLY_USED_REGISTERS 764 if (fixed == 0) 765 call_really_used_regs[i] = call_used; 766#endif 767 } 768 } 769 else 770 { 771 warning ("unknown register name: %s", name); 772 } 773} 774 775/* Mark register number I as global. */ 776 777void 778globalize_reg (i) 779 int i; 780{ 781 if (fixed_regs[i] == 0 && no_global_reg_vars) 782 error ("global register variable follows a function definition"); 783 784 if (global_regs[i]) 785 { 786 warning ("register used for two global register variables"); 787 return; 788 } 789 790 if (call_used_regs[i] && ! fixed_regs[i]) 791 warning ("call-clobbered register used for global register variable"); 792 793 global_regs[i] = 1; 794 795 /* If already fixed, nothing else to do. */ 796 if (fixed_regs[i]) 797 return; 798 799 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; 800 n_non_fixed_regs--; 801 802 SET_HARD_REG_BIT (fixed_reg_set, i); 803 SET_HARD_REG_BIT (call_used_reg_set, i); 804 SET_HARD_REG_BIT (call_fixed_reg_set, i); 805 SET_HARD_REG_BIT (regs_invalidated_by_call, i); 806} 807 808/* Now the data and code for the `regclass' pass, which happens 809 just before local-alloc. */ 810 811/* The `costs' struct records the cost of using a hard register of each class 812 and of using memory for each pseudo. We use this data to set up 813 register class preferences. */ 814 815struct costs 816{ 817 int cost[N_REG_CLASSES]; 818 int mem_cost; 819}; 820 821/* Structure used to record preferrences of given pseudo. */ 822struct reg_pref 823{ 824 /* (enum reg_class) prefclass is the preferred class. */ 825 char prefclass; 826 827 /* altclass is a register class that we should use for allocating 828 pseudo if no register in the preferred class is available. 829 If no register in this class is available, memory is preferred. 830 831 It might appear to be more general to have a bitmask of classes here, 832 but since it is recommended that there be a class corresponding to the 833 union of most major pair of classes, that generality is not required. */ 834 char altclass; 835}; 836 837/* Record the cost of each class for each pseudo. */ 838 839static struct costs *costs; 840 841/* Initialized once, and used to initialize cost values for each insn. */ 842 843static struct costs init_cost; 844 845/* Record preferrences of each pseudo. 846 This is available after `regclass' is run. */ 847 848static struct reg_pref *reg_pref; 849 850/* Allocated buffers for reg_pref. */ 851 852static struct reg_pref *reg_pref_buffer; 853 854/* Frequency of executions of current insn. */ 855 856static int frequency; 857 858static rtx scan_one_insn PARAMS ((rtx, int)); 859static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *)); 860static void dump_regclass PARAMS ((FILE *)); 861static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *, 862 const char **, rtx, 863 struct costs *, struct reg_pref *)); 864static int copy_cost PARAMS ((rtx, enum machine_mode, 865 enum reg_class, int)); 866static void record_address_regs PARAMS ((rtx, enum reg_class, int)); 867#ifdef FORBIDDEN_INC_DEC_CLASSES 868static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode)); 869#endif 870static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int)); 871 872/* Return the reg_class in which pseudo reg number REGNO is best allocated. 873 This function is sometimes called before the info has been computed. 874 When that happens, just return GENERAL_REGS, which is innocuous. */ 875 876enum reg_class 877reg_preferred_class (regno) 878 int regno; 879{ 880 if (reg_pref == 0) 881 return GENERAL_REGS; 882 return (enum reg_class) reg_pref[regno].prefclass; 883} 884 885enum reg_class 886reg_alternate_class (regno) 887 int regno; 888{ 889 if (reg_pref == 0) 890 return ALL_REGS; 891 892 return (enum reg_class) reg_pref[regno].altclass; 893} 894 895/* Initialize some global data for this pass. */ 896 897void 898regclass_init () 899{ 900 int i; 901 902 init_cost.mem_cost = 10000; 903 for (i = 0; i < N_REG_CLASSES; i++) 904 init_cost.cost[i] = 10000; 905 906 /* This prevents dump_flow_info from losing if called 907 before regclass is run. */ 908 reg_pref = NULL; 909 910 /* No more global register variables may be declared. */ 911 no_global_reg_vars = 1; 912} 913 914/* Dump register costs. */ 915static void 916dump_regclass (dump) 917 FILE *dump; 918{ 919 static const char *const reg_class_names[] = REG_CLASS_NAMES; 920 int i; 921 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 922 { 923 int /* enum reg_class */ class; 924 if (REG_N_REFS (i)) 925 { 926 fprintf (dump, " Register %i costs:", i); 927 for (class = 0; class < (int) N_REG_CLASSES; class++) 928 if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)] 929#ifdef FORBIDDEN_INC_DEC_CLASSES 930 && (!in_inc_dec[i] 931 || !forbidden_inc_dec_class[(enum reg_class) class]) 932#endif 933#ifdef CANNOT_CHANGE_MODE_CLASS 934 && ! invalid_mode_change_p (i, (enum reg_class) class, 935 PSEUDO_REGNO_MODE (i)) 936#endif 937 ) 938 fprintf (dump, " %s:%i", reg_class_names[class], 939 costs[i].cost[(enum reg_class) class]); 940 fprintf (dump, " MEM:%i\n", costs[i].mem_cost); 941 } 942 } 943} 944 945 946/* Calculate the costs of insn operands. */ 947 948static void 949record_operand_costs (insn, op_costs, reg_pref) 950 rtx insn; 951 struct costs *op_costs; 952 struct reg_pref *reg_pref; 953{ 954 const char *constraints[MAX_RECOG_OPERANDS]; 955 enum machine_mode modes[MAX_RECOG_OPERANDS]; 956 int i; 957 958 for (i = 0; i < recog_data.n_operands; i++) 959 { 960 constraints[i] = recog_data.constraints[i]; 961 modes[i] = recog_data.operand_mode[i]; 962 } 963 964 /* If we get here, we are set up to record the costs of all the 965 operands for this insn. Start by initializing the costs. 966 Then handle any address registers. Finally record the desired 967 classes for any pseudos, doing it twice if some pair of 968 operands are commutative. */ 969 970 for (i = 0; i < recog_data.n_operands; i++) 971 { 972 op_costs[i] = init_cost; 973 974 if (GET_CODE (recog_data.operand[i]) == SUBREG) 975 recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); 976 977 if (GET_CODE (recog_data.operand[i]) == MEM) 978 record_address_regs (XEXP (recog_data.operand[i], 0), 979 MODE_BASE_REG_CLASS (modes[i]), frequency * 2); 980 else if (constraints[i][0] == 'p' 981 || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0])) 982 record_address_regs (recog_data.operand[i], 983 MODE_BASE_REG_CLASS (modes[i]), frequency * 2); 984 } 985 986 /* Check for commutative in a separate loop so everything will 987 have been initialized. We must do this even if one operand 988 is a constant--see addsi3 in m68k.md. */ 989 990 for (i = 0; i < (int) recog_data.n_operands - 1; i++) 991 if (constraints[i][0] == '%') 992 { 993 const char *xconstraints[MAX_RECOG_OPERANDS]; 994 int j; 995 996 /* Handle commutative operands by swapping the constraints. 997 We assume the modes are the same. */ 998 999 for (j = 0; j < recog_data.n_operands; j++) 1000 xconstraints[j] = constraints[j]; 1001 1002 xconstraints[i] = constraints[i+1]; 1003 xconstraints[i+1] = constraints[i]; 1004 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, 1005 recog_data.operand, modes, 1006 xconstraints, insn, op_costs, reg_pref); 1007 } 1008 1009 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, 1010 recog_data.operand, modes, 1011 constraints, insn, op_costs, reg_pref); 1012} 1013 1014/* Subroutine of regclass, processes one insn INSN. Scan it and record each 1015 time it would save code to put a certain register in a certain class. 1016 PASS, when nonzero, inhibits some optimizations which need only be done 1017 once. 1018 Return the last insn processed, so that the scan can be continued from 1019 there. */ 1020 1021static rtx 1022scan_one_insn (insn, pass) 1023 rtx insn; 1024 int pass; 1025{ 1026 enum rtx_code code = GET_CODE (insn); 1027 enum rtx_code pat_code; 1028 rtx set, note; 1029 int i, j; 1030 struct costs op_costs[MAX_RECOG_OPERANDS]; 1031 1032 if (GET_RTX_CLASS (code) != 'i') 1033 return insn; 1034 1035 pat_code = GET_CODE (PATTERN (insn)); 1036 if (pat_code == USE 1037 || pat_code == CLOBBER 1038 || pat_code == ASM_INPUT 1039 || pat_code == ADDR_VEC 1040 || pat_code == ADDR_DIFF_VEC) 1041 return insn; 1042 1043 set = single_set (insn); 1044 extract_insn (insn); 1045 1046 /* If this insn loads a parameter from its stack slot, then 1047 it represents a savings, rather than a cost, if the 1048 parameter is stored in memory. Record this fact. */ 1049 1050 if (set != 0 && GET_CODE (SET_DEST (set)) == REG 1051 && GET_CODE (SET_SRC (set)) == MEM 1052 && (note = find_reg_note (insn, REG_EQUIV, 1053 NULL_RTX)) != 0 1054 && GET_CODE (XEXP (note, 0)) == MEM) 1055 { 1056 costs[REGNO (SET_DEST (set))].mem_cost 1057 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), 1058 GENERAL_REGS, 1) 1059 * frequency); 1060 record_address_regs (XEXP (SET_SRC (set), 0), 1061 MODE_BASE_REG_CLASS (VOIDmode), frequency * 2); 1062 return insn; 1063 } 1064 1065 /* Improve handling of two-address insns such as 1066 (set X (ashift CONST Y)) where CONST must be made to 1067 match X. Change it into two insns: (set X CONST) 1068 (set X (ashift X Y)). If we left this for reloading, it 1069 would probably get three insns because X and Y might go 1070 in the same place. This prevents X and Y from receiving 1071 the same hard reg. 1072 1073 We can only do this if the modes of operands 0 and 1 1074 (which might not be the same) are tieable and we only need 1075 do this during our first pass. */ 1076 1077 if (pass == 0 && optimize 1078 && recog_data.n_operands >= 3 1079 && recog_data.constraints[1][0] == '0' 1080 && recog_data.constraints[1][1] == 0 1081 && CONSTANT_P (recog_data.operand[1]) 1082 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1]) 1083 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2]) 1084 && GET_CODE (recog_data.operand[0]) == REG 1085 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]), 1086 recog_data.operand_mode[1])) 1087 { 1088 rtx previnsn = prev_real_insn (insn); 1089 rtx dest 1090 = gen_lowpart (recog_data.operand_mode[1], 1091 recog_data.operand[0]); 1092 rtx newinsn 1093 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn); 1094 1095 /* If this insn was the start of a basic block, 1096 include the new insn in that block. 1097 We need not check for code_label here; 1098 while a basic block can start with a code_label, 1099 INSN could not be at the beginning of that block. */ 1100 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) 1101 { 1102 basic_block b; 1103 FOR_EACH_BB (b) 1104 if (insn == b->head) 1105 b->head = newinsn; 1106 } 1107 1108 /* This makes one more setting of new insns's dest. */ 1109 REG_N_SETS (REGNO (recog_data.operand[0]))++; 1110 REG_N_REFS (REGNO (recog_data.operand[0]))++; 1111 REG_FREQ (REGNO (recog_data.operand[0])) += frequency; 1112 1113 *recog_data.operand_loc[1] = recog_data.operand[0]; 1114 REG_N_REFS (REGNO (recog_data.operand[0]))++; 1115 REG_FREQ (REGNO (recog_data.operand[0])) += frequency; 1116 for (i = recog_data.n_dups - 1; i >= 0; i--) 1117 if (recog_data.dup_num[i] == 1) 1118 { 1119 *recog_data.dup_loc[i] = recog_data.operand[0]; 1120 REG_N_REFS (REGNO (recog_data.operand[0]))++; 1121 REG_FREQ (REGNO (recog_data.operand[0])) += frequency; 1122 } 1123 1124 return PREV_INSN (newinsn); 1125 } 1126 1127 record_operand_costs (insn, op_costs, reg_pref); 1128 1129 /* Now add the cost for each operand to the total costs for 1130 its register. */ 1131 1132 for (i = 0; i < recog_data.n_operands; i++) 1133 if (GET_CODE (recog_data.operand[i]) == REG 1134 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) 1135 { 1136 int regno = REGNO (recog_data.operand[i]); 1137 struct costs *p = &costs[regno], *q = &op_costs[i]; 1138 1139 p->mem_cost += q->mem_cost * frequency; 1140 for (j = 0; j < N_REG_CLASSES; j++) 1141 p->cost[j] += q->cost[j] * frequency; 1142 } 1143 1144 return insn; 1145} 1146 1147/* Initialize information about which register classes can be used for 1148 pseudos that are auto-incremented or auto-decremented. */ 1149 1150static void 1151init_reg_autoinc () 1152{ 1153#ifdef FORBIDDEN_INC_DEC_CLASSES 1154 int i; 1155 1156 for (i = 0; i < N_REG_CLASSES; i++) 1157 { 1158 rtx r = gen_rtx_raw_REG (VOIDmode, 0); 1159 enum machine_mode m; 1160 int j; 1161 1162 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 1163 if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 1164 { 1165 REGNO (r) = j; 1166 1167 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; 1168 m = (enum machine_mode) ((int) m + 1)) 1169 if (HARD_REGNO_MODE_OK (j, m)) 1170 { 1171 PUT_MODE (r, m); 1172 1173 /* If a register is not directly suitable for an 1174 auto-increment or decrement addressing mode and 1175 requires secondary reloads, disallow its class from 1176 being used in such addresses. */ 1177 1178 if ((0 1179#ifdef SECONDARY_RELOAD_CLASS 1180 || (SECONDARY_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) 1181 != NO_REGS) 1182#else 1183#ifdef SECONDARY_INPUT_RELOAD_CLASS 1184 || (SECONDARY_INPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) 1185 != NO_REGS) 1186#endif 1187#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1188 || (SECONDARY_OUTPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) 1189 != NO_REGS) 1190#endif 1191#endif 1192 ) 1193 && ! auto_inc_dec_reg_p (r, m)) 1194 forbidden_inc_dec_class[i] = 1; 1195 } 1196 } 1197 } 1198#endif /* FORBIDDEN_INC_DEC_CLASSES */ 1199} 1200 1201/* This is a pass of the compiler that scans all instructions 1202 and calculates the preferred class for each pseudo-register. 1203 This information can be accessed later by calling `reg_preferred_class'. 1204 This pass comes just before local register allocation. */ 1205 1206void 1207regclass (f, nregs, dump) 1208 rtx f; 1209 int nregs; 1210 FILE *dump; 1211{ 1212 rtx insn; 1213 int i; 1214 int pass; 1215 1216 init_recog (); 1217 1218 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs)); 1219 1220#ifdef FORBIDDEN_INC_DEC_CLASSES 1221 1222 in_inc_dec = (char *) xmalloc (nregs); 1223 1224#endif /* FORBIDDEN_INC_DEC_CLASSES */ 1225 1226 /* Normally we scan the insns once and determine the best class to use for 1227 each register. However, if -fexpensive_optimizations are on, we do so 1228 twice, the second time using the tentative best classes to guide the 1229 selection. */ 1230 1231 for (pass = 0; pass <= flag_expensive_optimizations; pass++) 1232 { 1233 basic_block bb; 1234 1235 if (dump) 1236 fprintf (dump, "\n\nPass %i\n\n",pass); 1237 /* Zero out our accumulation of the cost of each class for each reg. */ 1238 1239 memset ((char *) costs, 0, nregs * sizeof (struct costs)); 1240 1241#ifdef FORBIDDEN_INC_DEC_CLASSES 1242 memset (in_inc_dec, 0, nregs); 1243#endif 1244 1245 /* Scan the instructions and record each time it would 1246 save code to put a certain register in a certain class. */ 1247 1248 if (!optimize) 1249 { 1250 frequency = REG_FREQ_MAX; 1251 for (insn = f; insn; insn = NEXT_INSN (insn)) 1252 insn = scan_one_insn (insn, pass); 1253 } 1254 else 1255 FOR_EACH_BB (bb) 1256 { 1257 /* Show that an insn inside a loop is likely to be executed three 1258 times more than insns outside a loop. This is much more 1259 aggressive than the assumptions made elsewhere and is being 1260 tried as an experiment. */ 1261 frequency = REG_FREQ_FROM_BB (bb); 1262 for (insn = bb->head; ; insn = NEXT_INSN (insn)) 1263 { 1264 insn = scan_one_insn (insn, pass); 1265 if (insn == bb->end) 1266 break; 1267 } 1268 } 1269 1270 /* Now for each register look at how desirable each class is 1271 and find which class is preferred. Store that in 1272 `prefclass'. Record in `altclass' the largest register 1273 class any of whose registers is better than memory. */ 1274 1275 if (pass == 0) 1276 reg_pref = reg_pref_buffer; 1277 1278 if (dump) 1279 { 1280 dump_regclass (dump); 1281 fprintf (dump,"\n"); 1282 } 1283 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) 1284 { 1285 int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; 1286 enum reg_class best = ALL_REGS, alt = NO_REGS; 1287 /* This is an enum reg_class, but we call it an int 1288 to save lots of casts. */ 1289 int class; 1290 struct costs *p = &costs[i]; 1291 1292 /* In non-optimizing compilation REG_N_REFS is not initialized 1293 yet. */ 1294 if (optimize && !REG_N_REFS (i) && !REG_N_SETS (i)) 1295 continue; 1296 1297 for (class = (int) ALL_REGS - 1; class > 0; class--) 1298 { 1299 /* Ignore classes that are too small for this operand or 1300 invalid for an operand that was auto-incremented. */ 1301 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)] 1302#ifdef FORBIDDEN_INC_DEC_CLASSES 1303 || (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1304#endif 1305#ifdef CANNOT_CHANGE_MODE_CLASS 1306 || invalid_mode_change_p (i, (enum reg_class) class, 1307 PSEUDO_REGNO_MODE (i)) 1308#endif 1309 ) 1310 ; 1311 else if (p->cost[class] < best_cost) 1312 { 1313 best_cost = p->cost[class]; 1314 best = (enum reg_class) class; 1315 } 1316 else if (p->cost[class] == best_cost) 1317 best = reg_class_subunion[(int) best][class]; 1318 } 1319 1320 /* Record the alternate register class; i.e., a class for which 1321 every register in it is better than using memory. If adding a 1322 class would make a smaller class (i.e., no union of just those 1323 classes exists), skip that class. The major unions of classes 1324 should be provided as a register class. Don't do this if we 1325 will be doing it again later. */ 1326 1327 if ((pass == 1 || dump) || ! flag_expensive_optimizations) 1328 for (class = 0; class < N_REG_CLASSES; class++) 1329 if (p->cost[class] < p->mem_cost 1330 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] 1331 > reg_class_size[(int) alt]) 1332#ifdef FORBIDDEN_INC_DEC_CLASSES 1333 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1334#endif 1335#ifdef CANNOT_CHANGE_MODE_CLASS 1336 && ! invalid_mode_change_p (i, (enum reg_class) class, 1337 PSEUDO_REGNO_MODE (i)) 1338#endif 1339 ) 1340 alt = reg_class_subunion[(int) alt][class]; 1341 1342 /* If we don't add any classes, nothing to try. */ 1343 if (alt == best) 1344 alt = NO_REGS; 1345 1346 if (dump 1347 && (reg_pref[i].prefclass != (int) best 1348 || reg_pref[i].altclass != (int) alt)) 1349 { 1350 static const char *const reg_class_names[] = REG_CLASS_NAMES; 1351 fprintf (dump, " Register %i", i); 1352 if (alt == ALL_REGS || best == ALL_REGS) 1353 fprintf (dump, " pref %s\n", reg_class_names[(int) best]); 1354 else if (alt == NO_REGS) 1355 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]); 1356 else 1357 fprintf (dump, " pref %s, else %s\n", 1358 reg_class_names[(int) best], 1359 reg_class_names[(int) alt]); 1360 } 1361 1362 /* We cast to (int) because (char) hits bugs in some compilers. */ 1363 reg_pref[i].prefclass = (int) best; 1364 reg_pref[i].altclass = (int) alt; 1365 } 1366 } 1367 1368#ifdef FORBIDDEN_INC_DEC_CLASSES 1369 free (in_inc_dec); 1370#endif 1371 free (costs); 1372} 1373 1374/* Record the cost of using memory or registers of various classes for 1375 the operands in INSN. 1376 1377 N_ALTS is the number of alternatives. 1378 1379 N_OPS is the number of operands. 1380 1381 OPS is an array of the operands. 1382 1383 MODES are the modes of the operands, in case any are VOIDmode. 1384 1385 CONSTRAINTS are the constraints to use for the operands. This array 1386 is modified by this procedure. 1387 1388 This procedure works alternative by alternative. For each alternative 1389 we assume that we will be able to allocate all pseudos to their ideal 1390 register class and calculate the cost of using that alternative. Then 1391 we compute for each operand that is a pseudo-register, the cost of 1392 having the pseudo allocated to each register class and using it in that 1393 alternative. To this cost is added the cost of the alternative. 1394 1395 The cost of each class for this insn is its lowest cost among all the 1396 alternatives. */ 1397 1398static void 1399record_reg_classes (n_alts, n_ops, ops, modes, 1400 constraints, insn, op_costs, reg_pref) 1401 int n_alts; 1402 int n_ops; 1403 rtx *ops; 1404 enum machine_mode *modes; 1405 const char **constraints; 1406 rtx insn; 1407 struct costs *op_costs; 1408 struct reg_pref *reg_pref; 1409{ 1410 int alt; 1411 int i, j; 1412 rtx set; 1413 1414 /* Process each alternative, each time minimizing an operand's cost with 1415 the cost for each operand in that alternative. */ 1416 1417 for (alt = 0; alt < n_alts; alt++) 1418 { 1419 struct costs this_op_costs[MAX_RECOG_OPERANDS]; 1420 int alt_fail = 0; 1421 int alt_cost = 0; 1422 enum reg_class classes[MAX_RECOG_OPERANDS]; 1423 int allows_mem[MAX_RECOG_OPERANDS]; 1424 int class; 1425 1426 for (i = 0; i < n_ops; i++) 1427 { 1428 const char *p = constraints[i]; 1429 rtx op = ops[i]; 1430 enum machine_mode mode = modes[i]; 1431 int allows_addr = 0; 1432 int win = 0; 1433 unsigned char c; 1434 1435 /* Initially show we know nothing about the register class. */ 1436 classes[i] = NO_REGS; 1437 allows_mem[i] = 0; 1438 1439 /* If this operand has no constraints at all, we can conclude 1440 nothing about it since anything is valid. */ 1441 1442 if (*p == 0) 1443 { 1444 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1445 memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]); 1446 1447 continue; 1448 } 1449 1450 /* If this alternative is only relevant when this operand 1451 matches a previous operand, we do different things depending 1452 on whether this operand is a pseudo-reg or not. We must process 1453 any modifiers for the operand before we can make this test. */ 1454 1455 while (*p == '%' || *p == '=' || *p == '+' || *p == '&') 1456 p++; 1457 1458 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) 1459 { 1460 /* Copy class and whether memory is allowed from the matching 1461 alternative. Then perform any needed cost computations 1462 and/or adjustments. */ 1463 j = p[0] - '0'; 1464 classes[i] = classes[j]; 1465 allows_mem[i] = allows_mem[j]; 1466 1467 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) 1468 { 1469 /* If this matches the other operand, we have no added 1470 cost and we win. */ 1471 if (rtx_equal_p (ops[j], op)) 1472 win = 1; 1473 1474 /* If we can put the other operand into a register, add to 1475 the cost of this alternative the cost to copy this 1476 operand to the register used for the other operand. */ 1477 1478 else if (classes[j] != NO_REGS) 1479 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; 1480 } 1481 else if (GET_CODE (ops[j]) != REG 1482 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) 1483 { 1484 /* This op is a pseudo but the one it matches is not. */ 1485 1486 /* If we can't put the other operand into a register, this 1487 alternative can't be used. */ 1488 1489 if (classes[j] == NO_REGS) 1490 alt_fail = 1; 1491 1492 /* Otherwise, add to the cost of this alternative the cost 1493 to copy the other operand to the register used for this 1494 operand. */ 1495 1496 else 1497 alt_cost += copy_cost (ops[j], mode, classes[j], 1); 1498 } 1499 else 1500 { 1501 /* The costs of this operand are not the same as the other 1502 operand since move costs are not symmetric. Moreover, 1503 if we cannot tie them, this alternative needs to do a 1504 copy, which is one instruction. */ 1505 1506 struct costs *pp = &this_op_costs[i]; 1507 1508 for (class = 0; class < N_REG_CLASSES; class++) 1509 pp->cost[class] 1510 = ((recog_data.operand_type[i] != OP_OUT 1511 ? may_move_in_cost[mode][class][(int) classes[i]] 1512 : 0) 1513 + (recog_data.operand_type[i] != OP_IN 1514 ? may_move_out_cost[mode][(int) classes[i]][class] 1515 : 0)); 1516 1517 /* If the alternative actually allows memory, make things 1518 a bit cheaper since we won't need an extra insn to 1519 load it. */ 1520 1521 pp->mem_cost 1522 = ((recog_data.operand_type[i] != OP_IN 1523 ? MEMORY_MOVE_COST (mode, classes[i], 0) 1524 : 0) 1525 + (recog_data.operand_type[i] != OP_OUT 1526 ? MEMORY_MOVE_COST (mode, classes[i], 1) 1527 : 0) - allows_mem[i]); 1528 1529 /* If we have assigned a class to this register in our 1530 first pass, add a cost to this alternative corresponding 1531 to what we would add if this register were not in the 1532 appropriate class. */ 1533 1534 if (reg_pref) 1535 alt_cost 1536 += (may_move_in_cost[mode] 1537 [(unsigned char) reg_pref[REGNO (op)].prefclass] 1538 [(int) classes[i]]); 1539 1540 if (REGNO (ops[i]) != REGNO (ops[j]) 1541 && ! find_reg_note (insn, REG_DEAD, op)) 1542 alt_cost += 2; 1543 1544 /* This is in place of ordinary cost computation 1545 for this operand, so skip to the end of the 1546 alternative (should be just one character). */ 1547 while (*p && *p++ != ',') 1548 ; 1549 1550 constraints[i] = p; 1551 continue; 1552 } 1553 } 1554 1555 /* Scan all the constraint letters. See if the operand matches 1556 any of the constraints. Collect the valid register classes 1557 and see if this operand accepts memory. */ 1558 1559 while (*p && (c = *p++) != ',') 1560 switch (c) 1561 { 1562 case '*': 1563 /* Ignore the next letter for this pass. */ 1564 p++; 1565 break; 1566 1567 case '?': 1568 alt_cost += 2; 1569 case '!': case '#': case '&': 1570 case '0': case '1': case '2': case '3': case '4': 1571 case '5': case '6': case '7': case '8': case '9': 1572 break; 1573 1574 case 'p': 1575 allows_addr = 1; 1576 win = address_operand (op, GET_MODE (op)); 1577 /* We know this operand is an address, so we want it to be 1578 allocated to a register that can be the base of an 1579 address, ie BASE_REG_CLASS. */ 1580 classes[i] 1581 = reg_class_subunion[(int) classes[i]] 1582 [(int) MODE_BASE_REG_CLASS (VOIDmode)]; 1583 break; 1584 1585 case 'm': case 'o': case 'V': 1586 /* It doesn't seem worth distinguishing between offsettable 1587 and non-offsettable addresses here. */ 1588 allows_mem[i] = 1; 1589 if (GET_CODE (op) == MEM) 1590 win = 1; 1591 break; 1592 1593 case '<': 1594 if (GET_CODE (op) == MEM 1595 && (GET_CODE (XEXP (op, 0)) == PRE_DEC 1596 || GET_CODE (XEXP (op, 0)) == POST_DEC)) 1597 win = 1; 1598 break; 1599 1600 case '>': 1601 if (GET_CODE (op) == MEM 1602 && (GET_CODE (XEXP (op, 0)) == PRE_INC 1603 || GET_CODE (XEXP (op, 0)) == POST_INC)) 1604 win = 1; 1605 break; 1606 1607 case 'E': 1608 case 'F': 1609 if (GET_CODE (op) == CONST_DOUBLE 1610 || (GET_CODE (op) == CONST_VECTOR 1611 && (GET_MODE_CLASS (GET_MODE (op)) 1612 == MODE_VECTOR_FLOAT))) 1613 win = 1; 1614 break; 1615 1616 case 'G': 1617 case 'H': 1618 if (GET_CODE (op) == CONST_DOUBLE 1619 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) 1620 win = 1; 1621 break; 1622 1623 case 's': 1624 if (GET_CODE (op) == CONST_INT 1625 || (GET_CODE (op) == CONST_DOUBLE 1626 && GET_MODE (op) == VOIDmode)) 1627 break; 1628 case 'i': 1629 if (CONSTANT_P (op) 1630#ifdef LEGITIMATE_PIC_OPERAND_P 1631 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1632#endif 1633 ) 1634 win = 1; 1635 break; 1636 1637 case 'n': 1638 if (GET_CODE (op) == CONST_INT 1639 || (GET_CODE (op) == CONST_DOUBLE 1640 && GET_MODE (op) == VOIDmode)) 1641 win = 1; 1642 break; 1643 1644 case 'I': 1645 case 'J': 1646 case 'K': 1647 case 'L': 1648 case 'M': 1649 case 'N': 1650 case 'O': 1651 case 'P': 1652 if (GET_CODE (op) == CONST_INT 1653 && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) 1654 win = 1; 1655 break; 1656 1657 case 'X': 1658 win = 1; 1659 break; 1660 1661 case 'g': 1662 if (GET_CODE (op) == MEM 1663 || (CONSTANT_P (op) 1664#ifdef LEGITIMATE_PIC_OPERAND_P 1665 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1666#endif 1667 )) 1668 win = 1; 1669 allows_mem[i] = 1; 1670 case 'r': 1671 classes[i] 1672 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; 1673 break; 1674 1675 default: 1676 if (REG_CLASS_FROM_LETTER (c) != NO_REGS) 1677 classes[i] 1678 = reg_class_subunion[(int) classes[i]] 1679 [(int) REG_CLASS_FROM_LETTER (c)]; 1680#ifdef EXTRA_CONSTRAINT 1681 else if (EXTRA_CONSTRAINT (op, c)) 1682 win = 1; 1683 1684 if (EXTRA_MEMORY_CONSTRAINT (c)) 1685 { 1686 /* Every MEM can be reloaded to fit. */ 1687 allows_mem[i] = 1; 1688 if (GET_CODE (op) == MEM) 1689 win = 1; 1690 } 1691 if (EXTRA_ADDRESS_CONSTRAINT (c)) 1692 { 1693 /* Every address can be reloaded to fit. */ 1694 allows_addr = 1; 1695 if (address_operand (op, GET_MODE (op))) 1696 win = 1; 1697 /* We know this operand is an address, so we want it to be 1698 allocated to a register that can be the base of an 1699 address, ie BASE_REG_CLASS. */ 1700 classes[i] 1701 = reg_class_subunion[(int) classes[i]] 1702 [(int) MODE_BASE_REG_CLASS (VOIDmode)]; 1703 } 1704#endif 1705 break; 1706 } 1707 1708 constraints[i] = p; 1709 1710 /* How we account for this operand now depends on whether it is a 1711 pseudo register or not. If it is, we first check if any 1712 register classes are valid. If not, we ignore this alternative, 1713 since we want to assume that all pseudos get allocated for 1714 register preferencing. If some register class is valid, compute 1715 the costs of moving the pseudo into that class. */ 1716 1717 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1718 { 1719 if (classes[i] == NO_REGS) 1720 { 1721 /* We must always fail if the operand is a REG, but 1722 we did not find a suitable class. 1723 1724 Otherwise we may perform an uninitialized read 1725 from this_op_costs after the `continue' statement 1726 below. */ 1727 alt_fail = 1; 1728 } 1729 else 1730 { 1731 struct costs *pp = &this_op_costs[i]; 1732 1733 for (class = 0; class < N_REG_CLASSES; class++) 1734 pp->cost[class] 1735 = ((recog_data.operand_type[i] != OP_OUT 1736 ? may_move_in_cost[mode][class][(int) classes[i]] 1737 : 0) 1738 + (recog_data.operand_type[i] != OP_IN 1739 ? may_move_out_cost[mode][(int) classes[i]][class] 1740 : 0)); 1741 1742 /* If the alternative actually allows memory, make things 1743 a bit cheaper since we won't need an extra insn to 1744 load it. */ 1745 1746 pp->mem_cost 1747 = ((recog_data.operand_type[i] != OP_IN 1748 ? MEMORY_MOVE_COST (mode, classes[i], 0) 1749 : 0) 1750 + (recog_data.operand_type[i] != OP_OUT 1751 ? MEMORY_MOVE_COST (mode, classes[i], 1) 1752 : 0) - allows_mem[i]); 1753 1754 /* If we have assigned a class to this register in our 1755 first pass, add a cost to this alternative corresponding 1756 to what we would add if this register were not in the 1757 appropriate class. */ 1758 1759 if (reg_pref) 1760 alt_cost 1761 += (may_move_in_cost[mode] 1762 [(unsigned char) reg_pref[REGNO (op)].prefclass] 1763 [(int) classes[i]]); 1764 } 1765 } 1766 1767 /* Otherwise, if this alternative wins, either because we 1768 have already determined that or if we have a hard register of 1769 the proper class, there is no cost for this alternative. */ 1770 1771 else if (win 1772 || (GET_CODE (op) == REG 1773 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) 1774 ; 1775 1776 /* If registers are valid, the cost of this alternative includes 1777 copying the object to and/or from a register. */ 1778 1779 else if (classes[i] != NO_REGS) 1780 { 1781 if (recog_data.operand_type[i] != OP_OUT) 1782 alt_cost += copy_cost (op, mode, classes[i], 1); 1783 1784 if (recog_data.operand_type[i] != OP_IN) 1785 alt_cost += copy_cost (op, mode, classes[i], 0); 1786 } 1787 1788 /* The only other way this alternative can be used is if this is a 1789 constant that could be placed into memory. */ 1790 1791 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) 1792 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); 1793 else 1794 alt_fail = 1; 1795 } 1796 1797 if (alt_fail) 1798 continue; 1799 1800 /* Finally, update the costs with the information we've calculated 1801 about this alternative. */ 1802 1803 for (i = 0; i < n_ops; i++) 1804 if (GET_CODE (ops[i]) == REG 1805 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1806 { 1807 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; 1808 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); 1809 1810 pp->mem_cost = MIN (pp->mem_cost, 1811 (qq->mem_cost + alt_cost) * scale); 1812 1813 for (class = 0; class < N_REG_CLASSES; class++) 1814 pp->cost[class] = MIN (pp->cost[class], 1815 (qq->cost[class] + alt_cost) * scale); 1816 } 1817 } 1818 1819 /* If this insn is a single set copying operand 1 to operand 0 1820 and one operand is a pseudo with the other a hard reg or a pseudo 1821 that prefers a register that is in its own register class then 1822 we may want to adjust the cost of that register class to -1. 1823 1824 Avoid the adjustment if the source does not die to avoid stressing of 1825 register allocator by preferrencing two coliding registers into single 1826 class. 1827 1828 Also avoid the adjustment if a copy between registers of the class 1829 is expensive (ten times the cost of a default copy is considered 1830 arbitrarily expensive). This avoids losing when the preferred class 1831 is very expensive as the source of a copy instruction. */ 1832 1833 if ((set = single_set (insn)) != 0 1834 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) 1835 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG 1836 && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) 1837 for (i = 0; i <= 1; i++) 1838 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1839 { 1840 unsigned int regno = REGNO (ops[!i]); 1841 enum machine_mode mode = GET_MODE (ops[!i]); 1842 int class; 1843 unsigned int nr; 1844 1845 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0) 1846 { 1847 enum reg_class pref = reg_pref[regno].prefclass; 1848 1849 if ((reg_class_size[(unsigned char) pref] 1850 == (unsigned) CLASS_MAX_NREGS (pref, mode)) 1851 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2) 1852 op_costs[i].cost[(unsigned char) pref] = -1; 1853 } 1854 else if (regno < FIRST_PSEUDO_REGISTER) 1855 for (class = 0; class < N_REG_CLASSES; class++) 1856 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) 1857 && reg_class_size[class] == (unsigned) CLASS_MAX_NREGS (class, mode)) 1858 { 1859 if (reg_class_size[class] == 1) 1860 op_costs[i].cost[class] = -1; 1861 else 1862 { 1863 for (nr = 0; nr < (unsigned) HARD_REGNO_NREGS (regno, mode); nr++) 1864 { 1865 if (! TEST_HARD_REG_BIT (reg_class_contents[class], 1866 regno + nr)) 1867 break; 1868 } 1869 1870 if (nr == (unsigned) HARD_REGNO_NREGS (regno,mode)) 1871 op_costs[i].cost[class] = -1; 1872 } 1873 } 1874 } 1875} 1876 1877/* Compute the cost of loading X into (if TO_P is nonzero) or from (if 1878 TO_P is zero) a register of class CLASS in mode MODE. 1879 1880 X must not be a pseudo. */ 1881 1882static int 1883copy_cost (x, mode, class, to_p) 1884 rtx x; 1885 enum machine_mode mode ATTRIBUTE_UNUSED; 1886 enum reg_class class; 1887 int to_p ATTRIBUTE_UNUSED; 1888{ 1889#ifdef HAVE_SECONDARY_RELOADS 1890 enum reg_class secondary_class = NO_REGS; 1891#endif 1892 1893 /* If X is a SCRATCH, there is actually nothing to move since we are 1894 assuming optimal allocation. */ 1895 1896 if (GET_CODE (x) == SCRATCH) 1897 return 0; 1898 1899 /* Get the class we will actually use for a reload. */ 1900 class = PREFERRED_RELOAD_CLASS (x, class); 1901 1902#ifdef HAVE_SECONDARY_RELOADS 1903 /* If we need a secondary reload (we assume here that we are using 1904 the secondary reload as an intermediate, not a scratch register), the 1905 cost is that to load the input into the intermediate register, then 1906 to copy them. We use a special value of TO_P to avoid recursion. */ 1907 1908#ifdef SECONDARY_INPUT_RELOAD_CLASS 1909 if (to_p == 1) 1910 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); 1911#endif 1912 1913#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1914 if (! to_p) 1915 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); 1916#endif 1917 1918 if (secondary_class != NO_REGS) 1919 return (move_cost[mode][(int) secondary_class][(int) class] 1920 + copy_cost (x, mode, secondary_class, 2)); 1921#endif /* HAVE_SECONDARY_RELOADS */ 1922 1923 /* For memory, use the memory move cost, for (hard) registers, use the 1924 cost to move between the register classes, and use 2 for everything 1925 else (constants). */ 1926 1927 if (GET_CODE (x) == MEM || class == NO_REGS) 1928 return MEMORY_MOVE_COST (mode, class, to_p); 1929 1930 else if (GET_CODE (x) == REG) 1931 return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; 1932 1933 else 1934 /* If this is a constant, we may eventually want to call rtx_cost here. */ 1935 return COSTS_N_INSNS (1); 1936} 1937 1938/* Record the pseudo registers we must reload into hard registers 1939 in a subexpression of a memory address, X. 1940 1941 CLASS is the class that the register needs to be in and is either 1942 BASE_REG_CLASS or INDEX_REG_CLASS. 1943 1944 SCALE is twice the amount to multiply the cost by (it is twice so we 1945 can represent half-cost adjustments). */ 1946 1947static void 1948record_address_regs (x, class, scale) 1949 rtx x; 1950 enum reg_class class; 1951 int scale; 1952{ 1953 enum rtx_code code = GET_CODE (x); 1954 1955 switch (code) 1956 { 1957 case CONST_INT: 1958 case CONST: 1959 case CC0: 1960 case PC: 1961 case SYMBOL_REF: 1962 case LABEL_REF: 1963 return; 1964 1965 case PLUS: 1966 /* When we have an address that is a sum, 1967 we must determine whether registers are "base" or "index" regs. 1968 If there is a sum of two registers, we must choose one to be 1969 the "base". Luckily, we can use the REG_POINTER to make a good 1970 choice most of the time. We only need to do this on machines 1971 that can have two registers in an address and where the base 1972 and index register classes are different. 1973 1974 ??? This code used to set REGNO_POINTER_FLAG in some cases, but 1975 that seems bogus since it should only be set when we are sure 1976 the register is being used as a pointer. */ 1977 1978 { 1979 rtx arg0 = XEXP (x, 0); 1980 rtx arg1 = XEXP (x, 1); 1981 enum rtx_code code0 = GET_CODE (arg0); 1982 enum rtx_code code1 = GET_CODE (arg1); 1983 1984 /* Look inside subregs. */ 1985 if (code0 == SUBREG) 1986 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); 1987 if (code1 == SUBREG) 1988 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); 1989 1990 /* If this machine only allows one register per address, it must 1991 be in the first operand. */ 1992 1993 if (MAX_REGS_PER_ADDRESS == 1) 1994 record_address_regs (arg0, class, scale); 1995 1996 /* If index and base registers are the same on this machine, just 1997 record registers in any non-constant operands. We assume here, 1998 as well as in the tests below, that all addresses are in 1999 canonical form. */ 2000 2001 else if (INDEX_REG_CLASS == MODE_BASE_REG_CLASS (VOIDmode)) 2002 { 2003 record_address_regs (arg0, class, scale); 2004 if (! CONSTANT_P (arg1)) 2005 record_address_regs (arg1, class, scale); 2006 } 2007 2008 /* If the second operand is a constant integer, it doesn't change 2009 what class the first operand must be. */ 2010 2011 else if (code1 == CONST_INT || code1 == CONST_DOUBLE) 2012 record_address_regs (arg0, class, scale); 2013 2014 /* If the second operand is a symbolic constant, the first operand 2015 must be an index register. */ 2016 2017 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) 2018 record_address_regs (arg0, INDEX_REG_CLASS, scale); 2019 2020 /* If both operands are registers but one is already a hard register 2021 of index or base class, give the other the class that the hard 2022 register is not. */ 2023 2024#ifdef REG_OK_FOR_BASE_P 2025 else if (code0 == REG && code1 == REG 2026 && REGNO (arg0) < FIRST_PSEUDO_REGISTER 2027 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) 2028 record_address_regs (arg1, 2029 REG_OK_FOR_BASE_P (arg0) 2030 ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), 2031 scale); 2032 else if (code0 == REG && code1 == REG 2033 && REGNO (arg1) < FIRST_PSEUDO_REGISTER 2034 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) 2035 record_address_regs (arg0, 2036 REG_OK_FOR_BASE_P (arg1) 2037 ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), 2038 scale); 2039#endif 2040 2041 /* If one operand is known to be a pointer, it must be the base 2042 with the other operand the index. Likewise if the other operand 2043 is a MULT. */ 2044 2045 else if ((code0 == REG && REG_POINTER (arg0)) 2046 || code1 == MULT) 2047 { 2048 record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), scale); 2049 record_address_regs (arg1, INDEX_REG_CLASS, scale); 2050 } 2051 else if ((code1 == REG && REG_POINTER (arg1)) 2052 || code0 == MULT) 2053 { 2054 record_address_regs (arg0, INDEX_REG_CLASS, scale); 2055 record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), scale); 2056 } 2057 2058 /* Otherwise, count equal chances that each might be a base 2059 or index register. This case should be rare. */ 2060 2061 else 2062 { 2063 record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), 2064 scale / 2); 2065 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); 2066 record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), 2067 scale / 2); 2068 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); 2069 } 2070 } 2071 break; 2072 2073 /* Double the importance of a pseudo register that is incremented 2074 or decremented, since it would take two extra insns 2075 if it ends up in the wrong place. */ 2076 case POST_MODIFY: 2077 case PRE_MODIFY: 2078 record_address_regs (XEXP (x, 0), MODE_BASE_REG_CLASS (VOIDmode), 2079 2 * scale); 2080 if (REG_P (XEXP (XEXP (x, 1), 1))) 2081 record_address_regs (XEXP (XEXP (x, 1), 1), 2082 INDEX_REG_CLASS, 2 * scale); 2083 break; 2084 2085 case POST_INC: 2086 case PRE_INC: 2087 case POST_DEC: 2088 case PRE_DEC: 2089 /* Double the importance of a pseudo register that is incremented 2090 or decremented, since it would take two extra insns 2091 if it ends up in the wrong place. If the operand is a pseudo, 2092 show it is being used in an INC_DEC context. */ 2093 2094#ifdef FORBIDDEN_INC_DEC_CLASSES 2095 if (GET_CODE (XEXP (x, 0)) == REG 2096 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) 2097 in_inc_dec[REGNO (XEXP (x, 0))] = 1; 2098#endif 2099 2100 record_address_regs (XEXP (x, 0), class, 2 * scale); 2101 break; 2102 2103 case REG: 2104 { 2105 struct costs *pp = &costs[REGNO (x)]; 2106 int i; 2107 2108 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; 2109 2110 for (i = 0; i < N_REG_CLASSES; i++) 2111 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2; 2112 } 2113 break; 2114 2115 default: 2116 { 2117 const char *fmt = GET_RTX_FORMAT (code); 2118 int i; 2119 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2120 if (fmt[i] == 'e') 2121 record_address_regs (XEXP (x, i), class, scale); 2122 } 2123 } 2124} 2125 2126#ifdef FORBIDDEN_INC_DEC_CLASSES 2127 2128/* Return 1 if REG is valid as an auto-increment memory reference 2129 to an object of MODE. */ 2130 2131static int 2132auto_inc_dec_reg_p (reg, mode) 2133 rtx reg; 2134 enum machine_mode mode; 2135{ 2136 if (HAVE_POST_INCREMENT 2137 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) 2138 return 1; 2139 2140 if (HAVE_POST_DECREMENT 2141 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) 2142 return 1; 2143 2144 if (HAVE_PRE_INCREMENT 2145 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) 2146 return 1; 2147 2148 if (HAVE_PRE_DECREMENT 2149 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) 2150 return 1; 2151 2152 return 0; 2153} 2154#endif 2155 2156static short *renumber; 2157static size_t regno_allocated; 2158static unsigned int reg_n_max; 2159 2160/* Allocate enough space to hold NUM_REGS registers for the tables used for 2161 reg_scan and flow_analysis that are indexed by the register number. If 2162 NEW_P is nonzero, initialize all of the registers, otherwise only 2163 initialize the new registers allocated. The same table is kept from 2164 function to function, only reallocating it when we need more room. If 2165 RENUMBER_P is nonzero, allocate the reg_renumber array also. */ 2166 2167void 2168allocate_reg_info (num_regs, new_p, renumber_p) 2169 size_t num_regs; 2170 int new_p; 2171 int renumber_p; 2172{ 2173 size_t size_info; 2174 size_t size_renumber; 2175 size_t min = (new_p) ? 0 : reg_n_max; 2176 struct reg_info_data *reg_data; 2177 2178 if (num_regs > regno_allocated) 2179 { 2180 size_t old_allocated = regno_allocated; 2181 2182 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ 2183 size_renumber = regno_allocated * sizeof (short); 2184 2185 if (!reg_n_info) 2186 { 2187 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); 2188 renumber = (short *) xmalloc (size_renumber); 2189 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated 2190 * sizeof (struct reg_pref)); 2191 } 2192 2193 else 2194 { 2195 VARRAY_GROW (reg_n_info, regno_allocated); 2196 2197 if (new_p) /* if we're zapping everything, no need to realloc */ 2198 { 2199 free ((char *) renumber); 2200 free ((char *) reg_pref); 2201 renumber = (short *) xmalloc (size_renumber); 2202 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated 2203 * sizeof (struct reg_pref)); 2204 } 2205 2206 else 2207 { 2208 renumber = (short *) xrealloc ((char *) renumber, size_renumber); 2209 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *) reg_pref_buffer, 2210 regno_allocated 2211 * sizeof (struct reg_pref)); 2212 } 2213 } 2214 2215 size_info = (regno_allocated - old_allocated) * sizeof (reg_info) 2216 + sizeof (struct reg_info_data) - sizeof (reg_info); 2217 reg_data = (struct reg_info_data *) xcalloc (size_info, 1); 2218 reg_data->min_index = old_allocated; 2219 reg_data->max_index = regno_allocated - 1; 2220 reg_data->next = reg_info_head; 2221 reg_info_head = reg_data; 2222 } 2223 2224 reg_n_max = num_regs; 2225 if (min < num_regs) 2226 { 2227 /* Loop through each of the segments allocated for the actual 2228 reg_info pages, and set up the pointers, zero the pages, etc. */ 2229 for (reg_data = reg_info_head; 2230 reg_data && reg_data->max_index >= min; 2231 reg_data = reg_data->next) 2232 { 2233 size_t min_index = reg_data->min_index; 2234 size_t max_index = reg_data->max_index; 2235 size_t max = MIN (max_index, num_regs); 2236 size_t local_min = min - min_index; 2237 size_t i; 2238 2239 if (reg_data->min_index > num_regs) 2240 continue; 2241 2242 if (min < min_index) 2243 local_min = 0; 2244 if (!reg_data->used_p) /* page just allocated with calloc */ 2245 reg_data->used_p = 1; /* no need to zero */ 2246 else 2247 memset ((char *) ®_data->data[local_min], 0, 2248 sizeof (reg_info) * (max - min_index - local_min + 1)); 2249 2250 for (i = min_index+local_min; i <= max; i++) 2251 { 2252 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; 2253 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; 2254 renumber[i] = -1; 2255 reg_pref_buffer[i].prefclass = (char) NO_REGS; 2256 reg_pref_buffer[i].altclass = (char) NO_REGS; 2257 } 2258 } 2259 } 2260 2261 /* If {pref,alt}class have already been allocated, update the pointers to 2262 the newly realloced ones. */ 2263 if (reg_pref) 2264 reg_pref = reg_pref_buffer; 2265 2266 if (renumber_p) 2267 reg_renumber = renumber; 2268 2269 /* Tell the regset code about the new number of registers. */ 2270 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); 2271} 2272 2273/* Free up the space allocated by allocate_reg_info. */ 2274void 2275free_reg_info () 2276{ 2277 if (reg_n_info) 2278 { 2279 struct reg_info_data *reg_data; 2280 struct reg_info_data *reg_next; 2281 2282 VARRAY_FREE (reg_n_info); 2283 for (reg_data = reg_info_head; reg_data; reg_data = reg_next) 2284 { 2285 reg_next = reg_data->next; 2286 free ((char *) reg_data); 2287 } 2288 2289 free (reg_pref_buffer); 2290 reg_pref_buffer = (struct reg_pref *) 0; 2291 reg_info_head = (struct reg_info_data *) 0; 2292 renumber = (short *) 0; 2293 } 2294 regno_allocated = 0; 2295 reg_n_max = 0; 2296} 2297 2298/* This is the `regscan' pass of the compiler, run just before cse 2299 and again just before loop. 2300 2301 It finds the first and last use of each pseudo-register 2302 and records them in the vectors regno_first_uid, regno_last_uid 2303 and counts the number of sets in the vector reg_n_sets. 2304 2305 REPEAT is nonzero the second time this is called. */ 2306 2307/* Maximum number of parallel sets and clobbers in any insn in this fn. 2308 Always at least 3, since the combiner could put that many together 2309 and we want this to remain correct for all the remaining passes. 2310 This corresponds to the maximum number of times note_stores will call 2311 a function for any insn. */ 2312 2313int max_parallel; 2314 2315/* Used as a temporary to record the largest number of registers in 2316 PARALLEL in a SET_DEST. This is added to max_parallel. */ 2317 2318static int max_set_parallel; 2319 2320void 2321reg_scan (f, nregs, repeat) 2322 rtx f; 2323 unsigned int nregs; 2324 int repeat ATTRIBUTE_UNUSED; 2325{ 2326 rtx insn; 2327 2328 allocate_reg_info (nregs, TRUE, FALSE); 2329 max_parallel = 3; 2330 max_set_parallel = 0; 2331 2332 for (insn = f; insn; insn = NEXT_INSN (insn)) 2333 if (GET_CODE (insn) == INSN 2334 || GET_CODE (insn) == CALL_INSN 2335 || GET_CODE (insn) == JUMP_INSN) 2336 { 2337 if (GET_CODE (PATTERN (insn)) == PARALLEL 2338 && XVECLEN (PATTERN (insn), 0) > max_parallel) 2339 max_parallel = XVECLEN (PATTERN (insn), 0); 2340 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0); 2341 2342 if (REG_NOTES (insn)) 2343 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); 2344 } 2345 2346 max_parallel += max_set_parallel; 2347} 2348 2349/* Update 'regscan' information by looking at the insns 2350 from FIRST to LAST. Some new REGs have been created, 2351 and any REG with number greater than OLD_MAX_REGNO is 2352 such a REG. We only update information for those. */ 2353 2354void 2355reg_scan_update (first, last, old_max_regno) 2356 rtx first; 2357 rtx last; 2358 unsigned int old_max_regno; 2359{ 2360 rtx insn; 2361 2362 allocate_reg_info (max_reg_num (), FALSE, FALSE); 2363 2364 for (insn = first; insn != last; insn = NEXT_INSN (insn)) 2365 if (GET_CODE (insn) == INSN 2366 || GET_CODE (insn) == CALL_INSN 2367 || GET_CODE (insn) == JUMP_INSN) 2368 { 2369 if (GET_CODE (PATTERN (insn)) == PARALLEL 2370 && XVECLEN (PATTERN (insn), 0) > max_parallel) 2371 max_parallel = XVECLEN (PATTERN (insn), 0); 2372 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno); 2373 2374 if (REG_NOTES (insn)) 2375 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); 2376 } 2377} 2378 2379/* X is the expression to scan. INSN is the insn it appears in. 2380 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. 2381 We should only record information for REGs with numbers 2382 greater than or equal to MIN_REGNO. */ 2383 2384static void 2385reg_scan_mark_refs (x, insn, note_flag, min_regno) 2386 rtx x; 2387 rtx insn; 2388 int note_flag; 2389 unsigned int min_regno; 2390{ 2391 enum rtx_code code; 2392 rtx dest; 2393 rtx note; 2394 2395 if (!x) 2396 return; 2397 code = GET_CODE (x); 2398 switch (code) 2399 { 2400 case CONST: 2401 case CONST_INT: 2402 case CONST_DOUBLE: 2403 case CONST_VECTOR: 2404 case CC0: 2405 case PC: 2406 case SYMBOL_REF: 2407 case LABEL_REF: 2408 case ADDR_VEC: 2409 case ADDR_DIFF_VEC: 2410 return; 2411 2412 case REG: 2413 { 2414 unsigned int regno = REGNO (x); 2415 2416 if (regno >= min_regno) 2417 { 2418 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); 2419 if (!note_flag) 2420 REGNO_LAST_UID (regno) = INSN_UID (insn); 2421 if (REGNO_FIRST_UID (regno) == 0) 2422 REGNO_FIRST_UID (regno) = INSN_UID (insn); 2423 /* If we are called by reg_scan_update() (indicated by min_regno 2424 being set), we also need to update the reference count. */ 2425 if (min_regno) 2426 REG_N_REFS (regno)++; 2427 } 2428 } 2429 break; 2430 2431 case EXPR_LIST: 2432 if (XEXP (x, 0)) 2433 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); 2434 if (XEXP (x, 1)) 2435 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); 2436 break; 2437 2438 case INSN_LIST: 2439 if (XEXP (x, 1)) 2440 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); 2441 break; 2442 2443 case CLOBBER: 2444 { 2445 rtx reg = XEXP (x, 0); 2446 if (REG_P (reg) 2447 && REGNO (reg) >= min_regno) 2448 { 2449 REG_N_SETS (REGNO (reg))++; 2450 REG_N_REFS (REGNO (reg))++; 2451 } 2452 } 2453 break; 2454 2455 case SET: 2456 /* Count a set of the destination if it is a register. */ 2457 for (dest = SET_DEST (x); 2458 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART 2459 || GET_CODE (dest) == ZERO_EXTEND; 2460 dest = XEXP (dest, 0)) 2461 ; 2462 2463 /* For a PARALLEL, record the number of things (less the usual one for a 2464 SET) that are set. */ 2465 if (GET_CODE (dest) == PARALLEL) 2466 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1); 2467 2468 if (GET_CODE (dest) == REG 2469 && REGNO (dest) >= min_regno) 2470 { 2471 REG_N_SETS (REGNO (dest))++; 2472 REG_N_REFS (REGNO (dest))++; 2473 } 2474 2475 /* If this is setting a pseudo from another pseudo or the sum of a 2476 pseudo and a constant integer and the other pseudo is known to be 2477 a pointer, set the destination to be a pointer as well. 2478 2479 Likewise if it is setting the destination from an address or from a 2480 value equivalent to an address or to the sum of an address and 2481 something else. 2482 2483 But don't do any of this if the pseudo corresponds to a user 2484 variable since it should have already been set as a pointer based 2485 on the type. */ 2486 2487 if (GET_CODE (SET_DEST (x)) == REG 2488 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER 2489 && REGNO (SET_DEST (x)) >= min_regno 2490 /* If the destination pseudo is set more than once, then other 2491 sets might not be to a pointer value (consider access to a 2492 union in two threads of control in the presense of global 2493 optimizations). So only set REG_POINTER on the destination 2494 pseudo if this is the only set of that pseudo. */ 2495 && REG_N_SETS (REGNO (SET_DEST (x))) == 1 2496 && ! REG_USERVAR_P (SET_DEST (x)) 2497 && ! REG_POINTER (SET_DEST (x)) 2498 && ((GET_CODE (SET_SRC (x)) == REG 2499 && REG_POINTER (SET_SRC (x))) 2500 || ((GET_CODE (SET_SRC (x)) == PLUS 2501 || GET_CODE (SET_SRC (x)) == LO_SUM) 2502 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 2503 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG 2504 && REG_POINTER (XEXP (SET_SRC (x), 0))) 2505 || GET_CODE (SET_SRC (x)) == CONST 2506 || GET_CODE (SET_SRC (x)) == SYMBOL_REF 2507 || GET_CODE (SET_SRC (x)) == LABEL_REF 2508 || (GET_CODE (SET_SRC (x)) == HIGH 2509 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST 2510 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF 2511 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) 2512 || ((GET_CODE (SET_SRC (x)) == PLUS 2513 || GET_CODE (SET_SRC (x)) == LO_SUM) 2514 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST 2515 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF 2516 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) 2517 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 2518 && (GET_CODE (XEXP (note, 0)) == CONST 2519 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF 2520 || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) 2521 REG_POINTER (SET_DEST (x)) = 1; 2522 2523 /* If this is setting a register from a register or from a simple 2524 conversion of a register, propagate REG_DECL. */ 2525 if (GET_CODE (dest) == REG) 2526 { 2527 rtx src = SET_SRC (x); 2528 2529 while (GET_CODE (src) == SIGN_EXTEND 2530 || GET_CODE (src) == ZERO_EXTEND 2531 || GET_CODE (src) == TRUNCATE 2532 || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src))) 2533 src = XEXP (src, 0); 2534 2535 if (GET_CODE (src) == REG && REGNO_DECL (REGNO (src)) == 0) 2536 REGNO_DECL (REGNO (src)) = REGNO_DECL (REGNO (dest)); 2537 else if (GET_CODE (src) == REG && REGNO_DECL (REGNO (dest)) == 0) 2538 REGNO_DECL (REGNO (dest)) = REGNO_DECL (REGNO (src)); 2539 } 2540 2541 /* ... fall through ... */ 2542 2543 default: 2544 { 2545 const char *fmt = GET_RTX_FORMAT (code); 2546 int i; 2547 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2548 { 2549 if (fmt[i] == 'e') 2550 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); 2551 else if (fmt[i] == 'E' && XVEC (x, i) != 0) 2552 { 2553 int j; 2554 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 2555 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); 2556 } 2557 } 2558 } 2559 } 2560} 2561 2562/* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 2563 is also in C2. */ 2564 2565int 2566reg_class_subset_p (c1, c2) 2567 enum reg_class c1; 2568 enum reg_class c2; 2569{ 2570 if (c1 == c2) return 1; 2571 2572 if (c2 == ALL_REGS) 2573 win: 2574 return 1; 2575 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) c1], 2576 reg_class_contents[(int) c2], 2577 win); 2578 return 0; 2579} 2580 2581/* Return nonzero if there is a register that is in both C1 and C2. */ 2582 2583int 2584reg_classes_intersect_p (c1, c2) 2585 enum reg_class c1; 2586 enum reg_class c2; 2587{ 2588#ifdef HARD_REG_SET 2589 register 2590#endif 2591 HARD_REG_SET c; 2592 2593 if (c1 == c2) return 1; 2594 2595 if (c1 == ALL_REGS || c2 == ALL_REGS) 2596 return 1; 2597 2598 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); 2599 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); 2600 2601 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); 2602 return 1; 2603 2604 lose: 2605 return 0; 2606} 2607 2608/* Release any memory allocated by register sets. */ 2609 2610void 2611regset_release_memory () 2612{ 2613 bitmap_release_memory (); 2614} 2615 2616#ifdef CANNOT_CHANGE_MODE_CLASS 2617/* Set bits in *USED which correspond to registers which can't change 2618 their mode from FROM to any mode in which REGNO was encountered. */ 2619 2620void 2621cannot_change_mode_set_regs (used, from, regno) 2622 HARD_REG_SET *used; 2623 enum machine_mode from; 2624 unsigned int regno; 2625{ 2626 enum machine_mode to; 2627 int n, i; 2628 int start = regno * MAX_MACHINE_MODE; 2629 2630 EXECUTE_IF_SET_IN_BITMAP (&subregs_of_mode, start, n, 2631 if (n >= MAX_MACHINE_MODE + start) 2632 return; 2633 to = n - start; 2634 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 2635 if (! TEST_HARD_REG_BIT (*used, i) 2636 && REG_CANNOT_CHANGE_MODE_P (i, from, to)) 2637 SET_HARD_REG_BIT (*used, i); 2638 ); 2639} 2640 2641/* Return 1 if REGNO has had an invalid mode change in CLASS from FROM 2642 mode. */ 2643 2644bool 2645invalid_mode_change_p (regno, class, from_mode) 2646 unsigned int regno; 2647 enum reg_class class; 2648 enum machine_mode from_mode; 2649{ 2650 enum machine_mode to_mode; 2651 int n; 2652 int start = regno * MAX_MACHINE_MODE; 2653 2654 EXECUTE_IF_SET_IN_BITMAP (&subregs_of_mode, start, n, 2655 if (n >= MAX_MACHINE_MODE + start) 2656 return 0; 2657 to_mode = n - start; 2658 if (CANNOT_CHANGE_MODE_CLASS (from_mode, to_mode, class)) 2659 return 1; 2660 ); 2661 return 0; 2662} 2663#endif /* CANNOT_CHANGE_MODE_CLASS */ 2664 2665#include "gt-regclass.h" 2666