regclass.c revision 102780
1/* Compute register class preferences for pseudo-registers. 2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996 3 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify it under 8the terms of the GNU General Public License as published by the Free 9Software Foundation; either version 2, or (at your option) any later 10version. 11 12GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13WARRANTY; without even the implied warranty of MERCHANTABILITY or 14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING. If not, write to the Free 19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 2002111-1307, USA. */ 21 22 23/* This file contains two passes of the compiler: reg_scan and reg_class. 24 It also defines some tables of information about the hardware registers 25 and a function init_reg_sets to initialize the tables. */ 26 27#include "config.h" 28#include "system.h" 29#include "rtl.h" 30#include "expr.h" 31#include "tm_p.h" 32#include "hard-reg-set.h" 33#include "flags.h" 34#include "basic-block.h" 35#include "regs.h" 36#include "function.h" 37#include "insn-config.h" 38#include "recog.h" 39#include "reload.h" 40#include "real.h" 41#include "toplev.h" 42#include "output.h" 43#include "ggc.h" 44 45#ifndef REGISTER_MOVE_COST 46#define REGISTER_MOVE_COST(m, x, y) 2 47#endif 48 49static void init_reg_sets_1 PARAMS ((void)); 50static void init_reg_modes PARAMS ((void)); 51 52/* If we have auto-increment or auto-decrement and we can have secondary 53 reloads, we are not allowed to use classes requiring secondary 54 reloads for pseudos auto-incremented since reload can't handle it. */ 55 56#ifdef AUTO_INC_DEC 57#if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) 58#define FORBIDDEN_INC_DEC_CLASSES 59#endif 60#endif 61 62/* Register tables used by many passes. */ 63 64/* Indexed by hard register number, contains 1 for registers 65 that are fixed use (stack pointer, pc, frame pointer, etc.). 66 These are the registers that cannot be used to allocate 67 a pseudo reg for general use. */ 68 69char fixed_regs[FIRST_PSEUDO_REGISTER]; 70 71/* Same info as a HARD_REG_SET. */ 72 73HARD_REG_SET fixed_reg_set; 74 75/* Data for initializing the above. */ 76 77static const char initial_fixed_regs[] = FIXED_REGISTERS; 78 79/* Indexed by hard register number, contains 1 for registers 80 that are fixed use or are clobbered by function calls. 81 These are the registers that cannot be used to allocate 82 a pseudo reg whose life crosses calls unless we are able 83 to save/restore them across the calls. */ 84 85char call_used_regs[FIRST_PSEUDO_REGISTER]; 86 87/* Same info as a HARD_REG_SET. */ 88 89HARD_REG_SET call_used_reg_set; 90 91/* HARD_REG_SET of registers we want to avoid caller saving. */ 92HARD_REG_SET losing_caller_save_reg_set; 93 94/* Data for initializing the above. */ 95 96static const char initial_call_used_regs[] = CALL_USED_REGISTERS; 97 98/* This is much like call_used_regs, except it doesn't have to 99 be a superset of FIXED_REGISTERS. This vector indicates 100 what is really call clobbered, and is used when defining 101 regs_invalidated_by_call. */ 102 103#ifdef CALL_REALLY_USED_REGISTERS 104char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; 105#endif 106 107/* Indexed by hard register number, contains 1 for registers that are 108 fixed use or call used registers that cannot hold quantities across 109 calls even if we are willing to save and restore them. call fixed 110 registers are a subset of call used registers. */ 111 112char call_fixed_regs[FIRST_PSEUDO_REGISTER]; 113 114/* The same info as a HARD_REG_SET. */ 115 116HARD_REG_SET call_fixed_reg_set; 117 118/* Number of non-fixed registers. */ 119 120int n_non_fixed_regs; 121 122/* Indexed by hard register number, contains 1 for registers 123 that are being used for global register decls. 124 These must be exempt from ordinary flow analysis 125 and are also considered fixed. */ 126 127char global_regs[FIRST_PSEUDO_REGISTER]; 128 129/* Contains 1 for registers that are set or clobbered by calls. */ 130/* ??? Ideally, this would be just call_used_regs plus global_regs, but 131 for someone's bright idea to have call_used_regs strictly include 132 fixed_regs. Which leaves us guessing as to the set of fixed_regs 133 that are actually preserved. We know for sure that those associated 134 with the local stack frame are safe, but scant others. */ 135 136HARD_REG_SET regs_invalidated_by_call; 137 138/* Table of register numbers in the order in which to try to use them. */ 139#ifdef REG_ALLOC_ORDER 140int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; 141 142/* The inverse of reg_alloc_order. */ 143int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER]; 144#endif 145 146/* For each reg class, a HARD_REG_SET saying which registers are in it. */ 147 148HARD_REG_SET reg_class_contents[N_REG_CLASSES]; 149 150/* The same information, but as an array of unsigned ints. We copy from 151 these unsigned ints to the table above. We do this so the tm.h files 152 do not have to be aware of the wordsize for machines with <= 64 regs. 153 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ 154 155#define N_REG_INTS \ 156 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32) 157 158static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] 159 = REG_CLASS_CONTENTS; 160 161/* For each reg class, number of regs it contains. */ 162 163unsigned int reg_class_size[N_REG_CLASSES]; 164 165/* For each reg class, table listing all the containing classes. */ 166 167enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; 168 169/* For each reg class, table listing all the classes contained in it. */ 170 171enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; 172 173/* For each pair of reg classes, 174 a largest reg class contained in their union. */ 175 176enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; 177 178/* For each pair of reg classes, 179 the smallest reg class containing their union. */ 180 181enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; 182 183/* Array containing all of the register names. Unless 184 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */ 185 186#ifdef DEBUG_REGISTER_NAMES 187const char * reg_names[] = REGISTER_NAMES; 188#endif 189 190/* For each hard register, the widest mode object that it can contain. 191 This will be a MODE_INT mode if the register can hold integers. Otherwise 192 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the 193 register. */ 194 195enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; 196 197/* 1 if class does contain register of given mode. */ 198 199static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE]; 200 201/* Maximum cost of moving from a register in one class to a register in 202 another class. Based on REGISTER_MOVE_COST. */ 203 204static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; 205 206/* Similar, but here we don't have to move if the first index is a subset 207 of the second so in that case the cost is zero. */ 208 209static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; 210 211/* Similar, but here we don't have to move if the first index is a superset 212 of the second so in that case the cost is zero. */ 213 214static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; 215 216#ifdef FORBIDDEN_INC_DEC_CLASSES 217 218/* These are the classes that regs which are auto-incremented or decremented 219 cannot be put in. */ 220 221static int forbidden_inc_dec_class[N_REG_CLASSES]; 222 223/* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec 224 context. */ 225 226static char *in_inc_dec; 227 228#endif /* FORBIDDEN_INC_DEC_CLASSES */ 229 230#ifdef CLASS_CANNOT_CHANGE_MODE 231 232/* These are the classes containing only registers that can be used in 233 a SUBREG expression that changes the mode of the register in some 234 way that is illegal. */ 235 236static int class_can_change_mode[N_REG_CLASSES]; 237 238/* Registers, including pseudos, which change modes in some way that 239 is illegal. */ 240 241static regset reg_changes_mode; 242 243#endif /* CLASS_CANNOT_CHANGE_MODE */ 244 245#ifdef HAVE_SECONDARY_RELOADS 246 247/* Sample MEM values for use by memory_move_secondary_cost. */ 248 249static rtx top_of_stack[MAX_MACHINE_MODE]; 250 251#endif /* HAVE_SECONDARY_RELOADS */ 252 253/* Linked list of reg_info structures allocated for reg_n_info array. 254 Grouping all of the allocated structures together in one lump 255 means only one call to bzero to clear them, rather than n smaller 256 calls. */ 257struct reg_info_data { 258 struct reg_info_data *next; /* next set of reg_info structures */ 259 size_t min_index; /* minimum index # */ 260 size_t max_index; /* maximum index # */ 261 char used_p; /* non-zero if this has been used previously */ 262 reg_info data[1]; /* beginning of the reg_info data */ 263}; 264 265static struct reg_info_data *reg_info_head; 266 267/* No more global register variables may be declared; true once 268 regclass has been initialized. */ 269 270static int no_global_reg_vars = 0; 271 272 273/* Function called only once to initialize the above data on reg usage. 274 Once this is done, various switches may override. */ 275 276void 277init_reg_sets () 278{ 279 int i, j; 280 281 /* First copy the register information from the initial int form into 282 the regsets. */ 283 284 for (i = 0; i < N_REG_CLASSES; i++) 285 { 286 CLEAR_HARD_REG_SET (reg_class_contents[i]); 287 288 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ 289 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 290 if (int_reg_class_contents[i][j / 32] 291 & ((unsigned) 1 << (j % 32))) 292 SET_HARD_REG_BIT (reg_class_contents[i], j); 293 } 294 295 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); 296 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); 297 memset (global_regs, 0, sizeof global_regs); 298 299 /* Do any additional initialization regsets may need */ 300 INIT_ONCE_REG_SET (); 301 302#ifdef REG_ALLOC_ORDER 303 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 304 inv_reg_alloc_order[reg_alloc_order[i]] = i; 305#endif 306} 307 308/* After switches have been processed, which perhaps alter 309 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ 310 311static void 312init_reg_sets_1 () 313{ 314 unsigned int i, j; 315 unsigned int /* enum machine_mode */ m; 316 char allocatable_regs_of_mode [MAX_MACHINE_MODE]; 317 318 /* This macro allows the fixed or call-used registers 319 and the register classes to depend on target flags. */ 320 321#ifdef CONDITIONAL_REGISTER_USAGE 322 CONDITIONAL_REGISTER_USAGE; 323#endif 324 325 /* Compute number of hard regs in each class. */ 326 327 memset ((char *) reg_class_size, 0, sizeof reg_class_size); 328 for (i = 0; i < N_REG_CLASSES; i++) 329 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 330 if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 331 reg_class_size[i]++; 332 333 /* Initialize the table of subunions. 334 reg_class_subunion[I][J] gets the largest-numbered reg-class 335 that is contained in the union of classes I and J. */ 336 337 for (i = 0; i < N_REG_CLASSES; i++) 338 { 339 for (j = 0; j < N_REG_CLASSES; j++) 340 { 341#ifdef HARD_REG_SET 342 register /* Declare it register if it's a scalar. */ 343#endif 344 HARD_REG_SET c; 345 int k; 346 347 COPY_HARD_REG_SET (c, reg_class_contents[i]); 348 IOR_HARD_REG_SET (c, reg_class_contents[j]); 349 for (k = 0; k < N_REG_CLASSES; k++) 350 { 351 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, 352 subclass1); 353 continue; 354 355 subclass1: 356 /* keep the largest subclass */ /* SPEE 900308 */ 357 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], 358 reg_class_contents[(int) reg_class_subunion[i][j]], 359 subclass2); 360 reg_class_subunion[i][j] = (enum reg_class) k; 361 subclass2: 362 ; 363 } 364 } 365 } 366 367 /* Initialize the table of superunions. 368 reg_class_superunion[I][J] gets the smallest-numbered reg-class 369 containing the union of classes I and J. */ 370 371 for (i = 0; i < N_REG_CLASSES; i++) 372 { 373 for (j = 0; j < N_REG_CLASSES; j++) 374 { 375#ifdef HARD_REG_SET 376 register /* Declare it register if it's a scalar. */ 377#endif 378 HARD_REG_SET c; 379 int k; 380 381 COPY_HARD_REG_SET (c, reg_class_contents[i]); 382 IOR_HARD_REG_SET (c, reg_class_contents[j]); 383 for (k = 0; k < N_REG_CLASSES; k++) 384 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); 385 386 superclass: 387 reg_class_superunion[i][j] = (enum reg_class) k; 388 } 389 } 390 391 /* Initialize the tables of subclasses and superclasses of each reg class. 392 First clear the whole table, then add the elements as they are found. */ 393 394 for (i = 0; i < N_REG_CLASSES; i++) 395 { 396 for (j = 0; j < N_REG_CLASSES; j++) 397 { 398 reg_class_superclasses[i][j] = LIM_REG_CLASSES; 399 reg_class_subclasses[i][j] = LIM_REG_CLASSES; 400 } 401 } 402 403 for (i = 0; i < N_REG_CLASSES; i++) 404 { 405 if (i == (int) NO_REGS) 406 continue; 407 408 for (j = i + 1; j < N_REG_CLASSES; j++) 409 { 410 enum reg_class *p; 411 412 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], 413 subclass); 414 continue; 415 subclass: 416 /* Reg class I is a subclass of J. 417 Add J to the table of superclasses of I. */ 418 p = ®_class_superclasses[i][0]; 419 while (*p != LIM_REG_CLASSES) p++; 420 *p = (enum reg_class) j; 421 /* Add I to the table of superclasses of J. */ 422 p = ®_class_subclasses[j][0]; 423 while (*p != LIM_REG_CLASSES) p++; 424 *p = (enum reg_class) i; 425 } 426 } 427 428 /* Initialize "constant" tables. */ 429 430 CLEAR_HARD_REG_SET (fixed_reg_set); 431 CLEAR_HARD_REG_SET (call_used_reg_set); 432 CLEAR_HARD_REG_SET (call_fixed_reg_set); 433 CLEAR_HARD_REG_SET (regs_invalidated_by_call); 434 435 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs); 436 437 n_non_fixed_regs = 0; 438 439 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 440 { 441 if (fixed_regs[i]) 442 SET_HARD_REG_BIT (fixed_reg_set, i); 443 else 444 n_non_fixed_regs++; 445 446 if (call_used_regs[i]) 447 SET_HARD_REG_BIT (call_used_reg_set, i); 448 if (call_fixed_regs[i]) 449 SET_HARD_REG_BIT (call_fixed_reg_set, i); 450 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) 451 SET_HARD_REG_BIT (losing_caller_save_reg_set, i); 452 453 /* There are a couple of fixed registers that we know are safe to 454 exclude from being clobbered by calls: 455 456 The frame pointer is always preserved across calls. The arg pointer 457 is if it is fixed. The stack pointer usually is, unless 458 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present. 459 If we are generating PIC code, the PIC offset table register is 460 preserved across calls, though the target can override that. */ 461 462 if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM) 463 ; 464#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 465 else if (i == HARD_FRAME_POINTER_REGNUM) 466 ; 467#endif 468#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM 469 else if (i == ARG_POINTER_REGNUM && fixed_regs[i]) 470 ; 471#endif 472#ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 473 else if (i == PIC_OFFSET_TABLE_REGNUM && fixed_regs[i]) 474 ; 475#endif 476 else if (0 477#ifdef CALL_REALLY_USED_REGISTERS 478 || call_really_used_regs[i] 479#else 480 || call_used_regs[i] 481#endif 482 || global_regs[i]) 483 SET_HARD_REG_BIT (regs_invalidated_by_call, i); 484 } 485 486 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode)); 487 memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode)); 488 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) 489 for (i = 0; i < N_REG_CLASSES; i++) 490 if (CLASS_MAX_NREGS (i, m) <= reg_class_size[i]) 491 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 492 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j) 493 && HARD_REGNO_MODE_OK (j, m)) 494 { 495 contains_reg_of_mode [i][m] = 1; 496 allocatable_regs_of_mode [m] = 1; 497 break; 498 } 499 500 /* Initialize the move cost table. Find every subset of each class 501 and take the maximum cost of moving any subset to any other. */ 502 503 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) 504 if (allocatable_regs_of_mode [m]) 505 { 506 for (i = 0; i < N_REG_CLASSES; i++) 507 if (contains_reg_of_mode [i][m]) 508 for (j = 0; j < N_REG_CLASSES; j++) 509 { 510 int cost; 511 enum reg_class *p1, *p2; 512 513 if (!contains_reg_of_mode [j][m]) 514 { 515 move_cost[m][i][j] = 65536; 516 may_move_in_cost[m][i][j] = 65536; 517 may_move_out_cost[m][i][j] = 65536; 518 } 519 else 520 { 521 cost = REGISTER_MOVE_COST (m, i, j); 522 523 for (p2 = ®_class_subclasses[j][0]; 524 *p2 != LIM_REG_CLASSES; 525 p2++) 526 if (*p2 != i && contains_reg_of_mode [*p2][m]) 527 cost = MAX (cost, move_cost [m][i][*p2]); 528 529 for (p1 = ®_class_subclasses[i][0]; 530 *p1 != LIM_REG_CLASSES; 531 p1++) 532 if (*p1 != j && contains_reg_of_mode [*p1][m]) 533 cost = MAX (cost, move_cost [m][*p1][j]); 534 535 move_cost[m][i][j] = cost; 536 537 if (reg_class_subset_p (i, j)) 538 may_move_in_cost[m][i][j] = 0; 539 else 540 may_move_in_cost[m][i][j] = cost; 541 542 if (reg_class_subset_p (j, i)) 543 may_move_out_cost[m][i][j] = 0; 544 else 545 may_move_out_cost[m][i][j] = cost; 546 } 547 } 548 else 549 for (j = 0; j < N_REG_CLASSES; j++) 550 { 551 move_cost[m][i][j] = 65536; 552 may_move_in_cost[m][i][j] = 65536; 553 may_move_out_cost[m][i][j] = 65536; 554 } 555 } 556 557#ifdef CLASS_CANNOT_CHANGE_MODE 558 { 559 HARD_REG_SET c; 560 COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]); 561 562 for (i = 0; i < N_REG_CLASSES; i++) 563 { 564 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class); 565 class_can_change_mode [i] = 0; 566 continue; 567 ok_class: 568 class_can_change_mode [i] = 1; 569 } 570 } 571#endif /* CLASS_CANNOT_CHANGE_MODE */ 572} 573 574/* Compute the table of register modes. 575 These values are used to record death information for individual registers 576 (as opposed to a multi-register mode). */ 577 578static void 579init_reg_modes () 580{ 581 int i; 582 583 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 584 { 585 reg_raw_mode[i] = choose_hard_reg_mode (i, 1); 586 587 /* If we couldn't find a valid mode, just use the previous mode. 588 ??? One situation in which we need to do this is on the mips where 589 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like 590 to use DF mode for the even registers and VOIDmode for the odd 591 (for the cpu models where the odd ones are inaccessible). */ 592 if (reg_raw_mode[i] == VOIDmode) 593 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; 594 } 595} 596 597/* Finish initializing the register sets and 598 initialize the register modes. */ 599 600void 601init_regs () 602{ 603 /* This finishes what was started by init_reg_sets, but couldn't be done 604 until after register usage was specified. */ 605 init_reg_sets_1 (); 606 607 init_reg_modes (); 608 609#ifdef HAVE_SECONDARY_RELOADS 610 { 611 /* Make some fake stack-frame MEM references for use in 612 memory_move_secondary_cost. */ 613 int i; 614 615 for (i = 0; i < MAX_MACHINE_MODE; i++) 616 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); 617 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE); 618 } 619#endif 620} 621 622#ifdef HAVE_SECONDARY_RELOADS 623 624/* Compute extra cost of moving registers to/from memory due to reloads. 625 Only needed if secondary reloads are required for memory moves. */ 626 627int 628memory_move_secondary_cost (mode, class, in) 629 enum machine_mode mode; 630 enum reg_class class; 631 int in; 632{ 633 enum reg_class altclass; 634 int partial_cost = 0; 635 /* We need a memory reference to feed to SECONDARY... macros. */ 636 /* mem may be unused even if the SECONDARY_ macros are defined. */ 637 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; 638 639 640 if (in) 641 { 642#ifdef SECONDARY_INPUT_RELOAD_CLASS 643 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); 644#else 645 altclass = NO_REGS; 646#endif 647 } 648 else 649 { 650#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 651 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); 652#else 653 altclass = NO_REGS; 654#endif 655 } 656 657 if (altclass == NO_REGS) 658 return 0; 659 660 if (in) 661 partial_cost = REGISTER_MOVE_COST (mode, altclass, class); 662 else 663 partial_cost = REGISTER_MOVE_COST (mode, class, altclass); 664 665 if (class == altclass) 666 /* This isn't simply a copy-to-temporary situation. Can't guess 667 what it is, so MEMORY_MOVE_COST really ought not to be calling 668 here in that case. 669 670 I'm tempted to put in an abort here, but returning this will 671 probably only give poor estimates, which is what we would've 672 had before this code anyways. */ 673 return partial_cost; 674 675 /* Check if the secondary reload register will also need a 676 secondary reload. */ 677 return memory_move_secondary_cost (mode, altclass, in) + partial_cost; 678} 679#endif 680 681/* Return a machine mode that is legitimate for hard reg REGNO and large 682 enough to save nregs. If we can't find one, return VOIDmode. */ 683 684enum machine_mode 685choose_hard_reg_mode (regno, nregs) 686 unsigned int regno ATTRIBUTE_UNUSED; 687 unsigned int nregs; 688{ 689 unsigned int /* enum machine_mode */ m; 690 enum machine_mode found_mode = VOIDmode, mode; 691 692 /* We first look for the largest integer mode that can be validly 693 held in REGNO. If none, we look for the largest floating-point mode. 694 If we still didn't find a valid mode, try CCmode. */ 695 696 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); 697 mode != VOIDmode; 698 mode = GET_MODE_WIDER_MODE (mode)) 699 if (HARD_REGNO_NREGS (regno, mode) == nregs 700 && HARD_REGNO_MODE_OK (regno, mode)) 701 found_mode = mode; 702 703 if (found_mode != VOIDmode) 704 return found_mode; 705 706 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); 707 mode != VOIDmode; 708 mode = GET_MODE_WIDER_MODE (mode)) 709 if (HARD_REGNO_NREGS (regno, mode) == nregs 710 && HARD_REGNO_MODE_OK (regno, mode)) 711 found_mode = mode; 712 713 if (found_mode != VOIDmode) 714 return found_mode; 715 716 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); 717 mode != VOIDmode; 718 mode = GET_MODE_WIDER_MODE (mode)) 719 if (HARD_REGNO_NREGS (regno, mode) == nregs 720 && HARD_REGNO_MODE_OK (regno, mode)) 721 found_mode = mode; 722 723 if (found_mode != VOIDmode) 724 return found_mode; 725 726 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); 727 mode != VOIDmode; 728 mode = GET_MODE_WIDER_MODE (mode)) 729 if (HARD_REGNO_NREGS (regno, mode) == nregs 730 && HARD_REGNO_MODE_OK (regno, mode)) 731 found_mode = mode; 732 733 if (found_mode != VOIDmode) 734 return found_mode; 735 736 /* Iterate over all of the CCmodes. */ 737 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m) 738 { 739 mode = (enum machine_mode) m; 740 if (HARD_REGNO_NREGS (regno, mode) == nregs 741 && HARD_REGNO_MODE_OK (regno, mode)) 742 return mode; 743 } 744 745 /* We can't find a mode valid for this register. */ 746 return VOIDmode; 747} 748 749/* Specify the usage characteristics of the register named NAME. 750 It should be a fixed register if FIXED and a 751 call-used register if CALL_USED. */ 752 753void 754fix_register (name, fixed, call_used) 755 const char *name; 756 int fixed, call_used; 757{ 758 int i; 759 760 /* Decode the name and update the primary form of 761 the register info. */ 762 763 if ((i = decode_reg_name (name)) >= 0) 764 { 765 if ((i == STACK_POINTER_REGNUM 766#ifdef HARD_FRAME_POINTER_REGNUM 767 || i == HARD_FRAME_POINTER_REGNUM 768#else 769 || i == FRAME_POINTER_REGNUM 770#endif 771 ) 772 && (fixed == 0 || call_used == 0)) 773 { 774 static const char * const what_option[2][2] = { 775 { "call-saved", "call-used" }, 776 { "no-such-option", "fixed" }}; 777 778 error ("can't use '%s' as a %s register", name, 779 what_option[fixed][call_used]); 780 } 781 else 782 { 783 fixed_regs[i] = fixed; 784 call_used_regs[i] = call_used; 785#ifdef CALL_REALLY_USED_REGISTERS 786 if (fixed == 0) 787 call_really_used_regs[i] = call_used; 788#endif 789 } 790 } 791 else 792 { 793 warning ("unknown register name: %s", name); 794 } 795} 796 797/* Mark register number I as global. */ 798 799void 800globalize_reg (i) 801 int i; 802{ 803 if (fixed_regs[i] == 0 && no_global_reg_vars) 804 error ("global register variable follows a function definition"); 805 806 if (global_regs[i]) 807 { 808 warning ("register used for two global register variables"); 809 return; 810 } 811 812 if (call_used_regs[i] && ! fixed_regs[i]) 813 warning ("call-clobbered register used for global register variable"); 814 815 global_regs[i] = 1; 816 817 /* If already fixed, nothing else to do. */ 818 if (fixed_regs[i]) 819 return; 820 821 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; 822 n_non_fixed_regs--; 823 824 SET_HARD_REG_BIT (fixed_reg_set, i); 825 SET_HARD_REG_BIT (call_used_reg_set, i); 826 SET_HARD_REG_BIT (call_fixed_reg_set, i); 827 SET_HARD_REG_BIT (regs_invalidated_by_call, i); 828} 829 830/* Now the data and code for the `regclass' pass, which happens 831 just before local-alloc. */ 832 833/* The `costs' struct records the cost of using a hard register of each class 834 and of using memory for each pseudo. We use this data to set up 835 register class preferences. */ 836 837struct costs 838{ 839 int cost[N_REG_CLASSES]; 840 int mem_cost; 841}; 842 843/* Structure used to record preferrences of given pseudo. */ 844struct reg_pref 845{ 846 /* (enum reg_class) prefclass is the preferred class. */ 847 char prefclass; 848 849 /* altclass is a register class that we should use for allocating 850 pseudo if no register in the preferred class is available. 851 If no register in this class is available, memory is preferred. 852 853 It might appear to be more general to have a bitmask of classes here, 854 but since it is recommended that there be a class corresponding to the 855 union of most major pair of classes, that generality is not required. */ 856 char altclass; 857}; 858 859/* Record the cost of each class for each pseudo. */ 860 861static struct costs *costs; 862 863/* Initialized once, and used to initialize cost values for each insn. */ 864 865static struct costs init_cost; 866 867/* Record preferrences of each pseudo. 868 This is available after `regclass' is run. */ 869 870static struct reg_pref *reg_pref; 871 872/* Allocated buffers for reg_pref. */ 873 874static struct reg_pref *reg_pref_buffer; 875 876/* Frequency of executions of current insn. */ 877 878static int frequency; 879 880static rtx scan_one_insn PARAMS ((rtx, int)); 881static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *)); 882static void dump_regclass PARAMS ((FILE *)); 883static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *, 884 const char **, rtx, 885 struct costs *, struct reg_pref *)); 886static int copy_cost PARAMS ((rtx, enum machine_mode, 887 enum reg_class, int)); 888static void record_address_regs PARAMS ((rtx, enum reg_class, int)); 889#ifdef FORBIDDEN_INC_DEC_CLASSES 890static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode)); 891#endif 892static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int)); 893 894/* Return the reg_class in which pseudo reg number REGNO is best allocated. 895 This function is sometimes called before the info has been computed. 896 When that happens, just return GENERAL_REGS, which is innocuous. */ 897 898enum reg_class 899reg_preferred_class (regno) 900 int regno; 901{ 902 if (reg_pref == 0) 903 return GENERAL_REGS; 904 return (enum reg_class) reg_pref[regno].prefclass; 905} 906 907enum reg_class 908reg_alternate_class (regno) 909 int regno; 910{ 911 if (reg_pref == 0) 912 return ALL_REGS; 913 914 return (enum reg_class) reg_pref[regno].altclass; 915} 916 917/* Initialize some global data for this pass. */ 918 919void 920regclass_init () 921{ 922 int i; 923 924 init_cost.mem_cost = 10000; 925 for (i = 0; i < N_REG_CLASSES; i++) 926 init_cost.cost[i] = 10000; 927 928 /* This prevents dump_flow_info from losing if called 929 before regclass is run. */ 930 reg_pref = NULL; 931 932 /* No more global register variables may be declared. */ 933 no_global_reg_vars = 1; 934} 935 936/* Dump register costs. */ 937static void 938dump_regclass (dump) 939 FILE *dump; 940{ 941 static const char *const reg_class_names[] = REG_CLASS_NAMES; 942 int i; 943 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 944 { 945 int /* enum reg_class */ class; 946 if (REG_N_REFS (i)) 947 { 948 fprintf (dump, " Register %i costs:", i); 949 for (class = 0; class < (int) N_REG_CLASSES; class++) 950 if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)] 951#ifdef FORBIDDEN_INC_DEC_CLASSES 952 && (!in_inc_dec[i] 953 || !forbidden_inc_dec_class[(enum reg_class) class]) 954#endif 955#ifdef CLASS_CANNOT_CHANGE_MODE 956 && (!REGNO_REG_SET_P (reg_changes_mode, i) 957 || class_can_change_mode [(enum reg_class) class]) 958#endif 959 ) 960 fprintf (dump, " %s:%i", reg_class_names[class], 961 costs[i].cost[(enum reg_class) class]); 962 fprintf (dump, " MEM:%i\n", costs[i].mem_cost); 963 } 964 } 965} 966 967 968/* Calculate the costs of insn operands. */ 969 970static void 971record_operand_costs (insn, op_costs, reg_pref) 972 rtx insn; 973 struct costs *op_costs; 974 struct reg_pref *reg_pref; 975{ 976 const char *constraints[MAX_RECOG_OPERANDS]; 977 enum machine_mode modes[MAX_RECOG_OPERANDS]; 978 int i; 979 980 for (i = 0; i < recog_data.n_operands; i++) 981 { 982 constraints[i] = recog_data.constraints[i]; 983 modes[i] = recog_data.operand_mode[i]; 984 } 985 986 /* If we get here, we are set up to record the costs of all the 987 operands for this insn. Start by initializing the costs. 988 Then handle any address registers. Finally record the desired 989 classes for any pseudos, doing it twice if some pair of 990 operands are commutative. */ 991 992 for (i = 0; i < recog_data.n_operands; i++) 993 { 994 op_costs[i] = init_cost; 995 996 if (GET_CODE (recog_data.operand[i]) == SUBREG) 997 { 998 rtx inner = SUBREG_REG (recog_data.operand[i]); 999#ifdef CLASS_CANNOT_CHANGE_MODE 1000 if (GET_CODE (inner) == REG 1001 && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner))) 1002 SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner)); 1003#endif 1004 recog_data.operand[i] = inner; 1005 } 1006 1007 if (GET_CODE (recog_data.operand[i]) == MEM) 1008 record_address_regs (XEXP (recog_data.operand[i], 0), 1009 MODE_BASE_REG_CLASS (modes[i]), frequency * 2); 1010 else if (constraints[i][0] == 'p') 1011 record_address_regs (recog_data.operand[i], 1012 MODE_BASE_REG_CLASS (modes[i]), frequency * 2); 1013 } 1014 1015 /* Check for commutative in a separate loop so everything will 1016 have been initialized. We must do this even if one operand 1017 is a constant--see addsi3 in m68k.md. */ 1018 1019 for (i = 0; i < (int) recog_data.n_operands - 1; i++) 1020 if (constraints[i][0] == '%') 1021 { 1022 const char *xconstraints[MAX_RECOG_OPERANDS]; 1023 int j; 1024 1025 /* Handle commutative operands by swapping the constraints. 1026 We assume the modes are the same. */ 1027 1028 for (j = 0; j < recog_data.n_operands; j++) 1029 xconstraints[j] = constraints[j]; 1030 1031 xconstraints[i] = constraints[i+1]; 1032 xconstraints[i+1] = constraints[i]; 1033 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, 1034 recog_data.operand, modes, 1035 xconstraints, insn, op_costs, reg_pref); 1036 } 1037 1038 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, 1039 recog_data.operand, modes, 1040 constraints, insn, op_costs, reg_pref); 1041} 1042 1043/* Subroutine of regclass, processes one insn INSN. Scan it and record each 1044 time it would save code to put a certain register in a certain class. 1045 PASS, when nonzero, inhibits some optimizations which need only be done 1046 once. 1047 Return the last insn processed, so that the scan can be continued from 1048 there. */ 1049 1050static rtx 1051scan_one_insn (insn, pass) 1052 rtx insn; 1053 int pass; 1054{ 1055 enum rtx_code code = GET_CODE (insn); 1056 enum rtx_code pat_code; 1057 rtx set, note; 1058 int i, j; 1059 struct costs op_costs[MAX_RECOG_OPERANDS]; 1060 1061 if (GET_RTX_CLASS (code) != 'i') 1062 return insn; 1063 1064 pat_code = GET_CODE (PATTERN (insn)); 1065 if (pat_code == USE 1066 || pat_code == CLOBBER 1067 || pat_code == ASM_INPUT 1068 || pat_code == ADDR_VEC 1069 || pat_code == ADDR_DIFF_VEC) 1070 return insn; 1071 1072 set = single_set (insn); 1073 extract_insn (insn); 1074 1075 /* If this insn loads a parameter from its stack slot, then 1076 it represents a savings, rather than a cost, if the 1077 parameter is stored in memory. Record this fact. */ 1078 1079 if (set != 0 && GET_CODE (SET_DEST (set)) == REG 1080 && GET_CODE (SET_SRC (set)) == MEM 1081 && (note = find_reg_note (insn, REG_EQUIV, 1082 NULL_RTX)) != 0 1083 && GET_CODE (XEXP (note, 0)) == MEM) 1084 { 1085 costs[REGNO (SET_DEST (set))].mem_cost 1086 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), 1087 GENERAL_REGS, 1) 1088 * frequency); 1089 record_address_regs (XEXP (SET_SRC (set), 0), 1090 MODE_BASE_REG_CLASS (VOIDmode), frequency * 2); 1091 return insn; 1092 } 1093 1094 /* Improve handling of two-address insns such as 1095 (set X (ashift CONST Y)) where CONST must be made to 1096 match X. Change it into two insns: (set X CONST) 1097 (set X (ashift X Y)). If we left this for reloading, it 1098 would probably get three insns because X and Y might go 1099 in the same place. This prevents X and Y from receiving 1100 the same hard reg. 1101 1102 We can only do this if the modes of operands 0 and 1 1103 (which might not be the same) are tieable and we only need 1104 do this during our first pass. */ 1105 1106 if (pass == 0 && optimize 1107 && recog_data.n_operands >= 3 1108 && recog_data.constraints[1][0] == '0' 1109 && recog_data.constraints[1][1] == 0 1110 && CONSTANT_P (recog_data.operand[1]) 1111 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1]) 1112 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2]) 1113 && GET_CODE (recog_data.operand[0]) == REG 1114 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]), 1115 recog_data.operand_mode[1])) 1116 { 1117 rtx previnsn = prev_real_insn (insn); 1118 rtx dest 1119 = gen_lowpart (recog_data.operand_mode[1], 1120 recog_data.operand[0]); 1121 rtx newinsn 1122 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn); 1123 1124 /* If this insn was the start of a basic block, 1125 include the new insn in that block. 1126 We need not check for code_label here; 1127 while a basic block can start with a code_label, 1128 INSN could not be at the beginning of that block. */ 1129 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) 1130 { 1131 int b; 1132 for (b = 0; b < n_basic_blocks; b++) 1133 if (insn == BLOCK_HEAD (b)) 1134 BLOCK_HEAD (b) = newinsn; 1135 } 1136 1137 /* This makes one more setting of new insns's dest. */ 1138 REG_N_SETS (REGNO (recog_data.operand[0]))++; 1139 REG_N_REFS (REGNO (recog_data.operand[0]))++; 1140 REG_FREQ (REGNO (recog_data.operand[0])) += frequency; 1141 1142 *recog_data.operand_loc[1] = recog_data.operand[0]; 1143 REG_N_REFS (REGNO (recog_data.operand[0]))++; 1144 REG_FREQ (REGNO (recog_data.operand[0])) += frequency; 1145 for (i = recog_data.n_dups - 1; i >= 0; i--) 1146 if (recog_data.dup_num[i] == 1) 1147 { 1148 *recog_data.dup_loc[i] = recog_data.operand[0]; 1149 REG_N_REFS (REGNO (recog_data.operand[0]))++; 1150 REG_FREQ (REGNO (recog_data.operand[0])) += frequency; 1151 } 1152 1153 return PREV_INSN (newinsn); 1154 } 1155 1156 record_operand_costs (insn, op_costs, reg_pref); 1157 1158 /* Now add the cost for each operand to the total costs for 1159 its register. */ 1160 1161 for (i = 0; i < recog_data.n_operands; i++) 1162 if (GET_CODE (recog_data.operand[i]) == REG 1163 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) 1164 { 1165 int regno = REGNO (recog_data.operand[i]); 1166 struct costs *p = &costs[regno], *q = &op_costs[i]; 1167 1168 p->mem_cost += q->mem_cost * frequency; 1169 for (j = 0; j < N_REG_CLASSES; j++) 1170 p->cost[j] += q->cost[j] * frequency; 1171 } 1172 1173 return insn; 1174} 1175 1176/* This is a pass of the compiler that scans all instructions 1177 and calculates the preferred class for each pseudo-register. 1178 This information can be accessed later by calling `reg_preferred_class'. 1179 This pass comes just before local register allocation. */ 1180 1181void 1182regclass (f, nregs, dump) 1183 rtx f; 1184 int nregs; 1185 FILE *dump; 1186{ 1187 rtx insn; 1188 int i; 1189 int pass; 1190 1191 init_recog (); 1192 1193 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs)); 1194 1195#ifdef CLASS_CANNOT_CHANGE_MODE 1196 reg_changes_mode = BITMAP_XMALLOC (); 1197#endif 1198 1199#ifdef FORBIDDEN_INC_DEC_CLASSES 1200 1201 in_inc_dec = (char *) xmalloc (nregs); 1202 1203 /* Initialize information about which register classes can be used for 1204 pseudos that are auto-incremented or auto-decremented. It would 1205 seem better to put this in init_reg_sets, but we need to be able 1206 to allocate rtx, which we can't do that early. */ 1207 1208 for (i = 0; i < N_REG_CLASSES; i++) 1209 { 1210 rtx r = gen_rtx_REG (VOIDmode, 0); 1211 enum machine_mode m; 1212 int j; 1213 1214 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 1215 if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 1216 { 1217 REGNO (r) = j; 1218 1219 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; 1220 m = (enum machine_mode) ((int) m + 1)) 1221 if (HARD_REGNO_MODE_OK (j, m)) 1222 { 1223 PUT_MODE (r, m); 1224 1225 /* If a register is not directly suitable for an 1226 auto-increment or decrement addressing mode and 1227 requires secondary reloads, disallow its class from 1228 being used in such addresses. */ 1229 1230 if ((0 1231#ifdef SECONDARY_RELOAD_CLASS 1232 || (SECONDARY_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) 1233 != NO_REGS) 1234#else 1235#ifdef SECONDARY_INPUT_RELOAD_CLASS 1236 || (SECONDARY_INPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) 1237 != NO_REGS) 1238#endif 1239#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1240 || (SECONDARY_OUTPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) 1241 != NO_REGS) 1242#endif 1243#endif 1244 ) 1245 && ! auto_inc_dec_reg_p (r, m)) 1246 forbidden_inc_dec_class[i] = 1; 1247 } 1248 } 1249 } 1250#endif /* FORBIDDEN_INC_DEC_CLASSES */ 1251 1252 /* Normally we scan the insns once and determine the best class to use for 1253 each register. However, if -fexpensive_optimizations are on, we do so 1254 twice, the second time using the tentative best classes to guide the 1255 selection. */ 1256 1257 for (pass = 0; pass <= flag_expensive_optimizations; pass++) 1258 { 1259 int index; 1260 1261 if (dump) 1262 fprintf (dump, "\n\nPass %i\n\n",pass); 1263 /* Zero out our accumulation of the cost of each class for each reg. */ 1264 1265 memset ((char *) costs, 0, nregs * sizeof (struct costs)); 1266 1267#ifdef FORBIDDEN_INC_DEC_CLASSES 1268 memset (in_inc_dec, 0, nregs); 1269#endif 1270 1271 /* Scan the instructions and record each time it would 1272 save code to put a certain register in a certain class. */ 1273 1274 if (!optimize) 1275 { 1276 frequency = REG_FREQ_MAX; 1277 for (insn = f; insn; insn = NEXT_INSN (insn)) 1278 insn = scan_one_insn (insn, pass); 1279 } 1280 else 1281 for (index = 0; index < n_basic_blocks; index++) 1282 { 1283 basic_block bb = BASIC_BLOCK (index); 1284 1285 /* Show that an insn inside a loop is likely to be executed three 1286 times more than insns outside a loop. This is much more 1287 aggressive than the assumptions made elsewhere and is being 1288 tried as an experiment. */ 1289 frequency = REG_FREQ_FROM_BB (bb); 1290 for (insn = bb->head; ; insn = NEXT_INSN (insn)) 1291 { 1292 insn = scan_one_insn (insn, pass); 1293 if (insn == bb->end) 1294 break; 1295 } 1296 } 1297 1298 /* Now for each register look at how desirable each class is 1299 and find which class is preferred. Store that in 1300 `prefclass'. Record in `altclass' the largest register 1301 class any of whose registers is better than memory. */ 1302 1303 if (pass == 0) 1304 reg_pref = reg_pref_buffer; 1305 1306 if (dump) 1307 { 1308 dump_regclass (dump); 1309 fprintf (dump,"\n"); 1310 } 1311 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) 1312 { 1313 int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; 1314 enum reg_class best = ALL_REGS, alt = NO_REGS; 1315 /* This is an enum reg_class, but we call it an int 1316 to save lots of casts. */ 1317 int class; 1318 struct costs *p = &costs[i]; 1319 1320 /* In non-optimizing compilation REG_N_REFS is not initialized 1321 yet. */ 1322 if (optimize && !REG_N_REFS (i)) 1323 continue; 1324 1325 for (class = (int) ALL_REGS - 1; class > 0; class--) 1326 { 1327 /* Ignore classes that are too small for this operand or 1328 invalid for an operand that was auto-incremented. */ 1329 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)] 1330#ifdef FORBIDDEN_INC_DEC_CLASSES 1331 || (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1332#endif 1333#ifdef CLASS_CANNOT_CHANGE_MODE 1334 || (REGNO_REG_SET_P (reg_changes_mode, i) 1335 && ! class_can_change_mode [class]) 1336#endif 1337 ) 1338 ; 1339 else if (p->cost[class] < best_cost) 1340 { 1341 best_cost = p->cost[class]; 1342 best = (enum reg_class) class; 1343 } 1344 else if (p->cost[class] == best_cost) 1345 best = reg_class_subunion[(int) best][class]; 1346 } 1347 1348 /* Record the alternate register class; i.e., a class for which 1349 every register in it is better than using memory. If adding a 1350 class would make a smaller class (i.e., no union of just those 1351 classes exists), skip that class. The major unions of classes 1352 should be provided as a register class. Don't do this if we 1353 will be doing it again later. */ 1354 1355 if ((pass == 1 || dump) || ! flag_expensive_optimizations) 1356 for (class = 0; class < N_REG_CLASSES; class++) 1357 if (p->cost[class] < p->mem_cost 1358 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] 1359 > reg_class_size[(int) alt]) 1360#ifdef FORBIDDEN_INC_DEC_CLASSES 1361 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1362#endif 1363#ifdef CLASS_CANNOT_CHANGE_MODE 1364 && ! (REGNO_REG_SET_P (reg_changes_mode, i) 1365 && ! class_can_change_mode [class]) 1366#endif 1367 ) 1368 alt = reg_class_subunion[(int) alt][class]; 1369 1370 /* If we don't add any classes, nothing to try. */ 1371 if (alt == best) 1372 alt = NO_REGS; 1373 1374 if (dump 1375 && (reg_pref[i].prefclass != (int) best 1376 || reg_pref[i].altclass != (int) alt)) 1377 { 1378 static const char *const reg_class_names[] = REG_CLASS_NAMES; 1379 fprintf (dump, " Register %i", i); 1380 if (alt == ALL_REGS || best == ALL_REGS) 1381 fprintf (dump, " pref %s\n", reg_class_names[(int) best]); 1382 else if (alt == NO_REGS) 1383 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]); 1384 else 1385 fprintf (dump, " pref %s, else %s\n", 1386 reg_class_names[(int) best], 1387 reg_class_names[(int) alt]); 1388 } 1389 1390 /* We cast to (int) because (char) hits bugs in some compilers. */ 1391 reg_pref[i].prefclass = (int) best; 1392 reg_pref[i].altclass = (int) alt; 1393 } 1394 } 1395 1396#ifdef FORBIDDEN_INC_DEC_CLASSES 1397 free (in_inc_dec); 1398#endif 1399#ifdef CLASS_CANNOT_CHANGE_MODE 1400 BITMAP_XFREE (reg_changes_mode); 1401#endif 1402 free (costs); 1403} 1404 1405/* Record the cost of using memory or registers of various classes for 1406 the operands in INSN. 1407 1408 N_ALTS is the number of alternatives. 1409 1410 N_OPS is the number of operands. 1411 1412 OPS is an array of the operands. 1413 1414 MODES are the modes of the operands, in case any are VOIDmode. 1415 1416 CONSTRAINTS are the constraints to use for the operands. This array 1417 is modified by this procedure. 1418 1419 This procedure works alternative by alternative. For each alternative 1420 we assume that we will be able to allocate all pseudos to their ideal 1421 register class and calculate the cost of using that alternative. Then 1422 we compute for each operand that is a pseudo-register, the cost of 1423 having the pseudo allocated to each register class and using it in that 1424 alternative. To this cost is added the cost of the alternative. 1425 1426 The cost of each class for this insn is its lowest cost among all the 1427 alternatives. */ 1428 1429static void 1430record_reg_classes (n_alts, n_ops, ops, modes, 1431 constraints, insn, op_costs, reg_pref) 1432 int n_alts; 1433 int n_ops; 1434 rtx *ops; 1435 enum machine_mode *modes; 1436 const char **constraints; 1437 rtx insn; 1438 struct costs *op_costs; 1439 struct reg_pref *reg_pref; 1440{ 1441 int alt; 1442 int i, j; 1443 rtx set; 1444 1445 /* Process each alternative, each time minimizing an operand's cost with 1446 the cost for each operand in that alternative. */ 1447 1448 for (alt = 0; alt < n_alts; alt++) 1449 { 1450 struct costs this_op_costs[MAX_RECOG_OPERANDS]; 1451 int alt_fail = 0; 1452 int alt_cost = 0; 1453 enum reg_class classes[MAX_RECOG_OPERANDS]; 1454 int allows_mem[MAX_RECOG_OPERANDS]; 1455 int class; 1456 1457 for (i = 0; i < n_ops; i++) 1458 { 1459 const char *p = constraints[i]; 1460 rtx op = ops[i]; 1461 enum machine_mode mode = modes[i]; 1462 int allows_addr = 0; 1463 int win = 0; 1464 unsigned char c; 1465 1466 /* Initially show we know nothing about the register class. */ 1467 classes[i] = NO_REGS; 1468 allows_mem[i] = 0; 1469 1470 /* If this operand has no constraints at all, we can conclude 1471 nothing about it since anything is valid. */ 1472 1473 if (*p == 0) 1474 { 1475 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1476 memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]); 1477 1478 continue; 1479 } 1480 1481 /* If this alternative is only relevant when this operand 1482 matches a previous operand, we do different things depending 1483 on whether this operand is a pseudo-reg or not. We must process 1484 any modifiers for the operand before we can make this test. */ 1485 1486 while (*p == '%' || *p == '=' || *p == '+' || *p == '&') 1487 p++; 1488 1489 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) 1490 { 1491 /* Copy class and whether memory is allowed from the matching 1492 alternative. Then perform any needed cost computations 1493 and/or adjustments. */ 1494 j = p[0] - '0'; 1495 classes[i] = classes[j]; 1496 allows_mem[i] = allows_mem[j]; 1497 1498 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) 1499 { 1500 /* If this matches the other operand, we have no added 1501 cost and we win. */ 1502 if (rtx_equal_p (ops[j], op)) 1503 win = 1; 1504 1505 /* If we can put the other operand into a register, add to 1506 the cost of this alternative the cost to copy this 1507 operand to the register used for the other operand. */ 1508 1509 else if (classes[j] != NO_REGS) 1510 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; 1511 } 1512 else if (GET_CODE (ops[j]) != REG 1513 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) 1514 { 1515 /* This op is a pseudo but the one it matches is not. */ 1516 1517 /* If we can't put the other operand into a register, this 1518 alternative can't be used. */ 1519 1520 if (classes[j] == NO_REGS) 1521 alt_fail = 1; 1522 1523 /* Otherwise, add to the cost of this alternative the cost 1524 to copy the other operand to the register used for this 1525 operand. */ 1526 1527 else 1528 alt_cost += copy_cost (ops[j], mode, classes[j], 1); 1529 } 1530 else 1531 { 1532 /* The costs of this operand are not the same as the other 1533 operand since move costs are not symmetric. Moreover, 1534 if we cannot tie them, this alternative needs to do a 1535 copy, which is one instruction. */ 1536 1537 struct costs *pp = &this_op_costs[i]; 1538 1539 for (class = 0; class < N_REG_CLASSES; class++) 1540 pp->cost[class] 1541 = ((recog_data.operand_type[i] != OP_OUT 1542 ? may_move_in_cost[mode][class][(int) classes[i]] 1543 : 0) 1544 + (recog_data.operand_type[i] != OP_IN 1545 ? may_move_out_cost[mode][(int) classes[i]][class] 1546 : 0)); 1547 1548 /* If the alternative actually allows memory, make things 1549 a bit cheaper since we won't need an extra insn to 1550 load it. */ 1551 1552 pp->mem_cost 1553 = ((recog_data.operand_type[i] != OP_IN 1554 ? MEMORY_MOVE_COST (mode, classes[i], 0) 1555 : 0) 1556 + (recog_data.operand_type[i] != OP_OUT 1557 ? MEMORY_MOVE_COST (mode, classes[i], 1) 1558 : 0) - allows_mem[i]); 1559 1560 /* If we have assigned a class to this register in our 1561 first pass, add a cost to this alternative corresponding 1562 to what we would add if this register were not in the 1563 appropriate class. */ 1564 1565 if (reg_pref) 1566 alt_cost 1567 += (may_move_in_cost[mode] 1568 [(unsigned char) reg_pref[REGNO (op)].prefclass] 1569 [(int) classes[i]]); 1570 1571 if (REGNO (ops[i]) != REGNO (ops[j]) 1572 && ! find_reg_note (insn, REG_DEAD, op)) 1573 alt_cost += 2; 1574 1575 /* This is in place of ordinary cost computation 1576 for this operand, so skip to the end of the 1577 alternative (should be just one character). */ 1578 while (*p && *p++ != ',') 1579 ; 1580 1581 constraints[i] = p; 1582 continue; 1583 } 1584 } 1585 1586 /* Scan all the constraint letters. See if the operand matches 1587 any of the constraints. Collect the valid register classes 1588 and see if this operand accepts memory. */ 1589 1590 while (*p && (c = *p++) != ',') 1591 switch (c) 1592 { 1593 case '*': 1594 /* Ignore the next letter for this pass. */ 1595 p++; 1596 break; 1597 1598 case '?': 1599 alt_cost += 2; 1600 case '!': case '#': case '&': 1601 case '0': case '1': case '2': case '3': case '4': 1602 case '5': case '6': case '7': case '8': case '9': 1603 break; 1604 1605 case 'p': 1606 allows_addr = 1; 1607 win = address_operand (op, GET_MODE (op)); 1608 /* We know this operand is an address, so we want it to be 1609 allocated to a register that can be the base of an 1610 address, ie BASE_REG_CLASS. */ 1611 classes[i] 1612 = reg_class_subunion[(int) classes[i]] 1613 [(int) MODE_BASE_REG_CLASS (VOIDmode)]; 1614 break; 1615 1616 case 'm': case 'o': case 'V': 1617 /* It doesn't seem worth distinguishing between offsettable 1618 and non-offsettable addresses here. */ 1619 allows_mem[i] = 1; 1620 if (GET_CODE (op) == MEM) 1621 win = 1; 1622 break; 1623 1624 case '<': 1625 if (GET_CODE (op) == MEM 1626 && (GET_CODE (XEXP (op, 0)) == PRE_DEC 1627 || GET_CODE (XEXP (op, 0)) == POST_DEC)) 1628 win = 1; 1629 break; 1630 1631 case '>': 1632 if (GET_CODE (op) == MEM 1633 && (GET_CODE (XEXP (op, 0)) == PRE_INC 1634 || GET_CODE (XEXP (op, 0)) == POST_INC)) 1635 win = 1; 1636 break; 1637 1638 case 'E': 1639#ifndef REAL_ARITHMETIC 1640 /* Match any floating double constant, but only if 1641 we can examine the bits of it reliably. */ 1642 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT 1643 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) 1644 && GET_MODE (op) != VOIDmode && ! flag_pretend_float) 1645 break; 1646#endif 1647 if (GET_CODE (op) == CONST_DOUBLE) 1648 win = 1; 1649 break; 1650 1651 case 'F': 1652 if (GET_CODE (op) == CONST_DOUBLE) 1653 win = 1; 1654 break; 1655 1656 case 'G': 1657 case 'H': 1658 if (GET_CODE (op) == CONST_DOUBLE 1659 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) 1660 win = 1; 1661 break; 1662 1663 case 's': 1664 if (GET_CODE (op) == CONST_INT 1665 || (GET_CODE (op) == CONST_DOUBLE 1666 && GET_MODE (op) == VOIDmode)) 1667 break; 1668 case 'i': 1669 if (CONSTANT_P (op) 1670#ifdef LEGITIMATE_PIC_OPERAND_P 1671 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1672#endif 1673 ) 1674 win = 1; 1675 break; 1676 1677 case 'n': 1678 if (GET_CODE (op) == CONST_INT 1679 || (GET_CODE (op) == CONST_DOUBLE 1680 && GET_MODE (op) == VOIDmode)) 1681 win = 1; 1682 break; 1683 1684 case 'I': 1685 case 'J': 1686 case 'K': 1687 case 'L': 1688 case 'M': 1689 case 'N': 1690 case 'O': 1691 case 'P': 1692 if (GET_CODE (op) == CONST_INT 1693 && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) 1694 win = 1; 1695 break; 1696 1697 case 'X': 1698 win = 1; 1699 break; 1700 1701 case 'g': 1702 if (GET_CODE (op) == MEM 1703 || (CONSTANT_P (op) 1704#ifdef LEGITIMATE_PIC_OPERAND_P 1705 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1706#endif 1707 )) 1708 win = 1; 1709 allows_mem[i] = 1; 1710 case 'r': 1711 classes[i] 1712 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; 1713 break; 1714 1715 default: 1716 if (REG_CLASS_FROM_LETTER (c) != NO_REGS) 1717 classes[i] 1718 = reg_class_subunion[(int) classes[i]] 1719 [(int) REG_CLASS_FROM_LETTER (c)]; 1720#ifdef EXTRA_CONSTRAINT 1721 else if (EXTRA_CONSTRAINT (op, c)) 1722 win = 1; 1723#endif 1724 break; 1725 } 1726 1727 constraints[i] = p; 1728 1729 /* How we account for this operand now depends on whether it is a 1730 pseudo register or not. If it is, we first check if any 1731 register classes are valid. If not, we ignore this alternative, 1732 since we want to assume that all pseudos get allocated for 1733 register preferencing. If some register class is valid, compute 1734 the costs of moving the pseudo into that class. */ 1735 1736 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1737 { 1738 if (classes[i] == NO_REGS) 1739 { 1740 /* We must always fail if the operand is a REG, but 1741 we did not find a suitable class. 1742 1743 Otherwise we may perform an uninitialized read 1744 from this_op_costs after the `continue' statement 1745 below. */ 1746 alt_fail = 1; 1747 } 1748 else 1749 { 1750 struct costs *pp = &this_op_costs[i]; 1751 1752 for (class = 0; class < N_REG_CLASSES; class++) 1753 pp->cost[class] 1754 = ((recog_data.operand_type[i] != OP_OUT 1755 ? may_move_in_cost[mode][class][(int) classes[i]] 1756 : 0) 1757 + (recog_data.operand_type[i] != OP_IN 1758 ? may_move_out_cost[mode][(int) classes[i]][class] 1759 : 0)); 1760 1761 /* If the alternative actually allows memory, make things 1762 a bit cheaper since we won't need an extra insn to 1763 load it. */ 1764 1765 pp->mem_cost 1766 = ((recog_data.operand_type[i] != OP_IN 1767 ? MEMORY_MOVE_COST (mode, classes[i], 0) 1768 : 0) 1769 + (recog_data.operand_type[i] != OP_OUT 1770 ? MEMORY_MOVE_COST (mode, classes[i], 1) 1771 : 0) - allows_mem[i]); 1772 1773 /* If we have assigned a class to this register in our 1774 first pass, add a cost to this alternative corresponding 1775 to what we would add if this register were not in the 1776 appropriate class. */ 1777 1778 if (reg_pref) 1779 alt_cost 1780 += (may_move_in_cost[mode] 1781 [(unsigned char) reg_pref[REGNO (op)].prefclass] 1782 [(int) classes[i]]); 1783 } 1784 } 1785 1786 /* Otherwise, if this alternative wins, either because we 1787 have already determined that or if we have a hard register of 1788 the proper class, there is no cost for this alternative. */ 1789 1790 else if (win 1791 || (GET_CODE (op) == REG 1792 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) 1793 ; 1794 1795 /* If registers are valid, the cost of this alternative includes 1796 copying the object to and/or from a register. */ 1797 1798 else if (classes[i] != NO_REGS) 1799 { 1800 if (recog_data.operand_type[i] != OP_OUT) 1801 alt_cost += copy_cost (op, mode, classes[i], 1); 1802 1803 if (recog_data.operand_type[i] != OP_IN) 1804 alt_cost += copy_cost (op, mode, classes[i], 0); 1805 } 1806 1807 /* The only other way this alternative can be used is if this is a 1808 constant that could be placed into memory. */ 1809 1810 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) 1811 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); 1812 else 1813 alt_fail = 1; 1814 } 1815 1816 if (alt_fail) 1817 continue; 1818 1819 /* Finally, update the costs with the information we've calculated 1820 about this alternative. */ 1821 1822 for (i = 0; i < n_ops; i++) 1823 if (GET_CODE (ops[i]) == REG 1824 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1825 { 1826 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; 1827 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); 1828 1829 pp->mem_cost = MIN (pp->mem_cost, 1830 (qq->mem_cost + alt_cost) * scale); 1831 1832 for (class = 0; class < N_REG_CLASSES; class++) 1833 pp->cost[class] = MIN (pp->cost[class], 1834 (qq->cost[class] + alt_cost) * scale); 1835 } 1836 } 1837 1838 /* If this insn is a single set copying operand 1 to operand 0 1839 and one operand is a pseudo with the other a hard reg or a pseudo 1840 that prefers a register that is in its own register class then 1841 we may want to adjust the cost of that register class to -1. 1842 1843 Avoid the adjustment if the source does not die to avoid stressing of 1844 register allocator by preferrencing two coliding registers into single 1845 class. 1846 1847 Also avoid the adjustment if a copy between registers of the class 1848 is expensive (ten times the cost of a default copy is considered 1849 arbitrarily expensive). This avoids losing when the preferred class 1850 is very expensive as the source of a copy instruction. */ 1851 1852 if ((set = single_set (insn)) != 0 1853 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) 1854 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG 1855 && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) 1856 for (i = 0; i <= 1; i++) 1857 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1858 { 1859 unsigned int regno = REGNO (ops[!i]); 1860 enum machine_mode mode = GET_MODE (ops[!i]); 1861 int class; 1862 unsigned int nr; 1863 1864 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0) 1865 { 1866 enum reg_class pref = reg_pref[regno].prefclass; 1867 1868 if ((reg_class_size[(unsigned char) pref] 1869 == CLASS_MAX_NREGS (pref, mode)) 1870 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2) 1871 op_costs[i].cost[(unsigned char) pref] = -1; 1872 } 1873 else if (regno < FIRST_PSEUDO_REGISTER) 1874 for (class = 0; class < N_REG_CLASSES; class++) 1875 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) 1876 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) 1877 { 1878 if (reg_class_size[class] == 1) 1879 op_costs[i].cost[class] = -1; 1880 else 1881 { 1882 for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++) 1883 { 1884 if (! TEST_HARD_REG_BIT (reg_class_contents[class], 1885 regno + nr)) 1886 break; 1887 } 1888 1889 if (nr == HARD_REGNO_NREGS (regno,mode)) 1890 op_costs[i].cost[class] = -1; 1891 } 1892 } 1893 } 1894} 1895 1896/* Compute the cost of loading X into (if TO_P is non-zero) or from (if 1897 TO_P is zero) a register of class CLASS in mode MODE. 1898 1899 X must not be a pseudo. */ 1900 1901static int 1902copy_cost (x, mode, class, to_p) 1903 rtx x; 1904 enum machine_mode mode ATTRIBUTE_UNUSED; 1905 enum reg_class class; 1906 int to_p ATTRIBUTE_UNUSED; 1907{ 1908#ifdef HAVE_SECONDARY_RELOADS 1909 enum reg_class secondary_class = NO_REGS; 1910#endif 1911 1912 /* If X is a SCRATCH, there is actually nothing to move since we are 1913 assuming optimal allocation. */ 1914 1915 if (GET_CODE (x) == SCRATCH) 1916 return 0; 1917 1918 /* Get the class we will actually use for a reload. */ 1919 class = PREFERRED_RELOAD_CLASS (x, class); 1920 1921#ifdef HAVE_SECONDARY_RELOADS 1922 /* If we need a secondary reload (we assume here that we are using 1923 the secondary reload as an intermediate, not a scratch register), the 1924 cost is that to load the input into the intermediate register, then 1925 to copy them. We use a special value of TO_P to avoid recursion. */ 1926 1927#ifdef SECONDARY_INPUT_RELOAD_CLASS 1928 if (to_p == 1) 1929 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); 1930#endif 1931 1932#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1933 if (! to_p) 1934 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); 1935#endif 1936 1937 if (secondary_class != NO_REGS) 1938 return (move_cost[mode][(int) secondary_class][(int) class] 1939 + copy_cost (x, mode, secondary_class, 2)); 1940#endif /* HAVE_SECONDARY_RELOADS */ 1941 1942 /* For memory, use the memory move cost, for (hard) registers, use the 1943 cost to move between the register classes, and use 2 for everything 1944 else (constants). */ 1945 1946 if (GET_CODE (x) == MEM || class == NO_REGS) 1947 return MEMORY_MOVE_COST (mode, class, to_p); 1948 1949 else if (GET_CODE (x) == REG) 1950 return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; 1951 1952 else 1953 /* If this is a constant, we may eventually want to call rtx_cost here. */ 1954 return COSTS_N_INSNS (1); 1955} 1956 1957/* Record the pseudo registers we must reload into hard registers 1958 in a subexpression of a memory address, X. 1959 1960 CLASS is the class that the register needs to be in and is either 1961 BASE_REG_CLASS or INDEX_REG_CLASS. 1962 1963 SCALE is twice the amount to multiply the cost by (it is twice so we 1964 can represent half-cost adjustments). */ 1965 1966static void 1967record_address_regs (x, class, scale) 1968 rtx x; 1969 enum reg_class class; 1970 int scale; 1971{ 1972 enum rtx_code code = GET_CODE (x); 1973 1974 switch (code) 1975 { 1976 case CONST_INT: 1977 case CONST: 1978 case CC0: 1979 case PC: 1980 case SYMBOL_REF: 1981 case LABEL_REF: 1982 return; 1983 1984 case PLUS: 1985 /* When we have an address that is a sum, 1986 we must determine whether registers are "base" or "index" regs. 1987 If there is a sum of two registers, we must choose one to be 1988 the "base". Luckily, we can use the REG_POINTER to make a good 1989 choice most of the time. We only need to do this on machines 1990 that can have two registers in an address and where the base 1991 and index register classes are different. 1992 1993 ??? This code used to set REGNO_POINTER_FLAG in some cases, but 1994 that seems bogus since it should only be set when we are sure 1995 the register is being used as a pointer. */ 1996 1997 { 1998 rtx arg0 = XEXP (x, 0); 1999 rtx arg1 = XEXP (x, 1); 2000 enum rtx_code code0 = GET_CODE (arg0); 2001 enum rtx_code code1 = GET_CODE (arg1); 2002 2003 /* Look inside subregs. */ 2004 if (code0 == SUBREG) 2005 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); 2006 if (code1 == SUBREG) 2007 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); 2008 2009 /* If this machine only allows one register per address, it must 2010 be in the first operand. */ 2011 2012 if (MAX_REGS_PER_ADDRESS == 1) 2013 record_address_regs (arg0, class, scale); 2014 2015 /* If index and base registers are the same on this machine, just 2016 record registers in any non-constant operands. We assume here, 2017 as well as in the tests below, that all addresses are in 2018 canonical form. */ 2019 2020 else if (INDEX_REG_CLASS == MODE_BASE_REG_CLASS (VOIDmode)) 2021 { 2022 record_address_regs (arg0, class, scale); 2023 if (! CONSTANT_P (arg1)) 2024 record_address_regs (arg1, class, scale); 2025 } 2026 2027 /* If the second operand is a constant integer, it doesn't change 2028 what class the first operand must be. */ 2029 2030 else if (code1 == CONST_INT || code1 == CONST_DOUBLE) 2031 record_address_regs (arg0, class, scale); 2032 2033 /* If the second operand is a symbolic constant, the first operand 2034 must be an index register. */ 2035 2036 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) 2037 record_address_regs (arg0, INDEX_REG_CLASS, scale); 2038 2039 /* If both operands are registers but one is already a hard register 2040 of index or base class, give the other the class that the hard 2041 register is not. */ 2042 2043#ifdef REG_OK_FOR_BASE_P 2044 else if (code0 == REG && code1 == REG 2045 && REGNO (arg0) < FIRST_PSEUDO_REGISTER 2046 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) 2047 record_address_regs (arg1, 2048 REG_OK_FOR_BASE_P (arg0) 2049 ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), 2050 scale); 2051 else if (code0 == REG && code1 == REG 2052 && REGNO (arg1) < FIRST_PSEUDO_REGISTER 2053 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) 2054 record_address_regs (arg0, 2055 REG_OK_FOR_BASE_P (arg1) 2056 ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode), 2057 scale); 2058#endif 2059 2060 /* If one operand is known to be a pointer, it must be the base 2061 with the other operand the index. Likewise if the other operand 2062 is a MULT. */ 2063 2064 else if ((code0 == REG && REG_POINTER (arg0)) 2065 || code1 == MULT) 2066 { 2067 record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), scale); 2068 record_address_regs (arg1, INDEX_REG_CLASS, scale); 2069 } 2070 else if ((code1 == REG && REG_POINTER (arg1)) 2071 || code0 == MULT) 2072 { 2073 record_address_regs (arg0, INDEX_REG_CLASS, scale); 2074 record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), scale); 2075 } 2076 2077 /* Otherwise, count equal chances that each might be a base 2078 or index register. This case should be rare. */ 2079 2080 else 2081 { 2082 record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), 2083 scale / 2); 2084 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); 2085 record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), 2086 scale / 2); 2087 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); 2088 } 2089 } 2090 break; 2091 2092 /* Double the importance of a pseudo register that is incremented 2093 or decremented, since it would take two extra insns 2094 if it ends up in the wrong place. */ 2095 case POST_MODIFY: 2096 case PRE_MODIFY: 2097 record_address_regs (XEXP (x, 0), MODE_BASE_REG_CLASS (VOIDmode), 2098 2 * scale); 2099 if (REG_P (XEXP (XEXP (x, 1), 1))) 2100 record_address_regs (XEXP (XEXP (x, 1), 1), 2101 INDEX_REG_CLASS, 2 * scale); 2102 break; 2103 2104 case POST_INC: 2105 case PRE_INC: 2106 case POST_DEC: 2107 case PRE_DEC: 2108 /* Double the importance of a pseudo register that is incremented 2109 or decremented, since it would take two extra insns 2110 if it ends up in the wrong place. If the operand is a pseudo, 2111 show it is being used in an INC_DEC context. */ 2112 2113#ifdef FORBIDDEN_INC_DEC_CLASSES 2114 if (GET_CODE (XEXP (x, 0)) == REG 2115 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) 2116 in_inc_dec[REGNO (XEXP (x, 0))] = 1; 2117#endif 2118 2119 record_address_regs (XEXP (x, 0), class, 2 * scale); 2120 break; 2121 2122 case REG: 2123 { 2124 struct costs *pp = &costs[REGNO (x)]; 2125 int i; 2126 2127 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; 2128 2129 for (i = 0; i < N_REG_CLASSES; i++) 2130 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2; 2131 } 2132 break; 2133 2134 default: 2135 { 2136 const char *fmt = GET_RTX_FORMAT (code); 2137 int i; 2138 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2139 if (fmt[i] == 'e') 2140 record_address_regs (XEXP (x, i), class, scale); 2141 } 2142 } 2143} 2144 2145#ifdef FORBIDDEN_INC_DEC_CLASSES 2146 2147/* Return 1 if REG is valid as an auto-increment memory reference 2148 to an object of MODE. */ 2149 2150static int 2151auto_inc_dec_reg_p (reg, mode) 2152 rtx reg; 2153 enum machine_mode mode; 2154{ 2155 if (HAVE_POST_INCREMENT 2156 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) 2157 return 1; 2158 2159 if (HAVE_POST_DECREMENT 2160 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) 2161 return 1; 2162 2163 if (HAVE_PRE_INCREMENT 2164 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) 2165 return 1; 2166 2167 if (HAVE_PRE_DECREMENT 2168 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) 2169 return 1; 2170 2171 return 0; 2172} 2173#endif 2174 2175static short *renumber; 2176static size_t regno_allocated; 2177static unsigned int reg_n_max; 2178 2179/* Allocate enough space to hold NUM_REGS registers for the tables used for 2180 reg_scan and flow_analysis that are indexed by the register number. If 2181 NEW_P is non zero, initialize all of the registers, otherwise only 2182 initialize the new registers allocated. The same table is kept from 2183 function to function, only reallocating it when we need more room. If 2184 RENUMBER_P is non zero, allocate the reg_renumber array also. */ 2185 2186void 2187allocate_reg_info (num_regs, new_p, renumber_p) 2188 size_t num_regs; 2189 int new_p; 2190 int renumber_p; 2191{ 2192 size_t size_info; 2193 size_t size_renumber; 2194 size_t min = (new_p) ? 0 : reg_n_max; 2195 struct reg_info_data *reg_data; 2196 2197 if (num_regs > regno_allocated) 2198 { 2199 size_t old_allocated = regno_allocated; 2200 2201 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ 2202 size_renumber = regno_allocated * sizeof (short); 2203 2204 if (!reg_n_info) 2205 { 2206 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); 2207 renumber = (short *) xmalloc (size_renumber); 2208 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated 2209 * sizeof (struct reg_pref)); 2210 } 2211 2212 else 2213 { 2214 VARRAY_GROW (reg_n_info, regno_allocated); 2215 2216 if (new_p) /* if we're zapping everything, no need to realloc */ 2217 { 2218 free ((char *) renumber); 2219 free ((char *) reg_pref); 2220 renumber = (short *) xmalloc (size_renumber); 2221 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated 2222 * sizeof (struct reg_pref)); 2223 } 2224 2225 else 2226 { 2227 renumber = (short *) xrealloc ((char *) renumber, size_renumber); 2228 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *) reg_pref_buffer, 2229 regno_allocated 2230 * sizeof (struct reg_pref)); 2231 } 2232 } 2233 2234 size_info = (regno_allocated - old_allocated) * sizeof (reg_info) 2235 + sizeof (struct reg_info_data) - sizeof (reg_info); 2236 reg_data = (struct reg_info_data *) xcalloc (size_info, 1); 2237 reg_data->min_index = old_allocated; 2238 reg_data->max_index = regno_allocated - 1; 2239 reg_data->next = reg_info_head; 2240 reg_info_head = reg_data; 2241 } 2242 2243 reg_n_max = num_regs; 2244 if (min < num_regs) 2245 { 2246 /* Loop through each of the segments allocated for the actual 2247 reg_info pages, and set up the pointers, zero the pages, etc. */ 2248 for (reg_data = reg_info_head; 2249 reg_data && reg_data->max_index >= min; 2250 reg_data = reg_data->next) 2251 { 2252 size_t min_index = reg_data->min_index; 2253 size_t max_index = reg_data->max_index; 2254 size_t max = MIN (max_index, num_regs); 2255 size_t local_min = min - min_index; 2256 size_t i; 2257 2258 if (reg_data->min_index > num_regs) 2259 continue; 2260 2261 if (min < min_index) 2262 local_min = 0; 2263 if (!reg_data->used_p) /* page just allocated with calloc */ 2264 reg_data->used_p = 1; /* no need to zero */ 2265 else 2266 memset ((char *) ®_data->data[local_min], 0, 2267 sizeof (reg_info) * (max - min_index - local_min + 1)); 2268 2269 for (i = min_index+local_min; i <= max; i++) 2270 { 2271 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; 2272 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; 2273 renumber[i] = -1; 2274 reg_pref_buffer[i].prefclass = (char) NO_REGS; 2275 reg_pref_buffer[i].altclass = (char) NO_REGS; 2276 } 2277 } 2278 } 2279 2280 /* If {pref,alt}class have already been allocated, update the pointers to 2281 the newly realloced ones. */ 2282 if (reg_pref) 2283 reg_pref = reg_pref_buffer; 2284 2285 if (renumber_p) 2286 reg_renumber = renumber; 2287 2288 /* Tell the regset code about the new number of registers */ 2289 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); 2290} 2291 2292/* Free up the space allocated by allocate_reg_info. */ 2293void 2294free_reg_info () 2295{ 2296 if (reg_n_info) 2297 { 2298 struct reg_info_data *reg_data; 2299 struct reg_info_data *reg_next; 2300 2301 VARRAY_FREE (reg_n_info); 2302 for (reg_data = reg_info_head; reg_data; reg_data = reg_next) 2303 { 2304 reg_next = reg_data->next; 2305 free ((char *) reg_data); 2306 } 2307 2308 free (reg_pref_buffer); 2309 reg_pref_buffer = (struct reg_pref *) 0; 2310 reg_info_head = (struct reg_info_data *) 0; 2311 renumber = (short *) 0; 2312 } 2313 regno_allocated = 0; 2314 reg_n_max = 0; 2315} 2316 2317/* This is the `regscan' pass of the compiler, run just before cse 2318 and again just before loop. 2319 2320 It finds the first and last use of each pseudo-register 2321 and records them in the vectors regno_first_uid, regno_last_uid 2322 and counts the number of sets in the vector reg_n_sets. 2323 2324 REPEAT is nonzero the second time this is called. */ 2325 2326/* Maximum number of parallel sets and clobbers in any insn in this fn. 2327 Always at least 3, since the combiner could put that many together 2328 and we want this to remain correct for all the remaining passes. 2329 This corresponds to the maximum number of times note_stores will call 2330 a function for any insn. */ 2331 2332int max_parallel; 2333 2334/* Used as a temporary to record the largest number of registers in 2335 PARALLEL in a SET_DEST. This is added to max_parallel. */ 2336 2337static int max_set_parallel; 2338 2339void 2340reg_scan (f, nregs, repeat) 2341 rtx f; 2342 unsigned int nregs; 2343 int repeat ATTRIBUTE_UNUSED; 2344{ 2345 rtx insn; 2346 2347 allocate_reg_info (nregs, TRUE, FALSE); 2348 max_parallel = 3; 2349 max_set_parallel = 0; 2350 2351 for (insn = f; insn; insn = NEXT_INSN (insn)) 2352 if (GET_CODE (insn) == INSN 2353 || GET_CODE (insn) == CALL_INSN 2354 || GET_CODE (insn) == JUMP_INSN) 2355 { 2356 if (GET_CODE (PATTERN (insn)) == PARALLEL 2357 && XVECLEN (PATTERN (insn), 0) > max_parallel) 2358 max_parallel = XVECLEN (PATTERN (insn), 0); 2359 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0); 2360 2361 if (REG_NOTES (insn)) 2362 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); 2363 } 2364 2365 max_parallel += max_set_parallel; 2366} 2367 2368/* Update 'regscan' information by looking at the insns 2369 from FIRST to LAST. Some new REGs have been created, 2370 and any REG with number greater than OLD_MAX_REGNO is 2371 such a REG. We only update information for those. */ 2372 2373void 2374reg_scan_update (first, last, old_max_regno) 2375 rtx first; 2376 rtx last; 2377 unsigned int old_max_regno; 2378{ 2379 rtx insn; 2380 2381 allocate_reg_info (max_reg_num (), FALSE, FALSE); 2382 2383 for (insn = first; insn != last; insn = NEXT_INSN (insn)) 2384 if (GET_CODE (insn) == INSN 2385 || GET_CODE (insn) == CALL_INSN 2386 || GET_CODE (insn) == JUMP_INSN) 2387 { 2388 if (GET_CODE (PATTERN (insn)) == PARALLEL 2389 && XVECLEN (PATTERN (insn), 0) > max_parallel) 2390 max_parallel = XVECLEN (PATTERN (insn), 0); 2391 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno); 2392 2393 if (REG_NOTES (insn)) 2394 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); 2395 } 2396} 2397 2398/* X is the expression to scan. INSN is the insn it appears in. 2399 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. 2400 We should only record information for REGs with numbers 2401 greater than or equal to MIN_REGNO. */ 2402 2403static void 2404reg_scan_mark_refs (x, insn, note_flag, min_regno) 2405 rtx x; 2406 rtx insn; 2407 int note_flag; 2408 unsigned int min_regno; 2409{ 2410 enum rtx_code code; 2411 rtx dest; 2412 rtx note; 2413 2414 code = GET_CODE (x); 2415 switch (code) 2416 { 2417 case CONST: 2418 case CONST_INT: 2419 case CONST_DOUBLE: 2420 case CONST_VECTOR: 2421 case CC0: 2422 case PC: 2423 case SYMBOL_REF: 2424 case LABEL_REF: 2425 case ADDR_VEC: 2426 case ADDR_DIFF_VEC: 2427 return; 2428 2429 case REG: 2430 { 2431 unsigned int regno = REGNO (x); 2432 2433 if (regno >= min_regno) 2434 { 2435 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); 2436 if (!note_flag) 2437 REGNO_LAST_UID (regno) = INSN_UID (insn); 2438 if (REGNO_FIRST_UID (regno) == 0) 2439 REGNO_FIRST_UID (regno) = INSN_UID (insn); 2440 } 2441 } 2442 break; 2443 2444 case EXPR_LIST: 2445 if (XEXP (x, 0)) 2446 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); 2447 if (XEXP (x, 1)) 2448 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); 2449 break; 2450 2451 case INSN_LIST: 2452 if (XEXP (x, 1)) 2453 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); 2454 break; 2455 2456 case SET: 2457 /* Count a set of the destination if it is a register. */ 2458 for (dest = SET_DEST (x); 2459 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART 2460 || GET_CODE (dest) == ZERO_EXTEND; 2461 dest = XEXP (dest, 0)) 2462 ; 2463 2464 /* For a PARALLEL, record the number of things (less the usual one for a 2465 SET) that are set. */ 2466 if (GET_CODE (dest) == PARALLEL) 2467 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1); 2468 2469 if (GET_CODE (dest) == REG 2470 && REGNO (dest) >= min_regno) 2471 { 2472 REG_N_SETS (REGNO (dest))++; 2473 REG_N_REFS (REGNO (dest))++; 2474 } 2475 2476 /* If this is setting a pseudo from another pseudo or the sum of a 2477 pseudo and a constant integer and the other pseudo is known to be 2478 a pointer, set the destination to be a pointer as well. 2479 2480 Likewise if it is setting the destination from an address or from a 2481 value equivalent to an address or to the sum of an address and 2482 something else. 2483 2484 But don't do any of this if the pseudo corresponds to a user 2485 variable since it should have already been set as a pointer based 2486 on the type. */ 2487 2488 if (GET_CODE (SET_DEST (x)) == REG 2489 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER 2490 && REGNO (SET_DEST (x)) >= min_regno 2491 /* If the destination pseudo is set more than once, then other 2492 sets might not be to a pointer value (consider access to a 2493 union in two threads of control in the presense of global 2494 optimizations). So only set REG_POINTER on the destination 2495 pseudo if this is the only set of that pseudo. */ 2496 && REG_N_SETS (REGNO (SET_DEST (x))) == 1 2497 && ! REG_USERVAR_P (SET_DEST (x)) 2498 && ! REG_POINTER (SET_DEST (x)) 2499 && ((GET_CODE (SET_SRC (x)) == REG 2500 && REG_POINTER (SET_SRC (x))) 2501 || ((GET_CODE (SET_SRC (x)) == PLUS 2502 || GET_CODE (SET_SRC (x)) == LO_SUM) 2503 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 2504 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG 2505 && REG_POINTER (XEXP (SET_SRC (x), 0))) 2506 || GET_CODE (SET_SRC (x)) == CONST 2507 || GET_CODE (SET_SRC (x)) == SYMBOL_REF 2508 || GET_CODE (SET_SRC (x)) == LABEL_REF 2509 || (GET_CODE (SET_SRC (x)) == HIGH 2510 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST 2511 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF 2512 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) 2513 || ((GET_CODE (SET_SRC (x)) == PLUS 2514 || GET_CODE (SET_SRC (x)) == LO_SUM) 2515 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST 2516 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF 2517 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) 2518 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 2519 && (GET_CODE (XEXP (note, 0)) == CONST 2520 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF 2521 || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) 2522 REG_POINTER (SET_DEST (x)) = 1; 2523 2524 /* If this is setting a register from a register or from a simple 2525 conversion of a register, propagate REG_DECL. */ 2526 if (GET_CODE (dest) == REG) 2527 { 2528 rtx src = SET_SRC (x); 2529 2530 while (GET_CODE (src) == SIGN_EXTEND 2531 || GET_CODE (src) == ZERO_EXTEND 2532 || GET_CODE (src) == TRUNCATE 2533 || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src))) 2534 src = XEXP (src, 0); 2535 2536 if (GET_CODE (src) == REG && REGNO_DECL (REGNO (src)) == 0) 2537 REGNO_DECL (REGNO (src)) = REGNO_DECL (REGNO (dest)); 2538 else if (GET_CODE (src) == REG && REGNO_DECL (REGNO (dest)) == 0) 2539 REGNO_DECL (REGNO (dest)) = REGNO_DECL (REGNO (src)); 2540 } 2541 2542 /* ... fall through ... */ 2543 2544 default: 2545 { 2546 const char *fmt = GET_RTX_FORMAT (code); 2547 int i; 2548 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2549 { 2550 if (fmt[i] == 'e') 2551 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); 2552 else if (fmt[i] == 'E' && XVEC (x, i) != 0) 2553 { 2554 int j; 2555 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 2556 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); 2557 } 2558 } 2559 } 2560 } 2561} 2562 2563/* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 2564 is also in C2. */ 2565 2566int 2567reg_class_subset_p (c1, c2) 2568 enum reg_class c1; 2569 enum reg_class c2; 2570{ 2571 if (c1 == c2) return 1; 2572 2573 if (c2 == ALL_REGS) 2574 win: 2575 return 1; 2576 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) c1], 2577 reg_class_contents[(int) c2], 2578 win); 2579 return 0; 2580} 2581 2582/* Return nonzero if there is a register that is in both C1 and C2. */ 2583 2584int 2585reg_classes_intersect_p (c1, c2) 2586 enum reg_class c1; 2587 enum reg_class c2; 2588{ 2589#ifdef HARD_REG_SET 2590 register 2591#endif 2592 HARD_REG_SET c; 2593 2594 if (c1 == c2) return 1; 2595 2596 if (c1 == ALL_REGS || c2 == ALL_REGS) 2597 return 1; 2598 2599 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); 2600 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); 2601 2602 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); 2603 return 1; 2604 2605 lose: 2606 return 0; 2607} 2608 2609/* Release any memory allocated by register sets. */ 2610 2611void 2612regset_release_memory () 2613{ 2614 bitmap_release_memory (); 2615} 2616